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2024
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Invention
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Quad-data-rate (qdr) host interface in a memory system.
Technologies for converting quad data ra... |
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Invention
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Memory-integrated neural network.
An integrated-circuit neural network includes chain of multipl... |
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Invention
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Clock buffer.
A phase-locked loop or delay locked loop provides a coarse alignment between an in... |
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Invention
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Method and apparatus for calibrating write timing in a memory system.
A system that calibrates t... |
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Invention
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Multi-processor device with external interface failover.
A multi-processor device is disclosed. ... |
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Invention
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Folded memory modules.
A memory module comprises a data interface including a plurality of data ... |
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Invention
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Memory bandwidth aggregation using simultaneous access of stacked semiconductor memory die.
A pa... |
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Invention
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Power management integrated circuit device having multiple initialization/power up modes.
Disclo... |
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Invention
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Memory device comprising programmable command-and-address and/or data interfaces.
A memory devic... |
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Invention
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Training and operations with a double buffered memory topology.
System and method for training a... |
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Invention
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Memory device with configurable adaptive double device data correction.
Technologies for configu... |
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Invention
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Device assisted cold page tracking.
Disclosed are techniques for a memory buffer to track access... |
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Invention
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High capacity memory system using standard controller component.
The embodiments described herei... |
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Invention
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Memory component with error-detect-correct code interface.
A memory component internally generat... |
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Invention
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Data buffer for memory devices with memory address remapping.
A memory system includes a memory ... |
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Invention
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Memory repair method and apparatus based on error code tracking.
A memory module is disclosed th... |
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Invention
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Stacked device system.
Multiple device stacks are interconnected in a ring topology. The inter-d... |
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Invention
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Memory system for flexibly allocating compressed storage.
A memory system enables a host device ... |
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Invention
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Stacked memory component. An assembly comprises a single face up base die (a.k.a., logic die) tha... |
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Invention
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Mitigation of refresh management row hammer.
A controller periodically (based on, for example, c... |
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Invention
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Reordering memory controller.
A memory controller includes a request queue and associated logic ... |
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Invention
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Low-power source-synchronous signaling.
A method of operating a memory controller is disclosed. ... |
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Invention
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High-capacity memory module with high command-bandwidth utilization and consistent latency. A mem... |
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Invention
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Memory appliance couplings and operations.
System and method for improved transferring of data i... |
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Invention
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Memory module with memory-ownership exchange.
Described are computational systems in which hosts... |
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Invention
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Apparatus and method for selective refresh suppression.
A memory device includes an array of sto... |
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Invention
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Memory component with adjustable core-to-interface data rate ratio.
A memory component includes ... |
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Invention
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Timing-drift calibration.
The disclosed embodiments relate to components of a memory system that... |
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Invention
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Clock generation for timing communications with ranks of memory devices.
A memory controller inc... |
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Invention
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Techniques for storing data and tags in different memory arrays.
A memory controller includes lo... |
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Invention
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Active interposer system.
An interposer interconnecting a first integrated circuit and a second ... |
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Invention
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Using dynamic bursts to support frequency-agile memory interfaces.
The disclosed embodiments rel... |
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Invention
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Block copy.
An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also ... |
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Invention
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Interconnect based address mapping for improved reliability.
Row addresses received by a module ... |
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Invention
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High-throughput low-latency hybrid memory module.
Disclosed herein are techniques for implementi... |
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Invention
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Interface for memory readout from a memory component in the event of fault.
Memory controllers, ... |
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Invention
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Domain-selective control component.
A control component implements pipelined data processing ope... |
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Invention
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Context-based compression in a memory system.
A memory system selectively compresses and/or deco... |
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Invention
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High performance persistent memory.
The embodiments described herein describe technologies for n... |
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Invention
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Storage and access of data and tags in a multi-way set associative cache.
Disclosed is a dynamic... |
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Invention
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Interface circuit for converting a serial data stream to a parallel data scheme with data strobe ... |
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Invention
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Dram metadata access.
A memory device includes functionality (e.g., mode, command, etc.) to conc... |
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Invention
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Flash memory device having a calibration mode.
A method of operation of a flash integrated circu... |
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Invention
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Signal receiver with skew-tolerant strobe gating.
A first-in-first-out (FIFO) storage structure ... |
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Invention
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Memory device with fine-grained refresh.
An integrated circuit (IC) memory device includes an ar... |
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Invention
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On-die termination of address and command signals. A memory device includes a set of inputs, and ... |
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Invention
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Reduced latency metadata encryption and decryption.
Techniques for providing reduced latency met... |
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2022
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Invention
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Low overhead refresh management of a memory device.
A system and method for performing a low ove... |
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Invention
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Logging burst error information of a dynamic random access memory (dram) using a buffer structure... |
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Invention
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Split-path equalizer and related methods, devices and systems. This disclosure provides a split-p... |
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2015
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P/S
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Computer hardware; integrated circuits; computer chips; microprocessors; computer memories; compu... |
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2014
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P/S
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Scientific, nautical, surveying, electric, photographic, cinematographic, optical, weighing, meas... |
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P/S
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computer hardware and software for electronic design interface validation and testing; computer h... |
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P/S
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Computer hardware and software for validation and testing of electronic circuitry and chips; comp... |
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2012
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P/S
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Light emitting diode (LED) light controls; light emitting diode (LED) displays; light emitting di... |
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2011
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P/S
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Appareils et instruments pour l'enregistrement, la transmission, le traitement, le stockage et l'... |
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P/S
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Apparatus and instruments for recording, transmitting,
processing, storing and exchanging data, ... |
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P/S
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Apparatus and instruments for the recording, transmission, processing, storage and exchange of da... |
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2008
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P/S
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Computers; computer hardware; computer memories; application-specific integrated circuits and gra... |
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2004
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P/S
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Computers; computer hardware; computer memories; memory devices; memory controllers; memory syste... |
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P/S
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Computer memories; memory devices, namely, [ dynamic random access memories (DRAMS), ] memory sys... |
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2003
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P/S
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Semiconductor devices and integrated circuits |
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P/S
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Licensing of intellectual property and technology; patent licensing |
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P/S
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Computer hardware; computer software; computer peripherals; computer memory components; microproc... |
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2002
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P/S
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LICENSING OF INTELLECTUAL PROPERTY AND PATENTED TECHNOLOGY TO OTHERS |
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P/S
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Licensing of intellectual property and technology |
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P/S
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Computer software and hardware, especially in the field of encrypted and secure communication as ... |
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1995
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P/S
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microprocessor components, peripheral controller components and computer memory components, namel... |
