A hybrid memory includes cache of relatively fast and durable dynamic, random-access memory (DRAM) in service of a larger amount of relatively slow and wear-sensitive flash memory. An address buffer on the module maintains a static, random-access memory (SRAM) cache of addresses for data cached in DRAM.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
2.
LOW-LATENCY MULTI-KEY ENCRYPTION AND DECRYPTION ENGINE AND TECHNIQUES
Disclosed systems and techniques involve low-latency multi-key encryption processing in which block keys are precomputed based on multiple cryptographic keys, stored, and then selected for encryption or decryption of data during run-time cryptographic operations. The block keys may be precomputed, for each cryptographic key, in such quantities that allow uninterrupted flow of encryption or decryption operations. Replacement block keys may be concurrently generated to replace the blocks being consumed and authentication values may be computed or updated. Various described techniques allow parallel processing for efficient low-latency block key generation and cryptographic operations.
Technologies for optimizing area and latency for network interfaces with data protection are described. One system includes a Media Access Control (MAC)unit coupled to a physical coding sublayer (PCS) through a media-independent interface (MII bus) and a MACsec engine located between the MAC unit and the PCS. The MAC unit provides MII signals with packet data on the MII bus, provides extra MII signals on the MII bus to eliminate MII bus decoding by the MACsec engine, and provides early packet signals to the MACsec engine. The early packet signals allow the MACsec engine to perform classification and transformation ahead of receiving the MII signals with the packet data on the MII bus. The MACsec engine modifies the packet data with substantially zero egress latency.
H04L 43/026 - Capture des données de surveillance en utilisant l’identification du flux
H04L 49/351 - Interrupteurs spécialement adaptés à des applications spécifiques pour des réseaux locaux [LAN], p. ex. des commutateurs Éthernet
H04L 69/324 - Protocoles de communication intra-couche entre entités paires ou définitions d'unité de données de protocole [PDU] dans la couche liaison de données [couche OSI 2], p. ex. HDLC
4.
INTEGRATED CIRCUIT MEMORY DEVICES WITH UNIDIRECTIONAL PORTS FOR CONCURRENT INTERFACE OPERATIONS
Technologies for concurrent interface operations of integrated circuit memory devices are described. An integrated circuit memory device includes an input port, a control port, and an output port. The input port receives interleaved input and a first timing reference. The interleaved input includes one or more commands or write data. The control port receives one or more control signals that specify that the interleaved input is the one or more commands or the write data. The output port transmits read data and a second timing reference. The commands or write data can be received concurrently with transmitting the read data.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
5.
DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY AT HIGH SIGNALING RATES
Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.
G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
7.
IN-PACKAGE ERROR CORRECTION FOR MULTI-DIE MEMORY STACKS
A memory device comprises a plurality of memory die arranged in a vertical stack. Each of the plurality of memory die comprises a memory array and an error correction circuit. The error correction circuit of at least one of the plurality of memory die is configured to generate parity information for data to be stored in the memory device, and at least a portion of the parity information is stored in the memory array of at least one other memory die of the plurality of the memory die.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
8.
Methods and Circuits for Streaming Data to Processing Elements in Stacked Processor-Plus-Memory Architecture
A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.
Disclosed aspects and implementations are directed to systems and techniques for efficient randomization-protected comparison operations deploying linear transformations and or matrix multiplications in the context of processing an input into the cryptographic operation. The disclosed techniques include obtaining a masked representation of a first vector and a second vector, the masked representation including shares of the first vector and the second vector or shares of a difference of the first vector and the second vector. The techniques further include transforming, using a matrix-based randomization operation, the masked representation to a transformed representation and obtaining, using the transformed representation, a determination whether the first vector is equal to the second vector. The techniques further include computing, using the determination, an output of the cryptographic operation associated with the input into the cryptographic operation.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
The described embodiments provide an integrated circuit (IC) memory controller to control operation of an IC memory device. The IC memory device includes a memory core and internal clock circuitry. The IC memory controller includes a command interface to transmit, to the IC memory device, a read command and a phase adjustment command. The phase adjustment command specifies a phase adjustment operation, to be performed by the IC memory device, in an intervening time between receipt of the read command by the IC memory device and the IC memory device outputting data accessed in response to receiving the read command. The internal clock circuitry is disabled after outputting the data. A data interface receives the data. A transmitter transmits a timing reference signal to the IC memory device to time outputting of the data by the IC memory device.
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
A memory controller for a dynamic random-access memory (DRAM) is disclosed. The memory controller includes control circuitry that is configured to transmit, via a command/address (CA) interface, a command to place the DRAM into a mode that causes the DRAM to perform a self-refresh operation. The memory controller is configured to receive address information recorded by the DRAM while operating in a test-during-self-refresh mode. The address information identifies memory cells internally read and evaluated for an error by the DRAM during the self-refresh operation.
G11C 29/24 - Accès à des cellules additionnelles, p. ex. cellules factices ou cellules redondantes
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
G11C 29/50 - Test marginal, p. ex. test de vitesse, de tension ou de courant
14.
MULTI-CONFIGURATION STACKED DIE DYNAMIC RANDOM ACCESS DEVICES
The embodiments herein are directed to technologies multi-configuration stacked die DRAM devices. DRAM devices may include a first semiconductor die, a second semiconductor die, and a plurality of input/output (I/O) pins. The DRAM device can be configured in a first mode of operation by connecting a first die and a second die to a first set of the plurality of I/O pins. The DRAM device can be configured in second mode of operation, the first semiconductor die is configured to connect to the first set of the plurality of I/O pins and the second semiconductor die is configured to connect to a second set of the plurality of I/O pins.
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G06F 12/08 - Adressage ou affectationRéadressage dans des systèmes de mémoires hiérarchiques, p. ex. des systèmes de mémoire virtuelle
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G11C 11/4078 - Circuits de sécurité ou de protection, p. ex. afin d'empêcher la lecture ou l'écriture intempestives ou non autoriséesCellules d'étatCellules de test
Described are computational systems in which hosts share pooled memory on the same memory module. A memory buffer with access to the pooled memory manages which regions of the memory are allocated to the different hosts such that memory regions, and thus the data they contain, can be exchanged between hosts. Unidirectional or bidirectional data exchanges between hosts swap regions of equal size so the amount of memory allocated to each host is not changed as a result of the exchange.
A memory controller includes a processing device to execute latency tracking logic to determine respective latencies for a plurality of memory access requests in a memory access queue. The latency tracking logic further determines respective bandwidth usages of the memory controller corresponding to the plurality of memory access requests and stores respective counts of the plurality of memory access requests having respective latencies corresponding to a plurality of latency ranges for the respective bandwidth usages. The latency tracking logic further configures operations of the memory controller in view of the respective counts for the respective bandwidth usages.
Write data bursts directed to two different channels (or ranks) may be time-interleaved and transmitted to a data buffer device. The data buffer device deinterleaves the write data bursts and transmits them to memory devices via two different memory channel data interfaces. When one of the channels is not being written to, the host may time-interleave write data for two write data bursts that are directed to the same channel. The write data burst for the first channel is transmitted to the memory devices via the first channel. The time-demultiplexed write data burst for the next write transaction directed to the first channel is stored by the data buffer device. At a later time, the data buffer device transmits stored write data burst to the memory devices via the first channel.
A DRAM device may have eight channels. In a first mode, these channels may all be operated independently of each other and each access different internal memory cores. In a second mode, four of the eight channels may be inactivated. In a third mode, six of the eight channels are inactivated leaving two channels active. In a fourth mode, seven channels are inactivated leaving a single channel active. In each of the second mode, third mode, and fourth mode, the remaining active channel(s) respectively access the internal memory cores that otherwise would have been accessed by the inactivated channels. To help reduce the pin count of an eight-channel device (and associated controller), various signals may be shared between the eight channels and/or subgroups (e.g., four channels per subgroup, two channels per subgroup, etc.).
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G06F 12/08 - Adressage ou affectationRéadressage dans des systèmes de mémoires hiérarchiques, p. ex. des systèmes de mémoire virtuelle
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
H03K 19/00 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion
G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G11C 11/4078 - Circuits de sécurité ou de protection, p. ex. afin d'empêcher la lecture ou l'écriture intempestives ou non autoriséesCellules d'étatCellules de test
19.
MULTIPLEXED STACK IDENTIFIERS FOR MULTI-DIE STACKED MEMORY
A memory device comprises a base die and three or more memory dies arranged in a vertical stack above the base die. The memory device further comprises two sets of connections per external channel between the three or more memory dies and the base die, wherein multiplexing circuitry on the base die manages concurrent access to two of the three or more memory dies via the two sets of connections.
A multiplexed stacked memory device comprises a base die and memory stack comprising one or more memory dies supporting a set of memory banks. The memory banks are organized into bank groups each internally accessed via separate internal data buses. The internal data buses may operate as different internal pseudochannels of a set of internal channels. The base die includes bus aggregation logic to switch data between an external data bus and multiple internal data buses, thereby enabling access to multiple bank groups via the single external data bus. The memory device may be configurable between a sequential access mode to enable sequential access on the external data bus to data on the multiplexed internal data buses and an interleaved access mode that enables interleaved access between the external data bus and the multiplexed internal data buses.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p. ex. canal ou processeur périphérique
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
G06F 13/364 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant des signaux indépendants de demande ou d'autorisation, p. ex. utilisant des lignes séparées de demande et d'autorisation
G06F 13/368 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 13/10 - Commande par programme pour dispositifs périphériques
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 13/20 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
Multiple multi-channel dynamic random access memory (DRAM) die are stacked with each other. Each DRAM die of the stack includes two sets of I/O pads for each channel on the die. Based on the rotational orientation of a respective die in the stack, one of the two sets of I/O pads are used for data communication, and the other set is not used. The set of I/O pads that will be closest to the memory controller may be selected thereby shortening the signal traces between the controller and the die. The die in the stack may have one of two rotational orientations. A first one of the two sets of I/O pads are used by the die having a first rotational orientation (e.g., 0°), and a second one of the two sets of I/O pads are used by the die having a second rotational orientation (e.g., 180°).
Helper data and/or physically unclonable function (PUF) output data may be analyzed to determine which bits of the raw PUF output are stable. A first subset of the stable PUF output bits are selected (e.g., randomly) to generate a first stable PUF output value to be used as a first device unique value. To change the device unique value (a.k.a., digital fingerprint or fingerprint) of the integrated circuit generated by the PUF circuitry, new subsets (which may be generated off-chip) with different stable PUF output bits may be provided to the integrated circuit (i.e., provisioned) from time to time (e.g., with a new firmware/software update, after some arbitrary period of time—e.g., one year—etc.). Each new and different subset of stable bits used by the integrated circuit causes the integrated circuit to generate new, and different, device unique values.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range, and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.
Bandwidth for information transfers between devices is dynamically changed to accommodate transitions between power modes employed in a system. Bandwidth is changed by selectively enabling and disabling individual control links and data links that carry information. During a highest bandwidth mode for the system, all of the data and control links are enabled to provide maximum information throughout. During lower bandwidth modes for the system, at least one data link and/or at least one control link is disabled to reduce the power consumption of the devices. At least one data link and at least one control link remain enabled during each low bandwidth mode. For these links, the same signaling rate is used for both bandwidth modes to reduce latency that would otherwise be caused by changing signaling rates. Also, calibration information is generated for disabled links so that these links may be quickly brought back into service.
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3293 - Économie d’énergie caractérisée par l'action entreprise par transfert vers un processeur plus économe en énergie, p. ex. vers un sous-processeur
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
25.
TRANSMITTER WITH DIFFERENTIAL SIGNAL CROSS POINT VOLTAGE CONTROL CIRCUITRY
Technologies for transmitters with differential signal cross point voltage control are described. One transmitter circuit includes a differential driver circuit to generate a differential output signal. The differential driver circuit includes a programmable phase distribution to adjust a differential cross-point ratio of the differential driver circuit. The differential driver circuit includes a plurality of voltage-mode drivers, each voltage-mode driver comprises a pull-up transistor, a pull-down transistor, and a pre-driver with a programmable phase that is individually controlled for each voltage-mode driver such that the plurality of voltage-mode drivers collectively adjust the differential cross-point ratio.
H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
The embodiments herein are directed to technologies for electrical pad orientation within dual data rate packages. One semiconductor package includes interconnect layers, a substrate layer, and a ball gate array (BGA), the interconnect layers between the substrate layer and the BGA. Electrical connections between electrical pads in the substrate layer and electrical pads in the interconnect layers are configured to remain separate and create electrical connection equity between the electrical pads and the corresponding solder balls of the BGA.
A buffer integrated circuit (IC) chip is disclosed. The buffer IC chip includes host interface circuitry to receive a read command to retrieve read data from a memory. Memory interface circuitry couples to the memory. Data freshness authentication circuitry performs a freshness verification operation on the read data. Read data forwarding circuitry, in a skid mode of operation, transmits the read data to the host prior to completion of the freshness verification operation.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
28.
PROTECTION OF POLYNOMIAL CRYPTOGRAPHIC OPERATIONS AGAINST SIDE-CHANNEL ATTACKS WITH CHANGE-OF-VARIABLE TRANSFORMATIONS
Disclosed aspects and implementations are directed to systems and techniques for protecting cryptographic operations using change-of-variable transformation, from a first variable to a second variable, of a first polynomial obtained using an input into a cryptographic operation and a second polynomial obtained using a cryptographic key for the cryptographic operation, performing a joint operation using the transformed first polynomial and the transformed second polynomial, and computing an output of the cryptographic operation using an output of the joint operation.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
29.
STACKED DYNAMIC RANDOM ACCESS MEMORY (DRAM) DEVICE WITH MULTIPLE MASTER DIE
A stacked die device includes a first master dynamic random access memory (DRAM) die having a first command interface to receive first commands and a first data interface to transfer first data. A second master DRAM die is stacked with the first master DRAM die and includes a second command interface to receive second commands that are independent of the first commands, and a second data interface to transfer second data that is independent of the first data. The first and second master DRAM die form respective portions of first and second memory channels. A third DRAM die is stacked with the first and second master DRAM die and includes a first selectively-enabled data input/output (I/O) circuit coupled to the first master DRAM die. A fourth DRAM die is stacked with the other die, and includes a second selectively-enabled data input/output (I/O) circuit coupled to the second master DRAM die.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
30.
DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING
A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
31.
BASE DIE FOR STACKED MEMORY DEVICE WITH MEMORY CONTROLLERS AND INTERCONNECT
A stacked memory device comprises a stack of dies including a base die comprising interface logic and a set of memory dies including memory banks. The interface logic includes a host-side interface to a host device that communicates packetized serial commands and data, an interconnect, and a set of memory controllers corresponding to respective memory channels. The host-side interface may include one or more independent serial links including at least one command link, at least one response link, and at least one data link. The memory controllers operate in parallel to receive the packetized commands and perform memory operations with respect to the memory banks. The interconnect may comprise a full crossbar switch that enables switching between any of the serial links of the host-side interface and any of the memory channels controlled by the respective memory controllers.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p. ex. canal ou processeur périphérique
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
G06F 13/364 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée utilisant des signaux indépendants de demande ou d'autorisation, p. ex. utilisant des lignes séparées de demande et d'autorisation
G06F 13/368 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès décentralisée
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 13/10 - Commande par programme pour dispositifs périphériques
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 13/20 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
32.
HIGH CAPACITY MEMORY SYSTEM WITH IMPROVED COMMAND-ADDRESS AND CHIP-SELECT SIGNALING MODE
A memory controller and buffers on memory modules each operate in two modes, depending on the type of motherboard through which the controller and modules are connected. In a first mode, the controller transmits decoded chip-select signals independently to each module, and the motherboard data channel uses multi-drop connections to each module. In a second mode, the motherboard has point-to-point data channel and command address connections to each of the memory modules, and the controller transmits a fully encoded chip-select signal group to each module. The buffers operate modally to correctly select ranks or partial ranks of memory devices on one or more modules for each transaction, depending on the mode.
A data buffer die is stacked with multiple memory die and interconnected with wire bonds. This packaging configuration helps reduce transmit power by reducing the electrical distance between memory die only packages and a separately packaged data buffer. This packaging configuration may also reduce the cost of memory modules using this type of packaging configuration by eliminating the need for separate packaging for the data buffer die. This configuration may be used to aggregate data communicated with the multiple memory die allowing a common timing signal to be used for communication with a host. This configuration may allow for reduced size memory modules by eliminating the need for separate space on memory modules to be used for the separately packaged data buffer devices. This configuration may help improve data routing on memory module by providing for the re-orientation (e.g., rotate by 90°) of signals to/from the multiple die packages.
A dynamic random access memory (DRAM) device includes an array of DRAM storage cells. Refresh control circuitry refreshes the DRAM storage cells within a refresh period. The refresh control circuitry includes circuitry to refresh, during a first sub-period of the refresh period, at least one row of the array of DRAM storage cells in a selected one of the multiple banks in response to receipt of an activate command from a memory controller that is directed to the selected one of the multiple banks. At the end of the first sub-period of the refresh period, a value is generated indicating a remaining number of refresh operations to refresh a remaining number of unrefreshed DRAM storage cells of the array of DRAM storage cells within a remaining period of the refresh period. Transmit circuitry transmits the value to the memory controller.
Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.
A memory allocation device for deployment within a host server computer includes control circuitry, a first interface to a local processing unit disposed within the host computer and local operating memory disposed within the host computer, and a second interface to a remote computer. The control circuitry allocates a first portion of the local memory to a first process executed by the local processing unit and transmits, to the remote computer via the second interface, a request to allocate to a second process executed by the local processing unit a first portion of a remote memory disposed within the remote computer. The control circuitry further receives instructions via the first interface to store data at a memory address within the first portion of the remote memory and transmits those instructions to the remote computer via the second interface.
A random access memory device includes memory cells in each row for storing metadata related to accesses to that row. These metadata dedicated memory cells may store counter values that may be updated (e.g., incremented or decremented) when certain events occur (e.g., activate row—ACT, column read—CAS, error detected, etc.). Which events cause an update of the metadata stored in a row, and under what conditions related to the metadata/count value (e.g., threshold, match, threshold value, etc.) cause further action to be taken (e.g., alert controller, set mode register, etc.) are configurable by a controller. Additional functions related to the metadata/counters are also configurable such as scanning counter values to determine the row address with highest or lowest value and pattern matching (e.g., process identification match/mismatch).
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 16/14 - Détails de la recherche de fichiers basée sur les métadonnées des fichiers
38.
Memory Controller and Command Buffer for Parallel Metadata Access and Enhanced Error Correction
A memory system includes a command buffer that services commands from a host processer via a memory controller to access data interleaved across multiple DRAM devices. The memory controller uses parity bits augmented with metadata for improved error detection and correction. Cache lines of data and parity bits are interleaved across the DRAM devices. Metadata for each cache line is stored in a separate, device-specific address in just one of the DRAM devices. The memory controller and command buffer save time and power by grouping accesses for metadata stored in different devices.
A receiver includes variable gain analog front-end (AFE) circuitry, a main sampler, and a monitor sampler. The gain of the AFE circuitry is controlled by a gain indicator provided by control circuitry. The threshold voltage of the monitor sampler is provided by a digital-to-analog converter (DAC) having a controllable step size. A calibration sequence is used to search for step size settings that, for various gain indicator values, reproduce or approximate a baseline threshold voltage of the main sampler at a baseline gain setting. The relationships between these step size settings and gain indicator values may be used to ensure a close relationship between the threshold of the main sampler and the threshold of the monitor sampler over a range of gain settings.
A memory buffer services commands from a host to access data in a memory using parity bits augmented with metadata for improved error correction and detection (EDC). The memory buffer performs EDC-protocol translation so EDC can be optimized for host-side and memory-side correction and detection. The memory buffer also services each host-side memory transaction with two or more memory-side transactions to efficiently read, write, and store metadata for each requested cache-line access.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
As information is written to a memory device stack, partial parity information is calculated by the non-parity devices in the stack from the information being written to that device and parity information received from the next lower device in the stack (if any). The partial parity information calculated by each non-parity device is transmitted to the next higher device in the stack so that it may perform a partial parity calculation using the partial parity information collectively calculated by the devices lower in the stack. Once complete parity has been collectively calculated by all of the non-parity devices in the stack, the complete parity information is stored by the parity memory device. The complete parity information may be used to recover or reconstruct data from a failing device in the stack by calculating and transmitting parity information from non-failing devices to the failing device and/or the parity device.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A 3D DRAM architecture may have one or more layers of cells where the access transistors of the memory cell array are fabricated among the metal layers rather than in the semiconductor (e.g., silicon) substrate. Counter and counter control circuits for each row in the memory cell array are fabricated under the array. These counters track the number of row hammers each row experiences. When a counter indicates a row has experienced a threshold number of row hammers, that row is refreshed. The row may be refreshed immediately after the current row is closed. The row may be scheduled to be refreshed as part of a regular refresh sequence. A signal may be sent to the memory controlling indicating that the bank with the row being refreshed immediately should not be accessed until the refresh is complete.
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4078 - Circuits de sécurité ou de protection, p. ex. afin d'empêcher la lecture ou l'écriture intempestives ou non autoriséesCellules d'étatCellules de test
43.
MEMORY SYSTEMS AND TECHNIQUES WITH SUPPORT FOR SPARSE NEURAL NETWORK COMPUTATIONS
Aspects and implementations include systems and techniques that implement efficient indexing and access to sparse neural network parameters. In one example, a memory system includes a buffer chip communicatively coupled to the one or more memory units. The buffer chip is to obtain a first index associated with positions of a plurality of elements of a sparse matrix (SM) along a first dimension of the SM and obtain a second index associated with positions of the plurality of the elements of the SM along a second dimension of the SM. The buffer chip is further to obtain, using the first index and the second index, memory addresses of the plurality of the elements of the SM stored in the one or more memory units, and retrieve, based on the memory addresses, the plurality of the elements of the SM from the one or more memory units.
Technologies for dynamic random access memory (DRAM) devices with variable burst lengths are described. One DRAM device includes a first mode of operation having a first burst length and a first column address range, and a second mode of operation having a second burst length and a second column address range. Only one of the first burst length and the second burst length is a power of two. A first product of the first column address range and the first burst length and a second product of the second column address range and the second burst length are substantially the same. The DRAM device includes an error correction code (ECC) block to generate, receive, and store ECC parity associated with data in the first mode of operation and the second mode of operation.
Technologies for stacked memory devices with error recovery support are described. One stacked memory device includes a base layer and a plurality of memory layers. The base layer includes a primary interface for regular data, a secondary interface for checkpoint data, and a buffer for temporarily storing the checkpoint data. The buffer is accessible by the plurality of memory layers and the secondary interface. The base layer, in response to a first command, initiates a first transfer of a first block of bits from a memory layer of the plurality of memory layers into the buffer. The base layer, in response to a second command, initiates a second transfer of a second block of bits from the buffer out of the stacked memory device via the secondary interface. The second transfer occurs concurrently with a third transfer of data over the primary interface.
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/20 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
46.
INTEGRITY-PROTECTION AUTHENTICATION THROUGH INTERMEDIATE STATES
Technologies for protecting data integrity of an authentication algorithm using intermediate states are described. One inline memory encryption (IME) engine performs an authentication algorithm that uses a hash function to compute an authentication tag. The IME engine includes integrity-protection logic to store an intermediate state of a tag computation and incoming data segments. In the event of an error in the computation, the integrity-protection logic can compute the intermediate state again using a last intermediate state and the last data segment.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
47.
DRAM Cache with Stacked, Heterogenous Tag and Data Dies
A high-capacity cache memory is implemented by multiple heterogenous DRAM dies, including a dedicated tag-storage DRAM die architected for low-latency tag-address retrieval and thus rapid hit/miss determination, and one or more capacity-optimized cache-line DRAM dies that render a net cache-line storage capacity orders of magnitude beyond that of state-of-the art SRAM cache implementations. The tag-storage die serves double-duty in some implementations, yielding rapid tag hit/miss determination for cache-line read/write requests while also serving as a high-capacity snoop-filter in a memory-sharing multiprocessor environment.
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p. ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.
An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.
Disclosed aspects and implementations are directed to systems and techniques for multi-counter memory encryption with targeted access of individual memory blocks. In one example, replacing a stored block in a memory device includes encrypting a replacement block using a first initialization vector (IV) having a block counter associated with a number of times the stored block has been previously replaced, replacing the stored block with the encrypted replacement block in the memory device, encrypting a second IV to obtain a tag encryption vector, the second IV including a tag counter associated with a number of times an authentication tag for a plurality of blocks has been previously updated, and updating, using the encrypted second IV, the authentication tag for the plurality of blocks.
A buffer device for a serial attached memory system interfaces between a host device and one or more memory devices. The buffer device receives packetized commands from the host device for performing memory operations and facilitates transfer of read and write data between the host device and the one or more memory devices. The host device controls scheduling of the packetized commands. The serial buffer device generates memory device commands based on the packetized commands and sequences the commands to control command timing in a manner that meets timing specifications of the memory device. The memory buffer device may optionally perform memory media ECC computations to generate ECC bits for write data being written to the one or more memory devices and to verify ECC bits of read data being read from the one or more memory devices.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G06F 13/30 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle avec commande prioritaire
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
In response to some access commands, a DRAM device is configured to receive cache tag query values and to compare stored cache tag values with the cache tag query values. A hit/miss (HM) interface/bus may indicate the result of the cache tag compare and stored cache line status bits to a controller. Based on the cache tag compare results and status bits of the associated cache line, the timing and content of the data responses and/or compare responses these access commands may be varied. The controller is configured to, based on the indicated results of the cache tag compare and stored cache line status bits, expect the varied timing and content in response to the access commands transmitted by the controller. In an embodiment, the DRAM protects the stored cache tag values with an error detection and correction code.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
53.
MEMORY CONTROLLER PARTITIONING FOR HYBRID MEMORY SYSTEM
A compute system includes an execution unit (e.g. of a CPU) with a memory controller providing access to a hybrid physical memory. The physical memory is “hybrid” in that it combines a cache of relatively fast, durable, and expensive memory (e.g. DRAM) with a larger amount of relatively slow, wear-sensitive, and inexpensive memory (e.g. flash). A hybrid controller component services memory commands from the memory controller component and additionally manages cache fetch and evict operations that keep the cache populated with instructions and data that have a high degree of locality of reference. The memory controller alerts the hybrid controller of available access slots to the cache so that the hybrid controller can use the available access slots for cache fetch and evict operations with minimal interference to the memory controller.
An intcgratcd-circuit memory device is configurable to operate in a relatively high-speed performance mode or a relatively low-speed, low-power mode. In the performance mode, accessing the memory device activates a wordline to select a full row of memory cells. A column of sense amplifiers reads from or writes to the active wordline and the memory device communicates the resulting data as a high-speed burst. In the low-power mode, an access activates a half wordline to select a half row of memory cells. A half column of sense amplifiers reads from or writes to the active wordline and the memory device communicates the resulting data as a low- speed burst.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G06F 12/04 - Adressage de mots de longueur variable ou de parties de mots
G11C 8/12 - Circuits de sélection de groupe, p. ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A memory device may be accessed via multiple channels (e.g., 2 channels, 4 channels, etc.). The data widths (i.e., number of data signals) allocated to each channel are configurable such that a given group of data input/output (I/O) signals may be part of a first channel in one configuration, but be part of another channel in a different configuration. Similarly, the memory arrays (e.g., banks, or bank groups) accessed by a given channel may be configurable such that a given memory array is accessed via a first channel in one configuration but is accessed via a different channel in a different configuration. Finally, the data burst length, data burst size, and data transfer clock cycle are configurable.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
An apparatus and method for low page overhead recompression. In one embodiment a memory buffer integrated circuit (IC) device is disclosed that includes a first circuit configured to independently compress equally sized portions of a page of data, and a second circuit configured to store the compressed data portions at respective addresses in memory. The memory buffer IC device also includes a third circuit configured to store a page table comprising an entry with information related to the respective memory addresses.
A high-capacity cache memory is implemented by one or more DRAM dies in which individual cache entries are split across multiple DRAM storage banks such that each cache-line read or write is effected by a time-staggered set of read or write operations within respective storage banks spanned by the target cache entry.
G06F 12/0895 - Mémoires cache caractérisées par leur organisation ou leur structure de parties de mémoires cache, p. ex. répertoire ou matrice d’étiquettes
G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p. ex. avec moyen de contrôle ou de surveillance
A fixed size block of data may be compressed, but not reduced in size, resulting in a high entropy (i.e., information carrying) portion and a low entropy (i.e., little or no information carrying—e.g., all zeros) portion. The high entropy portion and the low entropy portion of the compressed block may be stored by a controller in different memory devices of a memory module. The selection of the memory devices on the memory module to store the high entropy portion versus the low entropy portion may be based on temperature indicators associated with the memory devices. When reading or writing data to the module, entropy indicators (e.g., high or low entropy) are communicated and stored on a per memory device basis.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory modules, such as registered dual in-line memory modules (RDIMMs). One DRAM component may include a set of memory cells and steering logic. The steering logic may include a first data interface and a second data interface. The first and second data interfaces are selectively coupled to a controller component in a first mode and the first data interface is selectively coupled to the controller component in a second mode and the second data interface is selectively coupled to a second DRAM component in the second mode.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
60.
MULTI-CHANNEL MEMORY MODULE WITH VARIABLE-SPEED DRAM DEVICES AND DATA-BUFFER GEARBOX
A memory component supports relatively wide, low-bitrate bursts in a first operational mode. A data buffer combines the wide, low-bitrate bursts from multiple memory components into relatively higher-bitrate bursts for host communication. The memory component also supports relatively narrow, higher-bitrate bursts in a second operational mode. The data buffer combines the narrower, relatively high bitrate bursts from the multiple memory components into one burst for host communication. The bursts for host communication can be the same in both modes.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
61.
LATENCY-CONTROLLED INTEGRITY AND DATA ENCRYPTION (IDE)
Technologies for providing integrity and data encryption (IDE) with zero latency are described. One receiving device with a cryptographic circuit having an Advanced Encryption Standard (AES) engine with a fixed epoch size and a fixed latency for IDE can send a delay parameter to a transmitting device. The delay parameter represents a number of clock cycles corresponding to the fixed latency. The cryptographic circuit can pre-determine, using the AES engine, AES data for a first epoch before first input data of the first epoch is received from the transmitting device. After the number of clock cycles, the cryptographic circuit can receive the first input data from the transmitting device. The cryptographic circuit can determine first output data for the first epoch using the AES data and the first input data without storing the AES data in a buffer.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
62.
PROTECTION OF NEURAL NETWORKS BY OBFUSCATION OF NEURAL NETWORK OPERATIONS AND ARCHITECTURE
Aspects of the present disclosure involve implementations that may be used to protect neural network models against adversarial attacks by obfuscating neural network operations and architecture. Obfuscation techniques include obfuscating weights and biases of neural network nodes, obfuscating activation functions used by neural networks, as well as obfuscating neural network architecture by introducing dummy operations, dummy nodes, and dummy layers into the neural networks.
Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI). Additional equalization may also be applied to an input signal using analog front-end (AFE) circuitry with, for example, a continuous-time linear equalizer (CTLE) and/or a variable-gain-amplifier (VGA). Circuitry replicating the receiver AFE is provided with the same gain setting and an offset correction signal as the receiver AFE circuitry. In addition, a common-mode DFE tracking signal is used to correct for common-mode offsets introduced by the DFE tap values. In this manner, as a monitor threshold voltage provided to the input of the replica AFE circuitry is adjusted (e.g., swept), the AFE replica and common-mode DFE tracking compensate for gain variation and common-mode offsets introduced by the AFE circuitry and common-mode offsets due to DFE tap values thereby reducing the inaccuracies in signal eye measurements that would otherwise be introduced without these compensations/tracking.
A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while maintaining a fixed phase relationship between the input clock and the output clock regardless of the reference edge selection.
An integrated circuit (IC) memory device includes a command/address (CA) interface to receive CA information at multiple CA input circuits during a first mode of operation. The CA interface includes CA decoder circuitry to decode the CA information via a first CA decoding protocol during the first mode of operation. During a CA recovery mode of operation, the first CA decoding protocol is changed in response to detection of a CA error associated with a failed CA input circuit.
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
G06F 11/08 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/18 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage passif du défaut des circuits redondants, p. ex. par logique combinatoire des circuits redondants, par circuits à décision majoritaire
An apparatus and method for flexible metadata allocation and caching. In one embodiment of the method first and second requests are received from first and second applications, respectively, wherein the requests specify a reading of first and second data, respectively, from one or more memory devices. The circuit reads the first and second data in response to receiving the first and second requests. Receiving first and second metadata from the one or more memory devices in response to receiving the first and second requests. The first and second metadata correspond to the first and second data, respectively. The first and second data are equal in size, and the first and second metadata are unequal in size.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.
A computing device receives a request to run an application. The application is associated with a security context. The computing device obtains one or more permissions associated with the security context and modifies the one or more permissions based on a state of the computing device. The application is run based on the modified one or more permissions.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
An interconnected stack of Dynamic Random Access Memory (DRAM) die has a first set of DRAM die (e.g., two, three, four, etc.) coupled to a first independent memory channel, a second set of DRAM die (e.g., two, three, four, etc.) coupled to a second independent memory channel, and a shared die coupled to both independent memory channels. The shared die may be used to store information (e.g., error correcting code) for Reliability, Availability, and Serviceability (RAS) purposes. The shared die may also be used to replace the functionality of a failed or failing die.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
70.
STROBELESS DYNAMIC RANSOM ACCESS MEMORY (DRAM) DATA INTERFACE WITH DRIFT TRACKING CIRCUITRY
Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory chip is disclosed. The IC memory chip includes clock receive circuitry to receive a clock signal and command/address (C/A) receive circuitry to time reception of C/A signals using the clock signal. Data receive circuitry receives a first data burst from a first data path. Calibration circuitry sets an initial sampling phase for data reception timing of the first data burst relative to the clock signal. Timing circuitry tracks drift in the data reception timing using phase information from at least one toggling edge of the data burst and adjusts the data reception timing based on the phase information.
Memory devices on a memory module may include two (or more) interfaces that access non-overlapping sets of memory arrays (i.e., two pseudo-channels). The data bus directionality of each of the two pseudo-channels may be specified or required to always be in the same direction (i.e., both read, or both write). When the data bus directionalities are tied in this manner, the data buffer devices of the module may interleave/deinterleave (i.e., time-multiplex) data for communication with a host between the two pseudo-channel data busses. The data bus directionality of each of the two pseudo-channels may be independent of the directionality of the other pseudo-channel (i.e., either can read or write without regard to the data bus directionality of the other). When the data bus directionalities are independent in this manner, the data buffer devices may interleave/deinterleave data for communication with a host within each of the two pseudo-channel data busses.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
A memory system includes a host controller that issues access commands, including write pattern commands, to a dynamic, random-access memory (DRAM). Local control circuitry and a row-preset circuitry service write-pattern commands to minimize conflict with access transactions, e. In the memory device, local control circuitry and a row-preset circuit service the write-pattern commands in a manner that minimizes interference with normal read and write transactions. Presetting memory to e.g., erase potentially vulnerable data after use is therefore accomplished efficiently and with no or minimal impact on memory bandwidth and speed performance.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 13/00 - Interconnexion ou transfert d'information ou d'autres signaux entre mémoires, dispositifs d'entrée/sortie ou unités de traitement
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p. ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
G11C 8/12 - Circuits de sélection de groupe, p. ex. pour la sélection d'un bloc de mémoire, la sélection d'une puce, la sélection d'un réseau de cellules
A four-channel by two ranks-per-channel memory module includes four independent memory channels and dual-channel memory devices. The channels of the dual-channel memory module devices may be accessed independently. Thus, the four channels for accessing the memory module may each concurrently access, via a one of the two channels of the memory devices, a respective first rank and a second rank. Data buffer devices on the memory module communicate data between the two ranks and the channels. The data buffer devices multiplex/demultiplex (a.k.a., interleave/deinterleave) communication between the channels and the ranks so that the channels operate at a greater bandwidth (e.g., quad-data rate—QDR) than the memory devices (e.g., double-data rate—DDR). The data buffer devices also retime and/or redistribute data strobe signals communicated between the memory devices and the channels.
A memory module includes one or more memory devices and a memory interface chip coupled to the one or more memory devices via one or more communication links. The memory module further includes a persistent memory storing one or more sets of training and calibration settings corresponding to communication over the one or more communication links, where the one or more sets of training and calibration settings are stored in the persistent memory before operation of the memory module and used to configure one or more components of the memory interface chip during the operation of the memory module.
A multi-channel (e.g., two channel) memory device (e.g., dynamic random access memory —DRAM) shares a unidirectional read timing signal and a unidirectional write timing signal between the multiple channels. The write timing signal is transmitted to the memory device by a controller. The read timing signal is generated from the write timing signal by the memory device and transmitted to the controller. The write timing signal may be transmitted continuously. The read timing signal may be intermittently transmitted when any of the multiple channels are transmitting data to the controller. The command and address functions may be shared by the multiple channels. In an embodiment, the command and address functions may be separate for each of the multiple channels. A multi-channel device may comprise at least two identical memory device dies that are co-packaged and share unidirectional timing signals via an interface internal to the package.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.
Designs of a memory module can be configured for multiple rank configurations by varying the number of stacked die within each memory package on the module. Package arrangements help to support short command/address, clock, and data signal routing distances on the module. Heat dissipation may be reduced by limiting each package to one active die per package. Data buffers and short data channels to the packages are also supported. Stacked die of a module may be accessed as two separate time "slices." Combined registering clock driver and data buffer devices may be used. Some configuration are able to support Diekill error correction capability. Some configurations are able to support Packagekill error correction capability.
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.
When writing a block (e.g., cache line) of data to a memory, error detection and correction (EDC) information (check) symbols are calculated. The block of data, a first portion of the check symbols, and metadata are all written concurrently at a first address. The remaining portion of the check symbols are written at a second, different from the first, address. When reading the block of data, a first read command accesses the block of data, the first portion of the check symbols, and the metadata from the first address. Only the first portion of the check symbols is used to determine a first number of errors (if any) in the accessed data. If the first number of errors meets a threshold number of errors, a second read command is issued to access the second portion of the check symbols.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
84.
REVERSE DECOMPOSITION OF INTERMEDIATE VALUES IN CRYPTOGRAPHIC APPLICATIONS
Disclosed aspects and implementations are directed to systems and techniques for efficient execution of post-quantum cryptographic applications and protection of cryptographic computations against side-channel attacks. In one example, techniques for performing a cryptographic operation include generating a first value and computing, by the processing device, a second value. A low part of the second value is mapped to a high part of a product of a public value and the first value and a high part of the second value is mapped to a low part of the product of the public value and the first value. The techniques further include computing, using the second value, an output of the cryptographic operation that includes a digital signature for an input into the cryptographic operation or a ciphertext encrypting the input into the cryptographic operation.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
A memory device is operated using a reduced row address space (e.g., 48k rows per bank vs. a full capacity 64k rows per bank). The unused address space (e.g., 16k rows) is used and mapped by the memory device to store information for at least some of the bad rows. In this manner, many more bad rows may be "repaired" at the expense of a reduction in the capacity of the memory device. The translations of external row addresses to internal physical row addresses may include permuting row addresses within groups of row addresses to avoid bad rows within respective groups of row addresses. A linear filter (e.g., Bloom Filter, XOR filter, etc.) may be used to store information for the translations of external row addresses to internal physical row addresses. The information for the translations may be determined and programmed into the memory device once during manufacturing.
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G11C 8/20 - Circuits de sécurité ou de protection d'adresse, c.-à-d. dispositions pour empêcher un accès non autorisé ou accidentel
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die has a base logic die and one or more custom logic or processor die. The processor logic die snoops commands sent to and through the stack. In particular, the processor logic die may snoop mode setting commands (e.g., mode register set—MRS commands). At least one mode setting command that is ignored by the DRAM in the stack is used to communicate a command to the processor logic die. In response the processor logic die may prevent commands, addresses, and data from reaching the DRAM die(s). This enables the processor logic die to send commands/addresses and communicate data with the DRAM die(s). While being able to send commands/addresses and communicate data with the DRAM die(s), the processor logic die may execute software using the DRAM die(s) for program and/or data storage and retrieval.
An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
G06F 1/04 - Génération ou distribution de signaux d'horloge ou de signaux dérivés directement de ceux-ci
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/20 - Circuits d'initialisation de cellules de mémoire, p. ex. à la mise sous ou hors tension, effacement de mémoire, mémoire d'image latente
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 11/4072 - Circuits pour l'initialisation, pour la mise sous ou hors tension, pour l'effacement de la mémoire ou pour le préréglage
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
89.
DYNAMIC, RANDOM-ACCESS MEMORY WITH INTERLEAVED REFRESH
A memory includes a local control circuitry that manages refresh transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts refresh transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides refresh transactions into phases and periods based on whether the refresh transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt refresh transactions with access transactions in a manner that minimizes access interference.
Technologies for in-line memory encryption with a power-aware cache system (IME-PACS) are described. One memory encryption circuit includes cryptographic circuitry and control circuitry. Control circuitry, in a power-off process, causes the cryptographic circuitry to encrypt the plaintext data of one or more cache entries having the first persistent valid flag set to obtain ciphertext data, and stores the ciphertext data in a memory system. The control circuitry, in a power-on process, loads the ciphertext data from the memory system for the cache entries having the first persistent valid flag set, causes the cryptographic circuitry to decrypt the ciphertext data to obtain the plaintext data, and stores the plaintext data in the one or more cache entries of the first cache.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
91.
IN-LINE MEMORY ENCRYPTION WITH FRAGMENTED MEMORY INITIALIZATION
Technologies for in-line memory encryption with fragmented memory sanitization (IME-FMS) are described. One method splits a secure memory space into a plurality of subspaces and automatically initializes a first subspace of the plurality of subspaces to start a program. The method initializes a second subspace of the plurality of subspaces in response to a request for secure memory. The method creates back-pressure in response to a request for more secure memory when there are no initialized subspaces available.
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
A 3D memory device includes a plurality of mats that each include a memory array stacked over logic circuitry supporting operations of the memory array. The logic circuitry include a local column decoder under the memory array for selecting one or more local column select lines associated with a memory operation. The logic circuitry furthermore includes one or more selectable global array data bus redrivers for receiving global data signals from a set of global data signal buses, selecting one of the global data signal buses, and amplifying signals between the selected global data signal bus and a local data signal bus that communicates the data signals to and from the memory array. The 3D memory device supports concurrent sub-page accesses which may be interleaved for efficient memory operations.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
93.
A HIGH-SPEED, LOW-POWER, AND AREA-EFFICIENT TRANSMITTER
A transmitter employs simple inverters to predrive cascode-connected pull-up and pull-down output stages. Each output stage includes a drive transistor with a thin gate dielectric for fast switching. The drive transistor is cascode connected to a set of parallel-connected transistors. Calibration circuitry selectively enables the parallel-connected transistors to calibrate output resistance. The parallel transistors converge at a single resistor.
H03F 3/16 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs avec dispositifs à effet de champ
94.
Failover Methods and Systems in Three-Dimensional Memory Device
Described are memory systems and devices in which each memory die in a three-dimensional stack of memory dies includes drive and receive circuitry that can communicate data signals from the stack on behalf of all the memory dies in the stack. The drive and receive circuitry, if defective on one device in the stack, can be disabled and substituted with the drive and receive circuitry from another. The stack of memory dies can thus function despite a failure of drive or receive circuitry in one or more of the memory dies. Each memory die includes test circuitry to detect defective drive and receive circuitry.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module and provides for peer-to-peer communication of termination control signals.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4063 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation
G11C 11/413 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture, la synchronisation ou la réduction de la consommation
G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface
96.
HIGH LEVEL INSTRUCTIONS WITH LOWER-LEVEL ASSEMBLY CODE STYLE PRIMITIVES WITHIN A MEMORY APPLIANCE FOR ACCESSING MEMORY
A method of processing memory instructions including receiving a memory related command from a client system in communication with a memory appliance via a communication protocol, wherein the memory appliance comprises a processor, a memory unit controller and a plurality of memory devices coupled to the memory unit controller. The memory related command is translated by the memory appliance into a plurality of primitive commands that are lower level commands and formatted to perform prescribed data manipulation operations on data of the plurality of memory devices stored in data structures. The plurality of primitive commands is executed on data stored in the memory devices to produce a result, wherein the executing is performed by the memory controller. A direct memory transfer of the result is established over the communication protocol to a network.
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p. ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
H04L 67/568 - Stockage temporaire des données à un stade intermédiaire, p. ex. par mise en antémémoire
A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.
G06F 1/3237 - Économie d’énergie caractérisée par l'action entreprise par désactivation de la génération ou de la distribution du signal d’horloge
G06F 1/12 - Synchronisation des différents signaux d'horloge
G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 12/0855 - Accès de mémoire cache en chevauchement, p. ex. pipeline
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/36 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs
G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
98.
CIRCUITS AND METHODS FOR SELF-ADAPTIVE DECISION-FEEDBACK EQUALIZATION IN A MEMORY SYSTEM
Described are integrated circuits for equalizing parallel write-data and address signals from a memory controller. The integrated circuits each include a set of decision-feedback equalizers, one equalizer for each received signal. Each equalizer has a main sampler and a monitor sampler, each of which samples the respective input signal on edges of a common timing-reference signal. The main sampler samples the input signal relative to a reference. The monitor sampler samples the input signal relative to an adjustable threshold calibrated to monitor one or more levels of the input signal. A feedback network adjusts the respective input signal responsive to one or more tap values that can be adjusted to equalize the signal. An adaptive tap-value generator for one or a collection of the equalizers adjusts the tap value or values as a function of least-mean squares of errors to one or more of the sampler input ports.
Multiple stacks of dynamic random access memory devices are coupled with, and attached to, a buffer device to form a memory assembly. The buffer device interfaces between a controller and the memory device stacks such that each memory device stack function as separate ranks of memory residing on the same memory channel. The buffer device also serializes/deserializes data communicated with the memory device stacks such that the memory devices of a stack being accessed concurrently communicate with the buffer device using wider data words than are used to communicate with the controller. The buffer device and the controller may communicate using unidirectional communication links and a deterministic protocol using commands that combine the row and column functions and addressing. Read access commands may be pre-scheduled to allow multiple consecutive read commands to be issued without delaying read commands to allow for communication data on the unidirectional command/data links.
An integrated circuit host device controls operation of a memory device. The memory device includes a stack of integrated circuit memory dies, a plurality of command interfaces, and a sideband interface. The host device includes control circuitry configured to provide mode signals to the sideband interface of the memory device, so as to selectively transition one or more of the plurality of command interfaces of the memory device to a power state in which one or more command interfaces of the memory device do not respond to memory access commands.
G06F 1/28 - Surveillance, p. ex. détection des pannes d'alimentation par franchissement de seuils
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
