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2026
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Invention
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Calibration of electrical parameters in a deep learning artificial neural network.
Numerous exam... |
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Invention
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Output circuit for analog neural memory in an artificial neural network.
Numerous embodiments ar... |
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Invention
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Determination of a bias voltage to apply to one or more memory cells.
In one example, a method c... |
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Invention
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Input circuitry for analog neural memory in a deep learning artificial neural network.
Numerous ... |
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Invention
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Redundancy for an array of non-volatile memory cells using tag registers.
Numerous examples are ... |
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Invention
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Resistive random access memory cell array.
Numerous examples are disclosed of systems and method... |
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2025
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Invention
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Artificial neural network comprising an analog array and a digital array.
Numerous examples are ... |
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Invention
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Memory cell array comprising sensing bitline metal layer and current-carrying metal layer.
In on... |
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Invention
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Output block for array of non-volatile memory cells.
In one example, a circuit comprises a curre... |
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Invention
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Dual step multi-level cell program method for non-volatile memory. n-1n-1nn-1n-1n-1nn banks and t... |
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Invention
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Dual step multi-level cell program method for non-volatile memory.
A method and system that stor... |
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Invention
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Program refresh for non-volatile memory array in a semiconductor device. Programming technique fo... |
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Invention
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Program refresh for non-volatile memory array in a semiconductor device.
Programming technique f... |
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Invention
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Rram memory cell structure. Discloses is a resistive random access memory (RRAM) memory cell stru... |
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Invention
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Current profile balancing for flash memory. In one example, a method comprises precharging at lea... |
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Invention
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Rram memory cell structure.
A resistive random access memory (RRAM) memory cell structure includ... |
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Invention
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Fast program of non-volatile memory cells. A method of operating a semiconductor device by applyi... |
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Invention
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Current profile balancing for flash memory.
In one example, a method comprises precharging at le... |
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Invention
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Parameter enhanced sequential programming method. A method of programming a memory cell having a ... |
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Invention
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Parameter enhanced sequential programming method.
A method of programming a memory cell having a... |
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Invention
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Erase operation for non-volatile memory cell. In one example, a method for erasing a non-volatile... |
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Invention
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Dual read mode non-volatile memory semiconductor device. A method of operating a semiconductor de... |
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Invention
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Self-aligned method of forming eeprom cells. An EEPROM cell with junction, source and drain regio... |
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Invention
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Algorithms for updating software code in flash memory during system operation. n-1n-1nn-1n-1n-1nn... |
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Invention
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Self-aligned method of forming eeprom cells.
An EEPROM cell with junction, source and drain regi... |
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Invention
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Pumping controller for a plurality of charge pump units. In one example, a system comprises a plu... |
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Invention
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Temperature compensation for analog memory cells in a neural network. In one example, a method co... |
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Invention
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Bias circuit for non-volatile memory array in a neural network. In one example, a system comprise... |
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Invention
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Programming method for non-volatile memory cells. A method of programming a memory cell to a targ... |
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Invention
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Dual read mode non-volatile memory semiconductor device.
A method of operating a semiconductor d... |
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Invention
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Sense amplifier for a flash memory system. In one example, a method comprises generating a first ... |
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Invention
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High voltage schottky diode and charge pump. A diode comprises a semiconductor substrate, an n-we... |
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Invention
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Program refresh for non-volatile memory cells. A programming method for a semiconductor device th... |
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Invention
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Tracking memory cells for current leakage compensation in non-volatile memory array. A method and... |
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Invention
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Multi-chiplet semiconductor device with redundant data line. A semiconductor device includes an i... |
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Invention
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Erase operation for non-volatile memory cell.
In one example, a method for erasing a non-volatil... |
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Invention
|
High voltage schottky diode and charge pump.
A diode comprises a semiconductor substrate, an n-w... |
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Invention
|
Sense amplifier for a flash memory system.
In one example, a method comprises generating a first... |
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Invention
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Multi-chiplet semiconductor device with redundant data line.
A semiconductor device includes an ... |
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Invention
|
Tracking memory cells for current leakage compensation in non-volatile memory array.
A method an... |
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Invention
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Program refresh for non-volatile memory cells.
A programming method for a semiconductor device t... |
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2024
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Invention
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Bias circuit for non-volatile memory array in a neural network.
In one example, a system compris... |
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Invention
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Temperature compensation for analog memory cells in a neural network.
In one example, a method c... |
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Invention
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Weight scaling for neural network. In one example, a system comprises an array of non-volatile me... |
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Invention
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Configurable input and output blocks for vector-by-matrix multiplication array. In one example, a... |
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Invention
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Algorithms for updating software code in flash memory during system operation.
In one example, a... |
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Invention
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Weight scaling for neural network.
In one example, a system comprises an array of non-volatile m... |
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Invention
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Configurable input and output blocks for vector-by-matrix multiplication array.
In one example, ... |
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2003
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P/S
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Computer hardware, peripherals and integrated circuit components for digital, networking, wireles... |
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1998
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P/S
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Embedded controllers. Instructional manuals. |
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1991
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P/S
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computer hardware, peripherals, integrated circuit components and related documentation; namely, ... |
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1990
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P/S
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integrated circuit memories and related instruction manuals sold together as a unit |
