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2025
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Invention
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Vector-by-matrix mutiplication array comprising control gate lines perpendicular to word lines.
... |
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Invention
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Grouping and error correction for non-volatile memory cells.
Numerous examples are disclosed of ... |
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2024
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Invention
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Pumping controller for a plurality of charge pump units.
In one example, a system comprises a pl... |
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Invention
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Programming of analog non-volatile memory cell in neural network.
In one example, a method compr... |
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Invention
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Verifying or reading a cell in an analog neural memory in a deep learning artificial neural netwo... |
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Invention
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Sequential erase for tuning the program state of non-volatile memory cells. A method and device f... |
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Invention
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Sequential erase for tuning the program state of non-volatile memory cells.
A method and device ... |
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Invention
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Non-volatile memory cell with ono compound insulation layer between floating and control gates an... |
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Invention
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Vertically oriented split gate non-volatile memory cells, and method of making same. A semiconduc... |
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Invention
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Coarse and fine programming of non-volatile memory cells. A method of programming non-volatile me... |
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Invention
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Coarse and fine programming of non-volatile memory cells.
A method of programming non-volatile m... |
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Invention
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Vertically oriented split gate non-volatile memory cells, and method of making same.
A semicondu... |
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Invention
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Neural network classifier using array of three-gate non-volatile memory cells. A neural network d... |
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Invention
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Semiconductor device with non-planar mosfet device die and planar mosfet device die. A semiconduc... |
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Invention
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Semiconductor device with non-planar mosfet device die and planar mosfet device die.
A semicondu... |
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Invention
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Interface circuit for stack comprising a plurality of vector-by-matrix multiplication arrays. In ... |
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Invention
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Output block for vector-by-matrix multiplication array. In one example, a system comprises: a vec... |
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Invention
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Interface circuit for stack comprising a plurality of vector-by-matrix multiplication arrays.
In... |
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Invention
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Output block for vector-by-matrix multiplication array.
In one example, a system comprises: a ve... |
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Invention
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Method of making memory cells, transistor devices and logic devices on silicon-on-insulator subst... |
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Invention
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Program speed compensation for non-volatile memory cells. A method of programming memory cells th... |
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Invention
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Accelerated programming of four-gate, split-gate flash memory cells. A method of programming a me... |
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Invention
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Accelerated programming of four gate, split-gate flash memory cells.
A method of programming a m... |
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Invention
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Program speed compensation for non-volatile memory cells.
A method of programming memory cells t... |
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Invention
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Low voltage resistive random access memory (rram) cell and methods of formation. The disclosed me... |
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Invention
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Sigma-delta analog-to-digital converter to generate digital output from vector-by-matrix multipli... |
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Invention
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Low voltage resistive random access memory (rram) cells and method of formation.
A memory device... |
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Invention
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Programmable logic block comprising flash memory array to store configuration data for programmab... |
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Invention
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Erasing of a word or a page of non-volatile memory cells in an analog neural memory system.
In o... |
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2023
|
Invention
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Programming of a selected non-volatile memory cell by changing programming pulse characteristics.... |
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Invention
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Output circuit for a vector-by-matrix multiplication array. In one example, a system comprises a ... |
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Invention
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Input block for vector-by-matrix multiplication array. Numerous examples are disclosed of input b... |
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Invention
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Output circuit for a vector-by-matrix multiplication array.
In one example, a system comprises a... |
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Invention
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Input block for vector-by-matrix multiplication array.
Numerous examples are disclosed of input ... |
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Invention
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System and method for implementing temperature compensation in a memory device. A method of opera... |
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Invention
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Memory device formed on silicon-on-insulator substrate, and method of making same. A memory devic... |
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Invention
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Memory device formed on silicon-on-insulator substrate, and method of making same.
A memory devi... |
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Invention
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Analog computation-in-memory engine and digital computation-in-memory engine to perform operation... |
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Invention
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Masking sparse inputs and outputs in neural network array. Numerous examples are disclosed of a m... |
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Invention
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Masking sparse inputs and outputs in neural network array.
Numerous examples are disclosed of a ... |
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Invention
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Row decoder and row address scheme in a memory system. mmnprtruvmuunvvptt. |
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Invention
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Row decoder and row address scheme in a memory system. t. |
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Invention
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Split array architecture for analog neural memory in a deep learning artificial neural network. N... |
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Invention
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Output block for a vector-by-matrix multiplication array of non-volatile memory cells. A system c... |
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Invention
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Output block for array of non-volatile memory cells. In one example, a system comprises an array ... |
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2003
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G/S
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Computer hardware, peripherals and integrated circuit components for digital, networking, wireles... |
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1998
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G/S
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Embedded controllers. Instructional manuals. |
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1991
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G/S
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computer hardware, peripherals, integrated circuit components and related documentation; namely, ... |
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1990
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G/S
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integrated circuit memories and related instruction manuals sold together as a unit |
