Intel Corporation
États‑Unis d’Amérique
Nouveaux brevets et marques déposées la semaine dernière
Dernière mise à jour : 2026-07-26
Sommaire
Brevets |
Marques |
|
![]() |
21 | 0 |
![]() |
0 | 0 |
![]() |
5 | 0 |
![]() |
0 |
Commandez votre montre hebdomadaire Intel Corporation
1
Viewing 1 - 26 of 26
marques
brevets
| # | ID | Juridiction | Title |
|---|---|---|---|
| 1 | 19142756 |
|
REDUCED-CAPABILITY UE CONFIGURED FOR DL PRS AND SRS COLLISION HANDLING |
| 2 | 19140345 |
|
ENHANCED PROPAGATION CONDITION-AWARE MODEL CONFIGURATION IN AUTOENCODER-BASED CHANNEL STATE INFORMATION FEEDBACK FOR WIRELESS COMMUNICATIONS |
| 3 | 19572272 |
|
SINGLE TRP AND MULTIPLE TRP DYNAMIC SWITCHING FOR SINGLE DCI BASED PUSCH TRANSMISSIONS |
| 4 | 19569674 |
|
METHODS AND APPARATUS TO APPLY LOAD TO A SOCKETED INTEGRATED CIRCUIT PACKAGE INDEPENDENT OF A HEATSINK LOADING MECHANISM |
| 5 | 19411794 |
|
DESIGN OF FAKE BLOCK ACKNOWLEDGEMENT REQUEST ALTERNATIVE TO PROTECTED BLOCK ACKNOWLEDGMENT AGREEMENT CAPABLE |
| 6 | 19434280 |
|
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC |
| 7 | 19035076 |
|
THERMAL RELEASE LAYER FOR CARRIER ASSISTED BOTTOM-UP PLATING |
| 8 | 19570981 |
|
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING PRE-SPACER DEPOSITION CUT GATES WITH ETCH BACK PROCESS |
| 9 | 19451013 |
|
MEMORY CONTROLLER MANAGEMENT TECHNIQUES |
| 10 | CN2025117453 |
|
NEURO-SYMBOLIC KINEMATICS FOR INTELLIGENT AGENT |
| 11 | CN2025119979 |
|
THREE-DIMENSIONAL OBJECT RECONSTRUCTION VIA PHYSICS-AUGMENTED NEURAL RENDERING |
| 12 | CN2025102900 |
|
SLIDING-WINDOW QUANTIZATION OF PRETRAINED LARGE LANGUAGE MODEL |
| 13 | 19400106 |
|
ABSTRACTION LIBRARY TO ENABLE SCALABLE DISTRIBUTED MACHINE LEARNING |
| 14 | 19449629 |
|
DISTRIBUTED RADIOHEAD SYSTEM |
| 15 | 19133489 |
|
APPARATUS, SYSTEM, AND METHOD OF NON-COLLOCATED MULTI-LINK-DEVICE (MLD) INDICATION |
| 16 | 19573030 |
|
METHOD TO IMPLEMENT HALF WIDTH MODES IN DRAM AND DOUBLING OF BANK RESOURCES |
| 17 | 19540367 |
|
SCALING FACTOR DESIGN FOR LAYER 1 REFERENCE SIGNAL RECEIVED POWER (L1-RSRP) MEASUREMENT PERIOD |
| 18 | 19382721 |
|
KERNEL SOURCE ADAPTATION FOR EXECUTION ON A GRAPHICS PROCESSING UNIT |
| 19 | 19142263 |
|
Apparatuses, Devices, Methods and Computer Programs for a Worker Node and an Edge Server |
| 20 | 19436426 |
|
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE |
| 21 | 19446225 |
|
METHOD AND SYSTEM OF AUDIO FALSE KEYPHRASE REJECTION USING SPEAKER RECOGNITION |
| 22 | 19434478 |
|
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION |
| 23 | 19576978 |
|
FRAME RESOLUTION SCALING WITH REGION BLURRING |
| 24 | 19570741 |
|
SPACER SELF-ALIGNED VIA STRUCTURES USING ASSISTED GRATING FOR GATE CONTACT OR TRENCH CONTACT |
| 25 | CN2025103772 |
|
ELASTIC ADAPTER FOR FINE-TUNING NEURAL NETWORK |
| 26 | CN2025117754 |
|
SPATIAL-TEMPORAL GRAPH-TO-GRID LEARNER |
1



