Abrégé

During a first phase, a bit line voltage is transmitted to a first input end of a sense amplifier and a reference voltage is transmitted to a second input end of the sense amplifier, so that the sense amplifier outputs data based on a first voltage difference between its first and second input ends for providing a first data signal. During a second phase, the reference voltage is transmitted to the first input end of the sense amplifier and the bit line voltage is transmitted to the second input end of the sense amplifier, so that the sense amplifier outputs data based on a second voltage difference between its first and second input ends for providing a second data signal. During a third phase, a sense margin detecting signal is provided based on the first data signal and the second data signal.

Classes IPC  ?

• G11C 7/08 - Leur commande
• G11C 7/06 - Amplificateurs de lectureCircuits associés

Abrégé

A semiconductor structure includes a substrate, a top metal layer disposed on the substrate, a top dielectric layer disposed on the substrate and the top metal layer, at least one opening disposed in the top dielectric layer, and an aluminum layer conformally deposited on the top dielectric layer and in the at least one opening. When viewed from above, the at least one opening has a regular n-gon pattern (n is greater than or equal to 6), circular pattern or oval pattern.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer; and a metal layer is filled in the compensation groove.

Classes IPC  ?

• H10W 20/00 -
• H10P 50/00 -
• H10P 76/20 -
• H10W 20/42 -
• H10W 20/43 -

Abrégé

The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer; and a metal layer is filled in the compensation groove.

Classes IPC  ?

• H10W 20/00 -
• H10P 50/00 -
• H10P 76/20 -
• H10W 20/42 -
• H10W 20/43 -

Abrégé

A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

Classes IPC  ?

• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement

Abrégé

An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

Classes IPC  ?

• H10W 20/40 -
• H10D 1/20 - Inducteurs
• H10D 1/66 - Condensateurs à conducteur-isolant-semi-conducteur, p. ex. condensateurs MOS

Abrégé

A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

Classes IPC  ?

• H10N 50/01 - Fabrication ou traitement
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/80 - Détails de structure

Abrégé

A testing method and a testing device for an electronic circuit are provided. The testing method includes the following steps. A test voltage signal is provided to a connection pad of the electronic circuit. A voltage regulating circuit of the electronic circuit is controlled to generate a reference voltage and provide the reference voltage to the connection pad. A voltage value of one of the test voltage signal and the reference voltage is adjusted, and a test current flowing through the connection pad is received. A measured voltage value of the reference voltage is determined according to a change in a current direction of the test current.

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

Abrégé

An optical metasurface structure includes a substrate, a first metal rail structure, a second metal rail structure, a diffusion barrier layer, a high dielectric constant dielectric layer, and a liquid crystal material. The first metal rail structure and the second metal rail structure are disposed above the substrate. The diffusion barrier layer is disposed on the first metal rail structure and the second metal rail structure. The high dielectric constant dielectric layer is disposed on the diffusion barrier layer. The liquid crystal material is disposed above the substrate and at least a part of the liquid crystal material is located between the first metal rail structure and the second metal rail structure in a horizontal direction. The diffusion barrier layer has a first thickness, a portion of the high dielectric constant dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

Classes IPC  ?

• G02F 1/1343 - Électrodes

Abrégé

The invention provides a capacitor structure, which comprises a first capacitor structure located on a substrate, wherein the first capacitor structure comprises a plurality of lower electrode layers, wherein each lower electrode layer is arranged in the same direction and stacked with each other along a height direction (Z direction), and a second capacitor structure located on the first capacitor structure, wherein the second capacitor structure comprises a plurality of upper electrode layers, wherein some upper electrode layers are arranged in a first direction (X direction), and the other upper electrode layers are arranged in a second direction (Y direction), and the first direction and the second direction are perpendicular to each other.

Classes IPC  ?

• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H10D 1/62 - Condensateurs ayant des barrières de potentiel

Abrégé

A delay circuit includes a delay chain and a calibration circuit. The delay chain includes a plurality of delay cells coupled in series. The delay chain provides a delay amount, and delays a clock signal by the delay amount to generate a delayed clock signal. The calibration circuit is coupled to the delay chain, counts the number of pulses of the delayed clock signal during a preset time period to generate a count value, and generates calibration information according to the count value. The delay chain adjusts the delay amount by adjusting a transmission delay of at least one of the delay cells according to the calibration information.

Classes IPC  ?

• H03M 1/10 - Calibrage ou tests
• H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
• H03M 1/12 - Convertisseurs analogiques/numériques

Abrégé

A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first source electrode adjacent to one side of the gate structure, forming a second source electrode adjacent to another side of the gate structure, forming a first contact plug on the first source electrode, forming a second contact plug on the second source electrode, forming a field plate on the first contact plug and the second contact plug, and forming a drain electrode on a backside of the substrate.

Classes IPC  ?

• H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
• H10D 30/01 - Fabrication ou traitement
• H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
• H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel

Abrégé

An imprint method including the following steps is provided. Providing a first master mold including a first protruding pattern and a second protruding pattern. Providing a second master mold including a third protruding pattern. Performing a first imprint step on a first photoresist layer formed on a replica mold by using the first master mold. Performing a first etching step on the replica mold to form a first recessed portion and a second recessed portion. Performing a second imprint step on a second photoresist layer formed on the replica mold by using the second master mold. Performing a second etching step on the replica mold to form a third recessed portion overlapping the first recessed portion. Performing a third imprint step on a third photoresist layer formed on a substrate by using the replica mold. Performing a third etching step on the substrate to form a desired pattern.

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• B29C 33/38 - Moules ou noyauxLeurs détails ou accessoires caractérisés par la matière ou le procédé de fabrication
• B29C 43/02 - Moulage par pressage, c.-à-d. en appliquant une pression externe pour faire couler la matière à moulerAppareils à cet effet pour la fabrication d'objets de longueur définie, c.-à-d. d'objets séparés
• B29C 43/14 - Moulage par pressage, c.-à-d. en appliquant une pression externe pour faire couler la matière à moulerAppareils à cet effet pour la fabrication d'objets de longueur définie, c.-à-d. d'objets séparés en plusieurs étapes

Abrégé

The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

Classes IPC  ?

• H10D 84/01 - Fabrication ou traitement
• H10D 64/01 - Fabrication ou traitement
• H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
• H10W 20/00 -
• H10W 20/43 -

Abrégé

A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug in the ILD layer and electrically connected to the active device; and a second contact plug in the ILD layer and the insulating layer, wherein a top surface of the second contact plug is higher than a top surface of the ILD layer.

Classes IPC  ?

• H10W 20/00 -
• H10D 30/67 - Transistors à couche mince [TFT]
• H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
• H10P 90/00 -
• H10W 10/10 -

Abrégé

A semiconductor device includes a substrate having an active area, a first gate line extending along a first direction on the active area, a first gate line extension adjacent to the first gate line and outside the active area, a second gate line extending along the first direction on the active area and adjacent to the first gate line, and a second gate line extension adjacent to the second gate line and outside the active area. Preferably, the active area includes a first indentation and a second indentation, in which the first gate line extension overlaps the first indentation and the second gate line extension overlaps the first indentation.

Classes IPC  ?

• H10D 30/67 - Transistors à couche mince [TFT]
• H03F 3/16 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs avec dispositifs à effet de champ
• H10D 87/00 - Dispositifs intégrés comprenant à la fois des composants en vrac et des composants SOI ou SOS sur le même substrat

Abrégé

A semiconductor device includes a substrate, a dielectric layer, a gate structure, a lightly doped region, a first spacer and a heavily doped region. The dielectric layer is disposed on the substrate and includes a first section with a first thickness and a second section with a second thickness, the first thickness is greater than the second thickness, and the second section surrounds the first section. The gate structure covers a portion of the first section. The lightly doped region is formed in the substrate and adjacent to the gate structure. The first spacer is disposed on sidewalls of the gate structure and covers another portion of the first section. The heavily doped region is disposed in the lightly doped region and adjacent to the second section.

Classes IPC  ?

• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 30/01 - Fabrication ou traitement
• H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
• H10D 64/01 - Fabrication ou traitement

Abrégé

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, wherein the plurality of gate structures comprises at least one first gate structure and at least one second gate structure, at least one first metal layer located on the first gate structure, wherein the first metal layer is electrically connected with the first gate structure, and at least one second metal layer bridging the second gate structure and another one of the plurality of gate structures, wherein a top surface of the first gate structure is lower than a top surface of the second gate structure.

Classes IPC  ?

• H10D 84/01 - Fabrication ou traitement
• H10D 64/01 - Fabrication ou traitement
• H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
• H10W 20/00 -
• H10W 20/43 -

Abrégé

The present disclosure relates to a semiconductor device and a method of fabricating the same including a substrate, a first gate structure, two first source/drain structures, and an air barrier layer. The substrate includes at least one shallow trench isolation disposed therein. The first gate structure is disposed on the substrate. Two first source/drain structures are disposed in the substrate, at two sides of the first gate structure, and a side of each of the two first source/drain structures is adjacent to the at least one shallow trench isolation. The air gap barrier layer is disposed between the substrate and each of the two first source/drain structures, wherein the air gap barrier layer includes a bottom surface and two sidewalls each extending in three different directions.

Classes IPC  ?

• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/00 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel
• H10D 84/01 - Fabrication ou traitement
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement

Abrégé

A fabricating method for a transistor with a fin structure and a nanosheet begins by providing a first fin structure with a dummy gate, two spacers, a first embed epitaxial layer, and a second embed epitaxial layer. Subsequently, a first epitaxial layer and a second epitaxial layer are formed to cover the fin structure and the dummy gate. Two first mask layers are then formed. Parts of the first and the second epitaxial layers are removed using the two first mask layers as a mask to expose the dummy gate and a nanosheet is formed from the remaining second epitaxial layer. Later, the dummy gate is replaced by a first gate portion, and a second gate portion is formed to encapsulate the nanosheet. Finally, a metal gate is formed between the first gate portion and the second gate portion.

Classes IPC  ?

• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
• H10D 30/67 - Transistors à couche mince [TFT]
• H10D 64/01 - Fabrication ou traitement

Abrégé

An RRAM string includes a substrate and numerous RRAM cells disposed on the substrate in a memory region. The RRAM cells include at least two last RRAM cells and one middle RRAM cell. Each RRAM cell includes a bottom electrode, a resistive switching layer, a top electrode, and a cap layer stacked from bottom to top. A first spacer contacts a first sidewall of the bottom electrode and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and a third sidewall of the top electrode. Furthermore, a dielectric layer covers the second spacer in the memory region. The dielectric layer at an outer side of the last RRAM cells includes a slope. An end of the slope contacts the second spacer located on a surface of the substrate.

Classes IPC  ?

• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

Abrégé

A semiconductor device includes a substrate, a plurality of gate stack structures, a doped ring, a guard ring, and a plurality of conductive lines. The substrate includes a first region and a second region. The second region surrounds the first region. The gate stack structures are located in the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The guard ring is located on the substrate in the second region and surrounds the first region. The conductive lines are connected to the doped ring and the gate stack structures.

Classes IPC  ?

• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
• H10W 42/60 -

Abrégé

A method for forming a semiconductor structure is disclosed. A first dielectric layer is formed on a substrate. An etch stop layer is formed on the first dielectric layer. A second dielectric layer is formed on the etch stop layer. A first conductor and a second conductor are formed in the second dielectric layer. An air gap is formed in the second dielectric layer and between the first conductor and the second conductor. A first low-polarity dielectric layer is formed on a sidewall surface of the second dielectric layer within the air gap.

Classes IPC  ?

• H10W 20/46 -
• H10W 20/00 -
• H10W 20/41 -

Abrégé

A nanoprobe manufacturing machine and a method of manufacturing nanoprobe are provide. The nanoprobe manufacturing machine comprising a step motor held by a hold stage and is removable in an upward direction and in a downward direction; a positive electrode and a negative electrode respectively fixed on the step monitor; a first metal probe fixed and electrically connected to the positive electrode and a second metal probe fixed and electrically connected to the negative electrode; and a container containing an electrolyte, wherein the step motor carrying the first metal probe and the second metal probe into the electrolyte to form a nanoprobe from the first metal probe by a redox reaction in the electrolyte.

Classes IPC  ?

• G01R 1/067 - Sondes de mesure

Abrégé

A method for fabricating a semiconductor device includes the steps of first providing a substrate having through-silicon vias (TSVs) therein, forming an inorganic layer on the substrate, forming an organic layer on the inorganic layer, and then bonding dies having different functionalities on the organic layer. Preferably, the dies include a radio-frequency integrated circuit (RFIC) die, a power amplifier (PA) die, and/or a high electron mobility transistor (HEMT) die.

Classes IPC  ?

• H10D 84/01 - Fabrication ou traitement
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT

Abrégé

A semiconductor device includes an inter-metal dielectric (IMD) layer on a substrate, a metal interconnection in the IMD layer, a bottom electrode on the metal interconnection, and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a sidewall of the MTJ comprises a first slope and a second slope. Preferably, the MTJ further includes a pinned layer on the bottom electrode, in which a first angle included by a bottom surface of the bottom electrode and the sidewall of the MTJ is equal to a second angle included by a bottom surface of the pinned layer and the sidewall of the MTJ.

Classes IPC  ?

• H10N 50/01 - Fabrication ou traitement
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/80 - Détails de structure

Abrégé

A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; and a trench on an upper portion of the conductive via and in the first dielectric layer. The trench includes a first sidewall formed by the conductive via and a bottom surface formed by the conductive via and the first dielectric layer. A resistive switching structure is formed in the trench and contacts the first sidewall. The resistive switching structure includes a top electrode layer, a resistive switching material layer, and a bottom electrode layer disposed between the resistive switching material layer and the conductive via.

Classes IPC  ?

• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

Abrégé

An operating method and an operation assistance system for a robot arm are provided. The operating method for the robot arm includes the following steps. A plurality of moving detection values of the robot arm are obtained. At least one moving time length of at least one movement of the robot arm is obtained. A plurality of operation values are obtained. The filtering noises are filtered from the moving detection values via a clustering algorithm. A plurality of moving representative values of the moving detection values are obtained. A health status of the robot arm is obtained according to the moving representative values, the moving time length, and the operation values, via an NN algorithm.

Classes IPC  ?

• B25J 9/16 - Commandes à programme

Abrégé

A method for fabricating semiconductor device includes first bonding a first wafer to a carrier, performing a first grinding process on a backside of the first wafer, performing a first trimming process on a sidewall of the first wafer, forming a first protective layer on the sidewall of the first wafer, forming a first bonding pad on the backside of the first wafer, bonding a second wafer to the first bonding pad, performing a second grinding process on a backside of the second wafer, performing a second trimming process on a sidewall of the second wafer, forming a second protective layer on the sidewalls of the first wafer and the second wafer, and forming a second bonding pad on the backside of the second wafer.

Classes IPC  ?

• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

A radio-frequency (RF) device includes a main device on a substrate, a first port extending along a first direction adjacent to a first side of the main device, a second port extending along the first direction adjacent to a second side of the main device, a first shield structure adjacent to a third side of the main device, a second shield structure adjacent to a fourth side of the main device, a first connecting structure extending along a second direction to connect the first port and the main device, and a second connecting structure extending along the second direction to connect the second port and the main device.

Classes IPC  ?

• H10W 42/20 -
• H10W 20/41 -
• H10W 44/20 -

Abrégé

A circuit layout hotspot detection system includes a lithography simulator, an object detector, and a cross-model feature fusion module. The lithography simulator is used to receive circuit layout data to generate a layout deformation feature matrix. The object detector is coupled to the lithography simulator for generating a plurality of layout pattern feature matrices based on the circuit layout data. The cross-model feature fusion module is coupled to the lithography simulator and the object detector for generating potential abnormal hotspot data corresponding to the circuit layout data based on the plurality of layout pattern feature matrices and the layout deformation feature matrix. The circuit layout data includes at least one circuit layout layer. The potential abnormal hotspot data includes a location and a size of at least one potential abnormal hotspot.

Classes IPC  ?

• G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]

Abrégé

An optical metasurface structure includes a substrate, metal rail structures, and a liquid crystal material. The substrate includes a first region and a second region. The metal rail structures and the liquid crystal material are disposed above the first region. At least a part of the liquid crystal material is located between the metal rail structures adjacent to each other in a horizontal direction, and a top width of one of the metal rail structures is less than a bottom width of the one of the metal rail structures.

Classes IPC  ?

• G02F 1/1345 - Conducteurs connectant les électrodes aux bornes de la cellule
• B82Y 20/00 - Nano-optique, p. ex. optique quantique ou cristaux photoniques
• G02F 1/1343 - Électrodes

Abrégé

A capacity structure includes a semiconductor substrate, a first patterned conductive layer, at least one first contact plug and at least one second contact plug. The semiconductor substrate includes a first-conductivity well region and a second-conductivity well region adjacent to each other. The first patterned conductive layer is disposed on the semiconductor substrate and includes a first electrode pattern and a second electrode pattern separated from each other and forming at least one first parasitic capacitance there between. The first contact plug electrically connects the first electrode pattern and the first-conductivity well region. The second contact plug electrically connects the second electrode pattern and the second-conductivity well region, so as to form at least one second parasitic capacitance between the first-conductivity well region and the second-conductivity well region.

Classes IPC  ?

• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
• H10D 1/00 - Résistances, Condensateurs, Inducteurs

Abrégé

A memory component includes two memory units, a first gate and a doped region. The two memory units are disposed on a substrate. The first gate is disposed between the two memory units, and the first gate includes an embedded portion embedded in the substrate. The doped region is disposed in the substrate and surrounds the embedded portion.

Classes IPC  ?

• H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
• H10D 30/68 - Transistors IGFET à grille flottante

Abrégé

A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.

Classes IPC  ?

• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 64/01 - Fabrication ou traitement
• H10D 84/01 - Fabrication ou traitement
• H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement

Abrégé

Provided is a flash memory including a substrate including a recess, first, second and third dielectric layers, a floating gate, source and drain regions, an erase gate, and a select gate. The first dielectric layer is disposed in the recess. The floating gate fills the recess and the first dielectric layer located between the floating gate and the substrate. The second dielectric layer covers a top surface of the floating gate away from the substrate. The source region is disposed in the substrate at one side of the floating gate. The drain region is disposed in the substrate at another of the floating gate. The erase gate is disposed on the second dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate and separated from the second dielectric layer.

Classes IPC  ?

• H10B 41/23 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés
• H10D 30/68 - Transistors IGFET à grille flottante

Abrégé

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

Classes IPC  ?

• H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
• H10D 30/01 - Fabrication ou traitement
• H10P 14/694 -

Abrégé

A semiconductor structure includes a semiconductor substrate; a source structure in the semiconductor substrate, wherein the source structure includes a source drift region and a heavily doped source region within the source drift region; a recessed trench disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at a bottom of the recessed trench, wherein the drain structure includes a drain drift region, a heavily doped drain region disposed within the drain drift region, and a carbon-doped surface layer on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate between the source structure and the drain structure.

Classes IPC  ?

• H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
• H10D 30/01 - Fabrication ou traitement
• H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]

Abrégé

A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric ((IMD) layer on a substrate and a metal interconnection in the IMD layer, forming a dielectric layer on the IMD layer, patterning the dielectric layer to form an opening, forming a bonding pad in the opening, and then forming a passivation layer on the bonding pad. Preferably, a top surface of the bonding pad includes a first curve and a sidewall of the bonding pad includes a second curve.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

Classes IPC  ?

• H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
• H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
• H10P 30/20 -
• H10W 10/00 -
• H10W 10/17 -

Abrégé

Semiconductor device and method of fabricating the same, includes a substrate, a first dielectric layer and a second dielectric layer, a bonding interface layer, and a plurality of dummy vias. The first dielectric layer and the second dielectric layer are stacked in sequence on the substrate. The bonding interface layer is disposed between the first dielectric layer and the second dielectric layer, wherein the bonding interface layer includes a first interface layer and a second interface layer stacked in sequence. The plurality of dummy vias are disposed within one of the first dielectric layer and the second dielectric layer, being located at only one side of the bonding interface layer in a vertical direction of the substrate.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H10D 88/00 - Dispositifs intégrés tridimensionnels [3D]

Abrégé

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 35/01 - Fabrication ou traitement
• H10N 50/80 - Détails de structure
• H10W 10/00 -
• H10W 10/10 -
• H10W 20/00 -

Abrégé

A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10W 20/00 -
• H10W 20/41 -
• H10W 20/42 -

Abrégé

Provided are a transistor structure and a manufacturing method thereof. The transistor structure includes a gate dielectric layer, a gate disposed on the gate dielectric layer, a spacer structure located on the gate dielectric layer and disposed on the sidewall of the gate, first, second and third doped regions, and a metal silicide layer. The first doped regions are disposed in the substrate on two sides of the gate. The second doped regions are disposed in the first doped regions, respectively. The third doped regions is disposed in the second doped regions, respectively. The metal silicide layer is disposed at the surface of the third doped regions. In the channel direction, the first doped regions extend below the gate to partially overlap with the gate, the second doped regions extends below the spacer structure, and the metal silicide layer does not extend below the gate.

Classes IPC  ?

• H10D 30/67 - Transistors à couche mince [TFT]
• H10D 30/01 - Fabrication ou traitement
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/60 - Distribution ou concentrations d’impuretés
• H10D 64/01 - Fabrication ou traitement
• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]

Abrégé

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
• G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs

Abrégé

A sensing device and an operation method thereof are provided. The sensing device includes a Passive Infrared (PIR) sensor, a radiation emitter and a controller. The PIR sensor includes a plurality sensing elements. The PIR sensor is used to detect a heat source. The controller is connected to the radiation emitter and the PIR sensor. The controller enables the radiation emitter to emit a radiation light to the PIR sensor when the sensing elements reach a voltage balance for a predetermined time and then disables the radiation emitter.

Classes IPC  ?

• G01J 5/00 - Pyrométrie des radiations, p. ex. thermométrie infrarouge ou optique

Abrégé

A method for generating an OPC pattern is provided. A layout pattern including a first unit pattern in an edge region and second unit patterns in a central region. A first OPC sub-pattern corresponding to the first unit pattern and the second unit patterns in an edge portion of the central region adjacent to the edge region and a second OPC sub-pattern corresponding to the second unit pattern are built. A mark covering the edge region and the edge portion is formed. The edge region is identified, and a first OPC pattern is obtained according to the first OPC sub-pattern. The central region except the edge portion is identified according to the mark, and a second OPC pattern is obtained according to the second OPC sub-pattern. The first OPC pattern and the second OPC pattern are combined to obtain an OPC pattern of the layout pattern.

Classes IPC  ?

• G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet

Abrégé

A semiconductor device includes a multi-die package, a testkey region, and a scribe line. The multi-die package includes a plurality of dies each in a regular polygon shape, wherein each of the plurality of dies includes a number of sides, and the number is a multiplier of four and is greater than four. The testkey region is disposed between the plurality of dies and adjacent to one side of each of the plurality of dies. The testkey region is in an equilateral polygon shape. The scribe line surrounds a periphery of each of the plurality of dies and a periphery of the testkey region.

Classes IPC  ?

• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme

Abrégé

A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

Classes IPC  ?

• H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
• H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
• H10W 90/00 -

Abrégé

The present disclosure provides a semiconductor device and a method for forming the same. The semiconductor device includes a substrate including an active region defining by an isolation trench, an isolation structure disposed in the isolation trench and including a recess, and a thin film resistor structure disposed over the recess.

Classes IPC  ?

• H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
• H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
• H10D 84/01 - Fabrication ou traitement

Abrégé

A semiconductor device includes a substrate having a non-planar device region and a planar device region, a first isolation structure in the substrate of the planar device region, a first gate structure on the first isolation structure, a first epitaxial layer adjacent to the first gate structure, a second isolation structure in the substrate of the non-planar device region, a second gate structure on the second isolation structure, and a second epitaxial layer adjacent to the second gate structure. Preferably, the first gate structure includes a first metal gate and the second gate structure includes a second metal gate.

Classes IPC  ?

• H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
• H10D 84/01 - Fabrication ou traitement

Abrégé

A semiconductor structure with single diffusion break (SDB) is provided in the present invention, including a substrate with a first region and a second region defined thereon, the first region and the second region are adjacent to each other and have respective fins, a STI on the substrate and surrounding the fins, multiple gates crossing over the fins, a dummy gate on the STI between the first region and the second region and spaced apart with the gates, at least one conductive pattern on the dummy gate and connected therewith, and at least one dummy via on the at least one conductive pattern and connected therewith.

Classes IPC  ?

• H10D 64/01 - Fabrication ou traitement
• H01L 21/762 - Régions diélectriques
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H10D 30/01 - Fabrication ou traitement
• H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]

Abrégé

An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

Classes IPC  ?

• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
• H10D 30/01 - Fabrication ou traitement
• H10P 30/20 -
• H10P 95/90 -

Abrégé

An LCM structure includes a composite dielectric layer. The composite dielectric layer includes a nitrogen-doped silicon carbide layer, a silicon oxide layer and a silicon nitride layer stacked from bottom to top. A first metal rail includes a pedestal and a metal strip. The first metal rail embedded in the silicon oxide layer and the nitrogen-doped silicon carbide layer is defined as the pedestal, and the first metal rail embedded in the silicon nitride layer and protruding on the silicon nitride layer is defined as the metal strip. The width of the pedestal in the silicon oxide layer continuously and gradually increases along a direction toward the nitrogen-doped silicon carbide layer. A second metal rail is disposed at one side of the first metal rail. A gap is disposed between the first metal rail and the second metal rail. Nemours liquid crystals fill the gap.

Classes IPC  ?

• G02F 1/29 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de la position ou de la direction des rayons lumineux, c.-à-d. déflexion
• H10F 77/40 - Éléments ou dispositions optiques

Abrégé

A LDMOS is provided in the present invention, including multiple fins spaced apart, wherein each fin has a recess region, a shallow trench isolation in those recess regions forms a thick oxide layer, a gate crosses over those fins, wherein the thick oxide layer is close to one side of the gate and partially overlaps the gate, and a source and a drain respectively at two sides of the gate in each fin, wherein the thick oxide layer extends outside the gate to the drains.

Classes IPC  ?

• H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
• H10D 30/01 - Fabrication ou traitement
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs

Abrégé

The invention provides a layout pattern of static random access memory (SRAM) cell, which at least comprises an SRAM cell in a region, wherein the SRAM cell comprises a plurality of fin structures on a substrate, wherein a plurality of gate structures span the plurality of fin structures so as to form a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1A, a second pass gate transistor PG1B, a third pass gate transistor PG2A and a pass gate transistor PG2B are located on the substrate, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2 are aligned with each other in a Y direction when viewed from a top view.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

A photomask module includes a first photomask and a second photomask. The first photomask includes a main circuit pattern. The second photomask includes a pad pattern, and the pad pattern includes a pad body pattern portion and an extension pattern portion. The extension pattern portion extends outward from the pad body pattern portion. When the first photomask and the second photomask overlap with each other, the extension pattern portion is at least partially surrounded by the main circuit pattern.

Classes IPC  ?

• G03F 1/26 - Masques à décalage de phase [PSM phase shift mask]Substrats pour PSMLeur préparation
• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

The invention provides a static random access memory structure, which comprises a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected with the silicon substrate and protruding from the shallow trench isolation, a first gate structure spanning the first fin structure and parts of the shallow trench isolation, so that the first gate structure covers a top surface and a part of sidewalls of the first fin structure, and forms a pass gate transistor (PG). And a protruding part located directly below the first gate structure and on the shallow trench isolation, the protruding part covers part of the surface of at least one sidewall of the first fin structure, and a top surface of the protruding part is higher than a top surface of the shallow trench isolation.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
• H10D 84/01 - Fabrication ou traitement
• H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement

Abrégé

A method for fabricating a magnetoresistive random access memory (MRAM) device includes first providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, using a first patterned mask to remove the first IMD layer for forming a first via opening on the MRAM region and a second via opening on the logic region, forming a metal nitride layer in the first via opening and the second via opening, removing part of the metal nitride layer and part of the first IMD layer on the logic region for forming a trench opening, and forming a metal layer in the first via opening, the second via opening, and the trench opening for forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region.

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H10N 50/01 - Fabrication ou traitement
• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 50/85 - Matériaux de la région active

Abrégé

A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric ((IMD) layer on the substrate and a first metal interconnection in the first IMD layer, forming a bonding pad on the first IMD layer, forming a passivation layer on the bonding pad, removing part of the passivation layer to expose the bonding pad, performing a chip probing test on the bonding pad, removing the bonding pad to form a recess, forming a dielectric layer to fill the recess completely, and forming a second metal interconnection in the dielectric layer.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 21/3105 - Post-traitement
• H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

An MRAM includes a bottom electrode, a magnetic tunnel junction, a cap layer and a top electrode stacked in sequence from bottom to top. The magnetic tunnel junction includes a free layer. The cap layer includes a mixture layer. The mixture layer includes a magnesium layer, a magnesium oxide layer, a tantalum oxide layer and a first tantalum layer. The mixture layer contacts the free layer.

Classes IPC  ?

• H10N 50/85 - Matériaux de la région active
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/10 - Dispositifs magnéto-résistifs

Abrégé

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/01 - Fabrication ou traitement
• H10N 50/10 - Dispositifs magnéto-résistifs

Abrégé

An FinFET structure includes a semiconductor substrate. A fin structure protrudes from the semiconductor substrate. A gate crosses the fin structure. A source region and a drain region are respectively disposed on the fin structure at two sides of the gate. The source region includes a first epitaxial layer and a third epitaxial layer respectively embedded in the fin structure. A first non-epitaxial region is defined as the fin structure between the first epitaxial layer and the third epitaxial layer. The drain region includes a second epitaxial layer and a fourth epitaxial layer respectively embedded in the fin structure. A second non-epitaxial region is defined as the fin structure between the second epitaxial layer and the fourth epitaxial layer. A first contact plug is disposed on the third epitaxial layer and a second contact plug is disposed on the fourth epitaxial layer.

Classes IPC  ?

• H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
• H10D 30/01 - Fabrication ou traitement
• H10D 64/01 - Fabrication ou traitement

Abrégé

A semiconductor device includes a doped region, a first gate and an insulating structure. The doped region is disposed in a substrate. The first gate extends along a first direction on the doped region. The insulating structure is disposed at a side of the first gate along a second direction. The insulating structure includes a first curve side surface directly contacting the first gate, and the first curve side surface has an inclined angle less than 45 degrees.

Classes IPC  ?

• H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H10D 30/68 - Transistors IGFET à grille flottante

Abrégé

A semiconductor structure with a silicon through via (TSV) includes a semiconductor substrate. A TSV penetrates the semiconductor substrate. The TSV includes a metal layer, a barrier layer and an isolation layer. An end of the metal layer protrudes from a back side of the semiconductor substrate. A recess is disposed at one side of the end of the metal layer. A composite structure fills the recess. The composite structure includes a thermal conductive layer and a first dielectric layer. The thermal conductive layer contacts the sidewall of the end of the metal layer and contacts the barrier layer, the isolation layer and the semiconductor substrate. A first dielectric layer is disposed on the thermal conductive layer. A top surface of the first dielectric layer is aligned with the end of the metal layer. The thermal conductive layer includes aluminum nitride, aluminum oxide or diamond.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A protection diode circuit for 3D IC is provided in the present invention, including a SOI substrate, a BEOL metal interconnect on the SOI substrate, a bottom contact connecting a silicon base of the SOI substrate and a first part of the BEOL metal interconnect, a first protection diode with a first gate connecting the first part, a first P-type doped region connecting the first part and a first N-type doped region connecting a second part of the SOI substrate, a second protection diode with a second gate connecting the second part, a second P-type doped region connecting the second part, and a second N-type doped region connecting a third part of the BEOL metal interconnect.

Classes IPC  ?

• H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré

Abrégé

A semiconductor structure includes a semiconductor substrate, pad structures, dielectric structures, a second dielectric layer, and a void. The semiconductor substrate includes a first dielectric layer, the pad structures and the dielectric structure are disposed on the first dielectric layer, and each dielectric structure is disposed on a sidewall of one of the pad structures. A top surface of each dielectric structure is lower than a top surface of each pad structure in a vertical direction. The first dielectric layer includes a recess located between two adjacent dielectric structures in a horizontal direction. The second dielectric layer covers the pad structures, the dielectric structures, and the first dielectric layer. The void is located in the second dielectric layer. At least a part of the void is sandwiched between two adjacent pad structures in the horizontal direction, and the void is located directly above the recess in the vertical direction.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A manufacturing method of a semiconductor structure includes following steps. A metal layer is formed above a first region and a second region of a semiconductor substrate and includes a recess above the second region. The recess is lower than a top surface of the metal layer above the first region. An oxide layer is formed on the metal layer. The oxide layer is partly formed above the first region and partly formed in the recess. A first CMP step is performed to the oxide layer. A removing rate of the oxide layer in the first CMP step is higher than that of the metal layer. A part of the oxide layer remains in the recess after the first CMP step. A second CMP step is performed after the first CMP step. The metal layer above the first and the second regions are partially removed by the second CMP step.

Classes IPC  ?

• H01L 21/321 - Post-traitement
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A resistive memory structure includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, a top electrode layer disposed on the switching layer, and an oxidized protection layer disposed on a sidewall of the memory stack structure. A spacer is located around the memory stack structure. The spacer covers the oxidized protection layer. A dielectric buffer layer is disposed on the spacer.

Classes IPC  ?

• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

Abrégé

A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on the logic region and the capacitor region of a substrate, forming a first metal interconnection in the IMD layer of the logic region and a second metal interconnection in the IMD layer of the capacitor region, removing the IMD layer adjacent to the second metal interconnection, and then forming a high-k dielectric layer on the first metal interconnection and extending to the second metal interconnection. Preferably, the high-k dielectric layer encloses an air gap.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A semiconductor structure includes a substrate having a low-voltage device region and a high-voltage device region thereon; a plurality of finFETs disposed in the low-voltage device region; at least one high-voltage transistor disposed in the high-voltage device region; and a trench isolation structure disposed in the substrate between the low-voltage device region and the high-voltage device region. The trench isolation structure includes a trench-fill layer and a protective condition layer between the trench-fill layer and the substrate. The protective condition layer includes an amorphous silicon layer.

Classes IPC  ?

• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/762 - Régions diélectriques
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor structure includes a substrate, a conductive pillar, a capacitor structure and dummy pillar structures. The conductive pillar is disposed in the substrate. The capacitor structure is disposed in the substrate, and is separated from the conductive pillar. The dummy pillar structures are randomly distributed between the conductive pillar and the capacitor structure.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A semiconductor structure includes an SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer, a circuit element disposed on the device layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the device layer through the buried oxide layer and trench-filling oxide in the trench isolation region.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/762 - Régions diélectriques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/498 - Connexions électriques sur des substrats isolants

Abrégé

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a planar device region and a non-planar device region, forming fin-shaped structures on the non-planar device region, forming a first shallow trench isolation (STI) around the substrate on the planar device region, forming a second shallow trench isolation (STI) around the fin-shaped structures, forming first gate structures on the substrate of the planar device region, forming second gate structures on the fin-shaped structures, forming a first resistor on the first STI, and forming a second resistor on the second STI.

Classes IPC  ?

• H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H10D 84/01 - Fabrication ou traitement

Abrégé

ABSTRACT OF DISCLOSURE A semiconductor device includes a dielectric layer, a metal wire, and a plurality of via structures. The dielectric layer is disposed on a substrate, and the metal wire is disposed within the dielectric layer. The via structures are separately disposed within the dielectric layer, on the metal wire and physically contacting the metal wire. The via structures are arranged along a first direction and a second direction being perpendicular to the first direction, at least into a 2×2 array, wherein a ratio between a total area of the via structures and an area of the metal wire is greater than 0.13.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A patterning method including the following steps is provided. A first template including at least one first main pattern, first dummy patterns, and second main patterns is provided. The first dummy patterns are located aside the first main pattern. A density of the first main pattern is less than a density of the second main patterns. A first imprint material is provided on a first substrate. The first imprint material is imprinted by using the first template to form a first imprint layer. The first substrate is etched by using the first imprint layer as a mask to form a second template. A second imprint material is provided on a material layer. The second imprint material is imprinted by using the second template to form a second imprint layer. The material layer is etched by using the second imprint layer as a mask to form a patterned material layer.

Classes IPC  ?

• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable

Abrégé

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

Classes IPC  ?

• H10N 50/01 - Fabrication ou traitement
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 50/80 - Détails de structure

Abrégé

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 35/01 - Fabrication ou traitement
• H10N 50/80 - Détails de structure
• H10W 10/00 -
• H10W 10/10 -
• H10W 20/00 -

Abrégé

A method for monitoring an electron beam of a measuring apparatus and a monitoring apparatus using the same are provided. The monitoring apparatus includes a transmission unit, a controlling unit, a frame analyzing unit, a shift analyzing unit, a determining unit and a warning unit. The controlling unit is configured to transmit a capturing command to the measuring apparatus, for continuously capturing a plurality of electron beam frames of the measuring apparatus, after the measuring apparatus is calibrated. The frame analyzing unit is configured to analyze a density concentration point in each of the electron beam frames. The shift analyzing unit is configured to obtain a largest shift among the density concentration points in the electron beam frames. The warning unit is configured to issue a warning notification to the measuring apparatus, if the largest shift is larger than a predetermined distance.

Classes IPC  ?

• H01J 37/28 - Microscopes électroniques ou ioniquesTubes à diffraction d'électrons ou d'ions avec faisceaux de balayage

Abrégé

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a high resistance impedance layer between a gate and a first metal structure in a vertical direction, wherein the first metal structure comprises at least one equipotential first metal and at least one non-equipotential first metal, wherein the equipotential first metal and the high resistance impedance layer have the same potential, the non-equipotential first metal and high resistance impedance layer have not the same potential, and the non-equipotential first metal and the high resistance impedance layer do not overlap in the vertical direction, and a minimum distance, between an edge of the high resistance impedance layer and an edge of the non-equipotential first metal in a horizontal direction perpendicular to the vertical direction, is larger than a size of a random defect.

Classes IPC  ?

• H01L 29/43 - Electrodes caractérisées par les matériaux dont elles sont constituées
• H01L 21/762 - Régions diélectriques
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif

Abrégé

A writing circuit includes a writing voltage generator, a reference voltage provider, and a comparison circuit. The writing voltage generator generates a writing voltage to perform a writing operation on each resistive memory cell among a resistive memory cell array. The reference voltage provider, during the writing operation, generates and provides a reference voltage according to a resistance of a reference device. The comparing circuit generates a comparison result by comparing the reference voltage with a target value. The writing voltage generator adjusts a maintenance time of the writing voltage according to the comparison result.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A water leakage detection device and a detection method thereof are provided. The water leakage detection device includes a leakage sensing tape, a processor, an infrared imaging sensor and a wireless communication transmitting module. The leakage sensing tape is used to detect whether a water leakage occurs. The processor is electrically connected to the water leakage sensing tape. The infrared imaging sensor is connected to the processor. The infrared imaging sensor is used to detect a water leakage range. The wireless communication transmitting module is connected to the processor. The wireless communication transmitting module is used to transmit a water leakage detection result.

Classes IPC  ?

• G01M 3/16 - Examen de l'étanchéité des structures ou ouvrages vis-à-vis d'un fluide par utilisation d'un fluide ou en faisant le vide par détection de la présence du fluide à l'emplacement de la fuite en utilisant des moyens de détection électrique

Abrégé

A bipolar junction transistor includes an emitter region, a base region, a collector region and an isolation structure. The base region is disposed adjacent to a first side of the emitter region. The collector region is disposed adjacent to a second side of the emitter region. The isolation structure is disposed between the emitter region and each of the base region and the collector region.

Classes IPC  ?

• H01L 29/735 - Transistors latéraux
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus

Abrégé

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

Classes IPC  ?

• H10W 90/00 -
• H10W 72/00 -
• H10W 90/22 -
• H10W 90/26 -

Abrégé

A fan filter unit and a control method thereof are provided. The fan filter unit includes a fan and a control module. The control module includes a logic judgment circuit, a fan power supply and a control circuit. The logic judgment circuit is connected to an apparatus power supply of a semiconductor apparatus. The logic judgment circuit is used to judge whether the apparatus power supply is shut down. The control circuit is connected to the fan power supply and the logic judgment circuit. If the apparatus power supply is shut down, the control circuit switches a fan power supply path from the apparatus power supply to the fan power supply.

Classes IPC  ?

• B01D 46/46 - Commande de la filtration de façon automatique
• B01D 46/00 - Filtres ou procédés spécialement modifiés pour la séparation de particules dispersées dans des gaz ou des vapeurs
• B01D 46/42 - Équipement auxiliaire ou son utilisation
• F04D 25/06 - Ensembles comprenant des pompes et leurs moyens d'entraînement la pompe étant entraînée par l'électricité
• F04D 27/00 - Commande, p. ex. régulation, des pompes, des installations ou des systèmes de pompage spécialement adaptés aux fluides compressibles
• F04D 29/70 - Grilles d'aspirationFiltresSéparateurs de poussièreNettoyage

Abrégé

The invention provides a layout pattern of a static random access memory, which comprises a first region adjacent to a second region, a first SRAM cell located in the first region, a first diffusion region in the first region, and a second SRAM cell located in the second region, which comprises a second diffusion region. A gate structure spans the first diffusion region and constitutes a first pass gate transistor of the first SRAM cell, and the gate structure spans the second diffusion region and constitutes a second pass gate transistor of the second SRAM cell, wherein the gate structure extends along a first direction, and the first diffusion region overlapping with the gate structure and the second diffusion region overlapping with the gate structure are not connected in the first direction.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

A SiC MOSFET is provided in the present invention, including a SiC substrate, a gate oxide layer on the SiC substrate, an isolation oxide layer on the gate oxide layer, two gates respectively on the gate oxide layer at both sides of the isolation oxide layer, wherein the two gates are both provided with an extending part extending inwardly on the isolation oxide layer, two sources respectively in the SiC substrate at both sides of the gate oxide layer, and a drain contact metal on the other side of the SiC substrate opposite to the gate oxide layer.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

Classes IPC  ?

• H10W 20/46 -
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10W 20/00 -
• H10W 20/40 -
• H10W 20/41 -

Abrégé

A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

Classes IPC  ?

• H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
• H10D 84/01 - Fabrication ou traitement
• H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]

Abrégé

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

Classes IPC  ?

• H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
• H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
• H10P 14/20 -

Abrégé

The invention provides a transistor. The transistor includes a well region arranged in a substrate, a gate structure arranged on the well region, a gate oxide layer, wherein a first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer, a first doped region and a second doped region arranged in the well region, wherein along the horizontal direction, the distance between the first doped region and the first portion of the gate oxide layer is greater than the distance between the second doped region and the second portion of the gate oxide layer, and a salicide block located on the substrate and at one side of the gate structure, wherein the salicide block is located between the first portion of the gate oxide layer and the first doped region.

Classes IPC  ?

• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps: providing a substrate with a shallow trench isolation structure and a first active area, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the substrate in the first active area, performing an etching step to remove part of the shallow trench isolation structure so that the top surface of the shallow trench isolation structure is lower than that of the substrate in the first active area, and after the etching step, a doping step is performed on the first active area.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/311 - Gravure des couches isolantes
• H01L 21/3115 - Dopage des couches isolantes
• H01L 21/762 - Régions diélectriques
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

A fabricating method of an RRAM includes forming a bottom electrode that includes an inverted T-shaped profile followed by sequentially forming a resistive switching layer and a top electrode from bottom to top. The inverted T-shaped profile includes a bottom element and a vertical element disposed on the bottom element. The detailed process steps include forming a first metal layer and a dummy material layer covering the first metal layer. The dummy material layer is then etched to form a recess, exposing the first metal layer. A second metal layer is formed to fill the recess. After removing the dummy material layer, a resistive switching material layer and a third metal layer are formed in sequence. Finally, the third metal layer, the resistive switching material layer, and the first metal layer are patterned to form the top electrode, the resistive switching layer, and the bottom electrode.

Classes IPC  ?

• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]

Abrégé

A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate and a first inductance layer. The first inductance layer includes a first metal line and a first interconnect structure. The first metal line is disposed on the first substrate, and the first interconnect structure is electrically connected with the first metal line. The second wafer includes a second substrate and a second inductance layer. The second inductance layer includes a second metal line and a second interconnect structure. The second metal line is disposed on the second substrate, and the second interconnect structure is electrically connected with the second metal line. The second interconnect structure is bonded with the first interconnect structure, so that the first inductance layer and the second inductance layer together form an inductance element.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes

Abrégé

An adjustable capacitor device and a method for adjusting a capacitance value are provided. The adjustable capacitor device includes a first variable resistor, a first comparator coupled between the first variable resistor and a first node, a first capacitor, a second capacitor, a first transistor coupled between the first node, the first capacitor and the second capacitor, and a second transistor coupled between the first node, the first capacitor and the second capacitor.

Classes IPC  ?

• H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
• H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
• H10N 50/80 - Détails de structure
• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

Abrégé

A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, a silicon-rich tensile stress layer, a passivation layer, an ultraviolet (UV)-transparent protection layer, a gate structure, a source structure, and a drain structure. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. The passivation layer is disposed on the silicon-rich tensile stress layer. The UV-transparent protection layer is disposed on the passivation layer. The gate structure penetrates through the UV-transparent protection layer, the passivation layer, and the silicon-rich tensile stress layer. The gate structure is partly disposed in the silicon-doped III-V compound barrier layer. The source structure and the drain structure penetrate through the UV-transparent protection layer, the passivation layer, the silicon-rich tensile stress layer, and the silicon-doped III-V compound barrier layer.

Classes IPC  ?

• H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
• H10D 30/01 - Fabrication ou traitement
• H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
• H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN

Abrégé

A method for forming a semiconductor device is disclosed. A substrate having a flash memory region and a logic device region is provided. At least one logic transistor is formed in the logic device region. At least one flash memory transistor is formed in the flash memory region. The at least one flash memory transistor comprises a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

Classes IPC  ?

• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• H10B 41/23 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/23 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés

Abrégé

A method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a first semiconductor structure and a second semiconductor structure are provided. The first semiconductor structure includes a first conductive pillar and a first conduction layer connected to the first conductive pillar, and the second semiconductor structure includes a second conductive pillar and a second conduction layer connected to the second conductive pillar, wherein a material of the first conduction layer and a material of the second conduction layer are conductive material and are volatilizable at a predetermined temperature. Thereafter, the first semiconductor structure and the second semiconductor structure are bonded to combine the first conductive pillar with the second conductive pillar. After the step of bonding the first semiconductor structure and the second semiconductor structure is completed, the first conduction layer and the second conduction layer are disappeared.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

A method for forming a semiconductor structure includes forming a conductive structure in a first dielectric layer, the conductive structure including an terminal portion and an extending portion, forming a second dielectric layer on the first dielectric layer, forming a first opening through the second dielectric layer directly above the extending portion and a second opening through the second dielectric layer directly above the terminal portion, a width of the second opening being smaller than 50% of a width of the first opening, forming a conductive material layer on the second dielectric layer and filling the first opening and the second opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the first opening and the second opening to obtain a conductive via in the first opening and a dummy via in the second opening.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]

Abrégé

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion directly and physically connected to the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, a dummy via through the second dielectric layer and directly contacting the terminal portion, wherein the dummy via comprises a lower portion consisting of a first filling layer and an upper portion consisting of a second filling layer, wherein the first filling layer and the second filling layer comprise different materials.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]