Abstract

During a first phase, a bit line voltage is transmitted to a first input end of a sense amplifier and a reference voltage is transmitted to a second input end of the sense amplifier, so that the sense amplifier outputs data based on a first voltage difference between its first and second input ends for providing a first data signal. During a second phase, the reference voltage is transmitted to the first input end of the sense amplifier and the bit line voltage is transmitted to the second input end of the sense amplifier, so that the sense amplifier outputs data based on a second voltage difference between its first and second input ends for providing a second data signal. During a third phase, a sense margin detecting signal is provided based on the first data signal and the second data signal.

IPC Classes  ?

• G11C 7/08 - Control thereof
• G11C 7/06 - Sense amplifiersAssociated circuits

Abstract

A semiconductor structure includes a substrate, a top metal layer disposed on the substrate, a top dielectric layer disposed on the substrate and the top metal layer, at least one opening disposed in the top dielectric layer, and an aluminum layer conformally deposited on the top dielectric layer and in the at least one opening. When viewed from above, the at least one opening has a regular n-gon pattern (n is greater than or equal to 6), circular pattern or oval pattern.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates

Abstract

The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer; and a metal layer is filled in the compensation groove.

IPC Classes  ?

• H10W 20/00 -
• H10P 50/00 -
• H10P 76/20 -
• H10W 20/42 -
• H10W 20/43 -

Abstract

The invention provides a method for manufacturing semiconductor circuit patterns, which comprises providing a dielectric layer, a mask layer and a first photoresist layer stacked on each other, wherein the first photoresist layer includes a weak pattern, and the weak pattern corresponds to a weak point position, and a first photolithography process is performed to form a first circuit groove in the mask layer, a second photoresist layer is formed, the second photoresist layer includes a compensation pattern, and a second photolithography process is performed to form a compensation groove in the dielectric layer; and a metal layer is filled in the compensation groove.

IPC Classes  ?

• H10W 20/00 -
• H10P 50/00 -
• H10P 76/20 -
• H10W 20/42 -
• H10W 20/43 -

Abstract

A semiconductor device includes a substrate having a medium-voltage (MV) region and a logic region, a gate structure on the MV region, a first single diffusion break (SDB) structure and a second SDB structure in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, top surfaces of the first SDB structure and the second SDB structure are coplanar, bottom surfaces of the first SDB structure and the second SDB structure are coplanar, and the first SDB structure and the second SDB structure are made of same material.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

An electronic device including a substrate with a trench and an inductor disposed on the substrate is provided. The inductor includes a first conductive layer and a second conductive layer. The first conductive layer is conformally disposed on the substrate. At least a portion of the first conductive layer is disposed in the trench. The first conductive layer has a first end portion and a second end portion. The second conductive layer is conformally disposed on the first conductive layer. The second conductive layer has a first end portion and a second end portion on the first end portion of the first conductive layer and the second end portion of the first conductive layer, respectively. The first end portion of the second conductive layer is electrically connected with the second end portion of the first conductive layer.

IPC Classes  ?

• H10W 20/40 -
• H10D 1/20 - Inductors
• H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors

Abstract

A method for fabricating semiconductor device includes the steps of forming an inter-metal dielectric (IMD) layer on a substrate, forming a metal interconnection in the IMD layer, forming a magnetic tunneling junction (MTJ) on the metal interconnection, and performing a trimming process to shape the MTJ. Preferably, the MTJ includes a first slope and a second slope and the first slope is less than the second slope.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/80 - Constructional details

Abstract

A testing method and a testing device for an electronic circuit are provided. The testing method includes the following steps. A test voltage signal is provided to a connection pad of the electronic circuit. A voltage regulating circuit of the electronic circuit is controlled to generate a reference voltage and provide the reference voltage to the connection pad. A voltage value of one of the test voltage signal and the reference voltage is adjusted, and a test current flowing through the connection pad is received. A measured voltage value of the reference voltage is determined according to a change in a current direction of the test current.

IPC Classes  ?

• G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer

Abstract

An optical metasurface structure includes a substrate, a first metal rail structure, a second metal rail structure, a diffusion barrier layer, a high dielectric constant dielectric layer, and a liquid crystal material. The first metal rail structure and the second metal rail structure are disposed above the substrate. The diffusion barrier layer is disposed on the first metal rail structure and the second metal rail structure. The high dielectric constant dielectric layer is disposed on the diffusion barrier layer. The liquid crystal material is disposed above the substrate and at least a part of the liquid crystal material is located between the first metal rail structure and the second metal rail structure in a horizontal direction. The diffusion barrier layer has a first thickness, a portion of the high dielectric constant dielectric layer has a second thickness, and the first thickness is greater than the second thickness.

IPC Classes  ?

• G02F 1/1343 - Electrodes

Abstract

The invention provides a capacitor structure, which comprises a first capacitor structure located on a substrate, wherein the first capacitor structure comprises a plurality of lower electrode layers, wherein each lower electrode layer is arranged in the same direction and stacked with each other along a height direction (Z direction), and a second capacitor structure located on the first capacitor structure, wherein the second capacitor structure comprises a plurality of upper electrode layers, wherein some upper electrode layers are arranged in a first direction (X direction), and the other upper electrode layers are arranged in a second direction (Y direction), and the first direction and the second direction are perpendicular to each other.

IPC Classes  ?

• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/62 - Capacitors having potential barriers

Abstract

A delay circuit includes a delay chain and a calibration circuit. The delay chain includes a plurality of delay cells coupled in series. The delay chain provides a delay amount, and delays a clock signal by the delay amount to generate a delayed clock signal. The calibration circuit is coupled to the delay chain, counts the number of pulses of the delayed clock signal during a preset time period to generate a count value, and generates calibration information according to the count value. The delay chain adjusts the delay amount by adjusting a transmission delay of at least one of the delay cells according to the calibration information.

IPC Classes  ?

• H03M 1/10 - Calibration or testing
• H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
• H03M 1/12 - Analogue/digital converters

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a gate structure on a substrate, forming a first source electrode adjacent to one side of the gate structure, forming a second source electrode adjacent to another side of the gate structure, forming a first contact plug on the first source electrode, forming a second contact plug on the second source electrode, forming a field plate on the first contact plug and the second contact plug, and forming a drain electrode on a backside of the substrate.

IPC Classes  ?

• H10D 30/66 - Vertical DMOS [VDMOS] FETs
• H10D 30/01 - Manufacture or treatment
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 64/00 - Electrodes of devices having potential barriers

Abstract

An imprint method including the following steps is provided. Providing a first master mold including a first protruding pattern and a second protruding pattern. Providing a second master mold including a third protruding pattern. Performing a first imprint step on a first photoresist layer formed on a replica mold by using the first master mold. Performing a first etching step on the replica mold to form a first recessed portion and a second recessed portion. Performing a second imprint step on a second photoresist layer formed on the replica mold by using the second master mold. Performing a second etching step on the replica mold to form a third recessed portion overlapping the first recessed portion. Performing a third imprint step on a third photoresist layer formed on a substrate by using the replica mold. Performing a third etching step on the substrate to form a desired pattern.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• B29C 33/38 - Moulds or coresDetails thereof or accessories therefor characterised by the material or the manufacturing process
• B29C 43/02 - Compression moulding, i.e. applying external pressure to flow the moulding materialApparatus therefor of articles of definite length, i.e. discrete articles
• B29C 43/14 - Compression moulding, i.e. applying external pressure to flow the moulding materialApparatus therefor of articles of definite length, i.e. discrete articles in several steps

Abstract

The invention provides a semiconductor structure, the semiconductor structure comprises a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, a plurality of first metal layers located on a part of the gate structures, and the first metal layers are respectively electrically connected with the corresponding gate structures, at least one second metal layer, the second metal layer is bridged over at least two of the gate structures, wherein the depth of the first metal layer is greater than that of the second metal layer.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10W 20/00 -
• H10W 20/43 -

Abstract

A semiconductor device includes: a substrate having a first semiconductor layer, an insulating layer, and a second semiconductor layer; an active device on the substrate; an interlayer dielectric (ILD) layer on the active device; a first contact plug in the ILD layer and electrically connected to the active device; and a second contact plug in the ILD layer and the insulating layer, wherein a top surface of the second contact plug is higher than a top surface of the ILD layer.

IPC Classes  ?

• H10W 20/00 -
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H10P 90/00 -
• H10W 10/10 -

Abstract

A semiconductor device includes a substrate having an active area, a first gate line extending along a first direction on the active area, a first gate line extension adjacent to the first gate line and outside the active area, a second gate line extending along the first direction on the active area and adjacent to the first gate line, and a second gate line extension adjacent to the second gate line and outside the active area. Preferably, the active area includes a first indentation and a second indentation, in which the first gate line extension overlaps the first indentation and the second gate line extension overlaps the first indentation.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H03F 3/16 - Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
• H10D 87/00 - Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate

Abstract

A semiconductor device includes a substrate, a dielectric layer, a gate structure, a lightly doped region, a first spacer and a heavily doped region. The dielectric layer is disposed on the substrate and includes a first section with a first thickness and a second section with a second thickness, the first thickness is greater than the second thickness, and the second section surrounds the first section. The gate structure covers a portion of the first section. The lightly doped region is formed in the substrate and adjacent to the gate structure. The first spacer is disposed on sidewalls of the gate structure and covers another portion of the first section. The heavily doped region is disposed in the lightly doped region and adjacent to the second section.

IPC Classes  ?

• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 30/01 - Manufacture or treatment
• H10D 30/60 - Insulated-gate field-effect transistors [IGFET]
• H10D 64/01 - Manufacture or treatment

Abstract

The invention provides a semiconductor structure, the semiconductor structure includes a substrate, a dielectric layer located on the substrate, a plurality of gate structures located in the dielectric layer on the substrate, wherein the plurality of gate structures comprises at least one first gate structure and at least one second gate structure, at least one first metal layer located on the first gate structure, wherein the first metal layer is electrically connected with the first gate structure, and at least one second metal layer bridging the second gate structure and another one of the plurality of gate structures, wherein a top surface of the first gate structure is lower than a top surface of the second gate structure.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10W 20/00 -
• H10W 20/43 -

Abstract

The present disclosure relates to a semiconductor device and a method of fabricating the same including a substrate, a first gate structure, two first source/drain structures, and an air barrier layer. The substrate includes at least one shallow trench isolation disposed therein. The first gate structure is disposed on the substrate. Two first source/drain structures are disposed in the substrate, at two sides of the first gate structure, and a side of each of the two first source/drain structures is adjacent to the at least one shallow trench isolation. The air gap barrier layer is disposed between the substrate and each of the two first source/drain structures, wherein the air gap barrier layer includes a bottom surface and two sidewalls each extending in three different directions.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
• H10D 84/01 - Manufacture or treatment
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A fabricating method for a transistor with a fin structure and a nanosheet begins by providing a first fin structure with a dummy gate, two spacers, a first embed epitaxial layer, and a second embed epitaxial layer. Subsequently, a first epitaxial layer and a second epitaxial layer are formed to cover the fin structure and the dummy gate. Two first mask layers are then formed. Parts of the first and the second epitaxial layers are removed using the two first mask layers as a mask to expose the dummy gate and a nanosheet is formed from the remaining second epitaxial layer. Later, the dummy gate is replaced by a first gate portion, and a second gate portion is formed to encapsulate the nanosheet. Finally, a metal gate is formed between the first gate portion and the second gate portion.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 64/01 - Manufacture or treatment

Abstract

An RRAM string includes a substrate and numerous RRAM cells disposed on the substrate in a memory region. The RRAM cells include at least two last RRAM cells and one middle RRAM cell. Each RRAM cell includes a bottom electrode, a resistive switching layer, a top electrode, and a cap layer stacked from bottom to top. A first spacer contacts a first sidewall of the bottom electrode and a second sidewall of the resistive switching layer. A second spacer contacts the first spacer and a third sidewall of the top electrode. Furthermore, a dielectric layer covers the second spacer in the memory region. The dielectric layer at an outer side of the last RRAM cells includes a slope. An end of the slope contacts the second spacer located on a surface of the substrate.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A semiconductor device includes a substrate, a plurality of gate stack structures, a doped ring, a guard ring, and a plurality of conductive lines. The substrate includes a first region and a second region. The second region surrounds the first region. The gate stack structures are located in the first region. The doped ring is located in the substrate in the second region and surrounds the first region. The guard ring is located on the substrate in the second region and surrounds the first region. The conductive lines are connected to the doped ring and the gate stack structures.

IPC Classes  ?

• H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10W 42/60 -

Abstract

A method for forming a semiconductor structure is disclosed. A first dielectric layer is formed on a substrate. An etch stop layer is formed on the first dielectric layer. A second dielectric layer is formed on the etch stop layer. A first conductor and a second conductor are formed in the second dielectric layer. An air gap is formed in the second dielectric layer and between the first conductor and the second conductor. A first low-polarity dielectric layer is formed on a sidewall surface of the second dielectric layer within the air gap.

IPC Classes  ?

• H10W 20/46 -
• H10W 20/00 -
• H10W 20/41 -

Abstract

A nanoprobe manufacturing machine and a method of manufacturing nanoprobe are provide. The nanoprobe manufacturing machine comprising a step motor held by a hold stage and is removable in an upward direction and in a downward direction; a positive electrode and a negative electrode respectively fixed on the step monitor; a first metal probe fixed and electrically connected to the positive electrode and a second metal probe fixed and electrically connected to the negative electrode; and a container containing an electrolyte, wherein the step motor carrying the first metal probe and the second metal probe into the electrolyte to form a nanoprobe from the first metal probe by a redox reaction in the electrolyte.

IPC Classes  ?

• G01R 1/067 - Measuring probes

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate having through-silicon vias (TSVs) therein, forming an inorganic layer on the substrate, forming an organic layer on the inorganic layer, and then bonding dies having different functionalities on the organic layer. Preferably, the dies include a radio-frequency integrated circuit (RFIC) die, a power amplifier (PA) die, and/or a high electron mobility transistor (HEMT) die.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H01L 23/00 - Details of semiconductor or other solid state devices
• H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs

Abstract

A semiconductor device includes an inter-metal dielectric (IMD) layer on a substrate, a metal interconnection in the IMD layer, a bottom electrode on the metal interconnection, and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a sidewall of the MTJ comprises a first slope and a second slope. Preferably, the MTJ further includes a pinned layer on the bottom electrode, in which a first angle included by a bottom surface of the bottom electrode and the sidewall of the MTJ is equal to a second angle included by a bottom surface of the pinned layer and the sidewall of the MTJ.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/80 - Constructional details

Abstract

A resistive switching device includes a substrate; a first dielectric layer on the substrate; a conductive via in the first dielectric layer; and a trench on an upper portion of the conductive via and in the first dielectric layer. The trench includes a first sidewall formed by the conductive via and a bottom surface formed by the conductive via and the first dielectric layer. A resistive switching structure is formed in the trench and contacts the first sidewall. The resistive switching structure includes a top electrode layer, a resistive switching material layer, and a bottom electrode layer disposed between the resistive switching material layer and the conductive via.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

An operating method and an operation assistance system for a robot arm are provided. The operating method for the robot arm includes the following steps. A plurality of moving detection values of the robot arm are obtained. At least one moving time length of at least one movement of the robot arm is obtained. A plurality of operation values are obtained. The filtering noises are filtered from the moving detection values via a clustering algorithm. A plurality of moving representative values of the moving detection values are obtained. A health status of the robot arm is obtained according to the moving representative values, the moving time length, and the operation values, via an NN algorithm.

IPC Classes  ?

• B25J 9/16 - Programme controls

Abstract

A method for fabricating semiconductor device includes first bonding a first wafer to a carrier, performing a first grinding process on a backside of the first wafer, performing a first trimming process on a sidewall of the first wafer, forming a first protective layer on the sidewall of the first wafer, forming a first bonding pad on the backside of the first wafer, bonding a second wafer to the first bonding pad, performing a second grinding process on a backside of the second wafer, performing a second trimming process on a sidewall of the second wafer, forming a second protective layer on the sidewalls of the first wafer and the second wafer, and forming a second bonding pad on the backside of the second wafer.

IPC Classes  ?

• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

A radio-frequency (RF) device includes a main device on a substrate, a first port extending along a first direction adjacent to a first side of the main device, a second port extending along the first direction adjacent to a second side of the main device, a first shield structure adjacent to a third side of the main device, a second shield structure adjacent to a fourth side of the main device, a first connecting structure extending along a second direction to connect the first port and the main device, and a second connecting structure extending along the second direction to connect the second port and the main device.

IPC Classes  ?

• H10W 42/20 -
• H10W 20/41 -
• H10W 44/20 -

Abstract

A circuit layout hotspot detection system includes a lithography simulator, an object detector, and a cross-model feature fusion module. The lithography simulator is used to receive circuit layout data to generate a layout deformation feature matrix. The object detector is coupled to the lithography simulator for generating a plurality of layout pattern feature matrices based on the circuit layout data. The cross-model feature fusion module is coupled to the lithography simulator and the object detector for generating potential abnormal hotspot data corresponding to the circuit layout data based on the plurality of layout pattern feature matrices and the layout deformation feature matrix. The circuit layout data includes at least one circuit layout layer. The potential abnormal hotspot data includes a location and a size of at least one potential abnormal hotspot.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Abstract

An optical metasurface structure includes a substrate, metal rail structures, and a liquid crystal material. The substrate includes a first region and a second region. The metal rail structures and the liquid crystal material are disposed above the first region. At least a part of the liquid crystal material is located between the metal rail structures adjacent to each other in a horizontal direction, and a top width of one of the metal rail structures is less than a bottom width of the one of the metal rail structures.

IPC Classes  ?

• G02F 1/1345 - Conductors connecting electrodes to cell terminals
• B82Y 20/00 - Nanooptics, e.g. quantum optics or photonic crystals
• G02F 1/1343 - Electrodes

Abstract

A capacity structure includes a semiconductor substrate, a first patterned conductive layer, at least one first contact plug and at least one second contact plug. The semiconductor substrate includes a first-conductivity well region and a second-conductivity well region adjacent to each other. The first patterned conductive layer is disposed on the semiconductor substrate and includes a first electrode pattern and a second electrode pattern separated from each other and forming at least one first parasitic capacitance there between. The first contact plug electrically connects the first electrode pattern and the first-conductivity well region. The second contact plug electrically connects the second electrode pattern and the second-conductivity well region, so as to form at least one second parasitic capacitance between the first-conductivity well region and the second-conductivity well region.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H10D 1/00 - Resistors, capacitors or inductors

Abstract

A memory component includes two memory units, a first gate and a doped region. The two memory units are disposed on a substrate. The first gate is disposed between the two memory units, and the first gate includes an embedded portion embedded in the substrate. The doped region is disposed in the substrate and surrounds the embedded portion.

IPC Classes  ?

• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 30/68 - Floating-gate IGFETs

Abstract

A semiconductor device includes a semiconductor substrate, a first semiconductor channel layer, a second semiconductor channel layer, and an isolation structure. The first semiconductor channel layer, the second semiconductor channel layer, and the isolation structure are disposed above the semiconductor substrate. The isolation structure includes a vertical portion, a first horizontal portion, and a second horizontal portion. The vertical portion is disposed between the first semiconductor channel layer and the second semiconductor channel layer in a horizontal direction. The first horizontal portion is disposed between the first semiconductor channel layer and the semiconductor substrate in a vertical direction. The second horizontal portion is disposed between the second semiconductor channel layer and the semiconductor substrate in the vertical direction. The first horizontal portion and the second horizontal portion are connected with the vertical portion.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

Provided is a flash memory including a substrate including a recess, first, second and third dielectric layers, a floating gate, source and drain regions, an erase gate, and a select gate. The first dielectric layer is disposed in the recess. The floating gate fills the recess and the first dielectric layer located between the floating gate and the substrate. The second dielectric layer covers a top surface of the floating gate away from the substrate. The source region is disposed in the substrate at one side of the floating gate. The drain region is disposed in the substrate at another of the floating gate. The erase gate is disposed on the second dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate and separated from the second dielectric layer.

IPC Classes  ?

• H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
• H10D 30/68 - Floating-gate IGFETs

Abstract

A method for fabricating a high electron mobility transistor (HEMT) includes the steps of first forming a buffer layer on a substrate, forming a barrier layer on the buffer layer, forming a p-type semiconductor layer on the barrier layer, forming a compressive stress layer adjacent to one side of the p-type semiconductor layer, and then forming a tensile stress layer adjacent to another side of the p-type semiconductor layer.

IPC Classes  ?

• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 30/01 - Manufacture or treatment
• H10P 14/694 -

Abstract

A semiconductor structure includes a semiconductor substrate; a source structure in the semiconductor substrate, wherein the source structure includes a source drift region and a heavily doped source region within the source drift region; a recessed trench disposed in the semiconductor substrate and spaced apart from the source structure; a drain structure disposed at a bottom of the recessed trench, wherein the drain structure includes a drain drift region, a heavily doped drain region disposed within the drain drift region, and a carbon-doped surface layer on the heavily doped drain region; and a gate structure disposed on the semiconductor substrate between the source structure and the drain structure.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H10D 30/01 - Manufacture or treatment
• H10D 30/65 - Lateral DMOS [LDMOS] FETs
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

Abstract

A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric ((IMD) layer on a substrate and a metal interconnection in the IMD layer, forming a dielectric layer on the IMD layer, patterning the dielectric layer to form an opening, forming a bonding pad in the opening, and then forming a passivation layer on the bonding pad. Preferably, a top surface of the bonding pad includes a first curve and a sidewall of the bonding pad includes a second curve.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates

Abstract

A structure with a capacitor and a fin transistor includes a substrate. The substrate includes a capacitor region and a fin transistor region. A mesa is disposed within the capacitor region of the substrate. The mesa protrudes from a surface of the substrate. The mesa includes a top surface and two sloping surfaces. Each of the sloping surfaces connects to the top surface of the mesa and the surface of the substrate. A doping region is disposed within the mesa. A capacitor electrode is only disposed on the top surface. A capacitor dielectric layer is disposed between the capacitor electrode and the doping region.

IPC Classes  ?

• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 1/68 - Capacitors having no potential barriers
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10P 30/20 -
• H10W 10/00 -
• H10W 10/17 -

Abstract

Semiconductor device and method of fabricating the same, includes a substrate, a first dielectric layer and a second dielectric layer, a bonding interface layer, and a plurality of dummy vias. The first dielectric layer and the second dielectric layer are stacked in sequence on the substrate. The bonding interface layer is disposed between the first dielectric layer and the second dielectric layer, wherein the bonding interface layer includes a first interface layer and a second interface layer stacked in sequence. The plurality of dummy vias are disposed within one of the first dielectric layer and the second dielectric layer, being located at only one side of the bonding interface layer in a vertical direction of the substrate.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H10D 88/00 - Three-dimensional [3D] integrated devices

Abstract

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10N 35/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10W 10/00 -
• H10W 10/10 -
• H10W 20/00 -

Abstract

A semiconductor device includes a resistive random access memory (RRAM) device, a dual damascene structure, and a spacer. The dual damascene structure is disposed near the RRAM device, and the spacer is disposed in a sidewall of the RRAM device. The RRAM device includes a lower electrode, a metal oxide layer, and an upper electrode. The metal oxide layer is disposed on the lower electrode, and the upper electrode is disposed on the metal oxide layer. The dual damascene structure includes a via and a wire disposed on the via, in which a top part of the wire is coplanar with a top part of the upper electrode in the RRAM device.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10W 20/00 -
• H10W 20/41 -
• H10W 20/42 -

Abstract

Provided are a transistor structure and a manufacturing method thereof. The transistor structure includes a gate dielectric layer, a gate disposed on the gate dielectric layer, a spacer structure located on the gate dielectric layer and disposed on the sidewall of the gate, first, second and third doped regions, and a metal silicide layer. The first doped regions are disposed in the substrate on two sides of the gate. The second doped regions are disposed in the first doped regions, respectively. The third doped regions is disposed in the second doped regions, respectively. The metal silicide layer is disposed at the surface of the third doped regions. In the channel direction, the first doped regions extend below the gate to partially overlap with the gate, the second doped regions extends below the spacer structure, and the metal silicide layer does not extend below the gate.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/60 - Impurity distributions or concentrations
• H10D 64/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes

Abstract

The invention provides a semiconductor layout pattern, which comprises a substrate, wherein two content addressable memory cells are disposed on the substrate and arranged on two sides of a symmetry axis, and a first matching line conductive layer and a second matching line conductive layer are located on the substrate, wherein from a top view, the first matching line conductive layer and the second matching line conductive layer overlap the symmetry axis between the two content addressable memory cells and are arranged along the direction of the symmetry axis.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

A sensing device and an operation method thereof are provided. The sensing device includes a Passive Infrared (PIR) sensor, a radiation emitter and a controller. The PIR sensor includes a plurality sensing elements. The PIR sensor is used to detect a heat source. The controller is connected to the radiation emitter and the PIR sensor. The controller enables the radiation emitter to emit a radiation light to the PIR sensor when the sensing elements reach a voltage balance for a predetermined time and then disables the radiation emitter.

IPC Classes  ?

• G01J 5/00 - Radiation pyrometry, e.g. infrared or optical thermometry

Abstract

A method for generating an OPC pattern is provided. A layout pattern including a first unit pattern in an edge region and second unit patterns in a central region. A first OPC sub-pattern corresponding to the first unit pattern and the second unit patterns in an edge portion of the central region adjacent to the edge region and a second OPC sub-pattern corresponding to the second unit pattern are built. A mark covering the edge region and the edge portion is formed. The edge region is identified, and a first OPC pattern is obtained according to the first OPC sub-pattern. The central region except the edge portion is identified according to the mark, and a second OPC pattern is obtained according to the second OPC sub-pattern. The first OPC pattern and the second OPC pattern are combined to obtain an OPC pattern of the layout pattern.

IPC Classes  ?

• G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

A semiconductor device includes a multi-die package, a testkey region, and a scribe line. The multi-die package includes a plurality of dies each in a regular polygon shape, wherein each of the plurality of dies includes a number of sides, and the number is a multiplier of four and is greater than four. The testkey region is disposed between the plurality of dies and adjacent to one side of each of the plurality of dies. The testkey region is in an equilateral polygon shape. The scribe line surrounds a periphery of each of the plurality of dies and a periphery of the testkey region.

IPC Classes  ?

• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape

Abstract

A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H10W 90/00 -

Abstract

The present disclosure provides a semiconductor device and a method for forming the same. The semiconductor device includes a substrate including an active region defining by an isolation trench, an isolation structure disposed in the isolation trench and including a recess, and a thin film resistor structure disposed over the recess.

IPC Classes  ?

• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 1/47 - Resistors having no potential barriers
• H10D 84/01 - Manufacture or treatment

Abstract

A semiconductor device includes a substrate having a non-planar device region and a planar device region, a first isolation structure in the substrate of the planar device region, a first gate structure on the first isolation structure, a first epitaxial layer adjacent to the first gate structure, a second isolation structure in the substrate of the non-planar device region, a second gate structure on the second isolation structure, and a second epitaxial layer adjacent to the second gate structure. Preferably, the first gate structure includes a first metal gate and the second gate structure includes a second metal gate.

IPC Classes  ?

• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 84/01 - Manufacture or treatment

Abstract

A semiconductor structure with single diffusion break (SDB) is provided in the present invention, including a substrate with a first region and a second region defined thereon, the first region and the second region are adjacent to each other and have respective fins, a STI on the substrate and surrounding the fins, multiple gates crossing over the fins, a dummy gate on the STI between the first region and the second region and spaced apart with the gates, at least one conductive pattern on the dummy gate and connected therewith, and at least one dummy via on the at least one conductive pattern and connected therewith.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H01L 21/762 - Dielectric regions
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]

Abstract

An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

IPC Classes  ?

• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 30/01 - Manufacture or treatment
• H10P 30/20 -
• H10P 95/90 -

Abstract

An LCM structure includes a composite dielectric layer. The composite dielectric layer includes a nitrogen-doped silicon carbide layer, a silicon oxide layer and a silicon nitride layer stacked from bottom to top. A first metal rail includes a pedestal and a metal strip. The first metal rail embedded in the silicon oxide layer and the nitrogen-doped silicon carbide layer is defined as the pedestal, and the first metal rail embedded in the silicon nitride layer and protruding on the silicon nitride layer is defined as the metal strip. The width of the pedestal in the silicon oxide layer continuously and gradually increases along a direction toward the nitrogen-doped silicon carbide layer. A second metal rail is disposed at one side of the first metal rail. A gap is disposed between the first metal rail and the second metal rail. Nemours liquid crystals fill the gap.

IPC Classes  ?

• G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the position or the direction of light beams, i.e. deflection
• H10F 77/40 - Optical elements or arrangements

Abstract

A LDMOS is provided in the present invention, including multiple fins spaced apart, wherein each fin has a recess region, a shallow trench isolation in those recess regions forms a thick oxide layer, a gate crosses over those fins, wherein the thick oxide layer is close to one side of the gate and partially overlaps the gate, and a source and a drain respectively at two sides of the gate in each fin, wherein the thick oxide layer extends outside the gate to the drains.

IPC Classes  ?

• H10D 30/65 - Lateral DMOS [LDMOS] FETs
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

The invention provides a layout pattern of static random access memory (SRAM) cell, which at least comprises an SRAM cell in a region, wherein the SRAM cell comprises a plurality of fin structures on a substrate, wherein a plurality of gate structures span the plurality of fin structures so as to form a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first pass gate transistor PG1A, a second pass gate transistor PG1B, a third pass gate transistor PG2A and a pass gate transistor PG2B are located on the substrate, wherein the first pull-up transistor PU1 and the second pull-up transistor PU2 are aligned with each other in a Y direction when viewed from a top view.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A photomask module includes a first photomask and a second photomask. The first photomask includes a main circuit pattern. The second photomask includes a pad pattern, and the pad pattern includes a pad body pattern portion and an extension pattern portion. The extension pattern portion extends outward from the pad body pattern portion. When the first photomask and the second photomask overlap with each other, the extension pattern portion is at least partially surrounded by the main circuit pattern.

IPC Classes  ?

• G03F 1/26 - Phase shift masks [PSM]PSM blanksPreparation thereof
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or

Abstract

The invention provides a static random access memory structure, which comprises a silicon substrate, a shallow trench isolation on the silicon substrate, a first fin structure connected with the silicon substrate and protruding from the shallow trench isolation, a first gate structure spanning the first fin structure and parts of the shallow trench isolation, so that the first gate structure covers a top surface and a part of sidewalls of the first fin structure, and forms a pass gate transistor (PG). And a protruding part located directly below the first gate structure and on the shallow trench isolation, the protruding part covers part of the surface of at least one sidewall of the first fin structure, and a top surface of the protruding part is higher than a top surface of the shallow trench isolation.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 84/01 - Manufacture or treatment
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A method for fabricating a magnetoresistive random access memory (MRAM) device includes first providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, using a first patterned mask to remove the first IMD layer for forming a first via opening on the MRAM region and a second via opening on the logic region, forming a metal nitride layer in the first via opening and the second via opening, removing part of the metal nitride layer and part of the first IMD layer on the logic region for forming a trench opening, and forming a metal layer in the first via opening, the second via opening, and the trench opening for forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10N 50/01 - Manufacture or treatment
• H10N 50/10 - Magnetoresistive devices
• H10N 50/85 - Materials of the active region

Abstract

A method for fabricating a semiconductor device includes the steps of first forming a first inter-metal dielectric ((IMD) layer on the substrate and a first metal interconnection in the first IMD layer, forming a bonding pad on the first IMD layer, forming a passivation layer on the bonding pad, removing part of the passivation layer to expose the bonding pad, performing a chip probing test on the bonding pad, removing the bonding pad to form a recess, forming a dielectric layer to fill the recess completely, and forming a second metal interconnection in the dielectric layer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/3105 - After-treatment
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

An MRAM includes a bottom electrode, a magnetic tunnel junction, a cap layer and a top electrode stacked in sequence from bottom to top. The magnetic tunnel junction includes a free layer. The cap layer includes a mixture layer. The mixture layer includes a magnesium layer, a magnesium oxide layer, a tantalum oxide layer and a first tantalum layer. The mixture layer contacts the free layer.

IPC Classes  ?

• H10N 50/85 - Materials of the active region
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/10 - Magnetoresistive devices

Abstract

A method for fabricating a magnetoresistive random access memory (MRAM) device includes the steps of providing a substrate having a MRAM region and a logic region, forming a first inter-metal dielectric (IMD) layer on the substrate, forming a metal nitride layer on the first IMD layer, using a first patterned mask to remove the metal nitride layer on the logic region, using a second patterned mask to remove the metal nitride layer on the MRAM region, using a third patterned mask to remove the first IMD layer on the MRAM region and the logic region, forming a first metal interconnection on the MRAM region and a second metal interconnection on the logic region, and forming a magnetic tunneling junction (MTJ) on the first metal interconnection.

IPC Classes  ?

• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/10 - Magnetoresistive devices

Abstract

An FinFET structure includes a semiconductor substrate. A fin structure protrudes from the semiconductor substrate. A gate crosses the fin structure. A source region and a drain region are respectively disposed on the fin structure at two sides of the gate. The source region includes a first epitaxial layer and a third epitaxial layer respectively embedded in the fin structure. A first non-epitaxial region is defined as the fin structure between the first epitaxial layer and the third epitaxial layer. The drain region includes a second epitaxial layer and a fourth epitaxial layer respectively embedded in the fin structure. A second non-epitaxial region is defined as the fin structure between the second epitaxial layer and the fourth epitaxial layer. A first contact plug is disposed on the third epitaxial layer and a second contact plug is disposed on the fourth epitaxial layer.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

A semiconductor device includes a doped region, a first gate and an insulating structure. The doped region is disposed in a substrate. The first gate extends along a first direction on the doped region. The insulating structure is disposed at a side of the first gate along a second direction. The insulating structure includes a first curve side surface directly contacting the first gate, and the first curve side surface has an inclined angle less than 45 degrees.

IPC Classes  ?

• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/311 - Etching the insulating layers
• H10D 30/68 - Floating-gate IGFETs

Abstract

A semiconductor structure with a silicon through via (TSV) includes a semiconductor substrate. A TSV penetrates the semiconductor substrate. The TSV includes a metal layer, a barrier layer and an isolation layer. An end of the metal layer protrudes from a back side of the semiconductor substrate. A recess is disposed at one side of the end of the metal layer. A composite structure fills the recess. The composite structure includes a thermal conductive layer and a first dielectric layer. The thermal conductive layer contacts the sidewall of the end of the metal layer and contacts the barrier layer, the isolation layer and the semiconductor substrate. A first dielectric layer is disposed on the thermal conductive layer. A top surface of the first dielectric layer is aligned with the end of the metal layer. The thermal conductive layer includes aluminum nitride, aluminum oxide or diamond.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A protection diode circuit for 3D IC is provided in the present invention, including a SOI substrate, a BEOL metal interconnect on the SOI substrate, a bottom contact connecting a silicon base of the SOI substrate and a first part of the BEOL metal interconnect, a first protection diode with a first gate connecting the first part, a first P-type doped region connecting the first part and a first N-type doped region connecting a second part of the SOI substrate, a second protection diode with a second gate connecting the second part, a second P-type doped region connecting the second part, and a second N-type doped region connecting a third part of the BEOL metal interconnect.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips

Abstract

A semiconductor structure includes a semiconductor substrate, pad structures, dielectric structures, a second dielectric layer, and a void. The semiconductor substrate includes a first dielectric layer, the pad structures and the dielectric structure are disposed on the first dielectric layer, and each dielectric structure is disposed on a sidewall of one of the pad structures. A top surface of each dielectric structure is lower than a top surface of each pad structure in a vertical direction. The first dielectric layer includes a recess located between two adjacent dielectric structures in a horizontal direction. The second dielectric layer covers the pad structures, the dielectric structures, and the first dielectric layer. The void is located in the second dielectric layer. At least a part of the void is sandwiched between two adjacent pad structures in the horizontal direction, and the void is located directly above the recess in the vertical direction.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A manufacturing method of a semiconductor structure includes following steps. A metal layer is formed above a first region and a second region of a semiconductor substrate and includes a recess above the second region. The recess is lower than a top surface of the metal layer above the first region. An oxide layer is formed on the metal layer. The oxide layer is partly formed above the first region and partly formed in the recess. A first CMP step is performed to the oxide layer. A removing rate of the oxide layer in the first CMP step is higher than that of the metal layer. A part of the oxide layer remains in the recess after the first CMP step. A second CMP step is performed after the first CMP step. The metal layer above the first and the second regions are partially removed by the second CMP step.

IPC Classes  ?

• H01L 21/321 - After-treatment
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A resistive memory structure includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a bottom electrode layer, a switching layer disposed on the bottom electrode layer, a top electrode layer disposed on the switching layer, and an oxidized protection layer disposed on a sidewall of the memory stack structure. A spacer is located around the memory stack structure. The spacer covers the oxidized protection layer. A dielectric buffer layer is disposed on the spacer.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A method for fabricating a semiconductor device includes the steps of first forming an inter-metal dielectric (IMD) layer on the logic region and the capacitor region of a substrate, forming a first metal interconnection in the IMD layer of the logic region and a second metal interconnection in the IMD layer of the capacitor region, removing the IMD layer adjacent to the second metal interconnection, and then forming a high-k dielectric layer on the first metal interconnection and extending to the second metal interconnection. Preferably, the high-k dielectric layer encloses an air gap.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

A semiconductor structure includes a substrate having a low-voltage device region and a high-voltage device region thereon; a plurality of finFETs disposed in the low-voltage device region; at least one high-voltage transistor disposed in the high-voltage device region; and a trench isolation structure disposed in the substrate between the low-voltage device region and the high-voltage device region. The trench isolation structure includes a trench-fill layer and a protective condition layer between the trench-fill layer and the substrate. The protective condition layer includes an amorphous silicon layer.

IPC Classes  ?

• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/762 - Dielectric regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A semiconductor structure includes a substrate, a conductive pillar, a capacitor structure and dummy pillar structures. The conductive pillar is disposed in the substrate. The capacitor structure is disposed in the substrate, and is separated from the conductive pillar. The dummy pillar structures are randomly distributed between the conductive pillar and the capacitor structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A semiconductor structure includes an SOI substrate having a base substrate, a buried oxide layer on the base substrate, and a device layer on the buried oxide layer, a circuit element disposed on the device layer and surrounded by a trench isolation region in the SOI substrate; an etch stop layer disposed around the circuit element; a first dielectric layer disposed on the etch stop layer; and a buried power rail embedded in the first dielectric layer, the etch stop layer, the trench isolation region, and the buried oxide layer. The buried power rail is isolated from the device layer through the buried oxide layer and trench-filling oxide in the trench isolation region.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/498 - Leads on insulating substrates

Abstract

A method for fabricating a semiconductor device includes the steps of first providing a substrate having a planar device region and a non-planar device region, forming fin-shaped structures on the non-planar device region, forming a first shallow trench isolation (STI) around the substrate on the planar device region, forming a second shallow trench isolation (STI) around the fin-shaped structures, forming first gate structures on the substrate of the planar device region, forming second gate structures on the fin-shaped structures, forming a first resistor on the first STI, and forming a second resistor on the second STI.

IPC Classes  ?

• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 84/01 - Manufacture or treatment

Abstract

ABSTRACT OF DISCLOSURE A semiconductor device includes a dielectric layer, a metal wire, and a plurality of via structures. The dielectric layer is disposed on a substrate, and the metal wire is disposed within the dielectric layer. The via structures are separately disposed within the dielectric layer, on the metal wire and physically contacting the metal wire. The via structures are arranged along a first direction and a second direction being perpendicular to the first direction, at least into a 2×2 array, wherein a ratio between a total area of the via structures and an area of the metal wire is greater than 0.13.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A patterning method including the following steps is provided. A first template including at least one first main pattern, first dummy patterns, and second main patterns is provided. The first dummy patterns are located aside the first main pattern. A density of the first main pattern is less than a density of the second main patterns. A first imprint material is provided on a first substrate. The first imprint material is imprinted by using the first template to form a first imprint layer. The first substrate is etched by using the first imprint layer as a mask to form a second template. A second imprint material is provided on a material layer. The second imprint material is imprinted by using the second template to form a second imprint layer. The material layer is etched by using the second imprint layer as a mask to form a patterned material layer.

IPC Classes  ?

• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/311 - Etching the insulating layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate and a top electrode on the MTJ; forming a first inter-metal dielectric (IMD) layer around the MTJ and the top electrode; forming a stop layer on the first IMD layer; forming a second IMD layer on the stop layer; performing a first etching process to remove the second IMD layer and the stop layer; performing a second etching process to remove part of the top electrode; and forming a metal interconnection to connect to the top electrode.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/10 - Magnetoresistive devices
• H10N 50/80 - Constructional details

Abstract

A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a passivation layer on the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on the passivation layer. Preferably, a top surface of the passivation layer between the first MTJ and the second MTJ is lower than a top surface of the passivation layer directly on top of the first MTJ.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10N 35/01 - Manufacture or treatment
• H10N 50/80 - Constructional details
• H10W 10/00 -
• H10W 10/10 -
• H10W 20/00 -

Abstract

A method for monitoring an electron beam of a measuring apparatus and a monitoring apparatus using the same are provided. The monitoring apparatus includes a transmission unit, a controlling unit, a frame analyzing unit, a shift analyzing unit, a determining unit and a warning unit. The controlling unit is configured to transmit a capturing command to the measuring apparatus, for continuously capturing a plurality of electron beam frames of the measuring apparatus, after the measuring apparatus is calibrated. The frame analyzing unit is configured to analyze a density concentration point in each of the electron beam frames. The shift analyzing unit is configured to obtain a largest shift among the density concentration points in the electron beam frames. The warning unit is configured to issue a warning notification to the measuring apparatus, if the largest shift is larger than a predetermined distance.

IPC Classes  ?

• H01J 37/28 - Electron or ion microscopesElectron- or ion-diffraction tubes with scanning beams

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes a high resistance impedance layer between a gate and a first metal structure in a vertical direction, wherein the first metal structure comprises at least one equipotential first metal and at least one non-equipotential first metal, wherein the equipotential first metal and the high resistance impedance layer have the same potential, the non-equipotential first metal and high resistance impedance layer have not the same potential, and the non-equipotential first metal and the high resistance impedance layer do not overlap in the vertical direction, and a minimum distance, between an edge of the high resistance impedance layer and an edge of the non-equipotential first metal in a horizontal direction perpendicular to the vertical direction, is larger than a size of a random defect.

IPC Classes  ?

• H01L 29/43 - Electrodes characterised by the materials of which they are formed
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A writing circuit includes a writing voltage generator, a reference voltage provider, and a comparison circuit. The writing voltage generator generates a writing voltage to perform a writing operation on each resistive memory cell among a resistive memory cell array. The reference voltage provider, during the writing operation, generates and provides a reference voltage according to a resistance of a reference device. The comparing circuit generates a comparison result by comparing the reference voltage with a target value. The writing voltage generator adjusts a maintenance time of the writing voltage according to the comparison result.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

A water leakage detection device and a detection method thereof are provided. The water leakage detection device includes a leakage sensing tape, a processor, an infrared imaging sensor and a wireless communication transmitting module. The leakage sensing tape is used to detect whether a water leakage occurs. The processor is electrically connected to the water leakage sensing tape. The infrared imaging sensor is connected to the processor. The infrared imaging sensor is used to detect a water leakage range. The wireless communication transmitting module is connected to the processor. The wireless communication transmitting module is used to transmit a water leakage detection result.

IPC Classes  ?

• G01M 3/16 - Investigating fluid tightness of structures by using fluid or vacuum by detecting the presence of fluid at the leakage point using electric detection means

Abstract

A bipolar junction transistor includes an emitter region, a base region, a collector region and an isolation structure. The base region is disposed adjacent to a first side of the emitter region. The collector region is disposed adjacent to a second side of the emitter region. The isolation structure is disposed between the emitter region and each of the base region and the collector region.

IPC Classes  ?

• H01L 29/735 - Lateral transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes

Abstract

A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

IPC Classes  ?

• H10W 90/00 -
• H10W 72/00 -
• H10W 90/22 -
• H10W 90/26 -

Abstract

A fan filter unit and a control method thereof are provided. The fan filter unit includes a fan and a control module. The control module includes a logic judgment circuit, a fan power supply and a control circuit. The logic judgment circuit is connected to an apparatus power supply of a semiconductor apparatus. The logic judgment circuit is used to judge whether the apparatus power supply is shut down. The control circuit is connected to the fan power supply and the logic judgment circuit. If the apparatus power supply is shut down, the control circuit switches a fan power supply path from the apparatus power supply to the fan power supply.

IPC Classes  ?

• B01D 46/46 - Auxiliary equipment or operation thereof controlling filtration automatic
• B01D 46/00 - Filters or filtering processes specially modified for separating dispersed particles from gases or vapours
• B01D 46/42 - Auxiliary equipment or operation thereof
• F04D 25/06 - Units comprising pumps and their driving means the pump being electrically driven
• F04D 27/00 - Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
• F04D 29/70 - Suction gridsStrainersDust separationCleaning

Abstract

The invention provides a layout pattern of a static random access memory, which comprises a first region adjacent to a second region, a first SRAM cell located in the first region, a first diffusion region in the first region, and a second SRAM cell located in the second region, which comprises a second diffusion region. A gate structure spans the first diffusion region and constitutes a first pass gate transistor of the first SRAM cell, and the gate structure spans the second diffusion region and constitutes a second pass gate transistor of the second SRAM cell, wherein the gate structure extends along a first direction, and the first diffusion region overlapping with the gate structure and the second diffusion region overlapping with the gate structure are not connected in the first direction.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A SiC MOSFET is provided in the present invention, including a SiC substrate, a gate oxide layer on the SiC substrate, an isolation oxide layer on the gate oxide layer, two gates respectively on the gate oxide layer at both sides of the isolation oxide layer, wherein the two gates are both provided with an extending part extending inwardly on the isolation oxide layer, two sources respectively in the SiC substrate at both sides of the gate oxide layer, and a drain contact metal on the other side of the SiC substrate opposite to the gate oxide layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/66 - Types of semiconductor device

Abstract

A semiconductor device includes a conductive structure, a first dielectric layer, a second dielectric layer and a liner layer. The conductive structure is located on a substrate. The first dielectric layer covers the conductive structure and the substrate. The second dielectric layer is located on the first dielectric layer. An air gap is present in the first dielectric layer and the second dielectric layer, and is located above the conductive structure. The liner layer covers and surrounds a middle portion of the air gap.

IPC Classes  ?

• H10W 20/46 -
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10W 20/00 -
• H10W 20/40 -
• H10W 20/41 -

Abstract

A method for fabricating a semiconductor device includes providing a substrate having a first region and a second region, forming a first gate dielectric layer on the first region, forming a second gate dielectric layer on the second region, and forming a first gate structure on the first gate dielectric layer and the second gate dielectric layer. Preferably, the first gate dielectric layer and the second gate dielectric layer have different thicknesses.

IPC Classes  ?

• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method for fabricating a semiconductor device includes the steps of forming a gate structure on a substrate, forming recesses adjacent to two sides of the gate structure, forming a buffer layer in the recesses, forming a first linear bulk layer on the buffer layer, forming a second linear bulk layer on the first linear bulk layer, forming a bulk layer on the second linear bulk layer, and forming a cap layer on the bulk layer.

IPC Classes  ?

• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
• H10P 14/20 -

Abstract

The invention provides a transistor. The transistor includes a well region arranged in a substrate, a gate structure arranged on the well region, a gate oxide layer, wherein a first portion of the gate oxide layer is thicker than a second portion of the gate oxide layer, a first doped region and a second doped region arranged in the well region, wherein along the horizontal direction, the distance between the first doped region and the first portion of the gate oxide layer is greater than the distance between the second doped region and the second portion of the gate oxide layer, and a salicide block located on the substrate and at one side of the gate structure, wherein the salicide block is located between the first portion of the gate oxide layer and the first doped region.

IPC Classes  ?

• H01L 29/51 - Insulating materials associated therewith
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The invention provides a method for manufacturing a semiconductor structure, which comprises the following steps: providing a substrate with a shallow trench isolation structure and a first active area, wherein a top surface of the shallow trench isolation structure is higher than a top surface of the substrate in the first active area, performing an etching step to remove part of the shallow trench isolation structure so that the top surface of the shallow trench isolation structure is lower than that of the substrate in the first active area, and after the etching step, a doping step is performed on the first active area.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/311 - Etching the insulating layers
• H01L 21/3115 - Doping the insulating layers
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device

Abstract

A fabricating method of an RRAM includes forming a bottom electrode that includes an inverted T-shaped profile followed by sequentially forming a resistive switching layer and a top electrode from bottom to top. The inverted T-shaped profile includes a bottom element and a vertical element disposed on the bottom element. The detailed process steps include forming a first metal layer and a dummy material layer covering the first metal layer. The dummy material layer is then etched to form a recess, exposing the first metal layer. A second metal layer is formed to fill the recess. After removing the dummy material layer, a resistive switching material layer and a third metal layer are formed in sequence. Finally, the third metal layer, the resistive switching material layer, and the first metal layer are patterned to form the top electrode, the resistive switching layer, and the bottom electrode.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A semiconductor device includes a first wafer and a second wafer. The first wafer includes a first substrate and a first inductance layer. The first inductance layer includes a first metal line and a first interconnect structure. The first metal line is disposed on the first substrate, and the first interconnect structure is electrically connected with the first metal line. The second wafer includes a second substrate and a second inductance layer. The second inductance layer includes a second metal line and a second interconnect structure. The second metal line is disposed on the second substrate, and the second interconnect structure is electrically connected with the second metal line. The second interconnect structure is bonded with the first interconnect structure, so that the first inductance layer and the second inductance layer together form an inductance element.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements

Abstract

An adjustable capacitor device and a method for adjusting a capacitance value are provided. The adjustable capacitor device includes a first variable resistor, a first comparator coupled between the first variable resistor and a first node, a first capacitor, a second capacitor, a first transistor coupled between the first node, the first capacitor and the second capacitor, and a second transistor coupled between the first node, the first capacitor and the second capacitor.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
• H10N 50/80 - Constructional details
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

A semiconductor device includes a III-V compound semiconductor layer, a silicon-doped III-V compound barrier layer, a silicon-rich tensile stress layer, a passivation layer, an ultraviolet (UV)-transparent protection layer, a gate structure, a source structure, and a drain structure. The silicon-doped III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The silicon-rich tensile stress layer is disposed on the silicon-doped III-V compound barrier layer. The passivation layer is disposed on the silicon-rich tensile stress layer. The UV-transparent protection layer is disposed on the passivation layer. The gate structure penetrates through the UV-transparent protection layer, the passivation layer, and the silicon-rich tensile stress layer. The gate structure is partly disposed in the silicon-doped III-V compound barrier layer. The source structure and the drain structure penetrate through the UV-transparent protection layer, the passivation layer, the silicon-rich tensile stress layer, and the silicon-doped III-V compound barrier layer.

IPC Classes  ?

• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
• H10D 30/01 - Manufacture or treatment
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions

Abstract

A method for forming a semiconductor device is disclosed. A substrate having a flash memory region and a logic device region is provided. At least one logic transistor is formed in the logic device region. At least one flash memory transistor is formed in the flash memory region. The at least one flash memory transistor comprises a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.

IPC Classes  ?

• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
• H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/23 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels

Abstract

A method for manufacturing a semiconductor device is provided. The method includes the following steps. First, a first semiconductor structure and a second semiconductor structure are provided. The first semiconductor structure includes a first conductive pillar and a first conduction layer connected to the first conductive pillar, and the second semiconductor structure includes a second conductive pillar and a second conduction layer connected to the second conductive pillar, wherein a material of the first conduction layer and a material of the second conduction layer are conductive material and are volatilizable at a predetermined temperature. Thereafter, the first semiconductor structure and the second semiconductor structure are bonded to combine the first conductive pillar with the second conductive pillar. After the step of bonding the first semiconductor structure and the second semiconductor structure is completed, the first conduction layer and the second conduction layer are disappeared.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A method for forming a semiconductor structure includes forming a conductive structure in a first dielectric layer, the conductive structure including an terminal portion and an extending portion, forming a second dielectric layer on the first dielectric layer, forming a first opening through the second dielectric layer directly above the extending portion and a second opening through the second dielectric layer directly above the terminal portion, a width of the second opening being smaller than 50% of a width of the first opening, forming a conductive material layer on the second dielectric layer and filling the first opening and the second opening, and performing a chemical mechanical polishing process to remove the conductive material layer outside the first opening and the second opening to obtain a conductive via in the first opening and a dummy via in the second opening.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

A semiconductor structure includes a first dielectric layer on a substrate, a conductive structure disposed in the first dielectric layer and including a terminal portion and an extending portion directly and physically connected to the terminal portion and extending away from the terminal portion, a second dielectric layer disposed on the first dielectric layer, a conductive via through the second dielectric layer and directly contacting the extending portion, a dummy via through the second dielectric layer and directly contacting the terminal portion, wherein the dummy via comprises a lower portion consisting of a first filling layer and an upper portion consisting of a second filling layer, wherein the first filling layer and the second filling layer comprise different materials.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices