A processing system including multiple devices each providing a data set, multiple comparators each operative to compare a selected pair of data sets, multiple multiplexers each for selecting from among coupled data sets and providing selected data sets to inputs of corresponding comparators, and a comparator configuration controller that controls each the multiplexers to select pairs of data sets provided to the corresponding comparators. The multiplexers provide flexible comparator reconfiguration for improved comparator availability. In the event of failure of a device using a comparator, the controller reconfigures the corresponding multiplexer to re-use the comparator for a similar or different comparison configuration. Data latch buffers and configurable delay gates may be provided between the multiplexers and the comparators. The buffers may have ports available to be loaded by software. Clock multiplexers may be provided to select a clock signal for each comparator based on usage.
A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
3.
NETWORK NODE FOR A MULTIDROP SINGLE PAIR ETHERNET AND CORRESPONDING METHOD
The present disclosure relates to a network node comprising a transceiver, that is galvanically isolated coupled to the network terminals of the network node, wherein the network not also comprises a test unit, which is galvanically connected to the network nodes, such that the test unit can apply a predefined common mode voltage at the network terminals and also configured to detect a structural fault of a network, which may be connected to the network terminals. The present disclosure also relates to a corresponding system and method.
H04L 41/06 - Gestion des fautes, des événements, des alarmes ou des notifications
H04L 43/0805 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux en vérifiant la disponibilité
4.
RECONCILIATION MODULE AND ASSOCIATED METHOD FOR COLLISION AVOIDANCE
A reconciliation module for a node of a multidrop bus network, the reconciliation module comprising circuitry configured to:
receive data sent from a MAC module of the node as part of a first attempt by the MAC module to transmit the data;
assert a collision signal by default on receipt of the data from the MAC module to stop the MAC module from continuing to send the data; and
control a sense signal to cause the MAC module to resend the data as part of a second transmission attempt such that the data may be transmitted on the multidrop bus network via a PHY module of the node at an upcoming transmit opportunity.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
A reconciliation module for a node of a multidrop bus network, the node comprising a MAC module and a PHY module, the reconciliation module comprising circuitry configured to:
receive data from the MAC module for transmission on the multidrop bus network via the PHY module at a transmit opportunity of the node;
assert a sense signal on receipt of the data from the MAC module; and
delay de-assertion of the sense signal after transmission of the data to facilitate the transmission of further data at the next transmit opportunity of the node.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
A memory includes at least one memory bank which includes a set of memory arrays. Each memory cell includes a plurality of memory cells. The at least one memory bank includes: multiple word lines each connected to a corresponding row of the memory cells; a first decoder configured to receive address data, and decode the address data to provide intermediate data; a second decoder located in a central area of the memory bank between ones of the set of memory arrays, and configured to receive the intermediate data from the first decoder, and decode the intermediate data to provide selection data to the word lines. Memory cells addressable by a respective word line designated by the selection data are configured to be addressable by means of that selection data.
A three-dimensional structured light camera device includes a LUT memory configured to store a reference speckle image of a 3D target object and a processor. The processor is configured to perform object detection on a target speckle image, perform sub-pixel-level (SPL) processing that includes a plurality of interpolations of the reference speckle image and the target speckle image, perform an adaptive binarization process wherein the adaptive binarization process searches the LUT memory for SPL speckle features of the stored reference speckle image that match SPL speckle features of the SPL target speckle image, find SPL speckle features of the target speckle image that match searched SPL speckle features of the stored reference speckle image, and perform a depth value calculation of the 3D target object in response to the plurality of interpolations and the found SPL speckle features of the target SPL speckle image.
G06T 7/521 - Récupération de la profondeur ou de la forme à partir de la télémétrie laser, p. ex. par interférométrieRécupération de la profondeur ou de la forme à partir de la projection de lumière structurée
G02B 27/48 - Systèmes optiques utilisant la granulation produite par laser
A reconciliation module for a node of a multidrop bus network, the node comprising a MAC module and a PHY module, the reconciliation module comprising circuitry configured to:
assert a sense signal until the beginning of each transmit opportunity of the node;
de-assert the sense signal at that moment to cause the MAC module to send available data to the reconciliation module to start transmission of the data on the multidrop bus network via the PHY module at the respective transmit opportunity; and
re-assert the sense signal on receipt of the data from the MAC module or time-out of the respective transmit opportunity.
H04L 12/413 - Réseaux à ligne bus avec commande décentralisée avec accès aléatoire, p. ex. accès multiple avec détection de porteuse et détection de collision [CSMA-CD]
An RF device includes a first channel with a first frequency band, configured to receive a first signal; and a second channel with a second frequency band, configured to receive a second signal. The first frequency band and the second frequency band are different. The device includes control circuitry configured to obtain a first channel response associated with the received first signal at the first channel, to obtain a second channel response associated with the received second signal at the second channel and to calibrate the first channel response and the second channel response by steering to a calibration base. The control circuitry is further configured to calibrate the first channel response and second channel response by channel stitching to obtain a combined channel response.
A three-dimensional structured light camera device includes a LUT memory and a processor configured to perform object detection and identify a 3D object area of interest of a target speckle image and perform a local adaptive binarization process that searches the LUT memory for speckle features of a stored reference speckle image and matches speckle features of the target speckle image with the searched speckle features of the reference speckle image. In some examples, the processor may perform a morphological operation on matched speckle features of the target speckle image that generates a noise-reduced target speckle image; and perform binary encoding compression. A depth value calculation of the 3D target object is performed in response to the binary encoding compression performed on the noise-reduced target speckle image. In this manner, speckle matching can be accelerated with a lower number of calculations.
H04N 13/254 - Générateurs de signaux d’images utilisant des caméras à images stéréoscopiques en combinaison avec des sources de rayonnement électromagnétique pour l’éclairage du sujet
G06T 7/514 - Récupération de la profondeur ou de la forme à partir des spécularités
G06T 7/521 - Récupération de la profondeur ou de la forme à partir de la télémétrie laser, p. ex. par interférométrieRécupération de la profondeur ou de la forme à partir de la projection de lumière structurée
A device includes a filter circuit having both a transformer and a notch filter. The notch filter is formed via capacitive cross-coupling of windings of the transformer. The transformer includes a first winding with an input terminal and an output terminal and a second winding with an input terminal and an output terminal. The notch filter is formed by coupling a first capacitor between the input terminal of the first winding and the output terminal of the second winding, and by coupling a second capacitor between the output terminal of the first winding and the input terminal of the second winding.
A radar device including a radar function, a driver configured to control a pass device, and a radar controller. The radar function is configured for generating radar frames in a first mode for generating high isolation frames and in a second mode for generating low isolation frames. The radar function has a supply voltage input and is configured to operate with the supply voltage input at a radar supply voltage level. The radar controller configures the driver for controlling the pass device to regulate voltage provided to the supply voltage input of the radar function at the radar supply voltage level with high power supply rejection ratio to minimize ripple voltage when the radar function is in the first mode, and configures the driver to force the pass device into a bypass mode to reduce power dissipation when the radar function is in the second mode.
An inverter circuit, usable in a clock buffer circuit, includes a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to an input node and first current electrodes of the first and second transistors are coupled at an output node. The inverter circuit also includes a first set of additional transistors of the first conductivity type, a second set of additional transistors of the second conductivity type, and a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period.
A compensation system for a crystal oscillator including a DC level comparator, current compensation circuitry, and a compensation controller. The crystal oscillator includes an amplifier with a feedback resistance coupled between first and second terminals of a crystal resonator. The DC level comparator may be a hysteretic comparator that compares a DC level of the first node with a DC level of the second node and to provide a corresponding compensation signal. The compensation controller controls a magnitude and direction of the compensation current applied to the first node by the current compensation circuitry based on the compensation signal. The current compensation circuitry sources current to or sinks current from the first node until the leakage current is minimized. The compensation controller may include a digital counter the generates a digital control value used to activate selected current sources or sinks for developing the compensation current.
H03B 5/36 - Production d'oscillation au moyen d'un amplificateur comportant un circuit de réaction entre sa sortie et son entrée l'élément déterminant la fréquence étant un résonateur électromécanique un résonateur piézo-électrique l'élément actif de l'amplificateur comportant un dispositif semi-conducteur
A device includes a first radio controller configured to communicate using a first protocol, and a pseudo random number generator configured to generate a pseudo random output value based on an input data value. The device includes a processor configured to determine a preamble code based on an output of the pseudo random number generator, and process a data packet received using the first radio controller using the preamble code to generate a processed data packet.
A REE can approve or deny authentication based on a sensor output signal and a secure element (SE) operatively coupled to the REE can detect a replay attack. A feature extractor produces a feature vector from the sensor output signal. The feature vector can be used to authenticate a user. Detecting the replay attack can include storing previous feature vectors, sending a security breached signal to the REE in response to determining that the feature vector equals one of the previous feature vectors, and storing the feature vector as one of the previous feature vectors. The REE can deny authentication in response to receiving the security breached signal.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/32 - Authentification de l’utilisateur par données biométriques, p. ex. empreintes digitales, balayages de l’iris ou empreintes vocales
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
17.
TRANSMIT POWER CONTROL FOR AUTOMOTIVE RADAR SENSING
A system and method are presented. A plurality of target objects are determined by a radar system. Each target object in the plurality of target objects is associated with a distance value and a velocity value. A power reduction factor is determined using the distance value and the velocity value associated with each target object of the plurality of target objects. A second radar signal is transmitted at a second power level determined by the power reduction factor.
A method of operating a plurality of communications nodes in a 10BASE-T1S Ethernet network. The plurality of communications nodes are configured to implement a physical layer collision avoidance, PLCA, process. At least two of the communications nodes are candidate beacon generators. The method comprises: for each of the at least two candidate beacon generators, determining a time delay since a last received beacon, comparing the determined time delay with a threshold value associated with the candidate beacon generator, and if the time delay exceeds the threshold value then setting that candidate beacon generator as an in-use beacon generator; and the in-use beacon generator transmitting a beacon to define the start of a PLCA cycle, thereby triggering a transmit opportunity for each of the other communication nodes.
There is described a communication device, configured to perform a single-sided two-way-ranging, SS-TWR, communication with a further communication device, the communication device comprising a control device being configured to:
i) transmit a first SS-TWR signal to the further communication device,
ii) receive a second SS-TWR signal, associated with the first SS-TWR signal, from the further communication device,
iii) evaluate a carrier frequency offset of the received second SS-TWR signal, and
iv) determine, based on the evaluation, if an attack is performed to the SS-TWR communication.
A method is provided for detecting a proximity of a radio frequency (RF) field during an ongoing RF activity by a wireless device operating in reader mode. In the method, an input signal is modulated to provide a modulated RF signal comprising a plurality of RF modulation periods. The plurality of RF modulation periods are transmitted by the wireless device operating in the reader mode. An RF detector is enabled to monitor the plurality of modulation periods during the transmitting of the plurality of RF modulation periods. An external RF signal is detected when a characteristic of the plurality of RF modulation periods is different from an expected characteristic. In another embodiment, a wireless device is provided that implements the method.
A radar system and methods of operating radar system are provided. The radar system includes transmitter groups, each including transmitter modules, configured to transmit multiple transmit signals in accordance with a Random Time Division Multiplexing (RTDM)-Doppler Domain Multiplexing (DDM) scheme, a receiver modules configured to receive reflections of the transmit signals reflected by at least one object and to generate digital signals based on the received reflections, and a controller that includes a signal processor configured to generate multiple range-Doppler antenna cubes (RDACs) based on the reflections of the plurality of transmit signals, each of the multiple RDACs corresponding to a respective transmitter group of the transmitter groups, generate a combined range-Doppler map (RDM) by integrating the multiple RDACs, and generate object position data based on the combined RDM.
An integrated circuit (IC), including a recording circuit and a clocking system, is provided. During a capture phase of an at-speed testing of the IC, the recording circuit records a number of clock pulses of a test clock signal and generates configuration data indicative of the recorded number of the clock pulses. The clocking system receives a reference clock signal and the configuration data and generates an at-speed clock signal. During the capture phase, the at-speed clock signal includes clock pulses that are extracted from the reference clock signal based on the configuration data. A count of the extracted clock pulses is equal to the recorded number of clock pulses of the test clock signal. The at-speed testing of the IC is enabled based on the at-speed clock signal.
A power-on reset (POR) circuit includes first and second trip detector circuits. The first trip detector circuit generates a reset signal indicative of a state of a supply voltage based on a trip node voltage that ramps up when the supply voltage ramps up. The reset signal is asserted when the trip node voltage exceeds a threshold value. The second trip detector circuit generates a control signal based on the supply voltage and a reference voltage. The reference voltage is less than the supply voltage until the supply voltage ramps down. During the ramp-down of the supply voltage, the supply voltage falls below the reference voltage, and the control signal is asserted when the supply voltage is less than the reference voltage by a different threshold value. The asserted control signal results in the trip node voltage being altered such that the reset signal is de-asserted.
H03K 17/22 - Modifications pour assurer un état initial prédéterminé quand la tension d'alimentation a été appliquée
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
24.
SYSTEM AND METHOD OF DYNAMIC HARDWARE RECONFIGURATION DURING FAILURE OF DEVICE IN A LOCK-STEP CONFIGURATION TO IMPROVE AVAILABILITY
A hardware reconfiguration system for first and second devices is in a lock-step configuration using a comparator that provides a lock-step error indication. The system includes at least one register that stores a lock-step threshold. The system also includes a lock-step monitor configured to compare a count of occurrences of the lock-step error indication from the comparator with the lock-step threshold. When the lock-step threshold is reached, the lock-step monitor is configured to enter a repair state to determine which one of the first and second devices is operating correctly and reconfigure operation into a split-lock mode to resume operation using the one of the first and second devices that is operating correctly.
G06F 11/18 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage passif du défaut des circuits redondants, p. ex. par logique combinatoire des circuits redondants, par circuits à décision majoritaire
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
The present invention relates to a system and method for determining of a mechanical deformation of a battery based on an influence on an ultra wideband, UWB, signal 120, which is transmitted between two UWB units of the system, where one of the UWB units is part of a control module of the system, wherein the control module also comprising a control unit being configured to be connected to a battery cell 116 of the battery 118 for controlling and/or monitoring the battery cell 116.
G01B 15/06 - Dispositions pour la mesure caractérisées par l'utilisation d'ondes électromagnétiques ou de radiations de particules, p. ex. par l'utilisation de micro-ondes, de rayons X, de rayons gamma ou d'électrons pour mesurer la déformation dans un solide
A receiver circuit receives an input voltage waveform from a single wire and generates an output bit stream. The receiver includes a voltage determination circuit which indicates whether a voltage level of the input voltage waveform has one of a high level that is higher than a high voltage threshold, a low level that is lower than a low voltage threshold, or a mid level that is between the high and low voltage levels. The receiver includes a bit value generator which provides a next bit value of the output bit stream as a first value when the voltage level is the high level, as a second value when the voltage level is the low level, and as a same value as an immediately previous bit value of the output bit stream when the voltage level is the mid level. The first and second values correspond to opposite logic states.
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
27.
SEMICONDUCTOR DEVICE WITH ENHANCED SOLDERABILITY AND METHOD THEREFOR
A method of forming a semiconductor device is provided. The method includes mounting a semiconductor die on a die pad of a leadframe. The die pad includes a central opening configured to expose a central portion of the semiconductor die. A first end of a bond wire is attached to a bond pad of the semiconductor die and a second end of the bond wire is attached to a lead of the leadframe. An encapsulant encapsulates the semiconductor die and the leadframe. A portion of the lead and a portion of the die pad are exposed and protruded through the encapsulant.
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A method for checking a computation of a discrete Fourier transform (DFT), including: computing a first layer of the DFT using a plurality of butterfly operations on inputs to the first layer to produce first outputs; computing a second layer of the DFT using a plurality of butterfly operations on the first outputs to produce second outputs; performing an invariant check on the first outputs after the computation of the second layer based upon the inputs to the first layer; and indicating a fault in the computation of the DFT when the invariant check fails.
An interference signal reduction system and method of interference signal reduction is described. An input signal includes a plurality of signal segments (frames). The input signal is provided to a machine learning model trained to output an estimate of a desired target signal from the input signal. Each signal segment maybe classified as a target-only signal segment, an interference-only signal segment, or an undefined signal segment. The machine learning model may be adapted based on the target-only signal segments and the interference-only signal segments.
G10L 21/0216 - Filtration du bruit caractérisée par le procédé d’estimation du bruit
G06V 10/764 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant la classification, p. ex. des objets vidéo
G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
G10L 25/21 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant l’information sur la puissance
G10L 25/57 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation pour le traitement des signaux vidéo
G10L 25/84 - Détection de la présence ou de l’absence de signaux de voix pour différencier la parole du bruit
30.
RADAR INTERFERENCE MITIGATION AND TARGET RADAR DATA GAP FILLING
A radar interference mitigation method includes producing a plurality of frequency data sets from digitized samples generated from a received radar signal. Each frequency data set of the plurality of frequency data sets is associated with one received chirp reflection of a plurality of radar chirp reflections in the received radar signal. The method also includes determining a threshold based on magnitudes of samples across the plurality of frequency data sets. The method further includes suppressing samples in the plurality of frequency data sets that exceed the threshold to produce a plurality of modified frequency data sets. The range of one or more targets is computed based on the plurality of modified frequency data sets.
Securing protocol keys in a communication node comprises transferring a protocol access key stored in a secure enclave of a secure host platform to a secure key store in a communication platform via a secure transfer. The protocol access key which is plaintext is secure from access by a host processor of the secure host platform. A protocol key stored in the secure enclave is encrypted to an encrypted protocol key. The encrypted protocol key is transferred from the secure enclave to the communication platform over an unsecure bus. The encrypted protocol key is deciphered based on the protocol access key in the communication platform to form the protocol key. The protocol key which is plaintext is secured from access by the host processor, the communication controller, or both.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
A method of performing a Dilithium signature operation on a message M using a secret key sk, including: calculating a value {tilde over (r)} based upon w0, c, and s2, where w0 and c are calculated as part of the Dilithium signature operation and s2 is part of the secret key sk; performing a bound check on {tilde over (r)} based upon γ2 and β, where γ2 and β are parameters of the Dilithium signature operation; calculating a hint h based on the value {tilde over (r)} and deleting the value {tilde over (r)} in a memory; regenerating a value y using an ExpandMask function; calculating z based upon y, c, and s1, where s1 is part of the secret key sk and replacing y with z in the memory; performing a bound check on z based on γ1 and β, where γ1 is a parameter of the Dilithium signature operation; and returning a digital signature of the message M where the digital signature includes z and h.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
In implementations of signal processing for OFDM radar systems, an OFDM transceiver of an ISAC system is operated in full-duplex mode in a downlink communication phase. The ISAC system generates sensing symbols for an OFDM radar system by combining OFDM communication symbols and repetitions of the OFDM communication symbols as the sensing symbols. The OFDM transceiver attenuates subcarriers of received sensing symbols for processing by the OFDM radar system to increase a signal-to-noise ratio of the received sensing symbols.
A bipolar transistor and a method of making a bipolar transistor. The method includes providing a semiconductor substrate having a major surface, one or more layers located beneath the major surface for forming an intrinsic base, and a collector. The method also includes depositing a first oxide layer on the major surface, depositing a second oxide layer on the first oxide layer, and depositing an extrinsic base layer on the second oxide layer. The method further includes forming an emitter window through the extrinsic base layer. The method also includes removing at least a part of the second oxide layer to form a first cavity and forming an initial part of a base link region in the first cavity. The method also includes removing at least a part of the first oxide layer to form a second cavity and filling the second cavity to form a completed base link region.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A semiconductor device includes at least a first cell and a second cell. Each of the first and second cells includes: a first well of a first conductivity type; a second well in the first well, wherein the second well has a second conductivity type opposite the first conductivity type; and a discharge pin connected to the second well. The semiconductor device further includes a discharge path connected between the discharge pins of the first and second cells, such that the second wells of the first and second cells are on a same electric potential. A method of fabricating the semiconductor, and a method of designing the semiconductor device are also described.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
Aspects of the subject disclosure may include, for example, monitoring first data to identify a first plurality of test points, analyzing the first plurality of test points to identify the first data as being associated with a first time domain included in a plurality of time domains, wherein respective portions of a device under test (DUT) are operative in accordance with a given time domain included in the plurality of time domains, and based on the analyzing of the first plurality of test points, generating first control signals to cause a first clock signal to be adapted to generate a second clock signal that is different from the first clock signal.
A fault reaction handling time interval (FRTI) for a reaction to the fault is determined based on a domain identifier (DID) indicative of an application associated with a fault. A first reaction to recover from the fault is signaled and then a determination is made whether a safe state is reached after the FRTI. Based on the safe state not being reached, a second FRTI is determined for a second escalated reaction, the second FRTI also being based on the DID. Typically, the second reaction results in less system availability so by defining the FRTI based on the DID sufficient time is allowed for reaching a safe state before the reaction is escalated.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
38.
METHOD AND APPARATUS TO IDENTIFY PRESENCE OF A NEAR FIELD COMMUNICATION (NFC) CARD OR INTERFERENCE FROM A POLLER OR LISTENER OF A MULTIPLE POLLER NFC WIRELESS CHARGING SYSTEM
Wireless charging comprises halting a listener from responding to communication from a poller, wherein the poller and the listener form a charging pair. The poller then transmits a plurality of requests in response to halting the communication with the listener and receives a corresponding response to the plurality of requests. At least one corresponding response to the plurality of requests is received and a number of bits in the received response which is in error compared an expected bit sequence of a response to a transmitted request is counted. A determination is made whether a near field communication (NFC) card is in proximity to the wireless charger based on the count of the number of bits and the wireless charging is performed based on the determination.
H04B 5/00 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive
H02J 50/60 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique sensibles à la présence d’objets étrangers, p. ex. détection d'êtres vivants
A method for transferring eSIM profile data from a first wireless communication device having a first eUICC device to a second wireless communication device having a second eUICC device includes providing encrypted eSIM profile data together with encrypted confidential user data on the first eUICC device, where the encrypted eSIM profile data has been encrypted by means of profile encryption keys, and the encrypted confidential user data has been encrypted at least partially by means of a user key. The method also includes transferring the encrypted eSIM profile data together with the encrypted confidential user data from the first eUICC device to the second eUICC device, and decrypting and installing the encrypted eSIM profile data on the second wireless communication device. The confidential user data are decrypted and installed on the second wireless communication device at least partially by means of the user key.
H04W 12/033 - Protection de la confidentialité, p. ex. par chiffrement du plan utilisateur, p. ex. trafic utilisateur
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04W 8/18 - Traitement de données utilisateur ou abonné, p. ex. services faisant l'objet d'un abonnement, préférences utilisateur ou profils utilisateurTransfert de données utilisateur ou abonné
40.
RF communication device for adaptive detection of further RF communication devices
A first radiofrequency (RF) communication device is configured to detect whether an external device is an active RF communication device or a passive RF communication. The first device triggers transmission of a first RF signal and a second RF signal. The first device detects that the external device is an active device based on the first RF signal and/or that the external device is a passive device based on the second RF signal.
A device may include at least one transmitter unit and at least one receiver unit, wherein the at least one transmitter unit and the at least one receiver unit are configured to transmit and receive radar signals, wherein the at least one transmitter unit and the at least one receiver unit are co-located with a vehicle. A device may include a radar processor, configured to: determine an occupancy map, wherein the occupancy map identifies a location of an object with respect to the automotive radar system, determine, using the occupancy map, a beamforming weight vector w, and transmit, using the at least one transmitter unit, the radar signal using the beamforming weight vector w.
A magnetic cover is disclosed which is configured to be positioned on a wireless charging transmitter. The magnetic cover comprises: a magnetic ring positioned on the magnetic cover, wherein when the magnetic cover is positioned on a wireless charging transmitter, the magnetic ring encompasses a center planar charging coil of the wireless charging transmitter; and a plurality of passive identification circuits, each identification circuit having a respective resonance frequency. When the magnetic cover is positioned over a wireless charging transmitter, the plurality of passive identification circuits overlaps with a side planar charging coil of the wireless charging transmitter and the side planar charging coil overlaps with center planar charging coil. The disclosed magnetic cover is facilitates detection by the wireless charging transmitter and wireless charging in accordance with magnetic power profile (MPP) charging.
H02J 50/12 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif du type couplage à résonance
G01V 3/10 - Prospection ou détection électrique ou magnétiqueMesure des caractéristiques du champ magnétique de la terre, p. ex. de la déclinaison ou de la déviation fonctionnant au moyen de champs magnétiques ou électriques produits ou modifiés par les objets ou les structures géologiques, ou par les dispositifs de détection en utilisant des cadres inducteurs
43.
Distortion Correct based on First Come First Serve Method
Distortion correction from a distorted source image to a distortion corrected target image includes dividing the target image into a plurality of target tiles. The source image is divided into source tiles. Each source tile corresponds to a target tile according to a first mapping. The source tiles are processed to produce a source tile index until all the source tiles in the source image have been assigned a source tile index value in an ascending order. At least one y coordinate value of a first target tile is higher than a y coordinate value of a second target tile, wherein the first target tile corresponds to a source tile that appears earlier in the ascending order of the source tile index than a corresponding source tile of the second target tile. Distortion correction of the source image is performed by mapping each source tile to its corresponding target tile.
G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction
H04N 25/61 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit le bruit provenant uniquement de l'objectif, p. ex. l'éblouissement, l'ombrage, le vignettage ou le "cos4"
44.
UTILIZATION OF SACRIFICIAL MATERIAL FOR CURRENT ELECTRODE FORMATION
A process for making a transistor that includes removing a sacrificial material under a base layer that includes dopants for an intrinsic base of a transistor. After the removal of the sacrificial layer to form a cavity directly under the base layer, a semiconductor material is formed in the cavity. The semiconductor layer includes dopants for a current electrode of the transistor that is located directly under the intrinsic base of the transistor.
An analog-to-digital converter (ADC) includes a digital-to-analog converter (DAC), a comparator coupled to an output of the DAC, a successive approximation register (SAR) logic unit coupled to an output of the comparator, and a programmable delay unit. The comparator includes a preamplifier having an input coupled to the output of the DAC and a latch having an input coupled to the output of the preamplifier and an output coupled to the input of the SAR logic unit. SAR logic unit generates a control signal, and programmable delay unit adjusts a delay between the control signal and a delayed control signal based on at least one parameter, such that comparator receives control signal and delayed control signal. In some implementations, the parameter is at least one of a frequency of a signal input to the DAC, a source impedance of a circuit driving the input signal, and a preamplifier power mode.
A method of performing a Dilithium signature operation on a message M using a secret key sk, including: generating a polynomial y using an ExpandMask function; calculating a polynomial z based upon y, c, and s1; performing a bound check on z based upon γ1 and β; performing a bound check on ct0 based upon γ2; calculating a polynomial {tilde over (r)} based upon A, z, c, t, α, and w1; performing a bound check on {tilde over (r)} based upon γ2 and β; calculating a hint polynomial h based on the {tilde over (r)}; and returning a digital signature of the message M where the digital signature includes z and h.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
In accordance with a first aspect of the present disclosure, a key fob is provided, comprising: a wireless interface for establishing a wireless connection to a controller integrated in a vehicle, wherein the wireless connection enables the key fob to provide access credentials to said controller; a wired interface for connecting the key fob to a console integrated in the vehicle, such that the key fob is usable for carrying out wireless charging of an external mobile device and/or for acting as an anchor device for performing ranging operations with said external mobile device. In accordance with a second aspect of the present disclosure, a corresponding method of configuring a key fob is conceived.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
B60R 25/24 - Moyens pour enclencher ou arrêter le système antivol par des éléments d’identification électroniques comportant un code non mémorisé par l’utilisateur
H02J 50/10 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant un couplage inductif
48.
RADAR SIGNAL INTERFERENCE MITIGATION WITH GENERATIVE NETWORKS
A system includes a transmitter configured to transmit a radar signal towards a target object. A receiver is configured to receive a received signal in response to the transmitted radar signal. The system includes a processor configured to receive, using the receiver, a received signal, execute an iterative procedure using a desired signal prior and an interference signal prior and to determine an estimate of an interference signal component of the received signal and an estimate of the desired signal component of the received signal, wherein the interference signal prior is determined using generative modeling and each iteration of the iterative procedure executes a data consistency operation, use the estimate of the interference signal component and the received signal to determine a desired signal, and processing the desired signal to determine an attribute of the target object.
A method and apparatus for generating a vehicle acoustic alert signal for a vehicle comprising an acoustic vehicle alerting system (AVAS) is described. The method includes detecting and classifying an object. If the object is classified as a vulnerable road user (VRU), one or more VRU characteristics such as distance and velocity of the VRU are determined. An acoustic alert signal is generated and transmitted via the AVAS dependent on the at least one VRU characteristic. The at least one VRU characteristic is transmitted to a further vehicle for use in determining how the further vehicle generates an acoustic alert signal.
A fault tolerant DC-DC converter including a transformer and a pair of mirrored power converters. The transformer has a primary inductance driven by a power supply and has a secondary inductance with an intermediate tap. A main power converter includes first and second current control devices, a first inductance, and a first capacitance coupled to the secondary inductance for developing a main voltage output. A mirrored power converter includes third and fourth current control devices, a second inductance, and a second capacitance also coupled to the secondary inductance for developing a mirrored voltage output. Output circuitry couples to the main and mirrored power converters to share power to a load, such as a battery. The output circuitry may be configured as a buck boost converter that is responsive to a failure of any of the current control devices to maintain the primary output voltage level at a regulated level.
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 3/06 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A measurement apparatus comprising: an input configured to receive current measurements for each phase of a plurality of phases output by an inverter; and an estimator block configured to receive the current measurements at a first time; and receive at least two inverter control signals for control of the output of the inverter at the first time; and calculate an disturbance-estimation using an Unknown Input Observer, UIO, method; and a comparison block configured to receive the current measurement for each phase at a future, second time; and identify which of the plurality of phases is experiencing a measurement failure in the current measurement for that phase based on the current measurements for each phase at the second time and the disturbance-estimation.
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 7/5387 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur dans une configuration en pont
52.
DATA PROCESSING SYSTEM HAVING TAGGED AND UNTAGGED ADDRESS POINTERS AND METHOD FOR ACCESSING A LOCATION IN THE DATA PROCESSING SYSTEM
A data processing system is provided that includes a processor and a memory. The processor is configured to execute instructions to access a location pointed to by an address pointer. The memory is coupled to the processor and configured to have a plurality of memory portions. A first address pointer for accessing a first portion of the memory includes a type bit field, a tag bit field, and a first address bit field. A second address pointer for accessing a second portion of the memory is configured to have only the type bit field and a second address bit field without the tag bit field. The type bit field is set to a first value for the tagged pointer and a second value for the untagged pointer. In another embodiment, a method is provided for accessing a location in the data processing system.
A method is described for proving erasure of a memory. In the method a prover device receives a seed value from a verifier device. The prover device generates a series of data blocks starting with the seed value and a function. The series of data blocks is generated using the function and the seed to generate a first data block of the series of data blocks. Each subsequent data block is generated using the function and a preceding data block until a last data block of the series of data blocks is generated and written to the memory portion. The prover device writes the series of data blocks to the memory to overwrite all memory contents of a memory portion of the prover device. After the data blocks are written to the memory by the prover device, the prover device sends notification of memory erasure to the verifier device.
One example discloses a peripheral device, including: a radio receiver configured to, receive a first set of audio packets transmitted over a first wireless link from a first central device, and receive a second set of audio packets transmitted over a second wireless link by the second central device; and a processor configured to predict a collision between the first set of audio packets and the second set of audio packets based on a set of transmission scheduling parameters.
A method of forming a semiconductor device is provided. The method includes forming a redistribution layer (RDL) substrate over an active side of a semiconductor die. The RDL substrate includes a plurality of under-bump metallization (UBM) structures. A die pad of a leadframe is affixed on a backside of the semiconductor die. The leadframe includes a plurality of leads having a first portion of each lead connected to the die pad and a second portion of each lead extending vertically along sidewalls of the semiconductor die toward a plane of the RDL substrate. An encapsulant encapsulates the semiconductor die and the leadframe, a lead tip portion of each lead is exposed through the encapsulant.
Techniques for using machine learning to produce sensor data from vision sensor data are disclosed. By using a limited amount of sensor data together with vision sensor data, a deep learning network can be trained to produce estimated sensor point cloud distributions from, e.g., vision sensor data alone. Using a deep learning network trained in this way, vehicles with limited or no other sensor functionality can be equipped with a camera to produce estimated sensor point cloud distributions. The estimated sensor point cloud distributions can then be used to improve vehicle safety through vehicle controls or driver notifications and/or to produce enhanced sensor data.
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G01S 13/89 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
57.
VEHICLE SENSOR POINT CLOUD PROBABILITY DENSITY FUNCTION ESTIMATION BASED ON VISION SENSOR DATA
Techniques for using machine learning to produce vehicle location sensor data from vision sensor data are disclosed. By using a limited amount of vehicle location sensor data together with vision sensor data, a deep learning network can be trained to produce estimated vehicle location sensor point cloud distributions from, e.g., vision sensor data alone. Using a deep learning network trained in this way, vehicles with limited or no sensor functionality can be equipped with a camera to produce estimated vehicle location sensor point cloud distributions. These estimated vehicle location sensor point cloud distributions can then be compared with general sensor point cloud distributions to improve detection of vehicles, environmental objects, and ghost objects, and subsequently used to improve vehicle safety through vehicle controls or driver notifications and/or to produce enhanced sensor data.
G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p. ex. véhicules ou piétonsReconnaissance des objets de la circulation, p. ex. signalisation routière, feux de signalisation ou routes
G01S 13/89 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la cartographie ou la représentation
G06V 10/75 - Organisation de procédés de l’appariement, p. ex. comparaisons simultanées ou séquentielles des caractéristiques d’images ou de vidéosApproches-approximative-fine, p. ex. approches multi-échellesAppariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques utilisant l’analyse de contexteSélection des dictionnaires
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
58.
SYSTEM AND METHOD FOR COMPUTING MODERN CRYPTOGRAPHIC PRIMITIVES WITH CLASSIC CRYPTOGRAPHIC INTERFACES
A method for carrying out an elliptic curve based cryptographic operation using a cryptographic processor with a first elliptic curve and α fixed interface, including: converting a second point on a second elliptic curve to a first point on the first elliptic curve using a first function interface of the cryptographic processor and a second function interface of the cryptographic processor; performing a point multiplication on the first point to produce a third point on the first elliptic curve using a point multiplication interface of the cryptographic processor; and converting the third point on the first elliptic curve to a fourth point on the second elliptic curve using the first function interface of the cryptographic processor and the second function interface of the cryptographic processor, wherein the first function interface of the cryptographic processor computes r+h·d mod n and the second function interface of the cryptographic processor computes x−1 mod n.
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
59.
METHOD AND CONTROL UNIT FOR TRANSFERRING eSIM PROFILE DATA
A method for transferring eSIM profile data from a first eUICC device to a target entity includes providing encrypted eSIM profile data on the first eUICC device, the encrypted eSIM profile data having been encrypted by means of profile encryption keys. The method further includes transferring the encrypted eSIM profile data from the first eUICC device to the target entity, and deleting the encrypted eSIM profile data from the first eUICC device. The method further includes transferring the profile encryption keys from the first eUICC device to the target entity only after completion of steps of transferring and deleting the encrypted eSIM profile data. The method further includes decrypting the encrypted eSIM profile data by means of the profile encryption keys and installing the decrypted eSIM profile data on the target entity.
The disclosure relates to performing a proximity check to determine whether a transponder device is in proximity of a reader device. In an example embodiment, a method of performing a proximity check to determine whether a transponder device (220) is in proximity of a reader device (210) comprises: transmitting a command (231, 401, 507) from the reader device (210) to the transponder device (210), the command (231, 401, 507) including a request for a measured response time for a number n of previous command-response exchanges (503-506) stored by the transponder device (220); in response to receiving the command (231, 401, 507) at the transponder device (220), transmitting a response (402, 508) to the reader device (210), the response (402, 508) including a measured response time (4031-n) stored by the transponder device (220) for the previous n command-response exchanges (503-506); and determining whether a predetermined criterion for the proximity check is fulfilled by comparing a measured response time stored by the reader device (210) with the measured response time transmitted by the transponder device (220) in the response (402).
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
Methods and systems for multi-modal security access control for a System on a Chip (SoC) are disclosed herein. In an example embodiment, a method includes providing a secure enclave including a plurality of bus masters and a Sentinel Resource Domain Controller (SRDC), and receiving a request to access a control, asset, or resource. The method further includes assessing a plurality of attributes that include each of: a first attribute that is a privilege mode attribute; a second attribute that concerns an applicability or inapplicability of a Runtime Root of Trust (RROT) mode; a third attribute relating to a bus master type; and a fourth attribute related to a security state. The method additionally includes determining, based upon the attributes, whether the request is granted or denied, and causing the control, asset, or resource to which the request is directed to be accessible or inaccessible based upon the determining.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c.-à-d. avec au moins un mode sécurisé
62.
DIGITAL CHIRP OFDM RADAR AND RADAR SENSING METHODS
A radar transceiver includes a radar transmitter and a radar receiver. The radar transmitter includes generation circuitry to generate a digital radar chirp sequence, and one or more digital-to-analog converters to convert the digital radar chirp sequence into a radar signal to be transmitted via one or more transmit antennas. The radar receiver includes one or more analog-to-digital converters to convert a received reflection of the radar signal to a received digital signal, and a mixer to mix the received digital signal with the digital chirp sequence to generate a digital de-chirped signal for velocity estimation followed by range estimation.
G01S 13/34 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées utilisant la transmission d'ondes continues modulées en fréquence, tout en faisant un hétérodynage du signal reçu, ou d’un signal dérivé, avec un signal généré localement, associé au signal transmis simultanément
G01S 7/00 - Détails des systèmes correspondant aux groupes , ,
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement
G01S 13/92 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour la commande du trafic pour la mesure de la vitesse
63.
PHASE-LOCK LOOP USING PHASE CONVERGENCE COMPENSATION
Provided is a phase-lock loop that includes: an oscillator having an input for receiving a control signal and an output for providing an output signal having a frequency based on the control signal; a phase detector having a first input for receiving a reference signal, a second input coupled to the output of the oscillator for receiving a feedback signal, and an output for providing a phase-error signal that is indicative of a phase difference between the reference signal and the feedback signal; and a loop filter having a first input coupled to the output of the phase detector, a second input for receiving a proportional-phase-compensation value, and an output for providing the control signal to the oscillator. The control signal comprises a proportional component which is a combination of the phase-error signal and the proportional-phase-compensation value.
H03L 7/107 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage utilisant une fonction de transfert variable pour la boucle, p. ex. un filtre passe-bas ayant une largeur de bande variable
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
64.
QUADRATURE PHASE SHIFTED CLOCK GENERATION WITH DUTY CYCLE CORRECTION
A method for quadrature phase shifted clock generation with duty cycle correction includes A reference clock is delayed with a delay circuit to generate a delayed clock, wherein a delay of the delay circuit is proportional to a control value, and each of the reference clock and the delayed clock comprise a plurality of states comprising a first state and a second state. A first edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. A second edge value is increased or decreased in response to a respective combination of states of the reference clock and the delayed clock. The control value is driven to the first edge value during the second state of the delayed clock and to the second edge value during the first state of the delayed clock.
A semiconductor device includes a secured circuit, an electromagnetic interference (EMI) sensor over a surface of the secured circuit, and a sensing circuit. The EMI sensor is configured to receive a reference voltage and the EMI sensor includes at least one of electric (E) field sensor or a magnetic (H) field sensor. The sensing circuit includes a hysteresis comparator and a voltage level comparator. The hysteresis comparator has a first input coupled to a first node of the EMI sensor via a low pass filter, a second input directly connected to the first node, and an output configured to provide an output indicative an EMI attack. An antenna portion of the EMI sensor includes the first node and is coupled between inputs of the voltage level comparator, in which the voltage comparator is configured to provide an output indicative of a physical tampering with the antenna portion.
A voltage regulator for outputting a regulated output voltage to an integrated circuit, the voltage regulator comprising: a voltage supply terminal for receiving a supply voltage; an output terminal for outputting the regulated output voltage; a reference terminal; a feedforward Wilson current mirror comprising: a Wilson current mirror with an input current terminal and an output current terminal; an input current source coupled between the supply voltage terminal and the input current terminal of the Wilson current mirror; a feedforward capacitor arranged in parallel with the input current source; and an output current transistor with a conduction channel coupled between the supply voltage terminal and the output current terminal of the Wilson current mirror; and a flipped voltage follower, FVF, comprising: a pass transistor comprising a conduction channel coupled between the supply voltage terminal and the output terminal; a first FVF transistor with a conduction channel coupled between the output voltage and a FVF node; a second FVF transistor with a conduction channel coupled between a gate of the pass transistor and the FVF node; a third FVF transistor with a conduction channel coupled between the supply voltage terminal and the gate of the pass transistor, wherein a gate of the third FVF transistor is coupled to a gate of the output current transistor; and a FVF current source coupled between the FVF node and the reference terminal.
G05F 1/46 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu
G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance
Provided is a phase-lock loop gear shifter that includes: an input for receiving a loop gain that is dynamically controllable; an input for receiving a phase-error signal; a subtractor configured to provide a gain difference between the loop gain input at a second time and the loop gain input at a first time, the first time being earlier than the second time; a module that determines a characteristic phase-error value based on the phase-error signal; and a multiplier that multiplies the gain difference by the characteristic phase-error value to provide a control-signal correction value.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
68.
METHOD TO PROTECT A STACK FROM MANIPULATION IN A DATA PROCESSING SYSTEM
A method is provided to protect a stack of return addresses from manipulation. The return address indicates where to return in a computer program after a subroutine is called. In the method, an encryption key and an initial tweak value is selected. For a return address to be stored on the stack, a first chained address is generated by encrypting the return address with the encryption key and the initial tweak value. The first chained address is provided to the stack instead of the return address. For a subsequent return address that is subsequent to the return address, a second chained address is generated by encrypting the subsequent return address with the encryption key and the first chained address. The second chained address is provided to the stack instead of the subsequent return address. The method provides effective protection without requiring additional memory in a memory limited system.
G06F 21/52 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données
A radar system may include transmitter modules configured to transmit multiple transmit signals in accordance with a Doppler Domain Multiplexing (DDM) scheme, receiver modules configured to receive reflections from the plurality of transmit signals reflected off an object and to generate corresponding digital signals, and a signal processor configured to generate a range-Doppler antenna cube representing the digital signals, and, for each of range bin of the cube, to generate a decoded range-Doppler bit map (RDBM) from the range-Doppler antenna cube by generating decoded RDBM rows by extracting a range bin matrix, performing a Discrete Fourier Transform on range bin matrix to generate an output matrix, determining peak locations in the output matrix, comparing associated peak locations across transmit channels of the output matrix to identify location-matched peaks associated with the Doppler bin, and generating a decoded RDBM row based on the location-matched peaks.
A method of making a bipolar transistor includes forming an extrinsic base layer over an oxide layer on a substrate. After an emitter window is opened in the extrinsic base layer, a sidewall spacer is formed on the sidewall of the emitter window. After forming the sidewall spacer, the oxide layer may be etched away to expose the substrate and to form a cavity extending beneath the extrinsic base layer. Subsequently, a monocrystalline emitter is formed in the emitter window whereby a peripheral part of the monocrystalline emitter fills the cavity. An anneal is then performed to form an emitter diffusion region and a base link region of the bipolar transistor.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
A method and apparatus are disclosed for an integrated circuit having a high voltage tub including a buried layer of a first conductivity type formed in a substrate of a second conductivity type, a central region of the first conductivity type formed in the substrate in contact with the buried layer, a first floating isolation trench formed in the substrate to surround the central region and to extend down to and surround the buried layer, a second floating isolation trench formed in the substrate around the first isolation trench, a shallow ring region of the first conductivity type formed in the substrate between the first floating isolation trench and the second floating isolation trench, a first conductive interconnect structure for electrically shorting the central region to the shallow ring region, and a second conductive interconnect structure for electrically shorting the first floating isolation trench to the second floating isolation trench.
A tamper detection system for detecting tampering of an enclosure of an electronic device is provided. The tamper detection system includes a light source and a light sensor both mounted inside the enclosure and connected to a tamper detection circuit. The light sensor is spaced apart and separate from the light source. The light sensor is configured to sense light emitted by the light source, the light sensed by the light sensor having a characteristic. A characteristic of the sensed light is stored during an initialization phase. During normal operation, the tamper detection circuit is configured to turn the light source on and off on a predetermined time interval. Tampering of the enclosure is detected when the light sensed by the light sensor does not compare favorably to the stored characteristic. In another embodiment, a method for detecting tampering is provided.
A system includes a processor and a non-transitory computer-readable medium storing machine instructions that cause the processor to perform a first fast Fourier transform (FFT) on received radar data to obtain a range-antenna data array and to perform a second FFT on the range-antenna data array to obtain a range-Doppler-antenna data cube. The processor performs peak detection on the range-Doppler-antenna data cube based on object information to obtain a subset that includes confirmed peaks and candidate peaks. The processor performs angle of arrival calculations for the subset of the range-Doppler-antenna data cube, and filters candidate peaks in the subset to obtain a point cloud representative of an environment. In some implementations, the confirmed peaks are detected based on a default threshold value, the candidate peaks are detected based on at least one adapted threshold value, and the at least one adapted threshold value is determined based on the object information.
G01S 13/72 - Systèmes radar de poursuiteSystèmes analogues pour la poursuite en deux dimensions, p. ex. combinaison de la poursuite en angle et de celle en distance, radar de poursuite pendant l'exploration
A radar front-end is disclosed, comprising: an array of antennas, each antenna being coupled to first input of a respective one of a plurality of directional couplers, and comprising an end antenna coupled to a first input of a first directional coupler; the first directional coupler having an output configured to be coupled to a receiver unit; a remainder of the directional couplers each having an output coupled to an input of a respective delay line; wherein an output of each delay line is coupled to a second input of a respective neighbouring directional coupler. Radar system comprising the radar front-end are also disclosed.
A method for display noise canceling in a touch sensing system includes measuring a first feedback voltage of a feedback node resistively coupled to a line voltage of a capacitive touch panel, the line voltage formed by a continuous wave output of an amplifier responsive to a reference voltage difference between the first feedback voltage and a reference voltage. A second feedback voltage is clamped to a first upper voltage threshold in response to a first voltage difference between the first feedback voltage and the reference voltage being greater than the first upper voltage threshold. The second feedback voltage is clamped to a first lower voltage threshold in response to the first voltage difference being less than the first lower voltage threshold.
A method of manufacturing a semiconductor device is provided. The method includes forming a first non-conductive layer over a top side a semiconductor die and patterning the first non-conductive layer to form a collar structure surrounding an opening exposing a top surface of a bond pad. A second non-conductive layer is formed over the first non-conductive layer and exposed portions of the top side of the semiconductor die. The second non-conductive layer is different from the first non-conductive layer. The second non-conductive layer is patterned to expose the top surface of the bond pad and inner sidewalls of the of the collar structure surrounding the opening such that the second non-conductive layer does not contact the bond pad. A metal redistribution layer is formed over the second non-conductive layer and exposed top surface of the bond pad.
An elliptic curve point validation method, comprising: receiving a standard projective X and Z coordinate on an elliptic curve; computing X·Z; inverting X·Z to get (XZ)−1; multiplying Z2, (XZ)−1, and a constant √{square root over (b)} resulting in √{square root over (b)}·x−1, where b is a constant of the elliptic curve; multiplying X2 and (XZ)−1 resulting in x; computing Tr(x) and checking that it has a value of 1, where Tr(⋅) is a trace of Frobenius map that maps an input to a value of 0 or 1; computing Tr(√{square root over (b)}x−1) and checking that it has a value of 0; and outputting x and a PointOnCurve value, where the PointOnCurve value indicates whether x is on the elliptic curve.
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
78.
SYSTEMS AND METHODS OF ENFORCING POLICY COMPLIANCE OF VEHICLES
A vehicle includes a compliance security module (CSM) configured to ensure that the vehicle is capable of functioning in accordance with one or more policies. The CSM can be configured to obtain the one or more policies, authenticate the one or more policies, monitor the components of the vehicle and/or inform policy-related components of the vehicle of the one or more policies. The CSM can be configured to validate that the vehicle will comply with one or more policies, for example, by generating and transmitting a compliance certificate to an enforcing authority.
In accordance with a first aspect of the present disclosure, an access system is provided for gaining access to a vehicle, comprising: a communication unit configured to establish a communication channel with an external device and to receive at least one credential from the external device through said communication channel; a secure element configured to perform a verification of said credential and to grant or deny access to the vehicle in dependence on a result of the verification of the credential. In accordance with further aspects of the present disclosure, a corresponding method of operating an access system for gaining access to a vehicle is conceived, as well as a computer program for carrying out said method.
One example discloses a switching regulator circuit, comprising: a power supply input (Vin); a voltage reference (Vref); a power output (Vout); a high-side switch coupled between the power supply input (Vin) and the power output (Vout); a low-side switch coupled between a ground reference (GND) and the power output (Vout); a driver circuit coupled to the high-side switch and the low-side switch; a low-power comparator (COMP1) coupled to receive the voltage reference (Vref) and the power output (Vout); a high-power comparator (COMP2) having a first input and a second input; wherein the first input is coupled to a compensation capacitor (CC) and a first switch (SW1); wherein the second input is coupled to a current sense ramp; wherein the current sense ramp is coupled to the power output (Vout).
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
81.
EGO VELOCITY ASSISTED DIRECTION OF ARRIVAL ESTIMATOR FOR RADAR SYSTEMS
A radar system includes a processor and a non-transitory computer-readable medium storing machine instructions. The processor obtains an ego velocity Vego of a radar system, a range R of an object in an environment of the radar system, and a radial velocity Vr of the object. The processor determines a simplified two-dimensional (2D) angular search grid and performs a grid-based direction-of-arrival algorithm using the simplified 2D angular search grid. In some implementations, the processor determines a ring of possible positions for a stationary object based on the ego velocity Vego, the range R, and the radial velocity Vr, and includes the ring of possible positions in the simplified 2D angular search grid. In some implementations, the processor determines an arc of possible positions for a moving object based on the range R, and includes the arc of possible positions in the simplified 2D angular search grid.
G01S 13/60 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement dans lesquels l'émetteur et le récepteur sont montés sur l'objet mobile, p. ex. pour déterminer la vitesse par rapport au sol, l'angle de dérive, le trajet au sol
G01S 13/58 - Systèmes de détermination de la vitesse ou de la trajectoireSystèmes de détermination du sens d'un mouvement
In accordance with a first aspect of the present disclosure, a wireless charging device is provided, comprising: a charging unit configured to charge an external device by wirelessly transferring power to said external device; a detection unit configured to detect whether the external device is a passive near field communication (NFC) device or an active NFC device by analyzing a modulation characteristic of an NFC signal received by the external device; a controller configured to control the charging unit in dependence on an output of the detection unit, wherein said output indicates whether the external device is a passive NFC device or an active NFC device. In accordance with a second aspect of the present disclosure, a corresponding method of operating a wireless charging device is conceived.
H02J 50/80 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique mettant en œuvre l’échange de données, concernant l’alimentation ou la distribution d’énergie électrique, entre les dispositifs de transmission et les dispositifs de réception
H04B 5/79 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive spécialement adaptés à des fins spécifiques pour le transfert de données en combinaison avec le transfert d'énergie
Electronic control device (200), comprising:
a first input (201) for a control voltage (Vtune) of a voltage controlled device (200);
a second input (202) for a reference control voltage (Vtune0) of the voltage controlled device (200); and
an output (203), wherein
the electronic control device (200) is configured to provide a bias current change (ΔIB) via the output (203) to the voltage controlled device (200) in order to maintain a level of the control voltage (Vtune) inside a specified range.
H03L 1/02 - Stabilisation du signal de sortie du générateur contre les variations de valeurs physiques, p. ex. de l'alimentation en énergie contre les variations de température uniquement
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03L 7/18 - Synthèse de fréquence indirecte, c.-à-d. production d'une fréquence désirée parmi un certain nombre de fréquences prédéterminées en utilisant une boucle verrouillée en fréquence ou en phase en utilisant un diviseur de fréquence ou un compteur dans la boucle
The present disclosure relates to a system for a communication node at an interface between Ethernet communication and CAN communication, the system and/or method being configured to ensure a small geometric size and prevent loss of data.
For a mobile device having a main battery and a backup power source, a method is provided for wirelessly charging the backup power source using a reader when the main battery of the mobile device is fully depleted and unable to provide enough power for an RF transaction. The reader detects the mobile device cannot perform the RF transaction. In response, the reader generates an RF field that provides charge for the backup power source of the mobile device. After charging is complete, the mobile device performs the RF transaction using the charged backup power source. In one embodiment the mobile device is a mobile phone being used as a digital key and the reader is implemented in a smart door handle of an automobile that is unlocked by the RF transaction.
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
E05B 81/76 - Détection du maniement de la poignéeDétection d’un utilisateur s'approchant d'une poignéeActions de commutation électrique effectuées par les poignées
H02J 7/34 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
86.
INTER-SYMBOL INTERFERENCE COMPENSATION FOR ANALOG-TO-DIGITAL CONVERTER
A device may include a sigma-delta analog-to-digital converter (ADC) configured to convert an analog input signal to a digital signal that is a digital approximation of the analog input signal. A bitstream modifier is configured to receive the digital signal, output a first signal that is based on the digital signal at a first output terminal and output a first difference signal at a second output terminal that includes a first difference value between a first value of the digital signal and a second value of the digital signal. The second value is immediately prior to the first value in the digital signal. An error correction system is configured to receive the first signal, receive the first difference signal, use the first signal and the first difference signal to determine a correction value, and modify the digital signal to generate a corrected digital signal by applying the correction value.
A near-field communication (NFC) device is configured to track the amplitude associated with a received radio frequency (RF) signal while transmitting a different RF signal indicating a command. To this end, the NFC device includes tracking circuitry configured to track the amplitude associated with the received RF signal based on a modulation state indicated by a modulation envelope associated with the transmitted RF signal. In response to the modulation envelope indicating a modulated state, the tracking circuitry enters an idle state and does not track the amplitude associated with the received RF signal. In response to the modulation envelope indicating an unmodulated state, tracking circuitry tracks the amplitude associated with the received RF signal.
A method is provided for watermarking a machine learning model. A sequence of bits is generated. The sequence of bits may be text characters divided into chunks. A selected plurality of input samples from training data is divided into subsets of input samples. All of the input samples of each subset of the subsets of input samples are labeled with a same first label in a problem domain of the ML model. Each chunk is combined with a subset of the labeled subsets to produce a plurality of labeled trigger samples. Each trigger sample of each set of the plurality of sets is relabeled to have a second label different from the first label and in the problem domain to produce a relabeled set of trigger samples. The ML model is trained with the training data and the relabeled trigger samples to produce a watermarked ML model.
A security platform includes a security tag having a wireless communication circuitry configured to receive a user identification (ID) from an ID tag. After receiving the user ID, the security tag tracks the distance the security tag moves away from a predetermined point. The security tag then compares the determined distance to a predetermined distance threshold to determine whether the security tag is within a range. In response to the determined distance being greater than the predetermined distance threshold, the security tag determines that the security tag is outside of the range and activates an alarm. The alarm of the security tag continues to be active until a second user ID having appropriate access rights is received.
G06K 7/10 - Méthodes ou dispositions pour la lecture de supports d'enregistrement par radiation électromagnétique, p. ex. lecture optiqueMéthodes ou dispositions pour la lecture de supports d'enregistrement par radiation corpusculaire
90.
DUAL LEADFRAME SEMICONDUCTOR DEVICE AND METHOD THEREFOR
A method of manufacturing a semiconductor device is provided. The method includes attaching a first semiconductor die to a first die pad of a first leadframe and attaching a second semiconductor die to a second die pad of a second leadframe. The first leadframe is attached to the second leadframe by way of a non-conductive adhesive. A first plurality of leads of the first leadframe are interleaved with leads of a second plurality of leads of the second leadframe. The first and second semiconductor die and portions of the first and second leadframes are encapsulated with an encapsulant.
A secure processing system configured to produce a hash based digital signature of a message, including: random number generator (RNG); a monotonic counter device configured to produce a monotonically increasing counter value; a hash accelerator configured to produce a hash of the message based upon a random number from the RNG and the counter value; and a run time integrity check (RTIC) device configured to check the integrity of the operation of the hash accelerator based upon the counter value.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A method is provided for detecting tampering of a printed circuit board (PCB) using a tamper detection circuit implemented in an integrated circuit (IC) mounted on the PCB. In the method, a reference signal is generated and provided to a terminal of the IC. The terminal is connected to another circuit mounted on the PCB. A first response signal is received in response to the reference signal at the terminal. One or more characteristics of the first response signal are stored in a memory. The reference signal is again provided to the terminal of the integrated circuit and a second response signal is received at the terminal. The stored characteristics of the first response signal are compared to corresponding characteristics of the second response signal to generate a comparison result. The comparison result is used to detect tampering. When tampering is detected, an indication is provided.
A method includes techniques for identifying the phase step of one transmitter while conducting phase difference measurements between two transmitters in a multi-transmitter radar device. The method includes setting a first phase of a first transmitter in the multi-transmitter device to a fixed phase value and setting a second phase of a second transmitter in the multi-transmitter device to an initial phase value, varying the second phase of the second transmitter from the initial phase value to a final phase value and performing a sample measurement at each variation to obtain a plurality of intermediate frequency (IF) samples; and transforming the plurality of IF samples into complex samples. The method then includes determining one or more phase steps of the second transmitter based on the complex samples.
A battery management system includes battery management circuitry configured to be coupled to one or more battery modules. The battery management circuitry includes a secure element storing cryptographic information that enables the battery management circuitry to communicate securely with an external server as part of installation of a new battery module coupled to the battery management or removal of a battery module already coupled to the battery management circuitry.
A computing system divides an initial seed network into a plurality of blocks to form a network search space that includes candidate neural architectures. For each block in the plurality of blocks, sample-based search spaces are defined. Each sample-based search space includes candidate block configurations. The candidate block configurations are determined by determining candidate block configurations that minimize a block-wise knowledge distillation loss. A first set of block configurations that are Pareto optimal block configurations are determined from the candidate block configurations in the sample-based search spaces. Sub-super-net search spaces for each block configuration in the first set of block configurations are determined. Using input training data, each of the sub-super-net search spaces are trained to generate a trained candidate models. An optimized neural architecture is determined by determining a first trained candidate model of the trained candidate models that minimizes a knowledge distillation loss of the trained candidate models.
A first device operates to utilize RF signaling for both communication signaling and radar sensing. The first device transmits a first RF signal representing a first OFDM symbol at time index k−1 and transmits a second RF signal representing a second OFDM symbol at time index k. The first and second OFDM symbols represent communication data for receipt by at least a second device, and have cyclic prefixes of a length less than a channel length used for radar sensing by the JCAS device. A third RF signal that is a scattered representation of the second RF signal is received at the first device, and a compensation matrix determined from at least both the first and second OFDM symbols is used to compensate for ISI present in the third RF signal. From this compensated result a set pf radar channel coefficients representing the local environment are determined.
Embodiments of wireless communications systems, ultra-wide band (UWB) systems, and methods for wireless communications are described. In an embodiment, a wireless communications system includes a processor configured to obtain an angle of arrival (AoA) estimate from wireless signals; perform a Channel Impulse Response (CIR) analysis, and determine a confidence level for the AoA estimate based on the CIR analysis.
A semiconductor device may include a semiconductor substrate and an isolation structure including a first dielectric layer formed over the semiconductor substrate, the first dielectric layer including one or more air gaps, and a first conductive structure formed on the dielectric layer, the conductive structure having a lower surface that faces the semiconductor substrate. Respective air gaps of the one or more air gaps of the first dielectric layer each may be disposed directly between corners of the lower surface of the conductive structure and the semiconductor substrate.
The disclosure relates to temperature sensor circuits, an example embodiment including a temperature sensor circuit (200) comprising: a PTAT voltage circuit (201); a reference current source (202); a capacitor (203); a reset switch (204) connected across the capacitor (203); a comparator (205) configured to compare a voltage across the capacitor (203) to the PTAT voltage and provide a comparator output (U/D); a counter circuit (206) configured to increment or decrement an output word (Kdig) depending on the comparator output (U/D), and repeatedly perform the sequential steps of: i) providing a reset signal (207) to momentarily close the reset switch (204) to discharge the capacitor (203); ii) counting a number of clock cycles corresponding to the output word (Kdig) while the capacitor (203) is charged by the reference current source (202); and iii) incrementing or decrementing the output word (Kdig) depending on the comparator output (U/D), wherein, after repeating the sequential steps, the output word (Kdig) converges to a value corresponding to a temperature of the PTAT voltage circuit (201).
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
G05F 3/30 - Régulateurs utilisant la différence entre les tensions base-émetteur de deux transistors bipolaires fonctionnant à des densités de courant différentes
Control unit (100) for a transmission system, comprising:
a sample rate converter (10), which is coupled to a digital-to-analog converting unit (200), wherein digital input data (data_in) are feedable to the sample rate converter (10);
a PRBS generator (20), wherein an output signal (ss_div) of the PRBS generator (20) is feedable to the sample rate converter (10) and to a delay element (30), wherein an output signal (ss_div_del) of the delay element (30) is feedable to a frequency synthesizer (40), wherein the frequency synthesizer (40) is clockable by a reference clock (clk_ref) and wherein an output signal (clk_ss) of the frequency synthesizer (40) is feedable to a clock input (10a) of the sample rate converter (10) and to a clock input (200a) of the digital-to-analog converting unit (200).
