A method for determining an angle of arrival at a first communication device having a first antenna and a second antenna aligned along a direction and defining a normal thereto. The method comprises performing a respective signal exchange through each of a plurality of channels between the first communication device and a second communication device, storing a first plurality of in-phase and quadrature (I/Q) samples; estimating channel frequency responses for the first antenna and the second antenna respectively; measuring a respective distance; creating respective standard channel frequency response components corresponding to the respective distances; for each propagation path, selecting a first respective weight and a second respective weight; selecting a weight w1(1) and an other weight w2(1);determining, based on the weight w1(1) and the other weight w2(1), the angle of arrival, relative to the normal, of signals direct from the second communication device.
G01S 13/75 - Systems using reradiation of radio waves, e.g. secondary radar systemsAnalogous systems using transponders powered from received waves, e.g. using passive transponders
G01S 7/00 - Details of systems according to groups , ,
Monitoring object movement comprises attaching an ultra-wide band (UWB) sensor to an object and transmitting, by the UWB sensor in a radar mode, a plurality of UWB pulses. The UWB sensor in the radar mode receives a plurality of reflected UWB pulses and determines over a time a channel response (CIR) based on the plurality of transmitted and reflected UWB pulses. The CIR is indicative of the object movement.
Systems and methods for sharing a sensor between different actors in an Integrated Circuit (IC) are discussed. In some embodiments, an electronic circuit may include: first and second cores; and a sensor coupled to the first and second cores, the sensor comprising: (a) a first threshold register coupled to a first hardware access filter, where the first hardware access filter allows the first core to access the first threshold register to the exclusion of the second core, and (b) a second threshold register coupled to second hardware access filter, where the second hardware access filter allows the second core to access the second threshold register to the exclusion of the first core.
Dual-antenna communication devices and methods are disclosed. The device comprises: a controller, having a first, output, interface, comprising a first connector and a second connector; a first antenna coupled between the first connector and a ground; and
a second antenna, coupled between the first connector and the second connector; wherein the controller is configured to: transmit an output signal from the first antenna by providing a signal at the first connector and an in-phase copy of the signal at the second connector, and transmit the output signal from the second antenna by providing the signal at the first connector and an opposite-phase copy of the signal at the second connector.
H01Q 5/50 - Feeding or matching arrangements for broad-band or multi-band operation
H01Q 7/00 - Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
SECURING ELLIPTIC CURVE DIGITAL SIGNATURE ALGORITHM (ECDSA) NONCE COMMUNICATED BETWEEN SYMMETRIC AND ASYMMETRIC CRYPTOGRAPHIC CO-PROCESSORS IN A HETEROGENEOUS SYSTEM
Systems and methods for securing an Elliptic Curve Digital Signature Algorithm (ECDSA) nonce communicated between symmetric and asymmetric cryptographic co-processors in a heterogeneous system are discussed. In some embodiments, a processor may include: a symmetric portion configured to generate Boolean masked shares, wherein the Boolean masked shares constitute a nonce; and an asymmetric portion coupled to the symmetric portion, the asymmetric portion configured to produce an ECDSA signature based, at least in part, upon the nonce.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
Systems and methods for overclocking detection and response are discussed. In some embodiments, a device may include a Clock Monitoring Unit (CMU) and a control circuit coupled to the CMU, the control circuit configured to: upon initialization, determine a maximum allowed frequency based, at least in part, upon information stored in a One-Time Programmable (OTP) memory; and provide an indication of the maximum allowed frequency to the CMU, wherein the CMU is configured to detect overclocking based, at least in part, upon a comparison between a frequency of a clock signal and the maximum allowed frequency.
Disclosed is a clamping arrangement, comprising: a clamp circuit, arranged between an internal supply voltage supply rail (Vcc) and a second supply voltage supply rail (Vss) and configured to, on detection of a high-voltage ESD event at an external terminal, protect a protected circuit from the ESD high-voltage for a duration defined by an RC-timer; and an RC-interruption circuit configured to suspend the operation of the RC-timer and thereby extend the duration, wherein the RC-interruption circuit comprises; a detector configured to detect that a voltage at an input to the protected circuit is above a reference voltage, and a switch configured to provide a current path between a mid-node of the RC-timer and a one of the second voltage supply rail and the internal supply voltage supply rail, in response to the detector detecting that the voltage at the input to the protected circuit is above the reference voltage.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A capacitance sensing circuit and method uses a current pulse to charge an external capacitor. A first voltage associated with the external capacitor is converted to current to charge an internal capacitor. A second voltage, which is associated with the internal capacitor that corresponds to the first voltage, is compared with an adjustable threshold voltage to generate a toggle signal. The adjustable threshold voltage is changed in response to the toggle signal, which is associated with a capacitance of the external capacitor.
G01R 27/26 - Measuring inductance or capacitanceMeasuring quality factor, e.g. by using the resonance methodMeasuring loss factorMeasuring dielectric constants
A neural network processing system and a method of generating weights for a neural network processing system is described. The system includes a plurality of processor cores coupled to respective weight memories which store neural network weights. The neural network weights are stored as a plurality of weight mask bits, each weight mask bit indicating whether a corresponding weight is a pruned weight or a non-pruned weight and a plurality of non-pruned weights. At least one of the non-pruned weights has a pruned weight value. Non-pruned weights with a pruned weight value may be selectively added after initial pruning to equalize memory section size, word align memory sections or to ensure processing stalls (hiccups) occur in the same cycle. The resulting pruned weight sets may be used with neural processor accelerators operating in lock step.
A phase locked loop (PLL) includes an oscillator circuit and a built-in self-test (BIST) circuit. The BIST circuit tests the oscillator circuit by providing a set of input signals to the oscillator circuit and averages resulting output signals to generate an average oscillator characteristic. In some embodiments, the input signals are repeatedly sent to the oscillator circuit during a measurement window. The BIST circuit compares the resulting average oscillator characteristic to an oscillator model and determines whether the oscillator circuit is experiencing a failure based on how well the average oscillator characteristic matches the oscillator model.
A controller area network (CAN) system including a serial conductor(S) bus, a CAN bus, at least one configurable CAN device, and a leader device. Each configurable CAN device is inserted on the S bus and includes media access control (MAC) circuitry and physical medium circuitry. The physical medium circuitry forwards test clocks from the CAN bus to clock internal latches when the CAN bus is in a common mode and interfaces the MAC circuitry for programming via the CAN bus when the CAN bus is in a differential mode. The leader device drives the S bus between first and second logic states, switches the CAN bus between the common and differential modes, generates test clocks on the CAN bus to place a selected configurable CAN device in programming mode, and programs the selected configurable CAN device via the CAN bus.
The present disclosure provides a power ramping circuit configured to generate a combined output signal comprising: a plurality of ramp slice circuits each configured to, upon activation, provide an output voltage, wherein the power ramping circuit is configured to combine the output voltages of the ramp slice circuits in order to provide the combined output signal, and wherein each ramp slice circuit comprises: a buffer circuit comprising a buffer amplifier; and a smoothing circuit configured to selectively operate in a current-limiting mode and a non-current-limiting mode and an RF power amplifier which is configured to amplify an input signal and wherein the amplification applied by the RF power amplifier is controlled by the buffer circuit.
A voltage gain control circuit comprising: a current-to-current conversion circuit comprising; a first current mirror transistor; a second current mirror transistor; and a current mirror transistor, the voltage gain control circuit further comprising and a current-to-voltage conversion circuit, wherein an input of the current-to-voltage conversion circuit is coupled to an output of the current-to-current conversion circuit and wherein the current-to-voltage conversion circuit is configured to provide an output voltage signal which varies proportionately to a signal received at the input of the current-to-voltage conversion circuit, and wherein the configuration of the current-to-current conversion circuit is such that a linear current variation in the received linear control current results in an exponential current variation in an output current of the current-to-current conversion circuit provided to the current-to-voltage circuit via the second CMT input terminal.
H03G 3/30 - Automatic control in amplifiers having semiconductor devices
H01Q 3/36 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means with variable phase-shifters
One example discloses a system for advisory vehicle speed assistance, including: a controller coupled to receive a set of environmental information based on a location of an ego vehicle; wherein the environmental information includes a legal speed limit at the location; wherein the controller is configured to generate an advisory speed for the ego vehicle based on the set of environmental information; and wherein the advisory speed is different from the legal speed limit.
A clock circuit comprising a voltage-controlled oscillator having an input coupled to an output of an amplifier, and an output, outputting an output clock signal. The clock circuit further comprises, a reference branch and a feedback branch, both comprising, a first switch coupled to an input via an inverter and a second switch coupled to the input. The branches also both comprise, a variable capacitor coupled to a reference potential and coupled to the first switch, and a variable resistor coupled to the first switch. Both branches comprise a supply voltage coupled to the variable resistor and an output node, wherein the second switch is coupled to the variable capacitor and coupled to a node. The reference branch input is an input clock signal and the output is a reference voltage, and the feedback branch input is an output clock signal and the output is a feedback voltage.
A low complexity clock drift estimation scheme for UWB-MMS ranging is proposed, assuming sampling frequency offset (SFO) and carrier frequency offset (CFO) are driven from the same clock source. SFO is first estimated with the multiple CIR fragments, and it is used to compensate the CFO for the CIR fragments. Then a fine CFO estimate is obtained from the compensated CIRs. Combining the coarse SFO and fine CFO estimate to resample and phase rotate the original CIRs can significantly improve the performance for CIR combining, thus, improve the performance for ranging.
A radar system includes, transmitters, receivers, and a controller that determines a measurement vector using signals received by the plurality of receiver modules, determines a steering vector matrix, and determines a plurality of supports using the measurement vector. The controller executes a regression algorithm to determine a weight vector that defines a relationship between the measurement vector and the steering vector matrix by defining a set of selected supports out of the plurality of supports, executes an exchange operation to determine an optimized set of selected supports by removing a first support from the set of selected supports and adding a second support to the set of selected supports, and calculates the weight vector using the optimized set of selected supports. The controller is configured to determine an estimated angle of arrival of a first object by correlating the steering vector matrix to the measurement vector using the weight vector.
An automotive radar system includes at least one transmitter and at least one receiver and a processor configured to receive, from the at least one receiver, received radar signals, generate a first subsection of a radar cube using the received radar signals, detect a first set of candidate peaks in the first subsection of the radar cube, generate a second subsection of the radar cube using the received radar signals, detect a second set of candidate peaks in the second subsection of the radar cube, determine a set of locations in a candidate peak dataset, wherein each location in the set of locations is associated with candidate peaks in both the first set of candidate peaks and the second set of candidate peaks, and estimate a direction of arrival of an object using the candidate peaks associated with the set of locations.
A Zener diode comprising: a PN junction formed in a semiconductor material; and one or more stress-inducing regions configured to impart a compressive stress in the PN junction along a current flow direction of the PN junction.
A data processing system is provided that includes a first host processor, a first secure element operatively coupled to the first host processor, and a second secure element operatively coupled to the first host processor. The first secure element is configured to function as a server and the second secure element is configured to function as a client in a client-server relationship between the first secure element and the second secure element. The first secure element is configured to transmit synchronization data to the second secure element through the first host processor, where the synchronization data have been encrypted using a cryptographic key shared only between the first secure element and the second secure element.
Disclosed is a packaged semiconductor device, comprising: an MMIC device comprising a semiconductor die and having a differential IO; and a package substrate comprising dielectric between each of at least first through fourth metal layers, and electrically conductive vias between the metal layers; wherein the package substrate is connected to the MMIC device by a plurality of pillars between the MMIC device and the first metal layer, including a pair of the pillars which connect the differential IO to the first metal layer; wherein the first metal layer comprises a resonant slot opening therethrough between the pair of pillars; and wherein the second through fourth metal layers each comprise an opening therethrough, wherein the openings are configured to transition the IO signal between a differential mode and a waveguide fundamental mode of propagation at the fourth metal layer. A corresponding assembly further comprising a PCB is also disclosed.
A detector comprising: a filter arrangement configured to receive an output from a sigma-delta analogue to digital, SD-ADC, converter and generate a filtered output; a threshold comparison element configured to receive the filtered output and determine if signal content present in the filtered output is above or below a predetermined threshold, and wherein the detector is configured to, based on the determination of the threshold comparison element, output a flag signal indicative of a determination that the output of the SD-ADC is one of stable or unstable.
A memory comprises a multi stage clock-partitioning circuit, and at least one upper bitcell memory array and at least one lower bitcell memory array. An input is configured to receive an external clock signal. A first stage of the multi stage clock-partitioning circuit is configured to receive the external clock signal and generate a first internal clock signal and provide the first internal clock signal to the bitcell memory arrays. A second stage of the multi stage clock-partitioning circuit is configured to receive the first internal clock signal and generate a second internal clock signal. A third stage of the multi stage clock-partitioning circuit is configured to receive the second internal clock signal and generate a third word line generated clock signal and provide the third internal clock signal to the at least upper and lower bitcell memory arrays.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
A memory comprising a multi stage data path-partitioning circuit, the memory comprising at least: a first data path level partitioning comprising at least one input configured to input data to or output data from the memory via at least one global input-output circuit; a second data path level partitioning configured to input data to or output data from the memory between one of a plurality of write assist circuits and one of the at least one global input-output circuit wherein at least one of the plurality of write assist circuits and at least another of the plurality of write assist circuits are located in a central portion of an upper bitcell memory array and an lower bitcell memory array respectively; a third data path level partitioning configured to input data to or output data from the memory between one of a plurality of column multiplexing circuitry and sense amplifier circuits and one of the plurality of write assist circuits.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
One example discloses a capacitance device, including: a substrate; a bottom-plate coupled to the substrate; an insulator coupled to the bottom-plate; and a top-plate coupled to the insulator; wherein the top-plate includes a flat portion and a curved portion.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
An electrostatic discharge circuit for a semiconductor die includes a plurality of GGNMOS transistors coupled between a first rail and a second rail of the semiconductor die. Each GGNMOS transistor includes a body contact that is coupled to a trigger rail through a ballast circuit and is coupled to the second rail. During the detection of an ESD event of a sufficient severity, the trigger rail is placed in an asserted condition to make the GGNMOS transistors conductive to discharge ESD current from the first rail to the second rail.
One example discloses a heatsink device, including: a lead-frame having a die-pad, a first edge, a second edge, a third edge, and a fourth edge; wherein the lead-frame also includes a set of heatsinks, including, a first heatsink located where the first edge and the fourth edge of the lead-frame intersect; a second heatsink located where the first edge and the second edge of the lead-frame intersect; and a third heatsink located where the second edge and the third edge of the lead-frame intersect.
Wireless communication systems and methods are described, including a wireless communication system that includes a transceiver configured to generate Orthogonal Frequency-Division Multiplexing (OFDM) signals, perform signal shaping of an OFDM signal of the OFDM signals to generate a shaped OFDM signal by reducing magnitudes of one or more subcarriers of the OFDM signal near a center frequency of the OFDM signal, and wirelessly transmit the shaped OFDM signal.
The disclosure relates to a Gilbert mixer. Example embodiments include a Gilbert mixer that includes first and second multi-finger field effect transistor, FET, devices, each including gate fingers arranged between alternating source terminals and drain terminals; first and second pairs of voltage rails arranged across the first and second FET devices respectively, each of the first and second pairs including an upper rail and a lower rail; a first interconnect connecting the upper rail of the first pair and the lower rail of the second pair to a first input terminal; and a second interconnect connecting the lower rail of the first pair and the upper rail of the second pair to a second input terminal. Gate fingers of the first FET device are connected to the first pair of voltage rails and gate fingers of the second FET device are connected to the second pair of voltage rails.
The present disclosure relates to systems and methods for occupancy grid mapping. In one or more embodiments, a system includes a detection and ranging system configured to transmit signals, receive reflected signals corresponding to reflections of the transmitted signals by objects in an environment around the detection and ranging system, and generate point cloud data indicating positions of the objects, computer-readable memory configured to store side information, which can one or more digital maps, images of the environment, or previously generated occupancy grid maps, and processing circuitry configured to receive the point cloud data from the detection and ranging system, receive the side information from the computer-readable memory, determine hyperparameters for a mapping model based on the side information, and process the point cloud data using the mapping model using the hyperparameters to generate an occupancy grid map of the environment.
G06T 7/73 - Determining position or orientation of objects or cameras using feature-based methods
G01S 13/89 - Radar or analogous systems, specially adapted for specific applications for mapping or imaging
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads
31.
METHOD OF PERFORMING RADAR OPERATIONS, RADAR DEVICE AND RADAR SYSTEM
A method is provided which includes transmitting a first radar frame over a first communication channel and transmitting a second radar frame over a second communication channel. A reflection of the first radar frame is received, and a first channel impulse response is estimated based on a reflection of the first radar frame. A reflection of the second radar frame is received, and a second channel impulse response is estimated based on a reflection of the second radar frame. The first channel impulse response estimate and the second channel impulse response estimate are combined to obtain a channel impulse response estimate having a higher resolution than each of the first channel impulse response estimate and second channel impulse response estimate.
G01S 7/00 - Details of systems according to groups , ,
G01S 13/00 - Systems using the reflection or reradiation of radio waves, e.g. radar systemsAnalogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
G01S 13/02 - Systems using reflection of radio waves, e.g. primary radar systemsAnalogous systems
Techniques, circuits, and systems related to a multicore rotary traveling wave oscillator (RTWO) are provided. The multicore RTWO includes at least two metal layers and multiple RTWO cores, such that each core comprises a set of differential signal conductors that are interleaved across the metal layers to optimize space and reduce parasitic effects. The relative positional configuration of these differential signal conductors varies across a range of directionalities and/or orientations. In embodiments, an oscillator output signal is generated by the multicore RTWO; the frequency of this oscillator output signal is adjusted based on a comparison of its phase with that of a reference signal, such as within a phase locked loop circuit.
An electronic device and related method of fabricating such a device includes an electrically-conductive passive device (e.g., an inductor or transmission line) fabricated above an upper surface of a semiconductor substrate that has a body portion disposed between the upper surface and a lower surface of the substrate. The body portion is doped n-type or p-type and the passive device is separated from the upper surface by one or more layers of electrically insulating material. The substrate includes a set of electrically-insulating isolation trenches disposed beneath the passive device that extend from the upper surface of the substrate toward the lower surface of the substrate and the isolation trenches are disjoint from each other.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 23/52 - Arrangements for conducting electric current within the device in operation from one component to another
An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.
A system for cross-fading audio signals receives temporal data associated with the audio signals. Initially, current playback data corresponds to one of the temporal data. The system determines linear and non-linear data of the other temporal data that are linearly and non-linearly correlated with the temporal data, respectively. Further, the system receives a cross-fade request when a parameter value of a signal quality associated with the audio signal of the temporal data exceeds a threshold value. In response, the system cross-fades the current playback data from the temporal data to the linear data of the other temporal data. Additionally, the system inserts the non-linear data to the current playback data to successfully transition from the current temporal data to the other temporal data.
A CTAT circuit that generates a CTAT current. The circuit includes two SOI transistors of a first conductivity type arranged in a current mirror configuration where the gates of the two transistors and the back gate contact of one of the transistors is connected to the drain of the other transistor. The SOI transistor of the first conductivity type whose back gate contact is connected to the drain of the other SOI transistor of the first conductivity type is located in current path that carries a CTAT current. In some embodiments, the drains of the two transistors are each coupled to a drain of a respective one of a second pair of SOI transistors of a second conductivity type, where the second pair of SOI transistors are also configured in a current mirror configuration.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
A calibration circuit for correcting timing errors introduced by a DAC in a signal path of an ADC, the calibration circuit comprising: an input subtraction module configured to subtract an estimated error from an output of the ADC and provide a corrected output; a filter module configured to approximate an error transfer function corresponding to the DAC timing errors; a correlation module configured to correlate the corrected output with an output from the filter module to extract an error term; an integrator module configured to integrate the error term to provide an updated error coefficient; and a correction module configured to correlate the updated error coefficient with the output from the filter module to provide the estimated error to the input subtraction module.
A secure element includes a sensing unit configured to sense one or more signal characteristics. The signal characteristics include characteristics of signals transmitted to and from components of a vehicle access system. The secure element also includes a processing unit configured to conclude, in dependence on an output of the sensing unit, that one or more attacks are carried out on the vehicle access system. A corresponding method of operating a secure element is conceived, and a computer program for carrying out said method is provided.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
39.
OBJECT QUANTITY ESTIMATION TECHNIQUES IN MIMO RADAR SYSTEMS
Devices and methods for object quantity estimation in a radar system include receiving a plurality of radar echoes at a plurality of reception antennas of the radar system. The plurality of radar echoes correspond to radar signals transmitted from multiple transmission antennas of the radar system. A radar processor of the radar system generates a matrix based on the plurality of radar echoes and estimates the number of objects based on computing a rank of the matrix.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
H04W 24/02 - Arrangements for optimising operational condition
40.
DISTORTION CORRECTION BASED ON FIRST COME FIRST SERVED
Distortion correction from a distorted source image to a distortion-corrected target image includes dividing a target image into at least two vertical stripes and dividing each vertical stripe of the at least two vertical stripes into a plurality of target tiles. Each target tile has a target tile position having an x coordinate and a y coordinate within the target image. The distorted source image is divided into a plurality of source tiles, and the source tiles are processed to produce a source tile index. The method further includes reading target tiles of a distorted image of at least one vertical stripe, buffering a subsection of the read target tiles of the distorted image in a dedicated buffer, and performing distortion correction of source tiles of the distorted source image by mapping the subsection of source tiles to corresponding buffered subsection of target tiles of at least one vertical stripe.
A computerized technique is disclosed of identifying object features in an environment of a vehicle. The technique includes receiving, by an encoder, data representing a plurality of frames, the frames providing point-in-time versions of a segmented pointed cloud derived from output of one or more radar sensors of the vehicle and including points that represent radar detections corresponding to an object in the environment at respective instants in time. The technique further includes arranging the plurality of frames in a time-ordered queue and processing the frames in the queue, including (i) selecting, from among the points, a plurality of sample points that spans multiple frames of the queue, (ii) forming a plurality of groups of points based on respective sample points of the plurality of sample points, and (iii) extracting features of the object based on the plurality of sample points and the plurality of groups.
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
G01S 13/42 - Simultaneous measurement of distance and other coordinates
42.
SYSTEM AND METHOD FOR MULTI-LATERATION OF USER DEVICE
A processing circuit of an ultra-wideband (UWB) system communicates in contention-based ranging (CBR) with UWB anchors to transmit a time stamp. The time stamp facilitates determination of distance between the UWB system and each of the UWB anchors. Upon transmission of the time stamp, the UWB system receives details associated with a distance between the UWB system and a corresponding UWB anchor that transmits the distance. The UWB system generates payloads to relay the distance in combination with an updated time stamp indicating a time of generation of the payloads to another UWB anchor. The payloads facilitate in multi-lateration of the UWB system.
Embodiments of methods and semiconductor devices are described that are configured to determine a negative resistance margin (NRM) of an oscillator circuit. The semiconductor device may include an integrated circuit including an amplifier circuit coupled between a first node and a second node and NRM test circuitry including a resistor circuit selectively coupled between a first contact pad and the first node. The integrated circuit may receive an oscillating signal from an oscillator circuit coupled to the first contact pad and a second contact pad of the integrated circuit. In an NRM test mode, a resistance of the resistor circuit is selectively varied from an initial resistance value to one or more second resistance values and the oscillating signal is monitored at the second node to determine the NRM based on the one or more second resistance values when an amplitude of the oscillating signal falls below a threshold amplitude.
H03B 7/06 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device
H03B 5/06 - Modifications of generator to ensure starting of oscillations
H03B 5/36 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element being electromechanical resonator being a piezoelectric resonator active element in amplifier being semiconductor device
A digital signal processing (DSP) circuit of a system for blending audio signals executes a trained machine learning model to extract audio parameters associated with audio blocks of two received audio signals and generates audio quality scores. Each audio quality score indicates an audio quality of the audio block. Upon analyzing the corresponding audio quality scores of the two audio signals, the DSP circuit outputs an audio block of one of the audio signals based on a previous blended block or blends one of the audio blocks of the two audio signals to output a blended block that includes a composition of the corresponding audio blocks of the two audio signals. The system thus outputs an audio output signal that includes such audio blocks that are associated with at least one of the two audio signals.
A method of preconfiguring a neural architecture search, NAS, (NAS) is proposed. A ground truth performance is obtained, wherein the ground truth performance of a neural network is used for a limited amount of solutions taken as a reference which represent neural networks having been trained to their full extent. The proposed method delivers a performance estimation strategy to a NAS procedure, enabling an automated process of defining the NAS. Hence, a user has not to give any inputs as regards performance estimation strategy which optimizes a design space of NAS. This is achieved by an instance of the search space having been selected and trained, wherein a performance estimation metrics is computed. A library of performance estimation strategies is taken from a database, wherein a matrix of the strategies is computed for a small reduced set of neural networks.
A method of locating a UWB enabled mobile device in a UWB based transit deployment is disclosed. Performed is a data transfer process within a specified proximity between the UWB enabled device and anchors of a transit gate (G1 . . . Gn), wherein multiple distance measurements (RS1 . . . RSn) are performed between the transit gate (G1 . . . Gn) and the UWB enabled device during the data transfer process. Multiple ranging processes or ranging rounds during the data transfer phase are carried out in this way. The multiple ranging processes support improved security as regards data transfer between UWB enabled mobile device and transit gate.
In accordance with a first aspect of the present disclosure, a secure element is provided, comprising: a storage unit configured to store a profile and to store export control data associated with said profile; a processing unit operatively coupled to the storage unit, wherein said processing unit is configured to: verify whether the export control data meet a predefined condition; authorize an export of the profile to a target secure element if the export control data meet said predefined condition. In accordance with further aspects of the present disclosure, a corresponding method of operating a secure element is conceived, and a computer program for carrying out said method is provided.
In accordance with a first aspect of the present disclosure, a secure element is provided, comprising: a storage unit configured to store a profile and to store export target information associated with said profile; an interface unit configured to receive a message from a target secure element; a processing unit operatively coupled to the storage unit and the interface unit, wherein said processing unit is configured to: verify whether data included in said message matches with the export target information; authorize an export of the profile to the target secure element if the data included in said message matches with the export target information. In accordance with further aspects of the present disclosure, a corresponding method of operating a secure element is conceived, and a computer program for carrying out said method is provided.
G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
49.
METHOD OF LOCATING A UWB-ENABLED MOBILE DEVICE IN A UWB BASED TRANSIT DEPLOYMENT
A method of locating a UWB enabled mobile device in a UWB based transit deployment is disclosed. The method implements a trilateration procedure between three known anchor positions of transit gates and implements position determination based on determination of distance values between three of the transit gates and an ultra-wideband (UWB) device. In effect, by means of the anchors a maximal amount of mobile devices can be recognized. Thus, a scalable transit scenario is implemented without needing additional anchor infrastructure. A discovery process is implemented, in which user are recognized in order to pay via fare transaction. The whole process of discovery, gate selection und fare transaction is thus possible without DL-TDoA infrastructure. In this way, advantageously, DL-TDoA infrastructure can be saved to a maximum extent. A following fare transaction can be carried out as defined by a transit provider.
A system and method of producing a key for a digital signature method, including: providing a plurality of initial hardware security modules (HSM) with global public key parameters; running key generation to produce sub-public keys for respective sub-trees associated with the plurality of initial HSMs based upon the global public key parameters; picking a random seed and generating a sub-public key and a sub-tree based upon the random seed for a plurality of virtual HSMs; sending the sub-public keys of the plurality of initial HSMs to a root HSM; computing an overall public key of a tree structure associated with the root HSM; distributing the sub-public keys for the initial HSMs to the plurality of initial HSMs; splitting the random seed of the virtual HSMs into a plurality of key shares; and providing custodians associated with the plurality of virtual HSMs a key share from the plurality of key shares.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
The disclosure relates to cancellation of self-interference in radar transceivers. Example embodiments include a radar transceiver in which a correction module is configured to combine an analog baseband received signal with a digital correction signal to provide a corrected analog baseband signal, the correction module comprising a sampling capacitor, a variable cancellation capacitor controllable by the digital correction signal, an amplifier and a switching arrangement configured to sample the baseband received signal and sum a sampled charge across the sampling capacitor with a charge across the variable cancellation capacitor to provide a residue signal to the amplifier, the amplifier configured to amplify the residue signal to provide the corrected analog baseband signal to an ADC.
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
G01S 7/02 - Details of systems according to groups , , of systems according to group
G01S 13/02 - Systems using reflection of radio waves, e.g. primary radar systemsAnalogous systems
H01Q 1/52 - Means for reducing coupling between antennas Means for reducing coupling between an antenna and another structure
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
52.
PHASE-LOCKED LOOP REFERENCE CLOCK SWITCHING WITH CONTROLLED OUTPUT TRANSIENT FREQUENCY DRIFT
A reference clock switching controller for a PLL including select circuitry and a reset controller. The PLL includes a phase detector receiving a feedback clock and a selected reference clock, and a frequency divider receiving an output clock and providing the feedback clock. The select circuitry selects from among multiple reference clocks based on a select signal to provide the selected reference clock. The reset controller resets the phase detector in response to a transition of the select signal and releases the phase detector upon a following falling edge of the selected reference clock. The reset controller resets the frequency divider in response to the transition of the select signal and releases the frequency divider after the phase detector is released from reset upon a following rising edge of the selected reference clock. A phase limit controller limits phase error during clock switching by minimizing delay of feedback clock transitions.
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
53.
RADAR DEVICE HAVING SCANNING-ARRAY ANTENNAS WITH DIELECTRIC LENSING
Disclosed is a radar device comprising a lensed scanning-array unit, the lensed scanning-array unit comprising: a semiconductor package comprising: an array of antennas each having a respective feed on a first major surface of the semiconductor package and spaced apart along a first axis; and a radio frequency, RF, integrated circuit, IC, configured to operate with the first array of antennas as one of a scanning-array transmitter and a scanning-array receiver; and a lens arranged over the semiconductor package, and configured to focus incident radiation towards the semiconductor package; wherein the antenna feeds are arranged above a focal plane of the lens.
An apparatus for calibrating a digital filter to replicate a transfer function of a signal processing device comprising a detector with a first input to receive a first signal; a second input to receive a response signal of the signal processing device to the first signal; a signal modification block; a comparison block and a decimation block; wherein the comparison-block compares a phase and amplitude of the first signal after a correction has been applied by the signal modification block and decimation has been applied by the decimation block; and a feedback loop; wherein detector is configured to determine at least a feedback control signal at a first frequency and a second frequency, different to the first frequency and determine calibration information for programming of the transfer function of said digital filter.
The present disclosure relates to a Controller Area Network, CAN, device, wherein the CAN device is configured to transmit and receive CAN frames. The CAN device comprises a first queue configured to a first CAN frame, wherein a first queue credit is associated with the first queue, wherein the CAN device is configured to, if the first queue credit is greater than a predefined first reference value, start to transmit the first CAN frame of the first queue, and wherein the CAN device is configured to, if the first queue credit is less than the predefined first reference value, prevent transmission of the first CAN frame of the first queues.
An apparatus includes a SRAM element having a clock input, an address input, an SRAM output, and a first and second address space A clock signal causes the SRAM element to output the logic value stored in a designated address space. A logic arrangement couples the SRAM output to a register A feedback path receives an output of the logic arrangement and provides a feedback clock and address signal. In an oscillation mode, a one is stored in the first address space and a zero in the second address space, and the feedback path provides the output of the logic cell arrangement to the address input and provides the feedback clock signal to trigger the output of the logic value stored in the currently designated address space, Thereby the feedback path, the SRAM element, and the logic cell arrangement form an oscillation loop.
Disclosed is a scanning-array radar device comprising a transmitter and a receiver; wherein the transmitter comprises a first lensed scanning-array transmitter unit comprising: an array of transmit antennas each having a respective output feed spaced apart along a first axis; a radio frequency, RF, integrated circuit, IC, configured to operate with the array of transmit antennas as a scanning-array transmitter, and a lens configured to focus radiation from each of the output feeds; and wherein the receiver comprises a first lensed scanning-array receiver unit comprising: an array of receive antennas each having a respective input feed spaced apart along a second axis; a radio frequency, RF, integrated circuit, IC, configured to operate with the array of receive antennas as a scanning-array receiver, and a lens configured to focus radiation reflected from a target towards each of the input feeds.
A method is provided for visualizing a classification prediction by a machine learning model of a first image. A second image having similar features to the first image is chosen from a training data set used to train the machine learning model. A localization map is generated to show a location of similar features between the first and second images. The localization map includes a gradient of features toward a particular class to determine a relevance of the features determined to be mutually similar with respect to the particular class. The features not mutually similar with respect to the particular class are excluded from the localization map. The localization map is overlaid with the second image. A visualization of mutual class important features between the first and second images is generated from the overlay. The method may be implemented in a computer program having instructions executable by a processor.
G06V 10/771 - Feature selection, e.g. selecting representative features from a multi-dimensional feature space
G06V 10/74 - Image or video pattern matchingProximity measures in feature spaces
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/77 - Processing image or video features in feature spacesArrangements for image or video recognition or understanding using pattern recognition or machine learning using data integration or data reduction, e.g. principal component analysis [PCA] or independent component analysis [ICA] or self-organising maps [SOM]Blind source separation
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
A method for updating a device, including: receiving, by the device, a public one-time signature key; receiving, by the device, a secret encryption key; receiving an encrypted update package and signature from an update provider; verifying the signature using the public one-time signature key; decrypting the encrypted update package using the secret encryption key; and updating the device using the decrypted update package.
A system and method of digital to analog conversion including modulating a digital value DN-K with an oversampling delta sigma modulator to provide an M-bit coarse quantized value DM, in which DN-K comprises N-K least significant bits of an N-bit digital input value DN and in which quantization error may be shaped to a higher frequency above a signal band of interest, adding DM to a value DK to provide a select value DKM in which DK includes the K remaining most significant bits of DN, and applying mismatch shaping of a total of at least P=2K elements of a P-element DAC per cycle based on DKM to provide an analog output value. The analog output value may be filtered with a low-pass filter to provide a filtered analog output value. An order of low-pass filtering may be one more than an order of modulating.
A frequency beam-steered leaky wave antenna suitable for integration in a substrate such as a printed circuit board includes a waveguide formed from a first electrically-conductive surface and a second electrically conductive surfaces forming upper and lower surfaces of the waveguide and electrically-conductive vias form first and second sidewalls disposed between the upper and lower surfaces along a length of the waveguide. The waveguide has slotted openings distributed along the upper surface and a width of the waveguide is defined by a distance between the two sidewalls that varies along the length of the waveguide. A portion of radiofrequency energy travelling along a length of the waveguide is radiated away from the waveguide through the slotted openings. Performance characteristics of the antenna such as its directivity and operational bandwidth can be tuned by adjusting the geometry of the slotted openings and positioning of the vias.
H01Q 13/20 - Non-resonant leaky-waveguide or transmission-line antennas Equivalent structures causing radiation along the transmission path of a guided wave
H01Q 13/26 - Surface waveguide constituted by a single conductor, e.g. strip conductor
62.
MULTI-PULSE DRIVE CIRCUIT FOR POWER INTEGRATING LOAD
Multi-pulse drive circuits and methods for loads are described. In one example, a drive circuit includes a switch, and a storage capacitor coupled to the switch on one side and to a ground on the other side configured to supply power to the switch. The switch is configured to alternately connect and disconnect the storage capacitor to the load. A control circuit is coupled to the switch, configured to control the operation of the switch to provide a drive cycle to the load, the drive cycle having a series of pulses.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
A radar system includes transmitter modules configured to transmit radar signals and receiver modules. A controller is configured to encode a plurality of code division multiplexed radar, cause the plurality of transmitter modules to transmit the plurality of code division multiplexed radar signals as transmitted signals, receive reflections of the transmitted signals reflected by at least one object to generate signals based on the received reflections as observed signals, wherein a sparse matrix defines a relationship between the plurality of transmitter codes and values of the observed signals, execute a sparse recovery method to determine the sparse matrix, which is associated with distance estimates based on the observed signals, using the predefined code dictionary and the observed signals, estimating an attribute of the at least one object using the sparse matrix, and transmitting the attribute of the at least one object to a vehicle driver assistance system.
An earbud is provided having an earbud housing. Formed on a surface of the earbud housing are first and second conductive elements configured to form a first capacitive element. When the earbud is located within a charging case, the first and second conductive elements are arranged with a third conductive element mounted to an inside surface of the charging case in a location designed to influence a capacitance of the first and second conductive elements. An evaluation circuit of the earbud is positioned within the earbud housing and electrically coupled to the first and second conductive elements. In response to the first and second conductive elements having a capacitance value above a threshold, the evaluation circuit provides an indication the earbud is within the charging case. In another embodiment, a method is provided for detecting the earbud is within the charging case.
A processor including an instruction decoder configured to provide at least floating-point instruction control signals, a floating-point computational data path, a floating-point custom instruction control logic block coupled to the floating-point computational data path, a control and status register coupled to the floating-point computational data path, and the floating-point custom instruction control logic block, a first multiplexor configured to provide either floating-point instruction control signals or custom instruction control signals to the floating-point computational data path based on the state of a select control signal, and a second multiplexor configured to provide either floating-point operands or custom operands to the floating-point computational data path based on the state of the select control signal. The floating-point custom instruction control logic block asserts the select signal while directing the floating-point computational data path to assist it with the execution of a custom instruction. The custom instruction may be a floating-point exponential function.
G06F 7/483 - Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
66.
DEVICE FOR TESTING A CRYPTOGRAPHIC ALGORITHM HARDWARE
There is described a device for testing an electronic device, wherein the electronic device comprises a cryptographic algorithm, and wherein the cryptographic algorithm is a repetitive cryptographic algorithm, the device comprising a private key compression functionality, configured to compress a private key used to perform the cryptographic algorithm, and a test functionality, configured to perform or trigger the performance of the cryptographic algorithm by the electronic device using the compressed private key.
A method includes transmitting, with a transmitter, a first radar detection frame, and beginning a timer, at least in part based on the transmitting. The method also includes disabling a receiver, at least in part based on the transmitting. The method further includes enabling the receiver to receive a first radar detection response, at least in part based on the timer and a detection duration of a gating window of the receiver. In addition, the method includes receiving the first radar detection response with the receiver, the first radar detection response including a first reflection of a first target. The method additionally includes increasing the detection duration of the gating window, at least in part based on a determination that the first reflection of the first target was detected in the first radar detection response.
A variable gain arrangement of a receiver path configured to receive an input signal and apply a gain to the input signal to provide an output signal, comprising: an input capacitor arrangement comprising a first input capacitor; a feedback capacitor arranged in series with the input capacitor arrangement, wherein the gain is based on a ratio of the first input capacitor and the feedback capacitor; and a gain switching apparatus configured to provide for adjustment of the gain applied to the input signal by changing the ratio; an amplifier in series with the input capacitor arrangement, the amplifier arranged in parallel with the feedback capacitor, the amplifier configured to provide the output signal; and a transient compensation capacitor arrangement comprising a first transient compensation capacitor, wherein, upon a change in the gain, the at least one transient compensation capacitor is configured to be coupled to or decoupled from the feedback capacitor such that transient settling effects caused by the gain change are compensated.
A latch includes two outputs and two inputs where the outputs latch complementary values indicative of voltages at the latch inputs. The latch includes two sets of one or more inverters. For each set of inverters, the signal input of the first in series inverter is connected to a latch input and the output of the last in series inverter is connected to a latch output. The first in series inverters for each set of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by the other latch input. During a reset phase, the latch outputs are configured to be set to the same output value state. During a latching phase, the latch outputs are configured to be latched at complementary output value states. In some embodiments, the latch is used in a comparison circuit.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
A data processing system is provided that includes a memory, a processor, and a memory integrity circuit. The memory includes a plurality of memory regions configured to store information. The processor is configured to execute instructions to access an address in the memory. The memory integrity circuit is coupled to the processor and to the memory, and configured to validate read and write accesses to the memory by the processor. The memory integrity circuit validates a write access to an address of a memory region of the plurality of memory regions in response to n number of the read accesses being validated prior to the write access, where n is an integer, and in response to correctly calculating a message authentication code (MAC) of a combination of encrypted data stored at the address and a tweak value. In another embodiment, a method is provided for isolation security for the memory.
One example discloses a degradation circuit, including: a first structure configured to be coupled to an integrated circuit (IC); a second structure, coupled to the first structure, and configured to be coupled to the IC; wherein together the first and second structures form a degradation detection element; and a controller, coupled to the degradation detection element, and configured to set an operational state of the IC based on the degradation detection element.
The disclosure relates to decomposition of masked values in a cryptographically secure digital signing system. Example embodiments include a method of decomposing mod 44 an N bit Boolean share input (b′B,k), where N>12, the method comprising: i) reducing (302-305) a number of bits in the Boolean share input (b′B,k) by adding a lower 11:0 bits of the input (b′B,k) to an upper portion of the input left shifted by 2 bits to provide a first intermediate result (t1B,13) having M bits; ii) reducing (306-309) a number of bits of the first intermediate result (t1B,13) by adding a lower 6:0 portion of the intermediate result to an upper portion left shifted by 2 bits and subtracted from a multiple of 44 to provide a second intermediate result (t3B,8); and iii) adjusting (310-316) the second intermediate result (t3B,8) by adding and/or subtracting 44 to provide an output (w1B,k′) having a value within an interval of 0:43, the output (w1B,k′) being a mod 44 representation of the input (b′B,k).
H04L 9/34 - Bits, or blocks of bits, of the telegraphic message being interchanged in time
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
73.
ELECTRONIC DEVICE WITH WARPAGE MITIGATION AND METHOD THEREFOR
An electronic device with warpage mitigation is provided. The electronic device includes an electronic component mounted on a first major side of a device substrate and interconnected with a plurality of conductive traces of the device substrate. A heat sink having a raised feature is affixed with a second major side of the device substrate such that the raised feature is located below the electronic component.
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
74.
RADAR UNIT, CIRCUIT FOR A RADAR TRANSCEIVER AND METHOD THEREFOR
A radar unit includes a radar transceiver with a reference local oscillator (LO) and at least two transmitter paths arranged to transmit the reference LO. One transmitter path transmits the reference LO with a frequency shift of at least the ADC sampling frequency. A receiver coupled to two receiver paths includes a down-conversion circuit configured to receive a reflected radar signal and the reference signal and provide a down-converted baseband signal to a band-pass filter and an ADC. A DSP is configured to process the digital form of the down-converted, filtered, baseband signal. A frequency shifter circuit applies a frequency shift to the reference signal that shifts the transmit signals an amount where a first down-converted baseband signal is passed by a first bandpass filter in the first receiver path, and a second down-converted baseband signal is passed by a second bandpass filter in a second receiver path.
Embodiments of methods of providing a machine learning (ML) model for detection of radar targets are disclosed that include determining, using ultra-wideband circuitry, range data and location data from a range doppler map corresponding to one or more locations of one or more targets. The method may include determining, using the ML model, estimated target locations based on data from a Doppler range map and iteratively training the ML model based on differences between the estimated target locations and ground truth including a selected one of the location data or the range data.
A current comparator includes a first capacitor having a first terminal coupled to a first input signal, a second capacitor having a first terminal coupled to a second input signal, a first transistor having a control electrode coupled to a second terminal of the first capacitor, and a third transistor having a control electrode coupled to a second terminal of the second capacitor. First current electrodes of the first and second transistors are coupled, and second current electrodes of the first and second transistors are coupled to first and second circuit nodes, respectively. A single-ended cascode amplifier has an input coupled via a third capacitor to the second circuit node. A set of auto-zero switches, in response to an auto-zero control signal, selectively shorts the control electrode and second current electrode of the first transistor and selectively shorts the control electrode and the second current electrode of the second transistor.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In accordance with a first aspect of the present disclosure, a radar device is provided, comprising: a plurality of receiver channels; a plurality of mixers, wherein each of the receiver channels comprises one of said mixers; a first frequency synthesizer configured to generate a chirp signal; at least one test tone generator configured to generate a test tone signal having a constant frequency; wherein said mixers are configured to be fed with said chirp signal and with the test tone signal. In accordance with a second aspect of the present disclosure, a corresponding method of operating a radar device is conceived.
Systems and methods for performing both wireless communications and wireless sensing in combination are disclosed herein. In one example embodiment, the method includes sending, from a first antenna device of a base station (BS), a plurality of first wireless communication signals respectively during a first plurality of time periods associated respectively with a first plurality of symbols and also a plurality of first wireless sensing signals respectively during a second plurality of time periods associated respectively with a second plurality of symbols. Also, the method includes receiving, at the antenna device, a plurality of second wireless communication signals respectively during a third plurality of time periods associated respectively with a third plurality of symbols and also a plurality of second wireless sensing signals respectively during the second plurality of time periods. The second plurality of time periods are interleaved among respective pairs of the first plurality of time periods.
An ESD circuit includes an ESD clamp device with an ESD clamp transistor. The ESD clamp transistor has two sets of one or more body contacts. One set is coupled to a supply voltage rail and the other set is coupled to a clamp activation circuit. The clamp activation circuit is coupled to a clamp device. During an electrical stress event of a sufficient severity affecting a supply voltage rail, the activation circuit makes the clamp device conductive to transfer charge between supply voltage rails.
A circuit and method for testing failure of a connection between a radio frequency integrated circuit and external circuitry is described. The circuit includes a first amplifier having an input path and an output path, a second amplifier having an input path and an output path, a combiner for combining the signal from the output path of the first amplifier and the output path of the second amplifier, a coupler for receiving the output of the combiner, and a power detector coupled to the output of the coupler. The combiner is configured to send signals to the external circuitry. The power detector receives a reflected voltage from the external circuitry and determines that there is a connection failure between the RF circuit and the external circuitry when the reflected voltage exceeds a preset threshold voltage.
A system and method for processing received radar signals is presented. A steering matrix for the radar system is determined. A measurement vector is determined using signals received by a plurality of receiver modules. An output amplitude vector is initialized using the steering matrix and the measurement vector. An optimized output amplitude vector is determined by determining a diagonal loading vector using the output amplitude vector, calculating a weighting matrix using a first fast Fourier transform of the diagonal loading vector, determining an inverse matrix using the weighting matrix and an identity matrix, and executing a second fast Fourier transform using the inverse matrix to determine the optimized output amplitude vector, wherein the optimized output amplitude vector is determined by a relationship between the steering matrix and the measurement vector. An objects direction of arrival is determined by correlating the optimized output amplitude vector to the measurement vector.
A distributed radar system includes a management unit, a plurality of distributed radar units, and a dielectric waveguide network comprising a plurality of dielectric waveguides coupling the management unit to the plurality of distributed radar units. The management unit is configured to generate a reference signal for synchronization of operations of the plurality of distributed radar units. At least one of the distributed radar units may be configured to generate a digital data signal representative of results of a radar sensing operation of the distributed radar unit, the dielectric waveguide network may be configured to propagate a representation of the digital data signal to the management unit, and the management unit may be configured to control at least one operation of the distributed radar system based on the digital data signal.
An apparatus for processing radar signals is configured to receive a radar signal that includes a radar frame of a plurality of chirps, where the plurality of chirps includes at least a first group with a first pulse repetition interval, and a second group with a second pulse repetition interval. The groups are separated by a group separation time interval between a final chirp in the first group and a first chirp in the second group, where the group separation time interval is different than one or both of the first pulse repetition interval and the second pulse repetition interval. The apparatus further generates a modified received radar frame by performing a first extrapolation, based on temporal positions of the chirps in the first group of the received radar frame, to generate at least one extrapolated chirp in the modified received radar frame.
There is provided a radar system for a vehicle. The radar system includes a first radar unit with a first transmitter head and a first receiver head, a first coupling structure coupled to the first transmitter head or the first receiver head, and a first waveguide launcher coupled to the first coupling structure. The radar system further includes a second radar unit with a second transmitter head and a second receiver head, a second coupling structure coupled to the second receiver head, and a second waveguide launcher coupled to the second coupling structure. The radar system further includes a waveguide coupled between the first and second waveguide launchers. The radar system is configured to synchronize the radar units.
An integrated circuit DAC device and fabrication method are provided with a linear bias ladder circuit which generates a plurality of bias voltages, an inverting operational amplifier configured to generate an analog output voltage in response to an input current signal, and a plurality of MMT devices connected between the linear bias ladder circuit and the inverting operational amplifier to implement a DAC with a first current control gate of each MMT device connected to one of the plurality of N different bias voltages, with a second switch control gate of each MMT device connected to receive one of a plurality digital input code values, with a drain terminal of each MMT device connected to a digital bias voltage (Vdbias), and with a source terminal of each MMT device connected to provide the input current signal to the inverting operational amplifier.
An electronic device including a substrate having a first surface, a second surface, and one or more sidewalls. The electronic device may include a base metallization coupled to the first surface, one or more circuit layers formed on the second surface, and a dielectric layer on the one or more sidewalls and on the one or more circuit layers. The electronic device may include a metal layer formed on the dielectric layer. In some embodiments, one or more of the metal layer or the dielectric layer may form an ionic-contamination barrier. In some implementations, the metal layer, the dielectric layer, and one or more of the substrate or the base metallization layer may form a capacitor that extends around the one or more sides.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
87.
RADAR SYSTEM AND METHOD WITH INTERFERENCE SUPPRESSION
Radar systems and interference suppression methods are described, including a radar system that includes communication circuitry configured to transmit radar signals and to receive reflections of the transmitted radar signals reflected by an object in an environment of the radar system and processing circuitry. The processing circuitry is configured to generate a spectrogram by converting samples of the reflections into a time-frequency domain, determine a plurality of interference thresholds, including a respective interference threshold for each frequency bin of the spectrogram, identify interfered cells of the spectrogram based on the plurality of interference thresholds, determine scaling factors for the interfered cells based on at least the plurality of interference thresholds and magnitudes of the interfered cells, generate an interference-suppressed spectrogram by applying the scaling factors to the interfered cells to reduce the magnitudes of the interfered cells, and generate interference-suppressed samples based on the interference-suppressed spectrogram.
A semiconductor device, such as a heterojunction bipolar transistor (HBT), having a monocrystalline extrinsic base region may be formed via a method including steps of providing a substrate that includes a dielectric isolation region and a collector region that includes semiconductor material, forming a polycrystalline semiconductor layer over the substrate, forming a monocrystalline intrinsic base layer via epitaxial growth, where the intrinsic base layer is in direct contact with the polycrystalline semiconductor layer, removing the polycrystalline semiconductor layer after forming the monocrystalline intrinsic base layer, and forming a monocrystalline extrinsic base layer via epitaxial growth, where the monocrystalline extrinsic base layer is in direct contact with the monocrystalline intrinsic base layer.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A receiver includes an ultra-wideband, UWB, communication unit configured to operate in a radar mode and to receive a synchronization signal transmitted by a transmitter, and a synchronization unit operatively coupled to the UWB communication unit. The synchronization unit is configured to estimate a carrier frequency offset from the synchronization signal, derive a reference time from the synchronization signal, and derive a time window for the reception of a radar packet by the UWB communication unit. The time window is derived from the estimated carrier frequency offset and the reference time. A corresponding method of operating a receiver also is disclosed.
A semiconductor device is provided. The semiconductor device includes a leadframe having a plurality of leads. A first lead of the plurality of leads has a lead pad formed between a distal portion and a proximal portion of the first lead. A semiconductor die includes a plurality of bond pads located at an active side. Each bond pad of the plurality is connected to a respective lead of the plurality of leads. An encapsulant encapsulates the semiconductor die and at least a portion of the leadframe. A distal portion of each lead is exposed through the encapsulant at a first major side. The lead pad is exposed through the encapsulant at a second major side opposite of the first major side.
A radar system boots one or more radar sensors used in motor vehicles. Rather than storing software boot images, at different non-volatile memory (NVM) devices attached to each radar sensor module, the radar system supports booting of multiple radar sensors from the software boot images stored on the NVM device associated with a host. By booting multiple radar sensors with the boot images stored in a single NVM device, the overall number of NVM devices, and therefore the overall cost of the radar system, is reduced.
G01S 13/931 - Radar or analogous systems, specially adapted for specific applications for anti-collision purposes of land vehicles
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
One example discloses a first wireless device, including: a receiver configured to receive a symbol sequence in a wireless communication frame transmitted from a second wireless device; a first demodulator configured to generate a first differential symbol sequence by differentiating the received symbol sequence; a first correlator configured to compare the first differential symbol sequence to a first differential sync word; wherein the first correlator is configured to generate a first match signal if the first differential symbol sequence substantially matches the first differential sync word; a second demodulator configured to generate a second differential symbol sequence by differentiating the first differential symbol sequence; a second correlator configured to compare the second differential symbol sequence to a second differential sync word; wherein the second correlator is configured to generate a second match signal if the second differential symbol sequence substantially matches the second differential sync word.
Compact battery powered wireless devices such as automotive key fobs that enable secure vehicle access can realize improved battery life and user experience by including a wake-up receiver that wakes up near-field communication (NFC) circuitry and other circuitry such other communication circuitry (e.g., ultrawideband or Bluetooth circuitry) that is configured to operate with an antenna system that enables the device to detect a wake-up signal generated by an external NFC device at much longer distances than conventional wake-up receivers, even at low power levels, by modifying the wake-up receiver to operate in a frequency band in which the near-field regime can extend to at least one meter and wireless signals are not strongly attenuated by a user's body or clothing. The frequency band can also be chosen to coincide with communication frequencies used by legacy NFC and radiofrequency ID readers such as 13.56 MHz.
In a radiofrequency (RF) system with multiple transceivers configured to operate together (e.g., in beamforming applications), phase, delay, gain, or other offsets between individual transceivers can be compensated by pairwise measurements of RF signals transmitted by one active transmitter at a time as received by the receiver of the active transceiver and the receiver of another transceiver.
A fault detection circuit can detect setup time and/or hold time faults which can indicate a possible fault injection attack using flip-flop circuits which are powered by a supply voltage and receive a clock signal. A hold time violation can be identified by providing the clock signal to a data input of a D flip-flop or equivalent circuit, and the complement of the clock signal, with a predetermined delay to clock input of the flip-flop. The hold time violation is indicated when the inverted and delayed clock signal has a different voltage from the uninverted (and undelayed) clock signal. Setup time violations can be identified by connecting the inverted output of each of a pair of flip-flops to their respective data input terminals in a feedback arrangement. For one of the flip flops, the feedback loop includes a predetermined delay. A setup time fault is indicated when the output voltages of the two flip-flops are different from each other.
One example discloses a multi-display controller, including: a focus detector configured to detect an attention of a user; and one or more rendering engines configured to vary an attribute of at least one display in a set of two or more displays based the attention of the user.
One example discloses a digital radio signal receiver, including: wherein the receiver is configured to be coupled to a device; wherein the device is coupled to receive an RF signal; wherein the RF signal includes a desired signal and interference; wherein the receiver is configured to receive a first signal and interference model from an off-device training stage; an on-device training stage configured to construct a second signal and interference model based on the first signal and interference model and the RF signal received by the device; and a decoder configured to generate a set of data from the RF signal based on the second signal and interference model.
A method, system, apparatus, and architecture are provided for monitoring, handling, and escalating faults from a plurality of SoC subsystems by deploying at least one FCU instance at each SoC subsystem, where each FCU instance is configured to monitor one or more fault input signals at one or more fault inputs, to generate a local control signal for one or more hardware resources controlled by the FCU instance, and to escalate any unresolved fault on a fault output, and where a first plurality of FCU instances deployed at a first plurality of SoC subsystems are each connected in a fault escalation tree with an escalation FCU instance deployed at a first management SoC subsystem by connecting the fault outputs from the first plurality of FCU instances to the one or more escalation fault inputs of the escalation FCU instance deployed at the first management SoC subsystem.
A device includes a radar processor that transmits, at a first time, a first radar signal, receives a received signal, and processes the received signal to generate a range-Doppler data frame. The radar processor determines a first snapshot comprising a first plurality of values associated with a first range-Doppler bin of the range-Doppler data frame and processes the first plurality of values in the first snapshot to generate an autoregressive model based upon the first plurality of values. The radar processor uses use the autoregressive model to extrapolate a second snapshot, wherein the second snapshot includes the first plurality of values and a second plurality values generated using the autoregressive model, determines, using the second snapshot, a full rank covariance matrix, and identifies attributes of a plurality of objects using the full rank covariance matrix.
A system and method for processing received radar signals is presented. A range-Doppler map is determined that includes values associated with a plurality of range bins and a plurality of Doppler bins. A subarray is determined using the range-Doppler map. A plurality of spectra are calculated using the first subarray. Each spectra in the plurality of spectra is associated with a transmit channel of a plurality of transmit channels. Attributes of each spectrum in the plurality of spectra are determined. A first spectrum in the plurality of spectra that includes local peaks that are not in the other spectra in the plurality of spectra is determined. Values in the range-Doppler map associated with the transmit channel associated with the first spectrum are modified to determine a corrected range-Doppler map. An estimated direction of arrival of a first object is determined using the corrected range-Doppler map.
