Voltages and currents associated with a driver circuit associated with a diode can be controlled during start up of the driver circuit. The driver circuit can comprise transistors that can satisfy a defined bandwidth specification in connection with driving an electrical signal for the diode. During start up, start-up controller component can control voltage levels applied to gates or backgates of transistors to maintain operating voltage levels associated with transistors at or below a defined voltage level as bias current level is incrementally increased to target bias current level, and/or start-up reference voltage level is incrementally increased to facilitate incrementally increasing an anode voltage level of an anode voltage associated with the diode. The driver circuit can supply the electrical signal to the diode based on the bias current, which can facilitate operation of the driver circuit.
H01S 5/183 - Lasers à émission de surface [lasers SE], p. ex. comportant à la fois des cavités horizontales et verticales comportant uniquement des cavités verticales, p. ex. lasers à émission de surface à cavité verticale [VCSEL]
A power amplifier die according to some embodiments includes a substrate, a transistor formed on the substrate, and an integrated passive device, IPD, formed on the substrate adjacent to the transistor. A wire bond electrically connects the transistor and the IPD on the substrate. A method of manufacturing a power amplifier die is also provided.
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
3.
MULTI-TIP WAVEGUIDE COUPLER WITH IMPROVED ALIGNMENT GUIDANCE
Disclosed are various embodiments for a multi-tip laser coupler with improved alignment guidance. A photonic integrated circuit (PIC) includes an input interface, an output interface, and a waveguide array. The waveguide array includes a first waveguide, a second waveguide, and a third waveguide. The first waveguide and the third waveguide are coupled to the input interface and are not coupled to the output interface. The second waveguide is coupled to the input interface and the output interface. Further, the second waveguide is positioned parallel to and between the first waveguide and a third waveguide. The second waveguide includes a tapered body such that an output end of the second waveguide coupled to the output interface is wider than an input end of the second waveguide coupled to the input interface.
Resonators and devices including resonators are described. An illustrative resonator includes a metal bottom electrode, a metal top electrode, and a piezoelectric layer positioned between the metal bottom electrode and the metal top electrode. At least one property of the metal bottom electrode may differ from at least one property of the metal top electrode such that the metal bottom electrode, the metal top electrode, and the piezoelectric layer provide a resonator target frequency as if the metal top electrode and metal bottom electrode were symmetrically configured, but provide a higher electromechanical coupling coefficient (kt2) as compared to a symmetrical configuration of the metal bottom electrode and the metal top electrode.
Monolithic devices including combinations of diodes, with electrical components fabricated and electrically connected among them, are described herein, along with process techniques for forming the devices. An example method of forming a monolithic semiconductor circuit includes forming a plurality of layers of semiconductor materials over a substrate, forming Schottky diode contacts for a Schottky diode on a first subset of the plurality of layers, and forming PIN diode contacts for a PIN diode on a second subset of the plurality of layers. The layers can include an etch stop layer, and the etch stop layer can be positioned between the first subset of the plurality of layers and the second subset of the plurality of layers. The method can also include etching the layers of semiconductor materials down to the etch stop layer after forming the Schottky diode contacts and before forming the PIN diode contacts.
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
Aspects of gate voltage level shifting circuits are described. An example power amplifier includes a depletion mode power transistor and a level shift circuit. The level shift circuit is configured to generate a level-shifted gate bias control signal for the depletion mode power transistor based on a gate bias control signal. Among other benefits, the level shift circuit facilitates the replacement of the power transistor in a power amplifier system, particularly in cases where the gate bias control levels generated by the amplifier system are insufficient to completely pinch-off the depletion mode power transistor.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
Aspects of gate voltage level shifting circuits are described. An example power amplifier includes a depletion mode power transistor and a level shift circuit. The level shift circuit is configured to generate a level-shifted gate bias control signal for the depletion mode power transistor based on a gate bias control signal. Among other benefits, the level shift circuit facilitates the replacement of the power transistor in a power amplifier system, particularly in cases where the gate bias control levels generated by the amplifier system are insufficient to completely pinch-off the depletion mode power transistor.
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03K 19/0185 - Dispositions pour le couplageDispositions pour l'interface utilisant uniquement des transistors à effet de champ
A decoupling network for a radio frequency (RF) circuit includes a first decoupling capacitor coupled to a decoupling node of the RF circuit, a second decoupling capacitor coupled to the decoupling node of the RF circuit in parallel with the first decoupling capacitor, and an additional resistance in series with the first decoupling capacitor or the second decoupling capacitor.
A Doherty amplifier die according to some embodiments includes a substrate having a bandgap of above about 2 eV, a main amplifier, at least one peak amplifier, an input network connected to a first input of the main amplifier and to a second input of the at least one peak amplifier, an output combiner connected to a first output of the main amplifier and to a second output of the at least one peak amplifier; and an isolation structure arranged on the substrate between the input network and the output combiner. The isolation structure is configured to isolate the input network and the output combiner.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
Athermal arrayed waveguide grating structure that may operate as an optical filter including an input Silicon (Si) slab waveguide, an output Si slab waveguide, the input Si slab waveguide and the output Si slab waveguide optically connected by an arrayed group of Silicon Nitride (SiN) grating waveguides. Temperature insensitivity of the structure is achieved by locating output waveguide(s) of the Si output slab waveguide at/within a 10-degree angle offset from the center line of the output Si slab waveguide.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
A three-way Doherty amplifier according to some embodiments includes a first ratio of a gate width of a main amplifier to a first gate width of a first peak amplifier and a second ratio of the gate width of the main amplifier to a second gate width of a second peak amplifier, respectively, are configured to provide a substantially constant load on the main amplifier.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
A package including an IPD according to some embodiments includes a circuit board; and a flip chip (FC) IPD die including a substrate material and at least one capacitor or inductor, The FC IPD die is mounted so that the at least one capacitor or inductor face an upper surface of the circuit board. The package further includes a top-side cooling structure thermally connected to a first planar surface of the FC IPD die. The first planar surface of the FC IPD die includes the substrate material. The package further includes at least one first mechanical support thermally connecting the circuit board to a second planar surface of the FC IPD die. The second planar surface of the FC IPD includes the at least one capacitor or inductor.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
A configurable optical driver circuit includes an adjustable current source circuit configurable to drive one of a variety of different types of electrical to optical devices, an adjustable back-termination resistance circuit configurable to provide a back-termination resistance to one of a variety of different electrical to optical devices, and a programmable memory configured to provide configuration information to the adjustable current source circuit and to the adjustable back-termination resistance circuit to configure the adjustable current source circuit and the adjustable back-termination resistance circuit for operation with the one of a variety of different electrical to optical devices.
A device may include at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die. Also, the device may include drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die. Furthermore, the device may include source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die. In addition, the device may include a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers. Moreover, the device may include where the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad.
A device may include at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die. Also, the device may include drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die. Furthermore, the device may include source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die. In addition, the device may include a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers. Moreover, the device may include where the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad.
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
16.
CONFIGURABLE METAL - INSULATOR - METAL CAPACITOR AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
A metal-insulator-metal (MIM) capacitor component that includes a substrate, where the metal-insulator-metal (MIM) capacitor component is configured to form a first capacitor with a top metal and a first bottom metal having a dielectric layer therebetween; and where the metal-insulator-metal (MIM) capacitor component is configured to form a second capacitor with the top metal and a second bottom metal having the dielectric layer therebetween. Additionally, the top metal, the dielectric layer, the first bottom metal, and the second bottom metal are arranged on the substrate.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
Systems, circuits, and methods for mixing signals are provided. An illustrative circuit may include mixer circuitry including multiple inputs and at least one output, where the multiple inputs are connected across a local oscillator. The circuit may further include a terminal Radio Frequency (RF) output circuitry that is isolated from the local oscillator, where the at least one output of the mixer circuitry is directly connected to an input of the terminal RF output circuitry. The circuit may further include terminal Intermediate Frequency (IF) output circuitry that is isolated from the local oscillator, where the at least one output of the mixer circuitry is directly connected to an input of the terminal IF output circuitry.
H03D 7/12 - Transfert de modulation d'une porteuse à une autre, p. ex. changement de fréquence au moyen de dispositifs à semi-conducteurs ayant plus de deux électrodes
H03H 7/06 - Réseaux à deux accès sélecteurs de fréquence comprenant des résistances
Offset calibration for signal rms measurement is provided. A method includes determining a first offset calibration of a first differential pair of a circuit. The first differential pair comprises a first transistor and a second transistor. The method also includes determining a second offset calibration of a second differential pair of the circuit. The second differential pair comprises a third transistor and a fourth transistor. Further, the method includes, based on the first offset calibration and the second offset calibration, determining a third offset calibration of a common mode.
Adjustments to supply voltage level associated with an amplifier can be controlled based on a state associated with an automatic gain control (AGC) component associated with the amplifier. The AGC component can determine the AGC state based on an output signal associated with the amplifier component. Supply voltage controller component (SVCC) of an amplifier regulator can control a supply voltage level of a supply voltage supplied to the amplifier component by the amplifier regulator based on a state value indicative of the AGC state and received from AGC component, and a threshold supply voltage level associated with a threshold state value. If the state value does not satisfy threshold state value, SVCC adjusts or maintains supply voltage at the threshold supply voltage level. If the state value satisfies threshold state value, SVCC adjusts or maintains supply voltage at a desired supply voltage level that corresponds to the AGC state.
Aspects of an amplifier with bias stabilization are described. In one example, an amplifier includes an output amplifier stage having an input terminal, a biasing leg having a biasing node coupled to the input terminal, and a bias feedback network coupled between the input terminal of the output amplifier stage and the biasing leg. The bias feedback network can include a difference amplifier, a bypass stage, and a reference voltage generator in one example. The difference amplifier can generate a bias control signal based on a difference between a bias voltage at a base terminal of the output amplifier stage and a voltage reference generated by the reference voltage generator. The bias feedback network generates the bias control signal and controls the bias voltage based on feedback, to keep the bias voltage and bias current constant over process, temperature, gain and other variations for consistent performance.
An angular deviation optical tracking and detector device for use in optical systems such as a FSO communication systems—among others. The angular deviation optical tracking and detector device includes position sensor elements that are configured to detect any misalignment of incoming/received light and an optical tunnel structure coupled with a detector array to determine the angular deviation. The optical tracking and detector device includes a position sensor having an optical aperture configured to allow a portion of incoming light to pass through the position sensor; a plurality of position receivers positioned adjacent to the optical aperture, the plurality of position receivers configured to sense portions of the incoming light; and an optical detector array configured to detect portions of the incoming light that passes through the position sensor aperture and optical tunnel. Angular deviation may be determined from diode array readout of illuminated individual diodes.
G01S 3/781 - Radiogoniomètres pour déterminer la direction d'où proviennent des ondes infrasonores, sonores, ultrasonores ou électromagnétiques ou des émissions de particules sans caractéristiques de direction utilisant des ondes électromagnétiques autres que les ondes radio Détails
Independent control loops for mitigating positive and negative mismatch in differential amplifiers are provided. A method includes comparing a first voltage measured at a positive side output of an emitter follower with a reference voltage, resulting in a first voltage difference. The method also includes comparing a second voltage measured at a negative-side output of the emitter follower with the reference voltage, resulting in a second voltage difference. In addition, the method includes independently controlling the positive side and the negative side of the differential amplifier based on the first voltage difference and the second voltage difference.
An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.
A biasing circuit for biasing an output transistor in a radio frequency (RF) amplifier includes a first field-effect transistor (FET) monolithically integrated with the output transistor, the first FET being connected to the output transistor in a current mirror configuration, such that a gate-to-source voltage of the first FET is the same as a gate-to-source voltage of the output transistor, and a drain current in the first FET is matched to a drain current in the output transistor and scaled proportionally according to a size of the first FET relative to a size of the output transistor. The biasing circuit further includes a voltage divider integrated with the first FET and connected to a current source, the voltage divider being configured to generate a voltage that is substantially independent of process, voltage and/or temperature variations for controlling the drain current in the first FET.
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/08 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs
H03F 1/34 - Circuits à contre-réaction avec ou sans réaction
25.
VERSATILE ADAPTIVE VOLTAGE SCALING CONTROL CIRCUIT, RELATED APPARATUSES, AND RELATED METHODS
A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.
An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.
A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/04 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques
28.
SEMICONDUCTOR DIE WITH GROUP III NITRIDE-BASED AMPLIFIER CIRCUITS
A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
29.
SEMICONDUCTOR DIE WITH GROUP III NITRIDE-BASED AMPLIFIER CIRCUITS
A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
A Doherty amplifier circuit includes a main amplifier section and a peaking amplifier section, an output of the peaking amplifier section being connected to an output of the main amplifier section at a combining node in the Doherty amplifier circuit. The Doherty amplifier circuit further includes a direct current (DC) blocking capacitor connected between the combining node and an output of the Doherty amplifier circuit.
H03F 1/42 - Modifications des amplificateurs pour augmenter la bande passante
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
31.
THERMALLY CONDUCTIVE INTERPOSER, A DEVICE IMPLEMENTING A THERMALLY CONDUCTIVE INTERPOSER, AND PROCESSES FOR IMPLEMENTING THE SAME
A thermally conductive interposer includes an interposer substrate having a first substrate surface and a second substrate surface. The first substrate surface being configured to be attached to a first device component. The second substrate surface being configured to be attached to a second device component. The interposer substrate being configured to support the second device component on the first device component and integrate the first device component and the second device component within a microelectronic device. Further, the interposer substrate is configured to transfer heat between the first device component and the second device component; and the interposer substrate is configured to be electrically nonconductive.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
32.
Group III Nitride Doherty Amplifier Using Different Epitaxial Structures
A Doherty amplifier comprises a main amplifier and a peaking amplifier. The main amplifier and the peaking amplifier are electrically connected to a same input signal source. The main amplifier and the peaking amplifier comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier, the main amplifier and the peaking amplifier are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier and peaking amplifier, respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers are electrically connected to the input signal source.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
33.
GROUP III NITRIDE DOHERTY AMPLIFIER USING DIFFERENT EPITAXIAL STRUCTURES
A Doherty amplifier (10) comprises a main amplifier (18a) and a peaking amplifier (18b). The main amplifier (18a) and the peaking amplifier (18b) are electrically connected to a same input signal source. The main amplifier (18a) and the peaking amplifier (18b) comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier (10), the main amplifier (18a) and the peaking amplifier (18b) are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers (18a, 18b) comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier (18a) and peaking amplifier (18b), respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers (18a, 18b) are electrically connected to the input signal source.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. An example integrated amplifier includes an amplifier cell and a stability capacitor. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement. The common gate transistor includes a plurality of contacts. The stability capacitor is coupled between an output for the integrated amplifier and a gate of the common gate transistor. The stability capacitor is formed among the plurality of contacts of the common gate transistor over the semiconductor die. In one example, the stability capacitor includes a plurality of stability capacitors distributed among the plurality of contacts of the common gate transistor. The stability capacitor can also be distributed along an interconnect feed finger that extends between the contacts of the common gate transistor.
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
35.
OPTIMAL EQUALIZATION PARTITIONING WITH A LINEAR RECEIVER SIGNAL PATH
An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.
An electrode structure for a device, such as a GaN or AlGaN device is described. An example electrode structure includes a substrate with a gallium nitride material layer, an insulating layer formed on the substrate, the insulating layer including an opening that exposes a surface region of the gallium nitride material layer through the opening, a barrier metal layer on the surface region of the gallium nitride material layer and on a region of the insulating layer, and a conducting metal layer on the barrier metal layer. In other aspects, the electrode structure can also include a cap metal layer on the conducting metal layer, and a cap etch photoresist layer over the cap metal layer. The cap metal layer, the conducting metal layer, and the barrier metal layer can be etched down to the insulating layer over an area outside a width of the cap etch photoresist layer.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
37.
PACKAGED DEVICE HAVING AN INTEGRATED PASSIVE DEVICE WITH WAFER LEVEL FORMED CONNECTION TO AT LEAST ONE SEMICONDUCTOR DEVICE AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
38.
PACKAGED DEVICE HAVING AN INTEGRATED PASSIVE DEVICE WITH WAFER LEVEL FORMED CONNECTION TO AT LEAST ONE SEMICONDUCTOR DEVICE AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.
A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes a P-type silicon substrate, an intrinsic layer formed on the P-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first N-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second N-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional N-type regions can be formed to other depths.
A power amplifier, such as a radio-frequency (RF) Doherty power amplifier, for amplifying an input signal to an output signal is disclosed. The power amplifier includes a peaking amplifier circuit, where the peaking amplifier circuit is formed in gallium nitride materials on a silicon substrate. The power amplifier further includes a main amplifier circuit, where the main amplifier circuit is formed in gallium nitride materials on a silicon carbide substrate.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/24 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C d'étages transmetteurs de sortie
41.
COMPONENT CONFIGURED WITH INTRINSIC SHIELDING AND PROCESS OF IMPLEMENTING THE SAME
A shielded capacitor includes a first terminal; one or more first capacitor metals electrically connected to the first terminal; a second terminal; one or more second capacitor metals electrically connected to the second terminal. The shielded capacitor further includes a shielding structure. The shielding structure being configured to limit a variation of an RF characteristic due to a presence of a metallic structure.
A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.
A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.
A number of different types of semiconductor material structures and wafers, including epiwafers, are described herein. The semiconductor material wafers are optimized in certain aspects to form transistor amplifiers for use with new modulation communications systems. A semiconductor material wafer includes a silicon carbide substrate and at least one III-nitride material layer over the silicon carbide substrate. The semiconductor material wafers can include layers consisting of semiconductor materials without dopants such as iron or carbon, formed over the silicon carbide substrate.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 23/488 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de structures soudées
47.
BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY
A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
H01L 23/482 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
48.
METHODS OF FORMING PACKAGED SEMICONDUCTOR DEVICES AND LEADFRAMES FOR SEMICONDUCTOR DEVICE PACKAGES
A leadframe blank includes a first package blank, a second package blank and a tie bar between the first package blank and the second package blank. The tie bar includes a recessed cavity therein.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
Aspects of coaxial to microstrip transitional housings are described. A method of forming a transitional housing includes forming a channel to a first depth into a housing block from a top surface of the housing block, forming a first annular opening to a second depth into the housing block from the top surface of the housing block at a first end of the channel, forming a second annular opening to the second depth into the housing block from the top surface of the housing block at a second end of the channel, inserting a first cylindrical plug into the first annular opening, and inserting a second cylindrical plug into the second annular opening. The second depth can be greater than the first depth in some cases.
Semiconductor structures including III-nitride materials are described herein, including semiconductor structures comprising III-nitride material regions (e.g., gallium nitride material regions). An example semiconductor structure includes a substrate, a III-nitride material region located over the substrate, a first-type electrode over the III-nitride material region, and a second-type electrode over the III-nitride material region. The first-type electrode defines a first electrode interfacial area with the III-nitride material region. The second-type electrode defines a second electrode interfacial area with the III-nitride material region. The first electrode interfacial area is less than 20 times the second electrode interfacial area in at least one example.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/15 - Structures avec une variation de potentiel périodique ou quasi périodique, p.ex. puits quantiques multiples, superréseaux
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Electrode structures and methods of manufacturing electrode structures for devices are described. An example electrode structure includes a gate metal formation including a nitride layer with an opening that exposes a surface region of a substrate, a gate metal layer on the surface region of the substrate, a barrier metal layer on the gate metal layer and on at least a portion of a step around the opening in the nitride layer, and a conductive metal layer on the barrier metal layer. The gate metal layer is on the surface region of the substrate and on at least another portion of the step around the opening in the nitride layer in one example. The gate metal layer includes first and second gate metal layers in one example, such as nickel and tungsten.
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
A balun is enhanced with design features that extend the operational bandwidth of the balun allowing the balun to operate at lower frequencies. The design enhancements also suppress resonances that otherwise cause sudden power drops at a resonance frequency while a load is connected between the balun's differential outputs.
H01P 5/10 - Dispositifs de couplage du type guide d'ondes destinés au couplage de lignes ou de dispositifs de différentes sortes destinés au couplage de lignes ou de dispositifs équilibrés avec des lignes ou des dispositifs déséquilibrés
H03H 7/42 - Réseaux permettant de transformer des signaux équilibrés en signaux non équilibrés et réciproquement, p. ex. baluns
53.
ADAPTIVE TEMPERATURE PEAKING CONTROL FOR WIDEBAND AMPLIFIERS
Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.
Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.
H01L 21/76 - Réalisation de régions isolantes entre les composants
H01L 21/765 - Réalisation de régions isolantes entre les composants par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
59.
INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
An enhanced electrical circuit can employ conductive fill components that can facilitate providing desirable resistive stabilization of the electrical circuit and other desirable circuit qualities without having to use a physical resistor. The electrical circuit can comprise a transmission line, which can be a microstrip line, that can have defined dimensions. The electrical circuit can comprise respective conductive fill components that can be in proximity to desired sides of the transmission line, wherein the respective conductive fill components can provide the desired resistive stabilization for the electrical circuit. The respective conductive fill components can be separated from, and not in contact with, each other based on respective gaps of a defined size(s) between respective adjacent conductive fill components. The respective conductive fill components can be across a single layer or multiple layers of conductive fill components.
H01P 11/00 - Appareils ou procédés spécialement adaptés à la fabrication de guides d'ondes, résonateurs, lignes ou autres dispositifs du type guide d'ondes
A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.
H01G 4/40 - Combinaisons structurales de condensateurs fixes avec d'autres éléments électriques non couverts par la présente sous-classe, la structure étant principalement constituée par un condensateur, p. ex. combinaisons RC
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
62.
LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS
An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
63.
CAPACITOR NETWORKS FOR HARMONIC CONTROL IN POWER DEVICES
New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are described. An example capacitor network includes a bond pad and metal-insulator-metal (MIM) capacitors positioned over the top side of the substrate and along different sides of the bond pad. A first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad. A second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane on a bottom side of the substrate by a through-substrate via. The MIM capacitors can be arranged around the bond pad in the capacitor network for a tailored capacitance. A matching network in the integrated device can incorporate the capacitor network to reduce loss, provide better harmonic termination, and achieve better phase alignment for the power devices.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
64.
RADIO FREQUENCY POWER AMPLIFIER IMPLEMENTING AN OFF MODE OUTPUT IMPEDANCE CONTROL AND A PROCESS OF IMPLEMENTING THE SAME
Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
H01L 21/8252 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie III-V
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
66.
High Frequency, High Temperature Transistor Devices
Transistor devices are provided. In one example, a transistor device includes a Group III nitride-based semiconductor structure. The transistor device has a non-degradation time of at least about 350 hours without degrading an output power of the transistor device by 1 dB or greater during a test condition. The test condition is associated with an operating frequency of the transistor device of about 31.5 GHz and a junction temperature of the transistor device of about 380° ° C.
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.
H01S 5/0625 - Dispositions pour commander les paramètres de sortie du laser, p. ex. en agissant sur le milieu actif en faisant varier le potentiel des électrodes dans des lasers à plusieurs sections
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.
Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.
An amplifier circuit has a variable gain amplifier including an input receiving an input signal and an open-conduction output, and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit. The variable gain amplifier has a first transistor and second transistor each having a control input receiving the input signal. A third transistor has a control terminal receiving a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output. A fourth transistor has a control terminal receiving the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output.
Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Power amplifiers including balanced coaxial baluns are described. One example includes first and second amplifiers coupled to a balanced pair of first and second microstrip lines on a circuit board. A balun is coupled between the microstrip lines at a balanced end and between a conductive trace and a ground plane of the circuit board at an unbalanced end of the balun. The balun includes a coaxial balun line and a surface mount balancing inductor. The coaxial line includes center and shield conductors. A first end of the center conductor is coupled to the first microstrip line and a first end of the shield conductor is coupled to the second microstrip line at the balanced end of the balun. The balancing inductor is coupled between the first microstrip line and the ground plane to maintain symmetry for the balanced pair of microstrip lines.
H01P 5/10 - Dispositifs de couplage du type guide d'ondes destinés au couplage de lignes ou de dispositifs de différentes sortes destinés au couplage de lignes ou de dispositifs équilibrés avec des lignes ou des dispositifs déséquilibrés
H01Q 1/48 - Moyens de mise à la terreÉcrans de terreContrepoids
A transistor device may include a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer; a source contact and a drain contact on the barrier layer; a gate contact on the semiconductor structure between the source contact and the drain contact, the gate contact including a drain-side wing portion extending from a central portion of the gate contact; and a field plate on the semiconductor structure between the gate contact and the drain contact and laterally offset from the gate contact by a distance. The field plate may include a first wing portion extending from a central portion of the field plate.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.
An enhanced current mirror can be utilized to accurately control a bias current associated with an amplifier. A current controller component (CCC) can employ the enhanced current mirror and can be associated with the amplifier. The CCC can comprise a comparator that can compare an adjusted supply voltage level to a reference voltage level, the adjusted supply voltage level relating to a supply voltage level of a supply voltage supplied to the amplifier and CCC. The CCC can control switching of an operational state of a transistor of the comparator to switch in or out a resistance of a reference resistor component associated with the supply voltage, based on a result of the comparison of the adjusted supply voltage level to the reference voltage level, to facilitate accurately controlling an amount of bias current associated with the amplifier. The CCC and amplifier can be situated on the same die.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
77.
RF AMPLIFIERS WITH IMPROVED STABILITY BY SOURCE INDUCTANCE ADJUSTMENT
A radio frequency transistor amplifier package includes a package substrate with input, output, and ground terminals, and a transistor die on the package substrate. The transistor die includes a semiconductor structure having a plurality of transistors and gate, drain, and source contacts electrically coupled thereto. An inductance adjustment element is electrically coupled between the source contacts and the ground terminal, and is configured to provide a stability factor K of greater than or equal to 1 for a first operating frequency range of the transistor die. Related devices and methods are also discussed.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
78.
ADAPTIVE TEMPERATURE PEAKING CONTROL FOR WIDEBAND AMPLIFIERS
Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.
H03F 1/30 - Modifications des amplificateurs pour réduire l'influence des variations de la température ou de la tension d'alimentation
79.
SYMMETRICAL COMMON GATE DIRECT CURRENT BIAS NETWORK FOR STACKED FIELD EFFECT TRANSMITTER DISTRIBUTED HIGH-POWER AMPLIFIER, RELATED APPARATUSES AND RELATED METHODS
A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier (400), related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages (206, 208, 210, 212) connected in parallel between an input port (RF_IN) and an output port (RF OUT). The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages (206, 208, 210, 212). The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/22 - Modifications des amplificateurs pour réduire l'influence défavorable de l'impédance interne des éléments amplificateurs par utilisation de couplage dit "cascode", c.-à-d. étage avec cathode ou émetteur à la masse suivi d'un étage avec grille ou base à la masse respectivement
H03F 3/60 - Amplificateurs dans lesquels les réseaux de couplage ont des constantes réparties, p. ex. comportant des résonateurs de guides d'ondes
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
80.
SYMMETRICAL COMMON GATE DIRECT CURRENT BIAS NETWORK FOR STACKED FIELD EFFECT TRANSMITTER DISTRIBUTED HIGH-POWER AMPLIFIER, RELATED APPARATUSES AND RELATED METHODS
A symmetrical common gate direct current bias network for stacked field effect transmitter distributed high-power amplifier, related apparatus, and related method are provided. An apparatus includes a plurality of amplifier stages connected in parallel between an input port and an output port. The apparatus can also include a first common gate voltage generator operatively connected at a first side of the plurality of amplifier stages and a second common gate voltage generator operatively connected at a second side of the plurality of amplifier stages. The first common gate voltage generator can be operatively connected to the second common gate voltage generator in a symmetrical configuration.
Aspects of the present disclosure describe a voice coil actuated leaf spring prober that advantageously may be operated to probe every individual device (device under test—DUT) comprising a contemporary wafer. The prober according to aspects of the present disclosure includes one or more probe needles attached in an electrically isolated arrangement to an end of a horizontal-U-shaped, recurved, leaf spring arrangement. The prober includes—for example—a voice coil actuator positioned within the horizontal-U-shaped portion of the leaf spring which—when operated—results in leaf spring displacement and probe needle movement such that it may mechanically/electrically contact the DUT.
Aspects of the present disclosure describe a voice coil actuated leaf spring prober that advantageously may be operated to probe every individual device (device under test – DUT) comprising a contemporary wafer. The prober according to aspects of the present disclosure includes one or more probe needles attached in an electrically isolated arrangement to an end of a horizontal-U-shaped, recurved, leaf spring arrangement. The prober includes – for example – a voice coil actuator positioned within the horizontal-Ushaped portion of the leaf spring which – when operated – results in leaf spring displacement and probe needle movement such that it may mechanically/electrically contact the DUT.
Efficiency improvements for multi-stage power amplifiers are described. In one example, a power amplifier includes a driver amplifier formed on a first semiconductor die using a first semiconductor fabrication process, an output amplifier formed on a second semiconductor die using a second semiconductor fabrication process, and an inter-stage matching network formed between the driver amplifier and the output amplifier. The first semiconductor fabrication process is a lower voltage process and the second semiconductor fabrication process is a higher voltage process. The use of the two different fabrication processes leads to a number of advantages, including the simplification of the inter-stage matching network, increased radio frequency bandwidth, and improved line-up efficiency among the stages of the power amplifier.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
84.
TRANSISTOR AMPLIFIER WITH PCB ROUTING AND SURFACE MOUNTED TRANSISTOR DIE
A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.
RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.
H03F 3/187 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
Various aspects of Schottky diodes are described. The diodes are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter in some cases among other aspects. In one example, a Schottky diode includes a conduction layer, a first layer over the conduction layer, a second layer over the first layer, a first cathode and a second cathode spaced apart and in electrical contact with the conduction layer, and an anode over the second layer between the first cathode and the second cathode. The first cathode and the second cathode can be electrically connected to each other as a cathode of the Schottky diode.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H02M 7/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continuTransformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif
A transistor die includes a transistor including a control terminal, an output terminal, and a first partial matching circuit. The first partial matching circuit is connected to at least one of the control terminal of the transistor and the output terminal of the transistor, and is configured to tune an input impedance of the transistor die. A packaged device is also provided.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 1/56 - Modifications des impédances d'entrée ou de sortie, non prévues ailleurs
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
88.
STACKED RF CIRCUIT TOPOLOGY USING TRANSISTOR DIE WITH THROUGH SILICON CARBIDE VIAS ON GATE AND/OR DRAIN
A radio frequency (RF) power amplifier device package includes a substrate and a first die attached to the substrate at a bottom surface of the first die. The first die includes top gate or drain contacts on a top surface of the first die opposite the bottom surface. At least one of the top gate or drain contacts is electrically connected to a respective bottom gate or drain contact on the bottom surface of the first die by a respective conductive via structure. An integrated interconnect structure, which is on the first die opposite the substrate, includes a first contact pad on the top gate contact or the top drain contact of the first die, and at least one second contact pad connected to a package lead, a contact of a second die, impedance matching circuitry, and/or harmonic termination circuitry.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
H03F 3/193 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs comportant des dispositifs à effet de champ
H03F 3/195 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
H03F 3/213 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs dans des circuits intégrés
89.
ARRAYED WAVEGUIDE GRATINGS WITH STABILIZED PERFORMANCE UNDER VARYING PARAMETERS
An arrayed waveguide grating device includes an input coupler configured to receive a light signal and split the light signal into a plurality of output light signals. The device also includes a plurality of waveguides optically connected to the input coupler, each waveguide having a plurality of waveguide portions having respective sensitivities to variance in one or more parameters associated with operating of the optical arrayed grating device. Lengths of the respective portions are determined such that each waveguide applies a respective phase shift to the output light signal that propagates through the waveguide and the plurality of waveguides have at least substantially same change in phase shift with respective changes in the one or more parameters associated with operation of the device. An output coupler is optically connected to the plurality of waveguides to map respective light signals output from the plurality of waveguides to respective focal positions.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
90.
HIGH ELECTRON MOBILITY TRANSISTORS HAVING IMPROVED PASSIVATION STRUCTURES AND REDUCES DRAIN CURRENT DRIFT, AS WELL AS METHODS OF FABRICATING SUCH DEVICES
A high electron mobility transistor comprises a semiconductor layer structure that includes a channel layer (230) and a barrier layer (240) and source (250) and drain (252) contacts on the semiconductor layer structure. A gate contact (254) and a multi-layer passivation structure (262, 264, 266) are provided on the semiconductor layer structure between the gate contact (254) and the drain contact (252). The multi-layer passivation structure comprises at least first (262) and second (264) silicon nitride layers that have different material compositions. A spacer passivation layer (270) is provided at least between the gate contact (254) and the multi-layer passivation structure (262, 264, 266) on sidewalls of the first (262) and second (264) silicon nitride layers. A material composition of the spacer passivation layer (270) is different than a material composition of at least one of the layers of the multi-layer passivation structure (262, 264, 266). For example, the spacer passivation layer (270) may be a silicon nitride layer having a higher silicon content than the layers in the multi-layer passivation structure (262, 264, 266).
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/338 - Transistors à effet de champ à grille Schottky
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
91.
SEMICONDUCTOR STRUCTURES AND FABRICATION USING SUBLIMATION
Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer. The method also includes subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer. The material properties of the cap layer, as compared to the barrier layer, can be relied upon to form the opening in the cap layer down to the top surface of the barrier layer using sublimation, with high selectivity. Sublimation will stop with higher precision and selectivity at the interface between the cap layer and the barrier layer, as compared to etching.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
Semiconductor structures and methods of fabricating semiconductor structures using sublimation are described. An example method includes forming an opening through a mask layer over a wafer. The wafer includes a substrate, a channel layer over the substrate, a barrier layer over the channel layer, and a cap layer over the barrier layer. The method also includes subliming away a region of the cap layer, within the opening in the mask layer, to form an opening in the cap layer down to a top surface of the barrier layer. The material properties of the cap layer, as compared to the barrier layer, can be relied upon to form the opening in the cap layer down to the top surface of the barrier layer using sublimation, with high selectivity. Sublimation will stop with higher precision and selectivity at the interface between the cap layer and the barrier layer, as compared to etching.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/302 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes pour changer leurs caractéristiques physiques de surface ou leur forme, p. ex. gravure, polissage, découpage
H01L 21/336 - Transistors à effet de champ à grille isolée
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 21/337 - Transistors à effet de champ à jonction PN
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
93.
SYMMETRICAL DOHERTY POWER AMPLIFIER HAVING IMPROVED EFFICIENCY
Apparatus and methods for an improved-efficiency Doherty amplifier are described. The Doherty amplifier may include a two-stage peaking amplifier that transitions from an “off” state to an “on” state later and more rapidly than a single-stage peaking amplifier used in a conventional Doherty amplifier. The improved Doherty amplifier may operate at higher gain values than a conventional Doherty amplifier, with no appreciable reduction in signal bandwidth.
H03F 1/02 - Modifications des amplificateurs pour augmenter leur rendement, p. ex. étages classe A à pente glissante, utilisation d'une oscillation auxiliaire
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
94.
SEMICONDUCTOR LASER HAVING IMPROVED FACET RELIABILITY
Described herein are examples of improved semiconductor lasers having improved facet reliability for operation at high power and high current without significant change in device performance. The semiconductor laser may include a first semiconductor layer, an active layer, a second semiconductor layer sequentially adjacent to each other and arranged on a substrate, and a contact layer. In one example, the improved semiconductor laser may have a conductive contact less than the length of the semiconductor laser cavity and/or a dielectric layer arranged on at least one of the end portions of the contact layer.
A multi-stage driver circuit has a transmission line coupled to an output of the multi-stage driver circuit. The transmission line has inductive elements and programmable capacitive elements selected to shape the transmitted data signal. The programmable capacitive elements have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit.
A multi-stage driver circuit (116) has a transmission line (119) coupled to an output of the multi-stage driver circuit (116). The transmission line (119) has inductive elements and programmable capacitive elements (130) selected to shape the transmitted data signal. The programmable capacitive elements (130) have a first capacitor with a first terminal coupled to a first power supply conductor, and a first transistor with a first conduction terminal coupled to a second terminal of the first capacitor, and a second conduction terminal coupled to a second power supply conductor. The programmable capacitive elements (130) have a register with a first output coupled to a control terminal of the first transistor. The programmable capacitive elements (130) are selected to shape the transmitted data signal by observing operational dynamics of the multi-stage driver circuit (116).
Aspects of temperature dependent stabilization and peaking control in amplifiers are described. An example amplifier includes a variable gain amplifier, a power amplifier, a variable compensation element coupled to the variable gain amplifier, and a controller that directs operation of the variable compensation element to adjust one or more operating characteristics of the amplifier. In one aspect, the variable compensation element comprises a variable impedance, and the controller varies the impedance across inputs of the variable gain amplifier based on temperature to stabilize the amplifier. In another aspect, the variable compensation element comprises a negative capacitance, and the controller varies a coupling of the negative capacitance across inputs of the variable gain amplifier based on temperature to linearize gain of the amplifier. The variable compensation element can include both a variable impedance and negative capacitance, and stability, peaking control, and linearity of the amplifier can be controlled.
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
98.
PARASITIC CHANNEL MITIGATION USING SILICON CARBIDE DIFFUSION BARRIER REGIONS
Semiconductor structures that inhibit the conductivity of parasitic channels are described. In one example, a semiconductor structure includes a substrate, a III-nitride material region over a top surface of the substrate, a first species implanted within at least one region of surface region of the substrate in a first pattern spatially defined across a lateral dimension of the substrate, and a second species implanted within at least one region of the III-nitride material region. The second species can be implanted in a second pattern spatially defined across the lateral dimension of the substrate. The surface region of the substrate includes a parasitic channel. The at least one region of the substrate in which the first species is implanted includes a low-conductivity parasitic channel or is free of the parasitic channel.
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/205 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV comprenant plusieurs composés dans différentes régions semi-conductrices
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.
A distributed driver for an optic signal generator comprising amplifier cells having an amplifier cell input configured to receive the input signal and amplifiers configured to amplify the received signal to create an amplified signal, and an amplifier cell output. The distributed driver also includes an input path connected to the amplifier cell input to receive the input signal and distribute the input signal to the two or more amplifier cells. The input path includes one or more buffers configured to introduce a delay into the input signal. An output path is provided and connects to the amplifier cell outputs of the two or more amplifier cells. The output path is configured to receive the amplified signal and the output path includes one or more inductors that incorporated with the parasitic capacitance from the two or more amplifier cells form the LC segments of an artificial transmission line.
