A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
2.
HIGH-ELECTRON-MOBILITY TRANSISTOR HAVING GROUP-III-NITRIDE CAPPING LAYER SEPARATED FROM CONTACT
Group-III-nitride high-electron-mobility transistors (HEMTs) are provided. A Group-III-nitride HEMT includes a substrate. The Group-III-nitride HEMT includes a barrier layer on the substrate. The Group-III-nitride HEMT includes a source contact and a drain contact that are on the barrier layer. Moreover, the Group-III-nitride HEMT includes a Group-III-nitride capping layer on the barrier layer and separated from the drain contact by a gap.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
3.
HIGH-ELECTRON-MOBILITY TRANSISTOR HAVING GROUP-III-NITRIDE CAPPING LAYER SEPARATED FROM CONTACT
Group-III-nitride high-electron-mobility transistors (HEMTs) are provided. A Group-III-nitride HEMT includes a substrate. The Group-III-nitride HEMT includes a barrier layer on the substrate. The Group-III-nitride HEMT includes a source contact and a drain contact that are on the barrier layer. Moreover, the Group-III-nitride HEMT includes a Group-III-nitride capping layer on the barrier layer and separated from the drain contact by a gap.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
4.
METHODS OF SELECTIVELY FORMING GROUP III NITRIDE SEMICONDUCTOR REGIONS ON EPITAXIALLY GROWN GROUP III NITRIDE SEMICONDUCTOR LAYER STRUCTURES AND RELATED SEMICONDUCTOR DEVICES
A method of forming a semiconductor device comprises forming an anti-nucleation mask that includes an opening on an upper surface of a Group III nitride semiconductor layer structure, forming a Group III nitride semiconductor region on a portion of the Group III nitride semiconductor layer structure that is exposed by the opening.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
5.
CAPACITOR HAVING IMPROVED QUALITY FACTOR AND/OR REDUCED PLATE RESISTANCE AND METHOD OF IMPLEMENTING THE SAME
A capacitor component includes at least one dielectric layer, at least one capacitor top metal, and at least one capacitor bottom metal. The at least one capacitor top metal, the at least one capacitor bottom metal, and the at least one dielectric layer being configured as a capacitor. The capacitor component further includes at least one metallic structure configured to improve a quality factor of the capacitor and/or reduce a plate resistance of the capacitor. The at least one metallic structure is arranged on the at least one capacitor top metal.
New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are described. An example integrated device package includes a power transistor formed on a first substrate, a metal-insulator-metal (MIM) capacitor network formed on a second substrate, bond wires electrically coupled between a bond pad of the second substrate and a gate contact of the power transistor, a metal-oxide-semiconductor (MOS) capacitor network formed on a third substrate, and bond wires electrically coupled between a bond pad of the third substrate and the gate contact of the power transistor. The MIM capacitor network can include a MIM capacitor, with a first metal layer of the MIM capacitor being electrically coupled to the bond pad of the second substrate and a second metal layer of the MIM capacitor being electrically coupled to a ground plane on a bottom side of the second substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
7.
METHOD AND APPARATUS FOR ELECTROMIGRATION REDUCTION
A semiconductor circuit configured to reduce electromigration. The circuit comprises a power rail and ground rail located on a first layer. A power finger and a ground finger are located on a second layer. Cells are located on the second layer, such that the one or more cells are electrically connected to a power finger and a ground finger. The circuit also includes one or more power vias electrically connecting the power rail to the power finger. The one or more power vias extend from the first layer to the second layer. One or more ground vias electrically connecting the ground rail to the ground finger, such that the one or more ground vias extend from the first layer to the second layer. The placement of the fingers on a different level than the rails establishing the fingers as non-contiguous sections thereby reducing electromigration and overcoming design analysis errors.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
8.
LAYOUT TECHNIQUES AND OPTIMIZATION FOR POWER TRANSISTORS
An example field effect transistor includes a gate manifold, a first source metal, a second source metal, a drain metal, and a shielding. The drain metal is positioned between the first source metal and the second source metal. The shielding is connected to the first source metal and the second source metal. The shielding includes a depressed region extending between an end of the drain metal and the gate manifold and first and second stepped regions, which are raised from a top surface of the substrate. The gate manifold can include a gate manifold body, a first angled gate tab, and a second angled gate tab. The first angled gate tab can extend through a recess defined by the first stepped region of the shielding, and the second angled gate tab can extend through a recess defined by the second stepped region of the shielding.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
9.
BIASING CIRCUIT WITH OFFSET CORRECTION AND HIGH-SPEED INPUT STAGE BREAKDOWN PROTECTION
Circuits, semiconductor devices, and systems are provided. An illustrative circuit includes a first blocking capacitor coupled to an input of an amplifier and a second blocking capacitor coupled to the input of the amplifier, where the first blocking capacitor and the second blocking capacitor provide at least some Direct Current (DC) blocking to the amplifier. The circuit further includes one or more transistors that operate as an emitter follower for the amplifier and a biasing circuit to provide bias control and offset compensation for the amplifier, where the biasing circuit further provides a breakdown protection for the one or more transistors.
Circuits, semiconductor devices, and systems are provided. An illustrative circuit includes a first blocking capacitor coupled to an input of an amplifier and a second blocking capacitor coupled to the input of the amplifier, where the first blocking capacitor and the second blocking capacitor provide at least some Direct Current (DC) blocking to the amplifier. The circuit further includes one or more transistors that operate as an emitter follower for the amplifier and a biasing circuit to provide bias control and offset compensation for the amplifier, where the biasing circuit further provides a breakdown protection for the one or more transistors.
A device package includes a plurality of leads comprising lead structures configured as part of a leadframe during manufacturing. The plurality of leads include attachment pads and a lead alignment construction comprising one or more of the attachment pads being implemented with a solder mask material configured to promote alignment of all of the plurality of leads attached to the leadframe during solder reflow.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
A semiconductor device architecture includes a silicon substrate having sidewalls that are passivated by encapsulating the sidewalls in dielectric materials having high electric field strength. Encapsulating all the sidewalls using high field strength dielectric materials eliminates electrical paths in air or vacuum and confines the electric fields in these high field strength materials, increasing the breakdown voltage relative to unencapsulated devices and allowing the device to withstand greater standoff voltages. In some cases, encapsulating the sidewalls in this manner can allow the device to withstand voltages of 500V or greater.
A harmonic termination circuit is integrated into an RF amplifier semiconductor structure. A MIMcap is formed on a grounded source finger of an RF transistor amplifier, and one or more bond wires connect the MIMcap to a gate or drain bond pad of the transistor. The bond wire has an inherent inductance, and together with the MIMcap forms a series LC resonant circuit connected in shunt configuration from the gate or drain bond pad to ground. The LC circuit is tuned to shunt the desired harmonic component to ground, such as by adjusting the length of the bond wire (e.g., by altering its height). Such adjustment can be made after fabrication of the integrated circuit die is complete, and can be changed without requiring re-fabrication. The harmonic termination circuit resides entirely within the amplifier area, and does not increase the size of the die.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
In various embodiments, the present disclosure includes a system for sending 50 gigabits per second (Gbps), 75 Gbps, and 100 Gbps at 50 gigabaud (GBaud) for passive optical networks (PON) downstream and upstream. The system allows for transmission of three data rates at a single baud-rate while only using 2-bits of information per sample. A motivation for sending three data rates at a single baud-rate is to allow for further granularity in the control of the data-rates for downstream and upstream traffic in a flexible PON system based on the link margin. For example, the system can use non-return-to-zero (NRZ) at 50 GBaud for 50 Gbps and can use four-level pulse-amplitude modulation (PAM-4) at 50 GBaud for 100 Gbps. In addition for 75 Gbps, a double square-8 (DSQ-8) constellation can be used at 50 GBaud.
e.g.e.g., by altering its height). Such adjustment can be made after fabrication of the integrated circuit die is complete, and can be changed without requiring re-fabrication. The harmonic termination circuit resides entirely within the amplifier area, and does not increase the size of the die.
H10D 84/87 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of PN-junction gate FETs
H10D 1/68 - Capacitors having no potential barriers
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 84/60 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of BJTs
16.
METHODS OF FORMING HIGH ELECTRON MOBILITY TRANSISTORS WITH CONTROLLED GATE LENGTH AND HIGH ELECTRON MOBILITY TRANSISTORS WITH CONTROLLED GATE LENGTH
A method of forming a transistor device includes providing an epi wafer including a substrate and one or more epitaxial layers, forming source (10) and drain (16) contacts on a surface of the epi wafer, and forming a surface dielectric layer (26) on the surface of the epi wafer. A first opening is formed in the surface dielectric layer. The opening has a first width and exposes a first region of the surface of the epi wafer. A mask layer is formed on the epi wafer. The mask layer has a second opening that is offset from the first opening. The second opening exposes a portion of the first region of the surface of the epi wafer and a portion of the surface dielectric layer adjacent the first region of the surface of the epi wafer. A gate contact (12) is formed in the second opening.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 21/338 - Field-effect transistors with a Schottky gate
H01L 21/336 - Field-effect transistors with an insulated gate
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Cost reduction of semiconductor transistors is achieved by reduction in the amount of expensive metal, such as gold, used to form metal contacts and conductive paths in integrated circuits. A semiconductor transistor structure is formed, and ohmic source and drain terminals formed thereon. A gate terminal is formed over an insulating layer in the active area between the source and drain terminals. A field plate is formed at least partially over the gate terminal. Interface layers are deposited over the source and drain terminals, using the field plate metal structure, such as in the same processing step as field plate deposition. Metal contacts are then deposited over the interface layers. The metal contacts are considerably thinner than required in the prior art to support high current densities. Because gold is often used in the metal contacts, their smaller size reduces costs by requiring less gold to achieve the same performance.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A power amplifier includes a substrate, first and second transistor amplifiers, and at least one matching circuit. Respective output terminals of the first and second transistor amplifiers are coupled to a combining node, and the matching circuit includes one or more passive electrical components coupled between one of the respective output terminals and the combining node. At least one of the first and second transistor amplifiers or the one or more passive electrical components is mounted on the substrate in a flip chip configuration. The matching circuit may include a shunt inductance that is coupled to the one of the respective drain terminals by a conductive bump. Related devices are also discussed.
Systems, circuits, and methods for amplifying signals are provided. An illustrative circuit may include an amplifier that amplifies an input signal received at an input node of the amplifier and provides an amplified version of the input signal as an output signal at an output node of the amplifier. The circuit may further include at least one Continuous-Time Linear Equalizer (CTLE) circuit component connected with the amplifier, the CTLE circuit component providing an ultra-wide dynamic peaking control range for the amplifier.
Systems, circuits, and methods for a cross-coupled differential transistor amplifier. The cross-coupled transistor amplifier can be used in a multi-section amplifier, such as a 6-section differential distributed amplifier. Each cross coupled transistor includes a first transistor and a second transistor, wherein a drain of the first transistor is connected via at least one capacitor and at least one resistor to a gate of the second transistor, and a drain of the second transistor is connected via at least one additional capacitor and at least one additional resistor to a gate of the first transistor.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
Microstrip technology boards including microstrip traces matched over a range of different impedances are described. The microstrip boards include impedance-offset openings in ground planes under certain microstrip traces. The openings result in different effective dielectric constants and higher impedances for microstrip traces aligned with the openings, as compared to microstrip traces aligned over metal ground planes. The microstrip boards can also be mounted to conductive heatsinks. The conductive heatsinks act as ground planes for the microstrip traces aligned with the impedance-offset ground plane openings. The conductive heatsinks can include depressions co-located with the ground plane openings. Impedances of microstrip traces aligned with the ground plane openings are thus a function of the dielectric constant of the central core of the boards, the thickness of the central core, and the thickness of the air gap provided by the heatsink depressions.
Systems, circuits, and methods for amplifying signals are provided. An illustrative amplifier circuit may include an amplifier that amplifies an input signal received at an input node of the amplifier and provides an amplified version of the input signal as an output signal at an output node of the amplifier, a feedback loop connected between the input node of the amplifier and the output node of the amplifier, and a synchronized gain tracking sub-circuit provided in the feedback loop, where the synchronized gain tracking sub-circuit synchronously controls both a feedback resistance and forward gain of the amplifier circuit.
Broadband absorptive termination diode switches, and various embodiments and aspects thereof, are described. An example diode switch includes a common port, a first port, and a second port, a first switch arm between the first port and the common port, and a second switch arm between the second port and the common port. The first switch arm includes a first node and a second node each electrically coupled between and electrically separated from the first port and the common port. The first switch arm also includes a shunt diode electrically coupled between the first node and ground, a termination leg electrically coupled between the second node and ground, and a series diode electrically coupled between the first node and the second node. The use of the series diode between the first node and the second node results in broader bandwidth of operation in absorptive switches as compared to other designs.
H03K 17/76 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 17/10 - Modifications for increasing the maximum permissible switched voltage
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
24.
INTEGRATED CIRCUIT AC COUPLING DESIGN WITH ADJUSTED-RATIO AND HIGH IMPEDANCE EMITTER FOLLOWER STAGE
A system configured as part of an integrated circuit to block DC components from an amplifier comprising a matching network and an emitter follower circuit. The matching comprises an input configured to receive an input signal having a DC component. A voltage divider network comprises at least one resistor, and at least one capacitor. The network receives the signal and DC component and the voltage divider network blocks the DC component to generate a network output signal. The emitter follower (EF) circuit with EF devices configured to process the network output signal to generate an EF circuit output signal on an EF output. A biasing circuit generates a bias signal for the EF device. The bias signal has a value that is controlled by a bias control signal. Aias control signal generator compares the EF circuit output signal to a reference voltage, and generates the bias control signal.
A power amplifier die according to some embodiments includes a substrate, a transistor formed on the substrate, and an integrated passive device, IPD, formed on the substrate adjacent to the transistor. A wire bond electrically connects the transistor and the IPD on the substrate. A method of manufacturing a power amplifier die is also provided.
Voltages and currents associated with a driver circuit associated with a diode can be controlled during start up of the driver circuit. The driver circuit can comprise transistors that can satisfy a defined bandwidth specification in connection with driving an electrical signal for the diode. During start up, start-up controller component can control voltage levels applied to gates or backgates of transistors to maintain operating voltage levels associated with transistors at or below a defined voltage level as bias current level is incrementally increased to target bias current level, and/or start-up reference voltage level is incrementally increased to facilitate incrementally increasing an anode voltage level of an anode voltage associated with the diode. The driver circuit can supply the electrical signal to the diode based on the bias current, which can facilitate operation of the driver circuit.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
27.
MULTI-TIP WAVEGUIDE COUPLER WITH IMPROVED ALIGNMENT GUIDANCE
Disclosed are various embodiments for a multi-tip laser coupler with improved alignment guidance. A photonic integrated circuit (PIC) includes an input interface, an output interface, and a waveguide array. The waveguide array includes a first waveguide, a second waveguide, and a third waveguide. The first waveguide and the third waveguide are coupled to the input interface and are not coupled to the output interface. The second waveguide is coupled to the input interface and the output interface. Further, the second waveguide is positioned parallel to and between the first waveguide and a third waveguide. The second waveguide includes a tapered body such that an output end of the second waveguide coupled to the output interface is wider than an input end of the second waveguide coupled to the input interface.
Resonators and devices including resonators are described. An illustrative resonator includes a metal bottom electrode, a metal top electrode, and a piezoelectric layer positioned between the metal bottom electrode and the metal top electrode. At least one property of the metal bottom electrode may differ from at least one property of the metal top electrode such that the metal bottom electrode, the metal top electrode, and the piezoelectric layer provide a resonator target frequency as if the metal top electrode and metal bottom electrode were symmetrically configured, but provide a higher electromechanical coupling coefficient (kt2) as compared to a symmetrical configuration of the metal bottom electrode and the metal top electrode.
Monolithic devices including combinations of diodes, with electrical components fabricated and electrically connected among them, are described herein, along with process techniques for forming the devices. An example method of forming a monolithic semiconductor circuit includes forming a plurality of layers of semiconductor materials over a substrate, forming Schottky diode contacts for a Schottky diode on a first subset of the plurality of layers, and forming PIN diode contacts for a PIN diode on a second subset of the plurality of layers. The layers can include an etch stop layer, and the etch stop layer can be positioned between the first subset of the plurality of layers and the second subset of the plurality of layers. The method can also include etching the layers of semiconductor materials down to the etch stop layer after forming the Schottky diode contacts and before forming the PIN diode contacts.
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
Aspects of gate voltage level shifting circuits are described. An example power amplifier includes a depletion mode power transistor and a level shift circuit. The level shift circuit is configured to generate a level-shifted gate bias control signal for the depletion mode power transistor based on a gate bias control signal. Among other benefits, the level shift circuit facilitates the replacement of the power transistor in a power amplifier system, particularly in cases where the gate bias control levels generated by the amplifier system are insufficient to completely pinch-off the depletion mode power transistor.
Aspects of gate voltage level shifting circuits are described. An example power amplifier includes a depletion mode power transistor and a level shift circuit. The level shift circuit is configured to generate a level-shifted gate bias control signal for the depletion mode power transistor based on a gate bias control signal. Among other benefits, the level shift circuit facilitates the replacement of the power transistor in a power amplifier system, particularly in cases where the gate bias control levels generated by the amplifier system are insufficient to completely pinch-off the depletion mode power transistor.
A decoupling network for a radio frequency (RF) circuit includes a first decoupling capacitor coupled to a decoupling node of the RF circuit, a second decoupling capacitor coupled to the decoupling node of the RF circuit in parallel with the first decoupling capacitor, and an additional resistance in series with the first decoupling capacitor or the second decoupling capacitor.
A Doherty amplifier die according to some embodiments includes a substrate having a bandgap of above about 2 eV, a main amplifier, at least one peak amplifier, an input network connected to a first input of the main amplifier and to a second input of the at least one peak amplifier, an output combiner connected to a first output of the main amplifier and to a second output of the at least one peak amplifier; and an isolation structure arranged on the substrate between the input network and the output combiner. The isolation structure is configured to isolate the input network and the output combiner.
Athermal arrayed waveguide grating structure that may operate as an optical filter including an input Silicon (Si) slab waveguide, an output Si slab waveguide, the input Si slab waveguide and the output Si slab waveguide optically connected by an arrayed group of Silicon Nitride (SiN) grating waveguides. Temperature insensitivity of the structure is achieved by locating output waveguide(s) of the Si output slab waveguide at/within a 10-degree angle offset from the center line of the output Si slab waveguide.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A three-way Doherty amplifier according to some embodiments includes a first ratio of a gate width of a main amplifier to a first gate width of a first peak amplifier and a second ratio of the gate width of the main amplifier to a second gate width of a second peak amplifier, respectively, are configured to provide a substantially constant load on the main amplifier.
A configurable optical driver circuit includes an adjustable current source circuit configurable to drive one of a variety of different types of electrical to optical devices, an adjustable back-termination resistance circuit configurable to provide a back-termination resistance to one of a variety of different electrical to optical devices, and a programmable memory configured to provide configuration information to the adjustable current source circuit and to the adjustable back-termination resistance circuit to configure the adjustable current source circuit and the adjustable back-termination resistance circuit for operation with the one of a variety of different electrical to optical devices.
A package including an IPD according to some embodiments includes a circuit board; and a flip chip (FC) IPD die including a substrate material and at least one capacitor or inductor, The FC IPD die is mounted so that the at least one capacitor or inductor face an upper surface of the circuit board. The package further includes a top-side cooling structure thermally connected to a first planar surface of the FC IPD die. The first planar surface of the FC IPD die includes the substrate material. The package further includes at least one first mechanical support thermally connecting the circuit board to a second planar surface of the FC IPD die. The second planar surface of the FC IPD includes the at least one capacitor or inductor.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
38.
TRANSISTOR WITH GATE LAYOUT, DEVICE IMPLEMENTING THE TRANSISTOR WITH OUTPUT PRE-MATCHING, AND PROCESS OF IMPLEMENTING THE SAME
A device may include at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die. Also, the device may include drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die. Furthermore, the device may include source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die. In addition, the device may include a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers. Moreover, the device may include where the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad.
A device may include at least one drain pad arranged at a first die side of the transistor die and/or at a second die side of the transistor die, the first die side and the second die side being opposed sides of the transistor die. Also, the device may include drain fingers configured to extend from the at least one drain pad longitudinally toward a central location of the transistor die. Furthermore, the device may include source fingers configured to extend from the at least one drain pad longitudinally toward the central location of the transistor die. In addition, the device may include a gate pad and a gate and the gate is configured to extend along implementations of the drain fingers and/or the source fingers. Moreover, the device may include where the gate pad is arranged on an axis at least semi-orthogonally to an axis of the at least one drain pad.
A metal-insulator-metal (MIM) capacitor component that includes a substrate, where the metal-insulator-metal (MIM) capacitor component is configured to form a first capacitor with a top metal and a first bottom metal having a dielectric layer therebetween; and where the metal-insulator-metal (MIM) capacitor component is configured to form a second capacitor with the top metal and a second bottom metal having the dielectric layer therebetween. Additionally, the top metal, the dielectric layer, the first bottom metal, and the second bottom metal are arranged on the substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
Systems, circuits, and methods for mixing signals are provided. An illustrative circuit may include mixer circuitry including multiple inputs and at least one output, where the multiple inputs are connected across a local oscillator. The circuit may further include a terminal Radio Frequency (RF) output circuitry that is isolated from the local oscillator, where the at least one output of the mixer circuitry is directly connected to an input of the terminal RF output circuitry. The circuit may further include terminal Intermediate Frequency (IF) output circuitry that is isolated from the local oscillator, where the at least one output of the mixer circuitry is directly connected to an input of the terminal IF output circuitry.
H03D 7/12 - Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
H03H 7/06 - Frequency selective two-port networks including resistors
Offset calibration for signal rms measurement is provided. A method includes determining a first offset calibration of a first differential pair of a circuit. The first differential pair comprises a first transistor and a second transistor. The method also includes determining a second offset calibration of a second differential pair of the circuit. The second differential pair comprises a third transistor and a fourth transistor. Further, the method includes, based on the first offset calibration and the second offset calibration, determining a third offset calibration of a common mode.
Adjustments to supply voltage level associated with an amplifier can be controlled based on a state associated with an automatic gain control (AGC) component associated with the amplifier. The AGC component can determine the AGC state based on an output signal associated with the amplifier component. Supply voltage controller component (SVCC) of an amplifier regulator can control a supply voltage level of a supply voltage supplied to the amplifier component by the amplifier regulator based on a state value indicative of the AGC state and received from AGC component, and a threshold supply voltage level associated with a threshold state value. If the state value does not satisfy threshold state value, SVCC adjusts or maintains supply voltage at the threshold supply voltage level. If the state value satisfies threshold state value, SVCC adjusts or maintains supply voltage at a desired supply voltage level that corresponds to the AGC state.
Aspects of an amplifier with bias stabilization are described. In one example, an amplifier includes an output amplifier stage having an input terminal, a biasing leg having a biasing node coupled to the input terminal, and a bias feedback network coupled between the input terminal of the output amplifier stage and the biasing leg. The bias feedback network can include a difference amplifier, a bypass stage, and a reference voltage generator in one example. The difference amplifier can generate a bias control signal based on a difference between a bias voltage at a base terminal of the output amplifier stage and a voltage reference generated by the reference voltage generator. The bias feedback network generates the bias control signal and controls the bias voltage based on feedback, to keep the bias voltage and bias current constant over process, temperature, gain and other variations for consistent performance.
Independent control loops for mitigating positive and negative mismatch in differential amplifiers are provided. A method includes comparing a first voltage measured at a positive side output of an emitter follower with a reference voltage, resulting in a first voltage difference. The method also includes comparing a second voltage measured at a negative-side output of the emitter follower with the reference voltage, resulting in a second voltage difference. In addition, the method includes independently controlling the positive side and the negative side of the differential amplifier based on the first voltage difference and the second voltage difference.
An angular deviation optical tracking and detector device for use in optical systems such as a FSO communication systems—among others. The angular deviation optical tracking and detector device includes position sensor elements that are configured to detect any misalignment of incoming/received light and an optical tunnel structure coupled with a detector array to determine the angular deviation. The optical tracking and detector device includes a position sensor having an optical aperture configured to allow a portion of incoming light to pass through the position sensor; a plurality of position receivers positioned adjacent to the optical aperture, the plurality of position receivers configured to sense portions of the incoming light; and an optical detector array configured to detect portions of the incoming light that passes through the position sensor aperture and optical tunnel. Angular deviation may be determined from diode array readout of illuminated individual diodes.
G01S 3/781 - Direction-finders for determining the direction from which infrasonic, sonic, ultrasonic, or electromagnetic waves, or particle emission, not having a directional significance, are being received using electromagnetic waves other than radio waves Details
An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.
A biasing circuit for biasing an output transistor in a radio frequency (RF) amplifier includes a first field-effect transistor (FET) monolithically integrated with the output transistor, the first FET being connected to the output transistor in a current mirror configuration, such that a gate-to-source voltage of the first FET is the same as a gate-to-source voltage of the output transistor, and a drain current in the first FET is matched to a drain current in the output transistor and scaled proportionally according to a size of the first FET relative to a size of the output transistor. The biasing circuit further includes a voltage divider integrated with the first FET and connected to a current source, the voltage divider being configured to generate a voltage that is substantially independent of process, voltage and/or temperature variations for controlling the drain current in the first FET.
A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.
An architecture for peripheral component interconnect express compliant signals over optical fiber is provided. A method includes, based on a first determination that an impedance level of a receiver device satisfies a defined impedance level, causing a driver to pulse at a first defined frequency and duty cycle level. Further, based on a second determination that a number of pulses received, at a transimpedance amplifier, at the first defined frequency and duty cycle level satisfy a defined number of pulses and at least one defined criterion, the method causes a second impedance level of the driver to match the defined impedance level and causes the driver to enter an electrical idle state. The method also includes facilitating, by a transmitter, transmission of data to the receiver device at a second defined frequency level, via an optical fiber link.
A versatile adaptive voltage scaling control circuit, related apparatus, and related method are provided. A method includes monitoring one or more parameters determined to be associated with performance of a device that is driven by a direct current-to-direct current (DC-DC) converter. The method also includes determining a voltage target based on the one or more parameters and comparing the voltage target to a power supply voltage. Further, the method includes selectively adjusting an output voltage of the DC-DC converter via a feedback loop based on a result of the comparing.
A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
53.
SEMICONDUCTOR DIE WITH GROUP III NITRIDE-BASED AMPLIFIER CIRCUITS
A number of semiconductor die with Group III nitride-based amplifier circuits are described. In one example, the semiconductor die includes a first Group III nitride-based transistor having a first output contact. The semiconductor die includes a second Group III nitride-based transistor having a second output contact. The semiconductor die includes an output combiner inductor on the semiconductor die. The output combiner inductor may be coupled to the first output contact and to the second output contact. The output combiner inductor may further be coupled to a radio frequency (RF) output interface for the semiconductor die.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
Adjustments to gain levels, associated with amplifiers, including partial adjustments to gain levels associated with certain amplifiers can be controlled and performed in accordance with an amplifier gain adjustment sequence. In response to determining that an overall gain level associated with a group of amplifiers, comprising first, second, and third amplifiers, is to be reduced, AGC component can determine whether a third gain level associated with the third amplifier is at a minimum. In response to determining that third gain level is at minimum, AGC component can determine which of a first gain level associated with the first amplifier and a second gain level associated with the second amplifier is to be partially reduced, in accordance with the amplifier gain adjustment sequence that, in part, specifies alternating between partial first gain level reductions associated with the first amplifier and partial second gain level reductions associated with the second amplifier.
A Doherty amplifier comprises a main amplifier and a peaking amplifier. The main amplifier and the peaking amplifier are electrically connected to a same input signal source. The main amplifier and the peaking amplifier comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier, the main amplifier and the peaking amplifier are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier and peaking amplifier, respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers are electrically connected to the input signal source.
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A Doherty amplifier circuit includes a main amplifier section and a peaking amplifier section, an output of the peaking amplifier section being connected to an output of the main amplifier section at a combining node in the Doherty amplifier circuit. The Doherty amplifier circuit further includes a direct current (DC) blocking capacitor connected between the combining node and an output of the Doherty amplifier circuit.
A thermally conductive interposer includes an interposer substrate having a first substrate surface and a second substrate surface. The first substrate surface being configured to be attached to a first device component. The second substrate surface being configured to be attached to a second device component. The interposer substrate being configured to support the second device component on the first device component and integrate the first device component and the second device component within a microelectronic device. Further, the interposer substrate is configured to transfer heat between the first device component and the second device component; and the interposer substrate is configured to be electrically nonconductive.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
A Doherty amplifier (10) comprises a main amplifier (18a) and a peaking amplifier (18b). The main amplifier (18a) and the peaking amplifier (18b) are electrically connected to a same input signal source. The main amplifier (18a) and the peaking amplifier (18b) comprise different epitaxial structures of a Group III nitride material. To form the Doherty amplifier (10), the main amplifier (18a) and the peaking amplifier (18b) are formed comprising Group III nitride transistors comprising different epitaxial structures from different epiwafers such that the Group III nitride transistors of the main and peaking amplifiers (18a, 18b) comprise different epitaxial structures. The wafers are diced to produce respective amplifier dies comprising the main amplifier (18a) and peaking amplifier (18b), respectively. The amplifier dies are mounted on a common heat sink, and the main and peaking amplifiers (18a, 18b) are electrically connected to the input signal source.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Various aspects of integrated amplifiers, layouts for the integrated amplifiers, and packaged arrangements of the amplifiers are described. An example integrated amplifier includes an amplifier cell and a stability capacitor. The amplifier cell includes a common source transistor and a common gate transistor in a cascode arrangement. The common gate transistor includes a plurality of contacts. The stability capacitor is coupled between an output for the integrated amplifier and a gate of the common gate transistor. The stability capacitor is formed among the plurality of contacts of the common gate transistor over the semiconductor die. In one example, the stability capacitor includes a plurality of stability capacitors distributed among the plurality of contacts of the common gate transistor. The stability capacitor can also be distributed along an interconnect feed finger that extends between the contacts of the common gate transistor.
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/195 - High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
60.
OPTIMAL EQUALIZATION PARTITIONING WITH A LINEAR RECEIVER SIGNAL PATH
An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.
An electrode structure for a device, such as a GaN or AlGaN device is described. An example electrode structure includes a substrate with a gallium nitride material layer, an insulating layer formed on the substrate, the insulating layer including an opening that exposes a surface region of the gallium nitride material layer through the opening, a barrier metal layer on the surface region of the gallium nitride material layer and on a region of the insulating layer, and a conducting metal layer on the barrier metal layer. In other aspects, the electrode structure can also include a cap metal layer on the conducting metal layer, and a cap etch photoresist layer over the cap metal layer. The cap metal layer, the conducting metal layer, and the barrier metal layer can be etched down to the insulating layer over an area outside a width of the cap etch photoresist layer.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
62.
PACKAGED DEVICE HAVING AN INTEGRATED PASSIVE DEVICE WITH WAFER LEVEL FORMED CONNECTION TO AT LEAST ONE SEMICONDUCTOR DEVICE AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
63.
PACKAGED DEVICE HAVING AN INTEGRATED PASSIVE DEVICE WITH WAFER LEVEL FORMED CONNECTION TO AT LEAST ONE SEMICONDUCTOR DEVICE AND PROCESSES FOR IMPLEMENTING THE SAME
A device includes at least one integrated passive device having at least one bond pad; at least one semiconductor device having at least one bond pad; and at least one connection structure arranged on the at least one integrated passive device. Additionally, the at least one connection structure includes a solder portion configured to form a solder connection to the at least one bond pad of the at least one semiconductor device.
A monolithic, vertical, planar semiconductor structure with a number diodes having different intrinsic regions is described. The diodes have intrinsic regions of different thicknesses as compared to each other. In one example, the semiconductor structure includes a P-type silicon substrate, an intrinsic layer formed on the P-type silicon substrate, and a dielectric layer formed on the intrinsic layer. A number of openings are formed in the dielectric layer. Multiple anodes are sequentially formed into the intrinsic layer through the openings formed in the dielectric layer. For example, a first N-type region is formed through a first one the openings to a first depth into the intrinsic layer, and a second N-type region is formed through a second one of the openings to a second depth into the intrinsic layer. Additional N-type regions can be formed to other depths.
A power amplifier, such as a radio-frequency (RF) Doherty power amplifier, for amplifying an input signal to an output signal is disclosed. The power amplifier includes a peaking amplifier circuit, where the peaking amplifier circuit is formed in gallium nitride materials on a silicon substrate. The power amplifier further includes a main amplifier circuit, where the main amplifier circuit is formed in gallium nitride materials on a silicon carbide substrate.
A shielded capacitor includes a first terminal; one or more first capacitor metals electrically connected to the first terminal; a second terminal; one or more second capacitor metals electrically connected to the second terminal. The shielded capacitor further includes a shielding structure. The shielding structure being configured to limit a variation of an RF characteristic due to a presence of a metallic structure.
A level shifter, configured to shift an input voltage swing from a first voltage range to a second voltage range, comprising a first stage and a switching stage, with circuitry configured in isolation wells. The first stage includes a first stage input receiving an input signal that swings between a first voltage value and a second voltage, a buffer configured to shift the input signal to vary between a third value and a fourth value, and a first stage output configured to present a first stage output signal. The switching stage comprises switching stage inputs, configured to receive the first stage output signal, switch drivers, and switching devices configured to, responsive to the driver output, generate a switching stage output signal that is a shifted version of the input signal. The switching stage output signal ranges between a fifth voltage value and a sixth voltage value.
A device that includes a metal submount; a first transistor die arranged on said metal submount; a second transistor die arranged on said metal submount; a set of primary interconnects; and a set of secondary interconnects. Additionally, the set of primary interconnects and the set of secondary interconnects are configured to provide RF signal coupling between the first transistor die and the second transistor die by electromagnetic coupling.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.
A number of different types of semiconductor material structures and wafers, including epiwafers, are described herein. The semiconductor material wafers are optimized in certain aspects to form transistor amplifiers for use with new modulation communications systems. A semiconductor material wafer includes a silicon carbide substrate and at least one III-nitride material layer over the silicon carbide substrate. The semiconductor material wafers can include layers consisting of semiconductor materials without dopants such as iron or carbon, formed over the silicon carbide substrate.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
A technique for marking semiconductor devices with an identifiable mark or alphanumeric text yields a high-contrast, easily distinguishable mark on an electrical terminal of the device without impacting the device's breakdown voltage capability and without compromising the solderability and wire bondability of the terminal. This approach deposits the mark on the terminal as a patterned layer of palladium, which offers good contrast with the base metal of the terminal and maintains the solderability and bondability of the terminal.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
72.
BYPASSED GATE TRANSISTORS HAVING IMPROVED STABILITY
A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
73.
Packaged semiconductor devices with leadframes having tie bar with recessed cavity
A leadframe blank includes a first package blank, a second package blank and a tie bar between the first package blank and the second package blank. The tie bar includes a recessed cavity therein.
Aspects of coaxial to microstrip transitional housings are described. A method of forming a transitional housing includes forming a channel to a first depth into a housing block from a top surface of the housing block, forming a first annular opening to a second depth into the housing block from the top surface of the housing block at a first end of the channel, forming a second annular opening to the second depth into the housing block from the top surface of the housing block at a second end of the channel, inserting a first cylindrical plug into the first annular opening, and inserting a second cylindrical plug into the second annular opening. The second depth can be greater than the first depth in some cases.
Semiconductor structures including III-nitride materials are described herein, including semiconductor structures comprising III-nitride material regions (e.g., gallium nitride material regions). An example semiconductor structure includes a substrate, a III-nitride material region located over the substrate, a first-type electrode over the III-nitride material region, and a second-type electrode over the III-nitride material region. The first-type electrode defines a first electrode interfacial area with the III-nitride material region. The second-type electrode defines a second electrode interfacial area with the III-nitride material region. The first electrode interfacial area is less than 20 times the second electrode interfacial area in at least one example.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/15 - Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A balun is enhanced with design features that extend the operational bandwidth of the balun allowing the balun to operate at lower frequencies. The design enhancements also suppress resonances that otherwise cause sudden power drops at a resonance frequency while a load is connected between the balun's differential outputs.
H01P 5/10 - Coupling devices of the waveguide type for linking lines or devices of different kinds for coupling balanced lines or devices with unbalanced lines or devices
H03H 7/42 - Networks for transforming balanced signals into unbalanced signals and vice versa, e.g. baluns
77.
GATE METAL FORMATION ON GALLIUM NITRIDE OR ALUMINUM GALLIUM NITRIDE
Electrode structures and methods of manufacturing electrode structures for devices are described. An example electrode structure includes a gate metal formation including a nitride layer with an opening that exposes a surface region of a substrate, a gate metal layer on the surface region of the substrate, a barrier metal layer on the gate metal layer and on at least a portion of a step around the opening in the nitride layer, and a conductive metal layer on the barrier metal layer. The gate metal layer is on the surface region of the substrate and on at least another portion of the step around the opening in the nitride layer in one example. The gate metal layer includes first and second gate metal layers in one example, such as nickel and tungsten.
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
Amplifiers with temperature-adaptive gain and peaking gain control are described. In one example, a temperature-adaptive amplifier includes an amplifier, a temperature sense circuit, and a peaking control level shifter to bias shift the output of the amplifier and adjust a peaking gain of the amplifier based on the temperature control signal. The peaking control level shifter can adjust a peaking gain of the amplifier based on the temperature control signal. The temperature-adaptive control can help to compensate for peaking gain in amplifiers based on the operating temperature of the amplifier. The control can help to compensate for unwanted changes in amplifier peaking gain, over time, resulting in more consistent peaking gain over the full operating frequency range of amplifiers.
Extrinsic structures formed outside the active regions of active devices can influence aging characteristics and performance of the active devices. An example integrated device including such an extrinsic structure includes an active region of a semiconductor device in a plurality of layers of semiconductor materials over a substrate, an isolation region in at least one of the layers of semiconductor materials, the isolation region extending around the semiconductor device in an area outside of the active region, an insulating layer over at least a portion of the active region and over at least a portion of the isolation region, a via in the isolation region and outside the active region, the via extending through the insulating layer and down to a conduction layer among the layers of semiconductor materials in the isolation region, and an interconnect within the via and directly on the conduction layer in the isolation region.
H01L 21/76 - Making of isolation regions between components
H01L 21/765 - Making of isolation regions between components by field-effect
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A distributed amplifier system comprising an impedance matching network configured to match an input impedance to an output impedance of the signal source, and a DC block configured to block DC components in the input signal. A variable gain amplifier adjusts the gain applied to the input signal based on a gain control signal to generate a gain adjusted signal. An emitter follower circuit receives and processes the gain adjusted signal to introduce gain peaking to create a modified signal. A distributed amplifier receives and amplifies the modified signal from the emitter follower circuit, to create an amplified signal. The distributed amplifier includes a termination network and one or more impedance matching elements configured for gain shaping the amplified signal. The gain peaking introduced by the emitter follower circuit is controlled by a variable current source. The distributed amplifier may be an open collector distributed amplifier.
A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/053 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
85.
INTEGRATED PASSIVE DEVICES (IPD) HAVING A BASEBAND DAMPING RESISTOR FOR RADIOFREQUENCY POWER DEVICES AND DEVICES AND PROCESSES IMPLEMENTING THE SAME
A transistor device includes a metal submount; a transistor die arranged on said metal submount; an IPD component arranged on said metal submount, and the IPD component having a baseband damping resistor arranged on a thermally conductive dielectric substrate; and a second IPD component arranged on said metal submount, and the second IPD component may include a baseband decoupling capacitor arranged on a thermally conductive dielectric substrate.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
An enhanced electrical circuit can employ conductive fill components that can facilitate providing desirable resistive stabilization of the electrical circuit and other desirable circuit qualities without having to use a physical resistor. The electrical circuit can comprise a transmission line, which can be a microstrip line, that can have defined dimensions. The electrical circuit can comprise respective conductive fill components that can be in proximity to desired sides of the transmission line, wherein the respective conductive fill components can provide the desired resistive stabilization for the electrical circuit. The respective conductive fill components can be separated from, and not in contact with, each other based on respective gaps of a defined size(s) between respective adjacent conductive fill components. The respective conductive fill components can be across a single layer or multiple layers of conductive fill components.
A device according to some embodiments includes a first IPD die including a first SiC substrate. The first IPD die has a first surface and a second surface on the first SiC substrate opposite the first surface and includes a first contact and at least one first metal portion on the respective surfaces of the first SiC substrate. The device further includes a second IPD die including a second SiC substrate. The second IPD die has a third surface and a fourth surface on the second SiC substrate opposite the third surface and includes a second contact and at least one second metal portion on the respective surfaces of the second SiC substrate. The device further includes an electrical interconnection structure between one of the first and second surfaces of the first IPD die and one of the third and fourth surfaces of the second IPD die.
H01G 4/40 - Structural combinations of fixed capacitors with other electric elements not covered by this subclass, the structure mainly consisting of a capacitor, e.g. RC combinations
H01G 4/38 - Multiple capacitors, i.e. structural combinations of fixed capacitors
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
88.
Layout techniques and optimization for power transistors
An example field effect transistor includes a substrate, a first source metal over the substrate, a second source metal over the substrate, and a drain metal positioned between the first source metal and the second source metal over a channel of the field effect transistor. The drain metal includes a drain metal body having a notched region between the first source metal and the second source metal over the channel, and the notched region defines a first projecting portion and a second projecting portion of the drain metal body. In one aspect, the first projecting portion and the second projecting portion are positioned on respective sides of the notched region. The notched region is a triangular-shaped notched region in one example.
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
89.
Capacitor networks for harmonic control in power devices
New types, structures, and arrangements of capacitor networks for harmonic control and other purposes are described. An example capacitor network includes a bond pad and metal-insulator-metal (MIM) capacitors positioned over the top side of the substrate and along different sides of the bond pad. A first metal layer of each of the plurality of MIM capacitors is electrically coupled to the bond pad. A second metal layer of each of the plurality of MIM capacitors is electrically coupled to a ground plane on a bottom side of the substrate by a through-substrate via. The MIM capacitors can be arranged around the bond pad in the capacitor network for a tailored capacitance. A matching network in the integrated device can incorporate the capacitor network to reduce loss, provide better harmonic termination, and achieve better phase alignment for the power devices.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 1/68 - Capacitors having no potential barriers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
90.
RADIO FREQUENCY POWER AMPLIFIER IMPLEMENTING AN OFF MODE OUTPUT IMPEDANCE CONTROL AND A PROCESS OF IMPLEMENTING THE SAME
Semiconductor structures with reduced parasitic capacitance between interconnects and ground, for example, are described. An example method for making a semiconductor structure includes forming a trench in an interconnect area of a substrate between first and second device areas in the semiconductor structure, forming a low dielectric constant material region in the trench, forming a III-nitride material layer over the substrate and over the low dielectric constant material region in the trench, forming a first device in the III-nitride material layer in the first device area, forming a second device in the III-nitride material layer in the second device area, and forming an interconnect over the low dielectric constant material region, the interconnect comprising a continuous conductive metal interconnect from the first device area, over the low dielectric constant material region, and to the second device area.
H01L 21/8252 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using III-V technology
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
92.
High Frequency, High Temperature Transistor Devices
Transistor devices are provided. In one example, a transistor device includes a Group III nitride-based semiconductor structure. The transistor device has a non-degradation time of at least about 350 hours without degrading an output power of the transistor device by 1 dB or greater during a test condition. The test condition is associated with an operating frequency of the transistor device of about 31.5 GHz and a junction temperature of the transistor device of about 380° ° C.
Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.
H01S 5/0625 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes in multi-section lasers
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.
An optical module configured to electrically connect to a host. A linear equalizer performs equalization on a host equalized signal to create a module equalized signal, and a driver configured to present the module equalized signal from the linear equalizer to an optical conversion device at a magnitude suitable for the optical conversion device. An optical conversion device receives the module equalized signal from the driver, converts the module equalized signal to an optical signal, and transmit the optical signal over an optical channel. Also part of the optical module is an interface which communicates supplemental equalizer settings to the host. A memory stores the supplemental equalizer settings which reflect the optical modules effect on a signal passing through the optical module. A controller oversees communication of the supplemental equalizer settings to the host such that the host uses the supplemental equalizer settings to modify host equalizer settings.
H04B 10/077 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using a supervisory or additional signal
H04B 10/2543 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion due to fibre non-linearities, e.g. Kerr effect
Aspects of the present disclosure describe semiconductor DFB laser structures including both pumped and unpumped regions/sections wherein unpumped regions act as DBR reflector(s) while pumped regions act as DFB gratings. Semiconductor DFB laser devices according to aspects of the present disclosure include an active layer that extends the length of the device that is identical in both pumped and unpumped regions/sections.
An amplifier circuit has a variable gain amplifier including an input receiving an input signal and an open-conduction output, and an output stage including an input coupled to the open-conduction output of the variable gain amplifier and an output providing an output signal of the amplifier circuit. The variable gain amplifier has a first transistor and second transistor each having a control input receiving the input signal. A third transistor has a control terminal receiving a control signal and a first conduction terminal coupled to a first conduction terminal of the first transistor and a second conduction terminal being a first terminal of the open-conduction output. A fourth transistor has a control terminal receiving the control signal and a first conduction terminal coupled to a first conduction terminal of the second transistor and a second conduction terminal being a second terminal of the open-conduction output.
Devices and methods including hot via die attach jetting are described. An example integrated circuit device includes a semiconductor substrate, vias extending from a top to a bottom surface of the substrate, and a metal layer on the bottom surface of the substrate. The metal layer includes a metal pad extending around a via opening at the bottom surface of the substrate. The metal pad is electrically isolated from a remainder of the metal layer. The device also includes one or more jet-dispensed dots of a conductive die attach adhesive material on the metal pad. Electrical connections made through the metal pad and jet-dispensed dots may be preferred as compared to wire bonds or flip chip approaches, particularly for RF input and output signals. The use of jet-dispensed dots can facilitate high-volume and automated process techniques.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Power amplifiers including balanced coaxial baluns are described. One example includes first and second amplifiers coupled to a balanced pair of first and second microstrip lines on a circuit board. A balun is coupled between the microstrip lines at a balanced end and between a conductive trace and a ground plane of the circuit board at an unbalanced end of the balun. The balun includes a coaxial balun line and a surface mount balancing inductor. The coaxial line includes center and shield conductors. A first end of the center conductor is coupled to the first microstrip line and a first end of the shield conductor is coupled to the second microstrip line at the balanced end of the balun. The balancing inductor is coupled between the first microstrip line and the ground plane to maintain symmetry for the balanced pair of microstrip lines.
H01P 5/10 - Coupling devices of the waveguide type for linking lines or devices of different kinds for coupling balanced lines or devices with unbalanced lines or devices
A transistor device may include a semiconductor structure including a channel layer and a barrier layer on the channel layer, wherein the barrier layer has a higher bandgap than the channel layer; a source contact and a drain contact on the barrier layer; a gate contact on the semiconductor structure between the source contact and the drain contact, the gate contact including a drain-side wing portion extending from a central portion of the gate contact; and a field plate on the semiconductor structure between the gate contact and the drain contact and laterally offset from the gate contact by a distance. The field plate may include a first wing portion extending from a central portion of the field plate.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
