A semiconductor device includes a bit line extending in a first direction; a first gate extending in a second direction perpendicular to the first direction; an active region including a horizontal portion that contacts the bit line and a vertical portion that contacts the horizontal portion and extends in a third direction perpendicular to each of the first direction and the second direction; and a second gate overlapping with at least a portion of the horizontal portion while extending in the second direction, wherein the vertical portion of the active region is disposed between the first gate and the second gate.
Provided herein may be a semiconductor device and a method of manufacturing the same. A method of manufacturing a semiconductor device may include forming a stacked body in which first and second material layers are alternately stacked, the stacked body being formed in a chip area and a guard area, wherein the guard area is adjacent to the chip area, forming a plurality of first openings that pass through the stacked body of the guard area, the first openings being spaced apart from each other, forming a second opening from the plurality of first openings by expanding each of the plurality of first openings so that the plurality of first openings are coupled to each other, and forming a chip guard by filling the second opening with an insulating material.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
3.
IMAGE PROCESSOR AND IMAGE PROCESSING SYSTEM INCLUDING THE SAME
Disclosed is an image processor and an image processing system including the same. The image processor may include a first depth map generator configured to generate a first depth map having a first depth range corresponding to a first distance, based on first image values; a second depth map generator configured to generate a second depth map having a second depth range corresponding to a second distance longer than the first distance, based on the first image values and second image values; and a third depth map generator configured to combine the first depth map and the second depth map to generate a third depth map having a third depth range corresponding to the first and second distances.
A semiconductor device includes a lower structure; a first region including a plurality of first conductive layers vertically stacked in a first direction over the lower structure; a second region including a plurality of second conductive layers stacked in the first direction, the second conductive layers having the same horizontal length; and a plurality of contact structures coupled to the second conductive layers, respectively, wherein each of the second conductive layers includes a first horizontal conductive line; a second horizontal conductive line; and a pad between the first horizontal conductive line and the second horizontal conductive line.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
5.
MEMORY SYSTEM AND A METHOD FOR TRANSMITTING DATA THROUGH A COMMAND ADDRESS BUS
A memory system includes a memory controller and a memory apparatus. One of the memory controller and the memory apparatus is configured to transmit, through the command address bus, data to the other one of the memory controller and the memory apparatus.
A semiconductor device includes a first bit line extending in a first direction; a first transistor configured to include a first gate that extends in a second direction perpendicular to the first direction and a first active region; a second bit line extending in the first direction; and a second transistor configured to include a second active region connected to the second bit line and a second gate overlapping with the second active region. The first active region includes: a horizontal portion configured to contact the first bit line; and a vertical portion that contacts the horizontal portion and extends in a third direction perpendicular to each of the first direction and the second direction. The second gate contacts the vertical portion.
A semiconductor device includes: a sampling control circuit configured to select a coarse section from a plurality of coarse sections according to a first pattern signal during a sampling period, select a fine section from a plurality of fine sections according to a second pattern signal during the selected coarse section, and generate first to third sampling control signals having activated sections defined by the selected coarse section and the selected fine section; and a sampling circuit configured to sample an input address according to the first to third sampling control signals, respectively, to generate first to third sampling addresses, and schedule the first to third sampling addresses according to a sampling signal defining the sampling period to output an output address.
A semiconductor device includes a precharge pulse generation circuit configured to generate a first precharge pulse and a second precharge pulse, based on a column pulse generated when a column operation including a write operation and a read operation is performed. The semiconductor device also includes an input/output switching signal generation circuit configured to generate an input/output switching signal for connecting a first input/output line pair and a second input/output line pair to each other, based on the first precharge pulse and the second precharge pulse in a test mode.
A memory controller may include an external device interface configured to receive system configuration setting information from a first external device, a logical address feature map storage circuit configured to generate a logical address feature map by extracting, from the system configuration setting information, logical address feature data that defines a computational type for each logical address range specified by the first external device, a computational core configured to process write-requested data in a corresponding computational type, in response to a write request for a logical address included in the logical address feature map, and a memory interface configured to transmit the processed write data to a second external device.
A memory device includes a memory cell array including memory cells; a row control circuit coupled to the memory cells through word lines and configured to apply, to a selected word line during read operations, respective read voltages having different levels; a page buffer circuit coupled to the memory cells through bit lines and configured to adjust, according to a sensing control signal during each of the read operations, an amount of current flowing through the bit lines to sense the adjusted amount; and a read control circuit configured to adjust, during a second read operation subsequent to a first read operation among the read operations, a voltage level of the sensing control signal when a voltage level of a second read voltage corresponding to the second read operation is different from a level of a first read voltage corresponding to the first read operation.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes a gate stacked structure including insulating layers and conductive layers stacked alternately with each other, a first plug pattern and a second plug pattern extending in a vertical direction corresponding to a stacking direction of the gate stacked structure, first data storage layers disposed between the first plug pattern and the conductive layers and second data storage layers disposed between the second plug pattern and the conductive layers, an isolation structure extending in the vertical direction and separating the first plug pattern and the second plug pattern from each other, and insulating patterns disposed between the first data storage layers adjacent to each other in the vertical direction and the second data storage layers adjacent to each other in the vertical direction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
Disclosed is a memory device including a count circuit suitable for: generating a plurality of group selection signals corresponding to a plurality of address groups by counting, in units of the address groups, a number of times that each of a plurality of address signals is inputted to the memory device, wherein each of the address groups corresponds to one or more address signals from the plurality of address signals, and selecting a target group from the address groups, the target group corresponding to a greatest one of the numbers for the respective address groups, and a sampling circuit suitable for randomly sampling a target address signal from the target group based on the plurality of group selection signals and the plurality of address signals.
IUCF-HYU (Industry-University Cooperation Foundation Hanyang University) (République de Corée)
Inventeur(s)
Hyun, Jin Hoon
Lim, Jaemyung
Abrégé
A semiconductor device includes a driving circuit configured to generate a core voltage using a power supply voltage; a core circuit configured to perform a first operation and a second operation following the first operation, using the core voltage; and a boosting circuit configured to supply a boosting power to the core circuit, wherein the boosting circuit detects a voltage drop in the core voltage for a predetermined duration during the first operation, and supplies the boosting power, corresponding to the voltage drop, to the core circuit during the second operation.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
14.
STORAGE DEVICE CONTROLLING TARGET OPERATION BASED ON COLLECTED PERFORMANCE INFORMATION AND OPERATING METHOD THEREOF
A storage device may store performance information of the storage device in a target memory area including one or more of a plurality of memory blocks on determination that a set target condition is satisfied. And the storage device may control a target operation based on the stored performance information.
A semiconductor device includes a memory circuit including a plurality of mats and configured to output first read data having a data sequence identical to a data sequence of pattern data after the start of a read operation during a test operation mode operation and configured to output a fail address including error information of the first read data, and a data processing circuit configured to output the first read data as data and configured to generate fail location information by encoding the fail address.
A photovoltaic device and a wireless charging device including the same are disclosed. In an embodiment, a photovoltaic device includes a piezoelectric module configured to receive a pressure and to generate first electrical energy by converting energy from the received pressure into the first electrical energy, and a photovoltaic module configured to receive the first electrical energy generated from the received pressure by the piezoelectric module and configured to include a single photon avalanche diode (SPAD) configured to be powered by using the first electrical energy from the piezoelectric module to generate a current signal by responding to incident light incident upon the photovoltaic module.
H02S 10/10 - Centrales électriques PVCombinaisons de systèmes d’énergie PV avec d’autres systèmes pour la production d’énergie électrique comprenant une source supplémentaire d’énergie électrique, p. ex. systèmes hybrides diesel-PV
H02J 7/35 - Fonctionnement en parallèle, dans des réseaux, de batteries avec d'autres sources à courant continu, p. ex. batterie tampon avec des cellules sensibles à la lumière
H02J 50/00 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique
H02S 20/23 - Structures de support directement fixées sur un objet inamovible spécialement adaptées pour les bâtiments spécialement adaptées aux structures de toit
H10N 30/30 - Dispositifs piézo-électriques ou électrostrictifs à entrée mécanique et sortie électrique, p. ex. fonctionnant comme générateurs ou comme capteurs
H10N 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément piézo-électrique, électrostrictif ou magnétostrictif couvert par les groupes
17.
MEMORY INCLUDING ECC ENGINE AND OPERATION METHOD OF MEMORY
A memory may include a memory core; an error correction code (ECC) engine that reads data and an error correction code from the memory core and detects an error in the data using the data and the error correction code; and an error information generation circuit that generates error information to be output to an outside of the memory in response to an error detection result of the ECC engine, the error information including the number of errors being less than the number of errors included in the error detection result.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
An embodiment of the present disclosure may provide a read retry table optimized for a memory on the basis of a distribution of read voltages of word lines included in the corresponding memory, and by changing a method of setting a read retry table depending on the number of sample data, may provide an optimal read retry table even for a memory with insufficient sample data.
An embodiment of the disclosed technology reduces direct data transmission and reception between a plurality of host devices and enables data sharing by a data storage device, through management of allocation information and access mode information of memory regions included in the data storage device used by the plurality of host devices, thereby improving data processing performance by the plurality of host devices and the use efficiency of the data storage device.
Disclosed is an image sensing device including a pixel array including a unit pixel including sub-pixels. A first isolation region is disposed in an edge region of a sub-pixel, a second isolation region extends from the first isolation region to a central portion of the sub-pixel. The second isolation region includes: a first inner isolation region protruding in a first direction from one region of the first isolation region to the central portion of the sub-pixel, and a second inner isolation region formed on a same straight line as the first inner isolation region and protruding in a second direction from another region of the first isolation region to the central portion of the sub-pixel. A first grid is formed in an upper region located above a region between the first inner isolation region and the second inner isolation region, and the first grid includes an air layer.
A read retry table generator is coupled to a plurality of memory dies via a data path. The read retry table generator is configured to: collect data from a plurality of memory cells coupled to a plurality of word lines in the plurality of memory dies; determine a pass rate of collected data appertaining to a plurality of clusters; select a cluster candidate among the plurality of clusters, based on a pass rate of collected data; and cluster the collected data into the cluster candidate to generate a read retry table.
The present disclosure relates to a semiconductor device manufacturing method that includes: forming a first layer including a first substrate, a first plug formed in the first substrate, a photodiode, and a first wiring layer; forming a second layer including a second substrate, a second plug formed in the second substrate, and a second wiring layer; forming a third layer including a third substrate and a third wiring layer; bonding the first wiring layer of the first layer to the second wiring layer of the second layer; and bonding the second substrate of the second layer to the third wiring layer of the third layer.
An image sensor includes an image generator including pixels and configured to generate image data having pixel values corresponding to the pixels, and a focus manager configured to generate a first phase detection image and a second phase detection image based on pixel values for phase detection pixels, to determine a first target region of interest including a preset object within regions of interest in the first phase detection image based on a result of performing first pixel value sum operations for pixels included in regions of interest, determine a second target region of interest corresponding to the first target region of interest in the second phase detection image, and to perform an autofocus operation based on a result of performing second pixel value sum operations for pixels in first and second target regions of interest.
A selector includes a carbon material that includes carbon and a trivalent element that is chemically bond to cardon; and a dopant material implanted to the carbon material to form trap sites of conductive carriers based on a chemical bond between the carbon and the trivalent element in the carbon. A method for fabricating a selector includes forming a carbon layer that includes carbon; chemically reacting a trivalent element with the carbon in the carbon layer; and implanting a dopant through an ion implantation process.
A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.
A semiconductor device may include a first memory block including at least one first string that is connected between at least one first bit line and a first common source line, a second memory block including at least one second string that is connected between at least one second bit line and a second common source line, and a bit line connection circuit connected between the first bit line and the second bit line and configured to electrically connect or separate the first bit line and the second bit line.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/24 - Circuits de commande de lignes de bits
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A stack type semiconductor device includes a first semiconductor structure having a first integrated circuit layer and a first bonding layer and a second semiconductor structure having a second integrated circuit layer and a second bonding layer. The first integrated circuit layer has a first thermal endurance on one surface of the first integrated circuit layer. The first bonding layer is formed on the first integrated circuit layer. The second integrated circuit layer has a second thermal endurance, lower than the first thermal endurance, on one surface of the second integrated circuit layer. The second bonding layer is formed on the second integrated circuit layer and is hybrid-bonded to the first bonding layer. A third thermal endurance lower than the first thermal endurance. The third integrated circuit is arranged to face at least one of the first integrated circuit layer and the second integrated circuit layer.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
28.
COMPUTATIONAL STORAGE DEVICE AND DATA PROCESSING SYSTEM INCLUDING COMPUTATIONAL STORAGE DEVICE
A computational storage device includes a memory device configured to store therein a data unit group including a plurality of data units; and a controller configured to: calculate, based on a computational operation request, one or more logical addresses, to which a target data unit that is included in the data unit group has been allocated and is a target of a computational operation to be performed in response to the computational operation request, calculate a start logical address and a start offset of the target data unit based on information, the start logical address being included in the one or more logical addresses, read, from the memory device, data corresponding to the one or more logical addresses, and identify the target data unit in the read data.
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
A stack type semiconductor memory device may include a first structure and a second structure. The first structure may include a first substrate, a capacitor array and a first bonding layer. The first substrate may have an upper surface and a lower surface. The capacitor array may include a plurality of capacitors integrated on the upper surface of the first substrate. The first bonding layer may be formed on the capacitor array. The second structure may include a second substrate, an access array and a second bonding layer. The second substrate may have an upper surface and a lower surface. The access array may include a plurality of access transistors integrated on the upper surface of the second substrate. The second bonding layer may be formed on the lower surface of the second substrate. The second bonding layer may be hybrid-bonded to the first bonding layer.
A bit-flipping (BF) decoder and a decoding method based on a super node, which groups two or more component nodes corresponding to two or more bits in a codeword to generate a super node; and performs a decoding iteration on the super node. The decoding iteration includes: calculating a flipping energy for the super node based on a flipping energy for each of the component nodes and internal checks between the component nodes; and flipping at least one of the two or more bits in the super node upon a determination that the flipping energy for the super node exceeds a bit-flipping threshold.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
31.
MEMORY DEVICE FOR SUPPORTING EFFICIENT ERASE OPERATION AND OPERATING METHOD OF MEMORY DEVICE
A memory device includes a memory block having multiple string groups, and a controller configured to repeat one or more erase loops, each erase loop including a pulse application interval and a verification interval, configured to determine the multiple string groups as one of pass and fail string groups in a verification interval of a previous erase loop, and configured to apply a first voltage to a drain selection line corresponding to the fail string group from start timing to first timing, apply the first voltage to a drain selection line corresponding to the pass string group from the start timing to second timing earlier than the first timing, and apply a second voltage to the drain selection line from the second timing to the first timing in a pulse application interval of a subsequent erase loop subsequent to the previous erase loop.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A memory device, and a method of operating the memory device, includes a memory block including a cell plug extending between a first line and a second line, wherein a first select line, a first word line group, a first pass word line, a second word line group, and a second select line are arranged along the cell plug between the first line and the second line. The memory device also includes a peripheral circuit configured to apply an erase voltage to the first line or the second line, apply an assistance voltage to the first pass word line when the erase voltage is applied, and decrease a potential of the first pass word line while the erase voltage is maintained at a target level.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
Disclosed is a memory system including a memory device including a plurality of memory blocks, and a controller suitable for controlling the memory device to perform pre-read reclaim on pre-victim blocks of pre-read blocks among the plurality of memory blocks, the pre-victim blocks including uncorrectable errors, the pre-read blocks being blocks on which a pre-read operation has been performed.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/18 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire avec commande prioritaire
34.
SELECTOR, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD FOR FABRICATING SELECTOR AND SEMICONDUCTOR DEVICE
A selector includes a base material including carbon; and a dopant implanted into the base material. A method for fabricating a selector includes forming a carbon layer and implanting a dopant into the carbon layer. A semiconductor device includes a selector pattern including carbon as a base material and a dopant implanted through an ion implantation process; and a memory pattern disposed in an upper portion or a lower portion of the selector pattern.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
35.
ELECTRONIC SYSTEM RELATED TO DETECTING A RESULT OF A RUPTURE OPERATION
An electronic device includes a first counting circuit configured to generate a first counting signal based on a comparison signal that is generated by comparing a first row address after the start of a first bootup operation and first fuse data that are generated by a first rupture operation, a second counting circuit configured to generate a second counting signal based on the comparison signal that is generated by comparing a second row address after the start of a second bootup operation and second fuse data that are generated by a second rupture operation, and a repair comparison circuit configured to generate a repair detection signal for detecting whether the first and second rupture operations are additionally performed by comparing the first counting signal with the second counting signal and configured to output the repair detection signal.
A semiconductor device may include a first gate structure including stacked first gate lines; first contact plugs extending through the first gate structure and connected to the first gate lines, respectively; a second gate structure including stacked second gate lines; second contact plugs extending through the second gate structure and connected to the second gate lines, respectively; and a slit structure located between the first gate structure and the second gate structure and including a lower sidewall having a wave shape and an upper sidewall having a straight line shape.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
37.
SEMICONDUCTOR DEVICE FOR CONTROLLING OPERATING POWER SUPPLIED TO WORD LINE DRIVER
A semiconductor device may include a power control signal generation circuit configured to generate a power control signal that is activated when at least one of a power-up period and a test mode operation are performed and an operating power generation circuit configured to set operating power supplied to a word line driver as a high voltage in response to the power control signal.
A memory system and a method for decoding of one or more codewords. The system has a storage medium having therein a first decode, a first processor associated with the storage medium and configured to XOR results obtained from the first decoder when the one or more codewords in the storage medium are decoded, and a memory controller having therein a second decoder and a buffer, the memory controller configured to XOR results obtained from the second decoder. The second decoder decodes the one or more codewords after failure of the first decoder to decode the one or more codewords.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
39.
IMAGE RESTORING CIRCUIT USING NEURAL NETWORK AND IMAGE RESTORING METHOD USING THE CIRCUIT
Seoul National University R&DB Foundation (République de Corée)
Inventeur(s)
Oh, Youngjin
Park, Guyong
Chung, Haesoo
Cho, Nam Ik
Abrégé
An image restoring circuit includes a first restoring circuit including a first encoder and a first decoder, and configured to generate a first output image and first tensor data by restoring an input image; a second restoring circuit including a second encoder and a second decoder, and configured to restore the input image by using an output of the first encoder, an output of the first decoder, and the first tensor data to thereby generate a second output image; and a coupling circuit configured to generate second tensor data based on the output of the first encoder and the output of the first decoder and provide the second tensor data to the second encoder.
A semiconductor device includes a skip exit control circuit configured to select one of a plurality of skip signals as a selection skip signal, responsive to a test mode signal, and generate a skip exit signal, responsive to the selection skip signal, a mode control circuit configured to generate a mode signal to change the mode responsive to the skip exit signal until entering a preset final mode, and a command control circuit configured to generate internal commands for each mode, responsive to the mode signal.
An electronic system includes a controller configured to output a command, external row addresses, and external column addresses, receive a flag signal, and output the flag signal to a host. The electronic system also includes a semiconductor device configured to correct an error of internal data output from a memory cell selected based on the command, the external row addresses, and the external column addresses to output error-corrected internal data as data, and output the flag signal that is enabled when correcting the error in the internal data a set number of times.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
42.
SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a semiconductor pattern; an impurity region disposed at a side of the semiconductor pattern and having a lower surface that forms a flat surface with a lower surface of the semiconductor pattern; a gate structure disposed under the semiconductor pattern; and a contact plug disposed over the impurity region and electrically connected to the impurity region.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
43.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage; an interlayer insulating layer surrounding a sidewall of the selector pattern and having an opening disposed over the selector pattern; and an electrode disposed in the opening and having a width that is maximum at an uppermost portion of the opening, and wherein the uppermost portion of the opening has a rounded edge in a cross-sectional view.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
The present disclosure includes a memory device and a method of manufacturing the memory device. The memory device includes a channel layer passing through gate lines stacked spaced apart from each other, a channel junction extending on the channel layer, a capping layer surrounded by the channel layer, a void surrounded by the capping layer, a capping pattern surrounded by the channel junction and contacting an upper portion of the capping layer and the void, and a source line positioned on the gate lines and contacting the channel junction.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
45.
STORAGE DEVICE FOR MANAGING SUPER BLOCK AND METHOD OF OPERATING THE SAME
Provided herein is a semiconductor memory device having improved lifespan. The storage device may include a memory device including a plurality of super blocks, and a controller configured to control the memory device in response to each request among a plurality of requests from a host, wherein the controller is further configured to allocate a first super block to a first write request of a first type, and allocate a second super block different from the first super block to respond to a second write request of a second type, control the memory device to store in the first super block write data corresponding to the first write request, and when the second write request is received from the host before reallocation of the second super block after deallocation, control the memory device to store in the first super block write data corresponding to the second write request.
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a first semiconductor structure including a cell region and a peripheral circuit region, and including a cell capacitor disposed in the cell region and a first insulating layer disposed in the cell region and the peripheral circuit region to cover the cell capacitor; a second semiconductor structure including a cell transistor disposed over the first insulating layer in the cell region and a peripheral circuit transistor disposed over the first insulating layer in the peripheral circuit region; and a first conductor passing through the first insulating layer to electrically connect a first cell source/drain region of the cell transistor and an electrode of the cell capacitor.
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
47.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
In an embodiment, a semiconductor device includes: a variable resistance pattern configured to switch between different resistance states in response to an applied voltage or current; and a selector pattern disposed over the variable resistance pattern and having a lower surface in direct contact with an upper surface of the variable resistance pattern, the selector pattern structured to include an insulating material doped with dopants and to exhibit a threshold switching behavior to exhibit, and selectively switch between, an (1) electrical conducting state of providing an electrical conducting path in the selector pattern, and (2) an electrical non-conducting state of turning off the electrical conducting path in the selector pattern, wherein a sidewall of the variable resistance pattern and a sidewall of the selector pattern are aligned with each other.
An image signal processor may include a defect pixel determination unit configured to determine whether a target pixel is a defect pixel based on first comparison data that are a result of comparing pixel data of the target pixel included in a target kernel with pixel data of each of a plurality of pixels having attributes identical with attributes of the target pixel, a direction determination unit configured to determine a direction of the target kernel based on second comparison data that are a result of a comparison between pixel data of a pair of pixels that are disposed on a line in one direction and that have identical attributes, and a pixel interpolation unit configured to interpolate the pixel data of the target pixel by using the pixel data of each of a plurality of pixels that are disposed at locations corresponding to the direction of the target kernel.
A semiconductor memory device, and a method of manufacturing the same, includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs passing through the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs passing through the upper stack and being in contact with an upper portion of the plurality of cell plugs, and a separation pattern separating adjacent drain select plugs among the plurality of drain select plugs, wherein the separation pattern is in contact with a sidewall of each of the adjacent drain select plugs.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
50.
INITIAL CONTROL VOLTAGE GENERATING CIRCUIT FOR VOLTAGE-CONTROLLED OSCILLATOR AND PHASE-LOCKED LOOP CIRCUIT WITH THE INITIAL CONTROL VOLTAGE GENERATING CIRCUIT
An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
An image sensing device includes a substrate layer including a plurality of photoelectric conversion elements configured to generate photocharges, a plurality of color filters disposed over the substrate layer, a metal layer disposed between the color filters adjacent to each other, a buffer layer disposed over the metal layer, an air layer disposed over the buffer layer, and a capping layer formed to cover a stacked structure of the metal layer, the buffer layer, and the air layer. A region of the capping layer that covers the air layer is formed to have a larger thickness than the other regions of the capping layer that cover the metal layer and the buffer layer.
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
H10F 39/18 - Capteurs d’images à semi-conducteurs d’oxyde de métal complémentaire [CMOS]Capteurs d’images à matrice de photodiodes
52.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device includes a lower stack in which a plurality of first interlayer insulating layers and first conductive layers are alternately stacked, a plurality of cell plugs penetrating the lower stack in a vertical direction, an upper stack in which a plurality of second interlayer insulating layers and at least one second conductive layer are alternately stacked on the lower stack, a plurality of drain select plugs penetrating the upper stack and overlapping the plurality of cell plugs, respectively, and a separation pattern penetrating the upper stack and disposed between at least two adjacent drain select plugs among the plurality of drain select plugs, wherein the at least two adjacent drain select plugs each have a semi-cylindrical shape and remaining drain select plugs except for the at least two adjacent drain select plugs among the plurality of drain select plugs each have a cylindrical shape.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
53.
ELECTRONIC DEVICE INCLUDING STORAGE DEVICE AND CONTROLLER AND OPERATING METHOD THEREOF
A storage device includes: a nonvolatile storage area for storing a plurality of map segments including information of one or more map entries representing mapping information between a logical address provided by an external device and a physical address corresponding to the logical address; a volatile storage area for temporarily storing journal data including information that keeps track of changes to the mapping information to enable for updating the mapping information; and a controller in communication with the nonvolatile storage area and the 10 volatile storage area and configured to count a number of first map segments that store the updated mapping information, and updating the mapping information in the nonvolatile storage area according to a ratio of a number of logical addresses included in the journal data and the number of first map segments.
A pipeline system includes a first inverter latch configured to receive plural data entries, and plural second inverter latches coupled to each other in parallel for storing the plural data entries input from the first inverter latch in a distributive manner. Plural first switches are arranged between the first inverter latch and the plural second inverter latches, each first switch configured for controlling transmission of each of the plural data entries from the first inverter latch to one of the plural second inverter latches. Plural second switches are configured to output the plural data entries stored in the plural second inverter latches.
A semiconductor system includes a controller outputting a chip selection signal and a command address for performing a read operation and then outputting the chip selection signal and the command address for performing an ECS operation, and a semiconductor device including a plurality of memory cells and generating a latch row address and a latch column address by latching the command address when an error occurs in internal data that are output from a memory cell that is selected, among a plurality of memory cells, after the start of the read operation based on the chip selection signal and the command address, determining the priority of the ECS operation for the plurality of memory cells based on the latch row address and the latch column address, and storing the internal data in the same memory cell again by correcting the error of the internal data.
G11C 8/18 - Circuits de synchronisation ou d'horlogeGénération ou gestion de signaux de commande d'adresse, p. ex. pour des signaux d'échantillonnage d'adresse de ligne [RAS] ou d'échantillonnage d'adresse de colonne [CAS]
56.
SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING COMPLEMENTARY DELAY CIRCUITS
A semiconductor device includes a first delay circuit having a first delay amount that decreases according to a common bias, and configured to generate a first delay control signal based on the first delay amount; a second delay circuit having a second delay amount that increases according to the common bias, and configured to generate a second delay control signal based on the second delay amount; a signal generation circuit configured to generate a plurality of internal control signals in response to at least one of the first delay control signal and the second delay control signal; and an internal operation circuit configured to complementarily perform a first operation and a second operation within a target time in response to the internal control signals.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
57.
PHASE MIXER CIRCUIT, A PHASE MIXING METHOD, AND A CLOCK GENERATION CIRCUIT AND A SEMICONDUCTOR APPARATUS
A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
58.
STORAGE DEVICE FOR MANAGING MAP INFORMATION PROVIDED TO HOST AND METHOD OF OPERATING THE SAME
Provided herein may be a storage device capable of efficiently managing a host mapping table. The storage device may include a memory device and a memory controller configured to generate map information in which a physical address of the memory device is mapped to a logical address provided from a host, to provide a first map segment among a plurality of map segments included in the map information to the host, and to generate map change information when the first map segment is changed.
Provided herein may be a computing system having improved command processing speed. The computing system may include a host device configured to generate a command including information associated with operations to be requested, the information including a first information portion associated with a first operation of the operations and a second information portion associated with a second operation to be requested subsequent to the first operation, and output the command including the first information portion and the second information portion, and a storage device configured to store data and in communication with the host device, wherein the storage device is configured to: receive the command from the host device, perform the first operation in response to the command, and perform part of the second operation based on the second information portion in the command.
An image sensing device capable of detecting a distance to a target object according to a time-of-flight (TOF) method is disclosed. The image sensing device includes a plurality of light receiving elements each configured to generate a sensing voltage corresponding to a current pulse based on a photon reflected from a target object; a plurality of quenching circuits corresponding to the respective light receiving elements and each configured to output a pixel signal by controlling the sensing voltage from a corresponding light receiving element of the light receiving elements, and a readout circuit shared by the plurality of quenching circuits and configured to generate a readout signal by controlling a delay time of the pixel signal.
An image sensing device capable of generating a high dynamic range (HDR) image is disclosed. The image sensing device includes a pixel and a compensation circuit. The pixel configured to output to a sensing node, a sensing voltage corresponding to a voltage of a floating diffusion region, which is included therein and has first and second capacitances in respective first and second modes, the second capacitance being greater than the first capacitance. The compensation circuit controls, in a first section, an offset voltage level of the sensing node through a first path and boosts, in a second section, the sensing voltage through a second path.
H04N 25/42 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner en commutant entre différents modes de fonctionnement utilisant des résolutions ou des formats d'images différents, p. ex. entre un mode d'images fixes et un mode d'images vidéo ou entre un mode entrelacé et un mode non entrelacé
An image sensing device includes a semiconductor substrate, a photoelectric conversion region supported by the semiconductor substrate and configured to include first-type impurities and generate photocharges, a well region supported by the semiconductor substrate and configured to include second-type impurities and disposed over the photoelectric conversion region to contact the photoelectric conversion region within the semiconductor substrate, a floating diffusion region disposed in the well region and configured to store the photocharges, a transfer gate supported by the semiconductor substrate and configured to include a recess gate buried in the semiconductor substrate and configured to transmit the photocharges generated by the photoelectric conversion region to the floating diffusion region, and a first passivation layer supported by the semiconductor substrate and configured to include the second-type impurities, and covering side surfaces and a bottom surface of the recess gate within the semiconductor substrate.
Provided herein is a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a channel layer, and a source select line surrounding at least a part of the channel layer. A p-type impurity is locally doped in the part of the channel layer or a gate insulating layer includes a first member interposed between the channel layer and the source select line and aligned with a data storage layer.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
64.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a gate structure including gate lines and insulating layers alternately stacked, a channel structure extending through the gate structure and including a channel layer and a channel pad connected to the channel layer, a dummy gate structure including stacked dummy gate lines, a dummy channel structure extending through the dummy gate structure and including a dummy channel layer and a dummy channel pad connected to the dummy channel layer, an isolation insulating layer disposed between the gate structure and the dummy gate structure, and a dummy pad disposed on the isolation insulating layer between the gate structure and the dummy gate structure.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
65.
STORAGE DEVICE EXECUTING SUDDEN POWER-OFF RECOVERY OPERATION FOR TARGET ZONE AND METHOD FOR OPERATING THE SAME
A storage device may set a plurality of zones each of which includes one or more memory blocks among a plurality of memory blocks. When a sudden power-off is detected during a write operation for a target zone among the plurality of zones, the storage device may write dummy data to the target zone during a recovery operation for the sudden power-off. When writing data of a size matching that of the dummy data onto the target zone after the dummy data is written, the storage device may write the data to a target memory block in which is outside the target zone.
A receiver circuit is configured to generate a reception symbol from a multi-level signal. The receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. A first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. An averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.
H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
H03L 7/06 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase
67.
ELECTRONIC DEVICES INCLUDING INTERNAL VOLTAGE GENERATION CIRCUITS
An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
A method of manufacturing a semiconductor device may include forming a vertical stack comprising a plurality of recess target layers spaced apart from each other in a first direction over a lower structure; forming preliminary horizontal layers by recessing the recess target layers in a second direction perpendicular to the first direction; forming dielectric target layers on the preliminary horizontal layers; forming conductive target layers on the dielectric target layers; forming an inter-level dielectric layer by trimming the dielectric target layers in a third direction that intersects the second direction; forming horizontal layers by trimming the preliminary horizontal layers in the third direction; and forming trimmed target layers by trimming the conductive target layers in the third direction.
A semiconductor device includes a first chip having a first chip body and a first bonding layer which is disposed on the first chip body and includes a first bonding pad; and a second chip bonded on the first bonding layer, and having a second chip body and a second bonding layer which is disposed under the second chip body and includes a second bonding pad bonded to the first bonding pad, wherein a side surface of the first bonding layer and a side surface of the second chip are retracted inward of a side surface of the first chip body.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A receiver circuit includes a first buffer, a second buffer, and a sampling circuit. The first buffer receives a multi-level signal according to a first reference voltage to generate a first input signal. The second buffer receives the multi-level signal according to a second reference voltage to generate a second input signal. The sampling circuit samples each of the first input signal and the second input signal according to a first equalization method and a second equalization method, respectively, and outputs at least one of a first sampling result value according to the first equalization method and a second sampling result value according to the second equalization method according to a logic value of a previously input multi-level signal.
Embodiments of the present disclosure relate to a storage device and more particularly to a storage device which processes data for each zone in a device implemented with zone storage, and an operation method of the storage device. According to the embodiments of the present disclosure, remaining blocks generated in each zone are collected and set to an over provisioning area, so that a storage space can be efficiently used. According to the embodiments of the present disclosure, data is separated and written to different zones. Also, zone compression is performed on the data written to a specific zone, so that the storage space of the zone storage can be efficiently used.
A semiconductor device may include a first gate structure including stacked first selection lines, each first selection line including a first cell region and a first pad region adjacent in a first direction, a second gate structure including stacked second selection lines, each second selection line including a second cell region and a second pad region adjacent in the first direction, first contact plugs extending through the first pad region and respectively connected to the first selection lines, and second contact plugs extending through the second pad region and respectively connected to the second selection lines, and in a second direction crossing the first direction, the first pad region may have a width greater than that of the first cell region, and the second pad region may have a width greater than that of the first pad region.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
73.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
Disclosed is a method for manufacturing a semiconductor device, including: forming a first semiconductor structure comprising a logic transistor; forming a second semiconductor structure; bonding the first semiconductor structure to the second semiconductor structure, wherein forming the first semiconductor structure comprises: forming a first substrate; forming a first wiring layer comprising a plurality of first metal wirings and a plurality of first vias on the first substrate; forming a first bonding isolation layer on the first wiring layer, wherein forming the second semiconductor structure comprises: forming a second substrate; forming a second wiring layer comprising a plurality of second metal wirings and a plurality of second vias on the second substrate; forming a plurality of dummy plugs in the second wiring layer, forming a plurality of holes vertically penetrating the second substrate to a section in which the plurality of dummy plugs form, wherein the plurality of holes form after bonding the first semiconductor structure to the second semiconductor structure; and removing the dummy plugs.
Provided herein is a method of operating a host device. The method may include, a determining that read requests for data in a first file are successive, in response to the determination that read requests are successive, generating a first read command that instructs second data to be read ahead, the second data being successive to first data, determining a logical address corresponding to the first read command, providing to a storage device the first read command and the logical address, determining whether a read-ahead request for the first file has been completed, based on a first file pointer and a first offset corresponding to a storage area within the storage device in which the first file is stored, and executing a read-ahead request for a second file in response to the determination that the read-ahead request for the first file has been completed.
Provided herein are a memory device and a method of operating the memory device. The memory device may include a memory cell array including a plurality of memory cells coupled to a selected word line, a voltage generator configured to generate an operating voltage that is used for an internal operation, a row decoder configured to perform an under-drive operation including decreasing a voltage level of the selected word line and to apply the operating voltage to the selected word line, and control logic configured to control the row decoder to apply a ground voltage to the selected word line during the under-drive operation.
A semiconductor device may include an access line, a variable resistance layer, an electrode located between the access line and the variable resistance layer, and a barrier structure located between the access line and the electrode and including an amorphous barrier. The barrier structure may further include a diffusion barrier, and the amorphous barrier has a resistivity higher than that of the diffusion barrier.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
77.
ELECTRONIC DEVICE AND ELECTRONIC SYSTEM FOR GENERATING AN OPERATION VOLTAGE
An electronic device may include: a control pulse generation circuit configured to selectively generate one of a first control pulse and a second control pulse on the basis of a reference code during a test period; and a voltage control code generation circuit configured to perform an addition operation or subtraction operation on a logic bit set of a voltage control code to set the voltage level of an operation voltage on the basis of the first and second control pulses.
An image sensing device includes a pixel array including pixel units that include first pixel transistors located in different rows of the pixel array; first upper signal lines respectively connected to the first pixel transistors; a first test line commonly connected to the first upper signal lines; a first test pad connected to the first test line and configured to provide a first test signal to the first test line; and a first test transistor connected to the first test line and the first test pad and configured to enable or disable a test operation by selectively providing the first test signal to the first test line. During the test operation, the first test signal may be provided to the first pixel transistors located in different rows of the pixel array through the first test transistor, the first test line, and the first upper signal lines.
An imaging device is provided to include a physical unclonable function (PUF) pixel selection unit configured to identify a first pixel that is designated to generate PUF data and select a second pixel having a color identical to a color of the first pixel, a noise extraction unit coupled to the PUF pixel selection unit to receive information of the first pixel and the second pixel and configured to extract a first noise value of the first pixel and a second noise value of the second pixel, and a PUF data generation unit coupled to the noise extraction unit and configured to generate the PUF data based on the first noise value and the second noise value from the noise extraction unit.
H04N 25/67 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit appliqué au bruit à motif fixe, p. ex. non-uniformité de la réponse
A memory system or memory controller may calculate a first data size, which is the sum of sizes of data requested to be written by write requests from outside the memory system after a first reference time point, calculate a second data size, which is the sum of sizes of data updated by the write requests among data already stored in the memory device from a second reference time point, and control execution of garbage collection on data stored in the memory device based on the first data size and the second data size.
A three-dimensional memory device includes first and second isolation patterns extending in a first direction, and adjacent to each other in a second direction intersecting with the first direction; a stack disposed between the first isolation pattern and the second isolation pattern, and including a connection region including a plurality of electrode layers and a plurality of interlayer insulating layers alternately stacked in a vertical direction and an insulating region surrounded by the connection region; and a plurality of stairway-shaped recesses configured in the insulating region and the connecting region, and arranged in the first direction, wherein at least one of the plurality of stairway-shaped recesses comprises a first stairway structure connected to the first isolation pattern, a second stairway structure connected to the second isolation pattern, and a sidewall connecting the first stairway structure and the second stairway structure and disposed in the insulating region.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
82.
SEMICONDUCTOR SYSTEM PERFORMING ERROR CHECK SCRUB OPERATION
A semiconductor system includes a controller configured to output a command and address for performing an ECS operation after the start of entry into a power-down operation, receive data and output the data in response to correcting one or more errors occurring in the data, and output a command for performing a self-refresh operation when the ECS operation is terminated, and a semiconductor device configured to output, as the data, internal data stored in multiple memory cells after the start of a read operation of the ECS operation in response to receiving the command and address, receive the data having the one or more errors corrected after the start of a write operation of the ECS operation, store the data having the one or more errors corrected, and perform a self-refresh operation on the multiple memory cells after receiving the command when the ECS operation is terminated.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A system and a method for pattern search capable of enabling computation capability inside of a memory device. The memory system searches for a pattern data item in response to a pattern search command, and provide to the host the pattern data item associated with a particular pattern corresponding to the pattern search command. The memory device includes: a decoder configured to receive pattern data item from a plurality of pages, and decode the pattern data item; and a hash comparator configured to compare one or more host hash values with one or more memory hash values, and provide the controller with the decoded pattern data item according to the comparison results between the host hash values and the memory hash values.
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
A memory may include a memory core, a syndrome generation circuit configured to generate a syndrome by using data that are read from the memory core and an error correction code (ECC), a first decoder configured to generate first error correction information by using a first decoding table and the syndrome, a second decoder configured to generate second error correction information by using a second decoding table different from the first decoding table and the syndrome, and an error correction circuit configured to correct an error of the read data by using the first error correction information and the second error correction information.
A suspend parameter determination device may include a power monitoring circuit configured to monitor power consumption information of a storage device; a memory device configured to store an artificial intelligence model; and a control circuit configured to load the artificial intelligence model, input to the artificial intelligence model, performance information for the storage device and the power consumption information received from the power monitoring circuit, and transmit, to the storage device, a suspend parameter outputted by the artificial intelligence model.
A semiconductor device includes a plurality of semiconductor pillars having first and second sides facing each other in a first direction, and arranged in a second direction crossing the first direction; a plurality of insulating pillars having first and second sides facing each other in the first direction, and arranged alternately with the semiconductor pillars in the second direction; a back gate line formed on the first sides of the semiconductor pillars and the first sides of the insulating pillars, and extending in the second direction; and a front gate line formed on the second sides of the semiconductor pillars and the second sides of the insulating pillars, and extending in the second direction, wherein the semiconductor pillars respectively include protrusion portions that protrude more than the insulating pillars toward the front gate line in the first direction, and the front gate line surrounds a side of the protrusion portion.
An image sensing device for generating a high dynamic range (HDR) image is disclosed. The image sensing device includes a first pixel configured to generate a first pixel signal based on light received during a first exposure time, and a second pixel configured to share a floating diffusion region with the first pixel and to generate a second pixel signal based on light received during a second exposure time different from the first exposure time. When the floating diffusion region is reset based on a pixel reset signal in a first period, a reset signal is read out, the first pixel signal is read out in a second period, and the second pixel signal is read out in a third period. The first period, the second period, and the third period are included in one frame.
H04N 25/583 - Commande de la gamme dynamique impliquant plusieurs expositions acquises simultanément avec différents temps d'intégration
H04N 25/533 - Commande du temps d'intégration en utilisant des temps d'intégration différents pour les différentes régions du capteur
H04N 25/585 - Commande de la gamme dynamique impliquant plusieurs expositions acquises simultanément avec des pixels ayant des sensibilités différentes à l'intérieur du capteur, p. ex. des pixels rapides ou lents ou des pixels ayant des tailles différentes
H04N 25/77 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs
88.
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A memory device, and a method of manufacturing the same, includes a gate stack formed on a cell region and a pass transistor region, a plurality of cell plugs extending in a vertical direction in the gate stack of the cell region, a plurality of gate contact structures extending in the vertical direction by passing through the gate stack of the pass transistor region, and a plurality of pass transistors connected to the plurality of respective gate contact structures. Each of the plurality of pass transistors has a cylindrical shape structure.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
89.
MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A memory device, and a method of manufacturing the same, includes a discharge contact, a source pattern surrounding a periphery of the discharge contact and floated, and a source line surrounding a periphery of the source pattern and to which a source voltage is applied. The memory device also includes a separation pattern electrically isolating the source pattern and the source line, main support patterns positioned on the source pattern, sub support patterns positioned on the source line, and a contact positioned on the discharge contact.
H01L 23/60 - Protection contre les charges ou les décharges électrostatiques, p. ex. écrans Faraday
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
90.
MASK PATTERN AND METHOD OF FORMING A FINE PATTERN OF A SEMICONDUCTOR DEVICE USING THE SAME
A mask pattern may include a first spacer and a second spacer. The first spacer may be formed over a layer. The second spacer may be formed over the first spacer. The first spacer and the second spacer may define a mesh structure having a plurality of opened regions. The opened regions may be etched to form a hole array region and a plurality of dummy holes in the layer. The hole array region may include a plurality of holes. The dummy holes may be configured to surround the hole array.
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
A semiconductor memory device, and a method of manufacturing the same, includes a first stack and a second stack stacked on a semiconductor substrate in a cell region of the semiconductor memory device and a slit region of the semiconductor memory device adjacent to the cell region. The semiconductor memory device also includes a plurality of cell plugs at least partially passing through the second stack and the first stack of the cell region and extending in a vertical direction, a slit at least partially passing through the second stack and the first stack of the slit region, and a protective pattern disposed between the slit and dummy cell plugs adjacent to the slit among the plurality of cell plugs.
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
92.
SYSTEM-ON-CHIP DRIVEN BY CLOCK SIGNALS HAVING DIFFERENT FREQUENCIES
A system-on-chip includes plural components, configured to perform separate functions, separate calculations, or separate operations, and a bus interface configured to support data communication between the plural components according to a point-to-point interconnect protocol. At least one component of the plural components is operatively engaged with a memory device. The at least one component includes: plural memory interfaces configured to access the memory device in an n-way interleaving way, where n is a positive integer which is equal to or greater than 2; and at least one slave intellectual property (IP) core configured to distribute and transmit, to the plural memory interfaces, plural commands input through the bus interface.
The present technology relates to a semiconductor device. According to the present technology, a storage device capable of managing a bad block while maintaining interleaving performance may include a data storage device including a plurality of dies connected to a channel, and each of the dies includes a plurality of planes capable of a plane interleaving operation. Each of the planes includes a data storage device including a plurality of memory blocks, and a controller configured to control, when a bad block occurs in a target die among the plurality of dies, the data storage device to determine a replacement die corresponding to the target die among the dies based on replacement die recommendation information and control the data storage device to replace the bad block with a preliminary block included in the replacement die based on information on whether the plane interleaving operation is possible.
The present technology relates to a semiconductor device, a method of manufacturing the same, and a method of operating the same. The semiconductor device includes a gate stack including first interlayer insulating layers and word line stack layers alternately stacked, a vertical channel structure extending in a vertical direction in the gate stack, and memory structures interposed between the word line stack layers and the vertical channel structure, each of the word line stack layers includes an even conductive layer, a second interlayer insulating layer, and an odd conductive layer sequentially stacked, and a thickness of any one of the first interlayer insulating layers is greater than a thickness of any one of the second interlayer insulating layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
95.
PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE DEVICE AND SYSTEM INCLUDING THE SAME
Provided herein is a PCIe interface device. The PCIe interface device may include a NOP DLLP generator configured to generate a No Operation (NOP) data link layer packet (DLLP) including event information representing an event in response to the occurrence of the event and a transmitter configured to transmit the NOP DLLP to an external device through a link including a plurality of lanes.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 9/448 - Paradigmes d’exécution, p. ex. implémentation de paradigmes de programmation
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
A method of manufacturing a semiconductor device may include forming a stack with alternately stacked first material layers and second material layers, forming an opening passing through the stack, forming a memory layer in the opening, forming a slit passing through the stack and exposing the first material layers and the second material layers, and forming first barrier patterns, without removing the second material layers, by partially oxidizing the memory layer through the second material layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
97.
MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A method of manufacturing a semiconductor memory device includes alternately stacking sacrificial layers and interlayer insulating layers over a lower structure, forming a slit passing through the sacrificial layers and the interlayer insulating layers, removing the sacrificial layers through the slit through a wet etching process, and removing, through a dry etching process, a byproduct that is produced at ends of the interlayer insulating layers during the wet etching process.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
98.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
99.
ELECTRONIC DEVICE INCLUDING PROTON CONDUCTIVE LAYER AND RESISTANCE CHANGE CHANNEL LAYER CAPABLE OF RECEIVING HYDROGEN
An electronic device includes a substrate, a source electrode layer and a drain electrode layer that are disposed to be spaced apart from each other over the substrate, a channel layer disposed between the source electrode layer and the drain electrode layer over the substrate, a proton conductive layer disposed on the channel layer, and a gate electrode layer disposed on the proton conductive layer.
A data coding device may include a raw data storage configured to store raw data of which the total number of bits is 2N, a previous data storage configured to store previous data output before the raw data, a counter configured to count the number of reference data bits included in the raw data, and a data output circuit configured to invert and output the raw data according to a comparison result with the previous data when the number of reference data bits included in the raw data is N, and invert and output the raw data according to the number of reference data bits included in the raw data when the number of reference data bits included in the raw data is not N.
