A buffer chip includes: a chip select signal reception circuit configured to receive chip select signals transmitted from a memory controller; a command address reception circuit configured to receive command address signals transmitted from the memory controller; a chip select signal transmission circuit configured to transmit the chip select signals to a plurality of memory chips; a command address transmission circuit configured to transmit the command address signals to the plurality of memory chips; and a command address fixing circuit configured to fix levels of at least one of the command address signals transmitted by the command address transmission circuit when the chip select signals are deactivated for a predetermined time or more.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
2.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
Provided herein is a memory device and a method of operating the memory device. The memory device including a memory block connected to bit lines and a source line, a peripheral circuit configured to perform a program operation on the memory block, and a control circuit configured to control the peripheral circuit to perform the program operation on the memory block in response to a program command, control the peripheral circuit to suspend the program operation and perform a suspend operation in response to a suspend command, and control the peripheral circuit to resume the suspended program operation in response to a resume command, wherein the control circuit is configured to change verify levels corresponding to program states based on the suspend operation.
The image sensing device includes a semiconductor substrate including a first surface and a second surface facing or opposite to the first surface, photoelectric conversion regions supported by the semiconductor substrate and configured to generate photocharges in response to incident light received through the first surface, and a pixel isolation structure disposed between adjacent photoelectric conversion regions in the semiconductor substrate and configured to have a conductive material. The pixel isolation structure includes a first deep trench isolation (DTI) electrode extending from the second surface toward the first surface, and a second DTI electrode extending from the first surface toward the second surface and disposed apart from the first deep trench isolation (DTI) electrode to define a space for an air layer including air.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
5.
CAPACITOR, METHOD OF MANUFACTURING THE CAPACITOR, ELECTRONIC DEVICE INCLUDING THE CAPACITOR, AND METHOD OF MANUFACTURING THE ELECTRONIC DEVICE
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY (Republic of Korea)
Inventor
Lee, Jeongyeop
Park, Woo Young
Moon, Jiwon
Im, Kivin
Cho, Byung Jin
Kim, Seongho
Abstract
Disclosed are a device and method for an electronic device including a capacitor. The capacitor may include a first electrode; a second electrode disposed spaced apart from the first electrode; and a dielectric layer disposed between the first electrode and the second electrode, wherein the dielectric layer comprises: a first hafnium zirconium oxide layer region disposed in contact with or adjacent to the first electrode, and being doped with a first doping material, and a second hafnium zirconium oxide layer region disposed in contact with or adjacent to the second electrode, and being doped with a second doping material different from the first doping material; and an interlayer region disposed between the first and second hafnium zirconium oxide layer regions.
A semiconductor device includes a first electrode layer, a first resistance change layer disposed on the first electrode layer, a first filament control layer disposed on the first resistance change layer, a second resistance change layer disposed on the first filament control layer, a second filament control layer disposed on the second resistance change layer, a third resistance change layer disposed on the second filament control layer, an oxygen vacancy reservoir layer disposed on the third resistance change layer, and a second electrode layer disposed on the oxygen vacancy reservoir layer. A conductive filament corresponding to a resistance state of the semiconductor device is configured to be formed in a direction from the oxygen vacancy reservoir layer to the first electrode layer.
A semiconductor device includes a sense amplifier circuit including a plurality of sense amplifiers connected to a plurality of columns, wherein the plurality of sense amplifiers stores internal data output by the plurality of columns by amplifying the internal data, and generates an internal voltage by driving a segment line based on the internal data and a plurality of column signals after the start of an arithmetic operation, and an arithmetic circuit configured to generate weight data by performing a multiply-accumulate (MAC) operation based on a voltage level of the internal voltage and configured to output the weight data to the segment line.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
An embodiment of the disclosed technology reduces direct data transmission and reception between a plurality of host devices and enables data sharing by a data storage device, through management of allocation information and access mode information of memory regions included in the data storage device used by the plurality of host devices, thereby improving data processing performance by the plurality of host devices and the use efficiency of the data storage device.
When processing data corresponding to a command, a memory system processes the data by operating at least two banks included in a memory device. The operation of the banks according to the command is distributed, so the number of bits of data provided from a bank in which an error occurs is reduced, and the error may be corrected using a parity of a smaller number of bits.
Disclosed is an image sensor including a first tap pixel, a second tap pixel, and an overflow detection circuit suitable for detecting overflow of the first tap pixel based on a first tap pixel signal outputted from the first tap pixel and overflow of the second tap pixel based on a second tap pixel signal outputted from the second tap pixel, and forming a current path from an overflow current source to a ground voltage terminal when a voltage of the first tap pixel signal or a voltage of the second tap pixel signal drops below a predetermined voltage.
H04N 25/77 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
G01S 7/4913 - Circuits for detection, sampling, integration or read-out
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
Disclosed is a semiconductor device including a first pad, a pull-up resistor connected between the first pad and a supply terminal of a high voltage, a second pad connected to the first pad, a pull-down driver connected between the second pad and a supply terminal of a low voltage, and suitable for selectively driving the second pad with the low voltage based on a control signal corresponding to a predetermined signal, a first leakage prevention driver connected between an input terminal of the control signal and the supply terminal of the low voltage, and suitable for selectively driving the control signal with the low voltage based on a leakage prevention signal, and a controller connected to the second pad, and suitable for generating the leakage prevention signal based on a mode signal and a tie control signal.
A semiconductor device includes: a first semiconductor structure including a first semiconductor substrate, one or more first conductive patterns, a plurality of first conductive plugs, and a first bonding pad; a second semiconductor structure including a second semiconductor substrate, a plurality of second conductive patterns, one or more second conductive plugs, and a second bonding pad; and two through electrodes penetrating the second semiconductor substrate and respectively connected to two second conductive patterns positioned at opposite ends of the plurality of second conductive patterns, wherein the second bonding pad is bonded to the first bonding pad so that the plurality of second conductive patterns, the one or more second conductive plugs, the second bonding pad, the first bonding pad, the plurality of first conductive plugs, and the one or more first conductive patterns form a daisy chain.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A storage device is provided to include: a memory including a plurality of storage blocks, each storage block including pages including a valid page to which valid data is written and a snapshot page that stores data corresponding to or associated with data in the valid page; and a controller in communication with the memory and configured to i) generate a valid segment including valid address data indicating an address of the valid page and valid map information indicating a storage location of the valid segment, ii) manage the valid page based on the 10 valid segment and the valid map information, iii) generate a snapshot segment including snapshot address data indicating an address of the snapshot page and snapshot map information indicating a storage location of the snapshot segment, and iv) manage the snapshot page based on the snapshot segment and the snapshot map information.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
14.
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
A memory device includes cell strings coupled between bit lines and source lines, the cell strings including first select transistors, memory cells, and second select transistors; first select lines coupled to the first select transistors and spaced apart from each other in a direction in which the bit lines extend; a voltage generator configured to, during an erase operation, apply a first turn-on voltage to outer select lines among the first select lines, and apply a second turn-on voltage to inner select lines among the first select lines, the inner select lines being disposed between the outer select lines; and a control circuit configured to control, after the first turn-on voltage reaches a target level during the erase operation, the voltage generator so that the second turn-on voltage reaches a target level.
A storage device is provided to include: a memory including a plurality of storage blocks, each storage block including pages including a valid page to which valid data is written and a snapshot page that stores data corresponding to or associated with data in the valid page; and a controller in communication with the memory and configured to i) generate a valid segment including valid address data indicating an address of the valid page and valid map information indicating a storage location of the valid segment, ii) manage the valid page based on the valid segment and the valid map information, iii) generate a snapshot segment including snapshot address data indicating an address of the snapshot page and snapshot map information indicating a storage location of the snapshot segment, and iv) manage the snapshot page based on the snapshot segment and the snapshot map information.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
A memory may include a memory array configured to store write data therein and provide the write data stored therein as read data, a nonvolatile memory circuit configured to store repair information therein, a repair latch circuit configured to receive the repair information from the nonvolatile memory circuit and store the received repair information during a boot-up operation, and a repair circuit configured to repair the memory array using the stored repair information of the repair latch circuit, wherein the boot-up operation is performed during an initial operation period of the memory and is performed one or more times thereafter.
A memory may include a clock receiver configured to receive clocks; a first divider configured to divide the clocks to generate divided multi-phase clocks; a second divider configured to redivide the divided multi-phase clocks to generate redivided multi-phase clocks; and a command address reception circuit configured to receive a command and an address by using the divided multi-phase clocks in a first mode, and receive the command and the address by using the redivided multi-phase clocks in a second mode.
In an embodiment of the present disclosure, a data copy command of a host device may be processed without moving data in a memory by updating mapping information using a first mapping table between first logical block addresses and physical block addresses and a second mapping table between second logical block addresses and temporary logical block addresses corresponding to the first logical block addresses, whereby it is possible to improve the efficiency of processing the copy command.
POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION (Republic of Korea)
Inventor
Kim, Hyun Kyu
Kang, Tae Wook
Kim, Joon Rak
Park, Si Jeo
Choi, Dong Gu
Kim, Byung In
Park, Hyung Jun
Lee, Beom Hi
Han, Sun Jin
Abstract
Disclosed is a method for automating optimal placement and routing of transistors, in which in order to minimize a layout area, diversify a layout structure, and achieve routing optimization, electrical connection information of transistors constituting a circuit and parameters of the transistors are used to primarily place the transistors, heuristic-based pattern optimization and priority are determined, and then the transistors are placed and routed in an optimized state according to the above determination.
Provided herein may be a storage device for controlling a flush area and a method of operating the same. The storage device may include: a buffer memory device including a flush area configured to temporarily store data provided from a host; a memory device configured to store the data output from the flush area; and a memory controller configured to adjust a size of the flush area based on a number of internal operations related to a possibility of losing the data stored in the flush area.
A semiconductor device includes lower electrode; a selection element layer over the lower electrode; a middle electrode over the selection element layer; a carbon blocking element layer over the middle electrode; a variable resistance element layer over the carbon blocking element layer; and an upper electrode over the variable resistance element layer. The carbon blocking element layer includes a carbon absorption layer to absorb carbon atoms and a carbon barrier layer to block diffusion of the carbon atoms.
A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
23.
STORAGE DEVICE DISTRIBUTING BAD MEMORY UNITS IN SUPER MEMORY BLOCK AND OPERATING METHOD OF THE STORAGE DEVICE
When it is determined that a first super memory block among a plurality of super memory blocks satisfies an exchange condition, the storage device may exchange a first memory unit in the first super memory block with a second memory unit included in a second super memory block among the plurality of super memory blocks. In this case, the first memory unit is a bad memory unit and the second memory unit is a normal memory unit.
A three-dimensional semiconductor device includes a peripheral circuit device layer that includes a page buffer area, a pass transistor area adjacent to the page buffer layer, and a logic transistor area adjacent to the pass transistor area in the first direction, and a memory cell device layer that includes a cell area and a staircase area extending from the cell area. The peripheral circuit device layer includes transistors, peripheral circuit via plugs, and peripheral circuit interconnection layers on a substrate. The memory cell device layer includes word line stack including interlayer insulating layers and word lines alternately stacked, the word line stack including end portions stacked in a staircase in the staircase area; a bit line array including bit lines arranged in the cell area; and word line pillars electrically connected to the end portions of the word lines in the staircase area, respectively.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
25.
Method and System for In-NAND Checksum Calculating of LDPC Codes
SK hynix NAND Product Solutions Corp. (dba Solidigm) (USA)
Inventor
Asadi, Meysam
Zhang, Fan
Kwok, Zion
Abstract
A method and memory system for calculating checksums in a controller inside a memory device. This method and system select a subset matrix derived from an error correction code (ECC) parity-check matrix used in the controller and perform a partial checksum calculation using the subset matrix to estimate bit error rate (BER).
A method of operation of a memory device includes changing power from an off state to an on state, transmitting, to a controller, address information for memory cells having a shorter data retention time than other memory cells, reading data stored in memory cells corresponding the address information of the memory cells having the shorter data retention time and transmitting the data to the controller, and performing a refresh operation based on the results of an error correction operation of the controller.
In an embodiment of the present disclosure, operation frequency information on a memory region of a memory system is managed by the unit of a first size, and operation frequency information is managed by the unit of a second size smaller than the first size according to the operation frequency information by the unit of the first size. Therefore, by providing operation frequency information to a host device which is allocated and uses a memory region while efficiently using a storage space for operation frequency information, the management load of the host device may be reduced, and data processing performance by the host device may be improved.
Image sensing devices and methods of manufacturing image sensing devices are disclosed. In an embodiment, a method of manufacturing an image sensing device May include stacking a first structure that includes a first substrate, a first device layer, a first conductive pad, a first bonding layer, and a second structure that includes a second substrate, a second device layer, a second bonding layer by bonding the first bonding layer and the second bonding layer to each other to expose a back side of the first substrate, and etching the exposed back side of the first substrate by a partial thickness of a thickness of the first substrate to expose the first conductive pad in the first substrate.
A semiconductor design system and a method for designing a semiconductor device using the system include a design tool configured to: determine a target circuit block to designed; select a standard cell configured to perform a function of the target circuit block; determine a detailed configuration of the target circuit block according to a power characteristic and an input/output characteristic of the target circuit block; based on circuit block information including the detailed configuration of the target circuit block, a device type to which the target circuit block is applied, and an integration location for the target circuit block, select an alt-standard cell among a plurality of alt-standard cells associated with the selected standard cell, for which the alt-standard cell has circuit block information that most closely matches the circuit block information for the target circuit block; and lay out the target circuit block by loading the selected alt-standard cell.
A method for operating a LIDAR system includes dividing an entire valid measurement distance into a preset number of distance ranges, calculating a change value for laser positions applicable to the entire valid measurement distance, applying the change value to a reference value determining each of the distance ranges to reestablish each of the distance ranges, setting at least one region of interest for each of the reestablished distance ranges, and collecting depth data from the at least one region of interest.
A semiconductor device may include a substrate; an active region disposed over the substrate; a buried layer disposed between the substrate and the active region; an isolation structure surrounding a bottom surface and side surfaces of the active region and surrounding side surfaces of the buried layer; a gate trench formed in the active region; a gate dielectric layer formed on the gate trench; and a gate electrode disposed on the gate dielectric layer and partially filling the gate trench.
A semiconductor device includes an active region disposed in a substrate; a first node and a second node defined in the active region; and a buried electrode. The buried electrode includes a linear portion disposed between the first node and the second node to be through the active region, and an extended portion protruding from the linear portion to partially cover side walls of the second node.
Provided herein is a memory device. The memory device includes a memory block, an operation processor, and an address allocator. The memory block includes a plurality of string groups connected to a plurality of word lines. The operation processor is configured to set a program operation mode of the memory block to one of a single-level cell (SLC) mode and a multi-level cell (MLC) mode in response to a command received externally from the memory device. The address allocator is configured to allocate a row address of the memory block differently depending on the program operation mode.
An imaging device comprises a pixel including a photoelectric conversion device for generating pixel signals, a floating diffusion region, a first dual conversion gain (DCG) transistor for providing additional capacitance to the floating diffusion region, and a first DCG capacitor connected to the floating diffusion region through the first DCG transistor; and an analog-digital converter (ADC) for converting the pixel signals into image data, wherein the pixel includes a first metal layer including a first DCG gate electrode of the first DCG transistor and a first electrode of the first DCG capacitor, a second metal layer including a dual conversion line that supplies a first DCG gate signal to the first DCG gate electrode, and a second electrode overlapping the first electrode, a first insulating layer between the first DCG gate electrode and the dual conversion line, and a second insulating layer between the first electrode and the second electrode.
A memory system includes a memory device including a plurality of memory blocks constituting a plurality of super blocks in which a data entry to be stored is determined according to allocation information, and a controller configured to perform a bad block management operation when a memory block included in a first super block from among the plurality of super blocks is determined to be a bad block. For the bad block management operation, the controller is configured to change allocation information of the first super block based on a lifespan information of the first super block.
A memory system includes a memory device comprising plural memory dies, each memory die comprising plural memory blocks and including an active area and an inactive area and a controller configured to adjust sums of a bad block size and an inactive area size in the plural memory dies to be equal to each other based on a bad block occurring or found in the plural memory dies.
A storage device may include a memory and a controller. The memory includes M memory dies, each die including a plurality of memory blocks, each block including a plurality of memory cells, each cell storing K bits of data. The controller may receive M*K data units from a host, may calculate a first time taken to receive the M*K data units, and may determine a scheme of storing the M*K data units in the memory based on the first time.
A memory device includes a memory cell array including normal cell blocks and at least one error correction code (ECC) cell block, which include a plurality of rows; a scrub control circuit configured to perform an error check operation on each of the plurality of rows; and a write-back prevention circuit configured to store, based on local error signals for the normal cell blocks and the at least one ECC cell block during the error check operation, a severe address for a row in which a severe error occurs, and selectively perform a write-back operation on the row corresponding to the stored severe address during the error check operation or a read-modify-write (RMW) operation.
A semiconductor device includes a base chip configured to output a strobe signal and a control signal and to output a first update signal and a second update signal in response to receiving first and second core strobe signals, a first core chip configured to generate the first core strobe signal by delaying the strobe signal by a first delay amount while a pulse of the control signal is input, to output the first core strobe signal to the base chip, and to calibrate the first delay amount while the first update signal is enabled, and a second core chip configured to generate the second core strobe signal by delaying the strobe signal by a second delay amount when a pulse of the control signal is input, to output the second core strobe signal to the base chip, and to calibrate the second delay amount while the second update signal is enabled.
An imaging device is provided to include a pixel array including phase-difference detection pixels; a position determiner configured to determine a position of each unit pixel; a weight setting unit configured to set different weights for each position of each phase-difference detection pixel based on an output signal of the position determiner; a signal blending unit configured to generate phase images by adding the weight set by the weight setting unit to each phase-difference detection pixel; a parallax calculator configured to calculate a parallax in at least one direction from among a first direction from a center point of an optical axis in the phase images and a second direction from the center point of the optical axis in the phase images; and a focus position determiner configured to generate a driving signal for adjusting a position of a lens based on the parallax calculated by the parallax calculator.
Provided herein may be a controller, a memory system including the controller, and a method of operating the memory system. The controller may include a programmed capacity table including information on a capacity of data programmed to memory blocks included in a memory device, a block selector configured to compare a capacity of data stored in a buffer memory with a reference capacity, and select, based on a result of a comparison, one of memory blocks designated as a free status block and or an open status block, among memory blocks, and a command generator configured to output a command for programming the data to the selected memory block.
A memory device may include a memory cell array including a plurality of memory cells connected to word lines and bit lines, a peripheral circuit configured to perform a first program voltage apply operation of increasing threshold voltages of selected memory cells and a verify operation of verifying program states of the selected memory cells based on the increased threshold voltages, and a control logic configured to, after the verify operation has succeeded, control the peripheral circuit to determine a bit line voltage by which a bit line connected to the memory cell having succeeded in a verify operation is precharged, based on threshold voltages of memory cells connected to one or more adjacent word lines, and perform a second program voltage apply operation of increasing a threshold voltage of the memory cell having succeeded in the verify operation based on determined bit line voltage.
A method for fabricating a semiconductor device includes forming a vertical stack in which dielectric layers are alternately stacked with horizontal layer patterns, over a lower structure; forming cell isolation layers that contact side surfaces of the horizontal layer patterns and vertically extend in the vertical stack; forming a sacrificial structure that covers upper surfaces and lower surfaces of the horizontal layer patterns in the vertical stack; forming a hole-shape opening that vertically extends, by etching the sacrificial structure and the cell isolation layers; forming a double pocket layer on a sidewall of the hole-shape opening; forming storage openings, by recessing the horizontal layer patterns and the cell isolation layers using the double pocket layer as a barrier; and forming a data storage element in each of the storage openings.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A memory device and a method of operating the memory device are provided. The memory device includes memory cells located between a bit line and a source line, pass cells located between the memory cells, word lines coupled to the memory cells, pass word lines coupled to the pass cells, and a voltage generator configured to apply a read voltage to a selected word line among the word lines, a pass voltage to unselected word lines among the word lines, and a compensation voltage to the pass word lines during a read operation, wherein the voltage generator is configured to raise the compensation voltage more rapidly than the pass voltage.
A memory controller for efficiently managing power may include a memory interface, a power manager, and an Error Correction Code (ECC) engine. The memory interface may perform a data input/output operation of transmitting/receiving data to/from a memory device through an input/output line. The power manager may monitor a peak current period of the data input/output operation, and generate peak sensing information when the peak current period is sensed. The ECC engine may perform an error correction operation on the data while the data input/output operation is performed, and control a speed of the error correction operation in the peak current period in response to the peak sensing information.
According to embodiments of the present disclosure, a memory device may include a substrate, a plurality of landing pads on the substrate, a plurality of lower electrodes respectively disposed on the plurality of landing pads, a first insulating layer surrounding side surfaces of the plurality of landing pads, and a second insulating layer disposed on the first insulating layer, comprising a material different from a material forming the first insulating layer, and surrounding the side surfaces of the plurality of landing pads.
A semiconductor device includes a nano sheet including a first sheet region, a third sheet region, and a second sheet region extending horizontally between the first and third sheet regions, the first region having a curved profile; a first conductive line surrounding the second sheet region of the nano sheet; a second conductive line coupled to the first sheet region of the nano sheet; and a data storage element coupled to the third sheet region of the nano sheet.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
48.
BUFFER CHIP, AND SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP
A buffer chip includes a control signal transmission path that transmitting, to a memory chip, control signals transmitted from a memory controller; a data transmission path including a variable delay circuit having a delay value adjusted by a delay code and transmitting, to the memory controller, data transmitted from the memory chip; a ring oscillator generating a ring oscillator clock; a counter circuit configured to count the number of toggles of the ring oscillator clock while an external clock toggles a reference number of times; a reference value storage circuit configured to store a counting value of the counter circuit as a reference value; a current value storage circuit configured to store the counting value of the counter circuit as a current value in response to a comparison signal; and a code generation circuit configured to generate the delay code by comparing the reference value with the current value.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A semiconductor system may include a semiconductor apparatus; a controller configured to control the semiconductor apparatus through a command address bus and a data bus, and a baseboard management controller configured to control the semiconductor apparatus through a management bus. The semiconductor apparatus includes a plurality of memories each configured to store data under the control of the controller, configured to output data stored in the semiconductor apparatus, and configured to perform an on-die termination (ODT) setting operation based on an identifier (ID) that is assigned by the baseboard management controller.
A memory device includes a memory cell array and a regulator. The memory cell array includes a plurality of memory cells arranged in areas in which word lines and bit lines intersect with source lines, the word lines and the bit lines extending in a first direction and the source lines extending in the second direction. Memory cells along the first direction, among the plurality of memory cells, are electrically coupled to a same word line and a same bit line, memory cells along the second direction, among the plurality of memory cells, are electrically coupled to a same source line, and the bit lines are shunted at one or more shunt nodes. The regulator applies a bit line voltage to a common node at which the bit lines are electrically coupled in common.
A semiconductor device includes a memory circuit including a plurality of mats and a meta region and configured to block output of first internal data stored in the plurality of mats based on a column signal and a plurality of flag signals that are generated by performing a computational operation on an address during normal mode and configured to output second internal data from the meta region and a data input and output circuit configured to generate a plurality of data from the first internal data and the second internal data based on a plurality of shifting signals.
A storage device comprising a volatile memory comprising a plurality of physical areas, a compression operation circuit configured to compress write data at a first rate to generate first compressed data, and a control operation circuit configured to divide the plurality of physical areas included in the volatile memory into first physical areas and second physical areas, store the first compressed data in the first physical areas, and store first logical information indicating an area storing the first compressed data, in a first selected area of the second physical areas.
A memory device including a memory block, a cell counter, and a health information manager. The memory block includes a plurality of select transistors connected to a plurality of select lines and a plurality of memory cells connected to a plurality of word lines. The cell counter counts a number of degraded select transistors which exceed a normal threshold voltage distribution width among the plurality of select transistors, based on a cell current of the plurality of select transistors, and generates cell count information including the number of the degraded select transistors. The health information manager generates read reclaim information indicating whether the memory block is a read reclaim target according to a remaining read count of the memory block and a result obtained by comparing the remaining read count with a plurality of threshold read counts, based on the cell count information.
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.
A memory system includes at least one memory chip including first information regarding internal configurations and operational characteristics, and a memory controller configured to perform a data input/output operation on the at least one memory chip. The memory controller includes a core-processor engaged with firmware configured to generate at least one first command for controlling an operation associated with the first information, a memory control sequence generator configured to generate at least one second command for controlling an operation performed on a memory chip which includes second information, and a core interface configured to, when the first information is included in the second information, handover, to the core-processor from the memory control sequence generator, a process for generating some of the at least one command associated with a part of the first information, the part not included in the second information.
A storage device may include a memory storing data and a controller. Such a controller may receive a compression write command from an external device to compress and write original data, compress the original data, based on whether compression information that corresponds to the compression write command is supported, into compressed data using a preset value, and store the compressed data in the memory.
A memory media includes a first memory chip stacked over a substrate, a second memory chip stacked over the first memory chip, and a third memory chip stacked over the second memory chip. The first memory chip, the second memory chip, and the third memory chip are stacked in a staircase. Each of the first memory chip, the second memory chip, and the third memory chip includes outer chip pads disposed to form an outer row which is adjacent to a first edge; and inner chip pads disposed to form an inner row which is spaced apart from the first edge. The third memory chip is stacked over the second memory chip to expose the outer chip pads of the second memory chip and to cover the inner chip pads of the second memory chip.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
58.
SEMICONDUCTOR DEVICE INCLUDING OVERLAY KEYS AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including overlay keys and a method of manufacturing the device are provided. The semiconductor device includes first, second, third, and fourth pattern arrays. The first pattern array includes first conductive patterns and first overlay key segments. The second pattern array includes second overlay key segments and third overlay key segments. The third pattern array includes third conductive patterns and fourth overlay key segments. The fourth pattern array includes fifth overlay key segments and sixth overlay key segments. The first, second, third, fourth, fifth, and sixth overlay key segments provide alignment information of the fourth pattern array with respect to the first, second, and third pattern arrays.
A semiconductor device may include a peripheral circuit; a first gate structure disposed on the peripheral circuit; a second gate structure disposed on the first gate structure; a dielectric bonding structure extending between the first gate structure and the second gate structure; a first contact via extending through the first gate structure and extending into the dielectric bonding structure; a second contact via extending through the second gate structure and connected to the first contact via; and a peripheral circuit bonding structure electrically connecting the first contact via and the peripheral circuit to each other.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
60.
STORAGE DEVICE RESETTING, DEPENDING ON TEMPERATURE, WEIGHT FOR INCREASE IN READ COUNT AND OPERATING METHOD THEREOF
A storage device includes a memory, a controller, a first temperature sensor and a second temperature sensor. The storage device determines whether a preset weight reset condition is satisfied, based on at least one of the temperature of the memory measured from the first temperature sensor and the temperature of the controller measured from the second temperature sensor, and resets a weight for an increase in read count for data when it is determined that the weight reset condition is satisfied.
A semiconductor device includes a serializer, a transmission circuit, and a reception circuit. The serializer is configured to generate transmission data from first and second output data signals based on first and second transmission clock signals. The transmission circuit is configured to drive, based on the transmission data, a node that is electrically coupled to a signal transmission line. The reception circuit is configured to generate reception data, based on the first and second reception clock signals, the first and second output data signals, and a voltage level of the node.
A memory device includes a memory cell and a write circuit. The memory cell is coupled to a first access line and a second access line. The write circuit applies a first positive voltage to the first access line for a first period, applies a second positive voltage to the first access line for a second period, the second period being subsequent to the first period, and applies a negative voltage to the second access line for the first period and the second period.
Provided herein may be a data storage device for efficiently controlling performance and a method of operating the same. The data storage device may include a plurality of memory dies, a command storage configured to store commands, a credit information generator configured to generate and store maximum credit information indicating, for each command type, a maximum number of commands that are capable of being simultaneously performed by the plurality of memory dies, and a performance manager configured to provide the commands to the plurality of memory dies so that the plurality of memory dies process a number of commands greater than or equal to the maximum credit information.
Provided herein is a memory device and a method of manufacturing the memory device. The memory device includes gate lines stacked to be spaced apart from each other, first blocking layers enclosed by the gate lines and stacked to be spaced apart from each other, charge trap layers enclosed by the first blocking layers and stacked to be spaced apart from each other, protruding patterns located between the first blocking layers and between the charge trap layers, a tunnel isolation layer enclosed by the charge trap layers and the protruding patterns, and a channel layer enclosed by the tunnel isolation layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
According to an embodiment of the present disclosure, a fuse circuit includes an input circuit and a latch circuit. The input circuit transmits a fuse data signal to a first node and its inversion to a second node, controlled by a first control signal. The latch circuit, which includes a first inverter, a second inverter, and a clamp circuit, latches these signals. The first inverter outputs the inversion signal from the first node to the second node, while the second inverter outputs the original signal from the second node to the first node. The clamp circuit, connected between a power voltage node and the second node, maintains the signal at the first node at a stable level in response to the control signal and the voltage at the first node.
A memory system may include a memory device and a memory controller. The memory controller may execute firmware which controls the memory device, perform, when an abnormal event of the firmware is sensed, data communication with a host, based on hardware in place of the firmware, and reset the memory device when the access traffic is a threshold value or less.
A semiconductor memory device includes: a lower interconnection line; a lower electrode over the lower interconnection line; a variable resistance layer over the lower electrode; an oxygen reservoir layer over the variable resistance layer; an upper electrode over the oxygen reservoir layer; and an upper interconnection line over the upper electrode, wherein the variable resistance layer includes: a plurality of switching patterns spaced apart from each other in a horizontal direction; and an isolating dielectric layer filling spaces between the switching patterns. Each of the switching patterns includes an upper portion having a first width and a lower portion having a second width, and the first width is greater than the second width.
Provided herein may be an electronic device. The electronic device may include a housing providing an internal space and dissipating received heat, and a heat transfer structure transferring heat generated from a heater to a portion of the housing in response to gravity. The heat transfer structure may transfer the heat to a first surface of the housing corresponding to a forward direction of the gravity, and may form an air gap between a second surface of the housing corresponding to a reverse direction of the gravity and the heat transfer structure.
A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device is provided. The semiconductor device may include horizontal arrangement of switching elements including nano sheets and horizontal conductive lines surrounding the nano sheets; pyramid-shaped first contact nodes formed on first edges of the nano sheets in the horizontal arrangement; a horizontal arrangement of vertical conductive lines including pyramid portions surrounding the pyramid-shaped first contact nodes, and coupled to the nano sheets in the horizontal arrangement; data storage elements coupled to second edges of the nano sheets in the horizontal arrangement; and a supporter surrounding the vertical conductive lines in the horizontal arrangement.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 1/68 - Capacitors having no potential barriers
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
70.
STORAGE DEVICE SETTING ZONE WHERE COLD DATA IS TO BE STORED AND OPERATING METHOD OF THE STORAGE DEVICE
A storage device may receive provisioning information, which is setting information for a provisioning operation that sets a plurality of zones on a memory, from a host, and set a first zone in which cold data requested to be written by the host is stored, among the plurality of zones based on write booster type included in the provisioning information. The storage device may set the first zone in a first memory area if the write booster type is a first type, and set the first zone in a second memory area if the write booster type is a second type.
A method and associated memory system for randomizing memory storage data. The method and system receive at a randomizer user data and meta data having an inversion seed; generate a random sequence using a scrambling seed; generate a value for the inversion seed; XOR the user data including the meta data with the random sequence to produce an XORed sequence; and depending on the value of the inversion seed, bit-flip the XORed sequence except the inversion seed.
A memory device includes a bank configured to store a row counting value corresponding to the number of times each word line is accessed when an active operation is performed, and a column control circuit configured to perform a counting read operation and a counting write operation during a period in which a column selection operation set by a pre-charge command is performed.
A memory device includes a syndrome calculator configured to generate an error location signal based on first data and an error correction code; an error corrector configured to generate second data by correcting an error in the first data according to the error location signal; and a data mask (DM) calculation circuit configured to generate a DM signal according to logic high bits of the first data and change a logic level of the DM signal according to at least one of an increase signal and a decrease signal, by activating the increase signal when an error bit is detected in logic low bits of the first data and activating the decrease signal when the error bit is detected in the logic high bits of the first data, based on the error location signal.
A memory device include a plurality of memory cores and a plurality of meta storage circuits, each of the plurality of meta storage circuits corresponding to a different one of the plurality of memory cores. In an embodiment, when a meta write operation is performed, data that are received through an external line are stored in the plurality of memory cores based on a column address, and metadata that are received through a meta line are stored in a meta storage circuit, among the plurality of meta storage circuits, that is selected by the column address.
A storage device for providing a security function may include: a nonvolatile memory device including a Replay Protected Memory Block (RPMB); and a memory controller configured for receiving, from an external host, a command UFS Protocol Information Unit (UPIU) including a host RPMB message, and storing data in the RPMB according to authentication performed using the host RPMB message. The command UPIU may include a basic header segment commonly included in UPIUs transmitted/received between the external host and the memory controller, and the basic header segment may include a data segment length field as information indicating that the host RPMB message has been included in the command UPIU.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
A data storage device with improved lifespan according to the present technology may include a memory device including a plurality of memory cells disposed between word lines and bit lines, and a voltage generator configured to generate operation voltages and provide the operation voltages to the plurality of memory cells, and a controller configured to control the memory device to divide the plurality of memory cells into a plurality of groups according to a line resistance from the voltage generator to each of the plurality of memory cells, and store data in memory cells included in a selected group among the plurality of groups according to attribute of the data to be stored.
An imaging device includes an evaluation value calculator configured to calculate an evaluation value set including evaluation values corresponding to candidate parallaxes based on a phase image set, and a parallax calculator configured to calculate a target parallax based on the evaluation value set, the target parallax representing a phase shift value that allows to minimize a difference between phase images corresponding to phase signals with respect to an object to be imaged. Each of the evaluation values indicates a degree of certainty that the candidate parallax corresponding to each evaluation value is the target parallax.
A semiconductor device including high-integrated memory cells and a method for fabricating the semiconductor device are provided. The semiconductor device includes vertical and horizontal arrangements of nano sheets including horizontal sheets, which include protruding sheet nodes, and tapered sheets, which are continuous in a first horizontal direction from the horizontal sheets, a vertical arrangement of first conductive lines that surround portions of the horizontal sheets in the horizontal arrangement and are oriented in a second horizontal direction, first contact nodes covering the protruding sheet nodes of the horizontal sheets, a horizontal arrangement of second conductive lines that cover the first contact nodes and are oriented in a vertical direction, supporters that are disposed between the second conductive lines in the horizontal arrangement and are oriented in the vertical direction, and data storage elements coupled to the tapered sheets.
A semiconductor device including at least one memory cell is provided. The memory cell includes: a first electrode layer; a second electrode layer; a selection element layer coupled between the first electrode layer and the second electrode layer; and an insulating layer coupled between the first electrode layer and the second electrode such that a side surface of the insulating layer is in contact with a side surface of the selection element layer, wherein the selection element layer includes an insulating material doped with a first element, and wherein the insulating layer includes the insulating material doped with the first element at a lower concentration than the selection element layer, or the insulating material not doped with the first element.
A semiconductor device may include a substrate; a plurality of semiconductor pillars disposed over the substrate and arranged in a first direction and a second direction crossing the first direction; an insulating layer pattern disposed between the substrate and the semiconductor pillars and extending in the second direction; a first conductive line disposed between the insulating layer pattern and the semiconductor pillars and extending in the second direction; a second conductive line formed over sidewalls of the semiconductor pillars and extending in the first direction; and a storage node disposed over each of the semiconductor pillars.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
A semiconductor device may include: a first electrode; a switching layer located on the first electrode; an oxygen reservoir layer located on the switching layer; a second electrode located on the oxygen reservoir layer; a heating electrode located on a sidewall of the switching layer; and an insulating spacer located between the heating electrode and the switching layer.
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY (Republic of Korea)
Inventor
Lee, Seungjun
Jang, Junhyeok
Jung, Myoungsoo
Abstract
A data storage device includes an address estimating circuit configured to generate a start logical address and a request size corresponding to the start logical address from an input logical address corresponding to a write request; an address allocating circuit configured to allocate a target physical address corresponding to the input logical address by using the start logical address, the request size, and the input logical address; and a read queue storing a read command to be provided to a memory device, wherein the address estimating circuit estimates the start logical address considering a probability of the start logical address coexisting in the read queue with the input logical address.
An operating method of a memory system includes reading, by a plurality of memory chips, data from a first column of a defective row corresponding to a failure address; generating, by a memory controller, error-corrected data by correcting an error of the read data; and mapping, by a target chip selected from the plurality of memory chips, the failure address to a redundancy address, and writing the error-corrected data to a first column of a redundancy row corresponding to the redundancy address, wherein the reading, the generating, the mapping, and the writing are repeatedly performed on remaining columns of the defective row.
Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a cell region and a connection region arranged adjacent to each other in a first direction, a stacked structure formed in the cell region and the connection region, a first slit vertically passing through the stacked structure in the cell region and extending in the first direction, a second slit vertically passing through the stacked structure in the connection region and extending in the first direction, and a slit separation structure vertically penetrating the stacked structure at a boundary portion between the cell region and the connection region.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
85.
SEMICONDUCTOR WAFER INCLUDING FRAME IDENTIFIER, METHOD OF PROCESSING A SEMICONDUCTOR WAFER USING FRAME IDENTIFIER, AND SEMICONDUCTOR CHIP
A semiconductor chip according to an embodiment includes a substrate including a chip region and a residual scribe lane surrounding the chip region, and an infrared marker disposed inside the chip region or in the residual scribe lane. The infrared marker includes a plurality of optical patterns. The plurality of optical patterns includes integrated circuit structures with different stack structures over the substrate, and the plurality of optical patterns have differing infrared reflection characteristics.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
86.
MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE
Provided herein is a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to a plurality of word lines, respectively, a peripheral circuit configured to perform a test program operation and a pass bit detection operation of measuring a program speed of memory cells connected to a selected word line among the plurality of word lines during a test operation, and control logic configured to control the peripheral circuit to perform the test operation, and set a potential of a pass voltage to be used in a program operation, or a time point at which the pass voltage is to be applied, based on a number of times the test program operation is performed.
An imaging device and an image processing method and an image testing method for the same are disclosed. The image processing method includes generating a first transformed image by performing Fourier transform on a raw image; generating a second transformed image obtained by correcting the first transformed image using a correction parameter; and generating a corrected image by performing inverse Fourier transform on the second transformed image.
A semiconductor package includes a through electrode within a substrate. A wiring structure is disposed on the substrate and includes a chip pad and a protective insulating layer. A protrusion pattern is disposed on the protective insulating layer. A front bonding insulating layer is disposed on the wiring structure. The protrusion pattern is disposed within the front bonding insulating layer. A front bonding pad is disposed within the front bonding insulating layer and is connected to the chip pad.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
89.
PRECURSOR COMPOUND FOR THIN FILM FORMATION AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING SAME
The present techniques provide a precursor compound of chemical formula 1 for thin film formation and a preparation method therefor, wherein a photoresist layer can be prevented from undergoing pattern collapse by reducing the exposure time for pattern formation and minimizing the thickness of a lower layer with an etching selectivity similar to that of a photoresist or omitting the lower layer during post-exposure etching. In chemical formula 1, R0 is Si, Sn, Ge, Sb, In, Hf, Zr, Ti, or Te; R1 is CH3, CF3, CH═CH2, halogen, or phenyl; R2 and R2′ each are each independently alkyl or alkoxy; R3 is amine or halogen; R is hydrogen or halogen; n is an integer of 1-7.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
90.
SEMICONDUCTOR DEVICE, MEMORY SYSTEM INCLUDING DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF
A semiconductor device includes a delay locked loop (DLL) configured to output a first correction value corresponding to a single cycle of a clock and a duty correction circuit including a divider configured to divide the clock in half to generate a divided clock, delay the divided clock by a delay value corresponding to a half cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty ratio of 5:5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.
A semiconductor device includes a first insulating layer, a first bonding pad in the first insulating layer, a second insulating layer in contact with the first insulating layer, and a second bonding pad in the second insulating layer. The first bonding pad includes a first conductive layer and a first barrier layer surrounding the first conductive layer, and the second bonding pad includes a second conductive layer and a second barrier layer surrounding the second conductive layer. The second barrier layer is in contact with the first conductive layer. The second conductive layer is spaced apart from the first conductive layer. The first conductive layer includes a metal material which is different from a metal material included in the second conductive layer. The first and second barrier layers each include at least one of titanium and tantalum.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/43 - Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
92.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a peripheral circuit, a first gate structure positioned on the peripheral circuit, a first stack positioned at a level corresponding to the first gate structure, a source bonding structure positioned on the first gate structure, a first contact bonding structure positioned on the first stack, first channel structures extending into the source bonding structure through the first gate structure, a first contact plug extending into the first contact bonding structure through the first stack, a second gate structure positioned on the source bonding structure, a second stack positioned on the first contact bonding structure, second channel structures extending into the source bonding structure through the second gate structure, and a second contact plug extending into the first contact bonding structure through the second stack.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
93.
MEMORY DEVICE RELATED TO A READ VOLTAGE AND AN OPERATION METHOD OF THE MEMORY DEVICE
A memory device including: a plurality of word lines; a plurality of memory cells connected to each of the plurality of word lines, respectively; control logic configured to, based on an optimal read voltage value of a first word line among the plurality of word lines and an optimal read voltage value of a second word line among the plurality of word lines, calculates optimal read voltage values of word lines located between the first word line and the second word line by applying a position-based linear value; and a row decoder configured to apply the optimal read voltage value calculated by the control logic to a word line selected from the plurality of word lines.
Disclosed is a system including a first integrated circuit device and a second integrated circuit device coupled to the first integrated through a first transmission line and a second transmission line, wherein the first integrated circuit device includes a swing detector configured to detect a voltage level difference between the first transmission line and the second transmission line, a comparator configured to compare a detection value of the swing detector with a reference swing value, and a comparison result transmission circuit configured to transmit a comparison result of the comparator to the second integrated circuit device.
According to embodiments of the present disclosure, booting may be performed using different firmware based on the usage environment information of a storage device, and control may be performed by differently setting a processing delay time for the host device's commands and the operation priority for the reliability or stability of the storage device, thereby maintaining the operational stability of the storage device and preventing or minimizing the degradation of operating performance depending on the usage environment.
A memory device includes a first semiconductor layer including a memory cell array which is connected to word lines extending in a first direction and bit lines extending in a second direction substantially perpendicular to the first direction; and a second semiconductor layer disposed under the first semiconductor layer, and including a first area overlapping the first semiconductor layer in a third direction substantially perpendicular to the first and second directions and a second area overlapping the first area in the first direction, the second semiconductor layer including a row decoder disposed in the second area, and including pass transistors; and a first voltage switching circuit configured to transmit an operating voltage to the pass transistors, and including switching elements, wherein at least one switching element among the switching elements is disposed in the second area to overlap the pass transistors in the first direction.
A memory controller controls a storage medium including a first memory region and a second memory region, each of which has a plurality of memory blocks. The memory controller is configured to close an open block in the second memory region when a background operation is performed. The memory controller is configured to move data of at least one victim block of the first memory region and the second memory region, and erase the at least one victim block to generate at least one free block.
An operating method of a semiconductor device may include checking an operation time stamp when receiving a read command, calculating an elapsed time based on the operation time stamp that has been stored and a time when the read command has been received, comparing the elapsed time and a first setting time, selecting a read voltage having a first level instead of a target level when the elapsed time is greater than the first setting time, and performing a read operation based on the read voltage that has been selected.
A three-dimensional pillar type capacitive in-memory computing device may include a first wiring layer, a junction layer formed on the first wiring layer in a first direction, a channel including a pillar structure formed on the junction layer in the first direction, a charge storage layer configured to surround an upper surface and an outer surface of the channel, a charge transfer layer formed on the charge storage layer in the first direction, and a second wiring layer formed on the charge transfer layer in the first direction.
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
The present disclosure relates to a memory device including a first memory block including a first group of cell plugs and a second group of cell plugs, a second memory block including a third group of cell plugs and a fourth group of cell plugs, a connection region located between the first and second memory blocks, a first source select line commonly coupled to the first group of cell plugs and third group of cell plugs, a second source select line coupled to the second group of cell plugs, and a third source select line coupled to the fourth group of cell plugs.
