A data receiving circuit includes a first inductor, a second inductor, and a T-coil equalization circuit. The first inductor is coupled between a first node coupled with a data input/output pad and a second node. The second inductor is coupled between the second node and an internal circuit. The T-coil equalization circuit includes a T-coil with at least one capacitor coupled with the second node. The T-coil equalization circuit is configured to adjust inductive peaking of the T-coil in response to a control signal.
The present disclosure relates to a computing system. The computing system may include a memory system including a plurality of memory devices configured to store raw data and a near data processor (NDP) configured to receive the raw data by a first bandwidth from the plurality of memory devices and generate intermediate data by performing a first operation on the raw data, and a host device coupled to the memory system by a second bandwidth and determining a resource to perform a second operation on the intermediate data based on a bandwidth ratio and a data size ratio.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
3.
STORAGE DEVICE FOR LOADING MAP SEGMENT AND SENDING MAP SEGMENT TO EXTERNAL DEVICE, AND OPERATING METHOD THEREOF
A storage device may load, between a first time point at which information on candidate memory regions among a plurality of memory regions is started to be sent to an external device and a second time point at which a command requesting a map segment for a target memory region among the plurality of memory regions is received from the external device, all or a part of map segments corresponding to the candidate memory regions into a buffer.
Semiconductor devices and methods for fabricating semiconductor memory devices are disclosed. In an embodiment, a semiconductor device includes: a selector pattern configured to exhibit a threshold switching behavior; an insulating layer structured to a sidewall of the selector pattern and include an opening disposed within the insulating layer over the selector pattern; and an electrode formed in the opening to a thickness that blocks an entrance of the opening and does not completely fill the opening.
A memory device includes a memory cell array including a plurality of memory cells, a temperature sensor configured to measure an internal temperature and generate a temperature compensation code corresponding to the internal temperature, a voltage control circuit configured to generate a conversion temperature code converted from the temperature compensation code, and a voltage generation circuit configured to output a compensation voltage obtained by compensating for a level of a voltage used in an operation on the memory cell array responsive to the conversion temperature code. The temperature sensor and the voltage control circuit are may be located at different positions responsive to the memory cell array.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
A duty correction circuit includes a first delay circuit, a second delay circuit, a dividing circuit, a duty detection circuit, and a delay control signal generation circuit. The first delay circuit is configured to delay a clock signal to generate a first delayed clock signal. The second delay circuit is configured to delay the clock signal based on a delay control signal to generate a second delayed clock signal. The dividing circuit is configured to divide the first and second delayed clock signals to generate a first to fourth phase clock signals. The duty detection circuit is configured to detect phases of the first to fourth phase clock signals to generate a duty detection signal. The delay control signal generation circuit generates the delay control signal based on the duty detection signal.
An image sensing device including a source follower transistor is disclosed. The image sensing device includes first and second photoelectric conversion elements that supported by the semiconductor substrate and are spaced apart from each other, a first pixel isolation structure recessed from the second surface and configured to surround the first and second photoelectric conversion elements; second and third pixel isolation structures disposed between the first photoelectric conversion element and the second photoelectric conversion element and spaced apart from each other; and a source follower transistor supported by the semiconductor substrate and configured to include a gate disposed on the second surface in at least a portion of a gap region between the second pixel isolation structure and the third pixel isolation structure.
A power clamp circuit includes an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor, and a third triggering circuit including a third resistor and a third capacitor, and configured to turn off the third MOS transistor during a normal operation and turn on the third MOS transistor when an ESD event occurs.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
9.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a source structure, a support structure positioned on the source structure and including a first inclined surface extending in a second direction crossing the first direction, a gate structure positioned on the source structure and the support structure and including conductive layers and insulating layers alternately stacked, channel structures extending through the gate structure and connected to the source structure, and a slit structure extending in the first direction through the gate structure, wherein each of the conductive layers includes a second inclined surface extending in the second direction.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A memory includes: first to Nth register circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to Nth selection signals is activated, where N is an integer equal to or greater than 2; first to Nth resource latch circuits suitable for storing first to Nth resource signals indicating availability of the first to Nth register circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to Nth resource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to Nth selection signals.
A memory system is provided to include a memory device including a first memory block and a second memory block, and a memory controller configured, in response to a read request from a host, to control the memory device to read data stored in a first page corresponding to a first logical address included in the read request, update a read count of the first memory block including the first page, and perform a refresh operation of copying data stored in pages of the first memory block to the second memory block based on the read count of the first memory block. The memory controller is further configured to control a priority of the refresh operation on any page based on the number of times logical addresses corresponding to the pages of the first memory block that are received from the host.
A semiconductor device includes: a selector pattern including an insulating material having dopants implanted to the insulating material along an implantation direction and having a first sidewall and a second sidewall facing the first sidewall, the selector pattern configured to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage; and a first electrode layer and a second electrode layer respectively formed over the first sidewall and the second sidewall of the selector pattern, wherein the implantation direction of the dopants is different from a direction of a current flowing through the selector pattern between the first electrode layer and the second electrode layer when the selector pattern is turned on.
Provided herein is a method of manufacturing a memory device. The method may include forming an ion implantation region in a portion of an outer portion of an underlying structure by implanting ions into the underlying structure, transforming the ion implantation region into an etch stop pattern, forming a target structure on the underlying structure including the etch stop pattern, and performing an etching process to form first holes and second holes in the target structure, wherein the first width of the first holes is different than the second width of the second holes. The etching process is performed until the etch stop pattern is exposed through the first holes and the second holes.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM) (USA)
Inventor
Huang, Pengfei
Kwok, Zion
Zhang, Fan
Abstract
This application is directed to data validation in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device from a memory controller that is coupled to the memory device in a memory system. In response to the inquiry, the memory device selects a subset of the page of the memory device to represent the page. The subset of the page stores a set of memory data. The memory device obtains integrity data corresponding to the set of memory data, applies a plurality of validation operations on the set of memory data and the integrity data corresponding to the set of memory data to generate a plurality of validity results. The memory device determines an error parameter of the page locally based on the plurality of validity results and provides the error parameter to the memory controller.
An image processing device includes a bit length determiner configured to determine a bit length which indicates a number of at least one bit from among all bits of image data, an upper bit extractor configured to extract, from the image data, at least one upper bit corresponding to the bit length, and a noise processing unit configured to perform noise reduction processing for a target pixel using the at least one upper bit of the image data.
A bonding structure may include a non-conductive layer and at least one conductive pad. The non-conductive layer may have a first surface and a second surface opposite to the first surface. The conductive pad may be arranged in the non-conductive pad. The conductive pad may include a vertical pattern portion and at least one volume compensation portion. The vertical pattern portion may extend from the first surface to the second surface in the non-conductive layer. The volume compensation portion may be formed on a sidewall of the vertical pattern portion.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
The present disclosure relates to a semiconductor memory device including various types of memories to which a host is connected. The semiconductor memory device in one implementation includes a storage memory comprising a nonvolatile memory and a nonvolatile memory controller configured to control the nonvolatile memory; a main memory comprising a volatile memory and a volatile memory controller configured to control the volatile memory; and an access controller communicatively coupled to the storage memory and the main memory and configured to perform data communication with an external device based on a first protocol, perform data communication with the storage memory based on a second protocol, perform data communication with the main memory based on a third protocol, and control access from the external device to the storage memory and the main memory.
A data processing system is provided to include a storage unit and a controller in communication with the storage unit and configured to program write data to a first area as at least one of the plurality of storage areas with a priority over a second area as at least one of the plurality of storage areas and transfer data of the first area to the second area. The controller is further configured to adjust a size of the first area based on 1) a number of times saturated by the write data for the first area, a saturation occurring due to a size of the write data written to the first area being greater than a certain size and 2) an overflow size of the write data corresponding to a difference between the size of the write data and the certain size.
A memory device, and a method of manufacturing the same, includes interlayer insulation layers spaced apart from each other and stacked, gate lines formed between the interlayer insulation layers, and a plug vertically passing through the interlayer insulation layers and the gate lines. Each of the gate lines includes a barrier layer formed along an inner wall of the interlayer insulation layer and the plug, a first conductive layer surrounded by the barrier layer, and a second conductive layer surrounded by the first conductive layer and having a grain size different from a grain size of the first conductive layer. A volume of the second conductive layer is variable along a direction in which the gate lines extend.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
20.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device, and a method of manufacturing the same, includes a gate stack including an interlayer insulating layers and conductive patterns alternately stacked in a vertical direction on a substrate, a channel structure passing through the gate stack and having an upper end protruding above the gate stack, a memory layer surrounding a sidewall of the channel structure, and a source layer formed on the gate stack. The channel structure includes a core insulating layer extending in a central region of the channel structure in the vertical direction, and a channel layer surrounding a sidewall of the core insulating layer, the channel layer formed to be lower in the vertical direction than the core insulating layer and the memory layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
21.
STORAGE DEVICE DETERMINING MEMORY AREA TO WHICH DATA IS WRITTEN USING WRITE THROUGHPUT AND METHOD OF OPERATION
A storage device may determine write throughput based on a plurality of write commands received from the outside of the storage device, and write target data write-requested from the outside to a first memory area including one or more of a plurality of first type memory blocks or a second memory area including one or more of a second type memory blocks according to whether the write throughput is greater than or equal to a threshold throughput. The first type memory blocks may operate at a higher speed than the second type memory blocks.
A memory includes: a memory core; a list storage circuit suitable for storing a weak row list of rows that are vulnerable to a row hammer attack in the memory core; and a row hammer attack detection circuit suitable for selecting rows that are row-hammer-attacked among rows in the memory core as hammered rows, and increasing a probability that the rows stored in the list storage circuit are selected as the hammered rows.
A memory device, and a method of testing the memory device for failure, includes a first chip including a memory cell array and a second chip overlapping with the first chip. The second chip includes: a semiconductor substrate including a peripheral circuit area and a lower test area; a plurality of sub-test pads and an input pad, disposed on the lower test area of the semiconductor substrate and spaced apart from each other; a plurality of sub-test circuits respectively connected to the plurality of sub-test pads; and a detection circuit connected to a plurality of terminals of the plurality of sub-test circuits, the detection circuit configured to output a detection signal changed according to a plurality of signals input from the plurality of terminals.
An image signal processor includes a directional component extractor configured to extract directional components of a target kernel by performing a convolution operation between the target kernel including a target pixel and each of a plurality of directional kernels, an interpolation kernel determiner configured to determine an interpolation kernel based on the directional components, and a pixel interpolator configured to interpolate the target pixel using data included in the interpolation kernel.
A power clamp circuit includes an electro-static discharge (ESD) current discharge circuit including a first MOS transistor, a second MOS transistor, and a third MOS transistor that are coupled in series between a first power rail coupled to a supply voltage and a second power rail coupled to a ground voltage, a first triggering circuit including a first resistor, a first capacitor, and a fourth MOS transistor and configured to trigger the first MOS transistor, a second triggering circuit including a second resistor, a second capacitor, and a fifth MOS transistor and configured to trigger the second MOS transistor, and a third triggering circuit configured to turn off the third MOS transistor during a normal operation and turn on the third MOS transistor when an ESD event occurs.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
26.
PROCESSING-IN-MEMORY DEVICES HAVING MULTIPLICATION-AND-ACCUMULATION CIRCUITS
A processing-in-memory (PIM) device includes a first memory region, a second memory region, a third memory region, and a multiplication-and-accumulation MAC circuit. The first memory region is configured to store weight data comprised of elements of a weight matrix. The second memory region is configured to store vector data comprised of elements of a vector matrix. The third memory region is configured to store constant data. The MAC circuit is configured to selectively perform a MAC arithmetic operation of the weight data and the vector data or an element-wise multiplication (EWM) arithmetic operation of the weight data and the constant data.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
SK Hynix NAND Product Solutions Corp. (dba Solidigm) (USA)
Inventor
Huang, Pengfei
Kwok, Zion
Zhang, Fan
Abstract
This application is directed to data validation in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device from a memory controller that is coupled to the memory device in a memory system. In response to the inquiry, the memory device selects a subset of the page of the memory device to represent the page. The subset of the page stores a set of memory data. The memory device obtains integrity data corresponding to the set of memory data, applies a plurality of validation operations on the set of memory data and the integrity data corresponding to the set of memory data to generate a plurality of validity results. The memory device determines an error parameter of the page locally based on the plurality of validity results and provides the error parameter to the memory controller.
An embodiment of the present disclosure relates to a memory device configured to: apply an erase voltage and a first pass voltage at a first time, apply a turn-on voltage at a second time before a level of the erase voltage increases to a target level, maintain the erase voltage, the first pass voltage, and the turn-on voltage at a third time when the level of the erase voltage equals the target level, and reduce a voltage difference between a memory cell and a word line at a fourth time after the third time.
In an embodiment, a semiconductor device may include a T-coil transferring a signal from the outside to an internal circuit, a plurality of power lines transferring power from the outside to the internal circuit and disposed below the T-coil and at least one capacitor connected between the plurality of power lines.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
30.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a selector pattern including an insulating material doped with a dopant to exhibit different electrical conducting characteristics in response to an applied voltage with respect to a threshold voltage, wherein the selector pattern includes a first region that is formed in an edge extending from a sidewall of the selector pattern and a second region that has a sidewall in contact with the first region, and a concentration of the dopant in the first region is different from a concentration of the dopant in the second region.
An exposure mask for forming a pattern having a first width includes a first line, a second line, and at least one bridge line. The first line may be extended in a first direction. The first line has a second width narrower than the first width. The second line may be extended parallel to and spaced apart from the first line. The second line is formed having the second width. The bridge line may be connected between the first line and the second line.
A pull-down circuit and a pull-up circuit for using various voltages, and a voltage supply circuit including the pull-down circuit and the pull-up circuit are disclosed. The pull-up circuit includes a sink circuit configured to receive a charge pump voltage from a charge pump circuit and pull up the charge pump voltage of the charge pump circuit to a ground voltage, wherein the charge pump voltage is less than the ground voltage, and a level shifter configured to generate a level shifter output voltage and a one-shot signal in response to a charge pump enable signal controlling the charge pump circuit wherein the level shifter output voltage controls the sink circuit, and the one-shot signal prevents floating of a node through which the level shifter output voltage is output.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
33.
SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device according to an embodiment of the present disclosure may include forming a first sacrificial layer including a first portion and a second portion having a thickness thicker than a thickness of the first portion, forming a stack including first material layers and second material layers alternating with each other on the first sacrificial layer, forming a channel structure passing through the stack and extending to the first portion, forming a slit passing through the stack and extending to the second portion, removing the first sacrificial layer through the slit to form a first opening, and forming a second source layer connected to the channel structure in the first opening.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A clock generating circuit includes a buffer circuit and a phase compensating circuit. The buffer circuit buffers an input clock signal to generate an output clock signal. The phase compensating circuit detects a noise in a power voltage and adjusts, according to the noise of the power voltage, a voltage level of the input clock signal to compensate for a phase change of the output clock signal due to the noise of the power voltage.
A semiconductor memory device includes a bit line, a common source pattern above the bit line, a channel layer in contact with the common source pattern, the channel layer extending toward the bit line, and a filling insulating layer disposed between the bit line and the common source pattern, the filling insulating layer surrounding a first part of the channel layer. The semiconductor memory device also includes a gate stack structure disposed between the bit line and the filling insulating layer, the gate stack structure surrounding a second part of the channel layer. The semiconductor memory device further includes a first etch stop pattern on a sidewall of the filling insulating layer, a second etch stop pattern between the first etch stop pattern and the filling insulating layer, and a memory pattern between the gate stack structure and the channel layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
36.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
There are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. The semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
37.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
There are provided a semiconductor memory device and a method of manufacturing a semiconductor memory device. The semiconductor memory device includes a conductive pattern, an etch stop layer on the conductive pattern, a conductive bonding pattern including a contact portion connected to the conductive pattern, and a pad portion extending from the contact portion, a first dielectric layer disposed on the etch stop layer and spaced apart from the conductive bonding pattern, and a second dielectric layer including a first portion surrounding a sidewall of the contact portion of the conductive bonding pattern between the pad portion of the conductive bonding pattern and the etch stop layer, and a second portion extending from the first portion to cover an upper surface of the first dielectric layer.
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
38.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE
Provided herein is a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a first string group including at least one first memory string and a second string group including at least one second memory string, each string connected in parallel between the bit line and the source line, wherein the at least one first memory string and the at least one second memory string each include at least one down source select transistor, at least one first up source select transistor, and at least one second up source select transistor, and the at least one first up source select transistor of the at least one first memory string is programmed to a first state, and the at least one first up source select transistor of the at least one second memory string is programmed to a second state different from the first state.
In an embodiment of the disclosed technology, a data storage device includes at least one memory device including a plurality of memory regions configured to store data, a first controller configured to allocate the plurality of memory regions according to a memory allocation request of one or more host devices, and a second controller configured to: generate, in response to a snapshot request of a first host device among the one or more host devices, snapshot data corresponding to at least part of the data stored in at least part of the plurality of memory regions allocated to the first host device; and store the snapshot data into an auxiliary storage device coupled to the second controller.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
40.
SIGNAL DRIVER CIRCUIT, AND A SEMICONDUCTOR APPARATUS USING THE SAME
A signal driver circuit includes a pre-driving circuit, a driving signal generating circuit, a main driving circuit, and an output control circuit. The pre-driving circuit is configured to generate a first pre-driving signal and a second pre-driving signal based on an input signal and a clock signal. The driving signal generating circuit is configured to generate a pull-up driving signal and a pull-down driving signal based on the first pre-driving signal, the second pre-driving signal, and a complementary delayed output signal. The main driving circuit is configured to generate an output signal based on the pull-up driving signal and the pull-down driving signal. The complementary delayed output signal is generated by delaying the output signal. The output control circuit is configured to latch the output signal and configured to delay the output signal to generate a delayed output signal and the complementary delayed output signal.
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A lock detecting circuit includes a pre-clock detection signal generating circuit configured to detect phases of a first clock and a second clock to generate a first pre-clock detection signal and a second pre-clock detection signal based on the detected phases, a first clock detection signal generating circuit configured to generate a first clock detection signal by adjusting a pulse width of the first pre-clock detection signal, a second clock detection signal generating circuit configured to generate a second clock detection signal by adjusting a pulse width of the second pre-clock detection signal, and a lock control circuit configured to detect a phase difference between the first clock and the second clock, based on the first clock detection signal and the second clock detection signal to generate a lock signal.
H03L 7/095 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
The present technology relates to an image signal processor. According to the present technology, an image signal processor may include a depth map generator configured to generate, based on a target resolution of an output image, a downsized left image and a downsized right image based on an input image received from an external device, and generate a depth map image indicating depth values corresponding to pixels included in the output image based on the downsized left image and the downsized right image, and a noise remover configured to perform guide filtering on the depth map image using the input image as a guide image and generate the output image.
A semiconductor device includes a substrate; a first electrode layer disposed over the substrate; an interlayer insulating layer having an opening that exposes the first electrode layer; an oxide semiconductor layer formed along a surface of the opening and connected to the first electrode layer; a gate insulating layer formed along a surface of the oxide semiconductor layer; a stacked structure including a first gate electrode layer, a first insulating layer, a second gate electrode layer, and a second insulating layer stacked in a vertical direction while filling a remaining space of the opening in which the oxide semiconductor layer and the gate insulating layer are formed; and a second electrode layer disposed over the stacked structure and the oxide semiconductor layer and connected to the oxide semiconductor layer.
An image sensing device for obtaining an image of a scene by sensing light is disclosed. The image sensing device includes a pixel circuit configured to output a pixel signal based on a voltage level of a floating diffusion node at which charges generated corresponding to an intensity of incident light are accumulated, a voltage controller configured to control a voltage level of an output node where the pixel signal is output in response to a voltage control signal, a conversion circuit configured to convert the pixel signal into a digital signal, and a voltage trimming circuit configured to control the voltage control signal based on the digital signal.
An image sensing device includes a phase difference calculator configured to calculate a phase difference between a modulated light signal and reflected light based on a plurality of captured data generated by a plurality of modulation control signals, each of which has a predetermined modulation phase difference with respect to the modulated light signal; a phase difference corrector configured to calculate a contrast, which is a ratio of an amplitude component of the reflected light to an intensity component of the reflected light, using the plurality of captured data, and determine an aliasing value corresponding to the contrast; and a distance calculator configured to calculate a distance to a target object using a corrected phase difference obtained by correcting the phase difference according to the aliasing value.
H04N 23/76 - Circuitry for compensating brightness variation in the scene by influencing the image signals
G01S 17/36 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated with phase comparison between the received signal and the contemporaneously transmitted signal
H04N 25/703 - SSIS architectures incorporating pixels for producing signals other than image signals
46.
RAMP GENERATION CIRCUIT, IMAGE SENSING DEVICE INCLUDING THE RAMP GENERATION CIRCUIT, AND METHOD FOR OPERATING THE IMAGE SENSING DEVICE
A ramp generation circuit includes a ramping voltage generator configured to generate a ramping voltage that changes depending on a first slope or a second slope, a blocking capacitor configured to transmit the ramping voltage to a transfer node, a signal output unit configured to amplify a voltage of the transfer node and to output a ramp output signal to an output node, and a ramp switch configured to selectively connect the transfer node to the output node.
Memory systems and methods of operating the memory systems are disclosed. A memory system including a plurality of data storage zones may comprise a memory device including a plurality of zones for storing data, and a memory controller configured to control the memory device in performing a write operation in the memory device. The memory controller is configured to, upon performing a write operation corresponding to a write request received from a host, update a logical write pointer and a physical write pointer associated with a zone that is targeted to perform the write operation corresponding to the write request received from the host, and upon performing a write operation corresponding an internal write command internally issued by the memory controller, update a physical write pointer associated with the zone that is targeted to perform the write operation corresponding to an internal write command issued by the memory controller.
The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.
There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked, a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
50.
STORAGE DEVICE SYNCHRONIZING INFORMATION ON TARGET ZONE AND METHOD FOR OPERATING STORAGE DEVICE
A storage device may update, when executing a recovery operation for a sudden power-off, zone information for a target zone among a plurality of zones, and may transmit, after updating the zone information, an exception event alert message to a host. Further, the storage device may receive, after transmitting the exception event alert message, a command from the host, and may transmit updated zone information to the host as a response to the command.
A semiconductor device may include first and second transistors on a substrate. The first transistor may include first and second source/drain regions; a first channel region between the first and second source/drain regions; a first gate electrode over the first channel region; and a charge retention node between the first channel region and the first gate electrode. The second transistor may include third and fourth source/drain regions, a portion of the third source/drain region being connected to the charge retention node; a second channel region between the third and fourth source/drain regions; and a second gate electrode over the second channel region.
G11C 16/26 - Sensing or reading circuitsData output circuits
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A storage device manages memory use data, such as map data which the storage device manages using a host memory, as journal data in a buffer memory located inside the storage device in a low power mode. The memory use data may be managed by updating journal data during the low power mode, and a command of a host device may be processed by updated journal data after switching from a low power mode to an active mode.
A storage device includes a memory apparatus configured to store logical to physical (L2P) information, and a controller coupled to be in communications with the memory apparatus and configured to selectively change a map update mode based on a map update history after performing a map management operation on the L2P information.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductors; semiconductor chips; wafers for integrated circuits; integrated circuits; integrated circuit modules; printed circuit boards; semiconductor memories; downloadable and recorded computer software for managing semiconductor memories, solid state drives, hard disk drives and data storage apparatus; integrated circuit cards.
57.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes: a substrate; a first magnetic tunnel junction structure disposed over a portion of the substrate and including a first free layer; a first hard mask layer disposed over the first free layer; a second magnetic tunnel junction structure disposed over another portion of the substrate and including a second free layer having a thickness smaller than a thickness of the first free layer; a second hard mask layer disposed over the second free layer; and a doped layer interposed between the second free layer and the second hard mask layer and having conductivity.
H10N 59/00 - Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups
58.
BUFFER CHIP, SEMICONDUCTOR PACKAGE INCLUDING BUFFER CHIP AND MEMORY CHIP, OPERATION METHOD OF BUFFER CHIP, AND OPERATION METHOD OF SEMICONDUCTOR PACKAGE
An operation method of a buffer chip may include receiving first control signals for setting a first memory chip; buffering the first control signals and transmitting the buffered signals to the first memory chip; storing a setting value of the first memory chip in response to the first control signals; receiving second control signals for setting a second memory chip; buffering the second control signals and transmitting the buffered second control signals to the second memory chip; storing a setting value of the second memory chip in response to the second control signals; receiving third control signals for applying the setting value of the first memory chip; buffering the third control signals and transmitting the buffered third control signals to the first memory chip; and applying the stored setting value of the first memory chip as a setting value of a buffer chip in response to the third control signals.
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
59.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device may include: a first gate structure; a second gate structure disposed over the first gate structure; and a channel structure including a first portion extending through the first gate structure, the first portion having a tapered cross section, a second portion having a tapered cross section, and a third portion connecting the first portion with the second portion, wherein the third portion has a vertical profile, and wherein the second portion and the third portion extends through the second gate structure.
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
60.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a first electrode, a second electrode, a variable resistance layer positioned between the first electrode and the second electrode and maintaining a phase before and after a program operation, a non-conductive sealing layer positioned between the first electrode and the variable resistance layer, and a nanostructure positioned inside the non-conductive sealing layer and spaced apart from the variable resistance layer.
A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked, a channel layer passing through the gate structure, an insulating core disposed in the channel layer, and a capping layer including a capping pattern disposed in the channel layer and a capping liner disposed between the capping pattern and the insulating core and extending between the channel layer and the capping pattern, wherein the capping liner and the capping pattern may include impurities having different concentrations.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Provided herein may be a memory controller. The memory controller may include a shared memory configured to store data, a hardware group configured to generate entry data including result data of an operation corresponding to a command, and output an interrupt signal generated in response to storage of the entry data, and a processor group configured to receive the entry data from the shared memory, wherein the processor group includes an interface converter configured to manage first index information of the entry data in response to the interrupt signal, and generate a first address for the entry data based on the first index information, and a data transmitter configured to receive, based on a first address, the entry data through a first interface using a data input/output scheme, and transfer the received entry data to a processor through a second interface using a fixed data input/output scheme.
A pellicle structure may include a membrane border and a pellicle membrane. The membrane border defines an open region. The membrane is in contact with the membrane border and extending over the open region. Thus, the membrane is capable of maintaining a thin film having a uniform thickness to prevent pattern errors.
A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating the identified device information on memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
A normalizer for performing normalization on floating-point data includes a search circuit configured to receive selected mantissa data and to output reference exponent data and shift data, the selected mantissa data being either mantissa data of the floating-point data or 2's complement data of the mantissa data, an exponent adder configured to output normalized exponent data by adding exponent data of the floating-point data and the reference exponent data, and a unidirectional mantissa shifter configured to output normalized mantissa data by performing a unidirectional shift on the selected mantissa data based on a value of the shift data.
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
G06F 7/499 - Denomination or exception handling, e.g. rounding or overflow
66.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
Embodiments of the present invention provide a semiconductor device capable of improving current leakage property and a method for fabricating the same. According to an embodiment of the present invention, a capacitor comprises: a lower electrode; a dielectric layer over the lower electrode; and an upper electrode over the dielectric layer, the upper electrode including a conductive carbon-containing layer, wherein a carbon content in the conductive carbon-containing layer is more than 5 at % and equal to or less than 10 at %.
A method of manufacturing a semiconductor device may include forming a polishing stop layer on a substrate, forming a stack on the polishing stop layer, forming channel structures extending through the stack and the polishing stop layer and having different heights, polishing the substrate and the channel structures to expose the polishing stop layer, and removing the polishing stop layer.
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate; a lower portion of a first conductive pattern disposed over the substrate and extending in a second direction; a stacked structure disposed over the lower portion of the first conductive pattern and having a pillar shape, the stacked structure including an upper portion of the first conductive pattern, an oxide semiconductor channel, and a second conductive pattern; and a word line extending in a first direction intersecting the second direction and facing at least a portion of a sidewall of the oxide semiconductor channel with a gate insulating layer therebetween, wherein the first conductive pattern includes a first conductive metal oxide, and the lower portion of the first conductive pattern corresponds to a bit line, and the upper portion of the first conductive pattern corresponds to a drain electrode.
A memory device includes a plurality of memory planes, each including a plurality of memory banks; one or more plane groups, each comprising at least two memory planes sharing at least one peripheral circuit; a plurality of compressing circuits, each connected to a corresponding memory bank and outputting compressed data by compressing data read from the corresponding memory bank; a plurality of merge circuits, each receiving compressed data and at least one output control signal corresponding to a merge group of a plurality of merge groups, each merge circuit outputting, in response to at least one output control signal, merged data obtained by merging compressed data corresponding to memory banks grouped in the merge group; and an output buffer circuit latching and outputting the merged data in response to at least one output control signal. The merge group comprises at least two memory banks in a same plane group.
Disclosed is an image sensor and an image processing system including the same, and the image sensor includes a first pixel pair arranged in a first row, and configured to generate, during a first single readout time, first and second pixel signals according to a first order, a second pixel pair arranged in the first row, and configured to generate, during the first single readout time, third and fourth pixel signals according to a second order which is different from the first order, and a row controller configured to control, during the first single readout time, the first pixel pair according to the first order and the second pixel pair according to the second order.
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a first structure including a first chip area and a first scribe lane area, a second structure provided on the first structure, a first alignment key disposed in the first scribe lane area, at least one first bonding pad provided between the first alignment key and the first chip area, the first bonding pad bordering an upper surface of the first structure, and a second bonding pad bordering a lower surface of the second structure to contact the at least one first bonding pad.
An external connection pad apparatus includes a first pad and a second pad. The first pad has a first surface area. The second pad has a second surface area larger than the first surface area.
A semiconductor device includes a common conductive line extending in a first direction; a memory cell array including a plurality of horizontal layers stacked in the first direction while sharing the common conductive line; and a selector structure operatively coupled to the common conductive line, wherein the selector structure includes, a plurality of select transistors stacked in the first direction; and a selector commonly coupled to the select transistors.
A method for fabricating a semiconductor device includes forming a cell mold including a dummy channel pattern and a plurality of mold layers over a lower structure; forming a horizontal conductive line that intersects with the dummy channel pattern; forming a dummy channel layer by trimming the dummy channel pattern; forming a data storage element that is coupled to a first side of the dummy channel layer; replacing the dummy channel layer with a channel layer; and forming a vertical conductive line that is coupled to a second side of the channel layer.
A data storage device includes: a memory device including a plurality of first storage areas and a plurality of second storage areas, each of which stores a primary index corresponding to a primary key provided from a host and a primary value corresponding to the primary index, and a memory controller for controlling the memory device. The memory controller is configured to generate, according to a request from the host, the primary index including the primary key and address information of a target second storage area in which a primary value corresponding to the primary key is stored, among the plurality of second storage areas, generate, according to an additional request from the host, a secondary key corresponding to a secondary value including a portion of the primary value, and generate a secondary index including the secondary key and the address information of the target second storage area.
An image sensing device includes a substrate extending in a first direction and a second direction and including a first surface and a second surface; a plurality of unit pixel regions supported by the substrate to generate signal carriers through conversion of incident light; a plurality of circuit structures arranged to be spaced apart from each other in the first direction to generate a current in the substrate and capture the signal carriers carried by the current; a first isolation structure disposed between adjacent unit pixel regions in the substrate and extending vertically in a depth direction of the substrate while extending in the second direction; and a plurality of second isolation structures located on two opposite sides of the plurality of circuit structures in the second direction within the substrate, and arranged to extend obliquely in a depth direction in the substrate while extending in the first direction.
Provided herein are a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a transistor, a cell array structure, a molded insulating structure including a first area disposed between the transistor and the cell array structure and overlapping with the transistor and a second area extending sideways from the first area, a pass gate disposed in the second area of the molded insulating structure, an active pillar penetrating the pass gate, and a pass gate insulating layer disposed between the active pillar and the pass gate.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
G11C 16/08 - Address circuitsDecodersWord-line control circuits
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
78.
PELLICLE MEMBRANE, PELLICLE ASSEMBLY INCLUDING THE SAME AND METHOD OF MANUFACTURING THE PELLICLE ASSEMBLY
A pellicle assembly may include a pellicle membrane and a pellicle border. The pellicle membrane may include at least one recess and at least one opening. The at least one recess may extend from an upper surface or a lower surface of the pellicle membrane. The at least one opening may penetrate from the upper surface to the lower surface of the pellicle membrane. The pellicle border may support the pellicle membrane.
An image sensing device includes a semiconductor substrate; unit pixels supported by the semiconductor substrate to detect light incident to the unit pixels and to convert detected light into pixel signal, and an inter-pixel isolation structure disposed between adjacent unit pixels to physically isolate the adjacent unit pixel from each other. Each unit pixel includes photoelectric conversion elements, an inner-pixel isolation structure disposed between adjacent photoelectric conversion elements within the unit pixel and at least one overflow path configured to interconnect the photoelectric conversion elements within the unit pixel, and wherein each unit pixel is shaped in a triangular shape when viewed in a plane.
A memory controller includes a scrub control circuit configured to generate a scrub command for instructing a scrub operation; and an address generation circuit configured to generate a scrub address having an address sequence in which a first column bit group of a column address, a row address, and a second column bit group of the column address are sequentially allocated from a least significant bit (LSB) to a most significant bit (MSB), and change a value of the scrub address according to the scrub command.
An image sensing device includes a semiconductor substrate, a first pixel region, and a second gate. The semiconductor substrate includes a first pixel region configured to include at least one first photoelectric conversion region and at least one first floating diffusion region, a second pixel region located adjacent to the first pixel region in a first direction and configured to include at least one second photoelectric conversion region and at least one second floating diffusion region, and a first inter-pixel isolation structure disposed between the first pixel region and the second pixel region. The first gate disposed over the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region. The second gate disposed at one side of the first gate on the semiconductor substrate extends to overlap the first pixel region, the first inter-pixel isolation structure, and the second pixel region.
An image sensing device includes a counter configured to generate first count data by counting pulses corresponding to photocharges, a shift register configured to store second count data corresponding to upper digits of the first count data, and an adder configured to sum the second count data and an overflow value indicating whether the first count data has overflowed.
INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY (Republic of Korea)
Inventor
Kang, In Ku
Min, Kyung Hoon
Hong, Sung In
Song, Yun Heub
Sim, Jae Min
Song, Ji Ho
Abstract
A method of programming a three-dimensional semiconductor memory device includes applying a first word line programming voltage to a selected word line among the word lines, floating unselected word lines among the word lines, and applying a back-gate pass voltage to the back-gate electrode; applying a first word line verification voltage to the selected word line, applying a word line pass voltage to the unselected word lines, and applying a first back-gate verification voltage to the back-gate electrode; applying a second word line programming voltage to the selected word line, floating the unselected word lines, and applying the back-gate pass voltage to the back-gate electrode; and applying a second word line verification voltage to the selected word line, applying the word line pass voltage to the unselected word lines, and applying a second back-gate verification voltage to the back-gate electrode.
A Peripheral Component Interconnect express (PCIe) device includes a Direct Memory Access (DMA) device including a plurality of functions; and a PCIe interface device for performing communication between a host and the DMA device. The PCIe interface device includes a reset operation controller for, when a plurality of reset signals are received from the host, grouping operations, which are the same as one another among reset operations respectively corresponding to the plurality of reset signals, determining a processing order of the reset operations, and performing the reset operations according to the processing order.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
85.
IMAGE SIGNAL PROCESSOR AND IMAGE SIGNAL PROCESSING METHOD
An image signal processor capable of processing image signals and an image signal processing method for the same are disclosed. The image signal processor includes a remosaic processor configured to by perform remosaic processing on an input image to generate a converted image, a noise-amount estimator configured to estimate an amount of noise of the converted image based on preset noise-amount parameters and the input image, a noise-reduction-degree determiner configured to determine a degree of noise reduction and generate noise-reduction-degree information, and a noise suppression processor configured to generate an output image in which the degree of noise reduction is controlled based on the noise-reduction-degree information.
A memory device includes an open memory block and control circuitry. The open memory block includes at least one first page having an erased state. The control circuitry is configured to perform a read operation for a page included in the open memory block, and apply a weight determined based on a ratio of the at least one first page in the open memory block to calculate a read count subject to the read operation.
Disclosed is an interface circuit and a semiconductor device including the same. The interface circuit may include a data pad, a first driving circuit connected between the data pad and a first supply node, and configured to adjust a first resistance value applied between the data pad and the first supply node according to termination modes and selectively drive the data pad with a first supply voltage, and a first tuning circuit connected between the first supply node and a first voltage supply terminal, and configured to tune the first resistance value according to the termination modes.
Disclosed is an image processor and an image processing system including the same. The image processor includes an analyzer configured to generate quantified characteristic values of noise reflected in a captured image based on image values corresponding to the captured image, and a discriminator configured to determine whether the noise has occurred in the captured image based on the characteristic values.
A method for fabricating a semiconductor device includes: forming an isolation layer that defines a plurality of active regions over a substrate; forming a bit line stack over the substrate; forming a main hard mask layer over the bit line stack; forming a plurality of first sacrificial mask layers over the main hard mask layer; forming a plurality of second sacrificial mask layers overlapping with both side ends of the first sacrificial mask layers over the first sacrificial mask layers; forming a main hard mask layer pattern by using the first and second sacrificial mask layers as barriers and etching the main hard mask layer; and forming a bit line structure by using the main hard mask layer pattern as a barrier and etching the bit line stack.
A memory controller includes a command/address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command/address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.
A memory device including: a first stack structure including conductive layers stacked along a first direction, the first stack structure having a stepped structure defined by end portions of the conductive layers; contact plugs respectively connected to the conductive layers, the contact plugs extending along the first direction, the contact plugs extending to the inside of the first stack structure; and dummy layers located between the contact plugs.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
95.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating a semiconductor device includes forming a stack body including a plurality of recess target layers over a lower structure; forming sacrificial isolation openings in the stack body; forming sacrificial isolation layers in the sacrificial isolation openings; forming sacrificial vertical openings having bottom surfaces disposed at a lower level than bottom surfaces of the sacrificial isolation openings in the stack body between the sacrificial isolation layers; forming preliminary horizontal layers by recessing the recess target layers through the sacrificial vertical openings; forming sacrificial pillar structures that fill the sacrificial vertical openings; forming cell isolation openings by removing the sacrificial isolation layers; forming horizontal layers by trimming the preliminary horizontal layers through the cell isolation openings; and forming cell isolation layers that fill the cell isolation openings.
A memory device includes: a plurality of memory cells; a peripheral circuit for performing a program operation of storing data in the plurality of memory cells; and a program operation control circuit for, in the program operation, controlling the peripheral circuit to perform a foggy program operation of increasing a threshold voltage of the plurality of memory cells to a threshold voltage corresponding to any one state among an erase state and first to sixth foggy program states, and perform a fine program operation of increasing the threshold voltage of the plurality of memory cells to any one state among the erase state and first to fifteenth fine program states.
A semiconductor device includes a semiconductor substrate formed to include a first active region and a second active region, first and second dielectric layer disposed over the first and second active regions, first and second gate electrode disposed over the first and second dielectric layers, respectively; and wherein the first and second active region have different impurity doping types from each other, and fluorine concentration of the first dielectric layer is higher than fluorine concentration of the second dielectric layer.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Embodiments of the present disclosure relate to a monitoring circuit and a semiconductor device, and particularly, to a monitoring circuit including an oscillation circuit configured to generate an oscillation signal having a rising characteristic or a falling characteristic according to a threshold voltage level and a counter configured to count the number of rises or the number of falls of the oscillation signal, and a semiconductor device including the monitoring circuit.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
H01L 21/66 - Testing or measuring during manufacture or treatment
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
99.
SEMICONDUCTOR DEVICE CONFIGURED TO STORE PARITY DATA AND METHOD OF OPERATING THE SEMICONDUCTOR DEVICE
A semiconductor device includes a memory cell array and a plurality of read and write circuits. The memory cell array includes a plurality of planes. Any one of the read and write circuits generates parity data based on data sequentially received from a controller through a channel.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
An image signal processor includes a bit extension processor configured to generate extension data by expanding, by a first number of bits, a number of bits of input data including a Bayer image and a white image, and an output circuit configured to adjust, upon receiving the extension data, the first number of bits to a second number of bits, to generate output data.
G06T 3/4038 - Image mosaicing, e.g. composing plane images from plane sub-images
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
