Embodiments of the present disclosure relate to a data storage device that manages a spare region in each memory area to be maintained at a predetermined ratio or size or higher based on defect information of each memory area, and an operation method of the data storage device. According to the embodiments of the present disclosure, there may be provided an operation method of a data storage device, the method comprising classifying a plurality of memory areas provided in a memory device into a plurality of storage areas, managing the plurality of storage areas by mapping a logical address externally received to each of the plurality of storage areas, monitoring defect information generated in a memory area corresponding to each of the plurality of storage areas, and remapping the logical addresses for each of the plurality of storage areas based on the defect information.
A memory device includes a memory cell array, a page buffer, and a bit line operation controller. The memory cell array includes a memory cell. The page buffer being connected to the memory cell through a bit line. The page buffer configured to perform a sensing operation of sensing program data stored in the memory cell. The bit line operation controller configured to control the page buffer to perform a page buffer under drive operation before the sensing operation. The page buffer including a latch circuit, a sense amp circuit, and a page buffer control switch. The latch circuit configured to store the program data. The sense amp circuit configured to perform the sensing operation. The page buffer control switch configured to connect the bit line and the sense amp circuit to each other.
A semiconductor device includes a base chip configured to, during a scan operation, connect a first signal path and a second signal path to a first voltage source, a first memory chip configured to, during the scan operation, connect the first signal path to a second voltage source to generate a first fail result signal and output the first fail result signal to the base chip when a chip identification (ID) has a first combination, and a second memory chip configured to, during the scan operation, connect the second signal path to a third voltage source to generate a second fail result signal and to output the second fail result signal to the base chip when the chip ID has a second combination.
G11C 29/44 - Indication or identification of errors, e.g. for repair
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
An interface system may include a first interface device and a second interface device. The first interface device may include a first buffer. The second interface device may include a second buffer. The first interface device may compare a write pointer of the first buffer, which corresponds to the second interface device, with a read pointer of the first buffer, which corresponds to the first interface device, and update the read pointer, based on the comparison result. Each of the write pointer of the first buffer and the read pointer of the first buffer may include data bits indicating an address of the first buffer and a data bit indicating a reset signal. The first interface device may selectively update the read pointer according to the reset signal of the write pointer of the first buffer.
A method for forming a hole pattern includes forming a hard mask layer over an etch target layer; forming a first sacrificial pattern including a preliminary hole pattern over the hard mask layer; forming a first sacrificial spacer on an inner wall of the first sacrificial pattern; forming a second sacrificial pattern to gap-fill between the first sacrificial spacers; removing the first sacrificial pattern; forming second sacrificial spacers on both sidewalls of a pillar pattern which is formed of the first sacrificial spacer and the second sacrificial pattern; removing the second sacrificial pattern; forming a hard mask pattern by using the first and second sacrificial spacers as an etch barrier and etching the hard mask layer; and forming an etch pattern including a hole pattern by using the hard mask pattern as an etch barrier and etching the etch target layer.
A memory module may include: a battery; a plurality of devices including a first memory, a second memory, and a controller; and a power management integrated circuit configured to adjust a level of a battery power, received from the battery, and configured to supply a power supply voltage to each of the plurality of devices.
A display device is provided to include a substrate, a plurality of sub-pixels supported by the substrate and configured to emit light of different colors, a transparent layer disposed in the plurality of sub-pixels, a first protective layer disposed on the transparent layer, and a second protective layer disposed on the first protective layer, wherein a sub-pixel of the plurality of sub-pixels includes a light-emitting area which emits light, and a non-light-emitting area around the light-emitting area, and the first protective layer and the second protective layer are structured to expose the transparent layer.
Disclosed is a memory including a plurality of planes, and a plurality of microcontrollers, and during a specific operation of a selected plane, among the plurality of planes, at least two microcontrollers, among the plurality of microcontrollers, perform distributed execution of control operations on the selected plane.
A memory controller may include an interface, and an input/output driving circuit. The interface may be configured to transfer data between a host and a memory device. The input/output driving circuit may include a pull-down driver connected between a pad and a ground node, and a gate control logic connected between a pad voltage terminal and a first supply voltage terminal. The pull-down driver includes a plurality of NMOS transistors and the gate control logic includes a plurality of PMOS transistors.
A semiconductor device may include a substrate including a chip region and a sealing region surrounding the chip region; first bonding pads located on the substrate; second bonding pads located in the chip region and bonded to the first bonding pads; an interlayer insulating layer located on the first bonding pads; and contact rings located in the sealing region, extending through the interlayer insulating layer and connected to the first bonding pads, and each having a closed curve shape.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
11.
DATA STORAGE DEVICE WHICH ERASES BY GROUPING MEMORY BLOCKS AND METHOD OF OPERATING THE SAME
A data storage device may include a storage medium including a plurality of memory blocks; and a storage controller configured to combine memory blocks that are simultaneously accessed among the plurality of memory blocks to manage the combined memory blocks as a superblock. The storage controller erases a preliminary superblock for a subsequent write operation during a write time corresponding to a write operation mode of a selected superblock performing a write operation. The storage controller classifies memory blocks of the preliminary superblock into a plurality of erasing units each including a set number of the memory blocks, the plurality of erasing units being sequentially erased with a uniform erase interval between erase operations of the plurality of erasing units.
An electrostatic discharge circuit may include a control voltage generation circuit, an electrostatic detection circuit, a driving control circuit and a discharge driving circuit. The control voltage generation circuit may generate first to third control voltages through a division operation on a supply voltage. The electrostatic detection circuit may set a first setup voltage based on the first control voltage, and detect static electricity transferred through the first setup voltage. The driving control circuit may set a second setup voltage based on the second control voltage, and generate a driving control signal. The discharge driving circuit may set a third setup voltage based on the third control voltage, and perform a discharge operation on static electricity.
A storage device comprising: a memory, and a controller configured to perform a migration operation of migrating kept data units stored in the memory to an external storage device, wherein the controller selects updated data units, among N data units included in a kept data group for which an update check request has been made, by determining whether each of the N data units included in the kept data group has been updated when receiving an update check request for the plurality of kept data groups each comprising N kept data units, performs a selection operation of storing the updated data units in an update cache, predicts a kept data group for which an update check request is to be made next by analyzing the N data units, and performs a selection operation on the kept data group for which the update check request is to be made next.
A memory system includes a non-volatile memory device and a performance manager. The performance manager activates a plurality of sub-controllers according to a setting of a host device, allocates memory regions respectively to the plurality of sub-controllers, the memory regions being included in the non-volatile memory device, and determines, according to maximum performance values and a size ratio of the memory regions, credit sets to be allocated respectively to the plurality of sub-controllers.
A semiconductor device may include: a first electrode layer including a base and a plurality of protrusions protruding from the base; a switching layer extending along profiles of the plurality of protrusions; an oxygen reservoir layer located on the switching layer; a second electrode layer located on the oxygen reservoir layer; and an air gap located between the plurality of protrusions.
Electronic device and operation method therefor are provided. The electronic device is operable to communicate with another electronic device. The operation method comprises the following operations. A forward error correction (FEC) frame to be transmitted via a plurality of active lanes of a link is obtained, wherein the FEC frame includes a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block. The FEC frame is distributed over the lanes of the link in one of a plurality of different lane distribution orders selectively based on number of active lanes included in the plurality of active lanes. The FEC frame is transmitted over the plurality of lanes of the link to another electronic device.
A method for operating a storage system, a storage device and a non-transitory storage medium thereof are provided. The method comprises following steps. By a controller of the storage system, information associated with respective load levels of a plurality of flash transition layers (FTLs) of the storage system is detected. By the controller, sizes of over-provisioning (OP) portions associated with the plurality of FTLs of the storage system individually are adjusted dynamically based on the detected information associated with the respective load levels of the plurality of FTLs.
A receiver circuit may include a differential buffer configured to receive a signal through a first terminal and a signal through a second terminal, and output a first signal and a second signal which is a complementary signal of the first signal; a control circuit configured to generate a pass enable signal in response to the first signal and the second signal; and a pass circuit configured to output the first signal and the second signal as a first reception signal and a second reception signal, respectively, when the pass enable signal is activated, and fix logic levels of the first reception signal and the second reception signal when the pass enable signal is deactivated.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
According to one embodiment, a magnetic memory device includes first, second, third, fourth, fifth, sixth and seventh non-magnetic layers, and first, second and third ferromagnetic layers. The first ferromagnetic layer, the second non-magnetic layer, the second ferromagnetic layer, the third non-magnetic layer, the third ferromagnetic layer, the fourth non-magnetic layer, the fifth non-magnetic layer, the sixth non-magnetic layer, and the seventh non-magnetic layer are provided in this order above the first non-magnetic layer. The first non-magnetic layer includes silicon. The fourth non-magnetic layer includes magnesium and oxygen. The fifth non-magnetic layer includes molybdenum. The sixth non-magnetic layer includes hafnium. The seventh non-magnetic layer includes ruthenium.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
A ring voltage controlled oscillator includes an inverter chain circuit including inverters disposed in stages, the inverters being coupled to each other in a chain form, and a level shift circuit configured to receive an output signal from the inverter chain circuit to output a level-shifted final output signal. The level shift circuit includes an output inverter including a PMOS transistor and an NMOS transistor, coupled in series between a power supply terminal and a ground voltage terminal, and a common mode voltage providing circuit configured to provide a common mode voltage to the output signal from the inverter chain circuit to generate an intermediate output signal, the common mode voltage being provided in different magnitudes depending on transistor corners of the NMOS transistor and the PMOS transistor. The output inverter receives and inverts the intermediate output signal to generate the level-shifted final output signal.
Embodiments of the present disclosure provide shared package balls for supplying a signal to a semiconductor package including a plurality of semiconductor chips, and provide a method capable of driving the plurality of semiconductor chips using the shared package balls while reducing the number of package balls even when the number of semiconductor chips included in the semiconductor package is increased.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G06F 11/22 - Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
G06F 11/273 - Tester hardware, i.e. output processing circuits
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
The image sensing device includes a plurality of color filters, and a grid structure disposed between the color filters and configured to prevent optical crosstalk between adjacent color filters. The grid structure includes a first capping layer structured to define and to cover a space filled with air to form an air layer, and including a plurality of holes; and a second capping layer disposed at an outer surface and an inner surface of the first capping layer and configured to fill the plurality of holes.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
A semiconductor memory device, and a manufacturing method of the semiconductor memory device, includes a peripheral transistor, a first insulating layer covering the peripheral transistor, a source layer on the first insulating layer, and a stack structure on the source layer. The semiconductor memory device also includes a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor. The stack structure includes a stepped structure including a step side surface and a step top surface. The peripheral contact structure is in contact with the step side surface.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A semiconductor memory device may include a memory cell array circuit and a word line driving circuit. The memory cell array circuit may be connected with a plurality of word lines to store data in a program operation. The word line driving circuit may drive a selected word line among the word lines using a program voltage in the program operation. The word line driving circuit may drive each of non-selected word lines adjacent to the selected word line using a step pass voltage including at least two step voltages.
A memory device includes a target memory block and a peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises toward a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.
Disclosed is an image sensor including a first sub-pixel array including a plurality of first pixel groups, which are respectively coupled to a plurality of first readout lines extending in a first direction and are adjacent to one another in a second direction intersecting the first direction; and a plurality of first switches suitable for selectively coupling a plurality of first floating diffusion nodes included in the plurality of first pixel groups, based on a plurality of first control signals.
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
H04N 23/10 - Cameras or camera modules comprising electronic image sensorsControl thereof for generating image signals from different wavelengths
H04N 25/778 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
27.
MEMORY CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLER
A memory controller may store data in the nonvolatile memory device or read data from the nonvolatile memory device based on an external request; and schedule, based on appearance frequency of a logical address included in the external request, processing performance of a processing operation for the external request and an internal management operation for the nonvolatile memory device.
A semiconductor chip includes a command address input circuit configured to generate a rising command address and a falling command address by receiving an external command address and configured to output the rising command address and the falling command address to a through electrode, and a test circuit configured to generate a detection signal by latching a remaining one of the rising command address and the falling command address as any one of the rising command address and the falling command address and configured to detect a fail in the transmission of the rising command address and the falling command address by detecting the logic level of the detection signal.
An error correction circuit includes a syndrome generation circuit configured to generate a first odd syndrome, a first even syndrome, and a second syndrome based on data. The error correction circuit also includes a location information generation circuit configured to generate odd location information and even location information, based on the first odd syndrome, the first even syndrome, and the second syndrome. The error correction circuit further includes a correction data generation circuit configured to check and correct an error that is included in a first odd-numbered symbol included in the data and an error that is included in a first even-numbered symbol included in the data, based on the first odd syndrome, the first even syndrome, the odd location information, and the even location information.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
In a method of manufacturing a semiconductor device, a bulk substrate includes a plurality of semiconductor chip regions and a scribe lane region between the semiconductor chip regions. A lower dicing inducer having a first depth is formed in the scribe lane region of the bulk substrate. A dummy layer is formed on the scribe lane region of the bulk substrate. The dummy layer includes at least one upper dicing inducer. A passivation layer is formed on the dummy layer. The passivation layer is etched to form a recess in the passivation layer. A backside of the bulk substrate is grinded to generate cracks along at least one of a boundary of the lower dicing inducer, a boundary of the upper dicing inducer, a boundary between the bulk substrate and the dummy layer and a boundary of the recess. The semiconductor chip regions are singulated by the cracks.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
A storage device may receive, from a host, one or more write commands for writing a plurality of first data units and a plurality of second data units, obtain a start logical address and a size of each of the plurality of first data units and a start logical address and a size of each of the plurality of second data units from the one or more write commands, and write at least a part of the plurality of first data units and the plurality of second data units to the memory based on the start logical address and the size of each of the plurality of first data units and the start logical address and size of each of the plurality of second data units.
A semiconductor device includes: a plurality of pairs of tile regions arranged in a first direction and a second direction crossing the first direction; a first switching region disposed on a first side of the first tile region in the first direction and disposed beside a second sub-region of the first tile region; a first conductive line extending in the first direction to cross the first switching region and tile regions, and electrically connected to the first switching region; a second conductive line extending in the second direction to cross each pair of tile regions and the second switching region, and electrically connected to the second switching region; and a memory cell disposed in an intersection region between the first conductive line and the second conductive line in a third direction that is perpendicular to the first and second directions.
Provided is a memory device and a method of operating the same. The memory device includes a memory block including a plurality of memory cells, a source line driver configured to apply an erase voltage to a source line of the memory block during an erase operation, a page buffer group configured to apply the erase voltage to bit lines of the memory block during the erase operation, a voltage generating circuit configured to generate a select line voltage that is applied to a select line of the memory block during the erase operation, and control logic configured to control the source line driver, the page buffer group, and the voltage generating circuit to perform a suspend operation including suspending the erase operation in response to a suspend command.
Provided herein is a memory device and a method of manufacturing the memory device. The method of manufacturing a memory device includes forming a stacked body including first and second material layers on a lower structure, forming first openings passing through the stacked body, filling the first openings with preliminary contact plugs, respectively, forming, on the stacked body, a stepped structure including steps respectively corresponding to the preliminary contact plugs, forming second openings passing through respective steps of the stepped structure and open at least portions of the first openings, respectively, at different depths, exposing side surfaces of the second material layers by removing respective portions of the preliminary contact plugs adjacent to respective first sides of the first openings through the second openings, and forming the stacked body having a reverse step structure by removing exposed portions of the second material layers.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
35.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Provided herein may be a semiconductor device and a method of manufacturing the same. The semiconductor device may include a substrate including a first region and a second region, a transistor including a gate insulating layer and a gate electrode that are stacked over the first region of the substrate, a first diode, at least a portion of the first diode being formed in the second region of the substrate, an insulating layer disposed on the substrate, a second diode disposed in the insulating layer to be spaced apart from the substrate, and interconnections connected to the first diode, the second diode, and the gate electrode, respectively.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
36.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device may include a gate structure including conductive layers and insulating layers that are alternately stacked; support structures respectively located at vertices of a polygon defined on an upper surface of the gate structure and each support structure including a pillar extending through the gate structure and protrusion portions protruding from the pillar toward the conductive layers; and a contact structure extending through the gate structure inside the polygon and electrically connected to a first conductive layer of the conductive layers, wherein the protrusion portions may include first protrusion portions in contact with the contact structure and second protrusion portions located below the contact structure.
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
37.
SEMICONDUCTOR DEVICE AND OPERATING METHOD USING THE SAME
An operating method of a semiconductor device may include a write command reception step of receiving a write command, a pre-selection result determination step of determining whether a memory cell in which data are to be stored is a fail, and a write operation completion step of storing the data in the memory cell normally when the memory cell is determined to be normal.
Provided herein is a memory device and a method of manufacturing the memory device. The memory device includes a channel layer extending in a first direction, a tunnel isolation layer extending in the first direction and surrounding the channel layer, a first charge trap layer surrounding a portion of the tunnel isolation layer, a second charge trap layer surrounding the first charge trap layer, and a blocking layer surrounding the second charge trap layer, wherein the second charge trap layer is configured to trap more charges than the first charge trap layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
39.
MEMORY SYSTEM FOR PROCESSING WRITTEN DATA BY ZONE AND METHOD OF OPERATING THE SAME
A memory system may include a memory device including a plurality of memory regions and a memory controller configured to control the memory device and allocate some of the plurality of memory regions based on an allocation request of the memory device, the allocation request being provided from an external device. The memory controller is configured to perform a write request provided from the external device to at least one of the allocated memory regions, and monitor a size of written data in the at least one of the allocated memory regions based on the write request. When an error is detected in a first memory region among the allocated memory regions while performing of the write request of the external device, the memory controller is configured to determine whether to maintain the allocation of the first memory region.
A memory device includes a base die and a plurality of core dies stacked over the base die. The base die includes a first base scan control circuit connected to a first node connected to a first through via included in a first column and a second base scan control circuit connected to a second node connected to a second through via included in a second column. The first base scan control circuit sets the first node at a floating state when the first column is selected in a test mode and drives the first node when the second column is selected during the test mode.
A neural network architecture includes a plurality of processing-in-memory (PIM) devices configured to perform multi-head attention for transformer model. Each of the plurality of PIM devices includes a plurality of memory banks configured to store key vectors and value vectors that are used as input data of the multi-head attention, and a plurality of processing units corresponding to the plurality of memory banks and configured to perform the multi-head attention via the transformer model using the key vectors and the value vectors. The plurality of memory banks are configured to store the key vectors in a first manner and store the value vectors in a second manner that is different from the first manner.
A memory device, and methods of manufacturing and operating the memory device, include alternately stacked interlayer insulating layers and conductive layers, a vertical hole configured to pass through the alternately stacked conductive layers and interlayer insulating layers, first blocking layers formed along the interlayer insulating layers exposed through the vertical hole, and second blocking layers formed along the conductive layers exposed through the vertical hole, with each second blocking layer having a thickness greater than that of each of the first blocking layers. The memory device also includes charge trap layers formed on the same layer as the interlayer insulating layers, and surrounded by the first and second blocking layers, a tunnel insulating layer formed along inner walls of the second blocking layers and the charge trap layers, and a channel layer formed along an inner wall of the tunnel insulating layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory system includes a memory device including a plurality of planes each including a plurality of memory blocks; and a memory controller for controlling the memory device to perform an operation on target blocks among the plurality of memory blocks, to store, in a replacement block, data stored in a bad block, on which the operation fails among the target blocks, and control the memory device to temporarily store, in a backup block, data stored in the other blocks except the bad block among the target blocks according to a number of free blocks included in the memory device.
A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A semiconductor device and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a stacked structure including a plurality of conductive patterns and a plurality of insulating patterns alternately stacked on each other, a cell plug passing through the stacked structure, a select plug coupled to the cell plug, and a select pattern surrounding the select plug, wherein the select pattern includes a first conductive portion and a second conductive portion covering a sidewall and a top surface of the first conductive portion, and wherein the conductive patterns, the first conductive portion, and the second conductive portion include different materials.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
An embodiment provides: a composition for manufacturing a semiconductor device, comprising acetylene and a solvent for dissolving the acetylene therein, the solvent being at least one selected from the group consisting of triethyl phosphate, trimethyl phosphate, tris(N,N'-tetramethylene)phosphonic acid triamide, and γ-butyrolactone; a semiconductor device manufacturing apparatus comprising the composition for manufacturing a semiconductor device; and a method for manufacturing a semiconductor device by using the composition for manufacturing a semiconductor device.
A semiconductor device may include a read disturb reduction circuit, a first selection switch that is turned on based on a bit line selection signal, a second selection switch that that is turned on based on a word line selection signal, a memory cell electrically connected between the first selection switch and the second selection switch, a first bias voltage generation circuit configured to provide a first bias voltage to the memory cell through the first selection switch, a second bias voltage generation circuit configured to provide a second bias voltage to the memory cell through the first selection switch, a third bias voltage generation circuit configured to provide a third bias voltage to the memory cell through the second selection switch, and a connection switch configured to electrically connect or separate the read disturbance reduction circuit and the second selection switch.
Image sensing devices are disclosed. In an embodiment, an image sensing device includes a pixel array including a plurality of unit pixels. Each of the unit pixels includes a plurality of subpixels. Each of the plurality of subpixels includes a first isolation layer disposed in an edge region of a corresponding subpixel, and a second isolation layer extending toward a center of the corresponding subpixel from the first isolation layer. The second isolation layer includes: a first disposed in a substrate; and a second layer disposed on the first layer and including a material with a lower refractive index and a lower light absorption rate than the first layer.
A memory system include a memory device including a plurality of sequential areas in which data corresponding to consecutive logical addresses received from a host device are stored, and a memory controller for receiving, from the host device, a write request including the data and the logical addresses, grouping the plurality of sequential areas into a plurality of sequential area groups based on a program speed corresponding to each of the plurality of sequential areas, and mapping each of the logical addresses to one of the plurality of sequential area groups based on an access number and an access time of the data.
A semiconductor device includes: a first row line extending in a first direction; a first column line extending in a second direction that intersects the first direction; a first memory cell connected between the first row line and the first column line; a second column line located above the first column line and extending in the second direction; and a first resistance pattern located between the first column line and the second column line.
Disclosed are highly integrated memory cells and a semiconductor device including the highly integrated memory cells. The semiconductor device includes a first pillar and a second pillar spaced apart from each other by a shield trench, each pillar including an inner side that defines inner walls of the shield trench and an outer side that faces the inner side; a shield gate formed in the shield trench; a first main gate formed on the outer side of the first pillar; a second main gate formed on the outer side of the second pillar; a bit line formed on lower portions of the first and second pillars; and a capacitor formed on an upper portion of each of the first and second pillars.
A semiconductor device, and a method of manufacturing the semiconductor device, includes a transistor including a gate insulating layer and a gate electrode stacked on a substrate. The semiconductor device also includes a diode including a diode electrode, wherein the diode electrode is on the substrate, extends from the gate electrode, and is electrically connected to the gate electrode. The semiconductor device further includes a first plug physically and electrically connected to the diode electrode.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 99/00 - Subject matter not provided for in other groups of this subclass
53.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a first semiconductor structure including a peripheral circuit and an interconnection structure electrically connected to the peripheral circuit, a second semiconductor structure, a bonding layer positioned between the first and second semiconductor structures, a bonding pad electrically connected to the interconnection structure, the bonding pad extending into the bonding layer, and a contact plug extending into the bonding layer through the second semiconductor structure, wherein the contact plug is electrically connected to the bonding pad.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
54.
FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD OF FERROELECTRIC MEMORY DEVICE
The present disclosure relates to a ferroelectric memory device and a method of manufacturing the ferroelectric memory device. The ferroelectric memory device includes a dielectric layer including a plurality of ferroelectric areas alternately arranged with a plurality of non-ferroelectric areas in a first direction, the dielectric layer having a tubular structure, a channel layer extending in the first direction on an inner wall of the dielectric layer, and a gate stack structure including a plurality of conductive layers surrounding the plurality of ferroelectric areas of the dielectric layer, and wherein the plurality of conductive layers are spaced apart in the first direction.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A memory system may include a storage device, a buffer memory and a memory controller. The buffer memory may include a first portion and a second portion. The memory controller may detect a set event, store external data in the first portion before the event is detected, and store the external data in the second portion after the event is detected. The external data is associated with a read request or a write request from an external device.
Provided herein may be a data storage device. A memory device may include a plurality of memory cells; and an operation controller configured to control a word line controller and a bit line controller so that a normal write operation of applying a write voltage corresponding to a target state that is one of a set state or a reset state to the plurality of memory cells is performed, and a rewrite operation is selectively performed based on a result of the normal write operation. The rewrite operation may be an operation of providing, to the plurality of memory cells, a select voltage, having a polarity opposite to a polarity of the write voltage corresponding to the target state, and providing the write voltage corresponding to the target state.
An integrated circuit includes an ECC encoder circuit configured to operate an H matrix on transmission data, to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity to detect and correct an error in the reception data. A data portion of the H matrix is divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group. The group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted.
The image sensing device includes a photoelectric conversion region including impurities of a first type in a semiconductor substrate; a well region including impurities of a second type opposite to the first type and disposed over the photoelectric conversion region in the semiconductor substrate, the well region being in contact with the photoelectric conversion region in the semiconductor substrate; a floating diffusion region located in the well region; and a transfer gate disposed in the semiconductor substrate and coupled between the photoelectric conversion region and the floating diffusion region to transmit photocharges from the photoelectric conversion region to the floating diffusion region. The transfer gate includes a recess gate formed in a recess etched into the semiconductor substrate and a gate insulation layer disposed between the recess gate and the semiconductor substrate. The gate insulation layer has a varying thickness based on a distance to the floating diffusion region.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
60.
VERTICAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE VERTICAL SEMICONDUCTOR DEVICE
A vertical semiconductor device includes: a lower structure; a multi-layer stack structure including a source layer formed over the lower structure and gate electrodes formed over the source layer; a vertical structure penetrating the multi-layer stack structure and including a channel layer insulated from the source layer; a vertical source line spaced apart from the vertical structure to penetrate the multi-layer stack structure and contacting the source layer; and a horizontal source channel contact suitable for coupling the source layer and the channel layer and including a first conductive layer and a second conductive layer that include different dopants.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
61.
MEMORY SYSTEM, MEMORY CONTROLLER, AND METHOD FOR OPERATING SAME
Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. Garbage collection is performed with regard to the memory device on the basis of a first amount of time and a second amount of time, the first amount of time being a period of time between triggering of first garbage collection and triggering of second garbage collection, and the second amount of time being an amount of time necessary to perform the second garbage collection. A ratio of the first amount of time to the second amount of time is determined as a target ratio value, and the second amount of time is determined to be equal to or longer than a minimum garbage collection operation time. Accordingly, efficient garbage collection can be performed, and the optimal time to perform garbage collection can be determined with regard to a configured performance drop value.
A semiconductor memory apparatus includes a plurality of bit lines, a plurality of page buffers, and a page buffer control circuit. The plurality of page buffers are each coupled with the plurality of bit lines and operate in response to a plurality of page buffer control signals. The page buffer control circuit generates the plurality of page buffer control signals to perform program and verification operations comprising a plurality of loops. The page buffer control circuit uses the plurality of page buffer control signals to simultaneously precharge bit lines coupled with page buffers, among the plurality of page buffers, corresponding to a plurality of verification levels corresponding to each of the plurality of loops.
A duty cycle correction circuit includes a phase adjustment circuit, a divider circuit, a phase difference detection circuit, and a duty control circuit. The phase adjustment circuit adjusts a duty cycle of a first input clock signal according to a plurality of control codes to generate a duty corrected clock signal. The divider circuit divides the duty corrected clock signal to generate a plurality of multi-phase clock signals. The phase difference detection circuit detects phase differences between the plurality of multi-phase clock signals to generate detection signals. The duty control circuit detects a bang-bang state of the duty corrected clock signal in accordance with the detection signals, changes values of the plurality of control codes by a first unit in accordance with the detection signals until the bang-bang state is detected, and adjusts the value of the plurality of control codes by a second unit smaller than the first unit when the bang-bang state is detected.
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
64.
OSCILLATOR WITH LEAKAGE CURRENT COMPENSATION FUNCTION
An oscillator includes a relaxation oscillating circuit including a first resistor-capacitor (RC) circuit generating a first oscillation voltage at a first node and a second RC circuit generating a second oscillation voltage at a second node, and configured to output an oscillation voltage through an output line coupled to an output node, and a voltage averaging feedback circuit configured to receive a reference voltage and the oscillation voltage to output a control voltage through an output terminal. The relaxation oscillating circuit includes a leakage current compensation circuit coupled to the output line and configured to provide a leakage compensation current to the output node.
H03B 5/04 - Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
H03B 5/24 - Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising resistance and either capacitance or inductance, e.g. phase-shift oscillator active element in amplifier being semiconductor device
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
65.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
A semiconductor device includes a peripheral circuit structure, a memory cell array disposed over the peripheral circuit structure, and a bonding structure disposed between the peripheral circuit structure and the memory cell array. The memory cell array includes a first stack structure including first interlayer insulating layers and first conductive patterns disposed alternately with each other in a first direction over the bonding structure, second conductive patterns separated from each other in a horizontal direction between the first stack structure and the bonding structure, each of the second conductive patterns comprising electrode portions spaced apart from in the first direction and a connection portion extending in the first direction to couple the electrode portions, a vertical channel passing through the first stack structure and the electrode portions of each of the second conductive patterns, and a separation insulating layer disposed between the second conductive patterns.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
A multichip package includes a substrate connected to a plurality of solder balls including a first solder ball, a first chip stacked over or on the substrate, a second chip stacked over or on the first chip and including a first overhang not supported by the first chip, and a support structure supporting the first overhang and connected to the first solder ball that provides an external electrical connection to the substrate for a voltage external to the substrate.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
Provided herein may be a distributed processing system and a method of operating the same. The distributed processing system may include a storage device, a plurality of computing nodes, and a shared memory device. The storage device may store a database including a plurality of tables. The plurality of computing nodes may generate a target map of the first table by applying a target function to a first table among the plurality of tables, and divide a second table among the plurality of tables into a plurality of partitions. The shared memory device may store the target map of the first table. The plurality of computing nodes may execute queries including a target operation using different partitions among the plurality of partitions of the second table and the target map.
G06F 16/27 - Replication, distribution or synchronisation of data between databases or within a distributed database systemDistributed database system architectures therefor
Provided herein may be an interface device and a method of operating the same. The interface device may include a first port configured to enable communication with a host, a second port configured to enable communication with the host, and a function manager including a plurality of variable functions that are selectively assignable to at least one of the first port and the second port.
H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
A leakage current detection circuit includes: a mirror circuit configured to copy a leakage current flowing through a node and generate a copy current in a copy node; an oscillation circuit including a charge storage unit, the oscillation circuit being connected to the copy node, charged with the copy current, and configured to generate an oscillation signal by charging and discharging the charge storage unit; and a calculation circuit configured to calculate an amount of the leakage current based on the oscillation signal.
A switching controller controlling communication between a processor included in an external device and a memory included in a storage device may pre-fetch memory data into a buffer memory inside the switching controller and provides the data to the processor of the external device based on a command input for a predetermined period.
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
72.
STORAGE DEVICE TRANSLATING LOGICAL ADDRESS ON THE BASIS OF SEQUENTIALITY OF NAMESPACE, AND METHOD THEREOF
A storage device may generate mapping information between a plurality of memory regions and one or more namespaces. The storage device may record information on empty memory regions among the plurality of memory regions in an empty table, and may determine empty memory regions to be mapped to a target namespace among the empty memory regions recorded in the empty table.
A semiconductor device includes at least two planes including a plurality of memory bank groups, each of the plurality of memory bank groups including a plurality of memory banks, a plurality of compressing circuits, each coupled to at least two memory banks, the at least two memory banks being included in the same plane, each of the plurality of compressing circuits compressing a plurality of data read from the at least two memory banks to output compressed data, at least one merge circuit receiving a plurality of compressed data from at least two compressing circuits and merging the plurality of compressed data to output merged data, and an output buffer circuit receiving a plurality of merged data and outputting the plurality of merged data to an external device, wherein each memory bank, among the at least two memory banks, is included in different memory bank groups.
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Republic of Korea)
Inventor
Kim, Sang-Koog
Kim, Bojong
Kim, Junyoung
Jeon, Hae-Chan
Abstract
A signal transmission control device may include a device layer including a conductive layer and a dielectric layer disposed on the conductive layer, and a conductive line disposed on the dielectric layer and extending across a first inverted split ring resonator (ISRR) and a second inverted split ring resonator (ISRR). The device layer may define the first ISRR and the second ISRR spaced apart from each other, and a signal transmission characteristic between a first end and a second end of the conductive line may be controlled by the first ISRR and the second ISRR.
A memory device according to an embodiment of the present disclosure includes a stack structure including a cell region and a contact region, a cell plug located in the cell region and including a channel layer, a support pillar located in the contact region and including a dummy channel layer, and a contact opening contacting the support pillar wherein a thickness of the dummy channel layer is greater than a thickness of the channel layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
76.
STORAGE SYSTEM IMPROVING ENCRYPTION INTEGRITY OF DATA AND OPERATING METHOD THEREOF
A storage system may include a first device including a transmission circuit configured to generate encrypted first information by encrypting first information of a transmission target message, to generate encrypted second information by encrypting second information of the transmission target message, and to transmit the encrypted first information and the encrypted second information, and a second device including a reception circuit configured to decrypt the encrypted first information by receiving the encrypted first information and the encrypted second information from the first device and to store the first information that has been decrypted and the encrypted second information in a memory device.
The method may include forming a photoresist over a first structure, forming a photoresist pattern by removing a portion of the photoresist through a mask including a mask opening, wherein the mask opening includes a light-blocking pattern and a light-transmitting area, forming, by etching the first structure according to the photoresist pattern, a target opening corresponding to the mask opening and an auxiliary pattern corresponding to the light-blocking pattern of the mask opening, wherein the target opening is formed to have a first depth, wherein the auxiliary pattern is formed to have a second depth that is shallower than the first depth, and wherein the auxiliary pattern is located in the target opening and is implemented as a part of the first structure, and forming an alignment key by removing the auxiliary pattern from within the target opening.
A semiconductor memory device includes a chip formed in a cell array region of a substrate and including a plurality of structures and a plurality of channel pillars formed through the plurality of structures; and a plurality of dummy structures, at least one alignment key, and a first plurality of dummy pillars formed in an alignment area of a scribe lane of the substrate, the scribe lane configured to facilitate separation of plurality of chips. The at least one alignment key may extend through at least one of the plurality of dummy structures and extend into the substrate. The first plurality of dummy pillars is formed through the plurality of dummy structures and is formed around the alignment key.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
79.
MEMORY SYSTEM INCLUDING FIRMWARE AND AN OPERATION METHOD THEREOF
A memory system includes a memory device and a controller. The memory device includes firmware distributed and stored in plural locations. The controller is configured to read the firmware from a different location selected among the plural locations whenever the controller loads the firmware distributed and stored in the memory device.
Embodiments of the present disclosure update a level value indicating a read voltage according to a fail bit detected during a read operation for a memory and provide the updated level value to the memory before transmitting a read command to allow a read operation to be performed according to the read voltage indicated by the updated level value, thereby enhancing the accuracy of the read operation through a read operation suitable for the characteristics for each storage area of the memory and enhancing the operation performance and reliability of the memory.
KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION (Republic of Korea)
Inventor
Jo, Munki
Kim, Kyung Hye
Roh, Heejoong
Kim, Seoung Bum
Cho, Hansam
Baek, Insung
Jo, Yongwon
Bae, Jinsoo
Kim, Sungsu
Abstract
A learning-based semantic segmentation method and apparatus for semiconductor metrology are disclosed. The method includes performing, using a processor, a pre-training stage to determine initial weights among nodes within a neural network model by pre-training the neural network for process-specific semantic segmentation; and performing, using a processor, a fine-tuning stage to classify an input wafer TEM or SEM image into at least one object of interest based on pre-trained weights, and to assign a weight (α) greater than one ( ) to pixels corresponding to boundaries separating the objects of interest and a weight one (1) to other pixels corresponding to regions distinct from the boundaries using a loss function (LBF).
G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
G06V 10/34 - Smoothing or thinning of the patternMorphological operationsSkeletonisation
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 10/774 - Generating sets of training patternsBootstrap methods, e.g. bagging or boosting
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
82.
METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING AIR GAP
A method of forming a semiconductor device includes forming a plurality of first conductive patterns on a substrate. A block copolymer layer is formed between the plurality of first conductive patterns. A plurality of preliminary spacers and a by-product pattern are formed from the block copolymer layer. By removing the by-product pattern, an air gap is formed. By converting the plurality of spare spacers, a plurality of spacers is formed. A capping layer is formed covering the plurality of spacers and the air gap.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
83.
DATA AUGMENTATION METHOD AND APPARATUS FOR MACHINE LEARNING AND APPLICATIONS THEREOF
KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION (Republic of Korea)
Inventor
Kim, Kyung Hye
Roh, Heejoong
Jo, Munki
Kim, Seoung Bum
Cho, Hansam
Baek, Insung
Jo, Yongwon
Bae, Jinsoo
Kim, Sungsu
Abstract
Data augmentation methods and apparatus for machine learning, and utilization thereof, are disclosed. A computer-implemented method for data augmentation in electron microscope imaging, the method comprising: receiving, using a processor, an input image captured by an electron microscope; processing, using a processor, the input image to generate an augmented image dataset, the processing comprising: generating a first transformed image by converting an interior region of an object region of interest in the input image to a single color; generating a second transformed image by converting a region other than the object region of interest in the input image to a single color; and generating a third transformed image by modifying pixel positions exclusively within the interior region of the object region of interest in the input image; and outputting the augmented image dataset to train a machine learning model.
An SSD device comprises a first port linking up with a first host using a first link, a second port linking up with the first host or a second host using a second link, and a port mode controller controlling the first port and the second port to change an operating mode from a dual port mode, in which the first port and the second port operate independently of each other, to a single port mode, in which only the first port operates. The port mode controller controls the second port to reset the second link in a state where the first link is linked up.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
85.
STORAGE DEVICE, METHOD OF OPERATING THE SAME, AND COMPUTING SYSTEM INCLUDING THE STORAGE DEVICE
Storage devices, methods of operating storage devices, and computing systems including storage devices are disclosed. In an embodiment, a storage device may include a plurality of memory devices and a memory controller for controlling the plurality of memory devices to process a request of a host in accessing plurality of memory devices, wherein the memory controller is configured to allocate the plurality of memory devices to a plurality of functions, allocate a plurality of request slots allowed to process the request per unit time for each of the plurality of functions, determine idle request slots other than active request slots being used to process the request among the plurality of request slots allocated to each of the plurality of functions, and control an internal operation of the plurality of memory devices based on at least one target function including the idle request slots among the plurality of functions.
The present technology relates to an electronic device. According to the present technology, a storage device having an improved operation speed may include a nonvolatile memory device, a main memory configured to temporarily store data related to controlling the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device and the main memory under control of an external host. The main memory may aggregate and process a number of write transactions having continuous addresses, among write transactions received from the memory controller, equal to a burst length unit of the main memory.
A semiconductor device includes a substrate; and a plurality of sub-word line drivers, each of the sub-word line drivers including a plurality of transistors, wherein at least one of the plurality of transistors has a buried gate structure positioned in the substrate.
G11C 8/08 - Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 8/14 - Word line organisationWord line lay-out
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
H10B 99/00 - Subject matter not provided for in other groups of this subclass
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
88.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a substrate, a transistor including a gate electrode on the substrate and a junction in the substrate, a through via passing through the substrate through the junction and including a first portion that is in contact with the junction and a second portion extending from the first portion and having a width less than that of the first portion, and an insulating spacer surrounding the second portion of the through via.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/528 - Layout of the interconnection structure
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
89.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes: a peripheral circuit, a stack located over the peripheral circuit, a bonding pad located between the peripheral circuit and the stack, a probing pad located between the peripheral circuit and the stack and connected to the bonding pad, a contact plug extending through the stack and electrically connected to the peripheral circuit through the probing pad and the bonding pad, and a contact structure including a contact connect portion extending in a first direction, a first contact via protruding from the contact connect portion in a second direction intersecting the first direction, and a second contact via spaced apart from the first contact via and protruding from the contact connection portion in the second direction.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Data storage devices and operating methods that can improve a booting operation are disclosed. A storage device includes: a memory device including one or more boot partitions configured to store boot data for executing an operating system; and a memory controller coupled to the memory device and configured to perform, upon receiving power, a rebuild operation to restore first system data including active boot partition information associated with an activated boot partition among the one or more boot partitions and provide the active boot partition information to a host. Upon receiving, by the memory controller, from the host, a boot partition read request based on the active boot partition information, the memory controller transmits, to the host, the boot data stored in a boot partition corresponding to the active boot partition information.
A cleaner for an ionizer may include a communication interface, a cleaning member, a driver and a controller. The communication interface may be configured to communicate information with the ionizer. The cleaning member may be moved along a wire of the ionizer to remove and collect particles. The driver may be configured to drive the cleaning member. Further, the driver may recognize a starting of the cleaning member from a beginning spot of the wire, an arriving of the cleaning member at an ending spot of the wire, or a returning of the cleaning member to the beginning spot of the wire. The controller may control whole operations of the cleaner. The whole operations of the cleaner may include identifying states including the driving of the ionizer through the communication interface, removing the particles on the wire by driving the cleaning member through the driver, etc.
The present disclosure relates to a method of manufacturing a memory device. A method of manufacturing a memory device includes forming a peripheral circuit over a first substrate, forming a first source line over a second substrate, forming a memory cell array including gate lines, cell plugs extending through the gate lines, and bit lines electrically coupled to the cell plugs that protrude into the first source line, bonding the memory cell array to the peripheral circuit, and removing at least a portion of the second substrate.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
93.
STORAGE APPARATUS INCLUDING WORD LINE GROUPING DEVICE AND OPERATING METHOD THEREOF
A storage apparatus includes a memory device including a plurality of word lines; and a word line grouping device configured to group the plurality of word lines into a certain number of groups each serving as a memory block so that a read performance value, obtained by reading data of word lines included in a same group by using a representative read voltage, is satisfied with a set tolerance value.
A memory may include a plurality of word lines formed of N layers, M word lines being arranged in each layer, among the plurality of word lines, where each of N and M is an integer of 2 or more; a plurality of bit line pillars; and a plurality of memory cells disposed at intersections between the plurality of word lines and the plurality of bit line pillars, respectively. Among the plurality of word lines, two or more word lines of the plurality of word lines may be grouped and driven together.
A memory device includes an alignment data strobing signal generation circuit configured to generate an alignment data strobing signal from an internal clock signal when a read operation on a specific pseudo channel of a specific rank is performed based on a read identification signal and a read channel signal, and a core pipe configured to receive the alignment data strobing signal and output core data output from the specific pseudo channel, based on the alignment data strobing signal.
A semiconductor device may include a peripheral circuit comprising a plurality of transistors, a cell array and a contact array positioned adjacent to each other over the peripheral circuit, a bonding pad for electrically connecting the peripheral circuit with the cell array and the contact array, the bonding pad comprising first and second portions, wherein the first portion has a first width and is in electrical connection with at least one transistor of the peripheral circuit, wherein the second portion has a second width that is less than the first width of the first portion, and wherein a bonding via electrically connecting the bonding pad with the contact array or the cell array extends partially inside the first portion of the bonding pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
97.
SEMICONDUCTOR SYSTEM FOR DETECTING PROCESS VARIATION
A semiconductor device includes a comparison circuit configured to generate a flag signal by comparing a voltage level of a reference voltage with a voltage level of a process voltage after the start of a process variation detection operation and a process information generation circuit configured to generate a process detection signal that indicates process variation based on a counting detection signal that is generated based on the flag signal and based on timing of pulses included in a cycle signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G11C 8/18 - Address timing or clocking circuitsAddress control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
A semiconductor device includes a substrate; a channel layer over the substrate; a gate stack and a gate spacer pattern over the channel layer; an interlayer insulating layer covering the gate stack and the gate spacer pattern; and a contact pattern vertically passing through the interlayer insulating layer to be connected to the substrate. the contact pattern includes a contact plug; and a contact barrier layer surrounding a side surface of the contact plug. The contact barrier layer includes a protrusion portion protruding toward the channel layer in a horizontal direction.
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An image sensor based on an embodiment of the disclosed technology includes a photodiode formed in a pixel area of a substrate, a lens disposed in the pixel area of the substrate, a first reflector disposed in a separation area of the substrate that is arranged between adjacent pixel areas, and a light collection pattern disposed over the substrate.
A method of operating a storage device may include externally receiving a first target command of an administration command type, receiving a first data input/output command following the first target command, monitoring first data processing performance corresponding to the first data input/output command, and setting, based on a result of monitoring the first data processing performance, a priority related to response latency for outputting a processed result corresponding to a command of the administration command type.
