A method, system, and control for thermal shutdown of a storage device. The method and control determine that a temperature of the storage device is approaching a critical temperature; disable input power to the storage device upon determining that the temperature is approaching the critical temperature; when the input power to the storage device is disabled, power the storage device with auxiliary power; and under the auxiliary power, transfer data from a buffer in the storage device to a memory of the storage device.
A semiconductor die that operates using a first clock signal and a semiconductor die that operates using a second clock signal control transmission of data during operation periods using a mask circuit included in each semiconductor die to prevent or reduce the occurrence of data transmission and reception failure due to a difference in the clock signals between the semiconductor dies. Communication performance between the semiconductor dies is improved.
A memory device includes a memory cell array including a plurality of memory cells; a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including: a first operational circuit configured to perform a first operation according to a first sensing control signal; and a second operational circuit configured to perform a second operation according to a second sensing control signal; and an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
A storage device may include: a memory device for performing operations in response to a command received from an external host device; and a memory controller for measuring a performance time of the operations corresponding to the command, and generating a timeout signal in response to occurrence of a timeout. The memory controller may receive a request including timeout information for the command from the external host device, detect whether performance of the operations has been completed before a timeout reference time elapses based on the timeout information, and transmit, as a response to the command, the timeout signal generated corresponding to the timeout, in which the performance of the operations is not completed until before the timeout reference time elapses.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/34 - Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation
5.
SEMICONDUCTOR DEVICE WITH NANO SHEET TRANSISTOR AND METHOD FOR FABRICATING THE SAME
A semiconductor device comprises: a substrate including first and second buried source/drain layers; a first nano sheet stack including first nano sheets stacked in a direction vertical to the substrate; a second nano sheet stack including second nano sheets stacked in a direction vertical to the substrate; an isolation wall disposed between the first nano sheet stack and the second nano sheet stack; first gate covering portions of the first nano sheet stack and extending in a direction vertical to the substrate; second gate covering portions of the second nano sheet stack and extending in a direction vertical to the substrate; first common source/drain layers connected to end portions of the first nano sheets and to the first buried source/drain layers; and second common source/drain layers connected to end portions of the second nano sheets and to the second buried source/drain layers.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A semiconductor device may include a stack structure including first access lines and first insulating layers alternately stacked and extending in a first direction, first air gaps positioned to correspond to the first insulating layers and extending in the first direction along a sidewall of the stack structure, an electrode pillar extending through the stack structure, and second air gaps positioned to correspond to the first insulating layers and surrounding the electrode pillar.
A temperature sensor includes a variable voltage selection circuit configured to compare a first variable voltage having a voltage level corresponding to an internal temperature of a first region and a second variable voltage having a voltage level corresponding to an internal temperature of a second region to generate a selected variable voltage, when a selection pulse is generated, and a temperature code generation circuit configured to compare the selected variable voltage to a reference voltage to generate a temperature code whenever a comparison pulse is generated after a temperature code activation signal is activated.
In an embodiment of the present disclosure, processing order flags are set in flits transmitted and received between a host device and a data storage device, and in-order processing or out-of-order processing is controlled based on the processing order flags. Therefore, it is possible to provide measures capable of easily preventing occurrence of an error due to out-of-order processing of a flit while not degrading the efficiency of processing the flits transmitted and received.
A resistive memory cell may include a lower electrode, an upper electrode, a variable resistance layer and a charge bypass layer. The upper electrode may be substantially perpendicular to the lower electrode. The variable resistance layer may be interposed between the lower electrode and the upper electrode. The variable resistance layer may have a resistance changed by a conductive filament, which may include a reversibly generated oxygen vacancy, based on an electric field between the lower electrode and the upper electrode. When a voltage, which may be higher than a program voltage applied to the upper electrode, may be applied to the lower electrode, the charge bypass layer may include a plurality of discontinuous vertical grain boundaries and a plurality of horizontal grain boundaries connected between the discontinuous vertical grain boundaries.
An amplification circuit is configured to differentially amplify an input signal and a reference voltage to generate an output signal when a clock signal has a first logic level. The amplification circuit is configured to precharge the output signal when the clock signal has a second logic level. The amplification circuit is configured to adjust a current driving force that precharges the output signal based on the reference voltage.
A method for fabricating a semiconductor device includes forming a stack body including a preliminary horizontal layer over a lower structure; forming sacrificial slits in the stack body; forming pad isolation openings penetrating the stack body between the sacrificial slits; forming a pad level horizontal layer by recessing the preliminary horizontal layer of the stack body through the pad isolation openings; forming a first dielectric layer that covers the pad level horizontal layer; forming a second dielectric layer over the first dielectric layer; forming slit openings by removing the sacrificial slits; trimming the first dielectric layer through the slit openings so as to produce a trimmed first dielectric layer; trimming the pad level horizontal layer below the trimmed first dielectric layer; and forming slits that fill the slit openings.
A semiconductor device includes a plurality of active regions in a substrate; a gate trench formed in at least one of the plurality of the active regions, the gate trench including a first sidewall, a second sidewall opposite to the first sidewall, and a bottom sidewall; a growth promotion region formed on the first sidewall of the trench; a first gate dielectric layer formed on the first sidewall of the trench to contact the growth promotion region; a second gate dielectric layer formed on the second sidewall of the trench to be thinner than the first gate dielectric layer; and a gate electrode partially filling the trench over the first and second gate dielectric layers.
A controller includes at least one register configured to store a doorbell regarding a submission queue storing at least one request generated by a host, a first cache configured to store data corresponding to a first result of an operation performed in response to the at least one request, a second cache configured to store data corresponding to a second result of an operation performed in response to a read look ahead (RLA) request generated based on the at least one request, and a cache size manager configured to adjust a size of the second cache based on an update cycle of the doorbell and a change of a number of the at least one request corresponding to the doorbell.
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
15.
STORAGE DEVICE INCLUDING REPLAY PROTECTED MEMORY BLOCK (RPMB) HOST DEVICE ACCESSING THE RPMB, ELECTRONIC DEVICE INCLUDING STORAGE DEVICE AND HOST DEVICE, AND METHOD OF OPERATING THE SAME
Storage devices, host devices and electronic devices are disclosed. In an embodiment of the disclosed technology, an electronic device providing an improved security function may include a storage device including a replay protected memory block (RPMB), and a host device configured to provide a command protocol information unit (PIU) instructing the storage device to access the RPMB. The command PIU may include a basic header segment including a total extra header segment length field having a value other than 0 and an extra header segment including a host RPMB message.
G06F 3/06 - Digital input from, or digital output to, record carriers
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
An electronic device includes a count signal generation circuit configured to increase one of the values of a weak cell count signal and an active count signal by comparing a weak cell address with an adjacent address generated from a row address, when an active operation is performed. The electronic device also includes a target refresh control circuit configured to latch the adjacent address based on the values of the weak cell count signal and the active count signal and to output the latched adjacent address as a target address for a refresh operation based on a target refresh signal.
A memory device of a storage device may perform a test read of the memory device for each entry of a set of entries of an in-memory history read retry (HRR) table using a set of read thresholds corresponding to that entry. The memory device may identify an entry in the set of entries having a lowest failed bit count (FBC) obtained from the test read of each entry, and update the in-memory HRR table to have the identified entry with the lowest FBC be at a beginning of the in-memory HRR table. The memory device may also notify a memory controller coupled to the memory device to update an in-controller HRR table stored in the memory controller based on the update to the in-memory HRR table.
A semiconductor device may include a memory cell array including a plurality of memory cells arranged at locations where a plurality of word lines intersect with a plurality of bit lines, a row decoder configured to drive the plurality of word lines and a column decoder configured to drive the plurality of bit lines, wherein each of the plurality of memory cells has a set state or a reset state according to a normal write operation performed thereon, the plurality of memory cells include first memory cells in a specific area of the memory cell array, and the row decoder and the column decoder control a bit line and a word line coupled to a corresponding one of the first memory cells to increase a margin between the set state and the reset state of the corresponding first memory cell.
A semiconductor device includes a control circuit configured to deactivate a word line during an active operation during a test mode, generate a matching control signal and a sense amplifier drive signal, and activate the word line after a settling period during the test mode, and a sense amplifier configured to drive a bit line and an inverted bit line to a same voltage level based on the matching control signal during the mismatching cancellation operation, and sense and amplify a voltage difference between the bit line and the inverted bit line based on the sense amplifier drive signal when the word line is activated after the settling period during the test mode.
G11C 7/12 - Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Seo, Sanghyuk
Kim, Suhwan
Abstract
A transceiver connected to a specific channel via a channel connection node, the transceiver includes a transmitter driving a first node and a second node based on an input data signal in a transmission mode, the first node connected to the channel connection node; a receiver receiving a specific channel signal from the channel connection node and providing an output data signal based on the channel signal and an input differentiation signal in a reception mode, the input differentiation signal being generated based on at least one first output differentiation signal; and a switch network circuit connected between the second node and the channel connection node. The switching network circuit has a first circuit in the transmission mode and a second circuit in the reception mode, and provides at least one second output differentiation signal by differentiating the channel.
H04B 1/405 - Circuits using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency with multiple discrete channels
Image sensing devices are disclosed. In an embodiment, an image sensing device may include: a lower layer including a substrate and a plurality of photodetectors such as photodiodes; an upper layer disposed over the lower layer; a first meta-lens layer disposed over the upper layer and configured to focus incident light; and a second meta-lens layer disposed below the lower layer and configured to scatter or reflect the incident light toward the photodetector.
A memory chip includes a delay amount adjustment circuit configured to change a logic level combination of a code signal that adjusts a first delay amount for a strobe signal that is input or output through a conductive via based on a chip ID and a test mode signal after the start of a post-training operation and configured to generate an op-code signal by performing an arithmetic operation on the code signal and a data processing circuit configured to delay the strobe signal by a second delay amount that is based on the op-code signal, configured to latch internal data in synchronization with the strobe signal that is delayed by the second delay amount, and configured to output, as data, the internal data that are latched.
Disclosed is a memory device and a testing method thereof, and the memory device may include a memory circuit generating a plurality of test data in a test mode, a plurality of comparator groups generating first comparison signals based on part of the plurality of test data and part of a plurality of reference data, and generating second comparison signals based on remaining test data and remaining reference data, an error counter generating first symbol information indicating a first number of errors occurring in the part of the plurality of test data, based on the first comparison signals, and generating second symbol information indicating a second number of errors occurring in the remaining test data, based on the second comparison signals, and an error determiner generating a pass/fail signal indicating whether the memory circuit is normal, based on the first and second symbol information.
A method for fabricating a semiconductor device includes forming a stack body including a first region and a second region by sequentially forming a first stack, a recess target layer, and a second stack over a lower structure; forming sacrificial isolation layers in the first region; forming a plurality of vertical openings in the first region; forming a plurality of pad isolation openings in the second region; removing the first stack and the second stack from the first region and the second region through the vertical openings and the pad isolation openings; and forming a preliminary horizontal layer in each of the first region and the second region by recessing the recess target layer of the stack body.
An image sensing device may include a test control switch configured to selectively connect a test reset line for transmitting a test reset signal and a test image line for transmitting a first test image signal and a first correlated double sampling (CDS) circuit configured to receive the test reset signal through the test reset line and receive the first test image signal through the test image line. The first CDS circuit may receive a second test image signal through the test image line when the test control switch is closed.
H04N 25/616 - Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
H04N 25/75 - Circuitry for providing, modifying or processing image signals from the pixel array
26.
STORAGE DEVICE, CONTROLLER AND METHOD FOR PERFORMING GLOBAL WEAR-LEVELING
A storage device, a controller, and a method for performing global wear-leveling may count write counts of a plurality of respective cores in each of a plurality of logical areas each including logical block address groups of the plurality of cores, determine, on the basis of degradation counts of the plurality of cores, a first core and a second core for which data swap is to be performed, determine a target logical area among the plurality of logical areas on the basis of a write count of the first core and a write count of the second core, and perform data swap between a first logical block address group of the first core included in the target logical area and a second logical block address group of the second core included in the target logical area.
A semiconductor memory device and a method of manufacturing the semiconductor memory device are provided. The semiconductor memory device includes a gate stacked structure with a cell array region and a contact region with a stepped shape, and a roughness of a first sidewall of the cell array region is greater than that of a second sidewall of the contact region.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
The present disclosure relates to an image sensing device including a pixel array including a plurality of unit pixels is arranged. Each of the plurality of unit pixels includes: a substrate; a planarization layer formed over the substrate; and a color filter disposed over the planarization layer. The color filter includes at least one of a white color filter, a green color filter, a blue color filter, or a red color filter. The planarization layer includes a material of the white color filter.
A semiconductor device according to an aspect includes a first electrode layer, a ferroelectric tunnel barrier layer disposed over the first electrode layer, and a second electrode layer disposed over the ferroelectric tunnel barrier layer. The ferroelectric tunnel barrier layer includes oxygen vacancies. The second electrode layer includes a metal oxide. The second electrode layer has a relatively low density of conducting carriers, compared to the first electrode layer.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
A storage device and an operating method of the storage device are provided, which can determine and manage a reliability check target group based on an operating environment of the storage device. In one aspect, an operating method of a storage device comprises dividing, by the controller, weak wordlines having a number of fail bits greater than a predetermined value into a plurality of groups based on the number of fail bits, determining, among the plurality of groups based on operating environment information, target group on which a reliability check is to be performed, performing the reliability check on the target group; and performing a read reclaim operation based on results of the reliability check.
An ADC device includes: a comparator having first and second input terminals and an output terminal and being configured to compare an input signal input through the first input terminal with a reference voltage input through the second input terminal to output a comparison result value through the output terminal, the reference voltage being decreased by a preset value from a previous value in response to a clock signal; a counter configured to output a digital count value that increases each time the clock signal toggles; a register configured to latch the digital count value based on the comparison result value and generate a digital value corresponding to the input signal based on the latched digital count value; a blocking capacitor connected to the first input terminal and configured to transmit the input signal to the first input terminal; and a control circuit configured to generate the clock signal.
A power management circuit that supplies a voltage for driving a memory outputs, to the memory, a voltage that is adjusted on the basis of a driving reference voltage inputted from the outside and operation timing information and operation status information of the memory received from a controller. Therefore, it is possible to improve the performance of the memory that operates using a voltage supplied from the power management circuit while maintaining voltage supply efficiency.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
The present technology relates to an electronic device. According to the present technology, a memory controller may include a training controller, a training data storage, and a machine learning processor. The training controller may perform training of correcting interface signals exchanged with a memory device, generate training data that is a result of the training, and output the training data as sample training data based on a comparison result of a training reference and the training data. The training data storage may store training history information including plural pieces of sample training data. The machine learning processor may update the training reference through machine learning based on the training history information.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
G11C 29/04 - Detection or location of defective memory elements
G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns
G11C 29/56 - External testing equipment for static stores, e.g. automatic test equipment [ATE]Interfaces therefor
34.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor memory device, and a method of manufacturing the same, includes a gate stacked body including interlayer insulating layers and conductive patterns that are alternately stacked on a substrate in a vertical direction, a channel structure penetrating at least a portion of the gate stacked body and having a first end protruding upward higher than the gate stacked body, a memory layer enclosing a sidewall of the channel structure, and a source layer formed on the gate stacked body. The channel structure includes a core insulating layer formed in a central region of the channel structure and extending in a vertical direction, and a channel layer enclosing a sidewall of the core insulating layer and formed to be higher than the core insulating layer and the memory layer in the vertical direction.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
35.
METHOD FOR PROTOTYPING AND EVALUATION OF HARDWARE ACCELERATORS
A method for evaluating hardware accelerators in the design flow of the hardware accelerators. The method includes: generating a data processing graph for describing at least one algorithmic operation; evaluating a complexity and performance of the data processing graph using complexity and performance metrics; modifying the data processing graph based on set constraints, and the evaluated complexity and performance to generate multiple data processing graphs; evaluating the multiple data processing graphs using the complexity and performance metrics; and selecting at least one optimal graph from among the multiple data processing graphs for design of the hardware accelerator. The optional part of hardware implementation includes HDL description and FPGA/ASIC synthesis.
A semiconductor device may include at least one memory string that is connected between a bit line and a source line and includes a plurality of memory cells connected to a plurality of word lines, and a page buffer connected to the bit line and configured to sense data stored in the plurality of memory cells. Multi-bit data stored in a selected memory cell of the plurality of memory cells may be consecutively output by sequentially providing a selected word line of the plurality of word lines with read voltages having different levels in a state in which unselected word lines of the plurality of word lines are provided with a pass voltage.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
Disclosed is a storage device capable of improving performance by changing a period of a scan operation, and an operating method of the same. The storage device may include a memory including a plurality of memory blocks and a controller configured to set a plurality of scan trigger groups having different scan trigger periods, perform a scan operation on the plurality of memory blocks, assign each of the plurality of memory blocks to one of the plurality of scan trigger groups based on the number of bit errors included in data read by each of the memory blocks, and set different scan trigger periods for the memory blocks based on the scan trigger group to which each of the memory blocks belongs.
A pooled memory device includes plural memory devices and a controller. The plural memory devices include a first memory and a second memory with at least one power supply configured to control power supplied to each of the plural memory devices. The controller is coupled to an interconnect device which is configured to provide the plural memory devices to at least one external device as a logical device. The controller is configured to track available storage capacities of the first memory and the second memory and cut off power supplied to an unused memory among the first memory and the second memory.
There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.
A memory device includes a target memory block and a peripheral circuit configured to float local word lines which are coupled to the target memory block while an erase voltage rises toward a target level, apply a first voltage to the local word lines after the erase voltage reaches the target level, and apply one or more group voltages to the local word lines after applying the first voltage.
A memory system includes a plurality of memory modules; a plurality of module controllers configured to respectively control the plurality of memory modules; and a plurality of interface circuits configured to interface the plurality of memory modules with the plurality of module controllers, wherein, according to a setting signal, at least one target interface circuit is configured to interface a target module controller among the plurality of module controllers with a target memory module among the plurality of modules, or interfaces other module controllers different from the target module controller with the target memory module.
A semiconductor device may include: a first conductive line; a second conductive line intersecting the first conductive line; a first variable resistance pattern located between the first conductive line and the second conductive line and including a first group 16 element at a first concentration; a second variable resistance pattern located between the first variable resistance pattern and the second conductive line and including a second group 16 element at a second concentration higher than the first concentration; and a diffusion barrier pattern located between the first variable resistance pattern and the second variable resistance pattern.
A semiconductor device may include: a peripheral circuit located on a substrate; a stack structure located over the peripheral circuit in a non-core region and including insulating layers and dummy layers that are alternately and repeatedly stacked; a channel pattern located on the stack structure; a transistor located on the channel pattern; a contact structure extending through the stack structure and electrically connecting the peripheral circuit to the channel pattern; a gate structure located over the peripheral circuit in a core region and including insulating layers and conductive layers that are alternately and repeatedly stacked; a first source pattern located on the gate structure; and a channel structure extending through the gate structure to contact the first source pattern.
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
45.
SEMICONDUCTOR DEVICE INCLUDING ELECTRODE AND ISOLATION PATTERN AND METHOD OF FORMING THE SAME
A semiconductor device may include a stack structure bonded onto a circuit structure and including a plurality of molding layers alternately stacked with a plurality of electrodes. A source line may be disposed on the stack structure. A channel structure extending into the source line through the stack structure may be provided. An isolation insulating pattern disposed in a slit that extends through the source line and the stack structure may be provided. The isolation insulating pattern may include a first section adjacent to the source line and a second section adjacent to the stack structure. The isolation insulating pattern may include a convergence interface between the first section and the second section. The convergence interface may be disposed between an end of the channel structure and an end of the plurality of electrodes.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
46.
MEMORY DEVICE AND OPERATION METHOD FOR GENERATING CHECK POINTS BASED ON WRITE DATA PATTERN
A memory system includes a memory device and a controller. The memory device includes a plurality of memory blocks. The controller recognizes a change in a pattern of a plurality of write data, delays a checkpoint operation associated with a write operation regarding the plurality of write data entries when operational data regarding the plurality of write data entries is within a range that is capable of being stored in a buffer, and performs the checkpoint operation when the operational data is beyond the range.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
47.
THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
In an embodiment of the disclosed technology, a three-dimensional memory device includes a stack including a plurality of gate electrodes, each of which includes an electrode portion and a pad portion, the pad portion being disposed on one area of the electrode portion, and a plurality of interlayer insulating layers that are stacked alternately with the plurality of gate electrodes, the stack having a connection area in which the pad portions of the plurality of gate electrodes are disposed in step shapes; a row connection contact passing through the connection area and passing through a corresponding pad portion of a corresponding gate electrode, among the plurality of gate electrodes, thereby connecting to the corresponding pad portion of the corresponding gate electrode; and a plurality of first insulating patterns disposed between the row connection contact and side surfaces of electrode portions of gate electrodes that face the row connection contact.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
48.
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF A MANUFACTURING THE SEMICONDUCTOR MEMORY DEVICE
Provided herein is a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a plurality of first conductive layers of a first sub-stacked body, a plurality of second conductive layers of a second sub-stacked body disposed over the first sub-stacked body, and a first gate contact plug contacting a corresponding second conductive layer among the plurality of second conductive layers. The first gate contact plug includes a first contact portion contacting the corresponding second conductive layer, a first portion penetrating the first sub-stacked body, and a second portion extending from the first portion toward the first contact portion.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
49.
STORAGE DEVICE FOR STORING DATA AND METHOD OF OPERATING THE SAME
Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory blocks, each including a plurality of memory cells configured to store data, and a memory controller in communication with the memory device and configured to 1) determine a write mode of a memory block of the memory device to be either a first write mode in which one data bit is stored in a memory cell of a memory block or a second write mode in which a plurality of data bits is stored in a memory cell based on a temperature of the storage device and a number of read reclaim operations that have been performed in the memory block and 2) control the memory device to perform a write operation in the determined write mode.
The present disclosure relates to method of operating a memory device that includes programming program data by distributing the program data to a first memory cell group corresponding to a first drain select line and a second memory cell group corresponding to a second drain select line during a program operation of a selected memory block, reading memory cells included in each of the first memory cell group and the second memory cell group during a read operation of the selected memory block, and determining threshold voltages for the first memory cell group according to a read result for the first memory cell group and threshold voltages for the second memory cell group according to a read result for the second memory cell group and outputting data codes corresponding to combinations of the threshold voltages during a read operation of the selected memory block.
A memory device includes memory cells and a control unit. The memory cells are coupled in series between one or more first selection transistors coupled in series to a source line and one or more second selection transistors coupled in series to a bit line. The control unit is configured to apply, during a forcing period that is part of a rising period during which an increasing erase voltage is applied to the bit line, an increasing selection voltage to local selection lines coupled to the one or more first selection transistors and the one or more second selection transistors.
A method for manufacturing a semiconductor device includes forming a first insulation layer over a second region of a semiconductor substrate including first and second regions, forming a capping layer to cover the first insulation layer located over the second region, forming a charge transfer layer over the first region, and forming a second insulation layer over the charge transfer layer located over the first region.
H01L 29/792 - Field-effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistor
A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor memory device having a memory cell, the memory cell includes a lower electrode; a selection element over the lower electrode; a buffer layer over the selection element; a middle electrode over the buffer layer; a memory layer over the middle electrode; and an upper electrode over the memory layer. The buffer layer includes titanium, nitrogen, and oxygen. A titanium content ratio is higher than 1.21 times of a nitrogen content ratio in the buffer layer.
A semiconductor device is provided to include first conductive lines extending in a first direction; a second conductive lines disposed to be spaced apart from the first conductive lines in a third direction and extending in a second direction intersecting with the first direction; a memory cells overlapping with intersection areas of the first conductive lines and the second conductive lines; and first variable resistance patterns that are respectively coupled in series to the memory cells, one first variable resistance pattern per memory cell, so that each first variable resistance pattern and a corresponding memory cell are connected between a corresponding first conductive line of the first conductive lines and a corresponding second conductive line of the second conductive lines.
A semiconductor device including a circuit structure which includes a page buffer. A first stack structure bonded over the circuit structure. A first source line disposed on the first stack structure. A first channel structure connected to the first source line by passing through the first stack structure is provided. A second stack structure bonded over the first stack structure and the first source line. A second source line disposed on the second stack structure. A second channel structure connected to the second source line by passing through the second stack structure is provided. A first bit through electrode connected to the second channel structure by passing through the first stack structure is provided. The first channel structure and the second channel structure connected to the page buffer.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
56.
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
There are provided a semiconductor memory device and a manufacturing method thereof. The manufacturing method of the semiconductor memory device includes: forming a preliminary memory cell array that includes a gate stack structure and a channel structure, wherein the gate stack structure includes interlayer insulating layers and conductive patterns, alternately stacked on a first substrate, and wherein the channel structure has a first end portion that penetrates the gate stack structure and extends into the first substrate; forming a common source line to be in contact with a second end portion of the channel structure, the common source line formed on a first surface of the gate stack structure; removing the first substrate; and forming a bit line connected to the first end portion of the channel structure on a second surface of the gate stack structure that is opposite of the first surface of the gate stack structure.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
Techniques for decoding a low-density parity check (LDPC) can include determining an asymmetric ratio of bit errors read as logic zero to bit errors read as logic one. The energy of each variable node of the LDPC codeword can be computed. For each variable node having an energy greater than a threshold energy, the variable node can be added to a collection of candidate bits for bit flipping. The asymmetric ratio can then be applied to flip bits in the collection of candidate bits to decode the LDPC codeword.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/37 - Decoding methods or techniques, not specific to the particular type of coding provided for in groups
A semiconductor device may include a substrate including a chip region and a pad region, first bonding pads positioned in the chip region, second bonding pads positioned on the first bonding pads and having a front surface connected to the first bonding pads, a first probing pad positioned in the pad region, extending to the chip region, and connected to a rear surface of at least one second bonding pad among the second bonding pads, and a second probing pad positioned neighbor the first probing pad and connected to the rear surface of at least one second bonding pad among the second bonding pads.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
59.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device may include a gate structure including insulating layers and conductive layers alternately stacked over a source structure, a channel structure extending through the gate structure, an insulating support extending through the gate structure, a first seed layer surrounding a sidewall of the insulating support, and a first barrier layer positioned between the gate structure and the first seed layer.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
60.
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device may include memory strings coupled between bit lines, respectively, and a source line, each of memory strings including memory cells coupled to word lines, and page buffers coupled to the bit lines, respectively, each of page buffers configured to output a verification result by sensing data that have been stored in memory cells that are coupled to each selected word line, among the memory strings, after a start of a verification operation of a program operation. The number of memory cells that have been programmed successfully and a pass permission bit may be compared based on a temperature of the semiconductor device and the verification result after the start of the verification operation of the program operation, wherein the pass permission bit corresponds to the temperature.
In an embodiment of the disclosed technology, file type information and file size information are provided through an extra header segment of a command unit and a file mapping table based on the file type information and the file size information is generated and managed. Therefore, by loading in advance an address mapping table associated with a file configured by read-requested data upon a read request, the performance of a read operation based on a mapping table may be improved.
A fail classification device may determine, on the basis of threshold voltage distribution information, a cell type of a plurality of memory cells or whether the threshold voltage distribution information is abnormal. The fail classification device may transform the threshold voltage distribution information into a two-dimensional image, may input the two-dimensional image to a target artificial intelligence model corresponding to the cell type, and may classify the fail type of the plurality of memory cells on the basis of the output result of the target artificial intelligence model.
A memory device includes a cell array and a control circuit. The cell array includes a drain select line, a bit line and a cell string including plural memory cells. The control circuit is configured to sense data stored in a selected cell among the plural memory cells in the cell string and apply a first negative voltage to the drain select line while performing equalization for the plural memory cells.
There are provided a memory device and an operating method of the memory device. The memory device includes: a memory block including a plurality of memory cells; a peripheral circuit configured to perform a plurality of read voltage applying operations and a plurality of word line setting operations on the memory block; and control logic configured to control the peripheral circuit to perform a plurality of word line setting operations to set a plurality of word line potentials of word lines included in the memory block, wherein at least one word line setting operation among the plurality of word line setting operations is used to set a word line potential higher than a word line potential set by the other word line setting operations.
A data encoding method encodes eleven binary bits as seven symbols. The data encoding method generates a check signal based on first to fourth bits. The data encoding method includes encoding first to fifth bits to generate first to third symbols. The method includes encoding sixth to eighth bits to generate fourth and fifth symbols. The method also includes encoding ninth to eleventh bits to generate sixth and seventh symbols, when the check signal has a first logic level.
A semiconductor device includes a gate electrode layer; a control electrode layer; an oxide semiconductor layer disposed between the gate electrode layer and the control electrode layer; a gate dielectric layer disposed between the gate electrode layer and the oxide semiconductor layer; a reservoir layer disposed between the oxide semiconductor layer; and a solid-state electrolyte layer disposed between the oxide semiconductor layer and the reservoir layer.
A semiconductor device includes a lower interconnection line, a lower electrode disposed over the lower interconnection line, a first magnetic control layer disposed over the lower electrode, a selection element layer disposed over the first magnetic control layer, a second magnetic control layer disposed over the selection element layer, a memory element layer disposed over the second magnetic control layer, an upper electrode disposed over the memory element layer, and 10 an upper interconnection line disposed over the upper electrode. Each of the first and second magnetic control layers includes at least one of cobalt, iron, nickel, molybdenum, aluminum, chromium, permalloy, supermalloy, an oxide thereof, or a nitride thereof.
A semiconductor device includes a lower interconnection line; a memory cell structure over the lower interconnection line; and an upper interconnection line over the memory cell structure. The memory cell structure includes a first electrode; a selection element over the first electrode; a first carrier tunneling layer over the selection element layer; a second electrode over the first carrier tunneling layer; a memory element layer over the second electrode; and a third electrode over the memory element layer. The first carrier tunneling layer includes an insulating layer doped with at least one pentavalent element.
An image sensing device includes first conductive lines; second conductive lines disposed adjacent to the first conductive lines; a top test pad circuit including a first top test pad and a second top test pad; a bottom test pad circuit including a first bottom test pad and a second bottom test pad; a top switching circuit configured to connect a first terminal of each of the first conductive lines to the first top test pad and connect a first terminal of each of the second conductive lines to the second top test pad, based on a first switching signal; and a bottom switching circuit configured to connect a second terminal of each of the first conductive lines to the first bottom test pad and connect a second terminal of each of the second conductive lines to the second bottom test pad, based on a second switching signal.
H04N 25/677 - Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
Disclosed are a semiconductor device including highly integrated memory cells, and a method for fabricating the semiconductor device. A method for fabricating a semiconductor device includes forming a mold stack of conductive layers over a lower structure, the mold stack including a first horizontal conductive line, a second horizontal conductive line, and a pad between the first horizontal conductive line and the second horizontal conductive line; forming a vertical stack of a stair structure whose height is gradually decreased in a stack direction that the conductive layers are stacked by selectively etching a portion of the mold stack; forming contact holes in the stair structure, wherein heights of the contact holes are gradually decreased in the stack direction; and forming contact plugs in the contact holes, the contact plugs coupled to the conductive layers, respectively.
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a first etch stop layer; a source layer on the first etch stop layer; a second etch stop layer on the source layer; a stack structure on the second etch stop layer; and a channel structure penetrating the first and second etch stop layers, the source layer, and the stack structure, the channel structure being electrically connected to the source layer. A material of each of the first and second etch stop layers has an etch selectivity with respect to a material of the source layer.
A semiconductor device comprising: a first circuit configured to generate a transfer signal by decreasing an amplitude of an input signal provided through a first interface and configured to transfer the transfer signal through a transfer path, and a second circuit configured to generate an output signal by increasing an amplitude of the transfer signal transferred through the transfer path and configured to output the output signal through a second interface, wherein the second circuit includes a skewed inverter configured to asymmetrically set a reference level for determining a logic level of the transfer signal.
A computing system includes a substrate, a memory apparatus, and a host die. The memory apparatus is disposed on the substrate, and the host die is disposed on the memory apparatus. The host die is coupled to the substrate through a through via formed in a memory die included in the memory apparatus.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
An electrochemical memory cell may include a plurality of nano patterns, a gate and an interface layer. The nano patterns may be stacked on an active region by a set gap. The gate may surround all surfaces of each of the nano patterns. The interface layer may be interposed between the nano patterns and the gate. The nano patterns may include a variable resistance material.
A receiver circuit includes an input unit configured to receive a reception pattern signal in a training mode, and a reception normal signal in a normal mode, an enable control unit configured to determine whether to activate an enable signal according to the reception pattern signal in the training mode, a first decision feedback equalizer configured to operate in an activation period of the enable signal, and to remove a first post-cursor component for the reception normal signal by calibrating a currently received value based on a previously received value of the reception normal signal, and a second decision feedback equalizer configured to, when the enable signal is in an activated state, remove second to Nth post-cursor components for the reception normal signal by adjusting driving abilities of input transistors, to which the currently received value is applied, according to patterns of the reception normal signal.
A three-dimensional memory device includes a stack including a plurality of electrode layers and a plurality of interlayer insulating layers which are alternately stacked on a substrate; a contact plug extending to one of the plurality of electrode layers by vertically penetrating the stack; and hard mask layers disposed between an upper portion of the contact plug and electrode layers around the upper portion of the contact plug.
H01L 23/528 - Layout of the interconnection structure
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
77.
DEVICE WITH IMPROVED DATA RECEIVING LOGIC USING MULTIPLE LATCHING AND METHOD THEREOF
An electronic apparatus includes: a latch trigger generator configured to generate a plurality of latch triggers based on an input data strobe signal and a plurality of preset delay times; a data latch unit configured to latch a data line based on the plurality of latch triggers to generate a plurality of latched data; and a processor configured to set the plurality of delay times and determine reception data based on the plurality of latched data.
A semiconductor memory device includes a dummy stack structure, an insulative chip guard pattern penetrating a lower portion of the dummy stack structure, and a conductive chip guard pattern which is aligned over the insulative chip guard pattern and penetrates an upper portion of the dummy stack structure.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
79.
PAGE BUFFER RELATED TO PERFORMING A PROGRAM OPERATION, MEMORY DEVICE INCLUDING A PAGE BUFFER, AND METHOD OF OPERATING THE PAGE BUFFER
Provided herein may be a page buffer. The page buffer includes a sensing node connected to a bit line, a bit line voltage controlling circuit configured to precharge the bit line during a verify operation, a sensing node voltage controller configured to precharge the sensing node while the bit line is precharged, a first latch connected to the sensing node, and configured to store a first bit value determined based on a first evaluation operation among bit values corresponding to a voltage level of the sensing node after the sensing node is precharged, and a second latch connected to the sensing node, and configured to store a second bit value determined based on a second evaluation operation after the first bit value is stored. The first latch stores the first bit value determined based on a third evaluation operation after the second bit value is stored in the second latch.
A method for fabricating a semiconductor device includes forming a stack body over a lower structure in which a substrate, a blocking layer, and a support layer are sequentially stacked; forming a plurality of sacrificial vertical openings by etching the stack body and the support layer using the blocking layer as an etching stop layer; and forming, in the stack body, three-dimensional memory cells including a vertical conductive line, a horizontal conductive line, and a data storage element.
A semiconductor memory device includes a memory block including plurality of string groups, a peripheral circuit, and control logic. The peripheral circuit performs a program operation on source select transistors included in the memory block. The control logic controls the program operation of the peripheral circuit. Each of the plurality of string groups includes at least one cell string, and the at least one cell string includes inner source select transistors located adjacent to memory cells and outer source select transistors located adjacent to a common source line. The control logic controls the peripheral circuit to perform program operations on the outer source select transistors and the inner source select transistors by an ISPP method. The control logic controls the peripheral circuit to perform a verify operation by dividing the inner source select transistors into at least two groups during the program operation of the inner source select transistors.
A verification environment sanity checker and method for simulating a design under test (DUT) of a verification environment. The verification environment sanity checker includes a fault injector injects, to a simulation engine, at least one fault for at least one feature among the DUT features for at least one component of the DUT components such that the simulation engine simulates the DUT by injecting the fault into the DUT and a test bench tests the feature for the DUT. A verification environment parser analyzes a test result for the DUT associated with the feature, and produces an error list indicating an error of the DUT associated with the feature. The fault injector detects whether a faulty operation corresponding to the feature is captured, based on the error list.
A method and system for producing a health test (HT) processing engine to test a random number source. The method and system receive a set of health tests to program into the HT processing engine, determine operations, constants, and variables used by the set of health tests, map the constants and the variables to a memory buffer in the HT processing engine, generate binary code operational instructions for each operation for each health test in the set of health tests, synthesize the HT processing engine for a chosen hardware platform for processing the binary code operational instructions, and program hardware in the HT processing engine to process the binary code operational instructions with the chosen hardware platform.
An inverter including at least one PMOS transistor and at least one NMOS transistor. The PMOS transistor including a first gate, a first source and a first drain. The first gate may be connected to an input signal line. The first source may be connected to a power voltage line. The first drain may be connected to an output signal line. The NMOS transistor including a second gate, a second source and a second drain. The second gate may be connected to the input signal line. The second source may be connected to a ground voltage line. The second drain may be connected to the output signal line.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 23/528 - Layout of the interconnection structure
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
A storage apparatus includes a memory device including a first memory block and a second memory block and a storage controller configured to control the memory device. The storage controller is configured to determine, when first read data read-requested by an external apparatus is read from the first memory block, an attribute of the first read data set by the external apparatus and copy the first read data having a first attribute to the second memory block.
Data storage devices and controllers are disclosed. In an embodiment of the disclosed technology, an occupied logical memory address for loading an overlay code stored in a memory into a buffer memory is allocated and set in advance, and the loading of the overlay code is performed using the occupied logical memory address. Therefore, the overlay code can be loaded without allocating in advance a buffer area of the buffer memory, and thus the buffer memory may be efficiently used and the loading of the overlay code may be effectively performed.
The present disclosure relates a method of manufacturing a memory device. A method of manufacturing a memory device includes forming a stack structure including first material layers alternately stacked with second material layers, forming a channel layer including amorphous silicon in an opening extending through the stack structure, converting a first part of the channel layer into single crystalline silicon, doping the first part of the channel layer with a conductive material, doping a second part different from the first part of the channel layer with the conductive material, and converting the second part of the channel layer into polycrystalline silicon using the conductive material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
88.
IMPEDANCE CALIBRATION CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS AND MEMORY SYSTEM INCLUDING IMPEDANCE CALIBRATION CIRCUIT
An impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command. The code update control circuit prevents updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.
A dark shading correction method and a device for implementing the same provide technology capable of performing correction for each portion of an image causing the dark shading phenomenon that may occur at various locations as a semiconductor chip increases in size. The dark shading correction method for processing images from an image sensing device is provided. The dark shading correction method includes dividing a dark image into a plurality of first division images, dividing each of the first division areas to be re-divided according to a predetermined standard into a plurality of second division areas, and calculating correction parameters of each of the division areas. As a result, the dark shading correction method and device perform individual dark shading correction for each portion of an image, resulting in formation of images with improved quality.
A method for fabricating a semiconductor device includes: forming a first electrode layer; forming, over the first electrode layer, a plurality of dielectric layers with one or more metal-containing patterns or one or more metal-containing thin films being disposed between at least two neighboring dielectric layers of the plurality of dielectric layers; and forming a selector layer by performing a first implanting process to implant a dopant into the at least two neighboring dielectric layers including or in contact with the one or more metal-containing patterns or the one or more metal-containing thin films.
A semiconductor device includes first magnetic tunnel junction structures arranged in first and second directions crossing each other and having a first width in the first direction; second magnetic tunnel junction structures arranged in the first direction and the second direction and arranged alternately with the first magnetic tunnel junction structures in a third direction crossing the first and second directions, and having a second width of the first direction greater than the first width; and third magnetic tunnel junction structures having a long axis parallel to the first direction and a short axis parallel to the second direction, arranged alternately with the first magnetic tunnel junction structures in the first direction, and arranged alternately with the second magnetic tunnel junction structures in the second direction, and having the long axis parallel to the second direction and the short axis parallel to the first direction.
A semiconductor device includes a trench formed in a substrate; a first gate electrode filling a lower portion of the trench, and the first gate electrode containing a trap passivation material; and a second gate electrode formed over the first gate electrode, and the second gate electrode containing the trap passivation material. The reliability of semiconductor devices may be improved by applying a gate electrode containing a trap passivation material. The resistance of a word line may be reduced by applying a gate electrode containing a metal material. The gate-induced drain leakage (GIDL) may be reduced by adjusting the work functions of the upper and lower gate electrodes.
Disclosed are a semiconductor device including highly integrated memory cells, and a method for fabricating the semiconductor device. A semiconductor device includes a memory cell array disposed over the peripheral circuit region; a dummy region including a dummy stack that is spaced apart horizontally from the memory cell array; a peripheral circuit region disposed at a lower level than the memory cell array and dummy region; a stack level plug passing through the dummy stack; and a stack level spacer formed on a sidewall of the stack level plug.
Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory block including memory cell strings, a voltage supply circuit configured to apply operating voltages to global drain select lines, global source select lines, and global word lines, and apply an erase voltage to bit lines or to the bit lines and a source line during an erase operation, a pass circuit configured to couple the global drain select lines, global source select lines, and global word lines to local drain select lines, local source select lines, and local word lines in response to a block select signal, and control logic configured to control the voltage supply circuit to apply a first operating voltage to the global drain select lines and thereafter apply a second operating voltage to the global drain select lines.
A semiconductor device may include first wiring lines, a plurality of second wiring lines located over the first wiring lines, an interlayer insulating layer comprising a first portion, the first portion located in a gap between second wiring lines that neighbor each other in the first direction and a first auxiliary wiring line electrically coupling the first wiring lines.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
96.
SEMICONDUCTOR DEVICE AND OPERATION METHOD USING THE SAME
A semiconductor device may include a first source line driving circuit that drives a first source line, a second source line driving circuit that drives a second source line, a first memory block including a plurality of first memory strings coupled between the first source line and a plurality of bit lines, respectively, and a second memory block including a plurality of second memory strings coupled between the second source line and the plurality of bit lines, respectively.
A semiconductor device may include a gate structure including stacked gate lines, conductive supports extending perpendicularly or substantially perpendicularly through the gate structure, and contact plugs extending perpendicularly or substantially perpendicularly only partially inside the gate structure, each contact plug being positioned between adjacent conductive supports and respectively connected to the gate lines. A first contact plug among the contact plugs may be electrically connected to a first gate line among the gate lines, and the first contact plug may be electrically connected to a first conductive support among the conductive supports through the first gate line.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Provided herein is a memory device and a method of manufacturing the same. The memory device including a stacked body, a channel layer penetrating the stacked body, a tunnel isolation layer enclosing an outer side surface of the channel layer, a capping layer extending from the channel layer and protruding upward from the stacked body, a spacer enclosing an outer side surface of the capping layer on the stacked body, and a liner layer extending along a top surface of the stacked body and an outer side surface of the spacer. In an embodiment, the tunnel isolation layer having a first thickness, and the spacer may have a second thickness greater than the first thickness. In an embodiment, the spacer having a first height, and the liner layer having a second height lower than the first height.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
99.
CODING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION (Republic of Korea)
Inventor
Kang, Seongyoon
Park, Jongsun
Jang, Munseon
Abstract
A coding circuit includes an encoder circuit generating parity by applying input data to a parity generating matrix and generating an input codeword by concatenating the input data and the parity; and a decoder circuit detecting and correcting an error included in an output codeword based on a first syndrome, a second syndrome, and a third syndrome for identifying an error boundary. The first, second, and third syndromes are generated by applying the output codeword to the parity generating matrix.
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M 13/29 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
A stack chip package includes a first stack structure, a second stack structure and a passive element. The first and second stack structures include a plurality of semiconductor chips stacked on a package substrate, respectively. The first stack structure has a first sidewall portion and a second sidewall portion. The plurality of the semiconductor chips in the first stack structure are stacked on the first sidewall portion to form a first concave portion and a first protrusion alternately arranged. The second stack structure has a third sidewall portion and a fourth sidewall portion. The third sidewall portion faces the first sidewall portion. The plurality of the semiconductor chips in the second stack structure are stacked on the third sidewall portion to form a second concave portion and a second protrusion alternately arranged. The first concave portion faces the second protrusion. The first protrusion faces the second concave portion.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
