According to one exemplary embodiment, a chip is described, comprising a plurality of cascode circuits, wherein each cascode circuit has at least one cascode having at least one respective cascode transistor, a voltage generation circuit which is set up to generate control voltages for controlling the cascode transistors of the cascode circuits, a respective transistor circuit for each cascode, which is connected between the voltage generation circuit and the cascode, has a respective source follower and is set up to generate a cascode transistor control voltage for the at least one cascode transistor of the cascode by means of the respective source follower from a respective control voltage of the control voltages generated by the voltage generation circuit.
Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.
The innovative concept described herein relates to a magnetic-field-based current measuring device. The latter includes, inter alia, an at least two-dimensionally measuring magnetic field sensor mounted at a node at which a first, a second and a third electrical conductor, each coming from different directions, are brought together. The magnetic field sensor is configured to determine in each case a magnitude and/or a direction of the magnetic fields which are respectively generated in the first, second and third electrical conductors and meet at the node, and to derive, on the basis thereof, information about a magnitude and/or a direction of the individual electric currents flowing at the node. The innovative concept described herein additionally relates to a corresponding method for magnetic-field-based measurement of electric currents using a magnetic-field-based current measuring device.
G01R 19/00 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe
G01R 15/20 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs galvano-magnétiques, p. ex. des dispositifs à effet Hall
4.
Power Converter, Power Converter Controller, and Method of Controlling a Power Converter
A power converter, power converter controller, and method of controlling a power converter are described. The power converter includes: a half bridge or full bridge switch network; an LLC resonant tank electrically coupled to the switch network; a rectifier circuit electrically coupled to a filter capacitor configured to provide a DC output voltage; a transformer inductively coupling the rectifier circuit to the LLC resonant tank; and a controller configured to determine a reference voltage to which the DC output voltage is regulated, and adjust a switching frequency of the switch network based on a difference between the DC output voltage and the reference voltage. The controller is configured to determine the reference voltage based on input voltage and/or output current feedback for the power converter and/or determine a variable switching frequency or a variable switching period for the switch network based on input voltage magnitude and output current magnitude.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
5.
METHOD AND CONTROL CIRCUIT FOR OPERATING A HALF-BRIDGE CIRCUIT
A half-bridge includes a high-side switch and a low-side switch. A switching node is between the high-side switch and the low-side switch. A load is electrically connected to the switching node. In a first interval TP1 beginning with a current flow through the load in a first direction, the high-side switch is turned on for a first pulse time TL1 and the low-side switch is turned on for a first reverse conducting time TRC1 that begins after an end of the first pulse time TL1. In a second interval TP2 following the first interval TP1 and beginning with a current flow through the load in a second direction opposite the first direction, the low-side switch is turned on for a second pulse time TL2 and the high-side switch is turned on for a second reverse conducting time TRC2 starting after an end of the second pulse time TL2.
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 1/00 - Détails d'appareils pour transformation
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
09 - Appareils et instruments scientifiques et électriques
10 - Appareils et instruments médicaux
11 - Appareils de contrôle de l'environnement
12 - Véhicules; appareils de locomotion par terre, par air ou par eau; parties de véhicules
25 - Vêtements; chaussures; chapellerie
28 - Jeux, jouets, articles de sport
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Electricity generators; agricultural, earthmoving,
construction, oil and gas extraction and mining equipment;
industrial robots; pumps [machines]; compressors [machines];
rotary blowers; machines and machine tools for treatment of
materials and for manufacturing. Downloadable and recorded content; information technology
and audio-visual, multimedia and photographic equipment;
scientific and laboratory devices for treatment using
electricity; apparatus, instruments and cables for
electricity; safety, security, protection and signalling
devices; navigation, guidance, tracking, targeting and map
making equipment; measuring, detecting, monitoring and
controlling equipment; scientific research and laboratory
apparatus, educational apparatus and simulators. Physical therapy equipment; medical and veterinary apparatus
and instruments. Lighting and lighting reflectors; heating, ventilating, and
air conditioning and purification equipment (ambient);
cooking, heating, cooling and preservation equipment, for
food and beverages; industrial treatment apparatus and
installations; refrigerating and freezing equipment; heating
elements and filaments. Vehicles and conveyances. Clothing; footwear; headgear. Sporting and physical exercise equipment; toys, games, and
playthings. Science and technology services; IT services.
7.
SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE STRUCTURE AND BURIED SHIELDING REGION AND METHOD OF MANUFACTURING
In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
The application relates to a one-time programmable (otp) cell, including a selector device with a channel region, an otp capacitor with an otp capacitor dielectric associated with the selector device, and an isolation dielectric having an isolation dielectric thickness. The otp capacitor dielectric includes a first dielectric in a first area and a second dielectric in a second area. The second dielectric has a second thickness which is smaller than the isolation dielectric thickness. The first dielectric has a first thickness which is smaller than the second thickness. The first area is embedded into the second area.
A common-gate amplifying arrangement. The common-gate amplifying arrangement includes a common-gate amplifier and an inner regulated cascode. The inner regulated cascode amplifies a signal provided by the common-gate amplifier, which is responsive to an input signal.
A method of forming a semiconductor package includes providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and an adjacent stabilizing metal section, arranging the lead frame on a temporary carrier, arranging a semiconductor die on the temporary carrier within the central opening, forming a dielectric material that fills the central opening and encapsulates the semiconductor die, forming a first recess in the dielectric material above the semiconductor die so as to expose a first surface of the semiconductor die, electrically connecting terminals of the semiconductor die with the metal frame, and forming exposed outer contacts of the semiconductor package from the tie bars.
A semiconductor package includes a carrier having a die pad and a plurality of leads, a first discrete power device die mounted on the die pad and having a first load terminal pad disposed on a main surface that faces away from the die pad, a first package load terminal formed by one or more of the leads, and a first metal clip that electrically connects the first load terminal pad of the first discrete power device die with the first package load terminal, wherein the first metal clip comprises a local constriction that is configured to locally reduce a heat conductance of the first metal clip in a section of the first metal clip that is between the first discrete power device die and the first package load terminal.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
12.
SEMICONDUCTOR PACKAGE WITH HEAT FLOW RESTRICTING CONNECTOR
A semiconductor package includes a carrier having a die pad and a plurality of leads, a first discrete power device die mounted on the die pad and having a first load terminal pad disposed on a main surface that faces away from the die pad, a first package load terminal formed by one or more of the leads, and a first metal clip that electrically connects the first load terminal pad of the first discrete power device die with the first package load terminal, wherein the first metal clip comprises a local constriction that is configured to locally reduce a heat conductance of the first metal clip in a section of the first metal clip that is between the first discrete power device die and the first package load terminal.
H01L 25/11 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A control circuit is provided, for controlling switching elements of an asymmetric half bridge (AHB) converter. The AHB converter includes a first switching element, a second switching element, a capacitor, and a transformer having a primary side and a secondary side. The control circuit includes a first output, for controlling the first switching element; and a second output, for controlling the second switching element. The control circuit also includes control logic, configured to generate a first pulse width modulated, PWM, control signal at the first output and a second PWM control signal at the second output. The control logic may have a first operation mode in which it is configured to cause a magnetizing current of the transformer to remain greater than zero throughout a switching period of the first and second PWM control signals.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/38 - Moyens pour empêcher la conduction simultanée de commutateurs
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
14.
PACKAGE WITH CARRIER HAVING PLATED BOTTOM SURFACE AND SIDEWALL
A package and method is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant at least partially encapsulating the electronic component and partially encapsulating the carrier. At least a portion of a bottom surface and at least a portion of a sidewall of the carrier are exposed beyond the encapsulant. Said at least portion of the bottom surface and said at least portion of the sidewall are covered at least partially by a plating structure.
A battery package is provided. The battery package includes a battery, at least one terminal coupled to an antenna, a single wire interface configured to communicate with a processor and coupled to the at least one terminal, a battery authentication circuit arranged on the battery, a choke inductor coupled to the single wire interface, and a clamping transistor circuit including a clamping transistor and coupled to the choke inductor and configured to clamp a voltage applied to the single wire interface to an operating voltage of the battery authentication circuit.
A semiconductor package includes a semiconductor die having a bond pad, an insulating layer covering the bond pad and having an opening with sidewalls, a polymer layer formed over the insulating layer and covering the sidewalls of the opening in the insulating layer, the polymer layer having an opening, and an electrical conductor having a conductive base attached to a part of the bond pad exposed by the insulating layer opening and the polymer layer opening. The polymer layer includes an upper segment and a lower segment. The polymer layer opening is larger in the upper segment than in the lower segment.
A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.
A method is disclosed. The method includes switching off a power transistor circuit in an electronic circuit. The electronic circuit includes a power source and a load circuit. The power transistor circuit is connected between the power source and the load circuit. Switching off the power transistor circuit includes operating at least one power transistor included in the power transistor circuit in an Avalanche mode so that at least a portion of energy stored in the electronic circuit before switching off the power transistor circuit is dissipated in the at least one power transistor.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
H03K 17/284 - Modifications pour introduire un retard avant commutation dans les commutateurs à transistors à effet de champ
A semiconductor module includes a semiconductor die, a mold compound encasing the semiconductor die, a plurality of terminals electrically connected to the semiconductor die and protruding out of the mold compound, wherein a first one of the terminals has a constricted region covered by the mold compound, wherein the mold compound has a recess or an opening near the constricted region of the first terminal, and a coreless magnetic field sensor disposed in the recess or the opening of the mold compound and isolated from the first terminal by the mold compound. The coreless magnetic sensor is configured to generate a signal in response to a magnetic field produced by current flowing in the constricted region of the first terminal. The magnitude of the signal is proportional to the amount of current flowing in the constricted region of the first terminal. A method of manufacturing the module also is described.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
G01R 15/20 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs galvano-magnétiques, p. ex. des dispositifs à effet Hall
G01R 33/00 - Dispositions ou appareils pour la mesure des grandeurs magnétiques
G01R 33/07 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs à effet Hall
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/051 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base conductrice qui sert de support et en même temps de connexion électrique pour le corps semi-conducteur une autre connexion étant constituée par le couvercle parallèle à la base, p. ex. du type "sandwich"
H01L 23/057 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur les connexions étant parallèles à la base
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/44 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température le dispositif complet étant totalement immergé dans un fluide autre que l'air
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message. The use of key counters may be extended to guard against weak replay attacks via the implementation of a live membership tracking solution, which defines one or more membership groups. Each node within a membership group may request, or “challenge” other nodes with the same membership group at any time to verify their online status, and this online status may be maintained over time.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A system includes a semiconductor device comprising a source terminal, a drain terminal, and an interface layer between the source terminal and the drain terminal, the interface layer comprising a plurality of interface channels. The system also includes a degradation monitoring circuit comprising an electrical sensor, wherein the degradation monitoring circuit is configured to: generate, using the electrical sensor, a sensor signal corresponding to one or more interface channels of the plurality of interface channels; determine, based on the sensor signal, whether a degradation of a material is present at the one or more interface channels of the plurality of interface channels; and output information indicating whether the degradation of the material is present at the one or more interface channels of the plurality of interface channels.
An electronic device is described herein which may be used as an electronic fuse (smart fuse). The device includes an electronic switch having a load current path coupled between an output node and a supply node and configured to connect or disconnect the output node and the supply node in accordance with a control signal. The device further includes a control circuit configured to generate the control signal based on an input signal, a current sense circuit configured to provide a current sense signal that represents a load current passing through the electronic switch, and a monitoring circuit configured to generate an overcurrent signal based on the current sense signal. The overcurrent signal is indicative of whether, or not, to disconnect the output node from supply node. The control circuit is configured to operate in a normal mode, an idle mode, and in a diagnosis mode.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
23.
PACKAGE WITH COMPONENT-CARRYING INTERMEDIATE STRUCTURE AND ADDITIONAL CARRIER HAVING REFERENCE POTENTIAL STRUCTURE
A package is disclosed. In one example, the package includes an at least partially electrically conductive carrier having a coupling structure and a reference potential structure which is electrically decoupled from the coupling structure and which is configured to be brought to an electric reference potential during operation of the package, an intermediate structure at the carrier and having an electrically insulating structure oriented towards the carrier and having a mounting structure facing away from the carrier. An electronic component is mounted on the mounting structure and being electrically coupled with the coupling structure. An encapsulant is encapsulating at least part of the intermediate structure, at least part of the electronic component, and part of the carrier so as to expose at least part of the reference potential structure and at least part of the coupling structure.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
24.
POWER TRANSISTOR CONTROL AND OVERCURRENT DETECTION
In accordance with an embodiment, a circuit includes a power transistor connected between a supply terminal and an output terminal; a control circuit coupled to a control electrode of the power transistor and configured to apply a control current to the control electrode to turn the power transistor on or off; and an overcurrent protection circuit connected to the power transistor. The circuit is configured to operate in a first mode, in which some functions of the circuit are inactive to reduce power consumption, and in a second mode, in which all functions of the circuit are active. The overcurrent protection circuit is configured to: in response to the circuit being in the first mode and a sense signal indicative of a load current passing through the power transistor reaching a first threshold, cause the circuit to change from the first mode to the second mode.
H02H 3/093 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge avec des moyens de temporisation
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
25.
SYSTEM AND METHOD FOR FAST MODE CHANGE OF A DIGITAL MICROPHONE USING DIGITAL CROSS-TALK COMPENSATION
A circuit includes a cross-talk compensation component including a power profile reconstruction component for reconstructing the power profile of a digital microphone coupled to a microelectromechanical (MEMS) device, wherein the power profile represents power consumption of the digital microphone over time between at least two operational modes of the digital microphone, and a reconstruction filter for modeling thermal and/or acoustic properties of the digital microphone; and a subtractor having a first input for receiving a signal from the digital microphone, a second input coupled to the cross-talk compensation component, and an output for providing a digital output signal.
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
H04R 3/06 - Circuits pour transducteurs pour corriger la fréquence de réponse des transducteurs électrostatiques
A gate driver has a supply voltage terminal, a bootstrap terminal connected to the supply voltage terminal, a driver having a power input terminal connected to the bootstrap terminal and an output connected to a gate control signal output terminal and configured to generate a gate drive signal at the gate control signal output terminal based on a voltage on the power input terminal, a clamp driver connected to the bootstrap terminal, a clamp transistor connected between a clamp signal input terminal and a reference voltage terminal and having a gate connected to the clamp driver, and an energy harvesting circuit connected between the clamp signal input terminal and the gate of the clamp transistor.
H03K 17/30 - Modifications pour fournir un seuil prédéterminé avant commutation
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
27.
SEMICONDUCTOR DEVICE HAVING A TRANSISTOR WITH ACTIVE MESAS AND DUMMY MESAS
A semiconductor device includes a transistor that has: a drift region of a first conductivity type in a semiconductor substrate having a first main surface; a body region of a second conductivity type between the drift region and the first main surface; trenches in the first main surface and patterning the semiconductor substrate into mesas including a first mesa and a dummy mesa, the trenches including an active trench and a dummy trenches arranged in a row; a gate electrode arranged in the active trench; and a source region of the first conductivity type in the first mesa. The first mesa is arranged adjacent to the active trench. The dummy mesa is arranged between each adjacent pair of the dummy trenches and does not include a source region.
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
28.
SECURE COMMUNICATIONS USING PRE-SHARED KEYS AND LIVE MEMBERSHIP
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message. The use of key counters may be extended to guard against weak replay attacks via the implementation of a live membership tracking solution, which defines one or more membership groups. Each node within a membership group may request, or "challenge" other nodes with the same membership group at any time to verify their online status, and this online status may be maintained over time.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
In some examples, this disclosure describes a method that comprises controlling power switches to deliver a current to an electric motor, wherein the power switches are arranged in a bridge (e.g., an H-bridge or an h-bridge) comprising a first high-side power switch, a first low-side power switch, and a second low-side power switch. Controlling the power switches to deliver the current to the electric motor may include controlling the first high-side power switch ON and controlling the second low-side power switch ON, wherein the current to the electric motor flows through the high-side power switch and through the second low-side power switch. The method may comprise determining the current to the electric motor based on a voltage drop over one of the power switches arranged in the bridge.
An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine a plurality of addresses of packed data and fetch the packed data from a memory device based on the plurality of addresses. The packed data is stored on the memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the fetched packed data to the processor, where the output data is configured according to the predefined data structure. The memory fetch device is configured to process the packed data in a predefined order.
A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A method for assigning an address to an electronic device, and devices and circuit arrangements for implementing the method. The method may comprise:
a) sending a general command from a controller of a circuit arrangement to all electronic devices of the circuit arrangement, wherein the general command prompts each electronic device to start sending a respective unique identifier (UID) of the respective electronic device;
b) sending the respective UIDs from the electronic devices bit-by-bit in parallel;
c) performing a bit-by-bit arbitration among the electronic devices based on the UIDs until only one electronic device remains active;
d) sending an electrical parameter from the active electronic device to the controller;
e) determining a property of the active electronic device from the electrical parameter; and
f) assigning an address to the active electronic device from a predetermined set of addresses.
A switched capacitor converter can comprise an input pad for applying an analog input voltage; an input capacitor, the first terminal of which is continuously electrically conductively connected to the input pad and the second terminal of which is electrically conductively connected to an input of an amplifier; the amplifier; and a switched capacitor circuit, which is electrically conductively connected to the amplifier input on the one hand, and can be switched between a reference potential and a predefined reference voltage on the other.
H02M 3/07 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des résistances ou des capacités, p. ex. diviseur de tension utilisant des capacités chargées et déchargées alternativement par des dispositifs à semi-conducteurs avec électrode de commande
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H03M 1/80 - Conversion simultanée utilisant des impédances pondérées
A substrate includes a dielectric insulation layer, a first metallization layer attached to a first side of the dielectric insulation layer, and a second metallization layer attached to a second side of the dielectric insulation layer opposite the first side. The second metallization layer includes one or more first areas and one or more second areas. The second metallization layer in the one or more first areas has a first thickness, and in the one or more second areas has a second thickness that is greater than the first thickness. Methods of producing the substrate are also described.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
35.
AREA OPTIMIZED MODIFIED CROSS PARITY CODE FOR FAST ERROR CORRECTION AND DETECTION
A solution is directed to determining an error in k data bits comprising the steps: determining the error, in particular the position of the error, based on M check bits and on n check bits; wherein the k data bits are arranged according to a structure; wherein the structure comprises the M check bits, wherein the M check bits are calculated based on the k data bits; wherein the structure comprises n groups, n being larger or equal to two, wherein each of the k data bits is associated with one of the n groups and wherein each of the n groups is associated with one of the n check bits.
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
36.
CIRCUIT FOR DISCHARGING A CAPACITOR USING POWER TRANSISTORS OPERATING IN NON-LINEAR MODE
A circuit includes a first power transistor and a second power transistor. The circuit also includes a controller configured to control the first power transistor to perform a sequence of first switching cycles by applying, for each switching cycle of the sequence of first switching cycles, a first gate voltage exceeding a threshold gate voltage so that the first power transistor operates according to a non-linear transfer function. The controller is also configured to control the second power transistor to perform a sequence of second switching cycles by applying, for each switching cycle of the sequence of second switching cycles, a second gate voltage exceeding the threshold gate voltage so that the second power transistor operates according to the non-linear transfer function. The controller is configured to cause the capacitor to discharge according to a sequence of discharge phases.
Motor controller circuitry configured to operate two or more motors by driving the motors connected to output terminals of the motor controller circuitry. Each output terminal of the motor controller circuitry may connect to a driver circuit of the motor controller circuitry. Two, or more, of the motors may share an output terminal. For motors that share an output terminal, the operation of a first motor may affect the operation of other motors connected to that shared output terminal. The motor controller circuitry may store information about which output terminals may be paired, that is, which output terminals may connect to the same motor. Based on pairing information stored by the motor controller circuitry, protection circuitry of the motor controller circuitry may operate to prevent nuisance shutdown of a motor because the operation of another motor that shares the same output pin.
H02P 5/68 - Dispositions spécialement adaptées à la régulation ou la commande de la vitesse ou du couple d’au moins deux moteurs électriques pour commander au moins deux moteurs dynamo-électriques à courant continu
This disclosure includes a power converter assembly comprising: a stack of multiple circuit layers; multiple transformer windings disposed in the stack of multiple circuit layers, the multiple transformer windings including one or more primary windings and one or more secondary windings; and a first connectivity interface operative to connect the stack of multiple circuit layers to a host substrate. The first connectivity interface may be disposed on a first surface of the stack of multiple circuit layers. The first surface such as edges of the multiple circuit layers may be disposed substantially orthogonal with respect to planar surfaces of each of the multiple circuit layers of the stack to provide advantageous output of an output voltage generated by the power converter assembly to a load such as through the host substrate.
H01F 41/04 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques pour la fabrication de noyaux, bobines ou aimants pour la fabrication de bobines
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
39.
METAL-FILLED CONTACT HOLE IN MICRO-FABRICATED DEVICE
A metal-filled contact hole is generated in micro-fabrication technology by forming a first metal layer over a substrate and a first interface metal layer over the first metal layer. A metal of the first interface metal layer is different from a metal of the first metal layer. A dielectric layer is formed over the first interface metal layer. A contact hole is formed in the dielectric layer. A second interface metal layer is formed over the first interface metal layer after forming the contact hole. A second metal layer is formed over the second interface metal layer. A metal of the second interface metal layer is different from a metal of the second metal layer. The substrate is annealed, such that an oxide layer previously formed on the first interface metal layer in a period between the formation of the first and second interface metal layers is diluted by diffusion.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
The implementation proposes a magnetoresistive sensor, including at least one xMR sensor element formed from a layer stack, having a magnetically free layer having a magnetically free vortex magnetization, and having at least one reference layer having a reference magnetization in a predetermined direction. Magnetically free layers having a magnetically free vortex magnetization that are arranged along the predetermined direction on opposite sides of the xMR sensor element and laterally adjacent to the xMR sensor element. The adjacent magnetically free layers can act as magnetic flux concentrators for the magnetoresistive sensor element arranged therebetween.
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
41.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device is disclosed. The semiconductor device includes a chip carrier having a first cavity and a second cavity. A semiconductor die is mounted in the first cavity. The semiconductor die includes a patterned top metallization layer having a first electrical contact pad. An insulating layer is arranged inside the second cavity. A first end of a first electrical conductor is arranged over the insulating layer and a second end of the first electrical conductor is arranged on the first electrical contact pad of the semiconductor die. An encapsulant encapsulates the semiconductor die, both ends of the first electrical conductor, and parts of the chip carrier. A method for manufacturing the semiconductor device is also disclosed.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
42.
ULTRA-WIDEBAND RADAR DEVICE, METHOD FOR AUTHORIZING A CONTROL ACTION AND METHOD FOR SECURE LOCALIZATION
An ultra-wideband (UWB) radar device including a transmitter configured to generate a first radio signal by modulating a first carrier signal with a first M-sequence and transmit the first radio signal, a receiver configured to receive a radio signal and correlate the received radio signal with a predetermined second M-sequence different from the first M-sequence and a controller configured to authorize a predetermined control action in reaction to a determination, based on the correlation result, that a device has responded to the first radio signal with a second radio signal generated by modulating a second carrier signal with the second M-sequence.
G01S 13/76 - Systèmes utilisant la reradiation d'ondes radio, p. ex. du type radar secondaireSystèmes analogues dans lesquels des signaux de type pulsé sont transmis
A power converter includes an autotransformer, first switches, and second switches. The autotransformer includes multiple windings. The first switches are coupled between an input node and an output node of the power converter. The second switches are coupled between a reference potential and the output node. Yet further, the first switches are operable to control switching of circuit paths including the multiple windings of the autotransformer. The second switches are operable to convey currents from the multiple windings of the autotransformer through the second switches to the output node.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
A configuration management resource as discussed herein applies configuration settings to test operation of a first capacitive coupled communication link. Via amplitude monitoring during the testing, the communication management hardware detects a respective performance of the first capacitive coupled communication link to convey communications for each of the applied configuration settings. The communication management hardware selects a first configuration setting amongst the applied configuration settings to control the operation of the first capacitive coupled communication link based on the determined performances. In one application, the best performance corresponds to maximizing an amplitude of an envelope signal associated with received communications.
A molded surface mount package includes: a power semiconductor die attached to a metallic pad with a first side facing the pad and a second (opposite) side facing away from the pad, the metallic pad forming a first power terminal exposed at a surface mounting side of the package; a second power terminal, a first sense terminal, and a gate terminal each exposed at the surface mounting side and spaced apart from the first power terminal; a first electrical connection between the second power terminal and a first power pad at the second side of the die; a second electrical connection between the gate terminal and a gate pad at the second side of the die; a third electrical connection between the first sense terminal and a first sense pad at the second side of the die; and a first redundant electrical connection for the second or third electrical connection.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
In an embodiment, a semiconductor device includes a Group III nitride-based substrate having a first major surface, a lateral Group III nitride-based device formed in the Group III nitride-based substrate, a first power contact and a second power contact arranged on the first major surface. At least one of the first power contact and the second power contact includes an electrode arranged on the first major surface, a field plate arranged on the electrode and having a lateral extent in a first direction parallel to the first major surface that is greater than a lateral extent of the electrode in the first direction, and a power metallic layer arranged directly on the field plate. The power metallic layer has a lateral extent in the first direction that is less than the lateral extent of the field plate in the first direction.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
47.
METHOD AND CIRCUITRY TO APPLY AN INDIVIDUAL DC OFFSET TO ELECTRODES ON A LARGE-SCALE ION TRAP QUANTUM COMPUTER
A device includes a plurality of digital-to-analog converters (DACs), a multiplexer, a plurality of electrodes including a first electrode, and a plurality of direct current (DC) offset circuits including a first DC offset circuit. At least one of the plurality of electrodes is located along a lane for movement of an ion. The multiplexer has multiple inputs coupled to the plurality of DACs and multiple outputs including a first output. The first output is configured to provide a first voltage. The first DC offset circuit is coupled between the first output and the first electrode. The first DC offset circuit is configured to add a first DC offset voltage to either the first voltage or the first voltage amplified by a first gain. The first DC offset voltage is configurable.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Chips [integrated circuits]; semiconductor devices;
authentication software; cloud computing software; computer
operating system software; security software; software
development kit [SDK]; integrated circuit cards [smart
cards]; radio-frequency identification (RFID) tags; internet
of things [IoT] sensors; semiconductor chips;
semiconductors; microprocessors; microcontrollers;
electronic components; wireless transmitting and receiving
equipment; integrated circuit modules; transmitters and
receivers; electronic navigational and positioning apparatus
and instruments; sensors for determining position. Research and development services; software as a service
[SaaS]; cloud computing; consulting in the field of cloud
computing networks and applications; design and development
of computer hardware and software; advisory services
relating to computer programming.
49.
SEMICONDUCTOR DEVICE COMPRISING A CARRIER, A SEMICONDUCTOR DIE AND A C-SHAPED CLIP CONNECTED BETWEEN THEM
A semiconductor device comprising a carrier, a semiconductor die disposed on the carrier and comprising a first contact pad on a first main face remote from the carrier, and a clip. The clip comprises a horizontal portion, a vertical portion, and a bent-back portion connected with the carrier.
A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
In an embodiment, a transistor device includes a semiconductor substrate having at least one transistor cell. The transistor cell includes an elongate trench and an elongate mesa. The elongate trench is arranged in the first major surface of the semiconductor substrate and includes an elongate gate electrode electrically separated from the semiconductor substrate by a gate dielectric. A first insulating layer arranged on the first major surface covers the elongate trench. An elongate contact connection strip arranged on the first insulating layer extends above and parallel to the elongate trench. The elongate contact connection strip is electrically connected to the elongate gate electrode in the elongate trench by at least one first contact that extends through the first insulating layer.
A system includes: an ion trap device; an application board; a base plate arranged on the application board and having one or more through-holes; a substrate having a first side and a second side, the ion trap device being arranged on the first side and the second side being arranged on the base plate; electronic circuitry and/or electrical components arranged on the application board and configured to generate one or more signals for the ion trap device; and one or more conductive traces arranged on the application board and electrically coupled to the electronic circuitry and/or electrical components. The one or more conductive traces are routed to the base plate. An electrical connection is formed between the one or more conductive traces and the second side of the substrate via the one or more through-holes of the base plate.
In accordance with an embodiment, a method for augmenting training data for a neural network includes: running a validation dataset through the neural network to provide a first output; analyzing the first output of the neural network to determine first correct predictions and first incorrect predictions using a classifier; mutating seeds of the validation dataset corresponding to the first correct predictions; running the mutated seeds through the neural network to provide a second output; analyzing the second output of the neural network to determine second correct predictions and second incorrect predictions using the classifier; determining whether there is an increase in neural network coverage for mutated seeds yielding the second correct predictions; and performing steps of mutating the seeds, running the mutated seeds through the neural network, and analyzing the second output of the neural network for the mutated seeds yielding the second correct predictions.
A device is provided. The device includes a first portion having a phase change switch device on a first substrate and a second portion having a semiconductor circuit on a second substrate. The first and second portions are bonded together. A method of manufacturing the device is also described.
A sensor device contains a magnetic field sensor chip having a front face, a rear face and a side surface connecting the front face and the rear face. The magnetic field sensor chip has a sensor element which is arranged on the front face and is configured to detect a magnetic field component running parallel to the front face. The magnetic field sensor chip furthermore has multiple first contact pads arranged on the front face, wherein all of the first contact pads arranged on the front face are arranged at an edge of the magnetic field sensor chip lying between the front face and the side surface.
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
56.
SEMICONDUCTOR DEVICES WITH BENT POLYIMIDE TAPE AND ASSOCIATED MANUFACTURING METHODS
A semiconductor device includes an electrically conductive carrier, a semiconductor chip arranged over a section of the carrier, and a dielectric material arranged between the carrier section and the semiconductor chip. The dielectric material galvanically isolates the carrier section and the semiconductor chip from one another. The dielectric material includes a polyimide tape, wherein an edge region of the polyimide tape is bent away from the carrier section.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H10N 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément galvanomagnétique ou à effet Hall couvert par les groupes
An apparatus includes a controller that controls a motor including multiple motor windings. During operation, the motor controller receives an error value indicating a difference between a current angular position of a rotor in the motor with respect to a reference angular position of the rotor. Based on the error value, the controller selects a first angle-to-torque converter function amongst multiple angle-to-torque converter functions in a piecewise angle-to-torque converter function. Via the first angle-to-torque converter function, the controller derives a torque value indicating a magnitude of torque to apply to the rotor. The controller applies the torque as indicated by the torque value to the rotor.
H02P 21/09 - Calcul de l’angle de phase du champ basé sur l’équation de la tension de rotor en additionnant la fréquence de glissement et une fréquence proportionnelle à la vitesse
58.
SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING A N-DOPED GROUP III NITRIDE CONTACT
In an embodiment, a semiconductor substrate is provided that includes a multilayer Group III nitride substrate having a first major surface and at least one heterojunction that is capable of supporting a two-dimensional charge gas. At least one contact includes a contact trench that extends into the multilayer Group III nitride substrate from the first major surface. The contact trench is filled with n-doped Group III nitride material to form an electrical connection to the two-dimensional charge gas. The semiconductor substrate further includes at least one dummy trench extending into the multilayer Group III nitride substrate from the first major surface. The dummy trench is partially filled with n-doped Group III nitride material. The dummy trench has a width B and the contact trench has a width b, where B≥1.1b.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/82 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement
A method for performing a sequential diagnosis in a power network is presented. The method comprises:
a) sending a diagnosis control signal from a controller to a power switch for starting the sequential diagnosis at an initial diagnosis state of the power switch and using timeouts of the diagnosis control signal for changing a present diagnosis state of the power switch;
b) if a timeout matches a predetermined time interval, continuing the sequential diagnosis by going on to a subsequent diagnosis state of the present diagnosis state; and
c) if a timeout exceeds a predetermined time threshold, resetting the sequential diagnosis by restarting at the initial diagnosis state.
A method for performing a sequential diagnosis in a power network is presented. The method comprises:
a) sending a diagnosis control signal from a controller to a power switch for starting the sequential diagnosis at an initial diagnosis state of the power switch and using timeouts of the diagnosis control signal for changing a present diagnosis state of the power switch;
b) if a timeout matches a predetermined time interval, continuing the sequential diagnosis by going on to a subsequent diagnosis state of the present diagnosis state; and
c) if a timeout exceeds a predetermined time threshold, resetting the sequential diagnosis by restarting at the initial diagnosis state.
Further, a power switch is presented.
G01R 31/327 - Tests d'interrupteurs de circuit, d'interrupteurs ou de disjoncteurs
G01R 31/00 - Dispositions pour tester les propriétés électriquesDispositions pour la localisation des pannes électriquesDispositions pour tests électriques caractérisées par ce qui est testé, non prévues ailleurs
60.
Power Semiconductor Device and Method of Producing a Power Semiconductor Device
A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type and load terminals at opposite first and second sides of the semiconductor body. The power semiconductor device is configured to conduct a forward load current between the load terminals. A trench grid structure extending from the first side into the semiconductor body includes a plurality of macro cells. Each macro cell includes at least one first type micro cell configured for the forward load current conduction and a number of second type micro cells not configured for the forward load current conduction. Each micro cell is laterally confined by a respective portion of the trench grid structure. In each macro cell, the number of the second type micro cells is equal to or greater than the number of first type micro cells.
According to one exemplary embodiment, a data processing device is described, having a plurality of data processing components which are configured to exchange respective synchronization information with one another in pairs at predefined synchronization points, and having a writable configuration memory configured to store, for each reset type of a plurality of reset types, whether the exchange of the respective synchronization information is required for all of the synchronization points, in order that the respective pair of data processing components may continue its processing beyond the synchronization points. The data processing components are configured to continue or not continue their processing beyond synchronization points in accordance with the content of the writable configuration memory in the absence of an exchange of synchronization information.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
62.
ELECTRONIC SYSTEM HAVING AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT
The present disclosure relates to an electronic system including a master IC, a slave IC and a serial communication interface having a bidirectional data line and a clock line. The master IC is configured to send a data request command to the slave IC via the data line. The slave IC is configured to begin providing requested data in response to the data request command. The slave IC is configured to deactivate the clock line after receiving a data read command and until the slave IC can provide the requested data. The master IC is configured to measure a duration of the deactivation of the clock line and to set a wait time between a next data request command and a next data read command according to the measured duration.
A semiconductor device includes an electrically conductive carrier and a semiconductor chip arranged over a first portion of the carrier. The semiconductor device further includes a dielectric material arranged between the first portion of the carrier and the semiconductor chip, wherein the dielectric material galvanically isolates the first portion of the carrier and the semiconductor chip. At least one of the first portion of the carrier or the semiconductor chip includes at least one of a rounded corner or a rounded edge.
G01R 33/00 - Dispositions ou appareils pour la mesure des grandeurs magnétiques
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
64.
Methods of Semiconductor Device Fabrication Involving Porous Silicon Carbide
A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants that define a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
An ultrasonic touch sensor includes a touch structure comprising a touch surface configured to receive a touch; an ultrasonic transmitter configured to transmit at least one ultrasonic transmit wave toward the touch structure; an ultrasonic receiver configured to receive ultrasonic reflected waves produced by a plurality of reflections of the at least one ultrasonic transmit wave and generate a measurement signal representative of the ultrasonic reflected waves; and a measurement circuit configurable in a first operation mode corresponding to an air environment and a second operation mode corresponding to a wet environment. The measurement circuit is configured to calculate a rate of change of a plurality of samples of the measurement signal, perform a first comparison based on the rate of change and a rate of change threshold, and operate in the second operation mode based on the rate of change satisfying the rate of change threshold.
G06F 3/041 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction
G06F 3/043 - Numériseurs, p. ex. pour des écrans ou des pavés tactiles, caractérisés par les moyens de transduction utilisant la propagation d'ondes acoustiques
66.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A SEMICONDUCTOR DEVICE
A transistor device of a semiconductor device includes trench(es) formed in a first major surface of a semiconductor substrate, each including a side wall extending from a base to the first major surface. The side wall includes an intermediate section located between lower and upper sections. A field plate is located in the trench, with a field dielectric on the base and sidewall of the trench. The field dielectric has a first thickness in the upper section and a second thickness greater than the first thickness in the lower section. The field dielectric thickness changes from the first thickness at a first boundary between the upper and intermediate sections to the second thickness at a second boundary between the lower and intermediate sections. A surface of the field dielectric has a concave form at the first boundary and a convex form at the second boundary. The second boundary is edgeless.
An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/288 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un liquide, p. ex. dépôt électrolytique
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
69.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The present application relates to a semiconductor device with a gate region and/or field electrode region in a vertical trench. A dielectric of the gate region and/or field electrode region includes silicon oxide doped with a semi-metal or alkali metal such as being doped with boron.
In an embodiment, a semiconductor device includes a semiconductor body having a first major surface, a second major surface opposing the first major surface, and at least one transistor device structure. A source pad and a gate pad are arranged on the first major surface. A drain pad and at least one further contact pad are coupled to a further device structure. The drain pad and the at least one further contact pad are arranged on the second major surface.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H10D 62/57 - Défectuosités physiques les défectuosités étant sur la surface du corps semi-conducteur, p. ex. le corps ayant une surface rugueuse
In accordance with an example embodiment, a method includes: obtaining an in-phase and quadrature (IQ) representation of radar data indicating a received radar signal, determining an approximation of the IQ representation, the approximation having a spiral configuration, and determining a phase of the received radar signal based on the approximation.
G01S 7/41 - Détails des systèmes correspondant aux groupes , , de systèmes selon le groupe utilisant l'analyse du signal d'écho pour la caractérisation de la cibleSignature de cibleSurface équivalente de cible
72.
SEMICONDUCTOR DEVICE WITH METAL STRUCTURE PASSIVATION
A semiconductor device includes a semiconductor substrate. A metal structure is disposed over the semiconductor substrate. A metal of the metal structure is Cu or a Cu-based alloy. A passivation layer is disposed over the metal structure. The passivation layer includes a first layer including CuSiN, and a second layer including Si, N and H. In atomic numbers, a ratio of Si to N is equal to or greater than 3.3/4. A method of manufacturing the semiconductor device is also described.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
73.
DUMMY LOAD FOR A WIRELESS TRANSMISSION ARRANGEMENT
A power amplifier arrangement, for one or more antennae, with a calibratable dummy load. The power amplifier arrangement includes a calibration arrangement that controls or defines an amount of power drawn by the dummy load responsive to a power-responsive parameter that changes responsive to an amount of power drawn by one or more power amplifiers of the power amplifier arrangement when amplifying an input signal to be transmitted by the antenna(e).
A cache system is provided for system with a CPU and memory. The CPU has a stack pointer register for storing a stack pointer. The stack pointer represents an address in main memory at the top of the stack. The cache system has a cache RAM structured into cache lines and cache controller circuitry. The cache controller circuitry is operable to: receive the stack pointer, store a first cache line containing the contents of a first address range of bytes of the main memory, the first address range including the stack pointer; and lock the first cache line to protect the first cache line from cache eviction.
An electronic control unit is presented. The electronic control unit comprises: a plurality of digital drivers, each digital driver being configured for controlling at least one load; a central microcontroller configured for controlling the digital drivers; and an interconnection for communication between the central microcontroller and the digital drivers, the interconnection comprising: at least one serial bus configured for transmitting digital signals between the central microcontroller and the digital drivers; and at least one communication protocol comprising a set of commands and a set of addresses for communication. Further, a method for controlling a load by using the electronic control unit as well as a use for an automotive application of the electronic control unit and the method are presented.
A package configured as power stage is disclosed. In one example, the package includes a first transistor chip and a second transistor chip being interconnected to form a half bridge, a driver chip configured for driving the first transistor chip and the second transistor chip, and an encapsulant at least partially encapsulating the first transistor chip, the second transistor chip. The driver chip, wherein the driver chip comprises electrically conductive driver pads, at least one of which being arranged on each of both opposing main surfaces of the driver chip, and comprises at least one electrically conductive driver through connection extending through the driver chip between said opposing main surfaces.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
77.
PROGRAMMABLE GATE DRIVER CIRCUIT FOR AN INTEGRATED POWER SWITCH
A gate driver circuit and a corresponding gate driver system is presented. The gate driver circuit may be configured to drive a gallium nitride GaN transistor. The gate driver circuit may comprise a communication interface configured to receive a gate driver parameter. The communication interface may be an asynchronous serial communication interface, such as e.g. an UART communication interface. The gate driver parameter may be forwarded from one gate driver circuit to the next using the asynchronous serial communication protocol. One or more digital isolators may be coupled between the gate driver circuits.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
78.
SEMICONDUCTOR PACKAGE HAVING A LEADFRAME WITH A METAL-PLATED BOND AREA
A semiconductor package includes a semiconductor die having a first surface and a second surface opposite the first surface. A die pad is disposed at the first surface of the semiconductor die. A leadframe includes a carrier section on which the semiconductor die is mounted. The semiconductor die is solder-bonded to the carrier section with the second surface facing the carrier section. A metal-plated bond area is provided on the carrier section of the leadframe. A metal of the metal-plated bond area is different from a metal of the leadframe. An electrical conductor is connected to the die pad and bonded to the metal-plated bond area. The metal-plated bond area has a substantially triangular shape.
A semiconductor die includes: a semiconductor substrate; a power transistor formed in the semiconductor substrate; a current sense device formed in the semiconductor substrate and occupying less area of the semiconductor substrate than the power transistor; a first contact pad electrically connected to a first load terminal of the power transistor; a second contact pad electrically connected to a sense terminal of the current sense device, the second contact pad being dedicated to current sensing only; and a resistive and/or diodic connection between the sense terminal of the current sense device and the first load terminal of the power transistor. The resistive and/or diodic connection is designed solely for ESD (electrostatic discharge) protection of the current sense device, by providing an ESD discharge path to the first load terminal of the power transistor.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
The disclosure relates to a semiconductor die, comprising: a first diode chain having a number n1 of diode junctions connected in series, where n1≥1; a second diode chain having a number n2 of diode junctions connected in series, where n2≥1; the first diode chain and the second diode chain to be biased with the same current as a temperature sensor, wherein the first diode chain and the second diode chain differ from each other in their respective number n1, n2 of junctions and/or in a doping concentration of at least one of the junctions.
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
G01R 19/10 - Mesure d'une somme, d'une différence, ou d'un rapport
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
81.
SYSTEM AND METHOD FOR USING PSEUDO-LABELS WITH A MACHINE-LEARNING MODEL
In accordance with an embodiment, a method includes obtaining a machine-learning model in a first training state; using the machine-learning model in the first training state to infer predictions based on multiple measurement feature vectors obtained at an agent; based on the predictions, populating a first training dataset using labels for a first subset of the multiple measurement feature vectors; based on the predictions, populating a second training dataset using pseudo-labels for a second subset of the multiple measurement feature vectors; and determining a second training state of the machine-learning model based on the first training dataset and the second training dataset.
A transistor device includes a plurality of transistor cells. Each transistor cell includes two load electrodes and a control electrode. The two load electrodes of the transistor cells are arranged spaced apart from each other in a first direction. A first pitch between adjacent load electrodes of a first subset of pairs of the two load electrodes is smaller than a second pitch between adjacent load electrodes of a second subset of pairs of the two load electrodes. Airgaps are provided between adjacent load electrodes of the second subset of pairs.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
83.
Switch Module Having a Short Circuit Detection Circuit
Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch and a short circuit detection circuit. The transistor switch includes a control terminal, a first load terminal and a second load terminal. The short circuit detection circuit is configured to detect a short circuit state between the first load terminal and the second load terminal and to automatically switch off the transistor switch without additional signaling, by automatically electrically coupling the control terminal to the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is energized by a voltage between the control terminal and the first load terminal.
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
84.
ENCAPSULATED PACKAGE WITH CARRIER, LAMINATE BODY AND COMPONENT IN BETWEEN
A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
85.
LEVEL SHIFTER HAVING A CROSS-COUPLED CURRENT MIRROR CIRCUIT FOR REDUCING OR CANCELLING COMMON MODE SLEW CURRENT
A level shifter includes: a low voltage domain configured to output non-overlapping first and second current pulses based on opposite edges of a logic input signal; and a high voltage domain comprising a latch and a current mirror circuit configured to mirror the non-overlapping first and second current pulses such that the latch is set when the first current pulse is active and reset when the second current pulse is active. The current mirror circuit includes a first mirroring path for the first current pulse and a second mirroring path for the second current pulse. The level shifter has a common mode slew current that is added to the non-overlapping first and second current pulses. The first mirroring path and the second mirroring path are cross-coupled such that the common mode slew current is reduced or cancelled before the non-overlapping first and second current pulses are input to the latch.
A gate driver circuit includes a high-side region that operates in a first voltage domain; a low-side region that operates in a second voltage domain lower than the first voltage domain; a gate driver configured to drive a power switch between an on-state and an off-state; at least one capacitor cross-coupled to the high-side region and the low-side region; a sensing circuit coupled to the at least one capacitor and configured to provide a sense value representative of a voltage transient of the power switch; a comparator circuit configured to compare the sense value to a threshold, and further configured to generate a comparison result based on whether the sense value satisfies the threshold; and a short circuit detector configured to detect a short circuit event based on the on-state of the power switch being detected and based on the comparison result indicating that the sense value satisfies the threshold.
H03K 17/06 - Modifications pour assurer un état complètement conducteur
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
87.
Devices and Methods for Periodically Cooling Trapped Ions
A micro-fabricated device for controlling trapped ions includes a storage unit configured to store and cool the trapped ions. The storage unit includes a first cooling zone configured to cool ions located in the first cooling zone based on a laser cooling technique. The storage unit further includes a first closed shuttling path extending through the first cooling zone and configured to shuttle the trapped ions to periodically pass through the first cooling zone. A method for storing and cooling trapped ions in a device for controlling trapped ions is also described.
H01J 49/42 - Spectromètres à stabilité de trajectoire, p. ex. monopôles, quadripôles, multipôles, farvitrons
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H01J 49/04 - Dispositions pour introduire ou extraire les échantillons devant être analysés, p. ex. fermetures étanches au videDispositions pour le réglage externe des composants électronoptiques ou ionoptiques
A method for calibrating a phase modulator includes determining a set of phase measurement values, calculating a value for each error parameter of a set of error parameters corresponding to an error model related to the phase modulator using the set of phase measurement values and at least one analytical function derived from the error model and storing for each error parameter of the set of error parameters the calculated value in a memory for setting a phase correction to the phase modulator.
H01Q 3/34 - Dispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la phase relative ou l’amplitude relative et l’énergie d’excitation entre plusieurs éléments rayonnants actifsDispositifs pour changer ou faire varier l'orientation ou la forme du diagramme de directivité des ondes rayonnées par une antenne ou un système d'antenne faisant varier la distribution de l’énergie à travers une ouverture rayonnante faisant varier la phase par des moyens électriques
89.
PROCESSING ARCHITECTURE SUPPORTING AN OUT OF ORDER NUMBER THEORETIC TRANSFORM
The described techniques increase the performance and efficiency of hardware (HW) accelerators that may be used as part of post-quantum cryptography (PQC) applications. Such hardware accelerators comprise those configured to perform so-called “butterfly operations,” which process coefficients of a polynomial over which a number theoretic transform (NTT) operation is performed. The techniques include the use of re-ordering buffers to ensure an efficient memory storage solution that allows for the computation of a single address location when reading the inputs to the next stages of the hardware accelerator. The described architecture facilitates flexible and scalable solutions to meet the high performance demands of PQC processing.
A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/76 - Réalisation de régions isolantes entre les composants
H01L 21/765 - Réalisation de régions isolantes entre les composants par effet de champ
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
91.
CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM
Systems, methods, and circuitries are provided for detecting lost interrupt events in a reduced instruction set computer-V (RISC-V) architecture. An example architecture includes an advanced platform level interrupt controller (APLIC) and an incoming message signaled interrupt (MSI) controller (IMSIC) coupled to the APLIC. The APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority and each vector comprises a vector interrupt lost (IL) bit. The IMSIC is configured to receive MSI from the APLIC and to maintain an interrupt file that includes a set of a set of interrupt lost (IL) bits indexed by interrupt priority.
A driving safety system for a motor vehicle with at least one wheel speed sensor is disclosed, which is configured to determine the actual wheel speed on a wheel, and a driving safety control unit configured to receive a wheel speed signal generated by the wheel speed sensor, where the wheel speed signal represents a determined actual wheel speed. The wheel speed signal is transmitted via an unprotected transmission channel between the wheel speed sensor and the driving safety control unit. The driving safety control unit is configured to receive a travel signal that correlates with the actual vehicle speed and to compare the travel signal with the wheel speed signal to check the wheel speed signal for plausibility. The movement signal is transmitted to the driving safety control unit via a safe transmission channel.
B60W 50/00 - Détails des systèmes d'aide à la conduite des véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier
B60W 10/184 - Commande conjuguée de sous-ensembles de véhicule, de fonction ou de type différents comprenant la commande des systèmes de freinage avec des freins de roues
B60W 10/30 - Commande conjuguée de sous-ensembles de véhicule, de fonction ou de type différents comprenant la commande d'équipements auxiliaires, p. ex. des compresseurs pour la climatisation ou des pompes à huile
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message.
A circuit arrangement for operating a resistive sensor element is described. According to an example implementation, the circuit arrangement includes a first supply terminal and a second supply terminal, between which is applied a supply voltage during operation, and a sensor circuit having at least one resistive sensor element. The sensor circuit has a first circuit node and a second circuit node for applying a sensor voltage, wherein the first circuit node is connected to the first supply terminal. The circuit arrangement further includes a sensor supply circuit, which is configured to electrically couple, during a measurement time interval, a charged capacitor to the second circuit node in such a way that the sensor voltage between the first circuit node and the second circuit node is greater than the supply voltage.
G01N 27/18 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps chauffé électriquement dépendant de variations de température produite par des variations de la conductivité thermique d'un matériau de l'espace environnant à tester
G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes
A transient voltage suppressor (TVS) circuit is described. The TVS circuit includes a semiconductor substrate having a first TVS device and a second TVS device electrically connected in series. The TVS circuit further includes a resistor. The resistor and at least one of the first TVS device and the second TVS device are electrically connected in parallel. A method of manufacturing the TVS circuit is also described.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
96.
GROUP III NITRIDE TRANSISTOR DEVICE AND METHOD FOR FABRICATING A GROUP III NITRIDE TRANSISTOR DEVICE
A Group III nitride transistor device includes: a Group III nitride substrate having a first major surface, a Group III nitride channel layer, and a Group III nitride barrier layer arranged on the Group III nitride channel layer and forming a heterojunction therebetween; transistor cells; and a metallization structure including first and second electrically conductive layers. The first electrically conductive layer includes for each transistor cell a source finger and a drain finger arranged on the first major surface. The second electrically conductive layer includes a source bus and a drain bus. The source bus extends between and electrically connects the source fingers of the transistor cells and extends over and is electrically insulated from the drain fingers. The drain bus extends between and electrically connects the drain fingers of the transistor cells and extends over and is electrically insulated from the source fingers.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 27/08 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type
H01L 29/20 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des composés AIIIBV
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
97.
PAD OVER ACTIVE SENSOR CELLS INTEGRATED IN A CHIP PACKAGE
A chip-scale package includes a magnetic sensor integrated circuit (IC) and a conductive contact pad. The magnetic sensor IC includes an IC layer stack comprising a plurality of isolation layers and a plurality of conductive layers; and a magnetoresistive sensing element integrated in the IC layer stack. The magnetoresistive sensing element includes a reference layer having a fixed reference magnetization aligned with a magnetization axis, and a magnetic free layer having a magnetically free magnetization. The magnetically free magnetization is variable in a presence of an external magnetic field. The conductive contact pad is arranged on or integrated in the IC layer stack. Moreover, the conductive contact pad is arranged over the magnetoresistive sensing element such that the conductive contact pad and the magnetoresistive sensing element at least partially vertically overlap.
H10N 59/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément galvanomagnétique ou à effet Hall couvert par les groupes
G01R 33/00 - Dispositions ou appareils pour la mesure des grandeurs magnétiques
G01R 33/09 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs magnéto-résistifs
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A magnetic field sensor chip includes an input terminal configured to receive an external bias current from an external current source; an internal current generator configured to split the external bias current into a plurality of internal bias currents, including a first internal bias current and a second internal bias current; a Hall sensor configured to be biased by the first internal bias current and set at a first operating point based on the first internal bias current, wherein the Hall sensor is further configured to generate a sensor signal based on a magnetic field and the first operating point; and an amplifier configured to be biased by the second internal bias current and set at a second operating point based on the second internal bias current. The amplifier is configured to amplify the sensor signal into an amplified sensor signal based on the second operating point.
G01R 33/07 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques en utilisant des dispositifs galvano-magnétiques des dispositifs à effet Hall
G01R 15/20 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs galvano-magnétiques, p. ex. des dispositifs à effet Hall
99.
ENCAPSULANT WITH ORGANIC CONSTITUENT AND INORGANIC CONSTITUENT HAVING ADJUSTED RELATIVE DIELECTRIC CONSTANT
An encapsulant for an electronic package is disclosed. In one example, the encapsulant comprises at least one organic constituent, and at least one inorganic constituent. A difference between the relative dielectric constant of the at least one organic constituent and the relative dielectric constant of the at least one inorganic constituent divided by the relative dielectric constant of the at least one organic constituent has an absolute value of not more than 0.2.
A method of manufacturing a superconductive integrated circuit on a substrate includes forming a first superconductive layer of a superconductive material over the substrate. A Josephson junction (JJ) layer stack including a JJ barrier layer is formed over the first superconductive layer. The JJ layer stack is structured to form a JJ structure. The first superconductive layer is structured to form a structured first superconductive layer. A dielectric cover layer is formed over the JJ structure. The dielectric cover layer is structured a first time to expose an upper side of the JJ structure. A second superconductive layer of a superconductive material is formed over the dielectric cover layer. The second superconductive layer is structured to form a structured second superconductive layer.
