Systems, methods, and circuitries are provided for enabling in-field re-marking of micro controllers. In one example, a micro-controller unit (MCU), includes one or more processors; non-reprogrammable memory, reprogrammable memory, and marking circuitry. The non-reprogrammable memory is configured to store an umbrella license file defining a first set of MCU functions or MCU resources that are enabled for execution or access by the one or more processors and a second set of MCU functions or MCU resources that are permanently disabled for execution or access by the one or more processors. The reprogrammable memory is configured to store an actual license file defining a third set of MCU functions or MCU resources that are licensed for execution or access by the one or more processors. The marking circuitry configured to control access to the MCU functions and MCU resources based on the umbrella license file and the actual license file.
A method for producing a semiconductor module arrangement includes: arranging a molding tool vertically above a substrate of the semiconductor module arrangement, a plurality of pins and/or rivets being arranged on the substrate, each pin and/or rivet having essentially the same height in a vertical direction perpendicular to the substrate, the molding tool including a first subset and a second subset of cover elements, each cover element of the first subset being arranged vertically above a different one of the pins and/or rivets, the cover elements of the second subset not being arranged vertically above any pin or rivet; pressing each cover element of the first subset on the respective pin or rivet; and pouring a first material on the substrate. The first material is prevented from covering a top surface of each of the pins and/or rivets by the respective cover elements of the first subset.
A semiconductor device includes a semiconductor body having a base substrate and an upper region of type III-V semiconductor material formed on the base substrate, the upper region having one or more heterojunction interfaces between two layers of type III-V semiconductor material, a trench that extends from an upper surface of the semiconductor body into the upper region past the one or more heterojunction interfaces; and a resistor having a strip of type III-V semiconductor material formed within the trench.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
4.
ELECTRONIC CIRCUITS AND METHODS FOR MONITORING LEAKAGE CURRENT
CURRENT
CURRENT
An electronic circuit and a method is provided for detecting a leakage current in a second circuit. According to an embodiment, the electronic circuit comprises timing circuitry and monitoring circuitry, wherein the timing circuitry is configured to automatically activate the monitoring circuitry at time intervals set by the timing circuity to repeatedly measure a measurement current indicative of a leakage; and wherein the monitoring circuitry is configured to compare the measurement current measured at each interval to a leakage threshold current, wherein when the measurement current exceeds the leakage threshold current, the monitoring circuitry is configured to send an indication to control circuitry of the second circuit.
G01R 31/52 - Testing for short-circuits, leakage current or ground faults
B60L 3/00 - Electric devices on electrically-propelled vehicles for safety purposesMonitoring operating variables, e.g. speed, deceleration or energy consumption
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
5.
METHOD FOR OPERATING A POWER CONVERTER, POWER CONVERTER CIRCUIT, CONTROLLER AND COMPUTER PROGRAM
A method for operating a power converter comprises: providing an asymmetrical half bridge flyback converter circuit comprising a half bridge with a high side switch and a low side switch and a transformer with a primary winding and a secondary winding, wherein the primary winding is connected to the half bridge and the secondary winding is connected to an output of the power converter, providing a clamping circuit coupled via an auxiliary winding of the transformer to the primary winding, wherein the clamping circuit comprises a third switch and a second diode connected in series, providing a controller configured to switch on and switch off the high and low side switches and the third switch and configured to operate the power converter in a conduction mode.
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 17/16 - Modifications for eliminating interference voltages or currents
6.
ELECTRONIC SYSTEM HAVING INTERMETALLIC CONNECTION STRUCTURE WITH CENTRAL INTERMETALLIC MESH STRUCTURE AND MESH-FREE EXTERIOR STRUCTURES
An electronic system is disclosed. In one example, the electronic system comprises an at least partially electrically conductive carrier, an electronic component, and an intermetallic connection structure connecting the carrier and the component. The intermetallic connection structure comprising an intermetallic mesh structure in a central portion of the intermetallic connection structure, and opposing exterior structures without intermetallic mesh and each arranged between the intermetallic mesh structure and the carrier or the component.
Disclosed is a power converter. The power converter includes: a first converter stage (1) configured to receive three alternating input voltages (Va, Vb, Vc) at input nodes (11a, 11b, 11c) and provide a pulsating output voltage (V1) at an output (12, 13); a second converter stage (2) configured to receive an input voltage (V2) at an input (22, 23) and provide an output voltage (Vo) at an output (24, 25); and a link circuit (3) comprising a link (31, 32) coupled between the output (12, 13) of the first converter stage (1) and the input (22, 23) of the second converter stage (2), and supply nodes (33, 34) coupled to the second converter stage (2). The link circuit (3) is configured to regulate the output current (11) of the first converter stage (1) and regulate an output voltage (Vo) at the output of the second converter stage (2).
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
H02M 7/25 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only arranged for operation in series, e.g. for multiplication of voltage
8.
AMPLIFIER CIRCUIT HAVING A COIL STRUCTURE WITH MUTUALLY INDUCTIVELY COUPLED COILS
An amplifier circuit includes a first amplifier, a second amplifier, an output connection, and a coil structure. The output connection connects outputs of the first amplifier and second amplifier with a load node. The coil structure includes a first coil and a second coil that are mutually inductively coupled with one another. A first DC voltage feeds the first amplifier through the first coil. A second DC voltage feeds the second amplifier. The output of the first amplifier is connected to the load node through the second coil.
An amplifier circuit includes a first amplifier, a second amplifier, an output connection, and a coil structure. The output connection connects outputs of the first amplifier and second amplifier with a load node. The coil structure includes a first coil and a second coil that are mutually inductively coupled with one another. A first DC voltage feeds the first amplifier through the first coil. A second DC voltage feeds the second amplifier. The output of the first amplifier is connected to the load node through the second coil.
A responder node of a serial communications system is configured to receive a header part of a subscriber message frame with an identifier field that specifies the responder node is to send reply data to a commander node. During a response part of the subscriber message frame, the responder node sends reply data along with other reply data from at least one other responder node specified by the identifier field.
A soldering method is provided. The soldering method includes arranging a solder preform between a first metal surface and a second metal surface, arranging a reducing component between the first metal surface and the solder preform and between the second metal surface and the solder preform, and heating the solder preform to its melting temperature, which is higher than a boiling point of the reducing component, wherein the reducing component consists of: a reducing agent, or consists of: a reducing agent and a solvent, wherein the reducing agent consists of at least one of the following: a glycerol or its derivatives, a polyhydric alcohol (HOCH2(CHOH)nCH2OH with n=1 to 100), a polyethylene glycol (H—(O—CH2-CH2)n-OH (with n=1 to 1000), and a glycol (aliphatic diol), and wherein the solvent consists of at least one of the following: water, a glycol, an ether, glycolether, ethanol, propanol, and hexanol.
B23K 1/20 - Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
B23K 35/36 - Selection of non-metallic compositions, e.g. coatings, fluxesSelection of soldering or welding materials, conjoint with selection of non-metallic compositions, both selections being of interest
12.
METHOD FOR MANUFACTURING A CHIP PACKAGE, CHIP PACKAGE, WAFER STRUCTURE, AND METHOD FOR PROCESSING A CHIP PACKAGE COMPONENT
A chip package and method for manufacturing a chip package is provided. In one example, the method includes forming a metal oxide layer on a chip structure and applying a saline solution to the metal oxide layer to form a layered double hydroxide (LDH).
Implementation of an apparatus (circuitry, system, etc.) as discussed herein includes capacitor circuitry (or other suitable energy storage entity) operative to store energy. The implemented apparatus or system as discussed herein further includes charge-discharge converter circuitry as well as a controller. The charge-discharge converter circuitry is disposed in series between a first node of a first power converter and a second node of the first power converter, where the first power converter may be operative to convert a first voltage received at the first node into a second voltage outputted from the second node. The controller is operative to: i) receive feedback associated with conversion of the first voltage into the second voltage via the first power converter, and ii) based on the received feedback, control operation of the charge-discharge circuitry to switch between charging the capacitor circuitry and discharging the capacitor circuitry.
A tank apparatus for an electronic inhaler is provided. The tank apparatus includes an electronic heater configured to heat a liquid to be vaporized, an authentication circuit configured to authenticate the tank apparatus, and a first tank terminal and a second tank terminal, wherein the first tank terminal and the second tank terminal are configured for electrically connecting a first inhaler terminal and a second inhaler terminal of the electronic inhaler, wherein the first tank terminal, the electronic heater and the second tank terminal form a first electrical circuit allowing a current flow in a first direction and limiting a current flow in an opposite second direction, and wherein the first tank terminal, the authentication circuit and the second tank terminal form a second electrical circuit allowing a current flow in the second direction and limiting a current flow in the first direction.
A method of controlling an electric motor includes: storing, in a microcontroller, a first weight matrix calculated to transform an arbitrary set of multi-phase variables of any shape to equivalent quadrature-direct (Q-D) reference frame components, such that the Q-D reference frame components appear as dc signals in steady state, the first weight matrix being a function of a reference frame angle in the Q-D reference frame; calculating, by the microcontroller, a second weight matrix from the first weight matrix and a constant matrix, the second weight matrix being a function of the reference frame angle; and commutating winding currents in the electric motor based on the second weight matrix. A corresponding control system for an electric motor is also described.
A transmitter circuit disposed at a first terminal of a capacitor coupled communication link receives a first signal. Based on the first signal, the transmitter circuit produces a second signal (transmitter drive signal), which may be a first differential signal including a first sub-signal and a second sub-signal. The transmitter circuit generates the first sub-signal in accordance with a first duty cycle; the transmitter circuit generates the second sub-signal in accordance with a second duty cycle. The second duty cycle is different than the first duty cycle. The transmitter circuit further transmits the first differential signal including the first sub-signal and the second sub-signal over a capacitive coupled communication link to a receiver circuit at a second terminal of the capacitor coupled communication link. The implementation of the transmitter drive signal as discussed herein results in a stronger signal received at a receiver circuit with respect to a noise floor.
A low drop-out (LDO) voltage regulator circuit includes an LDO voltage regulator including a pass device coupled to a power supply voltage, wherein the pass device includes a bulk node; an amplifier having an input coupled to the power supply voltage; a first capacitor coupled between an output of the amplifier and the bulk node of the pass device; and a first resistor coupled between the bulk node of the pass device and the power supply voltage having a low ohmic value in a first operating mode and a high ohmic value in a second operating mode.
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
18.
Package with Lateral Semiconductor Flip-Chip and Bond Wires Crossing and Bridging a Routing Structure
A package includes a carrier having a main surface on and/or in which an electrically conductive routing structure is formed, a first electronic component being a lateral semiconductor chip and being mounted in a flip-chip configuration on the carrier to be electrically coupled with the routing structure, and a plurality of electrically conductive bond wires electrically connecting the carrier and/or the first electronic component. The bond wires, in a plan view on the carrier, cross the routing structure in at least one crossing region and extend above or below the routing structure for bridging the routing structure in the at least one crossing region.
A driver chip configured to drive a gate of a power transistor comprises: a slope reference configured to provide a first voltage, an output configured to be connected to a gate terminal of a power transistor, a shaping capacitor configured to be connected between the slope reference and a drain terminal of the power transistor, and a buffer connected between the slope reference and the output and configured to be provided with the first voltage.
A silicon controlled rectifier (SCR) circuit includes a first well of a first doping type, including a second well of a second doping type, a third well of the second doping type, and a fourth well of the first doping type; a fifth well of the second doping type adjacent to the first well, including a sixth well of the first doping type, a seventh well of the first doping type, and an eighth well of the second doping type; a first metal stripe contacting the second well and the fourth well; a second metal stripe contacting the third well and the sixth well; and a third metal stripe contacting the seventh well and the eighth well.
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
21.
METHOD AND DEVICE FOR DETERMINING A RELATIVE POSITION OF RADIO DEVICES
A method for determining a relative position of radio devices is provided. In one example, a method includes transmitting a ranging initiation signal to first and second responder devices and receiving first and second ranging response signals from the first and second responder devices. A first ranging result signal is received from the first responder device that includes timing information related to a time at which a ranging signal transmitted by the second responder device was received by the first responder device. A second ranging result signal is received from the second responder device that includes timing information related to at time which a ranging signal transmitted by the first responder device was received by the second responder device. Position-related information for the device and the first and second responder devices is determined based on the first and second ranging response signals and the first and second ranging result signals.
A sensor calibration system includes a first gas concentration sensor that measures a thermal conductivity of a target gas, a second gas concentration sensor that measures the thermal conductivity of the target gas, and a calibration circuit. The first gas concentration sensor includes a first measurement chamber. The second gas concentration sensor includes a second measurement chamber. The calibration circuit is configured to, while the first measurement chamber contains a measurement gas, a pressure inside the first measurement chamber is varied, and a temperature inside the first measurement chamber is fixed, acquire a first plurality of measurements from the first gas concentration sensor. The calibration circuit is configured to, while the second measurement chamber contains the measurement gas, a pressure inside the second measurement chamber is varied, and a temperature inside the second measurement chamber is fixed, acquire a second plurality of measurements from the second gas concentration sensor.
An inductor module includes: a magnetic core having a first main surface, a second main surface opposite the first main surface, and a plurality of side faces extending between the first and the second main surfaces; an inductor extending from the first main surface to the second main surface through the magnetic core; and a metallic body adjoining the first main surface, the second main surface and at least one of the side faces of the magnetic core. The metallic body and the inductor are electrically isolated from one another. Also described are a power stage module that includes the inductor module and methods of producing the inductor module and the power stage module.
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor package includes a leadframe having a die pad and a plurality of leads. The die pad has a first main face and a second main face opposite to the first main face. A semiconductor transistor die is disposed on the first main face of the die pad. A layer structure is disposed on the second main face of the die pad. The layer structure includes a ceramic layer. An encapsulant embeds the die pad, inner portions of the leads, the semiconductor transistor die, and the layer structure. At least a portion of an uppermost layer of the layer structure is exposed to the outside.
Embodiments comprise a semiconductor device comprising: a gate node a drain node a source node and a gate bus, wherein the gate bus is connected to the gate node, a source structure and a drain structure, wherein the source structure is coupled to the source node and wherein the drain structure is coupled to the drain node, a plurality of replication units, wherein a respective replication unit of the plurality of replication units comprises a gate finger; wherein the gate fingers, the source structure and the drain structure are arranged to form a transistor structure, and a plurality of resistors, wherein each resistor connects one of the gate fingers to the gate bus.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/05 - Manufacture or treatment characterised by using material-based technologies using Group III-V technology
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
An apparatus for force measurement includes a cavity package and a pressure sensor arranged in the cavity package. Additionally, the apparatus includes a first material and a second material arranged in the cavity package. The first material encloses the pressure sensor. The second material covers the first material, exhibits a higher Young's modulus than the first material, and is configured to transfer an external force applied to the second material to the first material. The pressure sensor is configured to measure pressure within the first material resulting from the external force.
G01L 1/14 - Measuring force or stress, in general by measuring variations in capacitance or inductance of electrical elements, e.g. by measuring variations of frequency of electrical oscillators
27.
PHOTOACOUSTIC GAS SENSOR AND LEAKAGE DETECTION SYSTEM
A photoacoustic gas sensor includes a substrate and a measurement cell within the substrate. An emitter is mounted on the substrate and configured to emit light into the measurement cell. A sensor is mounted on the substrate and configured to measure pressure variations in the measurement cell.
A transistor device and a method for producing a transistor device are disclosed. The transistor device includes a semiconductor body; a drift regionof a first doping type in the semiconductor body; a gate padformed above a first surfaceof the semiconductor body; a shielding structurearranged between the gate padand the drift regionand comprising a plurality of shielding electrodeseach arranged in a respective shielding trenchand dielectrically insulated from the gate padand the semiconductor body; a source padformed above the first surfaceof the semiconductor bodyand connected to the shielding electrodes; and a plurality of transistor cellseach comprising a gate electrodeconnected to the gate pad.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/00 - Electrodes of devices having potential barriers
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
29.
SUBSTRATE ASSEMBLY WITH TEST INTERFACE TO CONFIGURE ONBOARD CIRCUITRY
A layered assembly as discussed herein can be configured to include a circuit substrate and a test interface. The circuit substrate can be configured to include a first circuit substrate portion and a second circuit substrate portion; the first circuit substrate portion including first circuitry. The test interface can be configured to include at least one electrically conductive path extending between the second circuit substrate portion and the first circuit substrate portion, where the at least one electrically conductive path supports configuration of the first circuitry. Sometime subsequent to configuring the first circuitry, a fabricator resource can be configured to physically partition the first circuit substrate portion and the second circuit substrate portion, resulting in severing of the at least one electrically conductive path.
The disclosed concepts relate to a matrix transformer comprising a plurality of ferromagnetic legs, a plurality of primary windings, and a plurality of secondary windings. Each secondary winding is wound around each leg a same number of times. For each leg, the sum of the number of turns made by the plurality of primary windings around the respective leg is the same. Further, a total number of turns made by each respective primary winding around the plurality of legs does not equal an integer multiple of the number of legs. As a result, for a given/target number of legs, and for a given number of turns of the secondary winding, a greater number of turns ratios between the primary and secondary windings are possible, as the restriction of having the number of turns of each primary winding equal to an integer multiple of the number of legs is removed.
H01F 41/02 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets
A snap-in connector includes a body having a radial-symmetric inserting portion and a base portion. A first circumferential groove is arranged at the inserting portion spaced apart from the base portion in an inserting direction of the connector. The inserting portion includes an end portion spaced apart from the first circumferential groove in the inserting direction. A second circumferential groove is arranged at the inserting portion between the end portion and the first circumferential groove. The snap-in connector further includes a first gasket arranged in the first groove configured to seal-up in a radial direction, and a radial symmetric locking spring accommodated in the second groove.
A cooling device is configured for cooling electrical components, the device includes a first heat transfer portion and a second heat transfer portion, wherein the first heat transfer portion is configured to conduct heat from a heat source to the second heat transfer portion, the first heat transfer portion including a vapor chamber of an electrically isolating material, configured to be coupled to the heat source, an electrically isolating liquid contained inside the vapor chamber, a heat spreading element forming at least in part one sidewall of the vapor chamber, and wherein the second heat transfer portion is at least in part in thermal contact with the heat spreading element.
A power semiconductor package includes: a first FET die arranged on a power electronic substrate such that a first side of the die faces away from the substrate and a second side of the die faces a first side of the substrate; a second FET die arranged on top of the first side of the first FET die such that a second side of the second die faces the first die; a first conductive layer electrically connecting the dies to each other; an encapsulation body encapsulating the dies; a metal clip having a first portion arranged over a first side of the second die and electrically connected to a first power electrode on the first side of the second die, and a second portion arranged laterally next to the dies; and a connector electrically connecting a control electrode on the first side of the first die to the metal clip.
A sensor device is configured to be attached to a submount, the submount forming a main current path. The sensor device includes: a first connector to connect to the main current path; a second connector to connect to the main current path; an electrical bypass element arranged between and coupled to the first connector and the second connector, the bypass element forming a bypass current path; an insulator body receiving the bypass element; and a sense circuit including at least one magnetic field sensitive element configured to sense a magnetic field induced by a bypass current through the bypass element.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 3/00 - Apparatus or processes specially adapted for the manufacture of measuring instruments
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
A digital microphone includes a segmented microelectromechanical system (MEMS) device for generating a first signal having a first response to an ambient signal and for generating a second signal having a second response to the ambient signal; and a combination circuit for dynamically combining the first signal and the second signal to generate a combined output signal.
An approach is proposed for processing a value that is determined from a set of N ternary memory cells, including the steps of: (i) reading the set of ternary memory cells and determining the ternary symbol H, M or L contained in the respective ternary memory cell; (ii) determining a first binary sequence based on the ternary symbols H of the set of read ternary memory cells; (iii) determining a second binary sequence based on the ternary symbols H and M of the set of memory cells; (iv) determining a third binary sequence based on the first and second binary sequence, wherein the number of bits of the third binary sequence is reduced compared with the number of bits of the first and second binary sequence, (v) determining a composite binary value based on the first binary sequence and the third binary sequence, and (vi) processing the composite binary value.
According to various embodiments, a motor controller is described, including an estimation circuit configured to implement a state observer and an input configured to receive measurements representing a sequence of motor shaft angles of a motor and to supply the measurements to the state observer, wherein the estimation circuit is configured to perform motor shaft angle or motor shaft rotation speed estimation by generating, by means of the state observer, a time series representing motor shaft angle estimates, motor shaft rotation speed estimates or motor shaft angle estimation errors from the measurements, filtering the generated time series by a machine learning model having an autoencoder architecture and generating one or more estimates of the motor shaft angle or the motor shaft rotation speed from the filtered time series.
A cooling element for cooling of an electric device is provided. The cooling element includes a first plate having a first surface, a second plate having a first surface and a second surface opposite to the first surface, wherein the second surface is configured to be attached to the electric device, wherein the first plate and the second plate are attached to one another facing their respective first surface, wherein a first structure is arranged between the first plate and the second plate such that a channel is formed between the first plate and the second plate, and two liquid connectors in liquid communication with the channel for connecting the channel to a cooling circuit.
A cooling device for cooling a discrete semiconductor package, includes a housing, wherein the housing includes a heat exchange surface configured to match with a corresponding heat emitting surface of the semiconductor package, and wherein the housing surrounds a liquid chamber and includes distribution elements arranged to form a fluid channel for a cooling liquid through the liquid chamber between an inlet portion and an outlet portion, wherein the fluid channel is configured to guide a flow of the cooling liquid inside the housing alongside the heat exchange surface.
A power converter node is configured to receive an index value unique to the power converter node, and reset a counter associated with the index value responsive to a synchronization signal. The power converter node may receive a counter update signal that causes the power converter node to update the counter to control a state of the power converter node to supply energy to a load along with other power nodes of a multi-level converter.
H02J 13/00 - Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the networkCircuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
A photoacoustic gas sensor comprises an emitter configured to emit light, a sensor configured to measure pressure variations and a measurement cell enclosing the emitter and the sensor. At least a first ventilation opening and a second ventilation opening connect the measurement cell with an environment.
A silicon carbide device includes a silicon carbide body having a first doped region and a second doped region. The first doped region is n doped and the second doped region is p doped. A first interface layer in direct contact with the first doped region includes a first metal silicide/carbide containing a first transition metal. A first buffer layer is formed directly on the first interface layer. A second interface layer in direct contact with the second doped region includes a second metal silicide/carbide containing a second refractory metal. The second interface layer is formed along at least a lower sidewall portion of a trench that extends from a first surface into the silicon carbide body.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
09 - Scientific and electric apparatus and instruments
37 - Construction and mining; installation and repair services
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and audio-visual, multimedia and photographic equipment;
apparatus, instruments and cables for electricity;
measuring, detecting, monitoring and controlling equipment;
scientific research and laboratory apparatus, educational
apparatus and simulators. Computer hardware and telecommunication equipment
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44.
Cell Design for MOS-Controlled Power Semiconductor Device
A power semiconductor device includes trenches vertically extending into a semiconductor body. Each trench includes a trench electrode insulated from the semiconductor body by a trench insulator. Two control trenches spatially confine a first type mesa configured to conduct a part of a load current. Two exposed trenches spatially confine a second type mesa configured to not conduct an inversion channel current. The second type mesa is arranged spatially separated from the first type mesa by a spacer region. A shield region separate from a body region extends: at least partially further along the vertical direction than bottoms of some trenches, bottoms of at least the control trenches extending at least partially into the shield region; and so as to form at least a partial lateral overlap with the first type mesa, the partial overlap being greater as compared to an overlap with the second type mesa.
A method includes: applying a pre-layer to a first or second connection partner; arranging the first connection partner on the second connection partner with the pre-layer arranged therebetween; heating the connection partners with the pre-layer arranged therebetween; and while heating, exerting pressure on the first connection partner such that the first connection partner is pressed towards the second connection partner and a permanent connection layer is formed between the connection partners. A first pressure exerted on at least one first section of the first connection partner is less than a second pressure exerted on at least one second section of the first connection partner. The resulting permanent connection layer has a higher porosity in areas arranged below the at least one first section of the first connection partner and a lower porosity in areas arranged below the at least one second section of the first connection partner.
A transistor device is disclosed. The transistor device includes: a semiconductor body; a drift region in the semiconductor body; a plurality of transistor cells; and a gate node and a source node. Each transistor cells includes: a first trench electrode insulated from the semiconductor body by a first dielectric layer; a second trench electrode insulated from the semiconductor body by a second dielectric layer; a source region and a body region in a first mesa region between the first trench electrode and the second trench electrode; and a compensation region. The compensation region adjoins the body region, the first dielectric, and the second dielectric, and forms a pn-junction with the drift region. From the first trench electrode and the second trench electrode, at least the first trench electrode is connected to the gate node.
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
47.
INTEGRATED TWO STAGE AMPLIFIER WITH INTRINSIC IMPEDANCE MATCHING
A method of operating an amplifier device includes providing an amplifier device that includes providing an amplifier device that includes a driver stage transistor and an output stage transistor connected in series between an RF input terminal and an RF output terminal, and amplifying an RF signal as between the RF input terminal and the RF output terminal, wherein the driver stage transistor and the output stage transistor are each monolithically integrated in a single semiconductor body, and wherein amplifying the RF signal comprises operating the driver stage transistor at a first voltage magnitude and operating the output stage transistor at a second voltage magnitude that is greater than the first voltage magnitude.
A mechanism for controlling power flow from a voltage line to an electronic circuit of a microchip. A reset control system initially controls a voltage isolation circuit to prevent this power flow upon startup of the microchip and allows it only when one or more predetermined criteria are met. The voltage monitoring system generates a digital representation of the voltage at a supply line, which the reset control system monitors. The reset control system monitors the digital representation of this voltage to determine when the one or more predetermined criteria are met.
An electronic control unit (114) is presented. The electronic control unit (114) comprises an electronic device (118), an application controller (128) and a safety node (134). The application controller (128) is configured for controlling the electronic device (118). The safety node (134) is configured for monitoring input signals sent from a supervising controller (112) to the electronic control unit (114). The safety node (134) is further configured for identifying a failure signal from the input signals. The safety node (134) is further configured for triggering a reset of the application controller (128) when identifying the failure signal. Further, a method for triggering a reset and a control system (110) are presented.
In an embodiment a method includes providing a substrate arrangement having a back end of line (BEOL) stack on a semiconductor substrate, wherein the BEOL stack comprises a plurality of structured wiring layers stacked and embedded in an insulating material structure (IMS), and wherein an upmost structured wiring layer of the plurality of structured wiring layers comprises a plurality of contact pads, after providing the substrate arrangement, locally removing portions of the IMS for exposing a first set of contact pads of the plurality of contact pads of the upmost structured wiring layer, and after locally removing portions of the IMS, depositing a conductive layer comprising a metallic material on a surface of the BEOL stack and structuring the conductive layer to provide a first structured portion of the conductive layer comprising a contact pad array and a second portion of the conductive layer that is arranged on the first set of contact pads of the BEOL stack.
A power semiconductor device includes an active region and an edge termination region surrounding the active region. A field plate structure arranged around the active region includes at least one electrically conductive track electrically connected to a first potential of a first load terminal at a first joint and, at a second joint, electrically connected to a second potential of a second load terminal. The track forms at least n crossings, wherein n is greater 5, with a straight virtual line that extends from the active region towards an edge of the edge termination region. The difference in potential between adjacent two crossings increases in at least 50% of the length of the virtual line, and/or the difference in potential within, with respect to the active region, the first 20% of the length of virtual line is less than 10% of the difference in potential along the virtual line.
Systems, methods, and circuitries are provided for controlling access the secondary hardware devices in a controller based on a two part transaction identifier. In one example, a controller includes a primary hardware device, one or more secondary hardware devices, and an interconnect. The interconnect couples the one or more primary hardware devices to the one or more secondary hardware devices. The interconnect is configured to assign a transaction identifier to each access request generated by the primary hardware device based on a mask associated with the primary hardware device. The mask includes m bits and prevents transaction identifiers not associated with the primary hardware device from being assigned to an access request generated by the primary hardware device. Each transaction identifier includes an m bit main component mapped to an application in execution by the primary hardware device and an n bit sub-component mapped to a sub-task of the app
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
53.
MULTI-PHASE SWITCHING VOLTAGE REGULATOR AND CONTROLLER
A controller for a multi-phase switching voltage regulator includes a first control loop and a second control loop. The first control loop has a first set of coefficients for implementing pulse width modulation (PWM) and a second set of coefficients for implementing pulse frequency modulation (PFM). The second control loop is configured to implement phase current balancing for the multi-phase switching voltage regulator. In a first configuration, the first control loop is configured to implement PWM-based control of the multi-phase switching voltage regulator using the first set of coefficients. In a second configuration, the first control loop is configured to implement PFM-based control of the multi-phase switching voltage regulator using the second set of coefficients.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An integrated circuit includes a semiconductor layer with a first portion in a first device region and a second portion in a second device region. A galvanic isolation structure is formed between the first portion and the second portion of the semiconductor layer. A capacitive coupling element is formed on a first surface of the semiconductor layer. The capacitive coupling element includes a first lower electrode in the first device region and a capacitor dielectric separating the first lower electrode from a top electrode spanning across the galvanic isolation structure. The first lower electrode is signal-connected to a first circuit element in the first device region. The top electrode is operatively connected to a second circuit element in the second device region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 86/80 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
55.
METHOD OF SPLITTING A SEMICONDUCTOR SUBSTRATE AND SUBSTRATE SPLITTING APPARATUS
A method of splitting a semiconductor substrate includes forming a release layer (115) in a semiconductor substrate (110), wherein the semiconductor substrate (110) includes a first substrate portion (114) between a first surface (111) and the release layer (115) and a second substrate portion (116) between the release layer (115) and a second surface (112) opposite the first surface (111). An auxiliary layer (120) is formed on the first surface (111), wherein the auxiliary layer (120) and the semiconductor substrate (110) have different coefficients of thermal expansion. A main cooling plate (210) is brought into contact with a solid substrate composite (100) that includes the semiconductor substrate (110) and the auxiliary layer (120) in a cooling period. The main cooling plate (210) is cooled in the cooling period, wherein the auxiliary layer (120) is cooled. Mechanical vibrations are applied directly to the main cooling plate (210) in the cooling period, wherein the first substrate portion (114) is cleaved from the second substrate portion (116).
A device may provide a traffic flow via a first network interface, the traffic flow including a plurality of frames. The device may identify a plurality of priority metrics associated with the traffic flow, each priority metric of the plurality of priority metrics corresponding to a respective frame of the plurality of frames. The device may generate a replicated traffic flow based on the plurality of priority metrics, the replicated traffic flow including a replicate of a set of frames from the plurality of frames. The device may provide the replicated traffic flow via a second network interface.
A phase change material switch device is provided. The phase change material switch device includes a phase change material, a first electrode electrically coupled to the phase change material, plurality of spaced apart heaters thermally coupled to the phase change material, and an equalization device. The equalization device provides varying impedance coupling between the first electrode and the plurality of spaced apart heaters.
H01H 37/14 - Means for adjustment of "on" or "off" operating temperature by anticipatory electric heater
H01H 37/72 - Switches in which the opening movement and the closing movement of a contact are effected respectively by heating and cooling or vice versa
H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
58.
Devices for Controlling Trapped Atoms and Methods for Manufacturing Thereof
A device for controlling trapped atoms includes a structured electrode layer. The structured electrode layer forms multiple electrodes of an atom trap configured to trap atoms in a processing zone above the structured electrode layer. The device further includes at least four wires arranged in one or more metal layers beneath the structured electrode layer. The wires surround the processing zone and each of the wires includes a first portion configured to carry an electrical current in a direction towards the processing zone and a second portion configured to carry the electrical current in a direction away from the processing zone.
A power converter device comprises: a first substrate comprising a first circuit, wherein the first circuit comprises at least one switching cell, which is arranged as semiconductor material in at least one integrated electronic device; and a second substrate comprising a second circuit, wherein the first substrate and the second substrate are connected to each other through a connection of the integrated electronic device and the second circuit.
H02M 3/00 - Conversion of DC power input into DC power output
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
H05K 7/14 - Mounting supporting structure in casing or on frame or rack
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
An integrated wireless power transfer device comprises a laminated substrate comprising a plurality of layers, a first circuit comprising a first transformer winding and a second transformer winding coupled in series between a first input node and a second input node, a second circuit galvanically isolated from the first circuit and comprising a third transformer winding and a fourth transformer winding coupled in series between a first output node and a second output node, and a plurality of first contact pads and a plurality of second contact pads formed on a bottom surface of the laminated substrate. The first transformer winding is formed on a first layer of the laminated substrate, the third transformer winding is formed on the first layer of the laminated substrate, the fourth transformer winding is formed vertically above the first transformer winding on a second layer of the laminated substrate, the second transformer winding is formed vertically above the third transformer winding on the second layer of the laminated substrate, the first contact pads of the plurality of first contact pads are electrically coupled to the first circuit, and the second contact pads of the plurality of second contact pads are electrically coupled to the second circuit.
The implementation discloses an integrated circuit including a specific digital signal processor (DSP) having an associated arithmetic logic unit (ALU) and including a dedicated safety device for continuously monitoring the functional safety of this specific digital signal processor. The digital signal processor triggers a predetermined security mechanism that enables one or more specified test operations to be carried out by the ALU. The test results obtained in the process are stored in a test result register. The safety device reads out at certain times the content of the test result register and compares the content with a specified correct test result. In the event of a deviation, a fault indication is generated.
A semiconductor device includes a substrate including a channel layer of type III-V material and a barrier layer of type III-V material forming a heterojunction interface with the channel layer such that a two-dimensional charge carrier gas is disposed in the channel layer; and one or more high-electron mobility transistors monolithically formed in the semiconductor substrate, wherein each of the high-electron mobility transistors includes a gate structure that comprises a gate electrode and a first doped region of type III-V material arranged between the gate electrode and the barrier layer, wherein the first doped region is configured to generate an electric field that at least partially depletes the two-dimensional charge carrier gas, and wherein one of the high-electron mobility transistors includes a threshold voltage compensation region disposed below the gate structure that is configured to partially compensate for the electric field generated by the first doped region.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/60 - Impurity distributions or concentrations
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/82 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components
Disclosed is a method. The method includes: forming a plurality of trenches in a first surface of a semiconductor body such that the trenches are separated from each other by semiconductor mesa regions; and forming a channel region of a first doping type in each of the mesa regions. Forming the channel region includes implanting first type dopant atoms at least into a first sidewall of the respective mesa region. Implanting the first type dopant atoms into the first sidewall includes at least two implantation processes that are different from each other with regard to at least one process parameter.
A semiconductor package includes: a substrate having an insulation layer with a first upper main face and a second lower main face opposite to the first upper main face; a leadframe having a first upper main face and a second lower main face opposite to the first main face; a semiconductor transistor die arranged on the first main face of the leadframe; a joint layer coupling the second lower main face of the leadframe to the first upper main face of the ceramic insulation layer, the joint layer having a melting point entirely or in parts of greater than 260° C.; and an encapsulation covering an inner portion of the leadframe, the semiconductor transistor die, and the ceramic insulation layer.
In an embodiment, a method for forming a microfabricated structure includes depositing a first membrane disposed on a substrate, depositing a first dual-slope clamping layer disposed on the first membrane, depositing a stator layer disposed on the first dual-slope clamping layer, forming a perforated stator from the stator layer, wherein the first dual-slope clamping layer is disposed on a first surface of the perforated stator, depositing a second dual-slope clamping layer disposed on a second surface of the perforated stator and depositing a second membrane disposed on the second dual-slope clamping layer, including depositing a pillar coupled between the first membrane and the second membrane, wherein a first membrane contact point of a first edge of the first dual-slope clamping layer is laterally offset from a second membrane contact point of a second edge of the second dual-slope clamping layer.
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
The disclosure relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body in which a device structure with a load terminal is formed; a metallization on a first side of the SiC semiconductor body, in which a load pad is formed; a passivation system on the metallization, which has an opening on the load pad; wherein the passivation system, as viewed in a sectional plane perpendicular to a lateral edge of the load pad, extends between an outer lateral position x1 aside the load pad and an inner lateral position x2 on the load pad, wherein an interruption is provided in at least one layer of the passivation system at an interruption position xi between the lateral edge of the load pad and the inner lateral position x2.
A method for forming an optical package includes forming a patterned hard mask on a surface of a semiconductor wafer. The patterned hard mask includes a plurality of recesses defining positions of cavities to be formed in the semiconductor wafer. Additionally, the method includes forming a respective photoresist structure on the surface of the semiconductor wafer in the plurality of recesses. The method further includes performing a first etch process during which the semiconductor wafer is etched in the recesses at positions not covered by the photoresist structure. In addition, the method includes removing the photoresist structures after performing the first etch process and performing a second etch process after removing the photoresist structures. In the second etch process, the semiconductor wafer is etched in the recesses to form the cavities by lowering structures formed in the first etch process.
A memory device is provided. The memory device includes: a plurality of memory elements, wherein each of the plurality of memory elements is configured to store a data value, and a controller configured to read a plurality of stored data values from the plurality of memory elements, process the stored data values using an error detection code, thereby generating a first erasure vector, to map an address list of permanently dysfunctional memory elements generated during initial testing of the memory device onto the plurality of memory elements, thereby generating a second erasure vector; and to process the plurality of stored data values using an error correction code taking into account the first erasure vector and the second erasure vector.
In accordance with an embodiment, a field-effect transistor (FET) chip with integrated overtemperature protection, the FET chip including: a FET comprising a FET-gate comprising a first material, a FET-body arranged between a FET-source and a FET-drain, and a drain-source field oxide as a first isolator, the drain-source field oxide being arranged between the FET-gate and the FET-body; a temperature sensor configured for sensing a temperature of the FET, the temperature sensor comprising the first material; and a second isolator arranged between the FET and the temperature sensor.
A semiconductor device includes a semiconductor body having an active region and a substrate region beneath the active region, a bidirectional switch including first and second input-output terminals, a gate structure configured to control a conduction state of a channel within the active region, the gate structure comprising one or more gate electrodes, and a field plate structure configured to influence electric field distribution between the gate structure and each of the first and second input-output terminals, the field plate structure comprising a field plate that extends over access regions on either side of the one or more gate electrodes, a secondary circuit configured to generate a quasi-reference potential in both an on-state and an off-state of the bidirectional switch at a first node of the secondary circuit, and a quasi-reference potential connection that directly connects the field plate to the first node.
H10D 64/00 - Electrodes of devices having potential barriers
H01L 23/528 - Layout of the interconnection structure
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
71.
MEMS DEVICE AND METHOD FOR CHARACTERIZING A MEMS DEVICE
Provided is a MEMS device. The MEMS device includes a stator including a recess. Additionally, the MEMS device includes a rotor arranged in the recess and configured to oscillate about an oscillation axis. The rotor includes first rotor electrodes interdigitated with first stator electrodes and second rotor electrodes interdigitated with second stator electrodes. The first stator electrodes and the second stator electrodes are arranged at opposite sides of the recess. The MEMS device further includes drive circuitry configured to apply electric potentials to the first and second stator electrodes. When the rotor is in a rest position, the drive circuitry is configured to generate the electric potentials to apply a non-zero torque to the rotor to start oscillation of the rotor about the oscillation axis.
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
72.
SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME
The disclosure relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body; a passivation system on a first side of the SiC semiconductor body ; the passivation system comprising an inorganic passivation layer system and an organic layer on the inorganic passivation layer system, a lateral edge of the inorganic passivation layer system arranged on the SiC semiconductor body, wherein the inorganic passivation layer system is laterally set back under the organic layer, the lateral edge of the inorganic passivation layer system being covered by the organic layer.
A cascaded radio frequency (RF) device includes a first RF chip including a first local oscillator configured to generate and output a first local oscillator signal during an operation time interval, a second RF chip including a second local oscillator configured to generate and output a second local oscillator signal during the operation time interval, and a power combiner configured to combine the first local oscillator signal and the second local oscillator signal to a combined local oscillator signal and to output the combined local oscillator signal to an input of the first RF chip and to an input of the second RF chip, wherein the first local oscillator signal and the second local oscillator signal have a same frequency behavior during the operation time interval.
A sensor device includes a sensor chip having at least one sensor element which is arranged on a front side of the sensor chip and is configured to capture a physical variable, an electrically insulating material which is arranged on the front side of the sensor chip and surrounds the at least one sensor element, and an electrically insulating layer arranged over a rear side of the sensor chip opposite the front side.
A semiconductor device includes a semiconductor substrate, a power semiconductor device monolithically formed in the semiconductor substrate, and an electrical interconnect region formed on an upper surface of the semiconductor substrate. The semiconductor device includes an upper-level contact pad formed in an uppermost level of metallization from the electrical interconnect region, wherein a plurality of external contact structures is formed on the upper-level contact pad. Additionally, the semiconductor device includes a hybrid via-metallization structure pad formed in a lower part of an interconnect region and forming a via structure with a terminal of the power semiconductor device and an interconnect metallization.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
In a method of generating a microelectromechanical system, MEMS, device, a MEMS substrate including a movable element is provided. A glass cover member including a glass cover is formed by hot embossing. The glass cover member is bonded to the MEMS substrate so as to hermetically seal by the glass cover a cavity in which the movable element is arranged.
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
77.
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AN ELECTRICALLY CONDUCTIVE STRUCTURE OF A METALLIZATION STRUCTURE
In an embodiment, a semiconductor device is provided that includes a semiconductor substrate having a first major surface and a metallization structure located on the first major surface. The metallization structure includes one or more electrically conductive structures having a metallic diffusion barrier layer and a copper layer located on the metallic diffusion barrier layer. The metallic diffusion barrier layer has a thickness t, an upper surface, a lower surface, and a side face extending between an upper edge formed between the upper surface and the side face and a lower edge formed between the lower surface and the side face. The linear distance d between the upper edge and the lower edge is t≤d≤1.1 t or t≤d≤1.05 t.
A circuit is described herein which may be used as an electronic fuse. According to one example, the circuit includes an integrated circuit (IC) with a chip contact for connecting, during operation, a filter circuit. The IC further includes a driver configured to drive a power transistor in accordance with a logic signal; a squaring circuit configured to receive a current sense signal that represents a load current passing through the power transistor and to output, at the chip contact, a first current that represents the squared load current; a comparator circuit configured to compare a voltage present at the chip contact with a reference voltage; and a control logic configured to generate the logic signal and to cause a switch-off of the power transistor dependent on an output signal of the comparator circuit.
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 5/04 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal non-electric working conditions with or without subsequent reconnection responsive to abnormal temperature
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/18 - Modifications for indicating state of switch
A MEMS sound transducer element is operable in an audio and an ultrasonic range. The MEMS sound transducer element includes a first electrode structure, wherein a conductive material of the first electrode structure includes a plurality of electrically isolated electrode segments, and a second electrode structure spaced apart from the first electrode structure, wherein the first electrode structure and the second electrode structure are operable as an audio sound transducer. A first subset of the plurality of electrically isolated electrode segments of the first electrode structure is, in conjunction with the second electrode structure, operable as an ultrasonic or audio emitter, and a second subset of the plurality of the electrically isolated electrode segments of the first electrode structure is, in conjunction with the second electrode structure, operable as an ultrasonic or audio receiver.
An electrode interface for driving an electrode of a quantum circuit is described. The electrode is selectively connectable to at least one signal line. Each signal line is connected to an intermediate node by a respective first switch. The intermediate node is connected to the electrode by a second switch. A buffer capacitor couples the intermediate node to a ground or reference voltage. To disconnect a signal line from the electrode, the second switch is opened, to effectively decouple the first switch(es) from the intermediate node, before the first switch connected to the relevant signal line is opened.
An arrangement for a direct interconnect assembly includes an electronic component including a first main face and a first metallic layer disposed on the first main face; and an electric component comprising a second main face and a second metallic layer disposed on the second main face, wherein the electronic component is connected to the electric component, wherein the first metallic layer of the electronic component is directly connected with the second metallic layer of the electric component, wherein the first and second metallic layers are essentially free of oxygen.
An assembly as discussed herein includes: a first semiconductor chip substrate including an active region and an inactive region, the active region of the first semiconductor chip substrate fabricated to include first circuitry, the first circuitry being active circuitry, the inactive region of the first semiconductor chip substrate being void of active circuitry; and second circuitry coupled to the first semiconductor chip substrate, the second circuitry affixed to the inactive region of the first semiconductor chip substrate, the inactive region operative to receive and convey heat generated by the second circuitry.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
83.
Semiconductor Devices and Methods for Manufacturing the Same
A semiconductor device includes a semiconductor substrate having a first major surface, an active area, and an edge region laterally surrounding the active area. A trench structure formed in the first major surface includes a base, sidewalls, a transverse trench section, and longitudinal trench sections. The transverse trench section is located in the edge region. The longitudinal trench sections extend from the transverse trench section into the active area. The trench structure further includes a field plate electrically insulated from the semiconductor substrate by a dielectric layer located on the base and side walls of the trench structure. The dielectric layer has a thickness tend on the side walls in an end portion of the longitudinal trench sections located in the edge region and has a thickness tact on the side walls in a portion of the longitudinal trench sections located in the active area, where tend>tact.
A method of manufacturing a power device includes: etching a trench in a semiconductor body; forming at least a first layer of dielectric material in the trench; forming a first field electrode structure on the at least one first layer of dielectric material and in the trench; forming at least one second layer of dielectric material on the first electrode structure and in the trench; and forming a second field electrode structure on the at least one second layer of dielectric material and in the trench.
A method for overtemperature protection of an electronic device having a plurality of operation modes is presented. The method may comprise of assigning temperature thresholds to the operation modes of the electronic device; determining a present operation mode of the electronic
A method for overtemperature protection of an electronic device having a plurality of operation modes is presented. The method may comprise of assigning temperature thresholds to the operation modes of the electronic device; determining a present operation mode of the electronic
device; determining a present temperature of at least a part of the electronic device; and declaring an overtemperature condition of the electronic device if the present temperature exceeds the temperature threshold assigned to the present operation mode of the electronic device. Further, an overtemperature protection circuit and a use of the overtemperature detection circuit and the method for overtemperature protection are presented.
A MEMS transducer includes a deflectable membrane where the deflectable membrane includes two first layers and a second layer arranged between the two first layers. The two first layers comprise low-stress silicon nitride, and the second layer comprises doped silicon.
The invention relates to the field of current protection systems. The current protection system comprises a shunt sub-system, arranged between an input and an output of the current protection system, the shunt sub-system comprising a first switch and a shunt resistor, the first switch arranged in series with the shunt resistor. The current protection system further comprises a comparator sub-system, arranged in parallel to the shunt resistor, the comparator sub-system being configured for comparing a shunt voltage across the shunt resistor with a reference voltage, the comparator sub-system comprising an offset-compensated operational amplifier. And, the current protection system comprises a control component, arranged between an output of the comparator sub-system and a first control input of the first switch.
A semiconductor device may comprise an insulator substrate, a second substrate, a first structured metallization layer comprising a first section configured to operate at a first potential, and a second section configured to operate at a second potential. The insulator substrate may comprise a second structured metallization layer which may comprise a first section coupled to the first potential and a second section coupled to the second potential. At least one routable third structured metallization layer may comprise a first segment coupled to the second potential and a second segment coupled to the first potential.
A method of producing a molded package includes: attaching a bottom side of a semiconductor die to a substrate; attaching an electrically conductive clip to a top side of the semiconductor die such that a convex curved surface at a bottom side of the electrically conductive clip is attached to the top side of the semiconductor die and a flat surface at a top side of the electrically conductive clip faces away from the semiconductor die and overlays the semiconductor die; encapsulating the semiconductor die and the electrically conductive clip in a mold compound; and removing the mold compound from the flat surface of the electrically conductive clip. Along a vertical cross-section of the electrically conductive clip between the flat surface and the convex curved surface, the electrically conductive clip has a plano-convex shape delimited by the flat surface and the convex curved surface.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Apparatus, instruments and cables for electricity; Electrical and electronic components; Electrical and electronic components, particularly semiconductor devices, semiconductor chips, integrated circuit chips, semiconductor chip housings, microcontroller, printed circuit boards, circuit boards provided with integrated circuits; Downloadable and recorded content; Downloadable and recorded content, particularly downloadable computer software and firmware for operating system programs, Software development kits [SDK], Computer software for encryption, downloadable software for automotive data processing; Measuring, detecting, monitoring and controlling equipment. IT services; IT services, particularly computer programming, computer software design for others; Science and technology services; Design services; Design services, particularly design of semiconductor chips, provision of virtual computer systems and virtual computer environments through cloud computing.
In an embodiment, a method for tracking a target includes: receiving raw data from a millimeter-wave radar, the raw data including a plurality of macro-Doppler frames, each macro-Doppler frame having N chirps, where each macro-Doppler frame stretches over a time interval having a first duration; generating micro-Doppler frames from the plurality of macro-Doppler frames, each micro-Doppler frame including L chirps from M macro-Doppler frames, where each micro-Doppler frame stretches over a time interval having a second duration that is longer than the first duration; detecting one or more moving targets based on the macro-Doppler frames; detecting one or more static targets based on the micro-Doppler frames; and tracking a first target as the target transitions from being detected based on the macro-Doppler frames to being detected based on the micro-Doppler frames.
G01S 13/72 - Radar-tracking systemsAnalogous systems for two-dimensional tracking, e.g. combination of angle and range tracking, track-while-scan radar
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
G01S 13/58 - Velocity or trajectory determination systemsSense-of-movement determination systems
92.
SEMICONDUCTOR DEVICE WITH DEGRADATION DETECTION CAPABILITY
A semiconductor device with a power transistor is described herein. The power transistor is composed of a plurality of transistor cells arranged in a cell array, wherein the plurality of transistor cells comprise first transistor cells arranged in a first part of the cell array and second transistor cells arranged in a second part of the cell array. The semiconductor device further includes a metallization layer that forms the source electrode of the power transistor, first bond wires with end pieces that are bonded to a first part of the metallization layer that covers the first part of the cell array, and second bond wires with end pieces that are bonded to a second part of the metallization layer that covers the second part of the cell array. The end pieces of the second bond wires have a higher volume than the end pieces of the first bond wires.
A semiconductor device includes a semiconductor substrate including at least a first semiconductor substrate portion and a second semiconductor substrate portion separated from one another by a first part of an intermediate dielectric structure along a first lateral direction. The semiconductor device further includes a patterned first metal layer over a first surface of the semiconductor substrate. A first part of the patterned first metal layer electrically connects the first and second semiconductor substrate portions at the first surface. Each of the first and second semiconductor substrate portions includes a main portion adjoining the first surface and an auxiliary portion adjoining a second surface opposite to the first surface. With respect to each of the first and second semiconductor substrate portions, a width of the auxiliary portion along the first lateral direction is larger than a width of the main portion along the first lateral direction.
H01L 23/60 - Protection against electrostatic charges or discharges, e.g. Faraday shields
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A level shifter for a power converter includes: a differential detector; a first transistor having a drain electrically connected to a first node of the differential detector, a gate, and a source; a second transistor having a drain electrically connected to a second node of the differential detector, a gate, and a source; and a circuit configured to simultaneously apply a same voltage to the source of the first and the second transistors based on a digital signal input to the level shifter. The circuit is also configured to apply a different gate voltage depending on the input digital signal, to choose which side of the level shifter will draw current to the differential detector. The differential detector is configured to translate the digital signal to a different voltage level based on a differential current between the first and the second transistors.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
95.
PHOTONIC DEVICES AND SYSTEMS INCLUDING PHOTONIC DEVICES
A photonic device includes a first interface configured to couple a plurality of first waveguides of the photonic device to a plurality of waveguides of a light source, and a second interface configured to couple a plurality of second waveguides of the photonic device to a plurality of waveguides of an atom trap device. A number of the plurality of first waveguides is smaller than a number of the plurality of second waveguides. A first pitch of the plurality of first waveguides is greater than a second pitch of the plurality of second waveguides.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
G02B 6/35 - Optical coupling means having switching means
A radio frequency (RF) device includes at least one RF chip, and a structure coupled to the at least one RF chip, wherein the at least one RF chip and the structure are integrated in a same semiconductor package, wherein the structure is configured to couple at least two RF signals of the at least one RF chip to at least two modes of a package-external waveguide and/or vice versa, and wherein the at least two modes are orthogonal to each other.
H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart
H01Q 21/24 - Combinations of antenna units polarised in different directions for transmitting or receiving circularly and elliptically polarised waves or waves linearly polarised in any direction
In accordance with an embodiment, a microelectromechanical system (MEMS) switch device includes: a substrate; a switching membrane disposed above the substrate; a pull-in electrode disposed above the switching membrane; a metal contact disposed on the switching membrane; and a pull-back electrode disposed below the switching membrane, wherein the switching membrane is movable between an open position and a closed position, and wherein in the closed position, the metal contact electrically connects two RF signal lines.
A semiconductor die includes: a semiconductor substrate; an electronic device formed in the semiconductor substrate; a partially formed frontside metallization disposed over a frontside of the semiconductor substrate; and a partially formed backside metallization disposed over a backside of the semiconductor substrate. The partially formed frontside metallization and the partially formed backside metallization have a same composition. Methods of processing semiconductor wafers and producing semiconductor modules are also described.
The present disclosure relates to a MEMS pressure transducer Wafer-Level Chip-Scale Package and a method for manufacturing the same. The method comprises a step of providing a MEMS wafer comprising adjacently arranged MEMS membrane structures. The method comprises a further step of providing an ASIC wafer comprising adjacently arranged integrated electronic components, and bonding the MEMS wafer with the ASIC wafer with their respective front sides facing each other. The method comprises a further step of structuring at least one first cavity into MEMS wafer and structuring a smaller second cavity into the first cavity.
The described techniques address issues related to secured communications via asymmetrical data communications, e.g. when one of the secured channels has a higher-bandwidth than the other secured channel. The techniques facilitate the detection of an impending expiration of a cryptographic key used for secured communications prior to its actual expiration and, in response, updating the cryptographic key for that secured channel. The updated cryptographic key for one secured channel may then be transmitted via the other secured channel as part of secured (e.g. encrypted) data communications. The techniques also allow for the use of different cryptographic algorithms per secured channel, different key lengths for the cryptographic keys, and/or different software or hardware solutions to be implemented per secured channel.
