Abrégé

The present disclosure provides a skyrmion transistor and a method of controlling a skyrmion transistor. The transistor includes: a ferromagnetic nanotube; a writing magnetic tunnel junction and a reading magnetic tunnel junction surrounding both ends of the ferromagnetic nanotube respectively; and a ferroelectric ring surrounding an outer side of the ferromagnetic nanotube and located between the writing magnetic tunnel junction and the reading magnetic tunnel junction, where the ferromagnetic nanotube and the ferroelectric ring form a ferromagnetic/ferroelectric heterojunction.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 50/85 - Matériaux de la région active

Abrégé

The present disclosure discloses a deep ultraviolet lithography method, a lithography pattern and a semiconductor structure, which relates to the field of deep ultraviolet lithography technology. The deep ultraviolet lithography method includes: dividing, when a depth of field of the deep ultraviolet lithography is less than a height of the step of the substrate, a pattern to be photoetched into at least two portions according to a distribution situation of the step, where each of the at least two portions corresponds to an on-step pattern or an off-step pattern of the step; corresponding the at least two portions of the pattern to be photoetched onto at least two masks respectively; and simultaneously baking and developing the exposed at least two masks after the at least two masks are exposed sequentially.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes
• G03F 7/20 - ExpositionAppareillages à cet effet

Abrégé

A static random access memory (SRAM) cell includes: a substrate; first and second interconnection structures parallel to an upper surface of the substrate and opposite to each other; a first pull-down (PD) transistor and a first pass gate (PG) transistor on the first interconnection structure; a second PD transistor and a second PG transistor on the second interconnection structure; a first pull-up (PU) transistor under the first interconnection structure and overlapping vertically with the first PD transistor; and a second PU transistor under the second interconnection structure and overlapping vertically with the second PD transistor. Channel layers of the first PU, PD, PG transistors are offset from the first interconnection structure on a side away from the second interconnection structure. Channel layers of the second PU, PD, PG transistors are offset from the second interconnection structure on a side away from the first interconnection structure.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

Provided in the present application are a three-dimensional vertical memristor and a manufacturing method therefor. The three-dimensional vertical memristor comprises: a substrate; alternately stacked on the substrate, insulating layers and word line layers, there being at least three insulating layers and at least two word line layers, the oxygen ion capturing capability of at least one word line layer being greater than or equal to a first preset value, and the oxygen ion capturing capability of at least one word line layer being less than the first preset value; a channel penetrating through the insulating layers and the word line layers; and, located on a side wall of the channel, a storage layer, a selection layer and a bit line layer, the selection layer being located on the side of the storage layer away from the side wall of the channel, and the bit line layer being located on the side of the selection layer away from the channel. In the present application, the word line layers having different oxygen ion capturing capabilities are provided, among which the word line layer having a strong oxygen ion capturing capability exhibits a non-volatile property, and the word line layer having a weak oxygen ion capturing capacity exhibits a dynamic property, thereby achieving a three-dimensional memristor array having different properties.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]

Abrégé

The present disclosure relates to a method of obtaining a nanoscale line by using a laser, including: forming a dielectric layer and an amorphous silicon layer on a substrate sequentially; irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer, where a grain boundary of a polycrystalline silicon formed by the silicon crystallization in the partial region of the amorphous silicon layer is determined by a spacing between holes with a regular shape on the mask plate; performing a planarization process on the grain boundary of the polycrystalline silicon of the amorphous silicon layer; removing the grain boundary by using a corrosion solution to form a grain boundary trench; and obtaining the nanoscale line on the substrate by using the grain boundary trench.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique

Abrégé

A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

Classes IPC  ?

• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

Provided in the present disclosure are a prediction model training method and apparatus, a resistance-state retention restoration method and apparatus, and a device. The prediction model training method comprises: performing a first preset number of erase/write operations on all M resistive random access memories in a conductive state, so as to obtain M first resistive random access memories and erase/write operation voltages respectively corresponding to the M first resistive random access memories; for each of the M first resistive random access memories, performing, within a first preset duration, a continuous read operation on the first resistive random access memory at every second preset duration, so as to obtain first resistance-state data; performing a step-by-step read operation on the first resistive random access memory at every second preset duration, so as to obtain second resistance-state data; on the basis of the first resistance-state data, second resistance-state data and erase/write operation voltage corresponding to each of the M first resistive random access memories, obtaining training sample data; and on the basis of the training sample data, training a resistance-state retention prediction model, so as to obtain a target prediction model.

Classes IPC  ?

• G11C 29/50 - Test marginal, p. ex. test de vitesse, de tension ou de courant

Abrégé

An optimization method and apparatus for an oxide-based resistive random access memory, and a retention test method and apparatus for an oxide-based resistive random access memory, which relate to the technical field of microelectronics. The optimization method comprises: performing a forming operation on an oxide-based resistive random access memory, so as to obtain a first resistive random access memory in an active state (S110); performing a first preset number of first erase/write operations on the first resistive random access memory, so as to obtain a second resistive random access memory within a preset resistive state range (S120); and performing a second preset number of second erase/write operations on the second resistive random access memory, so as to obtain a target resistive random access memory within the preset resistive state range (S130), wherein a second reset voltage, which is used in the second erase/write operations, is obtained by finding the sum of a preset voltage value and an average value of first reset voltages, which are respectively used in the first preset number of first erase/write operations.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

The present disclosure provides a stacked nanosheet gate-all-around device with an air spacer and a manufacturing method. The device includes: a substrate, where a first dielectric layer is on the substrate, a gap array is in the first dielectric layer, the gap array includes multiple gap units, and each gap unit is in a fin shape above the substrate; a nanosheet stacking portion above the gap unit, including a stack formed by multiple nanosheets, and the stack formed by the nanosheets constitutes multiple conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region on two opposite sides of the nanosheet stacking portion, where an empty spacer is between the source/drain region and the gate-all-around. An interior of the gap array and an interior of the empty spacer are filled with at least one of air, a reducing gas, or an inert gas.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

Provided are a static random access memory (SRAM) cell, a memory, and an electronic device. The SRAM cell may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor on a substrate. The first and second pull-up transistors are provided at a first height relative to the substrate. The first and second pull-down transistors and the first and second pass-gate transistors are provided at a second height different from the first height relative to the substrate. Each of the transistors includes a channel nanosheet extending in a first direction and source/drain portions provided above and below the channel nanosheet respectively. The first pull-down transistor is aligned with the first pull-up transistor in a vertical direction, and the second pull-down transistor is aligned with the second pull-up transistor in the vertical direction.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

The present application provides a spintronic neuron device, a modeling method, and a spiking neural network training method. The spintronic neuron device comprises electrodes at two ends, a transmission component which is located between the two electrodes and formed of multiple layers of films, and multiple output components deployed at different positions of the transmission component. In this way, different output components can be selected to work, to change the length of the transmission path of magnetic domain wall motion, thereby automatically adjusting the firing threshold of the spintronic neuron device. Characteristic simulation behaviors of the spintronic neuron device are modeled, and a spiking neural network for implementing identification tasks is constructed by means of the obtained neuron models having different performance and different mechanisms; the performance of the spiking neural network can be optimized by changing the number of neuron models, the threshold adjustment rate of a firing threshold, and/or synaptic weights, without the need to use peripheral circuits, thereby achieving the homeostasis of the spiking neural network and improving the stability and robustness of the spiking neural network to different inputs.

Classes IPC  ?

• G06N 3/049 - Réseaux neuronaux temporels, p. ex. éléments à retard, neurones oscillants ou entrées impulsionnelles

Abrégé

Provided in the present disclosure are a switch structure for reducing the leakage current of a parasitic body diode of an MOS transistor, and a digital circuit. The switch structure comprises: N first-type transistors connected in series, N being a positive integer greater than or equal to 2. A substrate of the first first-type transistor is connected to a first substrate voltage, a second electrode of the ith first-type transistor is separately connected to a substrate and a first electrode of the (i+1)th first-type transistor, i∈1,2,···,N, and gates of all the first-type transistors are connected together. By connecting parasitic body diodes in series, the switch structure of the present disclosure reduces the leakage current of body diodes of MOS transistors, thereby reducing the static power consumption of circuits. In addition, when the switch structure is applied to a digital logic circuit, a voltage output by an output end can be closer to a reference voltage, thus improving logic level integrity.

Classes IPC  ?

• H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ

Abrégé

A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.

Classes IPC  ?

• H10D 30/01 - Fabrication ou traitement
• H10D 30/00 - Transistors à effet de champ [FET]
• H10D 30/67 - Transistors à couche mince [TFT]
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 64/01 - Fabrication ou traitement

Abrégé

A multi-band and multi-functional antenna integrated module and a preparation method thereof are provided. The multi-band and multi-functional antenna integrated module has an electromagnetic wave capture layer, a frequency selection circuit layer, and a signal processing circuit layer stacked vertically in sequence. The frequency selection circuit layer and the frequency selection circuit layer are interconnected through a metallized through hole. The frequency selection circuit layer has a plurality of frequency selection circuit units with different processing bands. The signal processing circuit layer has a plurality of signal processing circuit units with different functions. The plurality of frequency selection circuit units are interconnected to the plurality of signal processing circuit units in a one-to-one correspondence manner through a plurality of metallized through holes.

Classes IPC  ?

• H01Q 15/00 - Dispositifs pour la réflexion, la réfraction, la diffraction ou la polarisation des ondes rayonnées par une antenne, p. ex. dispositifs quasi optiques
• H01Q 21/06 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles

Abrégé

Provided in the present disclosure are a spin electronic device, a storage pool device, and a storage pool neural network architecture. The spin electronic device comprises a magnetic domain device and at least two electrodes. The magnetic domain device comprises: a substrate; a spin-orbit coupling layer disposed on the top surface of the substrate; a magnetic layer disposed on the top surface of the spin-orbit coupling layer; and a barrier layer disposed on the top surface of the magnetic layer. The electrodes are inserted into the substrate from the top surface of the magnetic domain device, and the electrodes are configured to form an observation port of the spin electronic device; and the combined action of the antisymmetric interaction and dipole interaction of the spin-orbit coupling layer and the magnetic layer allows for the formation of a complex, stable, and periodically alternating magnetic domain structure. In the storage pool device, a volatile nonlinear response is obtained via application of an external magnetic field or electric pulse excitation, thus enabling a recognition function of the storage pool network.

Classes IPC  ?

• H10N 52/00 - Dispositifs à effet Hall

Abrégé

The present disclosure is applicable to the technical field of artificial intelligence, and provides a method, apparatus, and system for calculating a function on the basis of integration of memory and computation, a device, and a storage medium. The method comprises: for a first power term in a first Taylor expansion in a first function to be calculated, on the basis of a coefficient value of a first coefficient corresponding to the first power term, adjusting a first conductance value of a variable resistor on a word line in a semiconductor memory device which corresponds to the first power term; on the basis of the numerical value of the first power term, inputting a pulse voltage to the word line passing through the variable resistor in the semiconductor memory device, and obtaining a first current outputted by a bit line; performing analog-to-digital conversion on the first current, and obtaining a first current value corresponding to the first current; and, on the basis of the first current value, determining a first calculation result of said first function.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation

Abrégé

A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; a source, a drain, and at least one nanostructure layer, which are disposed on the semiconductor substrate; and a gate stack structure surrounding each nanostructure layer, where the at least one nanostructure layer is disposed between the source and the drain, each nanostructure layer comprises a first material layer and second material layers, the second material layers are disposed at two sides of the first material layer along a thickness direction of the first material layer, each of the first material layer and the second material layers is in contact with both the source and the drain, and at least a part of the second material layers is different from the first material layer in material.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

The memory cell includes: a piezoelectric substrate layer, wherein two ends of the piezoelectric substrate layer are respectively provided with a first electrode and a second electrode, and a current-free drive of skyrmion is implemented by applying a voltage to the first electrode and the second electrode; a magnetic layer on a surface of the piezoelectric substrate layer, wherein the magnetic layer is used to form a heterojunction with the piezoelectric substrate layer, and is used to generate, stabilize, and serve as a basic carrier for a movement of the skyrmion; wherein the magnetic layer includes a convex body, the convex body is configured to divide the magnetic layer into a bit region and a memory region, and the bit region is provided with a magnetic tunnel junction used to perform generation and detection functions of the skyrmion.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 30/853 - Compositions céramiques
• H10N 50/01 - Fabrication ou traitement
• H10N 50/85 - Matériaux de la région active

Abrégé

The semiconductor device includes a semiconductor substrate; and a first gate-all-around transistor and a second gate-all-around transistor formed on the semiconductor substrate and spaced apart from each other in a direction parallel to a surface of the semiconductor substrate. Each of the first gate-all-around transistor and the second gate-all-around transistor includes at least one nanostructure layer between a source region and a drain region. The nanostructure layer in the first gate-all-around transistor and the nanostructure layer in the second gate-all-around transistor are integrally formed. A thickness of each part of each nanostructure layer in the first gate-all-around transistor in a length direction of the nanostructure layer is less than a thickness of a corresponding nanostructure layer in the second gate-all-around transistor. A thickness of a gate stack in the first gate-all-around transistor is greater than a thickness of a gate stack in the second gate-all-around transistor.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
• H01L 21/762 - Régions diélectriques
• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince

Abrégé

Provided in the embodiments of the present application are an image feature extraction method and apparatus based on a magnetic tunnel junction array. The method comprises: a training stage, involving: on the basis of a preset voltage-pixel mapping relationship, a voltage-current mapping relationship and a preset convolution kernel, obtaining a pixel-current mapping relationship, wherein the convolution kernel is a magnetic tunnel junction array; and a feature extraction stage, involving: mapping, into a voltage, pixels of an image to be processed; using the voltage as an input, and on the basis of the convolution kernel, outputting current coordinates corresponding to said image; and on the basis of the current coordinates and the pixel-current mapping relationship, determining pixels, which have been subjected to convolution, of said image. The technical solution provided in the present application is used for solving the problems in the prior art of the writing rate being low, the energy consumption being high, the reliability being poor, etc.

Classes IPC  ?

• G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos

Abrégé

Provided are a semiconductor device with decreased source and drain resistance and a manufacturing method. The semiconductor device includes a substrate and multiple three-dimensional semiconductor device arrays. The three-dimensional semiconductor device arrays are on the substrate, and the three-dimensional semiconductor device arrays are separated by isolation grooves. Each three-dimensional semiconductor device array includes a plurality of device layers in a vertical direction, each device layer includes a stack of a source/drain layer, a channel layer and a source/drain layer, and an end face of the source/drain layer adjacent to the isolation groove is metallized. The three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stack penetrates each device layer in the vertical direction and includes a gate material and a gate dielectric layer, and a device unit is defined at an intersection of the gate stack and the device layer.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/762 - Régions diélectriques
• H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en

Abrégé

The present application provides a three-dimensional stacked dynamic random access memory and a manufacturing method therefor. The three-dimensional stacked dynamic random access memory comprises: a substrate, a source, a drain, a storage structure, a source-end common electrode, drain-end electrodes, and gates. The storage structure comprises a stack formed by a plurality of nanosheets; the nanosheets extend to the source and the drain; the source-end common electrode is in contact with each nanosheet; the source-end common electrode is connected to the ground potential; part of the nanosheets that extends to the drain forms a stepped structure; each drain-end electrode among the plurality of drain-end electrodes penetrates through part of the drain; each drain-end electrode is in contact with a nanosheet in the stepped structure; the drain-end electrodes are connected to bit lines; the gates surround the nanosheets; and the gates are connected to word lines. Therefore, by vertically stacking storage units, configuring the gates to surround the storage units, and configuring the part of the storage units connected to the drain to form the stepped structure, a three-dimensional stacked 1T storage unit array structure can be formed, thereby greatly improving the integration density of the dynamic random access memory and achieving high-density data storage.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.

Classes IPC  ?

• G11C 11/419 - Circuits de lecture-écriture [R-W]
• G11C 11/418 - Circuits d'adressage
• H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON

Abrégé

The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A nanowire/nanosheet device with a crystal spacer, a method of manufacturing the nanowire/nanosheet device with the crystal spacer, and an electronic apparatus including the nanowire/nanosheet device are provided. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; source/drain layers located at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a spacer provided on a sidewall of the gate stack, wherein the spacer has a crystal structure substantially identical to a crystal structure of the nanowire/nanosheet in at least a part of a region of the spacer adjacent to the nanowire/nanosheet.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/762 - Régions diélectriques
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A three-dimensional integrated circuit and a manufacturing method therefor is used for improving the performance of the integrated circuit when the integrated circuit includes a power gating circuit. The three-dimensional integrated circuit includes a substrate, and a front-section circuit, a rear-section metal interconnection layer, and a rear-section power gating circuit that are formed on the substrate; the rear-section metal interconnection layer is formed on the front-section circuit; the rear-section power gating circuit is located in the rear-section metal interconnection layer; and the front-section circuit is electrically connected to a power supply or a ground wire by means of the rear-section metal interconnection layer and the rear-section power gating circuit.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter

Abrégé

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur

Abrégé

The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.

Classes IPC  ?

• H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire

Abrégé

A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

The present disclosure provides a spintronic device and a recurrent neural network. The spintronic device comprises a substrate; a spin-orbit coupling layer arranged on a top surface of the substrate; a magnetic layer arranged on a top surface of the spin-orbit coupling layer, wherein a stable periodically alternating magnetic domain structure can be formed under the combined action of the antisymmetric exchange effect and the dipole interaction of the spin-orbit coupling layer and the magnetic layer; a barrier layer arranged on a top surface of the magnetic free layer; and at least two electrodes respectively arranged on two sides of the top surface of the substrate, separately connected to the spin-orbit coupling layer, the magnetic layer and the barrier layer and used for application of an input electric signal, wherein when the input electric signal is applied to the electrodes, the input electric signal flows into the spintronic device, so that the spintronic device generates joule heat with the input electric signal, and the resistance value of the spintronic device has dynamic fluctuation characteristics.

Classes IPC  ?

• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• G06N 3/044 - Réseaux récurrents, p. ex. réseaux de Hopfield

Abrégé

An electron beam exposure method and apparatus. The method comprises: acquiring exposure patterns, and according to the sizes of the exposure patterns, determining the sizes of a plurality of cells comprised in a reference grid, and arranging the exposure patterns at center positions of the cells, wherein the sizes of the cells are the sizes of write fields of electron beam exposure; and providing a reference rectangle, wherein the relative position between the reference rectangle and the reference grid is fixed, such that the positions of a plurality of write fields during electron beam exposure can be determined, so as to arrange the exposure patterns at center positions of the write fields of electron beam exposure, and therefore all the exposure patterns can be exposed at the center positions of the write fields, thereby achieving the optimal exposure effect, reducing the probability that the sizes of patterns formed by means of exposure are inaccurate due to deviations of exposure positions of the exposure, and improving the size accuracy of the exposure patterns.

Classes IPC  ?

• G03F 7/20 - ExpositionAppareillages à cet effet

Abrégé

A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

Classes IPC  ?

• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01L 21/762 - Régions diélectriques
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/161 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en
• H01L 29/24 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, à part les matériaux de dopage ou autres impuretés, uniquement des matériaux semi-conducteurs inorganiques non couverts par les groupes , ,  ou
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

Embodiments of the present application provide a training method and apparatus for plasma photolithography imaging. The method comprises: acquiring a training imaging structure of plasma photolithography imaging, the training imaging structure comprising a plurality of training mask patterns which are two-dimensionally periodically changed; constructing a simulation model on the basis of the training imaging structure, and performing simulation on the basis of the simulation model to obtain training plasma photolithography images corresponding to the training mask patterns; and training a rapid imaging model on the basis of the training mask patterns and the training plasma photolithography images to obtain a rapid imaging model for the two-dimensionally periodically changed training mask patterns. Therefore, by establishing a rapid imaging model for two-dimensionally periodically changed mask patterns, a training plasma photolithography image of each mask pattern can be directly obtained by using the rapid imaging model, achieving rapid imaging by means of the rapid imaging model, and satisfying the subsequent research requirements on the plasma photolithography.

Classes IPC  ?

• G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
• G03F 7/20 - ExpositionAppareillages à cet effet
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.

Classes IPC  ?

• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET

Abrégé

The present invention relates to the technical field of semiconductors, and in particular to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, nanosheet channels, a metal gate, a source-drain region, and an insulating dielectric layer, wherein the nanosheet channels are located above the substrate, the metal gate surrounds the nanosheet channels, the source-drain region is connected to the nanosheet channels, and the insulating dielectric layer is located between the substrate and the source-drain region and between the substrate and the nanosheet channels. According to the present invention, etching of silicon in the source-drain region is added to form a trench where a source and a drain are communicated, and then an insulating dielectric material fills the trench to form complete isolation between the bottoms of the channels and the bottoms of the source and the drain, so that a substrate parasitic channel and channel leakage between the source and the drain are fundamentally eliminated.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present application relates to the field of spin torque electronics. Disclosed are a control method for a spin torque nano-oscillator, and a spin torque nano-oscillator. The control method for a spin torque nano-oscillator is applied to a spin torque nano-oscillator which comprises a bottom electrode, and a ferromagnetic reference layer, a ferromagnetic free layer and a top electrode which are sequentially arranged on the bottom electrode. The control method comprises: during the process of performing reservoir computing by means of a spin torque nano-oscillator and on the basis of a strong nonlinear relationship between an input current intensity and an oscillation frequency corresponding to a self-oscillation state, regulating and controlling process parameters of related materials or voltage-controlled magnetic anisotropy, so as to regulate and control an anisotropy inclination direction of a ferromagnetic reference layer; and regulating and controlling the anisotropy inclination direction and/or regulating and controlling the input current intensity, so as to regulate and control an oscillation frequency and/or a line width corresponding to the spin torque nano-oscillator.

Classes IPC  ?

• H10N 50/01 - Fabrication ou traitement
• H10N 50/10 - Dispositifs magnéto-résistifs
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• H10N 50/85 - Matériaux de la région active

Abrégé

Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus

Abrégé

The present application discloses a battery cover plate assembly and a lithium-ion battery. The battery cover plate assembly comprises a cover plate body and a sealing member. The cover plate body has a first surface and a second surface, wherein a gas discharge hole is formed in the first surface. The sealing member partially extends into the gas discharge hole and is connected to the side wall of the gas discharge hole. A crimping portion is provided at the edge of the end of the sealing member facing away from the second surface in protruding fashion. The crimping portion extends in a direction away from the axis of the gas discharge hole. The orthographic projection of the crimping portion on the first surface is at least partially located outside the gas discharge hole.

Classes IPC  ?

• H10N 50/85 - Matériaux de la région active
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin

Abrégé

Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.

Classes IPC  ?

• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/786 - Transistors à couche mince

Abrégé

A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

Abrégé

A semiconductor device having a double-gate structure and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a first gate stack and a second gate stack on opposite sides of the channel portion in a first direction lateral to the substrate. A distance between an upper edge and/or a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion may be less than a distance between a corresponding upper edge and/or a corresponding lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01L 21/784 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs qui consistent chacun en un seul élément de circuit le substrat étant un corps semi-conducteur
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

Abrégé

A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée

Abrégé

A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/10 - Dispositifs magnéto-résistifs

Abrégé

The present disclosure relates to the technical field of microelectronics, and in particular relates to a ferroelectric gate stack, a ferroelectric field effect transistor, and a preparation method therefor, which are used for solving the problem of accumulation flipping that easily occurs in existing ferroelectric field effect transistors. The ferroelectric gate stack comprises, from bottom to top, a gate oxide layer, a dielectric thin layer, and another gate dielectric layer which are sequentially stacked; a ferroelectric layer is further provided between the dielectric thin layer and the gate oxide layer, and a resistive switching layer is further provided between the dielectric thin layer and the other gate dielectric layer; or a resistive switching layer is further provided between the dielectric thin layer and the gate oxide layer, and a ferroelectric layer is further provided between the dielectric thin layer and the other gate dielectric layer. According to the present disclosure, the resistive switching layer is added into the ferroelectric gate stack, so that when the voltage on the ferroelectric gate stack is smaller than a flipping voltage, accumulation flipping does not easily occur due to surrounding crosstalk, and after reaching a desired coercive voltage, start-up is normal, thereby weakening the accumulation flipping effect.

Classes IPC  ?

• H01L 29/51 - Matériaux isolants associés à ces électrodes
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Disclosed are a vertical semiconductor device having continuous gate lengths and a manufacturing method therefor, and an electronic device comprising the semiconductor device. According to embodiments, the semiconductor device may comprise: a semiconductor base on a substrate; a first vertical channel portion and a second vertical channel portion which are vertical to the substrate on the semiconductor base, wherein the first vertical channel portion and the second vertical channel portion protrude from the semiconductor base, are spaced apart from each other in a first direction and are self-aligned with each other, and the semiconductor base extends continuously between the first vertical channel portion and the second vertical channel portion; a first source/drain portion and a second source/drain portion which are respectively provided on the first vertical channel portion and the second vertical channel portion; and a gate stack at least partially provided on the first vertical channel portion, the semiconductor base and the second vertical channel portion to define continuous channels between the first source/drain portion and the second source/drain portion.

Classes IPC  ?

• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/41 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.

Classes IPC  ?

• H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

Classes IPC  ?

• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

A nanowire/nanosheet device and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a source/drain layer at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a first spacer on a sidewall of the gate stack, wherein the first spacer includes a continuously extending material layer which has a first part along a surface of the nanowire/nanosheet, a second part along a sidewall of the source/drain layer facing the gate stack, and a third part along a sidewall of the gate stack facing the source/drain layer, and the second part and the third part have a seam or an interface therebetween.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A method for fast precise optical calibration on a photolithography system, including: determining a fitting relationship for a spot width corresponding to a point light source based on distribution of field strength generated by the point light source at an exit plane of a focusing element; determining, based on the fitting relationship, a first correspondence between the spot width and a parameter for exposing a photoresist, where the spot width in the first correspondence is for optical microscopy; determining a first spot-width dataset for the point light source based on an optical microscopic image of a spot-mapping pattern on a surface of the photoresist; determining, based on the first spot-width dataset, a second correspondence between the spot width and the parameter; and determining the first correspondence as a means for determining the parameter, when the first correspondence and the second correspondence meet a preset condition.

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet

Abrégé

The present invention relates to a hybrid integrated SRAM storage unit structure and a manufacturing method therefor. In the present invention, some regions for which channel release is not performed, and remaining regions for which channel release is performed are selected, so as to form, at different positions, a FinFET structure with a larger driving current and a GAAFET with a smaller driving current, respectively, such that hybrid integration of the GAAFET and FinFET is realized, and the area of a circuit does not increase during the designing of a transistor proportion, thereby facilitating a further improvement in an integration density.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• B82Y 10/00 - Nanotechnologie pour le traitement, le stockage ou la transmission d’informations, p. ex. calcul quantique ou logique à un électron
• B82Y 40/00 - Fabrication ou traitement des nanostructures
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée

Abrégé

The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• H10N 50/85 - Matériaux de la région active
• H10N 52/00 - Dispositifs à effet Hall

Abrégé

A magnetoresistive memory unit, a preparation method, an array circuit, and a binary neural network chip. The magnetoresistive memory unit comprises a heavy metal layer configured to input a write current; a first magnetic tunnel junction, arranged on one side of a bottom surface of the heavy metal layer, a first preset included angle being formed between the easy axis of the first magnetic tunnel junction and an input direction of the write current; and a second magnetic tunnel junction, arranged on the other side of the bottom surface of the heavy metal layer, a second preset included angle being formed between the easy axis of the second magnetic tunnel junction and the input direction of the write current. The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G11C 11/15 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments à pellicules minces utilisant des couches magnétiques multiples
• H10N 50/10 - Dispositifs magnéto-résistifs
• G11C 11/409 - Circuits de lecture-écriture [R-W]

Abrégé

Provided in the present disclosure are a spin electronic device, a circuit unit, a computing network, an operator, and a neural network. A random spin electronic device comprises: a heater, which heater is configured to flow a write control pulse signal; an isolation layer, which is formed on the top surface of the heater; an antiferromagnetic layer, which is formed on the top surface of the isolation layer; a ferromagnetic layer, which is formed on the top surface of the antiferromagnetic layer, wherein the antiferromagnetic layer is configured to fix the magnetic moment of the ferromagnetic layer, such that the ferromagnetic layer does not generate a magnetic domain wall; an RKKY coupling layer, which is formed on the top surface of the ferromagnetic layer; and a magnetic tunnel junction, which is formed on one side of the top surface of the RKKY coupling layer, wherein when a write pulse signal is input, a magnetic domain wall in a magnetic domain wall free layer of the magnetic tunnel junction moves.

Classes IPC  ?

• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin

Abrégé

The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

t1122trainedtrained. According to the failure model construction method in the present invention, a prediction period is reasonably set, thereby greatly improving the accuracy of model prediction, and providing a more accurate basis for timely and effective intervention of failed storage units.

Classes IPC  ?

• G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle

Abrégé

pt[i]pt[i]pt[i] into a corresponding trained failure prediction model, so as to obtain a true/false failure binary classification prediction result of the storage unit within the next erasure cycle t+1; and when the prediction result indicates false failure, performing secondary determination, so as to obtain a prediction result indicating whether the storage unit is a false failure storage unit that actually needs to be repaired.

Classes IPC  ?

• G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
• G06N 3/08 - Méthodes d'apprentissage
• G11C 29/00 - Vérification du fonctionnement correct des mémoiresTest de mémoires lors d'opération en mode de veille ou hors-ligne
• G06N 3/0464 - Réseaux convolutifs [CNN, ConvNet]

Abrégé

Provided is a signal driving system with a constant slew. The signal driving system with the constant slew includes: a step voltage generation unit configured to provide multiplex arithmetic gradient voltage signals; a multiplexer, wherein an input end of the multiplexer is connected to the step voltage generation unit to receive the multiplex arithmetic gradient voltage signals, and another input end of the multiplexer is connected to a control signal generation unit, and the multiplexer is configured to selectively output the multiplex arithmetic gradient voltage signals under a control of a control signal generated by the control signal generation unit; a voltage following unit connected to the multiplexer, wherein the voltage following unit is configured to serve as an isolation and improve a driving ability; and an output following unit connected to the voltage following unit, wherein the output following unit is configured to drive a subsequently-connected load unit.

Classes IPC  ?

• H03K 19/0175 - Dispositions pour le couplageDispositions pour l'interface

Abrégé

A semiconductor device having a ferroelectric/negative capacitor and a method of manufacturing the same, and an electronic device including the semiconductor device are provided. According to the embodiments, the semiconductor device may include: a gate electrode and a source/drain electrode formed on a substrate; a positive capacitor formed on the substrate, a first terminal of the positive capacitor being electrically connected to the gate electrode; a ferroelectric or negative capacitor formed on the substrate, a first terminal of the ferroelectric or negative capacitor being electrically connected to the gate electrode, wherein a second terminal of one of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to a gate voltage application terminal, and a second terminal of the other of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to the source/drain electrode.

Classes IPC  ?

• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire

Abrégé

Disclosed are a memory device, a method of manufacturing the memory device, and an electronic device. The memory device may include: a plurality of first device layers, each including first and second source/drain regions and a channel region; a plurality of second device layers stacked on the first device layers, each including third and fourth source/drain regions and a channel region; and a gate stack extending vertically to pass through the first and second device layers. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer, and a memory cell is defined at an intersection of the gate stack and each device layer. The gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur

Abrégé

Disclosed are a memory device, a manufacturing method therefor, and an electronic device comprising a memory device. According to the embodiments, the memory device may comprises: a plurality of first device layers vertically stacked on a substrate, each first device layer comprising a first source/drain region and a second source/drain region which are respectively arranged at a lower vertical height and an upper vertical height, and a channel region therebetween; a plurality of second device layers stacked on the first device layers, each second device layer comprising a third source/drain region and a fourth source/drain region which are respectively arranged at a lower vertical height and an upper vertical height, and a channel region therebetween; and a gate stack extending vertically to pass through the first device layers and the second device layers. The gate stack comprises gate conductor layers and memory function layers arranged between the gate conductor layers and the device layers, memory cells being defined at the intersections of the gate stack and the device layers. Where the first device layers are adjacent to the second device layers, the gate stack has surfaces in curved shapes.

Classes IPC  ?

• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
• H10B 43/20 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur

Abrégé

A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

Classes IPC  ?

• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

Abrégé

Disclosed are a semiconductor apparatus, a manufacturing method, and an electronic device. The semiconductor apparatus includes first and second devices vertically stacked. Each of the first and second devices includes a first source/drain layer, a channel layer and a second source/drain layer vertically stacked, and a gate stack surrounding a periphery of the channel layer. The first device protrudes in a first direction relative to the second device to form a first step. A second step is defined by the second device. On a side in a second direction intersecting with the first direction, the first source/drain layer of each device protrudes in the second direction relative to the second source/drain layer and gate stack, to form a sub-step. Each sub-step is on a corresponding step. On another side in the second direction, the gate stack of each device protrudes in the second direction relative to the second source/drain layer.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

Provided are a reconfigurable neuron device based on ion gate regulation and a method of preparing the same. The device includes: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer and a top electrode layer which are sequentially stacked from bottom to top. A left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions are provided on two opposite edges of a bottom end of the synthetic antiferromagnetic layer, and a magnetic tunnel junction configured to output a spike signal is further provided in a middle portion of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer and the top electrode layer constitute an ion gate, the ionic liquid layer includes a positive ion and a negative ion.

Classes IPC  ?

• G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

Classes IPC  ?

• G11C 11/408 - Circuits d'adressage
• G11C 11/4097 - Organisation de lignes de bits, p. ex. configuration de lignes de bits, lignes de bits repliées

Abrégé

A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
• G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat

Abrégé

The present disclosure provides a memristor, including a transistor and a resistive random access memory, where a drain electrode of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory includes: the bottom electrode, a resistive random access material layer, a current compliance layer and a top electrode from bottom to top, where the current compliance layer is configured to stabilize a fluctuation of a low resistance by reducing a surge current and optimizing a heat distribution, so as to improve a calculation accuracy of a Hamming distance.

Classes IPC  ?

• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation

Abrégé

A gate-all-around transistor is provided, including: a semiconductor substrate, a nanostructure, a gate stack structure and a gate length defining structure. In a length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the two. Materials of the source region and drain region include a first metal semiconductor compound. The gate stack structure surrounds the channel region. In a length direction of the gate stack structure, a sidewall of the gate stack structure is recessed relative to a sidewall of the channel region to form a recess, and the gate length defining structure is filled in the recess. The gate length defining structure is made of a second metal semiconductor compound, and a semiconductor material for making the second metal semiconductor compound is different from that for making the first metal semiconductor compound.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

Abrégé

A center bit line framework of a three-dimensional memory, a three-dimensional memory, and a manufacturing method therefor, relating to the technical field of three-dimensional memories. The center bit line framework comprises: a first common source (ACS1) and a second common source (ACS2) which are arranged opposite to each other; multiple layers of word lines (WL) stacked between the first common source (ACS1) and the second common source (ACS2) in a first direction; a plurality of channel holes running through the multiple layers of word lines and connected to the first common source (ACS1) and the second common source (ACS2), each channel hole forming a byte string (string); and a plurality of center bit lines (CBL) which are arranged in the middles of the channel holes and are arranged at intervals in a second direction crossing the first direction, wherein the multiple layers of word lines (WL) and the plurality of byte strings (string) form a whole block (BLOCK), and the plurality of center bit lines (CBL) divide the whole block (BLOCK) into a first sub-block located at the upper part and a second sub-block located at the lower part, so as to respectively drive the byte strings (string) in the first sub-block and the second sub-block, thereby not only reducing the block capacity, but also reducing the channel length (i.e., the channel resistance).

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A metal interconnection structure of a semiconductor device and a method for forming the same. The method includes: providing a substrate; forming a first dielectric layer on the substrate; forming a first conductive structure in the first dielectric layer; etching back part of the first conductive structure; forming an etch stop layer on the first conductive structure; forming a second dielectric layer on the etch stop layer and performing chemical mechanical polishing; and forming a second conductive structure in the second dielectric layer, where the second conductive structure is electrically connected to the first conductive structure.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

Abrégé

A method for manufacturing a semiconductor and a semiconductor. The method includes: providing a substrate, wherein an active region trench is on the substrate, and a channel stack of a gate-all-around transistor is formed in the active region trench, the active region trench is divided into a source trench and a drain trench by the channel stack; epitaxially growing a source crystal structure in the source trench and a drain crystal structure in the drain trench, and stopping epitaxial growth before crystal planes with different orientations of the source crystal structure intersect and crystal planes with different orientations of the drain crystal structure intersect; and filling gaps between the crystal planes with different orientations of the source crystal structure and the drain crystal structure by using an isotropic metal material, and forming a source and a drain of the gate-all-around transistor in the source trench and the drain trench, respectively.

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.

Classes IPC  ?

• C12M 1/12 - Appareillage pour l'enzymologie ou la microbiologie avec des moyens de stérilisation, filtration ou dialyse
• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet

Abrégé

The present application provides a method for eliminating gate-all-around nanosheet channel damage. The method comprises: forming two or more channel layers and one or more sacrificial layers alternately on a substrate in sequence to form a channel stack; forming a dummy gate across the channel stack on the substrate, and forming a first side wall on the surface of the dummy gate; etching the sacrificial layer to form a concave structure on the side surface of the channel stack, and forming a second side wall in the concave structure; respectively manufacturing a source and a drain on two sides of the channel stack; when the channel layers in the channel stack are in contact with the dummy gate, etching the dummy gate and the adjacent channel layers until the sacrificial layer is exposed, and then etching the sacrificial layer to form a gate-all-around manufacturing space; and manufacturing an annular metal gate in the gate-all-around manufacturing space to form a gate-all-around component. The method for eliminating gate-all-around nanosheet channel damage provided by the present application can effectively eliminate the nanosheet channel damage in a gate-all-around component and improve the component performance.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

The present application provides a semiconductor device and a preparation method therefor. The preparation method comprises: providing a substrate; forming a fin, a dummy gate, first sidewalls, and a hard mask on one surface of the substrate; etching the substrate to form a groove, wherein the groove is located directly under the fin and passes through second sidewalls; forming a filling layer in the groove by using an insulating dielectric material, wherein the two opposite outer side surfaces of the filling layer are respectively flush with the outer side surfaces of the corresponding second sidewalls, and the heat conductivity of the insulating dielectric material is higher than that of the substrate; etching off the second sidewalls; etching two opposite ends of a plurality of sacrificial layers to form filling gaps of a predetermined length; filling the filling gaps to form inner sidewalls; selecting to epitaxially grow a source and a drain on the substrate; depositing a dielectric to form a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate and releasing channels of conductive nanosheets; and forming a gate-all-around. According to the present application, a parasitic channel in a CMOS device can be eliminated, and the thermal aggregation effect is avoided.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

Provided in the present application is a method for preparing a gate-all-around TFET device. The method comprises: sequentially and alternately forming one or more channel layers and one or more sacrificial layers on a substrate, so as to form a stacked channel layer; forming a dummy gate, which is across the channel stack layer, on the substrate, and forming a first side wall on the surface of the dummy gate; etching the sacrificial layer to form a concave structure on the side surface of the stacked channel layer, and forming a second side wall in the concave structure; sequentially preparing a source region and and a drain region, wherein when the source region is prepared, the drain region is protected by using a dielectric material, and when the drain region is prepared, the source region is protected by using a dielectric material; etching the dummy gate and the sacrificial layer to form a gate-all-around preparation space; and preparing an annular metal gate in the gate-all-around preparation space, so as to form a gate-all-around TFET device. By means of the method for preparing a gate-all-around TFET device provided in the present application, the preparation of a TFET device can be compatible with a preparation process of a gate-all-around device, thereby realizing batch production of gate-all-around TFET devices.

Classes IPC  ?

• H01L 29/73 - Transistors bipolaires à jonction

Abrégé

A method and an apparatus for correcting a proximity effect of an electron beam. An initial dose of the electron beam is preset for each exposed square, and proximity effect energy representing an influence of exposing all exposed squares other than a current exposed square on the current exposed is calculated. A corrected dose of the electron beam for the current exposed square is then calculated, and the corrected dose for each exposed square in the electron beam exposure layout matrix is successively calculated. Then, the above calculation iterates for T times to obtain a final corrected dose of the electron beam for each exposed square.

Classes IPC  ?

• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet

Abrégé

The present disclosure provides a method for optimizing mask parameters, and the method includes: acquiring a test pattern, light source parameters, and initial mask parameters, the initial mask parameters including a mask thickness and an initial mask sidewall angle; generating multiple sets of candidate mask parameters according to the initial mask sidewall angle in the initial mask parameters; the multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness; obtaining an imaging contrast of each set of candidate mask parameters based on the test pattern and the light source parameters; and selecting an optimal mask sidewall angle from the multiple sets of candidate mask parameters according to the imaging contrasts. By generating multiple sets of candidate mask parameters including different mask sidewall angles and the same mask thickness, and simulating these sets of candidate mask parameters respectively, the imaging contrast of each set of candidate mask parameters is obtained, so that the optimal mask sidewall angle is found according to the imaging contrasts. Therefore, by optimizing the mask parameters of the multi-layer film lens structure, the imaging contrast can also be significantly improved, and the imaging resolution can be improved.

Classes IPC  ?

• G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
• G03F 1/44 - Aspects liés au test ou à la mesure, p. ex. motifs de grille, contrôleurs de focus, échelles en dents de scie ou échelles à encoches
• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet

Abrégé

The present invention relates to a vertical surrounding gate thin film transistor and a manufacturing method therefor. The vertical surrounding gate thin film transistor sequentially comprises from bottom to top: a substrate; an isolation layer, provided on the substrate; a source electrode layer, provided on the isolation layer; a circular thin film channel, vertically provided on the source electrode layer; a drain electrode layer, provided on the upper part of the circular thin film channel; and a vertical surrounding gate, which fills the inside of the circular thin film channel and covers the side walls of said circular channel. In the present invention, a metal side wall is used as a sacrificial layer to achieve the sacrificial layer effect of protecting a lower-layer thin film and releasing the channel during an etching process. The semiconductor side wall is used as a channel; after removing the sacrificial layer by means of corrosion, a sheet-shaped or pillar-shaped semiconductor side wall channel stands between lower source metal and upper drain metal, and then a gate-all-around structure is formed by means of filling with a gate medium and gate metal. In addition, the channel is in the vertical direction, and the manufacturing process for the channel may be PVD, CVD or ALD without the need of epitaxy.

Classes IPC  ?

• H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant

Abrégé

Provided in the present invention is a manufacturing method for MOS devices. The method comprises: providing a substrate, wherein a gate region and a source/drain region are formed on the substrate, a through hole is formed in a dielectric layer on the substrate, and the through hole exposes the surface of the source/drain region; doping the source/drain region; performing pre-amorphization processing on the doped source/drain region, so as to form an amorphous layer on the surface of the source/drain region; processing the source/drain region by using an oxidation process, so as to cause impurities to realize segregation close to the amorphous layer; removing the oxidized amorphous layer; and forming a metal silicide on the surface of the source/drain region. The present invention can reduce the source-drain contact resistance.

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

A semiconductor device, including a substrate, a first electrode layer, a functional layer, and a second electrode layer. The functional layer is located between the first electrode layer and the second electrode layer, and includes a first region and a second region having a C-shaped structure surrounding the first region. The C-shape structure opens toward a direction that is parallel with the substrate and away from the first region, that is, the C-shaped structure opens toward a distal side. The first region is made of at least germanium, and the second region includes a C-shaped ferroelectric layer and a C-shaped gate that are sequentially stacked. The C-shaped ferroelectric layer serves as a memory layer of the memory device.

Classes IPC  ?

• H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
• H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur

Abrégé

The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Disclosed are a solid-state drive and a limited access control method therefor, and an electronic device. The solid-state drive comprises: a master chip, a flash memory array and a limited access circuit. The master chip comprises: a host interface controller, a central processing unit and a flash memory controller. The limited access circuit comprises: a limit counter, a first logic gate circuit and a state machine. Initialization data of all storage units of the limit counter are "1", and the first logic gate circuit performs or calculates multi-bit counting data separately read from storage units of the limit counter and transmits an OR operation result to the state machine; the state machine writes a "0" value into the limit counter every time the state machine detects that a host accesses the flash memory array, and prohibits the host from accessing the flash memory array when it is detected that the OR operation result is "0". In this way, an upper limit can be set for the number of times the flash memory array can be accessed in the solid-state drive, thereby effectively improving the security of data in the solid-state drive.

Classes IPC  ?

• G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
• G06F 21/60 - Protection de données
• G06F 21/44 - Authentification de programme ou de dispositif
• G06M 1/272 - Caractéristiques d'ordre général pour représenter le résultat d'un comptage sous la forme de signaux électriques, p. ex. par lecture de marques sur un tambour de compteur utilisant des moyens photo-électriques

Abrégé

The present invention relates to a semiconductor memory cell structure, a semiconductor memory as well as preparation method and application thereof. The semiconductor memory cell structure includes: a substrate; and a first transistor layer, an isolation layer and a second transistor layer. The first transistor layer includes a first stack structure formed by stacking a first source, a first channel, and a first drain from bottom to top; and a first gate located on a sidewall of the first stack structure. The second transistor layer includes: a second stack structure formed by stacking a second drain, a second channel, and a second source from bottom to top; and a second gate located on a sidewall of the second stack structure, at least a part of a sidewall of the second drain is in direct contact with the first gate. The present invention provides a 2T0C type DRAM cell with an improved structure, has the advantages of vertical stack integration, high integration level, low leakage current, short refresh time and the like, and is significantly superior to the existing 2T0C type DRAM.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince

Abrégé

The present invention relates to a vertical gate-all-around transistor structure and a preparation method therefor, and a vertical gate-all-around capacitor-less memory structure and a preparation method therefor. The capacitor-less memory structure comprises, from bottom to top: a base; an isolation layer; a read bit line layer; first columnar stacking structures, which are arranged on the upper surface of the read bit line layer, and are each formed by stacking a first channel layer, a read word line layer and a first hard mask layer; a first gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the first stacking structures and on the upper surface of the read bit line layer; a first gate layer, which covers a surface of the first gate dielectric layer; second columnar stacking structures, which are arranged on the upper surface of the first gate layer, and are each formed by sequentially stacking a second channel layer, a write bit line layer and a second hard mask layer from bottom to top; a second gate dielectric layer, which is arranged, in a surrounding manner, on side surfaces and upper surfaces of the second stacking structures and on the upper surface of the first gate layer; and a second gate layer. The present invention solves the problem of a low integration density caused by the horizontal arrangement of channels, and enhances the capability of a gate electrode to control a conductive channel.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of pattern transfer in a chip manufacturing process. Provided are a hard mask structure for integrated circuit manufacturing, and a method for manufacturing an integrated circuit device. The hard mask structure comprises a first hard mask layer and a second hard mask layer, which are stacked from top to bottom, wherein the first hard mask layer is used for forming a noble metal on the surface thereof and serves as a pattern transfer sacrificial layer, and the second hard mask layer serves as a protection layer and is used for etching the material of a pattern to be transferred; the first hard mask layer and the second hard mask layer are made of different materials, and can both tolerate the corrosion of a strong oxidizing chemical liquid which is used for removing the noble metal; and the second hard mask layer can tolerate the corrosion of a chemical liquid which is used for removing the first hard mask layer by means of wet etching, and a preset corrosion rate selection ratio of the second hard mask layer for the first hard mask layer is ensured. The present disclosure can avoid the killing of a device by means of noble metal ions, such that a noble metal thin film can be used for manufacturing large-scale integrated circuits.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou

Abrégé

A three-dimensional reservoir based on three-dimensional volatile memristors and a method for manufacturing the same. In the three-dimensional reservoir, a memory layer, a select layer, and an electrode layer in each via form a memristor which is a reservoir unit. The three-dimensional reservoir is formed based on a stacking structure and multiple vias. The three-dimensional reservoir is constructed by using virtual nodes generated from dynamic characteristics of the three-dimensional memristors. An interfacial memristor is first constructed, and its volatility is verified through electric tests. A vertical three-dimensional array is manufactured based on the volatile memristor. A dynamic characteristic of the memristor is adjusted through a Schottky barrier. Different layers in the three-dimensional reservoir correspond to different reservoirs, which are constructed by controlling memristors in the different layers, respectively.

Classes IPC  ?

• H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation

Abrégé

A storage device includes a substrate, a storage unit array, and word lines extending in the first direction. The storage unit array includes storage units arranged along a first direction and a second direction. Each storage unit includes: an active region extending in a third direction and including a vertical stack of first source/drain, channel and second source/drain layers, and a gate stack between the first and second source/drain layers in a vertical direction and sandwiching the channel layer from at least two opposite sides. First source/drain layers of each column are continuous to form a bit line extending in the second direction in a zigzag shape. Each word line extends in the first direction to intersect the active regions of a respective row, and is electrically connected to the gate stack of each storage unit on two opposite sides of the channel layer.

Classes IPC  ?

• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/04 - Corps semi-conducteurs caractérisés par leur structure cristalline, p.ex. polycristalline, cubique ou à orientation particulière des plans cristallins
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An activation function generator based on a magnetic domain wall driven magnetic tunnel junction and a method for manufacturing the same are provided, including: a spin orbit coupling layer configured to generate a spin orbit torque; a ferromagnetic free layer formed on the spin orbit coupling layer and configured to provide a magnetic domain wall motion racetrack; a nonmagnetic barrier layer formed on the ferromagnetic free layer; a ferromagnetic reference layer formed on the nonmagnetic barrier layer; a top electrode formed on the ferromagnetic reference layer; antiferromagnetic pinning layers formed on two ends of the ferromagnetic free layer; a left electrode and a right electrode respectively formed at two positions on the antiferromagnetic pinning layers.

Classes IPC  ?

• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/01 - Fabrication ou traitement
• H10N 50/80 - Détails de structure
• H10N 50/85 - Matériaux de la région active

Abrégé

A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layer each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

Classes IPC  ?

• H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]

Abrégé

Disclosed are a semiconductor device with a spacer and a C-shaped channel portion, a method of manufacturing the same, and an electronic apparatus including the semiconductor device. The semiconductor device may include: a channel portion on a substrate, wherein the channel portion includes a curved nanosheet or nanowire with a C-shaped cross-section; a first source/drain portion and a second source/drain portion respectively located at upper and lower ends of the channel portion with respect to the substrate; a first gate stack and a second gate stack located on opposite sides of the channel portion; a first spacer located between the first gate stack and the first source/drain portion and between the first gate stack and the second source/drain portion respectively; and a second spacer located between the second gate stack and the first source/drain portion and between the second gate stack and the second source/drain portion respectively.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

Abrégé

A multi-resistance-state spintronic device, including: a top electrode and a bottom electrode respectively connected to a read-write circuit; and a magnetic tunnel junction between two electrodes. The magnetic tunnel junction includes from top to bottom: a ferromagnetic reference layer, a barrier tunneling layer, a ferromagnetic free layer, and a spin-orbit coupling layer. Nucleation centers are provided at two ends of the ferromagnetic free layer to generate a magnetic domain wall; the spin-orbit coupling layer is connected to the bottom electrode, and when a write pulse is applied, an electron spin current is generated and drives the magnetic domain wall through a spin-orbit torque to move; a plurality of local magnetic domain wall pinning centers are provided at an interface between the spin-orbit coupling layer and the ferromagnetic free layer to enhance a strength of a DM interaction constant between interfaces.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• H03K 19/21 - Circuits OU EXCLUSIF, c.-à-d. donnant un signal de sortie si un signal n'existe qu'à une seule entréeCircuits à COÏNCIDENCES, c.-à-d. ne donnant un signal de sortie que si tous les signaux d'entrée sont identiques
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• H10N 50/80 - Détails de structure
• H10N 50/85 - Matériaux de la région active

Abrégé

A spin electronic device (100), an array circuit, and an optimization method for a recurrent neural network. The spin electronic device (100) comprises: a magnetic domain device (110) having a preset thickness, wherein the magnetic domain device (110) can form a labyrinth-like magnetic domain structure under the modulation of Dzyaloshinskii-Moriya interaction and dipole-dipole interaction, the labyrinth-like magnetic domain structure comprising a plurality of magnetic domain areas having random magnetic domain directions, and the junction of two adjacent magnetic domain areas being a magnetic domain wall; at least one cycle of heterogeneous thin film (120), which is arranged on a first surface of the magnetic domain device (110); and at least four electrodes (130), which are arranged on a second surface of the magnetic domain device (110), wherein the four electrodes (130) are respectively connected to different magnetic domain areas.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs

Abrégé

Provided is a method for correcting a lithography pattern of a surface plasma, including: forming a plurality of test patterns on a test mask; exposing a photoresist layer by using the test mask containing the test patterns to form a plurality of photoresist patterns; establishing a first data table based on a correspondence between the first test parameter and the second test parameter of the test pattern and the first exposure parameter and the second exposure parameter of the photoresist pattern; processing the first data table according to the first exposure parameter to obtain a second data table; and respectively correcting second test parameters of a plurality of design patterns according to the second data table to obtain corrected design patterns, and manufacturing a mask for exposure by using the corrected design patterns.

Classes IPC  ?

• G03F 1/44 - Aspects liés au test ou à la mesure, p. ex. motifs de grille, contrôleurs de focus, échelles en dents de scie ou échelles à encoches
• G03F 1/72 - Réparation ou correction des défauts dans un masque
• G03F 7/20 - ExpositionAppareillages à cet effet

Abrégé

A laminated structure and a preparation method therefor, a pattern transfer method, and a reworking method. A stripping layer (100) capable of being etched and removed by means of a wetting method is arranged below a bottom anti-reflection structure (200), so that pattern transfer can be realized, and when reworking is needed, a substrate can be separated by removing the stripping layer (100) by means of the wetting method, so that the reworking difficulty is greatly reduced, and the substrate is not damaged, thereby avoiding the formation of defects.

Classes IPC  ?

• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• G03F 7/09 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires
• G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage

Abrégé

A memory device, a method of manufacturing the same, and an electronic apparatus including the same. The memory device includes: a plurality of cell active layers vertically stacked on a substrate, each cell active layer including a lower source/drain region and an upper source/drain region located at different vertical heights and a channel region between the lower source/drain region and the upper source/drain region; a gate stack on the substrate and extending vertically relative to the substrate to pass through the cell active layers, the gate stack including a gate conductor layer and a memory functional layer arranged between the gate conductor layer and the cell active layers, and a memory cell being defined at an intersection of the gate stack and each cell active layer; and a conductive metal layer arranged on a lower surface of each cell active layer and/or an upper surface of each cell active layer.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur

Abrégé

Provided are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate relative to the substrate, including lower and upper source/drain regions, and a middle portion between the lower and upper source/drain regions for defining a channel region; first and second gate stacks which are disposed on first and second sides of the active region which are opposite to each other in a lateral direction relative to the substrate; and a body contact layer disposed on the second side of the active region to overlap a part of the middle portion of the active region, so as to apply a body bias to the active region, wherein the second gate stack includes first and second portions below and above the body contact layer respectively.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 21/8234 - Technologie MIS
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

Disclosed are a vertical semiconductor device with a body contact, a manufacturing method, and an electronic apparatus. The semiconductor device includes: an active region vertically disposed on a substrate, including lower and upper source/drain regions, and a middle portion between lower and upper source/drain regions for defining a channel region; a gate stack on a first side of the active region in a lateral direction to at least overlap with the middle portion; and a body contact layer on a second side of the active region opposite to the first side in the lateral direction to overlap with the middle portion to apply a body bias to the active region. In a vertical direction, distances between a part of the middle portion overlapping with the body contact layer and the lower source/drain region and between the part and the upper source/drain region are first and second spacing distances, respectively.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

Disclosed in the present application are a spin-wave-unit-based in-memory computing array structure and a control method therefor, which relate to the field of integrated circuits. The spin-wave-unit-based in-memory computing array structure comprises a plurality of in-memory computing units which are connected to one another, each in-memory computing unit comprising a spin wave unit and a transistor unit connected to the spin wave unit. Each spin wave unit comprises: a spin wave body, the spin wave body comprising a spin wave signal generation end and a spin wave signal detection end which are oppositely arranged; a first magnetic domain wall driving unit and a second magnetic domain wall driving unit which are respectively arranged on two adjacent sides of the spin wave body away from one side of the spin wave signal generation end and from one side of the spin wave signal detection end; and a magnetic domain wall in the spin wave body. The weighting in Hopfield neutral network computing reaches a preset weighting. Due to the occurrence of scattering and reflection of spin waves during a propagation process and the presence of fluctuations during magnetization of the magnetic domain walls themselves, the reliability and stability of spin electronic devices and in-memory computing are improved.

Classes IPC  ?

• G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
• G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
• G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques