Abstract

A method and an apparatus for training on imaging of plasma lithography. The method comprises: determining a structure for training on an imaging of the plasma lithography is determined, where a training mask pattern repeats periodically along two directions in the structure; constructing a model simulating the structure; obtaining a training image pattern of the plasma lithography is obtained through computation based on the model, where the training image pattern corresponds to the training mask pattern; and training a fast imaging model through the training mask pattern and the training image pattern to obtain a trained imaging model for the training mask pattern.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06F 111/14 - Details relating to CAD techniques related to nanotechnology

Abstract

The present disclosure provides a semiconductor device, a method, and an electronic apparatus. The device includes: a substrate; a channel layer stacking portion including multiple channel layers along a thickness direction of the substrate, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end along the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a spacer structure including first and second spacers. The first spacer is between first ends and second ends of adjacent channel layers, and includes a cavity. The second spacer is on a side of the channel layer stacking portion away from the substrate and on both sides of the gate-all-around along the length direction. A dielectric constant of the first spacer is greater than that of the second spacer.

IPC Classes  ?

• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 30/00 - Field-effect transistors [FET]
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

The present disclosure provides a semiconductor device, a method and an electronic apparatus. The semiconductor device includes a substrate; a channel layer stacking portion including multiple channel layers, a length direction of the channel layer is perpendicular to the thickness direction of the substrate, and the channel layer includes a first end, a middle section and a second end in the length direction; a gate-all-around surrounding the middle section; a source/drain functional portion; and a first spacer between the source/drain functional portion and the gate-all-around, between the first ends of adjacent channel layers and between the second ends of the adjacent channel layers. The first spacer includes first and second portions in the length direction, the first portion is in contact with the gate-all-around, the second portion is in contact with the source/drain functional portion. A material of the first portion is different from that of the second portion.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/01 - Manufacture or treatment
• H10D 64/01 - Manufacture or treatment

Abstract

Disclosed in the present application are a reservoir computing network optimization method and a related apparatus. The method comprises: sampling an input signal to obtain a sampling signal; performing quantization processing on the sampling signal by means of at least two kinds of quantization modes, so as to obtain at least two kinds of digital signals, values of elements in different digital signals being different; inputting voltage pulses corresponding to the elements in the different digital signals into reservoirs constructed by different quantities of virtual nodes, so as to extract signal features of the input signal in different quantization modes by the different reservoirs. By quantizing signals in different modes and inputting same into reservoirs constructed by different quantities of virtual nodes, the richness of internal states of the reservoirs can be improved, thereby further improving the signal identification accuracy of a reservoir system.

IPC Classes  ?

• G06N 3/044 - Recurrent networks, e.g. Hopfield networks
• G06N 3/0495 - Quantised networksSparse networksCompressed networks
• G06N 3/0985 - Hyperparameter optimisationMeta-learningLearning-to-learn

Abstract

A method for manufacturing a MOS device, comprising: providing a substrate comprising a gate portion and a source-or-drain portion, where a through hole is formed in a dielectric layer disposed on the substrate and exposes a surface of the source-or-drain portion; doping the source-or-drain portion; amorphizing the doped source-or-drain portion to form an amorphous layer on a surface of the source-or-drain portion; oxidizing the source-or-drain portion to segregate dopants in adjacency of the amorphous layer; removing the oxidized amorphous layer; and forming a metal silicide on the surface of the source-or-drain portion. Contact resistance of a source and/or a drain is significantly reduced.

IPC Classes  ?

• H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
• H01L 21/321 - After-treatment
• H01L 21/3215 - Doping the layers
• H10D 30/01 - Manufacture or treatment

Abstract

The present disclosure relates to a vertical gate-all-around thin film transistor and a method of manufacturing a vertical gate-all-around thin film transistor. The vertical gate-all-around thin film transistor includes a substrate; an isolation layer on the substrate; a source layer on the isolation layer; an annular thin film channel on the source layer; a drain layer on an upper part of the annular thin film channel; and a vertical surrounding gate filled on an inner side of the annular thin film channel and covering a sidewall of the annular thin film channel, wherein the substrate, the isolation layer, the source layer, the annular thin film channel, the drain layer, and the vertical surrounding gate are stacked sequentially from bottom to up.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H10D 30/01 - Manufacture or treatment

Abstract

A method for optimizing a mask absorption material based on a surface plasmon multilayer structure. The method comprises: S1) constructing a plurality of structures for a multilayer superlens; S2) simulating light transmission in each structure of the plurality of structures through software modelling to obtain an image contrast of a pattern formed at a central region of a photoresist coated on a base layer; and S3) determining the parameter of the layer of the plurality of absorption masks for a structure of the multilayer superlens based on the image contrast. In comparison with the conventional technology, the above method is based on the multilayer structure and optimizes three-dimensional parameters of the absorption mask(s). Experiments have shown that the above method has a significant effect on improving the resolution and the image contrast of the multilayer structure.

IPC Classes  ?

• G02B 5/00 - Optical elements other than lenses
• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

A 3D stacked DRAM and a method for manufacturing the same. The 3D stacked DRAM comprises: a substrate, a source, a drain, a storage structure, a common source electrode, drain electrodes, and a gate. The storage structure comprises a stack of nanosheets extending from the source to the drain. The common source electrode is in contact with each nanosheet and is grounded. A portion of the nanosheets extending into the drain is shaped as a stair structure. Each drain electrode runs into the drain, is in contact with a respective nanosheet in the stair structure and is connected to a bit line. The gate surrounds each nanosheet and is connected to a word line.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

Provided in the present disclosure are a ferroelectric device and a manufacturing method therefor, which can be applied in the technical field of semiconductors. The ferroelectric device comprises: a substrate layer; a bottom gate electrode, located within the substrate layer; a ferroelectric layer, located inside the ferroelectric device, the lower surface of the ferroelectric layer being in contact with the bottom gate electrode; a first device isolation layer, surrounding the ferroelectric layer; a channel layer, which is in contact with the upper surface of the ferroelectric layer; a source electrode, a drain electrode and a top gate electrode, which are all in contact with the upper surface of the channel layer; a second device isolation layer, which is located between the source electrode, the drain electrode and the top gate electrode; and a stop layer, which is located between the first device isolation layer and the second device isolation layer and surrounds the source electrode, the drain electrode and the top gate electrode.

IPC Classes  ?

• H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Abstract

Provided in the present disclosure are a preparation method for a semiconductor device, and a semiconductor device. The preparation method comprises: performing oxidization and deposition on a first surface of a first substrate to obtain a composite dielectric layer; performing metal thin film deposition on the composite dielectric layer to obtain a first metal layer; etching the first metal layer on a first top surface and the first metal layer on a second top surface, and exposing the composite dielectric layer, so as to obtain a first sidewall metal layer; performing metal thin film deposition on the first sidewall metal layer, the composite dielectric layer on the first top surface and the composite dielectric layer on the second top surface, so as to obtain a second metal layer; performing metal thin film deposition on the second metal layer to obtain a third metal layer; performing photolithography and etching on the third metal layer and the second metal layer to obtain a gate electrode; and performing doping on the first top surface adjacent to a second side surface of the gate electrode and the second top surface adjacent to a third side surface of the gate electrode, so as to respectively obtain a first source/drain region and a second source/drain region.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

The capacitor-free memory includes: a substrate; an isolation layer; a read bit line layer; a columnar first stack on an upper surface of the read bit line layer which including a first channel layer, a read word line layer, and a first hard mask layer; a first gate dielectric layer surrounding a side surface and an upper surface of the first stack, and the upper surface of the read bit line layer; a first gate layer covering a surface of the first gate dielectric layer; a columnar second stack on an upper surface of the first gate layer which including a second channel layer, a write bit line layer, and a second hard mask layer; a second gate dielectric layer surrounding a side surface of the second stack, an upper surface of the second stack, and the upper surface of the first gate layer; and a second gate layer.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present invention relates to the technical field of integrated circuit design. Disclosed are an RRAM-based blood test system and method, used for solving the problem of how to improve the test efficiency and accuracy of blood test. The system comprises: a calculation chip, an RRAM chip, a power supply module, and a sensor module; the calculation chip is connected to the RRAM chip; the RRAM chip is connected to the sensor module; the power supply module is separately connected to the calculation chip and the RRAM chip; the sensor module is used for testing substances in blood and converting test result data into a plurality of pieces of first voltage data; the RRAM chip is used for carrying out data preprocessing on the plurality of pieces of received first voltage data to obtain second current data; and the calculation chip is used for performing function calculation on the second current data according to a preset function calculation model and on the basis of the second current data to obtain a classification result for the blood. In this way, the blood is tested by means of an integrated circuit, and the efficiency and accuracy of disease screening in blood are improved.

IPC Classes  ?

• G01N 27/416 - Systems

Abstract

The present disclosure relates to a hybrid integrated SRAM memory cell structure and a method of manufacturing a hybrid integrated SRAM memory cell structure. The hybrid integrated SRAM memory cell structure includes a plurality of transistors, and the plurality of transistors include a pull-up transistor, a pull-down transistor and a pass-gate transistor. At least one of the pull-up transistor, the pull-down transistor and the pass-gate transistor is a gate-all-around field effect transistor, at least one of the pull-up transistor, the pull-down transistor and the pass-gate transistor is a fin field effect transistor; and the fin field effect transistor is a superlattice stack layer fin field effect transistor.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

The present disclosure provides a thin film transistor and a method of manufacturing a thin film transistor. The thin film transistor includes a first conductive layer, an isolation layer and a semiconductor layer. The isolation layer is formed on a side of the first conductive layer, the isolation layer includes a body portion and a buffer portion that are arranged continuously, the body portion includes a first surface away from and in parallel to the first conductive layer, and a thickness of the buffer portion gradually decreases from a side close to the body portion to a side away from the body portion. The semiconductor layer includes a first portion and a second portion that are arranged continuously, the first portion is formed on a side of the isolation layer away from the first conductive layer, and the second portion is in contact with the first conductive layer.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

A Static Random Access Memory (SRAM) cell, a method of manufacturing an SRAM cell, a memory including such SRAM cell and an electronic device are provided. The SRAM cell includes: a substrate; first and second pull-up transistors, first and second pass-gate transistors at substantially a same height relative to the substrate; and first and second pull-down transistors at substantially a same height relative to the substrate, where the first pull-down transistor is stacked on the first pull-up transistor, and the second pull-down transistor is stacked on the second pull-up transistor, where an active region of each of the first and second pull-up transistors, the first and second pull-down transistors, the first and second pass-gate transistors includes a first source/drain layer, a channel layer and a second source/drain layer sequentially disposed in a vertical direction, and the channel layer is in a form of a vertical nanosheet.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

A memory cell of a dynamic random access memory, an array, a memory, and a device are provided. The memory cell includes a write word line, a write bit line, a write transistor, a read word line, a read bit line and a read transistor. The read transistor includes multiple channel layers composed of different materials. A gate electrode, a first electrode and a second electrode of the write transistor are connected to the write word line, the write bit line and a gate electrode of the read transistor respectively. The first and second electrodes of the write transistor are respectively source and drain electrodes of the write transistor. First and second electrodes of the read transistor are connected to the read bit line and the read word line respectively. The first and second electrodes of the read transistor are respectively source and drain electrodes of the read transistor.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device, which may be applied to the field of semiconductor technology. The semiconductor device includes: a first source/drain layer, a channel layer and a second source/drain layer sequentially provided in a vertical direction on a substrate, where the channel layer is connected between the first source/drain layer and the second source/drain layer, and the channel layer has a doping profile along the vertical direction, in which a middle portion of the channel layer has a high doping concentration and end portions of the channel layer have a low doping concentration; and a body contact connected to the middle portion of the channel layer, where the middle portion of the channel layer has a height in the vertical direction greater than a height of the body contact in the vertical direction.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

The present disclosure relates to a thin film transistor and a method of manufacturing a thin film transistor. The thin film transistor includes: a substrate; an insulation layer on an upper surface of the substrate; a fin gate on an upper surface of the insulation layer; a surrounding gate dielectric layer and a surrounding channel, where the surrounding gate dielectric layer covers a top surface of the fin gate and a side surface of the fin gate, and the surrounding channel surrounds an outer wall of the surrounding gate dielectric layer; and a source region and a drain region on the upper surface of the substrate, where the source region and the drain region are located on two opposite sides of the fin gate respectively and are in contact with the surrounding channel.

IPC Classes  ?

• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]

Abstract

An operational amplifier circuit and an operating method thereof. The operational amplifier circuit comprises: a first operational amplifier, which is used for outputting a regulating signal on the basis of a first signal, wherein the first operational amplifier comprises a chopper circuit, the chopper circuit being used for regulating an offset voltage and noise of the regulating signal; and a second operational amplifier, which is used for regulating an offset voltage and noise of the first signal on the basis of the regulating signal, in order to output a second signal. Thus, a second operational amplifier is integrated into an operational amplifier circuit, the second operational amplifier being used for outputting a regulating signal to a first operational amplifier, so as to regulate an offset voltage and noise of a first signal.

IPC Classes  ?

• H03F 1/26 - Modifications of amplifiers to reduce influence of noise generated by amplifying elements

Abstract

A method for operating a memory cell and a resistive random access memory, and an electronic device are provided. The method for operating a memory cell includes: performing a writing operation and an erasing operation on a resistive device. The writing operation includes: applying a writing voltage on the resistive device; determining whether a resistance value of the resistive device reaches a low resistance state threshold; and applying a constant current to the resistive device in response to the resistance value of the resistive device reaching the low resistance state threshold, wherein a voltage value generated by the constant current on the resistive device is smaller than a voltage value of the writing voltage.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The present disclosure provides a method of manufacturing a vertical device by firstly etching an active region of the device, which may be applied to the field of semiconductor technology. The method includes: providing a stack of a first source/drain defining layer, a channel defining layer and a second source/drain defining layer on a substrate; providing a mask layer on the stack; providing a patterned photoresist on the stack, where the patterned photoresist exposes a first region; etching off, in the first region, a first depth of the stack based on the patterned photoresist; and further etching off, in the first region and a second region on an inner side of the first region, a second depth of the stack based on the mask layer, where the stack is penetrated by the etching off and the further etching off in the first region to form an isolation trench.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks

Abstract

An analytical method and an analytical apparatus for quantitatively calculating line edge roughness of plasmon super diffraction photolithography. The method includes: determining a theoretical point spread function of a light source based on field intensity distribution of the light source at an exit plane of a focusing element of the plasmon super diffraction photolithography; determining multiple transverse widths of spots in a spot-mapping pattern based on the spot-mapping pattern; determining actual point spread functions corresponding to the multiple transverse widths, based on the theoretical point spread function and the multiple transverse widths; and establishing an analytical equation of line edge roughness of the plasmon super diffraction photolithography based on the variation due to line edge roughness, an exposure dose of each line pattern, the near-field photoresist contrast, and the logarithmic slope of each line pattern. Applicability of surface plasma super diffraction photolithography technology is greatly improved.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• G01Q 60/24 - AFM [Atomic Force Microscopy] or apparatus therefor, e.g. AFM probes

Abstract

The present disclosure relates to the field of microelectronic manufacturing technology, in particular to a SOT-MRAM memory cell and a method of manufacturing a SOT-MRAM memory cell. The SOT-MRAM memory cell includes a bottom electrode layer, a magnetic tunnel junction, an antiferromagnetic layer and a top electrode layer provided sequentially from bottom to top, where the magnetic tunnel junction includes a free layer, a tunneling layer and a pinning layer, the bottom electrode layer is a stack of odd number of layers, and the odd number of layers include at least one W metal layer and at least one Ta metal layer.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/01 - Manufacture or treatment
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/85 - Materials of the active region

Abstract

A semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate comprising a first surface and a second surface opposite to each other; forming, on the first surface, a first transistor structure comprising a first channel layer, a first gate structure disposed on the first channel layer, and a first source-drain epitaxial layer disposed on two lateral sides of the first gate structure; providing, on the second surface, a second transistor structure comprising a second channel layer, a second gate structure disposed on the second channel layer, and a second source-drain epitaxial layer disposed on two lateral sides of the second gate structure; forming, in the second source-drain epitaxial layer and the substrate, a first conductive plug electrically connected to the first source-drain epitaxial layer; and forming a first interconnection layer on the first conductive plug and the second gate structure.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Provided in the present invention is an optimization method for a mask absorption material based on a surface plasma multilayer film structure. The method comprises the following steps: S1) constructing a plurality of groups of multilayer film superlens structures having different mask absorption layer parameters; S2) modeling and simulating optical behaviors of light in the multilayer film superlens structures by means of software, so as to obtain the image contrast of a spatial image formed at the middle position of a photoresist covering a substrate layer; and S3) on the basis of the image contrast, determining the mask absorption layer parameters of the multilayer film superlens structures. Compared with the prior art, the present invention optimizes three-dimensional parameters of mask absorption layers on the basis of multilayer film structures, and the results show that the resolution and imaging contrast of the multilayer film structures are significantly improved.

IPC Classes  ?

• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G03F 1/38 - Masks having auxiliary features, e.g. special coatings or marks for alignment or testingPreparation thereof
• G02B 5/00 - Optical elements other than lenses
• G02B 1/00 - Optical elements characterised by the material of which they are madeOptical coatings for optical elements

Abstract

The present disclosure relates to a method of manufacturing a fin in a transistor and a method of manufacturing a fin field effect transistor. The method of manufacturing the fin in the transistor includes: epitaxially growing a semiconductor layer on a substrate; etching the semiconductor layer into a fin-shaped portion by using a spacer transfer technique; oxidizing a sidewall of the fin-shaped portion with ozone, so as to form an oxide film on the sidewall; and etching the oxide film by using an atomic layer etching method, so as to remove the oxide film.

IPC Classes  ?

• H01L 29/66 - Types of semiconductor device
• H01L 21/311 - Etching the insulating layers
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate

Abstract

A vertical semiconductor device with a continuous gate length and a method of manufacturing the same, and an electronic apparatus including the same. The semiconductor device includes: a semiconductor base on a substrate; first and second vertical channel portions on the semiconductor base, where the first and second vertical channel portions are vertical relative to the substrate, protrude from the semiconductor base, are spaced apart from in a first direction and self-aligned with each other, and the semiconductor base extends continuously between the first and second vertical channel portions; a first source/drain portion and a second source/drain portion on the first vertical channel portion and the second vertical channel portion, respectively; and a gate stack at least partially on the first vertical channel portion, the semiconductor base, and the second vertical channel portion to define a continuous channel between the first source/drain portion and the second source/drain portion.

IPC Classes  ?

• H10D 30/63 - Vertical IGFETs
• H10D 30/01 - Manufacture or treatment
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates

Abstract

The present disclosure relates to a nanosheet gate-all-around transistor and a method of manufacturing a nanosheet gate-all-around transistor. The nanosheet gate-all-around transistor includes: a substrate having a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, the stack formed by the nanosheets constitutes a plurality of conductive channels, and the nanosheets are graphene nanosheets; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where a spacer is provided between the source/drain region and the gate-all-around.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A thin film transistor, a memory, and a method of manufacturing a thin film transistor are provided, which relate to a field of semiconductor device technology. The thin film transistor includes a substrate; a gate on a surface of the substrate; an insulation layer covering the gate; a source and a drain; a channel between the insulation layer and the source and the drain, wherein the source and the drain are located on a surface of the channel away from the substrate; and an insulation dielectric layer between the source and the drain, wherein the insulation dielectric layer partially overlaps with the channel in a first direction, wherein the substrate, the gate, the insulation layer, the source and the drain, the channel, and the insulation dielectric layer are stacked in the first direction.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H10D 30/01 - Manufacture or treatment

Abstract

The present disclosure provides a skyrmion transistor and a method of controlling a skyrmion transistor. The transistor includes: a ferromagnetic nanotube; a writing magnetic tunnel junction and a reading magnetic tunnel junction surrounding both ends of the ferromagnetic nanotube respectively; and a ferroelectric ring surrounding an outer side of the ferromagnetic nanotube and located between the writing magnetic tunnel junction and the reading magnetic tunnel junction, where the ferromagnetic nanotube and the ferroelectric ring form a ferromagnetic/ferroelectric heterojunction.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10N 50/85 - Materials of the active region

Abstract

The present disclosure discloses a deep ultraviolet lithography method, a lithography pattern and a semiconductor structure, which relates to the field of deep ultraviolet lithography technology. The deep ultraviolet lithography method includes: dividing, when a depth of field of the deep ultraviolet lithography is less than a height of the step of the substrate, a pattern to be photoetched into at least two portions according to a distribution situation of the step, where each of the at least two portions corresponds to an on-step pattern or an off-step pattern of the step; corresponding the at least two portions of the pattern to be photoetched onto at least two masks respectively; and simultaneously baking and developing the exposed at least two masks after the at least two masks are exposed sequentially.

IPC Classes  ?

• H01L 21/311 - Etching the insulating layers
• G03F 7/20 - ExposureApparatus therefor

Abstract

A static random access memory (SRAM) cell includes: a substrate; first and second interconnection structures parallel to an upper surface of the substrate and opposite to each other; a first pull-down (PD) transistor and a first pass gate (PG) transistor on the first interconnection structure; a second PD transistor and a second PG transistor on the second interconnection structure; a first pull-up (PU) transistor under the first interconnection structure and overlapping vertically with the first PD transistor; and a second PU transistor under the second interconnection structure and overlapping vertically with the second PD transistor. Channel layers of the first PU, PD, PG transistors are offset from the first interconnection structure on a side away from the second interconnection structure. Channel layers of the second PU, PD, PG transistors are offset from the second interconnection structure on a side away from the first interconnection structure.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors
• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

Provided in the present application are a three-dimensional vertical memristor and a manufacturing method therefor. The three-dimensional vertical memristor comprises: a substrate; alternately stacked on the substrate, insulating layers and word line layers, there being at least three insulating layers and at least two word line layers, the oxygen ion capturing capability of at least one word line layer being greater than or equal to a first preset value, and the oxygen ion capturing capability of at least one word line layer being less than the first preset value; a channel penetrating through the insulating layers and the word line layers; and, located on a side wall of the channel, a storage layer, a selection layer and a bit line layer, the selection layer being located on the side of the storage layer away from the side wall of the channel, and the bit line layer being located on the side of the selection layer away from the channel. In the present application, the word line layers having different oxygen ion capturing capabilities are provided, among which the word line layer having a strong oxygen ion capturing capability exhibits a non-volatile property, and the word line layer having a weak oxygen ion capturing capacity exhibits a dynamic property, thereby achieving a three-dimensional memristor array having different properties.

IPC Classes  ?

• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices

Abstract

The present disclosure relates to a method of obtaining a nanoscale line by using a laser, including: forming a dielectric layer and an amorphous silicon layer on a substrate sequentially; irradiating a mask plate by using the laser to perform a silicon crystallization in a partial region of the amorphous silicon layer, where a grain boundary of a polycrystalline silicon formed by the silicon crystallization in the partial region of the amorphous silicon layer is determined by a spacing between holes with a regular shape on the mask plate; performing a planarization process on the grain boundary of the polycrystalline silicon of the amorphous silicon layer; removing the grain boundary by using a corrosion solution to form a grain boundary trench; and obtaining the nanoscale line on the substrate by using the grain boundary trench.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching

Abstract

A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

IPC Classes  ?

• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

Provided in the present disclosure are a prediction model training method and apparatus, a resistance-state retention restoration method and apparatus, and a device. The prediction model training method comprises: performing a first preset number of erase/write operations on all M resistive random access memories in a conductive state, so as to obtain M first resistive random access memories and erase/write operation voltages respectively corresponding to the M first resistive random access memories; for each of the M first resistive random access memories, performing, within a first preset duration, a continuous read operation on the first resistive random access memory at every second preset duration, so as to obtain first resistance-state data; performing a step-by-step read operation on the first resistive random access memory at every second preset duration, so as to obtain second resistance-state data; on the basis of the first resistance-state data, second resistance-state data and erase/write operation voltage corresponding to each of the M first resistive random access memories, obtaining training sample data; and on the basis of the training sample data, training a resistance-state retention prediction model, so as to obtain a target prediction model.

IPC Classes  ?

• G11C 29/50 - Marginal testing, e.g. race, voltage or current testing

Abstract

An optimization method and apparatus for an oxide-based resistive random access memory, and a retention test method and apparatus for an oxide-based resistive random access memory, which relate to the technical field of microelectronics. The optimization method comprises: performing a forming operation on an oxide-based resistive random access memory, so as to obtain a first resistive random access memory in an active state (S110); performing a first preset number of first erase/write operations on the first resistive random access memory, so as to obtain a second resistive random access memory within a preset resistive state range (S120); and performing a second preset number of second erase/write operations on the second resistive random access memory, so as to obtain a target resistive random access memory within the preset resistive state range (S130), wherein a second reset voltage, which is used in the second erase/write operations, is obtained by finding the sum of a preset voltage value and an average value of first reset voltages, which are respectively used in the first preset number of first erase/write operations.

IPC Classes  ?

• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or

Abstract

The present disclosure provides a stacked nanosheet gate-all-around device with an air spacer and a manufacturing method. The device includes: a substrate, where a first dielectric layer is on the substrate, a gap array is in the first dielectric layer, the gap array includes multiple gap units, and each gap unit is in a fin shape above the substrate; a nanosheet stacking portion above the gap unit, including a stack formed by multiple nanosheets, and the stack formed by the nanosheets constitutes multiple conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region on two opposite sides of the nanosheet stacking portion, where an empty spacer is between the source/drain region and the gate-all-around. An interior of the gap array and an interior of the empty spacer are filled with at least one of air, a reducing gas, or an inert gas.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The present disclosure relates to a stacked nanosheet gate-all-around device with an air spacer and a method of manufacturing a stacked nanosheet gate-all-around device with an air spacer. The stacked nanosheet gate-all-around device with the air spacer includes: a substrate with a shallow trench isolation structure on a surface of the substrate; a nanosheet stacking portion provided above the substrate, where the nanosheet stacking portion includes a stack formed by a plurality of nanosheets, and the stack formed by the nanosheets constitutes a plurality of conductive channels; a gate-all-around surrounding the nanosheet stacking portion; and a source/drain region located on two opposite sides of the nanosheet stacking portion, where an empty spacer is provided between the source/drain region and the gate-all-around, where an interior of the empty spacer is filled with at least one of air, a reducing gas, or an inert gas.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Provided are a static random access memory (SRAM) cell, a memory, and an electronic device. The SRAM cell may include a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first pass-gate transistor, and a second pass-gate transistor on a substrate. The first and second pull-up transistors are provided at a first height relative to the substrate. The first and second pull-down transistors and the first and second pass-gate transistors are provided at a second height different from the first height relative to the substrate. Each of the transistors includes a channel nanosheet extending in a first direction and source/drain portions provided above and below the channel nanosheet respectively. The first pull-down transistor is aligned with the first pull-up transistor in a vertical direction, and the second pull-down transistor is aligned with the second pull-up transistor in the vertical direction.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices

Abstract

The present application provides a spintronic neuron device, a modeling method, and a spiking neural network training method. The spintronic neuron device comprises electrodes at two ends, a transmission component which is located between the two electrodes and formed of multiple layers of films, and multiple output components deployed at different positions of the transmission component. In this way, different output components can be selected to work, to change the length of the transmission path of magnetic domain wall motion, thereby automatically adjusting the firing threshold of the spintronic neuron device. Characteristic simulation behaviors of the spintronic neuron device are modeled, and a spiking neural network for implementing identification tasks is constructed by means of the obtained neuron models having different performance and different mechanisms; the performance of the spiking neural network can be optimized by changing the number of neuron models, the threshold adjustment rate of a firing threshold, and/or synaptic weights, without the need to use peripheral circuits, thereby achieving the homeostasis of the spiking neural network and improving the stability and robustness of the spiking neural network to different inputs.

IPC Classes  ?

• G06N 3/049 - Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs

Abstract

Provided in the present disclosure are a switch structure for reducing the leakage current of a parasitic body diode of an MOS transistor, and a digital circuit. The switch structure comprises: N first-type transistors connected in series, N being a positive integer greater than or equal to 2. A substrate of the first first-type transistor is connected to a first substrate voltage, a second electrode of the ith first-type transistor is separately connected to a substrate and a first electrode of the (i+1)th first-type transistor, i∈1,2,···,N, and gates of all the first-type transistors are connected together. By connecting parasitic body diodes in series, the switch structure of the present disclosure reduces the leakage current of body diodes of MOS transistors, thereby reducing the static power consumption of circuits. In addition, when the switch structure is applied to a digital logic circuit, a voltage output by an output end can be closer to a reference voltage, thus improving logic level integrity.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Abstract

A method for fabricating a GAA nanosheet structure, comprising: forming at least two channel layers and at least one sacrificial layer alternately stacked on a substrate to form a channel stack; forming, on the substrate, a dummy gate astride the channel stack; forming a first sidewall on a surface of the dummy gate; etching the sacrificial layer to form a recess at a side surface of the channel stack; forming a second sidewall within the recess; forming a source and a drain at two sides of the channel stack; in response to a channel layer being in contact with the dummy gate, etching the dummy gate and the channel layer to expose the at least one sacrificial layer, and then etching the at least one sacrificial layer to form a space for manufacturing a surrounding gate; and forming a metallic surrounding gate in the space.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/00 - Field-effect transistors [FET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

A multi-band and multi-functional antenna integrated module and a preparation method thereof are provided. The multi-band and multi-functional antenna integrated module has an electromagnetic wave capture layer, a frequency selection circuit layer, and a signal processing circuit layer stacked vertically in sequence. The frequency selection circuit layer and the frequency selection circuit layer are interconnected through a metallized through hole. The frequency selection circuit layer has a plurality of frequency selection circuit units with different processing bands. The signal processing circuit layer has a plurality of signal processing circuit units with different functions. The plurality of frequency selection circuit units are interconnected to the plurality of signal processing circuit units in a one-to-one correspondence manner through a plurality of metallized through holes.

IPC Classes  ?

• H01Q 15/00 - Devices for reflection, refraction, diffraction or polarisation of waves radiated from an antenna, e.g. quasi-optical devices
• H01Q 21/06 - Arrays of individually energised antenna units similarly polarised and spaced apart

Abstract

Provided in the present disclosure are a spin electronic device, a storage pool device, and a storage pool neural network architecture. The spin electronic device comprises a magnetic domain device and at least two electrodes. The magnetic domain device comprises: a substrate; a spin-orbit coupling layer disposed on the top surface of the substrate; a magnetic layer disposed on the top surface of the spin-orbit coupling layer; and a barrier layer disposed on the top surface of the magnetic layer. The electrodes are inserted into the substrate from the top surface of the magnetic domain device, and the electrodes are configured to form an observation port of the spin electronic device; and the combined action of the antisymmetric interaction and dipole interaction of the spin-orbit coupling layer and the magnetic layer allows for the formation of a complex, stable, and periodically alternating magnetic domain structure. In the storage pool device, a volatile nonlinear response is obtained via application of an external magnetic field or electric pulse excitation, thus enabling a recognition function of the storage pool network.

IPC Classes  ?

• H10N 52/00 - Hall-effect devices

Abstract

The present disclosure is applicable to the technical field of artificial intelligence, and provides a method, apparatus, and system for calculating a function on the basis of integration of memory and computation, a device, and a storage medium. The method comprises: for a first power term in a first Taylor expansion in a first function to be calculated, on the basis of a coefficient value of a first coefficient corresponding to the first power term, adjusting a first conductance value of a variable resistor on a word line in a semiconductor memory device which corresponds to the first power term; on the basis of the numerical value of the first power term, inputting a pulse voltage to the word line passing through the variable resistor in the semiconductor memory device, and obtaining a first current outputted by a bit line; performing analog-to-digital conversion on the first current, and obtaining a first current value corresponding to the first current; and, on the basis of the first current value, determining a first calculation result of said first function.

IPC Classes  ?

• G11C 11/4063 - Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing

Abstract

A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; a source, a drain, and at least one nanostructure layer, which are disposed on the semiconductor substrate; and a gate stack structure surrounding each nanostructure layer, where the at least one nanostructure layer is disposed between the source and the drain, each nanostructure layer comprises a first material layer and second material layers, the second material layers are disposed at two sides of the first material layer along a thickness direction of the first material layer, each of the first material layer and the second material layers is in contact with both the source and the drain, and at least a part of the second material layers is different from the first material layer in material.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
• H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The semiconductor device includes a semiconductor substrate; and a first gate-all-around transistor and a second gate-all-around transistor formed on the semiconductor substrate and spaced apart from each other in a direction parallel to a surface of the semiconductor substrate. Each of the first gate-all-around transistor and the second gate-all-around transistor includes at least one nanostructure layer between a source region and a drain region. The nanostructure layer in the first gate-all-around transistor and the nanostructure layer in the second gate-all-around transistor are integrally formed. A thickness of each part of each nanostructure layer in the first gate-all-around transistor in a length direction of the nanostructure layer is less than a thickness of a corresponding nanostructure layer in the second gate-all-around transistor. A thickness of a gate stack in the first gate-all-around transistor is greater than a thickness of a gate stack in the second gate-all-around transistor.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The memory cell includes: a piezoelectric substrate layer, wherein two ends of the piezoelectric substrate layer are respectively provided with a first electrode and a second electrode, and a current-free drive of skyrmion is implemented by applying a voltage to the first electrode and the second electrode; a magnetic layer on a surface of the piezoelectric substrate layer, wherein the magnetic layer is used to form a heterojunction with the piezoelectric substrate layer, and is used to generate, stabilize, and serve as a basic carrier for a movement of the skyrmion; wherein the magnetic layer includes a convex body, the convex body is configured to divide the magnetic layer into a bit region and a memory region, and the bit region is provided with a magnetic tunnel junction used to perform generation and detection functions of the skyrmion.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 30/853 - Ceramic compositions
• H10N 50/01 - Manufacture or treatment
• H10N 50/85 - Materials of the active region

Abstract

A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/786 - Thin-film transistors

Abstract

A semiconductor device and a method for manufacturing the same. The method comprises: providing a substrate; forming a fin, a dummy gate, a first spacer, and a hard mask on a surface of the substrate; etching the substrate to form a groove located directly beneath the fin and running through a second spacer; forming, in the groove, a filling layer made of an insulating dielectric material, and thermal conductivity of the insulating dielectric material is higher than that of the substrate; removing the second spacer through etching; removing two opposite ends of each sacrificial layer to form cavities; filling the cavities to form inner spacers; forming a source and a drain on the substrate; forming a first dielectric layer; planarizing the first dielectric layer to expose the dummy gate; removing the dummy gate to release a channel comprising conductive nanosheets; forming a surrounding gate surrounding the conductive nanosheets.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/762 - Dielectric regions
• H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Provided in the embodiments of the present application are an image feature extraction method and apparatus based on a magnetic tunnel junction array. The method comprises: a training stage, involving: on the basis of a preset voltage-pixel mapping relationship, a voltage-current mapping relationship and a preset convolution kernel, obtaining a pixel-current mapping relationship, wherein the convolution kernel is a magnetic tunnel junction array; and a feature extraction stage, involving: mapping, into a voltage, pixels of an image to be processed; using the voltage as an input, and on the basis of the convolution kernel, outputting current coordinates corresponding to said image; and on the basis of the current coordinates and the pixel-current mapping relationship, determining pixels, which have been subjected to convolution, of said image. The technical solution provided in the present application is used for solving the problems in the prior art of the writing rate being low, the energy consumption being high, the reliability being poor, etc.

IPC Classes  ?

• G06V 10/94 - Hardware or software architectures specially adapted for image or video understanding

Abstract

Provided are a semiconductor device with decreased source and drain resistance and a manufacturing method. The semiconductor device includes a substrate and multiple three-dimensional semiconductor device arrays. The three-dimensional semiconductor device arrays are on the substrate, and the three-dimensional semiconductor device arrays are separated by isolation grooves. Each three-dimensional semiconductor device array includes a plurality of device layers in a vertical direction, each device layer includes a stack of a source/drain layer, a channel layer and a source/drain layer, and an end face of the source/drain layer adjacent to the isolation groove is metallized. The three-dimensional semiconductor device array further includes a plurality of gate stacks arranged in an array, the gate stack penetrates each device layer in the vertical direction and includes a gate material and a gate dielectric layer, and a device unit is defined at an intersection of the gate stack and the device layer.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/762 - Dielectric regions
• H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group

Abstract

The present application provides a three-dimensional stacked dynamic random access memory and a manufacturing method therefor. The three-dimensional stacked dynamic random access memory comprises: a substrate, a source, a drain, a storage structure, a source-end common electrode, drain-end electrodes, and gates. The storage structure comprises a stack formed by a plurality of nanosheets; the nanosheets extend to the source and the drain; the source-end common electrode is in contact with each nanosheet; the source-end common electrode is connected to the ground potential; part of the nanosheets that extends to the drain forms a stepped structure; each drain-end electrode among the plurality of drain-end electrodes penetrates through part of the drain; each drain-end electrode is in contact with a nanosheet in the stepped structure; the drain-end electrodes are connected to bit lines; the gates surround the nanosheets; and the gates are connected to word lines. Therefore, by vertically stacking storage units, configuring the gates to surround the storage units, and configuring the part of the storage units connected to the drain to form the stepped structure, a three-dimensional stacked 1T storage unit array structure can be formed, thereby greatly improving the integration density of the dynamic random access memory and achieving high-density data storage.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

The computing-in-memory circuit includes: an SRAM memory cell array including at least one memory cell connected between a first bit line and a second bit line, the memory cell includes a first inverter and a second inverter cross-coupled with each other, and the first inverter and the second inverter have an asymmetric configuration with respect to each other; a control circuit configured to: receive a first input signal, a second input signal and an operation mode control signal, process the first input signal and the second input signal according to operation mode control signal, so as to obtain a processed first input signal and a processed second input signal, and apply the processed first input signal and the processed second input signal to the first bit line and the second bit line, respectively; and a readout circuit configured to read out data stored in memory cell from the memory cell.

IPC Classes  ?

• G11C 11/419 - Read-write [R-W] circuits
• G11C 11/418 - Address circuits
• H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Abstract

The present disclosure provides a memory with a three-dimensional vertical structure and a manufacturing method. The memory includes: a semiconductor substrate, a first isolation layer, a first transistor and a second transistor. The first transistor includes a first source layer, a second isolation layer, a first drain layer, a third isolation layer, and a first through hole penetrating to the first source layer. A first active layer, a first gate dielectric layer and a first gate layer are on an inner sidewall of the first through hole. The second transistor includes a fourth isolation layer, a second source layer, a fifth isolation layer, and a second through hole penetrating to the first gate layer. A second active layer, a second gate dielectric layer and a second gate layer are on an inner sidewall of the second through hole. The second through hole is surrounded by the first through hole.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices

Abstract

A nanowire/nanosheet device with a crystal spacer, a method of manufacturing the nanowire/nanosheet device with the crystal spacer, and an electronic apparatus including the nanowire/nanosheet device are provided. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; source/drain layers located at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a spacer provided on a sidewall of the gate stack, wherein the spacer has a crystal structure substantially identical to a crystal structure of the nanowire/nanosheet in at least a part of a region of the spacer adjacent to the nanowire/nanosheet.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/762 - Dielectric regions
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A three-dimensional integrated circuit and a manufacturing method therefor is used for improving the performance of the integrated circuit when the integrated circuit includes a power gating circuit. The three-dimensional integrated circuit includes a substrate, and a front-section circuit, a rear-section metal interconnection layer, and a rear-section power gating circuit that are formed on the substrate; the rear-section metal interconnection layer is formed on the front-section circuit; the rear-section power gating circuit is located in the rear-section metal interconnection layer; and the front-section circuit is electrically connected to a power supply or a ground wire by means of the rear-section metal interconnection layer and the rear-section power gating circuit.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device includes: a substrate; an insulating layer provided with a plurality of trenches extending in a first direction; a first electrode layer and a second electrode layer, where a spacing region is provided between the first electrode layer and the second electrode layer; a semiconductor layer covering bottom portions and sidewalls of all channel trenches, where the channel trenches are at least a part of trench bodies of the trenches located in the spacing region; a gate dielectric layer covering a surface of the semiconductor layer in the channel trenches on a side away from the bottom portions and the sidewalls of the channel trenches; a gate layer, where at least a part of the channel trenches are fully filled with the gate layer.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/49 - Metal-insulator semiconductor electrodes

Abstract

The present disclosure provides a semiconductor device based on a dielectric material containing a metal interstitial impurity, including: a substrate, a dielectric material layer, and a functional layer. A material for preparing the dielectric material layer is a compound containing the metal interstitial impurity. The dielectric material layer and/or the functional layer is configured to subject to at least one of electricity, heat, light or magnetism, such that the dielectric material layer reaches a crystallization temperature to transit from a first state to a second state.

IPC Classes  ?

• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 29/51 - Insulating materials associated therewith
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Abstract

A semiconductor device and a method for manufacturing the same. The method comprise: forming a first field-effect transistor (FET) disposed on a substrate and a first isolation layer disposed on the first FET; forming a first through hole in the first isolation layer, where a metal layer is deposited in the first through hole and is electrically connected to the first FET; forming a second isolation layer, which is disposed on the first isolation layer and the metal layer; and forming a second FET which is disposed on the second isolation layer, where a second through hole is disposed in the second FET and the second isolation layer, a metal material filled in the second through hole serves as a first contact plug, and the first contact plug is electrically connected to the metal layer. The metal layer serves as a power distribution network for both FETs.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The present disclosure provides a spintronic device and a recurrent neural network. The spintronic device comprises a substrate; a spin-orbit coupling layer arranged on a top surface of the substrate; a magnetic layer arranged on a top surface of the spin-orbit coupling layer, wherein a stable periodically alternating magnetic domain structure can be formed under the combined action of the antisymmetric exchange effect and the dipole interaction of the spin-orbit coupling layer and the magnetic layer; a barrier layer arranged on a top surface of the magnetic free layer; and at least two electrodes respectively arranged on two sides of the top surface of the substrate, separately connected to the spin-orbit coupling layer, the magnetic layer and the barrier layer and used for application of an input electric signal, wherein when the input electric signal is applied to the electrodes, the input electric signal flows into the spintronic device, so that the spintronic device generates joule heat with the input electric signal, and the resistance value of the spintronic device has dynamic fluctuation characteristics.

IPC Classes  ?

• H10N 50/20 - Spin-polarised current-controlled devices
• G06N 3/044 - Recurrent networks, e.g. Hopfield networks

Abstract

An electron beam exposure method and apparatus. The method comprises: acquiring exposure patterns, and according to the sizes of the exposure patterns, determining the sizes of a plurality of cells comprised in a reference grid, and arranging the exposure patterns at center positions of the cells, wherein the sizes of the cells are the sizes of write fields of electron beam exposure; and providing a reference rectangle, wherein the relative position between the reference rectangle and the reference grid is fixed, such that the positions of a plurality of write fields during electron beam exposure can be determined, so as to arrange the exposure patterns at center positions of the write fields of electron beam exposure, and therefore all the exposure patterns can be exposed at the center positions of the write fields, thereby achieving the optimal exposure effect, reducing the probability that the sizes of patterns formed by means of exposure are inaccurate due to deviations of exposure positions of the exposure, and improving the size accuracy of the exposure patterns.

IPC Classes  ?

• G03F 7/20 - ExposureApparatus therefor

Abstract

A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

IPC Classes  ?

• H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/161 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group
• H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , ,  or
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

Embodiments of the present application provide a training method and apparatus for plasma photolithography imaging. The method comprises: acquiring a training imaging structure of plasma photolithography imaging, the training imaging structure comprising a plurality of training mask patterns which are two-dimensionally periodically changed; constructing a simulation model on the basis of the training imaging structure, and performing simulation on the basis of the simulation model to obtain training plasma photolithography images corresponding to the training mask patterns; and training a rapid imaging model on the basis of the training mask patterns and the training plasma photolithography images to obtain a rapid imaging model for the two-dimensionally periodically changed training mask patterns. Therefore, by establishing a rapid imaging model for two-dimensionally periodically changed mask patterns, a training plasma photolithography image of each mask pattern can be directly obtained by using the rapid imaging model, achieving rapid imaging by means of the rapid imaging model, and satisfying the subsequent research requirements on the plasma photolithography.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G03F 7/20 - ExposureApparatus therefor
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof

Abstract

The memory cell includes: an array of channel layers including N channel layers vertically provided on a substrate, a tunneling layer and a memory layer being sequentially provided on an outer side of the channel layers; N thermal conductive cores provided in the N channel layers respectively and penetrating the substrate; and an array of thermocouples including a thermocouple word line layer grown on the substrate and N thermocouple layers on the thermocouple word line layer, the thermocouple layers being connected one-to-one with the thermal conductive cores. A first potential difference is applied between the thermocouple word line layer and the thermocouple layer, and the thermal conductive core connected with the thermocouple layer is heated, so that the channel layer and the memory layer corresponding to the thermal conductive core are maintained at first and second preset temperatures respectively under a thermal insulation effect of the tunneling layer.

IPC Classes  ?

• H01L 23/373 - Cooling facilitated by selection of materials for the device
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits
• H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
• H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Abstract

The present invention relates to the technical field of semiconductors, and in particular to a semiconductor device and a manufacturing method therefor. The semiconductor device comprises a substrate, nanosheet channels, a metal gate, a source-drain region, and an insulating dielectric layer, wherein the nanosheet channels are located above the substrate, the metal gate surrounds the nanosheet channels, the source-drain region is connected to the nanosheet channels, and the insulating dielectric layer is located between the substrate and the source-drain region and between the substrate and the nanosheet channels. According to the present invention, etching of silicon in the source-drain region is added to form a trench where a source and a drain are communicated, and then an insulating dielectric material fills the trench to form complete isolation between the bottoms of the channels and the bottoms of the source and the drain, so that a substrate parasitic channel and channel leakage between the source and the drain are fundamentally eliminated.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

The present application relates to the field of spin torque electronics. Disclosed are a control method for a spin torque nano-oscillator, and a spin torque nano-oscillator. The control method for a spin torque nano-oscillator is applied to a spin torque nano-oscillator which comprises a bottom electrode, and a ferromagnetic reference layer, a ferromagnetic free layer and a top electrode which are sequentially arranged on the bottom electrode. The control method comprises: during the process of performing reservoir computing by means of a spin torque nano-oscillator and on the basis of a strong nonlinear relationship between an input current intensity and an oscillation frequency corresponding to a self-oscillation state, regulating and controlling process parameters of related materials or voltage-controlled magnetic anisotropy, so as to regulate and control an anisotropy inclination direction of a ferromagnetic reference layer; and regulating and controlling the anisotropy inclination direction and/or regulating and controlling the input current intensity, so as to regulate and control an oscillation frequency and/or a line width corresponding to the spin torque nano-oscillator.

IPC Classes  ?

• H10N 50/01 - Manufacture or treatment
• H10N 50/10 - Magnetoresistive devices
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/85 - Materials of the active region

Abstract

Provided are a NOR-type memory device, a manufacturing method, and an electronic device. The device includes: a plurality of gate stacks extending vertically on a substrate, wherein the gate stack includes a first gate conductor layer and a first filling layer; at least one device layer surrounding a periphery of the gate stack and extending along a sidewall of the gate stack; and a single-crystal vertical channel on a side of the device layer close to the gate stack and in contact with the first filling layer. At least one side surface of the gate stack in the vertical direction is a (100) or (110) crystal plane; and/or the body region includes a second filling layer or the body region includes a second gate conductor layer and a third filling layer, wherein at least one of first and third filling layers is a storage functional layer.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

Abstract

The present application discloses a battery cover plate assembly and a lithium-ion battery. The battery cover plate assembly comprises a cover plate body and a sealing member. The cover plate body has a first surface and a second surface, wherein a gas discharge hole is formed in the first surface. The sealing member partially extends into the gas discharge hole and is connected to the side wall of the gas discharge hole. A crimping portion is provided at the edge of the end of the sealing member facing away from the second surface in protruding fashion. The crimping portion extends in a direction away from the axis of the gas discharge hole. The orthographic projection of the crimping portion on the first surface is at least partially located outside the gas discharge hole.

IPC Classes  ?

• H10N 50/85 - Materials of the active region
• H10N 50/20 - Spin-polarised current-controlled devices

Abstract

Provided are a three-dimensional stack field-effect transistor (3DS FET) and a method of manufacturing the same. According to embodiments, the 3DS FET includes: a lower active region arranged on a substrate, an upper active region above the lower active region and a gate stack. The lower active region includes: a fin extending in a first direction on the substrate, and lower source/drain portions at two opposite ends of the fin in the first direction, respectively. The upper active region includes: one or more nanosheets, a lowest nanosheet is spaced apart from the fin in a vertical direction relative to the substrate, and upper source/drain portions at two opposite ends of the one or more nanosheets in the first direction, respectively. The gate stack extends in a second direction intersecting with the first direction so as to intersect with the fin and the one or more nanosheets.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/786 - Thin-film transistors

Abstract

A gate-all-around transistor and a method for manufacturing the same. The gate-all-around transistor comprises: a semiconductor substrate; an active structure disposed on the semiconductor substrate, where the active structure comprises a source, a drain, and a channel between the source and the drain; a doped epitaxial structure, where a portion of the semiconductor substrate beneath the channel is recessed to form a first groove, the first groove is fully filled with the doped epitaxial structure, and primary carriers of the doped epitaxial structure are opposite in polarity to primary carriers of the source and the drain; and a gate stack structure surrounding the channel, where a portion of the gate stack structure beneath the channel is disposed between the doped epitaxial structure and the channel.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A semiconductor device having a double-gate structure and a method of manufacturing the same, and an electronic apparatus including the semiconductor device are provided. The semiconductor device may include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion relative to the substrate; and a first gate stack and a second gate stack on opposite sides of the channel portion in a first direction lateral to the substrate. A distance between an upper edge and/or a lower edge of an end of the first gate stack facing the channel portion in a vertical direction and a corresponding source/drain portion may be less than a distance between a corresponding upper edge and/or a corresponding lower edge of an end of the second gate stack facing the channel portion in the vertical direction and a corresponding source/drain portion.

IPC Classes  ?

• H01L 29/786 - Thin-film transistors
• H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
• H01L 21/784 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, each consisting of a single circuit element the substrate being a semiconductor body
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A method of manufacturing a semiconductor device is provided. The method includes: forming a channel defining layer and a source/drain layer sequentially on a substrate of a crystalline material; patterning the channel defining layer and the source/drain layer as a ridge protruding relative to the substrate; forming a channel layer on a sidewall of the ridge by deposition; and performing a crystallization process to recrystallize the channel layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Abstract

A memory device, including: device layers vertically stacked on a substrate, each device layer including an array of active regions of selection transistors, the array including rows in a first direction and columns in a second direction, the active region including a lower source/drain region, a channel portion, and an upper source/drain region; bit lines arranged in the second direction and extending in the first direction along rows; word line layers vertically stacked and corresponding to the device layers, and each including word lines arranged in the first direction and extending in the second direction to at least partially surround a channel portion in a column of a device layer; sub bit lines extending vertically from each bit line and each electrically connected to a lower source/drain region in a row in each device layer above the bit line; and a memory element electrically connected to the upper source/drain region.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/10 - Magnetoresistive devices

Abstract

The present disclosure relates to the technical field of microelectronics, and in particular relates to a ferroelectric gate stack, a ferroelectric field effect transistor, and a preparation method therefor, which are used for solving the problem of accumulation flipping that easily occurs in existing ferroelectric field effect transistors. The ferroelectric gate stack comprises, from bottom to top, a gate oxide layer, a dielectric thin layer, and another gate dielectric layer which are sequentially stacked; a ferroelectric layer is further provided between the dielectric thin layer and the gate oxide layer, and a resistive switching layer is further provided between the dielectric thin layer and the other gate dielectric layer; or a resistive switching layer is further provided between the dielectric thin layer and the gate oxide layer, and a ferroelectric layer is further provided between the dielectric thin layer and the other gate dielectric layer. According to the present disclosure, the resistive switching layer is added into the ferroelectric gate stack, so that when the voltage on the ferroelectric gate stack is smaller than a flipping voltage, accumulation flipping does not easily occur due to surrounding crosstalk, and after reaching a desired coercive voltage, start-up is normal, thereby weakening the accumulation flipping effect.

IPC Classes  ?

• H01L 29/51 - Insulating materials associated therewith
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

Disclosed are a vertical semiconductor device having continuous gate lengths and a manufacturing method therefor, and an electronic device comprising the semiconductor device. According to embodiments, the semiconductor device may comprise: a semiconductor base on a substrate; a first vertical channel portion and a second vertical channel portion which are vertical to the substrate on the semiconductor base, wherein the first vertical channel portion and the second vertical channel portion protrude from the semiconductor base, are spaced apart from each other in a first direction and are self-aligned with each other, and the semiconductor base extends continuously between the first vertical channel portion and the second vertical channel portion; a first source/drain portion and a second source/drain portion which are respectively provided on the first vertical channel portion and the second vertical channel portion; and a gate stack at least partially provided on the first vertical channel portion, the semiconductor base and the second vertical channel portion to define continuous channels between the first source/drain portion and the second source/drain portion.

IPC Classes  ?

• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 29/41 - Electrodes characterised by their shape, relative sizes or dispositions
• H01L 21/336 - Field-effect transistors with an insulated gate

Abstract

The folded channel gallium nitride based field-effect transistor includes: a base layer; a multi-heterojunction layer, including a channel layer and a barrier layer alternatingly stacked from bottom to top on a gallium nitride semi-insulating layer; a gallium nitride control layer on the multi-heterojunction layer and extending from one side of the channel region to at least a part of the groove; a current collapse suppression structure formed on the multi-heterojunction layer on another side of the channel region; a source electrode and a drain electrode that are respectively in contact with two sides of the multi-heterojunction layer on the gallium nitride semi-insulating layer; a gate electrode formed on the multi-heterojunction layer between the source electrode and the gallium nitride control layer; and a connecting structure passing over the gate electrode to electrically connect to the source electrode and the gallium nitride control layer.

IPC Classes  ?

• H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

A nanowire/nanosheet device and a method of manufacturing the same, and an electronic apparatus including the nanowire/nanosheet device. The nanowire/nanosheet device includes: a substrate; a nanowire/nanosheet spaced apart from a surface of the substrate and extending in a first direction; a source/drain layer at opposite ends of the nanowire/nanosheet in the first direction and adjoining the nanowire/nanosheet; a gate stack extending in a second direction intersecting with the first direction to surround the nanowire/nanosheet; and a first spacer on a sidewall of the gate stack, wherein the first spacer includes a continuously extending material layer which has a first part along a surface of the nanowire/nanosheet, a second part along a sidewall of the source/drain layer facing the gate stack, and a third part along a sidewall of the gate stack facing the source/drain layer, and the second part and the third part have a seam or an interface therebetween.

IPC Classes  ?

• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method for fast precise optical calibration on a photolithography system, including: determining a fitting relationship for a spot width corresponding to a point light source based on distribution of field strength generated by the point light source at an exit plane of a focusing element; determining, based on the fitting relationship, a first correspondence between the spot width and a parameter for exposing a photoresist, where the spot width in the first correspondence is for optical microscopy; determining a first spot-width dataset for the point light source based on an optical microscopic image of a spot-mapping pattern on a surface of the photoresist; determining, based on the first spot-width dataset, a second correspondence between the spot width and the parameter; and determining the first correspondence as a means for determining the parameter, when the first correspondence and the second correspondence meet a preset condition.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

An interconnection structure and a method of manufacturing the same, and an electronic device including the interconnection structure are provided. According to an embodiment, the interconnection structure includes: a first interconnection line at a first level, including at least a first portion extending along a first direction; a second interconnection line at a second level higher than the first level, including at least a second portion extending along a second direction crossing the first direction; a via plug disposed between the first portion of the first interconnection line and the second portion of the second interconnection line, and configured to electrically connect the first interconnection line and the second interconnection line, wherein the via plug includes a first pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the first portion and a second pair of sidewalls respectively extending substantially parallel to corresponding sidewalls of the second portion.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials

Abstract

The present invention relates to a hybrid integrated SRAM storage unit structure and a manufacturing method therefor. In the present invention, some regions for which channel release is not performed, and remaining regions for which channel release is performed are selected, so as to form, at different positions, a FinFET structure with a larger driving current and a GAAFET with a smaller driving current, respectively, such that hybrid integration of the GAAFET and FinFET is realized, and the area of a circuit does not increase during the designing of a transistor proportion, thereby facilitating a further improvement in an integration density.

IPC Classes  ?

• H10B 12/00 - Dynamic random access memory [DRAM] devices
• B82Y 10/00 - Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• B82Y 40/00 - Manufacture or treatment of nanostructures
• H01L 21/8234 - MIS technology
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Abstract

The present disclosure provides an SOT-MRAM memory cell, including: a bottom electrode; a magnetic tunnel junction layer located on the bottom electrode; an orbital Hall effect layer located on the magnetic tunnel junction layer; a first transistor, a drain of which is connected to the orbital Hall effect layer; and a second transistor, a drain of which is connected to the bottom electrode. The present disclosure further provides an SOT-MRAM memory, an operation method, and an SOT-MRAM memory array.

IPC Classes  ?

• H10N 50/10 - Magnetoresistive devices
• G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
• H10N 50/20 - Spin-polarised current-controlled devices
• H10N 50/85 - Materials of the active region
• H10N 52/00 - Hall-effect devices

Abstract

A magnetoresistive memory unit, a preparation method, an array circuit, and a binary neural network chip. The magnetoresistive memory unit comprises a heavy metal layer configured to input a write current; a first magnetic tunnel junction, arranged on one side of a bottom surface of the heavy metal layer, a first preset included angle being formed between the easy axis of the first magnetic tunnel junction and an input direction of the write current; and a second magnetic tunnel junction, arranged on the other side of the bottom surface of the heavy metal layer, a second preset included angle being formed between the easy axis of the second magnetic tunnel junction and the input direction of the write current. The first magnetic tunnel junction and the second magnetic tunnel junction are configured to input a read current.

IPC Classes  ?

• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 11/15 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
• H10N 50/10 - Magnetoresistive devices
• G11C 11/409 - Read-write [R-W] circuits

Abstract

Provided in the present disclosure are a spin electronic device, a circuit unit, a computing network, an operator, and a neural network. A random spin electronic device comprises: a heater, which heater is configured to flow a write control pulse signal; an isolation layer, which is formed on the top surface of the heater; an antiferromagnetic layer, which is formed on the top surface of the isolation layer; a ferromagnetic layer, which is formed on the top surface of the antiferromagnetic layer, wherein the antiferromagnetic layer is configured to fix the magnetic moment of the ferromagnetic layer, such that the ferromagnetic layer does not generate a magnetic domain wall; an RKKY coupling layer, which is formed on the top surface of the ferromagnetic layer; and a magnetic tunnel junction, which is formed on one side of the top surface of the RKKY coupling layer, wherein when a write pulse signal is input, a magnetic domain wall in a magnetic domain wall free layer of the magnetic tunnel junction moves.

IPC Classes  ?

• H10N 50/20 - Spin-polarised current-controlled devices

Abstract

The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

IPC Classes  ?

• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device

Abstract

t1122trainedtrained. According to the failure model construction method in the present invention, a prediction period is reasonably set, thereby greatly improving the accuracy of model prediction, and providing a more accurate basis for timely and effective intervention of failed storage units.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model

Abstract

pt[i]pt[i]pt[i] into a corresponding trained failure prediction model, so as to obtain a true/false failure binary classification prediction result of the storage unit within the next erasure cycle t+1; and when the prediction result indicates false failure, performing secondary determination, so as to obtain a prediction result indicating whether the storage unit is a false failure storage unit that actually needs to be repaired.

IPC Classes  ?

• G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
• G06N 3/08 - Learning methods
• G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
• G06N 3/0464 - Convolutional networks [CNN, ConvNet]

Abstract

Provided is a signal driving system with a constant slew. The signal driving system with the constant slew includes: a step voltage generation unit configured to provide multiplex arithmetic gradient voltage signals; a multiplexer, wherein an input end of the multiplexer is connected to the step voltage generation unit to receive the multiplex arithmetic gradient voltage signals, and another input end of the multiplexer is connected to a control signal generation unit, and the multiplexer is configured to selectively output the multiplex arithmetic gradient voltage signals under a control of a control signal generated by the control signal generation unit; a voltage following unit connected to the multiplexer, wherein the voltage following unit is configured to serve as an isolation and improve a driving ability; and an output following unit connected to the voltage following unit, wherein the output following unit is configured to drive a subsequently-connected load unit.

IPC Classes  ?

• H03K 19/0175 - Coupling arrangementsInterface arrangements

Abstract

A semiconductor device having a ferroelectric/negative capacitor and a method of manufacturing the same, and an electronic device including the semiconductor device are provided. According to the embodiments, the semiconductor device may include: a gate electrode and a source/drain electrode formed on a substrate; a positive capacitor formed on the substrate, a first terminal of the positive capacitor being electrically connected to the gate electrode; a ferroelectric or negative capacitor formed on the substrate, a first terminal of the ferroelectric or negative capacitor being electrically connected to the gate electrode, wherein a second terminal of one of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to a gate voltage application terminal, and a second terminal of the other of the positive capacitor and the ferroelectric or negative capacitor is electrically connected to the source/drain electrode.

IPC Classes  ?

• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region

Abstract

Disclosed are a memory device, a method of manufacturing the memory device, and an electronic device. The memory device may include: a plurality of first device layers, each including first and second source/drain regions and a channel region; a plurality of second device layers stacked on the first device layers, each including third and fourth source/drain regions and a channel region; and a gate stack extending vertically to pass through the first and second device layers. The gate stack includes a gate conductor layer and a memory functional layer disposed between the gate conductor layer and each device layer, and a memory cell is defined at an intersection of the gate stack and each device layer. The gate stack has a surface in a bended shape at a position where the plurality of first device layers are adjacent to the plurality of second device layers.

IPC Classes  ?

• H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
• H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Disclosed are a memory device, a manufacturing method therefor, and an electronic device comprising a memory device. According to the embodiments, the memory device may comprises: a plurality of first device layers vertically stacked on a substrate, each first device layer comprising a first source/drain region and a second source/drain region which are respectively arranged at a lower vertical height and an upper vertical height, and a channel region therebetween; a plurality of second device layers stacked on the first device layers, each second device layer comprising a third source/drain region and a fourth source/drain region which are respectively arranged at a lower vertical height and an upper vertical height, and a channel region therebetween; and a gate stack extending vertically to pass through the first device layers and the second device layers. The gate stack comprises gate conductor layers and memory function layers arranged between the gate conductor layers and the device layers, memory cells being defined at the intersections of the gate stack and the device layers. Where the first device layers are adjacent to the second device layers, the gate stack has surfaces in curved shapes.

IPC Classes  ?

• H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
• H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Disclosed are a semiconductor apparatus, a manufacturing method, and an electronic device. The semiconductor apparatus includes first and second devices vertically stacked. Each of the first and second devices includes a first source/drain layer, a channel layer and a second source/drain layer vertically stacked, and a gate stack surrounding a periphery of the channel layer. The first device protrudes in a first direction relative to the second device to form a first step. A second step is defined by the second device. On a side in a second direction intersecting with the first direction, the first source/drain layer of each device protrudes in the second direction relative to the second source/drain layer and gate stack, to form a sub-step. Each sub-step is on a corresponding step. On another side in the second direction, the gate stack of each device protrudes in the second direction relative to the second source/drain layer.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A method for manufacturing a reservoir computing apparatus, related to artificial intelligence. The method comprises: step a), providing a bottom electrode layer, a dielectric layer, a resistive switching layer, and a top electrode layer based on the above-listed sequence on a substrate to obtain a to-be-annealed reservoir computing apparatus; and step b), annealing the to-be-annealed reservoir computing apparatus to obtain the reservoir computing apparatus, where a temperature of the annealing ranges from 300° C. to 700° C., and duration of the annealing duration ranges from 30s to 100s. The manufactured reservoir computing apparatus is subject to rapid annealing, which redistributes defects, forms a more stable film, and introduces a ferroelectric O-phase into the film. The rapid annealing reduces power consumption and improves computing accuracy effectively.

IPC Classes  ?

• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
• H10N 70/20 - Multistable switching devices, e.g. memristors

Abstract

Provided are a reconfigurable neuron device based on ion gate regulation and a method of preparing the same. The device includes: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer and a top electrode layer which are sequentially stacked from bottom to top. A left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions are provided on two opposite edges of a bottom end of the synthetic antiferromagnetic layer, and a magnetic tunnel junction configured to output a spike signal is further provided in a middle portion of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer and the top electrode layer constitute an ion gate, the ionic liquid layer includes a positive ion and a negative ion.

IPC Classes  ?

• G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means

Abstract

A storage device is provided, including: a substrate; word lines extending in a first direction; bit lines extending in a second direction perpendicular to the first direction; and a storage unit including a plurality of storage units, each of which is electrically connected to a word line and a bit line. Each storage unit includes: an active region extending in a third direction inclined with the first direction; a vertical stack of a first source/drain layer, a channel layer and a second source/drain layer; and gate stacks between the first source/drain layer and the second source/drain layer, and on opposite sides of the channel layer in a fourth direction orthogonal to the third direction, to sandwich the channel layer. The word line corresponding to each storage unit extends across the storage unit in the first direction to be electrically connected to the gate stacks on opposite sides.

IPC Classes  ?

• G11C 11/408 - Address circuits
• G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result

Abstract

The present disclosure provides a memristor, including a transistor and a resistive random access memory, where a drain electrode of the transistor is connected to a bottom electrode of the resistive random access memory; and the resistive random access memory includes: the bottom electrode, a resistive random access material layer, a current compliance layer and a top electrode from bottom to top, where the current compliance layer is configured to stabilize a fluctuation of a low resistance by reducing a surge current and optimizing a heat distribution, so as to improve a calculation accuracy of a Hamming distance.

IPC Classes  ?

• H10N 70/20 - Multistable switching devices, e.g. memristors
• G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
• H10B 63/00 - Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
• H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Abstract

A gate-all-around transistor is provided, including: a semiconductor substrate, a nanostructure, a gate stack structure and a gate length defining structure. In a length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the two. Materials of the source region and drain region include a first metal semiconductor compound. The gate stack structure surrounds the channel region. In a length direction of the gate stack structure, a sidewall of the gate stack structure is recessed relative to a sidewall of the channel region to form a recess, and the gate length defining structure is filled in the recess. The gate length defining structure is made of a second metal semiconductor compound, and a semiconductor material for making the second metal semiconductor compound is different from that for making the first metal semiconductor compound.

IPC Classes  ?

• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/40 - Electrodes
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

A center bit line framework of a three-dimensional memory, a three-dimensional memory, and a manufacturing method therefor, relating to the technical field of three-dimensional memories. The center bit line framework comprises: a first common source (ACS1) and a second common source (ACS2) which are arranged opposite to each other; multiple layers of word lines (WL) stacked between the first common source (ACS1) and the second common source (ACS2) in a first direction; a plurality of channel holes running through the multiple layers of word lines and connected to the first common source (ACS1) and the second common source (ACS2), each channel hole forming a byte string (string); and a plurality of center bit lines (CBL) which are arranged in the middles of the channel holes and are arranged at intervals in a second direction crossing the first direction, wherein the multiple layers of word lines (WL) and the plurality of byte strings (string) form a whole block (BLOCK), and the plurality of center bit lines (CBL) divide the whole block (BLOCK) into a first sub-block located at the upper part and a second sub-block located at the lower part, so as to respectively drive the byte strings (string) in the first sub-block and the second sub-block, thereby not only reducing the block capacity, but also reducing the channel length (i.e., the channel resistance).

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure