An aligner station includes an aligner stage configured to support a carrier for a process kit ring. The aligner station further includes a lift mechanism configured to lift the process kit ring from the carrier. The aligner station, using the aligner stage and the lift mechanism, is configured to independently align the process kit ring and the carrier to a target orientation.
A method includes receiving a first group of parameters corresponding to a substrate manufacturing process, generating, using a statistical model, a first health index of a flow controller, receiving a second group of parameters corresponding to a flow controller used during the substrate manufacturing process, generating, using a physical model, a second health index of the flow controller, and based on at least one of the first and second health indices, perform a corrective action with respect to the flow controller.
The present disclosure relates to plate and absorptive mass arrangements for localized thermal adjustability, and related methods and processing chambers. In one or more embodiments, a processing chamber includes a chamber body at least partially defining an internal volume, a substrate support disposed in the internal volume, a plate apparatus disposed in the internal volume and at least partially defining a processing volume between the plate apparatus and the substrate support. The plate apparatus includes one or more flow openings formed in one or more plate walls. The processing chamber includes one or more absorptive masses disposed in the one or more flow openings.
Methods and systems for organic defect source identification using artificial intelligence (AI) are provided. One or more images depicting a surface of a substrate processed using one or more manufacturing equipment is provided as input to an artificial intelligence (AI) model. Output(s) of the AI model is obtained, where the output(s) indicate defect characterization data associated with a defect detected on the surface of the substrate depicted by the one or more images. A determination is made of whether a level of confidence of at least one defect type and associated defect source from the defect characterization data satisfies one or more confidence criteria. Upon a determination that at least one defect type and associated defect source satisfy the one or more confidence criteria, the at least one defect type and associated defect source are provided to a client device for presentation to one or more users.
A method of forming a DTD interconnect includes measuring a shift in a multi-die interconnect bridge of a partial DTD interconnect. A plurality of via channels and bridge via channels are formed in the build-up layers. A plurality of vias and a plurality of bridge vias are formed in the via channels and the bridge via channels. Interconnect layers are disposed over the plurality of vias and an elongated bridge interconnect is disposed over the plurality of bridge via channels. A plurality of package micro-bump pads and a plurality of bridge micro-bump pads are disposed over the plurality of vias and the bridge vias, respectively. The plurality of vias are aligned with the package micro-bump pads and the plurality of bridge vias are aligned with the plurality of bridge micro-bump pads. One or more dies are bonded to the DTD interconnect.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
6.
SEMICONDUCTOR WAFER PROCESSING WITH TEMPERATURE CONTROL AND BIAS POWERED PROCESS RING FOR EXTREME EDGE CONTROL
Examples described herein generally related to a process kit for a semiconductor processing chamber. In one example, the process kit includes an edge ring having an inner diameter, a bottom surface and a top surface. The edge ring is configured to circumscribe a substrate in a semiconductor processing chamber. The process kit includes a insert ring positioned beneath the edge ring. The insert ring has an upper surface configured to contact the bottom surface of the edge ring. The insert ring has a body having a lower surface, an electrode disposed in the body, and a pin extending into the body through the lower surface coupled to the electrode. A conductive pin of the pin protrudes from the lower surface and is configured to couple to a power supply for the electrode.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
7.
METHODS AND SYSTEMS OF ENHANCING EDGE PLACEMENT ERROR INSPECTION
This disclosed subject matter includes a computer-implemented method and computer system for enhancing and/or optimizing metrology recipes for Edge Placement Error (EPE) measurements, including roughness, Critical Dimensions (CD), and Critical Dimension Uniformity (CDU). The approach uses skewed CAD versions and a CAD-to-SEM ML model to generate synthetic SEM images for recipe validation. An iterative process refines recipes by adjusting recipe parameters based on discrepancies between measured values and true values.
G06F 30/12 - CAO géométrique caractérisée par des moyens d’entrée spécialement adaptés à la CAO, p. ex. interfaces utilisateur graphiques [UIG] spécialement adaptées à la CAO
8.
SUBSTRATE STRESS MANAGEMENT USING HIGH TEMPERATURE IMPLANTATION
A method for stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate and performing a high-temperature implant procedure in an ion implanter to implant a dose of ions into the stress compensation layer. The high temperature implant procedure may include heating the substrate to an implant temperature, the implant temperature being between 300 ºC and 750 ºC, and exposing the substrate to an ion beam while the substrate is held at the implant temperature, wherein the implant procedure alters an out-of-plane distortion of the substrate.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
9.
SEMICONDUCTOR WAFER PROCESSING WITH TEMPERATURE CONTROL AND BIAS POWERED PROCESS RING FOR EXTREME EDGE CONTROL
Examples described herein generally related to a process kit for a semiconductor processing chamber. In one example, the process kit includes an edge ring having an inner diameter, a bottom surface and a top surface. The edge ring is configured to circumscribe a substrate in a semiconductor processing chamber. The process kit includes a insert ring positioned beneath the edge ring. The insert ring has an upper surface configured to contact the bottom surface of the edge ring. The insert ring has a body having a lower surface, an electrode disposed in the body, and a pin extending into the body through the lower surface coupled to the electrode. A conductive pin of the pin protrudes from the lower surface and is configured to couple to a power supply for the electrode.
The present disclosure relates to systems, apparatus, and methods for multi-wavelength monitoring for semiconductor manufacturing. In one or more embodiments, a system for processing substrates includes a chamber body at least partially defining an internal volume, one or more heat sources configured to heat the internal volume, a substrate support disposed in the internal volume, and a sensor assembly operable to measure energy of a plurality of wavelengths in the internal volume. The sensor assembly includes one or more optical sensors, a movable tray coupled to a motor, and a plurality of filters supported by the movable tray, the motor operable to move the movable tray to move the plurality of filters relative to the one or more optical sensors to respectively align the plurality of filters with at least one of the one or more optical sensors.
Embodiments of methods of performing an Al metallization process on a substrate are provided herein. In some embodiments, a method of performing an Al metallization on a substrate includes: depositing a diffusion stopping layer on the substrate; depositing an interfacial layer comprising a nitrogen-enriched titanium layer, or a titanium alloy, or a nitrogen-enriched titanium alloy on the diffusion stopping layer; and depositing a bulk aluminum layer on the interfacial layer to metallize the substrate.
A workpiece processing system for extracting ion beams at low extraction voltages is disclosed. The workpiece processing system includes an ion source with an extraction plate having an extraction aperture. A ground electrode is rigidly affixed to the extraction plate so as to tightly control the positioning accuracy between the extraction aperture and the aperture in the ground electrode. A suppression electrode is located between the extraction plate and the ground electrode. This suppression electrode is also rigidly mounted so as to create a fixed first gap between the extraction plate and the suppression electrode and a fixed second gap between the suppression electrode and the ground electrode. This system may be operated at extraction voltages as low as 100V and as high as several kV.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
13.
ETCHING METHOD TO RECESS SIGE AND SIGEC IN EPI STACK WITH SELECTIVITY TO SILICON
Embodiments of the present disclosure generally relate to 3D semiconductor device fabrication techniques. More specifically, embodiments, described herein provide processes by which to selectively etch layers of SiGe and/or SiGeC from Si layers. In some embodiments, a method for processing a semiconductor device includes positioning a semiconductor device in a processing volume of a processing chamber. The semiconductor device includes alternating silicon (Si) layers and silicon germanium (SiGe) layers. The method further includes introducing a process gas to the processing chamber. The process gas includes an etchant gas and a passivation gas. The method further includes performing a selective etch operation using the process gas to remove the SiGe layers from the semiconductor device.
The present technology is directed to methods and systems for cleaning deposition and/or fill byproducts from a backside or edge of a substrate. Methods include providing one or more deposition and/or fill precursors to a processing region of a semiconductor processing chamber and depositing one or more layers of the deposition and/or fill material on the substrate. Methods include forming a gap between the substrate and a substrate support surface of the substrate support. Methods include generating a DC plasma between the substrate support and a sidewall of the semiconductor processing chamber. Methods include treating the deposition and/or fill material with a DC plasma to remove at least a portion of the deposition and/or fill material from a back side and/or a bevel of the substrate.
C23C 16/50 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
15.
CAVITY CONTACT FORMATION USING PLASMA DOPING PROCESS
Approaches herein relate to devices and methods for forming cavity contacts using a plasma doping process. One method may include forming a plurality of alternating first layers and second layers, and forming a source/drain epitaxial material within a trench of the plurality of alternating first layers and second layers. The method may further include forming a cavity in source/drain epitaxial material, and performing a plasma doping process to form a doped area in the source/drain epitaxial material.
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
16.
INTEGRATED SEMICONDUCTOR DEVICE MODULE, METHOD OF OPERATING AN APPARATUS FOR TESTING OF AN INTEGRATED SEMICONDUCTOR DEVICE MODULE, AND APPARATUS FOR TESTING INTEGRATED SEMICONDUCTOR DEVICE MODULE
A 3D integrated semiconductor device module, particularly a high-bandwidth memory module, is described. The 3D integrated semiconductor device module includes a semiconductor body having a first surface opposite a second surface; a plurality of device connections; one or more data buses coupled to the plurality of device connections; a plurality of logic elements coupled to the one or more data buses; a plurality of ground connections; a ground network coupled directly or indirectly to the plurality of ground connections; a plurality of test connections, the plurality of test connections disconnected from the one or more data buses, and disconnected from the ground network, the plurality of test connections configured for voltage signal testing of the 3D integrated semiconductor device module; and a plurality of test interconnect paths, each coupled to one or more of the plurality of test connections.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
G01R 31/307 - Test sans contact utilisant des faisceaux électroniques de circuits intégrés
G01R 31/303 - Test sans contact de circuits intégrés
H01J 37/28 - Microscopes électroniques ou ioniquesTubes à diffraction d'électrons ou d'ions avec faisceaux de balayage
17.
METHOD OF TRANSPORTING A SUBSTRATE, CARRIER ASSEMBLY FOR CARRYING A SUBSTRATE, SHIELD CARRIER, AND DEPOSITION SYSTEM
A carrier assembly comprises a shield carrier detachably connectable to a substrate support component to provide a combined carrier. The substrate support component comprises a chucking device for holding the substrate at a substrate holding surface. The shield carrier comprises: an edge exclusion shield configured to cover an edge region of the substrate support component and of the substrate held at the substrate holding surface, when the substrate support component and the shield carrier are connected; and a shield carrier transport unit configured to interact with a first carrier transport system for transporting the shield carrier along a first carrier transport path in the deposition system. At least one of the substrate support component and the shield carrier comprises at least one connector configured to attach the shield carrier and the substrate support component to each other to provide the combined carrier.
Embodiments herein provide for a measurement system for determining an optical device modulation transfer function (MTF). The measurement system includes a stage operable to retain an optical device or an optical device substrate having at least one optical device disposed thereon. A light engine is disposed above the stage. The light engine includes a light source operable to project a light to the optical device at a range of wavelengths. A reticle is operable to form a pattern from the light projected from the light source. A first lens operable to collimate the light from the light source toward the optical device or optical device substrate. A near field detector is operable to detect the light from the optical device or optical device substrate. A far field detector is operable to detect the light from the optical device of optical device substrate.
A method for coating an optically reflective layer on a waveguide having an in-coupler grating, the method comprising:
depositing an ink by screen printing on the in-coupler grating of the waveguide.
C03C 17/10 - Traitement de surface du verre, p. ex. du verre dévitrifié, autre que sous forme de fibres ou de filaments, par revêtement par des métaux par dépôt à partir d'une phase liquide
G02B 6/34 - Moyens de couplage optique utilisant des prismes ou des réseaux
Exemplary substrate processing systems may include a plurality of processing regions. The systems may include a transfer region housing defining a transfer region fluidly coupled with the plurality of processing regions. The systems may include a plurality of substrate supports, and each substrate support of the plurality of substrate supports may be vertically translatable between the transfer region and an associated processing region of the plurality of processing regions. The systems may include a transfer apparatus including a rotatable shaft extending through the transfer region housing. The transfer apparatus may include an end effector coupled with the rotatable shaft. The end effector may include a central hub defining a central aperture fluidly coupled with a purge source. The end effector may also include a plurality of arms having a number of arms equal to a number of substrate supports of the plurality of substrate supports.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/54 - Appareillage spécialement adapté pour le revêtement en continu
Embodiments of the disclosure provided herein include systems and methods for cleaning semiconductor substrates The method includes rotating a substrate disposed on a substrate support, spraying a front side of the substrate using a cleaning agent including one or more chelating agents through a front side nozzle assembly disposed above the substrate support, and spraying a back side of the substrate using the cleaning agent through a back side dispenser assembly disposed below the substrate support.
B08B 3/08 - Nettoyage impliquant le contact avec un liquide le liquide ayant un effet chimique ou dissolvant
B08B 3/04 - Nettoyage impliquant le contact avec un liquide
B08B 3/12 - Nettoyage impliquant le contact avec un liquide avec traitement supplémentaire du liquide ou de l'objet en cours de nettoyage, p. ex. par la chaleur, par l'électricité ou par des vibrations par des vibrations soniques ou ultrasoniques
A workpiece processing system for extracting ion beams at low extraction voltages is disclosed. The workpiece processing system includes an ion source with an extraction plate having an extraction aperture. A ground electrode is rigidly affixed to the extraction plate so as to tightly control the positioning accuracy between the extraction aperture and the aperture in the ground electrode. A suppression electrode is located between the extraction plate and the ground electrode. This suppression electrode is also rigidly mounted so as to create a fixed first gap between the extraction plate and the suppression electrode and a fixed second gap between the suppression electrode and the ground electrode. This system may be operated at extraction voltages as low as 100V and as high as several kV.
An end effector that includes replaceable pads is disclosed. The pads may be constructed from a different dielectric material than the end effector. This difference in dielectric material may help reduce particle generation and workpiece damage. Additionally, the pad is attached to the end effector using a latch and a spring, which allows the assembly to remain operational over a wide range of temperatures, even if the end effector and pad have coefficients of thermal expansion that differ by an order of magnitude or more. This assembly may operate to temperatures from −150° C. up to 500° C.
B25J 15/04 - Têtes de préhension avec possibilité pour l'enlèvement ou l'échange à distance de la tête ou de parties de celle-ci
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
24.
PLASMA PROCESSING SYSTEM CONFIGURED TO DELIVER A PULSED VOLTAGE WAVEFORM
Embodiments of plasma processing systems are provided. The plasma processing systems include a junction box enclosure electrically coupling a direct current voltage source and a pulsed voltage source to a direct current conductor that is coupled to a substrate support and further electrically coupling the pulsed voltage source to a radio frequency conductor coupled to the radio frequency baseplate. The junction box enclosure includes a pulsed voltage filter circuit coupled between the radio frequency source and the radio frequency conductor. The junction box enclosure includes a radio frequency filter circuit coupled between the pulsed voltage source and the direct current conductor. The junction box enclosure includes a bias compensation module coupled between the radio frequency filter circuit and the direct current voltage source. The junction box enclosure includes a compensator circuit configured to compensate for a parasitic capacitance generated by the bias compensation module.
Disclosed herein is a removable isolation panel for an equipment front end module (EFEM). The removable isolation panel may include a rectangular body having dimensions that approximately correspond to dimensions of one or more filters of the EFEM, a gas inlet, one or more handles to facilitate carrying of the removable isolation panel and positioning of the removable isolation panel into the EFEM, and a gasket at a peripheral edge of the rectangular body to seal the removable isolation panel against a surface of an upper plenum of the EFEM or an EFEM chamber of the EFEM. In some embodiments, the removable isolation panel is configured to flow a gas through the gas inlet towards one or more filters of the EFEM while the EFEM is open to an ambient environment to prevent the one or more filters from absorbing moisture of the ambient environment.
iiiiiiiii) generating a third pulse at a third voltage at the common node at the first time based on a third transformer ratio of a third transformer included in a third voltage stage.
The present disclosure generally relates to methods for forming a semiconductor device, a semiconductor device, and a processing system. The method includes forming a first epitaxial semiconductor layer on a cavity within the source/drain region of a semiconductor device structure formed on a substrate, forming a second highly doped recessed semiconductor layer that wraps around the first epitaxial semiconductor layer, and forming a metal contact plug. The first epitaxial semiconductor layer and the second epitaxial semiconductor layer are formed without breaking vacuum in the processing system. Embodiments of the present disclosure enable the formation of the semiconductor device that includes one or more layers with reduced contact resistance by using integrated processes that allows various operations of epitaxial semiconductor layer formation be performed within the same processing system.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
Multi-die packages may include a cover or lid that is placed over vertical stacks of silicon dies. This lid connects to a cooling system or heatsink to dissipate heat away from the dies. However, as thermal expansion/contraction occurs, the dies may lose contact with the cover and heat may build up within the cover around the dies. To solve this problem, a cover may include a flexible membrane on the bottom surface of the cover. The flexible membrane may create an internal cavity filled with a pressurized thermally conductive liquid. The liquid may cause the flexible membrane to expand and conform to a profile of the dies as they move due to temperature changes. The flexible membrane ensures that a thermally conductive pathway is maintained between the cover and the dies to effectively dissipate heat away from the dies.
Methods and systems for organic defect source identification using artificial intelligence (AI) are provided. One or more images depicting a surface of a substrate processed using one or more manufacturing equipment is provided as input to an artificial intelligence (AI) model. Output(s) of the AI model is obtained, where the output(s) indicate defect characterization data associated with a defect detected on the surface of the substrate depicted by the one or more images. A determination is made of whether a level of confidence of at least one defect type and associated defect source from the defect characterization data satisfies one or more confidence criteria. Upon a determination that at least one defect type and associated defect source satisfy the one or more confidence criteria, the at least one defect type and associated defect source are provided to a client device for presentation to one or more users.
G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
In one or more embodiments, a processing chamber includes a first plate, a second plate, and a plurality of sidewalls partially defining a processing volume. A cover is disposed above the first plate. The cover and the first plate at least partially define an upper heating area. A first energy module is disposed within the upper heating area. The first energy module includes a plurality of heating elements. A plurality of ribs are disposed around the first plate, the second plate, and the sidewalls. A substrate support is disposed in the processing volume. One or more spot heaters are configured to emit a radiation beam toward the substrate support. The one or more spot heaters include a collimator supported by a holder and a stage. The holder is disposed on the stage. The one or more spot heaters further include a support, wherein the stage is disposed on the support.
Embodiments described herein relate to a method for changing a tone of a metal oxide resist (MOR) layer that is patterned to have a first pattern. In an embodiment, the method includes transferring the first pattern into an underlayer below the MOR layer, forming a hardmask around the underlayer with an area selective deposition process, and removing the underlayer to form a second pattern in the hardmask. In an embodiment, the second pattern is an inverse of the first pattern.
G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage
Embodiments described herein relate to a method of modifying a resist layer that is provided over an underlayer. In an embodiment, the method includes exposing a portion of the resist layer and the underlayer to extreme ultraviolet (EUV) radiation to form an exposed region and an unexposed region, where the EUV radiation releases an acid from the exposed region of the underlayer. In an embodiment, the method further includes neutralizing photo decomposable quenchers (PDQs) in the exposed region of the resist layer with the acid.
G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage
G03F 7/16 - Procédés de couchageAppareillages à cet effet
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
Multi-die packages may include a cover or lid that is placed over vertical stacks of silicon dies. This lid connects to a cooling system or heatsink to dissipate heat away from the dies. However, as thermal expansion/contraction occurs, the dies may lose contact with the cover and heat may build up within the cover around the dies. To solve this problem, a cover may include a flexible membrane on the bottom surface of the cover. The flexible membrane may create an internal cavity filled with a pressurized thermally conductive liquid. The liquid may cause the flexible membrane to expand and conform to a profile of the dies as they move due to temperature changes. The flexible membrane ensures that a thermally conductive pathway is maintained between the cover and the dies to effectively dissipate heat away from the dies.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
35.
ELECTROSTATIC CHUCK WITH LIGHT-UP RESISTANT FLOW ENHANCEMENT PLUG
Flow enhancement plugs and electrostatic chucks having the same are disclosed herein that that inhibit gas light-up while providing excellent flow conductance for the delivery of backside gases to the substrate support surface of the electrostatic chuck. The flow enhancement plugs advantageously prevents line of sight passage through the plug. The flow enhancement plugs described herein have high conductance flow structures selected from one, two or all of a network of engineered gas passages, external gas passages and internal gas passages. As a result, the high conductance flow structures of the flow enhancement plugs disclosed herein beneficially have a conductance that is much lower than conventional porous plug.
Embodiments described herein relate to methods and apparatus for detecting and/or monitoring, e.g., abnormalities in wafer transfer and handling. In an embodiment, a method for wafer dechucking verification is provided. The method includes initiating a wafer transfer operation to transfer a wafer between components of a semiconductor processing system, the semiconductor processing system comprising a motor coupled to a lift pin, the motor configured to adjust a height of the lift pin above a pedestal, the lift pin for raising or lowering the wafer. The method further includes measuring one or more first parameters during the wafer transfer operation, comparing the one or more first parameters to one or more first pre-determined parameter ranges, and changing a force applied to the lift pin based on the one or more first parameters. Apparatus for wafer dechucking verification and non-transitory computer-readable mediums storing instructions for wafer dechucking verification are also provided
Substrate support assembly and methods of making such substrate support assemblies are provided. Substrate support assemblies include an electrostatic chuck body defining a substrate support surface, a support stem coupled with the electrostatic chuck body, and an electrode embedded within the electrostatic chuck body. Substrate support surfaces exhibit a resistivity of 1×108 Ω-cm to 1×1011 Ω-cm at a temperature of greater than 650° C. Substrate support surfaces can include a composite ceramic material having a base dielectric material and a second dielectric material having an electrical resistivity at least about two times higher than an electrical resistivity of the base dielectric material at a temperature of greater than 650° C.
A method includes receiving data indicative of an input value of a setting for calibration of an equipment parameter of a process tool of a plurality of process tools of a manufacturing system. The method further includes determining, based on the data, a predicted value of a metric corresponding to the equipment parameter. The method further includes updating the setting for calibration of the equipment parameter based on the input value and the predicted value.
G05B 13/02 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques
G05B 13/04 - Systèmes de commande adaptatifs, c.-à-d. systèmes se réglant eux-mêmes automatiquement pour obtenir un rendement optimal suivant un critère prédéterminé électriques impliquant l'usage de modèles ou de simulateurs
39.
EVAPORATION SOURCE, VACUUM DEPOSITION SYSTEM, AND METHOD OF COATING A SUBSTRATE
An evaporation source for depositing a mixed material layer onto a substrate (10) that is arranged in a substrate plane in a vacuum chamber is described. The evaporation source (100) includes: a first vapor distribution pipe (110); a plume shaper arrangement (210); and a second vapor distribution pipe (120). a row of first nozzles (111) and a row of second nozzles (121) are configured to deposit a mixed material layer including the first and second materials onto a substrate that is moved relative to the evaporation source.
H10K 71/16 - Dépôt d'une matière active organique en utilisant un dépôt physique en phase vapeur [PVD], p. ex. un dépôt sous vide ou une pulvérisation cathodique
40.
METHOD AND APPARATUS FOR MANUFACTURING PIXELS ON A SUBSTRATE
A method of manufacturing pixels on a substrate (10) includes guiding an evaporated source material through a plurality of nozzles (22) of an evaporation source (20), each of the nozzles generating a plume (318) of evaporated source material propagating towards the substrate. The method includes individually shaping the plumes using a plurality of shaping apertures (33). Each shaping aperture has an aperture shape and an aperture orientation. A portion of the plumes passes through a plurality of pixel openings (490) of a mask structure to deposit a pixel pattern including a plurality of pixel layers (410) on the substrate. Each pixel opening (490) has a pixel opening shape and a pixel opening orientation. At least one of the aperture shape and the aperture orientation of the shaping apertures is adapted to at least one of the pixel opening shape and the pixel opening orientation of the pixel openings.
H10K 71/16 - Dépôt d'une matière active organique en utilisant un dépôt physique en phase vapeur [PVD], p. ex. un dépôt sous vide ou une pulvérisation cathodique
C23C 14/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method of forming a contact structure on a semiconductor substrate includes performing a microwave oxidation etch process on the contact structure. The microwave oxidation etch process includes flowing a first process gas over the contact structure and delivering a microwave energy to the first process gas without generating a plasma in a processing chamber. The contact structure includes a feature, the feature is defined by a silicon-based portion, a bottom surface, a top-side surface, a first sidewall, and a second sidewall. At least one liner layer is disposed over the contact structure. The method further includes depositing a metal gap fill material over the contact structure to fill the feature.
Flow enhancement plugs and electrostatic chucks having the same are disclosed herein that inhibit gas light-up while providing excellent flow conductance for the delivery of backside gases to the substrate support surface of the electrostatic chuck. The flow enhancement plugs advantageously prevents line of sight passage through the plug. The flow enhancement plugs described herein have high conductance flow structures selected from one, two or all of a network of engineered gas passages, external gas passages and internal gas passages. As a result, the high conductance flow structures of the flow enhancement plugs disclosed herein beneficially have a conductance that is much higher than conventional porous plug.
Embodiments of the present disclosure generally relate to optical devices including a high-elongation interface material, and related methods. In one or more embodiments, an optical device, includes at least one grating over a surface of a substrate. Each grating includes a plurality of structures and one or more gap fill materials over the plurality of structures. The optical device further includes an encapsulation material over the one or more gap fill materials and a high-elongation material over the encapsulation material. The high-elongation material has an elongation greater than or equal to 20%. The optical device further includes a lens over the high-elongation material.
Embodiments described herein generally relate to an assembly. In one or more embodiments, an assembly includes a substrate having a first surface and a second surface, the first surface opposite the second surface. A first redistribution layer (RDL) is disposed over the first surface. At least one non-embedded component disposed over the first RDL. At least one embedded component is disposed within the substrate and contacts the first RDL. At least one component interconnect connects the at least one embedded component to the at least one non-embedded component.
Embodiments described herein relate to a method of patterning a resist layer with an exposed region and an unexposed region. In an embodiment, the method includes applying a block copolymer over the resist layer, where the block copolymer includes a polar region and a non-polar region, and where a chemical difference between the exposed region and the unexposed region allows for directed self-assembly of the block copolymer over the resist layer. In an embodiment, the method further includes selectively removing either the polar region or the non-polar region to form a patterned mask over the resist layer, and patterning the resist layer with an etching process using the patterned mask.
G03F 7/11 - Matériaux photosensibles caractérisés par des détails de structure, p. ex. supports, couches auxiliaires avec des couches de recouvrement ou des couches intermédiaires, p. ex. couches d'ancrage
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
Approaches herein relate to devices and methods for forming cavity contacts using a plasma doping process. One method may include forming a plurality of alternating first layers and second layers, and forming a source/drain epitaxial material within a trench of the plurality of alternating first layers and second layers. The method may further include forming a cavity in source/drain epitaxial material, and performing a plasma doping process to form a doped area in the source/drain epitaxial material.
H01L 21/223 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase gazeuse
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
The present technology is directed to methods and systems for cleaning deposition and/or fill byproducts from a backside or edge of a substrate. Methods include providing one or more deposition and/or fill precursors to a processing region of a semiconductor processing chamber and depositing one or more layers of the deposition and/or fill material on the substrate. Methods include forming a gap between the substrate and a substrate support surface of the substrate support. Methods include generating a DC plasma between the substrate support and a sidewall of the semiconductor processing chamber. Methods include treating the deposition and/or fill material with a DC plasma to remove at least a portion of the deposition and/or fill material from a back side and/or a bevel of the substrate.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
48.
SUBSTRATE STRESS MANAGEMENT USING HIGH TEMPERATURE IMPLANTATION
A method for stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate, and performing a high-temperature implant procedure in an ion implanter to implant a dose of ions into the stress compensation layer. The high temperature implant procedure may include heating the substrate to an implant temperature, the implant temperature being between 300° C. and 750° C., and exposing the substrate to an ion beam while the substrate is held at the implant temperature, wherein the implant procedure alters an out-of-plane distortion of the substrate.
The present disclosure relates to systems, apparatus, and methods for multi-wavelength monitoring for semiconductor manufacturing. In one or more embodiments, a system for processing substrates includes a chamber body at least partially defining an internal volume, one or more heat sources configured to heat the internal volume, a substrate support disposed in the internal volume, and a sensor assembly operable to measure energy of a plurality of wavelengths in the internal volume. The sensor assembly includes one or more optical sensors, a movable tray coupled to a motor, and a plurality of filters supported by the movable tray, the motor operable to move the movable tray to move the plurality of filters relative to the one or more optical sensors to respectively align the plurality of filters with at least one of the one or more optical sensors.
A system that obtains a plurality of sensor values associated with a deposition process performed in a process chamber to deposit film on a surface of a substrate. The system then applies a virtual model to the plurality of sensor values. The virtual model is trained based on historical sensor data and a plurality of physics based outputs used to process non-linear relationships between the historical sensor data from different sensors in the process chamber. The plurality of physics based outputs were generated using a transformation function and the historical sensor data. The transformation function comprises functions associated with at least one of chemical kinetics or Langmuir adsorption model. The system obtains an output of the virtual model, the output identifying predictive metrology data for the film.
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 18/214 - Génération de motifs d'entraînementProcédés de Bootstrapping, p. ex. ”bagging” ou ”boosting”
H01L 21/70 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun, ou de parties constitutives spécifiques de ceux-ciFabrication de dispositifs à circuit intégré ou de parties constitutives spécifiques de ceux-ci
51.
HIGH HEAT LOSS HEATER AND ELECTROSTATIC CHUCK FOR SEMICONDUCTOR PROCESSING
Exemplary substrate support assemblies may include an electrostatic chuck body defining a support surface that defines a substrate seat. The substrate support surface may include a dielectric coating. The substrate support assemblies may include a support stem coupled with the electrostatic chuck body. The substrate support assemblies may include a cooling hub positioned below a base of the support stem and coupled with a cooling fluid source. The electrostatic chuck body may define at least one cooling channel that is in communication with a cooling fluid source. The substrate support assemblies may include a heater embedded within the electrostatic chuck body. The substrate support assemblies may include an AC power rod extending through the support stem and electrically coupled with the heater. The substrate support assemblies may include a plurality of voids formed within the electrostatic chuck body between the at least one cooling channel and the heater.
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
A method of chemical mechanical polishing of a substrate is provided. The method includes retrieving a substrate (122) with a first substrate surface (401) oriented away from a polishing head (110) and a second substrate surface (403) oriented toward the polishing head (110), translating the polishing head (110) over a bulk polishing pad (421) and performing a first bulk polishing operation on the first substrate surface (401), translating the polishing head (110) over a fine polishing pad (423) and performing a first fine polishing operation on the first substrate surface (401), reorienting the substrate (122), translating the polishing head (110) over the bulk polishing pad and performing a second bulk polishing operation on the second substrate surface (403), and translating the polishing head (110) over the fine polishing pad and performing a second fine polishing operation on the second substrate surface (403). The first substrate surface (401) is a carbon rich surface, and the second substrate surface (403) is a device side of the substrate. The method can enhance the polishing of the substrate surfaces to remove defects such as dark edge rings.
A method (100) of loading an evaporation source (300) with material for evaporation is described. The method includes: filling (110) an evaporation crucible (200) in an inert gas atmosphere with the material for evaporation; closing (120) the evaporation crucible (200) in the inert gas atmosphere via a sliding closing mechanism (220); mounting (130) the evaporation crucible (200) to the evaporation source (300) in a mounting direction (131); and opening (140) a slidable closure (221) of the sliding closing mechanism (220) by moving the slidable closure (221) in a direction (132) opposite to the mounting direction (131). Further, an evaporation crucible to evaporate material, an evaporation source and a deposition system are described.
Embodiments described herein relate to a method of patterning a resist layer with an exposed region and an unexposed region. In an embodiment, the method includes applying a block copolymer over the resist layer, where the block copolymer includes a polar region and a non¬ polar region, and where a chemical difference between the exposed region and the unexposed region allows for directed self-assembly of the block copolymer over the resist layer. Tn an embodiment, the method further includes selectively removing either the polar region or the non¬ polar region to form a patterned mask over the resist layer, and patterning the resist layer with an etching process using the patterned mask.
An ion implanter. The ion implanter may include an ion source, to generate an ion beam. The ion source may include an ion source chamber, and an adjustable electrode set, external to the ion source chamber. The ion implanter may include a set of beamline components, disposed along a beamline of the ion implanter, and arranged to direct the ion beam to a substrate position. The ion implanter may further include an in-situ beam imaging system, having at least one detector that images the ion beam in at least one location, between the ion source and the substrate position.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
H01J 37/22 - Dispositifs optiques ou photographiques associés au tube
Methods and apparatus for processing a substrate using a plasma processing system. One example plasma processing system generally includes a first electrode, a second electrode, and a system controller comprising one or more processors and memory that includes computer-executable instructions. The one or more processors are generally configured to execute the computer- executable instructions and cause the plasma processing system to: deliver, using a first radio frequency (RF) generator, a first RF waveform to the first electrode at a first RF frequency, and adjust, using a direct current (DC) supply, a voltage applied to the second electrode during the delivery of the first RF waveform.
Embodiments of the present disclosure generally relate to near-eye display systems. More specifically, embodiments described herein provide a near-eye display system with a waveguide display assembly having a light engine with polarized light output and a polarization switch for projecting image light toward an input coupling grating of a waveguide combiner.
G02B 27/28 - Systèmes ou appareils optiques non prévus dans aucun des groupes , pour polariser
G02F 1/1335 - Association structurelle de cellules avec des dispositifs optiques, p. ex. des polariseurs ou des réflecteurs
G02F 1/139 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des cristaux liquides, p. ex. cellules d'affichage individuelles à cristaux liquides caractérisés par l'effet électro-optique ou magnéto-optique, p. ex. transition de phase induite par un champ, effet d'orientation, interaction entre milieu récepteur et matière additive ou diffusion dynamique basés sur des effets d'orientation où les cristaux liquides restent transparents
Embodiments described herein relate to an apparatus that includes a laser configured to emit a laser beam, and an optics module optically coupled to the laser. In an embodiment, the optics module includes an optical element configured to split the laser beam into a plurality of split beams. In an embodiment, the apparatus further includes a plurality of optical fibers, where each of the plurality of optical fibers is configured to receive a corresponding one of the plurality of split beams.
G01N 21/3504 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge pour l'analyse des gaz, p. ex. analyse de mélanges de gaz
61.
ION IMPLANTER AND METHOD OF ION BEAM CONTROL USING ION BEAM IMAGING SYSTEM
An ion implanter. The ion implanter may include an ion source, to generate an ion beam. The ion source may include an ion source chamber, and an adjustable electrode set, external to the ion source chamber. The ion implanter may include a set of beamline components, disposed along a beamline of the ion implanter, and arranged to direct the ion beam to a substrate position. The ion implanter may further include an in-situ beam imaging system, having at least one detector that images the ion beam in at least one location, between the ion source and the substrate position.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method of forming a contact structure on a semiconductor substrate includes performing a microwave oxidation etch process on the contact structure. The microwave oxidation etch process includes flowing a first process gas over the contact structure and delivering a microwave energy to the first process gas without generating a plasma in a processing chamber. The contact structure includes a feature, the feature is defined by a silicon-based portion, a bottom surface, a top-side surface, a first sidewall, and a second sidewall. At least one liner layer is disposed over the contact structure. The method further includes depositing a metal gap fill material over the contact structure to fill the feature.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
63.
Heat Dissipation Methods and Structures for Semiconductor Devices
A method of increasing thermal uniformity of a substrate incorporates high thermal conductivity material in place of shallow trench isolation (STI) dielectric material or interlayer dielectric (ILD) material on a backside of a thinned substrate. The method may comprise removing at least a portion of an STI dielectric material and/or ILD material and depositing a second dielectric material in place of the STI dielectric material that is removed. The second dielectric material has a higher thermal conductivity than the STI dielectric material. The removal may incorporate a wet or dry etch process that is selective to the STI dielectric material and/or the ILD material over other materials used in formation of semiconductor structures on a substrate.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A method and apparatus for forming a super-lattice structure on a substrate is described herein. The super-lattice structure includes a plurality of silicon-germanium layers and a plurality of silicon layers disposed in a stacked pattern. The methods described herein produce a super-lattice structure with transition width of less than about 1.4 nm between each of the silicon-germanium layers and an adjacent silicon layer. The methods described herein include flowing one or a combination of a silicon containing gas, a germanium containing gas, and a halogenated species.
H10D 62/815 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux de structures présentant des effets de confinement quantique, p. ex. des puits quantiques uniquesCorps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux de structures présentant une variation de potentiel périodique ou quasi-périodique de structures présentant une variation périodique ou quasi-périodique de potentiel, p. ex. super-réseaux ou puits quantiques multiples [MQW]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
Disclosed herein is a system for non-destructive classification of specimens. The system includes an e-beam source, an X-ray measurement module, and a computational module. The e-beam source is configured to project e-beams on a specimen at one or more e-beam landing energies, so as to penetrate the specimen and induce emission of X-rays. The X-ray measurement module is configured to measure the emitted X-rays. The computational module is configured to process the measurement data to obtain an energy signature of at least one target substance included in the specimen and classify the inspected specimen based on the obtained energy signature and one or more reference energy signatures pertaining to one or more reference specimens, respectively.
G01N 23/2252 - Recherche ou analyse des matériaux par l'utilisation de rayonnement [ondes ou particules], p. ex. rayons X ou neutrons, non couvertes par les groupes , ou en mesurant l'émission secondaire de matériaux en utilisant des microsondes électroniques ou ioniques en utilisant des faisceaux d’électrons incidents, p. ex. la microscopie électronique à balayage [SEM] en mesurant les rayons X émis, p. ex. microanalyse à sonde électronique [EPMA]
Exemplary semiconductor processing methods may include providing a halogen-containing precursor and an inert gas to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of silicon-containing material may overlie the substrate. The methods may include contacting the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a first period of time to form a halogenated portion of the layer of silicon-containing material. The methods may include, subsequent to the first period of time, applying a source power and a bias power or a bias voltage while continuing to contact the layer of silicon-containing material with the halogen-containing precursor and the inert gas for a second period of time to desorb the halogenated portion of the layer of silicon-containing material.
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
67.
DUAL-LAYER COATINGS FOR ENHANCED SEMICONDUCTOR PROCESSING CHAMBER PROTECTION
Exemplary coating methods may include providing one or more coating precursors to a processing region of a semiconductor processing chamber. The processing region may be at least partially defined by a lid and one or more walls. The coating methods may include forming plasma effluents of the one or more coating precursors. The coating methods may include depositing a first portion of a coating on the lid and one or more walls at a first pressure. The coating methods may include, subsequent to a first period of time, increasing a pressure within the processing region to a second pressure over a second period of time while depositing a second portion of the coating on the first portion of the coating. The coating methods may include depositing a third portion of the coating on the second portion of the coating over a third period of time at the second pressure.
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
68.
ZONAL WINDOW CONTROL TO IMPROVE WAFER FILM THICKNESS UNIFORMITY
A window for use in a processing chamber applicable for use in semiconductor manufacturing, including a first zone disposed between a first radius and a second radius including a first transmissivity and a second zone disposed between the second radius and a third radius including a second transmissivity.
A system configured to, in response to an occurrence of a corrective maintenance event, obtain first sensor data pertaining to a first process run and second sensor data pertaining to a second process run. Responsive to determining that a comparison of the first sensor data and the second sensor data fails to satisfy a first threshold criterion, the system generates a first normalized dataset based on the first sensor data and a second normalized dataset based on the second sensor data. The system then generates trace matching data by performing a trace matching operation on the first normalized dataset and the second normalized dataset. Responsive to determining that the trace matching data satisfies a second threshold criterion, the system identifies a set of sensors associated with the first sensor data as the cause of the fault that triggered the corrective maintenance event.
Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method for etching a semiconductor device structure is disclosed includes performing a microwave oxidation etch process on the semiconductor device structure, wherein a hard mask is disposed over at least a portion of the semiconductor device structure. The microwave oxidation etch process includes flowing a first process gas over the semiconductor device structure and delivering a microwave energy to the first process gas without generating a plasma. The method further includes performing a preclean process on the semiconductor device structure. The preclean process includes flowing a second process gas over the semiconductor device structure.
The present invention relates to components in ion implanters having surfaces adjacent to the path of the ion beam through the ion implanter. Such surfaces will be prone to deposition and the present invention addresses problems associated with delamination of deposited material. An ion implanter component is provided that has a surface defining at least in part an ion beam path through the ion implanter, wherein at least a portion of the surface is textured, the texture including serrations or pyramidal structures.
H01J 37/317 - Tubes à faisceau électronique ou ionique destinés aux traitements localisés d'objets pour modifier les propriétés des objets ou pour leur appliquer des revêtements en couche mince, p. ex. implantation d'ions
72.
AMORPHPOUS SILICON GAPFILL USING ICP PLASMA AT LOW PRESSURE AND HIGHER TEMPERATURE
Methods and devices for forming gap fill materials on the surface of a substrate are provided herein. Embodiments include flowing a silicon-containing precursor into a process chamber at a flow rate that allows for maintaining a pressure inside the process chamber at less than 5 mTorr. Embodiments further include depositing an amorphous silicon layer on a feature of a substrate based on applying an inductively coupled plasma power of at least three kilowatts (kW).
C23C 16/46 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour le chauffage du substrat
C23C 16/507 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement au moyen de décharges électriques utilisant des décharges à radiofréquence utilisant des électrodes externes, p. ex. dans des réacteurs de type tunnel
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
Embodiments described herein relate to a device. The device includes a substrate, a plurality of separation structures disposed over the substrate, wherein each separation structure comprises an upper surface, and a plurality of sub-pixels. Each sub-pixel includes adjacent overhang structures having an overhang defined by an extension of a second structure extending laterally past an upper surface of a first structure. The second structure is disposed over the first structure. An overhang structure of the adjacent overhang structures defines a repair hole formed in the first structure and the second structure. The anode includes a first sub-pixel division, a second sub-pixel division, and a connection region electrically coupling the first subpixel division and the second sub-pixel division. A separation structure is disposed between the first sub-pixel division and the second sub-pixel division. The repair hole exposes a portion of the separation structure disposed over the connection region.
Embodiments of the present disclosure herein generally relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. In one embodiment, a device is disclosed. The device includes a pixel-defining layer (PDL) structure disposed over the substrate, defining an anode, and an overhang structure thereover. The PDL structure has a first PDL region, a second PDL region opposing the first PDL region, a third PDL region, and a fourth PDL region opposing the third PDL region. At least one sub-pixel is defined by the overhang structure, and includes a cathode. The cathode contacts at least one of the first sidewall and the second sidewall at a first thickness, and the third sidewall and the fourth sidewall at a second thickness. The first thickness is greater than the second thickness.
In one or more embodiments, a device includes a substrate, a first busbar, and a second busbar. Overhang structures are disposed over the substrate. A first subpixel is bounded by a first overhang structure and a second overhang structure. The first sub-pixel includes a first anode. A first organic light-emitting (OLE) material is disposed over the first anode. A first cathode is disposed over the first OLE material. The first cathode contacts the first overhang structure. The first overhang structure is electrically coupled to the first busbar. A second sub-pixel is bounded by a third overhang structure and a fourth overhang structure. The second sub-pixel includes a second anode. A second organic light-emitting (OLE) material is disposed over the second anode. A second cathode is disposed over the second OLE material. The second cathode contacts the third overhang structure. The third overhang structure is electrically coupled to the second busbar.
A window for use in a processing chamber applicable for use in semiconductor manufacturing, including a first zone disposed between a first radius and a second radius including a first transmissivity and a second zone disposed between the second radius and a third radius including a second transmissivity.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H05B 3/02 - Chauffage par résistance ohmique Détails
77.
PLASMA PROCESSING SYSTEMS WITH DIRECT CURRENT VOLTAGE FOR PLASMA ENERGY CONTROL
Methods and apparatus for processing a substrate using a plasma processing system. One example plasma processing system generally includes a first electrode, a second electrode, and a system controller comprising one or more processors and memory that includes computer-executable instructions. The one or more processors are generally configured to execute the computer-executable instructions and cause the plasma processing system to: deliver, using a first radio frequency (RF) generator, a first RF waveform to the first electrode at a first RF frequency, and adjust, using a direct current (DC) supply, a voltage applied to the second electrode during the delivery of the first RF waveform.
A plasma source includes a holding structure and a plurality of plasma generating cells coupled to the holding structure. Each plasma generating cell includes a base structure including a dielectric rod, a plurality of electrodes disposed on an outer surface of the dielectric rod, and a dielectric layer disposed over at least a region of the plurality of electrodes to form a dielectric barrier discharge (DBD) region.
G01F 1/56 - Mesure du débit volumétrique ou du débit massique d'un fluide ou d'un matériau solide fluent, dans laquelle le fluide passe à travers un compteur par un écoulement continu en utilisant des effets électriques ou magnétiques
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
G01F 1/688 - Dispositions de structureMontage des éléments, p. ex. relativement à l'écoulement de fluide utilisant un élément de chauffage, de refroidissement ou de détection d'un type particulier
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
Methods and apparatus for generating plasma in an inductively coupled plasma (ICP) process chamber leverage pulsing of power sources in response to processes being performed by the ICP process chamber. In some embodiments, a method may include generating ICP RF powers from multiple ICP RF power sources to produce plasma in a process volume of the ICP process chamber where the ICP RF power sources interact with coils positioned above the process volume, generating an auxiliary RF power from one or more auxiliary RF plasma power sources connected to an auxiliary plasma source in fluid communication with the process volume of the ICP process chamber to supply plasma to the process volume, and pulsing the ICP RF powers or pulsing the auxiliary RF power with a power controller, at least in part, in response to a process being performed by the ICP process chamber.
Exemplary semiconductor processing methods may include providing an etchant precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. A layer of material may be disposed on the substrate. The methods may include directing an ultraviolet (UV) light source into the processing region. The methods may include contacting the layer of material with the etchant precursor. The contacting may etch the layer of material.
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/3065 - Gravure par plasmaGravure au moyen d'ions réactifs
Embodiments described herein relate to an apparatus that includes a laser configured to emit a laser beam, and an optics module optically coupled to the laser. In an embodiment, the optics module includes an optical element configured to split the laser beam into a plurality of split beams. In an embodiment, the apparatus further includes a plurality of optical fibers, where each of the plurality of optical fibers is configured to receive a corresponding one of the plurality of split beams.
G01N 21/39 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant des lasers à longueur d'onde réglable
G01N 21/25 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes
G01N 21/3504 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge pour l'analyse des gaz, p. ex. analyse de mélanges de gaz
G01J 3/02 - SpectrométrieSpectrophotométrieMonochromateursMesure de la couleur Parties constitutives
G01J 3/18 - Production du spectreMonochromateurs en utilisant des éléments diffractants, p. ex. réseaux
82.
MICROWAVE ANNEALING FOR LOW-TEMPERATURE HIGH-POWER APPLICATIONS
A system includes a support base comprising a conductive material, where the support base is to support an activation region. The system further includes a microwave annealing chamber, configured to perform a microwave annealing operation on the activation region supported by the support base to activate the activation region. The support base is disposed within a processing volume of the microwave annealing chamber.
Embodiments described herein generally relate to semiconductor device fabrication. More specifically, embodiments of the present disclosure relate to methods of removing metal oxides during semiconductor device manufacturing. The method includes performing a first soak process on the semiconductor device structure, forming a metal fill material in at least one feature, and performing a second soak process on the semiconductor device structure. The semiconductor device structure includes at least one feature formed in a dielectric layer of the semiconductor device structure. The first soak process includes flowing a first precursor gas over the at least one feature. The metal fill material is formed by partially filling the at least one feature where a gap region forms between a sidewall of the at least one feature and the metal fill material. The second soak process includes flowing a second precursor gas over the at least one feature and the metal fill material.
A radiation sensing device that includes (a) a readout circuit that includes a first readout capacitor and a second readout capacitor, and (b) a pixel that includes: (i) a radiation sensing element that is configured to convert radiation that impinges on the radiation sensing element to radiation indicative charge; (ii) a floating diffusion branch that includes a floating diffusion region, a floating diffusion reset switch, and a floating diffusion branch output circuit; (iii) a capacitor branch that includes a capacitor branch switch, a capacitor, a capacitor reset switch and a capacitor branch output circuit; wherein a capacitance of the capacitor exceeds a capacitance of the floating diffusion region; and (iv) an input transfer gate that is configured to couple the radiation sensing element to at least one of the capacitor branch and the floating diffusion branch.
H10F 30/00 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs
H10F 39/15 - Capteurs d’images à couplage de charge [CCD]
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
Embodiments described herein relate to an apparatus that includes a stepper motor, a driver chip communicatively coupled to the stepper motor, an encoder communicatively coupled to the stepper motor, and a feedback controller communicatively coupled to the driver chip and the encoder. In an embodiment, the feedback controller includes a state space plant configured to receive a control signal and generate a vector including a position and velocity of the stepper motor. In an embodiment, the feedback controller further includes a pulse width modulation (PWM) converter configured to receive the vector and output a first PWM signal corresponding to a number of steps to drive the stepper motor and a second PWM signal corresponding to a direction of the number of steps of the stepper motor. In an embodiment, the feedback controller further includes a Luenberger observer configured to receive a feedback signal from the encoder.
Embodiments of the present disclosure relate to compositions and methods for forming metal films. In at least some embodiment, a composition of matter includes a metal-hydride precursor represented by a general formula (I), a general formula (II), or oligomers thereof, where M is a trivalent metal and each of R1, R2, R3, R3', R4, and R4'12012012012012012020 substituted alkynyl group, a trialkylsilyl group, a substituted aromatic group, an unsubstituted aromatic group, a non-metal atom, a non-metal group, or combinations thereof.
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
C23C 16/18 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir de composés organométalliques
C23C 16/08 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le dépôt d'un matériau métallique à partir d'halogénures métalliques
Embodiments of the present disclosure generally relate to multi-temperature methods of forming semiconductor devices. In one or more embodiments, the methods form silicon and silicon germanium superlattice structures. In one or more embodiments, a method of forming a semiconductor device includes forming a first semiconductor layer using a first temperature. The first semiconductor layer has a first composition. The method includes forming a second semiconductor layer using a second temperature. The second temperature is a ratio of the first temperature and the ratio is at least 1.05, and the second semiconductor layer has a second composition different than the first composition.
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
88.
HEAT DISSIPATION METHODS AND STRUCTURES FOR SEMICONDUCTOR DEVICES
A method of increasing thermal uniformity of a substrate incorporates high thermal conductivity material in place of shallow trench isolation (STI) dielectric material or interlayer dielectric (ILD) material on a backside of a thinned substrate. The method may comprise removing at least a portion of an STI dielectric material and/or ILD material and depositing a second dielectric material in place of the STI dielectric material that is removed. The second dielectric material has a higher thermal conductivity than the STI dielectric material. The removal may incorporate a wet or dry etch process that is selective to the STI dielectric material and/or the ILD material over other materials used in formation of semiconductor structures on a substrate.
Gate-all-around (GAA) transistor devices and methods for forming GAA transistor devices are provided. The method includes forming a sacrificial capping layer over a source/drain cavity, the source/drain cavity defined by a pair of opposing sidewalls, the sidewalls each defined by alternating pairs of a first semiconductor layer and a second semiconductor layer, the sacrificial capping layer defining an air gap in between the opposing sidewalls and at least a portion of the sacrificial capping layer covers the air gap. The method further includes performing a replacement metal gate process and removing the sacrificial capping layer to expose the source/drain cavity, wherein the sacrificial capping layer keeps the source/drain cavity free from deposition during the replacement metal gate process.
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
90.
GRAYSCALE PATTERNING OF HYBRID PLASMONIC-ORGANIC WAVEGUIDES
Embodiments disclosed herein include methods of fabricating a photonic packaged device. More particularly, the embodiments provide techniques for fabricating bump fields and waveguides on a substrate. In an embodiment, a method is provided and includes depositing a metal seed layer on a substrate having one or more vias formed therein, depositing a patterned cladding layer, depositing a core material layer over the patterned cladding layer, and defining a first pattern and a second pattern in the core material layer in a single lithography operation. Portions of the core material layer are removed to form one or more bump fields and a conductive layer is deposited to form one or more bumps in each of the one or more bump fields. Portions of the core material layer according to the first pattern may then be removed to form hybrid plasmonic waveguides on the substrate.
Described herein is an alloy composition including aluminum and one or more additional elements including at least one of silicon, magnesium, iron, manganese, zinc, or titanium. The alloy composition is substantially free of at least one of chromium or copper.
C22C 21/08 - Alliages à base d'aluminium avec le magnésium comme second constituant majeur avec du silicium
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
92.
PLASMA PROCESSING SYSTEM CONFIGURED TO DELIVER A PULSED VOLTAGE WAVEFORM
Embodiments of plasma processing systems are provided. The plasma processing systems include a junction box enclosure electrically coupling a pulsed voltage source to a direct current conductor that is coupled to a substrate support and further electrically coupling the pulsed voltage source to a radio frequency conductor coupled to the radio frequency baseplate. The junction box enclosure includes a pulsed voltage filter circuit coupled between the radio frequency source and the radio frequency conductor, the pulsed voltage filter circuit operable to filter the pulsed voltage waveform. The junction box enclosure includes a radio frequency filter circuit coupled between the pulsed voltage source and the direct current conductor. The junction box enclosure includes a blocking capacitor coupled between the pulsed voltage source and the radio frequency filter circuit. The junction box enclosure includes one or more electrical components coupled between the direct current conductor and the radio frequency conductor.
The present disclosure provides a substrate processing chamber configured to produce an inductively coupled plasma. In one example, the substrate processing chamber includes a chamber body, a substrate support assembly disposed within the chamber body, a lid assembly enclosing a processing region within the chamber body, the lid assembly comprising an inductive coil configured to generate a plasma within the processing region of the chamber body, at least one magnet coupled to a magnet power source, and at least one electrode circumferentially extending along a perimeter of the chamber body. The at least one electrode is positioned below a metal lid support ring and above the at least one magnet.
The present disclosure generally provides methods of forming contact structures on semiconductor substrates. A metal layer is formed on a surface of a contact structure by maintaining a first temperature of a substrate and providing a first carrier gas, a first metal-containing precursor, and a first hydrogen-containing precursor to a first deposition chamber. The contact structure includes a feature. The feature includes an opening with a bottom surface and sidewalls, which comprise a dielectric material. The metal layer is formed over the sidewalls and the bottom surface and the metal layer comprises a metal and a silicon containing material. The metal layer is exposed to a metal chloride containing precursor to remove a top portion of the metal layer from the sidewalls. A metal gap fill material is deposited over the metal layer to fill the feature formed in the surface of the semiconductor substrate.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
Embodiments described herein relate to an apparatus that includes a stepper motor, a driver chip communicatively coupled to the stepper motor, an encoder communicatively coupled to the stepper motor, and a feedback controller communicatively coupled to the driver chip and the encoder. In an embodiment, the feedback controller includes a state space plant configured to receive a control signal and generate a vector including a position and velocity of the stepper motor. In an embodiment, the feedback controller further includes a pulse width modulation (PWM) converter configured to receive the vector and output a first PWM signal corresponding to a number of steps to drive the stepper motor and a second PWM signal corresponding to a direction of the number of steps of the stepper motor. In an embodiment, the feedback controller further includes a Luenberger observer configured to receive a feedback signal from the encoder.
Embodiments of the present disclosure generally relate to non-plasma methods of processing a substrate. More specifically, the methods disclosed herein incorporate microwave oxidation that is used to selectively etch materials during semiconductor device manufacturing. The method for etching a semiconductor device structure is disclosed includes performing a microwave oxidation etch process on the semiconductor device structure, wherein a hard mask is disposed over at least a portion of the semiconductor device structure. The microwave oxidation etch process includes flowing a first process gas over the semiconductor device structure and delivering a microwave energy to the first process gas without generating a plasma. The method further includes performing a preclean process on the semiconductor device structure. The preclean process includes flowing a second process gas over the semiconductor device structure.
A system configured to, in response to an occurrence of a corrective maintenance event, obtain first sensor data pertaining to a first process run and second sensor data pertaining to a second process run. Responsive to determining that a comparison of the first sensor data and the second sensor data fails to satisfy a first threshold criterion, the system generates a first normalized dataset based on the first sensor data and a second normalized dataset based on the second sensor data. The system then generates trace matching data by performing a trace matching operation on the first normalized dataset and the second normalized dataset. Responsive to determining that the trace matching data satisfies a second threshold criterion, the system identifies a set of sensors associated with the first sensor data as the cause of the fault that triggered the corrective maintenance event.
Conditions at the perimeter of the wafer may be characterized and and used to adjust current stolen by the weir thief electrodes during a plating process to generate more uniform film thicknesses. An electrode may be positioned in a plating chamber near the periphery of the wafer as the wafer rotates. To characterize the electrical contacts on the seal, a wafer with a seed layer may be loaded into the plating chamber, and a constant current may be driven through the electrode into the conductive layer on the wafer. As an electrical characteristic of this current varies, such as a voltage required to drive a constant current, a mapping characterizing the seal quality or the openings in the mask layer may be generated.
A processing chamber and port adaptor are provided. Processing chambers include a chamber body having a lid coupled to the first end of the chamber body, a gas ring adjacent the first end of the chamber body, and a substrate support, where a processing region is defined between the substrate support and the lid. The processing chamber includes a port adapter coupled to the second end of the chamber body. The port adapter includes a body defining a plurality of apertures in fluid communication with the processing region, where each of the apertures are spaced apart along the body such that a distance between adjacent apertures is within about 20% of an average aperture spacing distance, an individually controllable valve fluidly coupled to one or more of the plurality of apertures, and an exhaust system in fluid communication with a system foreline and the plurality of apertures.
H01J 37/32 - Tubes à décharge en atmosphère gazeuse
C23C 16/44 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement
C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
