An active discharge method is executed during a discharge period after inputting a discharge instruction signal instructing discharge of a bus capacitor. The active discharge method is a method of generating a first PWM signal having a discharge switching frequency different from a normal switching frequency, and a second PWM signal that is a complementary signal to the first PWM signal, for a gate driver for a high side and a gate driver for a low side.
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
B60L 50/60 - Propulsion électrique par source d'énergie intérieure au véhicule utilisant de la puissance de propulsion fournie par des batteries ou des piles à combustible utilisant de l'énergie fournie par des batteries
B60L 53/22 - Détails de structure ou aménagements des convertisseurs de charge spécialement adaptés pour recharger des véhicules électriques
B60L 58/10 - Procédés ou agencements de circuits pour surveiller ou commander des batteries ou des piles à combustible, spécialement adaptés pour des véhicules électriques pour la surveillance et la commande des batteries
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
2.
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE
A semiconductor device capable of stabilizing the output voltage of a linear regulator even when there are variations in operating conditions or load conditions. The linear regulator steps down a primary power supply voltage to a secondary voltage and outputs the secondary voltage. The variable resistor is connected in series with the power supply line with respect to the output voltage of the linear regulator. The ADC detects a voltage corresponding to the output voltage of the linear regulator. The control circuit controls the resistance value of the variable resistor based on the detected output voltage.
G05F 1/565 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance
G05F 1/63 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée est indifféremment du type alternatif ou continu utilisant des impédances variables en série avec la charge comme dispositifs de réglage final
3.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An interlayer insulating film having an upper portion and a lower portion is formed on a first main surface of a semiconductor substrate. Furthermore, a contact hole penetrating the interlayer insulating film is formed, and a contact member is formed in the contact hole. In the cross-sectional view, the width of the contact hole in a first direction is wider at an upper end than at a lower end of the contact hole, and is wider at a depth corresponding to the upper portion of the interlayer insulating film than at a depth corresponding to the lower portion of the interlayer insulating film.
A manufacturing method of a semiconductor device includes preparing a semiconductor substrate having an upper surface and a lower surface, forming a first mask having a plurality of openings on the upper surface divided into a first region and a second region, forming a second mask that exposes a portion of the first mask arranged in the first region and covers a portion arranged in the second region, etching the semiconductor substrate in the first region using the first mask and the second mask as a mask, removing the second mask, and etching the semiconductor substrate in the first region and the second region using the first mask as a mask.
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
A semiconductor device has an IGBT (Insulated Gate Bipolar Transistor) and includes a trench gate arranged in a semiconductor substrate, a trench emitter arranged parallel to the gate trench in plan view of the semiconductor substrate, and a contact electrode arranged parallel to the trench emitter in plan view of the semiconductor substrate. The contact electrode protrudes towards the trench emitter in plan view of the semiconductor substrate and has a protruding part connected to the trench emitter.
A semiconductor device includes a semiconductor substrate including a p-type semiconductor and an n-type semiconductor region arranged on the p-type semiconductor region; a first pattern overlapping the n-type semiconductor region in plan view and formed over the semiconductor substrate; and a second pattern overlapping the first pattern in plan view and magnetically or capacitively coupled to the first pattern.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
In a contact hole, a first side surface of an interlayer insulating film is separated from a second side surface of a first conductive film so that a part of an upper surface of the first conductive film is exposed from the interlayer insulating film. In the contact hole, a third side surface of an insulating film is separated from the second side surface of the first conductive film so that a part of the lower surface of the first conductive film is exposed from the insulating film. A plug includes a silicide layer formed on the second side surface of the first conductive film, a barrier metal film formed on the silicide layer, and a second conductive film formed on the barrier metal film.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H01L 21/263 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée
H01L 21/3205 - Dépôt de couches non isolantes, p. ex. conductrices ou résistives, sur des couches isolantesPost-traitement de ces couches
Even when the processing result at a certain layer in a convolutional neural network is input to the next layer and further subsequent layers, the processing can be executed more appropriately. A subnetwork included in a convolutional neural network includes a first layer, a second layer, a third layer, and a fourth layer, the output of the first layer is input to the second layer, the output of the second layer is input to the third layer, and the output of the first layer and the output of the third layer are input to the fourth layer, the acquisition unit divides and acquires the data to be processed so that the total size of the input data to each layer is equal to or less than the storage capacity of the internal memory.
A field plate electrode configured from a first conductive film is formed in a trench. The field plate electrode is recessed. A first insulation film in the trench is recessed. A gate insulation film is formed in the trench and, simultaneously, a second insulation film is formed so as to cover the field plate electrode. A gate electrode configured from a second conductive film is formed in the trench. A portion of the gate electrode covering a drawer portion, which is a part of the field plate electrode via the second insulation film, is selectively removed.
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
10.
INFORMATION PROCESSING DEVICE, METHOD, AND PROGRAM
An information processing device is provided to quantitatively visualize the progress of execution of a program containing multiple instructions. The processor of the information processing device, when executing the control program instructions, causes the information processing device to perform operations. This operation includes collecting output data outputted with the execution of multiple instructions contained in a program when the program containing multiple instructions is executed, determining the progress of execution of the program containing multiple instructions based on the amount of the collected output data since the execution of the program containing multiple instructions began, and providing a user interface including an object representing the determined progress for display.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/451 - Dispositions d’exécution pour interfaces utilisateur
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
11.
HIGH-SIDE DEVICE CONTROL IN PHASE SHIFT FULL BRIDGE DC/DC CONVERTER
Gate drivers, systems and methods are described. A gate driver can include a comparator configured to detect a zero voltage switching (ZVS) event of a high-side (HS) switching device and in response to detection of the ZVS event, generate an ON signal to turn on the HS switching device. The gate driver can further include a timing circuit configured to an OFF signal to turn off the HS switching device, wherein generation of the OFF signal is based on a predefined fixed ON time of the HS switching device.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
12.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate into which a first impurity of an n-type is introduced, an epitaxial layer formed on the semiconductor substrate and into which a second impurity of the n-type is introduced, and a semiconductor region of the n-type formed in a portion of the epitaxial layer located under the first portion, into which a third impurity of the n-type is introduced and which has an impurity concentration higher than an impurity concentration of the epitaxial layer.
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A semiconductor device configured to suppress increase in power consumption increased by temperature increase is provided. A logic circuit has characteristics in which a lower limit voltage achieving operations is decreased by temperature increase. A reference voltage generation circuit generates a reference voltage based on a negative coefficient voltage Vpn2 decreased by temperature increase. A voltage regulator circuit generates a power supply voltage based on the reference voltage. A power supply voltage maintenance circuit suppresses decrease in the reference voltage decreased by temperature increase, before the power supply voltage is made lower than a lower limit voltage by temperature increase.
A semiconductor device includes a semiconductor substrate, a sealing ring, and at least one routing wiring. The semiconductor substrate has a peripheral region in plan view. The sealing ring is formed on the peripheral region. The sealing ring includes a plurality of conductors and a plurality of first plugs. Each of the plurality of conductors is laminated along a thickness direction of the semiconductor substrate and extends along the peripheral region in plan view. Each of the plurality of conductors has an outer edge and an inner edge in plan view. The plurality of conductors includes a first conductor located at the uppermost layer and a plurality of second conductors located below the first conductor. The outer edge of the first conductor is positioned outside any of outer edges of each of the plurality of second conductors.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
A tracking filter includes an extraction multiplier, a low-pass filter, and a restoration multiplier. The extraction multiplier multiplies a tracking input signal by a cosine wave signal or a sine wave signal having a tracking frequency. The restoration multiplier generates a tracking output signal by multiplying an output signal of the low-pass filter by the cosine wave signal or the sine wave signal having the tracking frequency. The monitoring circuit detects an AC component included in the output signal of the low-pass filter, and determines whether or not the tracking filter is abnormal on the basis of a magnitude thereof.
H02P 27/08 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p. ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions
H02P 21/05 - Dispositions ou procédés pour la commande de machines électriques par commande par vecteur, p. ex. par commande de l’orientation du champ spécialement adaptés pour amortir les oscillations des moteurs, p. ex. pour la réduction du pompage
H02P 21/13 - Commande par observateurs, p. ex. en utilisant des observateurs de Luenberger ou des filtres de Kalman
H02P 21/22 - Commande du courant, p. ex. en utilisant une boucle de commande
A semiconductor device capable of suppressing an increase in chip area due to the widening of a conductor located on the topmost layer of a sealing ring is provided. The semiconductor device includes a semiconductor substrate and the sealing ring. The sealing ring is formed on a periphery of the semiconductor substrate in a plan view. The sealing ring includes a plurality of conductors stacked on each other. Each of the plurality of conductors has an inner peripheral edge and an outer peripheral edge. An inner peripheral edge of a first conductor, which is located on the topmost layer of the plurality of conductors, is positioned more inward than any of inner peripheral edges of a plurality of second conductors located below the first conductor in a plan view.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
A semiconductor device includes a semiconductor substrate having an upper surface, a first source layer formed in the semiconductor substrate and disposed at the upper surface, a first drain layer formed in the semiconductor substrate and disposed at the upper surface so as to be spaced apart from the first source layer in a first direction, a first drain insulating film formed at the upper surface and located between the first source layer and the first drain layer in the first direction, a first gate insulating film formed on the upper surface and located between the first drain insulating film and the first source layer in the first direction, and a first gate electrode formed on the first gate insulating film and on the first drain insulating film.
A semiconductor device includes a plurality of bonding pads which are constituted by an uppermost layer of a wiring layers, first and third bonding pads connected to an external power supply of the semiconductor chip, second and fourth bonding pads connected to the ground, a fifth bonding pad connected to the third bonding pad via the first inner wiring, and a sixth bonding pad connected to the fourth bonding pad via the second inner wiring, wherein there is no wiring constituting a circuit in one layer just below the uppermost layer at the first and second bonding pads, and there is a wiring constituting the circuit in the one layer just below the uppermost layer at the third to sixth bonding pads.
A semiconductor device includes a selection transistor having a first paraelectric film, a ferroelectric film, a metal film, and a selection gate electrode that are formed on a semiconductor substrate in order, and a memory transistor having a second paraelectric film, the ferroelectric film, the metal film, and a memory gate electrode that are formed on the semiconductor substrate in order. A thickness of the first paraelectric film is larger than a thickness of the second paraelectric film. Each of the first and second paraelectric films contains nitrogen, and a nitrogen concentration in the first paraelectric film decreases toward a lower surface of the first paraelectric film from an upper surface of the first paraelectric film.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
A semiconductor device capable of operating a content addressable memory at higher speed is provided. The semiconductor device 1 includes a memory array 4 with a master block 2 storing a first portion of a bit string constituting data entries, and a slave block 3 storing the remaining second portion of the bit string, and a search unit 21 included in the master block 2 to determine a match between a portion corresponding to the first portion of the search data and any of the first portions of the data entries. Master block 2 controls to activate the slave block 3 in response to the start of determination by the search unit 21, and controls to continue the activation or inactivate the slave block 3 according to the result of the determination by the search unit 21.
G11C 15/04 - Mémoires numériques dans lesquelles l'information, comportant une ou plusieurs parties caractéristiques, est écrite dans la mémoire et dans lesquelles l'information est lue au moyen de la recherche de l'une ou plusieurs de ces parties caractéristiques, c.-à-d. mémoires associatives ou mémoires adressables par leur contenu utilisant des éléments semi-conducteurs
A semiconductor device includes a wiring substrate having an upper surface, a semiconductor chip mounted on the wiring substrate, and a stiffener ring fixed onto the wiring substrate via a plurality of adhesive layers. The upper surface is a quadrangular shape, and first and second center lines and first and second diagonal lines can be drawn. The stiffener ring has four extension portions and four corner portions. Adhesive layers include first, second, third and fourth adhesive layers that respectively overlap with the four extension portions and that are arranged at a portion overlapping with one of the first center line and the second center line. Also the adhesive layers include fifth, sixth, seventh, and eighth adhesive layers that respectively overlap with the four corner portions and that are arranged at a portion overlapping with one of the first diagonal line and the second diagonal line.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/16 - Matériaux de remplissage ou pièces auxiliaires dans le conteneur, p. ex. anneaux de centrage
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
22.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A gate electrode is formed inside a trench via a gate insulating film. The gate insulating film formed on a semiconductor substrate is removed. An insulating film is formed on the semiconductor substrate. A p-type base region is formed in the semiconductor substrate. An n-type emitter region is formed in the base region. Hydrogen annealing process is performed to the semiconductor substrate. A boundary between the base region and the emitter region is located at a position deeper than the insulating film formed between a side surface of the trench and the gate insulating film.
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
23.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an insulating layer (IFL) on a semiconductor substrate (SUB), a conductive film (PL) on the insulating layer (IFL), an interlayer insulating film (IL) covering the conductive film (PL), a contact hole (CH1) in the interlayer insulating film (IL), the conductive film (PL) and the insulating layer (IFL), and a plug (PG1) embedded in the contact hole (CH1). A side surface of the interlayer insulating film (IL) is separated from a side surface of the conductive film (PL) to expose a part of an upper surface of the conductive film (PL), and a side surface of the insulating layer (IFL) is separated from the side surface of the conductive film (PL) to expose a part of a lower surface of the conductive film (PL). A distance (L1) from the lower surface of the conductive film (PL) to the bottom of the contact hole (CH1) is longer than a distance (L2) from the side surface of the conductive film (PL) to the side surface of the interlayer insulating film (IL).
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
24.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type source region and an n-type drain region ND1 are formed in a semiconductor substrate. A gate electrode is formed via a gate insulating film on a portion of the semiconductor substrate located between the source region and the drain region. A p-type impurity region is: formed in a portion of the semiconductor substrate located under the drain region, under the gate electrode, and under the source region. An impurity concentration of the impurity region is higher than an impurity concentration of the semiconductor substrate. The impurity region is spaced apart from an upper surface of the semiconductor substrate.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
In inverter control of a motor, an inverter control method is provided that increases system efficiency in all speed ranges from low speed to high speed based on system efficiency. Specifically, the inverter control method of switching between overmodulation control and rectangular wave control, especially in the medium to high-speed range is provided, with taking system efficiency into consideration.
A read assist circuit is configured so as to be capable of switching validation/invalidation, and lowers a word line voltage applied to a word line in order to secure a static noise margin of a memory cell when being valid. An SNM detection circuit has a replica memory cell configured so as to make data retention ability lower than that of memory cell. The SNM detection circuit detects the static noise margin of the memory cell in a pseudo manner by using the replica memory and cell, switches the validation/invalidation of the read assist circuit depending on a detection result.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
27.
SEMICONDUCTOR DEVICE, MOTOR CONTROL SYSTEMS AND MOTOR CONTROL METHODS
In a method where a controller controls a motor via a semiconductor device, reduce power consumption while ensuring control accuracy. In the semiconductor device, the remaining step number control circuit obtains the first remaining step number by subtracting the number of steps that could be processed for FB (feedback) signal generation between the first CTE (carrier period event) and the next second CTE from the first next step number at the time of the first CTE occurrence. The total step number control circuit obtains the second total step number by adding the second next step number and the first remaining step number at the time of the second CTE occurrence. The output circuit generates the FB signal based on the second total step number.
A second semiconductor chip is mounted on a second die pad, and a first semiconductor chip and a third semiconductor chip are mounted on a first die pad spaced apart from the second die pad in a Y direction. The third semiconductor chip includes a transformer and is adjacent to the first semiconductor chip in an X direction. In plan view, a third side of the third semiconductor chip faces a first side of the first semiconductor chip, and a fourth side of the third semiconductor chip opposite the third side faces the second side of the second semiconductor chip. The first semiconductor chip and the third semiconductor chip are electrically connected with each other via a plurality of first wires. The second semiconductor chip and the third semiconductor chip are electrically connected with each other via a plurality of second wires.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A method of manufacturing a semiconductor device according to the present disclosure includes: stacking a WSi layer and a TEOS layer on a surface of a P-type polysilicon layer formed on an SiC substrate; patterning the stacked WSi layer and TEOS layer so as to leave a second stacked region corresponding to an anode of the temperature detection diode; performing a first mask process so that, on a surface of the p-type polysilicon layer, a first region corresponding to a cathode of the temperature detection diode is exposed; implanting n-type ions into the first region; performing a second mask process so that, on the surface of the p-type polysilicon layer, a formation region of the temperature detection diode is masked; and performing etching on an exposed polysilicon layer.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
Control the period during which voltage is applied to the drain to provide a reservoir computer with low power consumption. A reservoir computer is provided, comprising an FeFET with a drain connected to a sense circuit that applies a drain voltage and detects the drain current by converting it from analog to digital. The gate electrode is connected to a gate voltage generation circuit that inputs a gate voltage in the form of a triangular wave with peaks of positive and negative voltages. Additionally, it includes a first switch positioned between the sense circuit and the drain. The gate voltage generation circuit comprises a charge pump circuit for applying positive voltage, a charge pump circuit for applying negative voltage, a pulse generation circuit, and a Vref regulator.
A position of an upper surface of a lead-out portion of a gate electrode is higher than an upper surface of an active portion of the gate electrode. An insulating film has a first raised portion positioned on a side surface of the active portion of the gate electrode via a sidewall spacer and a second raised portion positioned on a side surface of the lead-out portion of the gate electrode via the sidewall spacer. An active portion of a field plate electrode is in contact with the first raised portion, and a position of an uppermost portion of the lead-out portion of the field plate electrode is lower than a position of an uppermost portion of the insulating film positioned over the upper surface of the lead-out portion of the gate electrode.
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
A clamp element 46 applies a fixed potential to a bit line BL at a time of a readout operation. A reference current source RCS generates a reference current Iref. An offset current source OCS1 is activated at a time of a readout operation for an OTP cell OTPC, and at a time of being activated, generates an offset current Iof1 to be subtracted from a cell current Icel. At the time of the readout operation for the OTP cell OTPC, the sense amplifier SA detects a magnitude relationship between the reference current Iref and a readout current Ird obtained by subtracting the offset current Iof1 from the cell current Icel.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
A semiconductor device comprising an n-type epitaxial layer, a plurality of p-type column regions formed in the epitaxial layer so as to be spaced apart from each other in a plan view, and a gate electrode formed between each of the plurality of p-type column regions. The plurality of p-type column region is formed in the epitaxial layer and is composed of first, second and third sub-column regions, which are arranged in order from the side closer to a main surface of the epitaxial layer EP. Additionally, a distance between a position of a maximum impurity concentration of the first sub-column region and a position of a maximum impurity concentration of the second sub-column region is smaller than a distance between the position of the maximum impurity concentration of the second sub-column region and a position of a maximum impurity concentration of the third sub-column region.
Semiconductor devices, systems and methods are described. A semiconductor device can include a driver configured to output a gate current to drive a power module. The semiconductor device can further include a buffer configured to buffer a reference voltage that is less than a supply voltage being provided to the driver. The semiconductor device can further include a controller configured to determine a gate voltage of the power module is equivalent to the reference voltage. The controller can, in response to determination that the gate voltage is equivalent to the reference voltage, disable the driver to cause the driver to stop providing the gate current to the power module and enable the buffer to supply the reference voltage to the power module.
H03K 17/30 - Modifications pour fournir un seuil prédéterminé avant commutation
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
35.
PROGRAMMABLE GATE VOLTAGE FOR ON RESISTANCE CONTROL OF POWER MODULE
Semiconductor devices, systems and methods are described. A semiconductor device can include a driver configured to output a gate current to drive a power module. The semiconductor device can further include a buffer configured to buffer a reference voltage that is less than a supply voltage being provided to the driver. The semiconductor device can further include a controller configured to determine a gate voltage of the power module is equivalent to the reference voltage. The controller can, in response to determination that the gate voltage is equivalent to the reference voltage, disable the driver to cause the driver to stop providing the gate current to the power module and enable the buffer to supply the reference voltage to the power module.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
36.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A built-in resistor electrically connecting a trench gate electrode and a gate pad is formed of a conductive film formed on a semiconductor substrate via an insulating film. Here, a film thickness of the insulating film is larger than a film thickness of an insulating film in a trench and is smaller than an insulating film which is a field oxide film.
H10D 84/60 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors BJT
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
Provided is a wide band gap semiconductor device having high robustness against misalignment between gate electrodes (trenches) and a punch-through stopper layer. A technical concept is to configure the planar shape of the punch-through stopper layer from a pattern having periodicity in each of the X and Y directions constituting the plane, on the premise that the trenches extending in the Y direction out of the X direction and the Y direction constituting the plane are arranged at predetermined intervals in the X direction.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
38.
MANUFACTURING METHOD OF A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR WAFER
A semiconductor device capable of controlling the warpage of a semiconductor wafer is provided. A semiconductor wafer is provided in which a first semiconductor chip with a first trench arranged in a first direction and a second semiconductor chip with a second trench arranged in a second direction different from the first direction are alternately arranged laterally. In the semiconductor wafer, it is possible that a first semiconductor chip with a first trench arranged in a first direction and a second semiconductor chip with a second trench arranged in a second direction different from the first direction are alternately arranged longitudinally.
A semiconductor device includes a central processing unit (CPU), a memory, a test data input terminal that receive test data, a test group identification terminal that receive a test group identification signal, a test data input control unit that receives the test group identification signal through the test group identification terminal and generates a memory write enable signal for allowing the test data to be written into the memory based on the test group identification signal, and a memory write control circuit that generates test data write address and selects the test data received through the test data input terminal based on the memory write enable signal to transfer the test data selected and the test data write address to the memory, whereby a test with the test data in the memory is executed.
An information processing device is provided that synchronizes the progress of data transferring unit with the timing of processing by calculation processing unit. The information processing device comprises an external bus connecting unit for connecting data transferring unit, a local memory, and a command list processing unit to the external memory, the data transferring unit for transferring data, which are conditions for calculation stored in the external memory, to the local memory, the local memory for storing data and a list of commands, the command list processing unit for generating commands that cause the calculation processing unit to execute calculations, by reading the list of commands from the local memory while data is being transferred from the external memory to the local memory, and the calculation processing unit for executing calculations and processing data.
A semiconductor device includes an offset drain region and a p-type well. In a gate length direction of a gate electrode, a first distance between the offset drain region and a first portion of the p-type well is larger than a second distance between the offset drain region and a second portion of the p-type well. The semiconductor device includes an n-type semiconductor region formed in a portion of an epitaxial layer located between the offset drain region and a source region.
A semiconductor device has an interlayer insulation film made of antiferroelectric. The minimum value of a relative dielectric constant of the interlayer insulation film is less than 2.
A semiconductor device is provided. The semiconductor devices is connected to a power device. The semiconductor device includes a gate driver unit with a first circuit and a second circuit, a resistor unit connecting the gate of the power device and the gate driver unit, and a first control circuit connected to the gate driver unit. The first control circuit is configured to increase the resistance of the power device by issuing an instruction to reduce the slew rate of the power device to the first circuit during the turn-off of the power device.
The current control circuit switches the cutting control transistor to the on state with respect to the AND circuit, passing a current of a first current value through the electrical fuse, and using the heat generated by passing the first current value through the electrical fuse to start melting the cutting region of the electrical fuse; the current detection circuit detects a second current value that is smaller than the first current value and greater than 0 amperes; the current detection circuit outputs a low current detection signal to the detection signal processing circuit based on detecting the second current value; the detection signal processing circuit outputs a control signal to the AND circuit based on the low current detection signal, and the AND circuit switches the cutting control transistor to the off state based on the control signal, performing the cutting of the electrical fuse.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
45.
SEMICONDUCTOR DEVICE, BOOT PROGRAM EXECUTION METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM
A semiconductor device 1 includes a CPU 11, a DMA controller 12, a first memory 13, and a second memory 14. The CPU 11 executes an initialization program in the first memory 13 to write an interrupt program and interrupt jump instructions into the second memory 14. The DMA controller 12 starts a DMA transfer process of a boot program to the second memory 14 by overwriting the interrupt jump instructions. The CPU 11 starts an execution process of the boot program after a predetermined time has elapsed since a start of the DMA transfer process. The CPU 11 executes the interrupt jump instruction when an instruction execution address reaches an address of a DMA untransferred area. The CPU 11 executes the interrupt program at a jump destination to delay the execution process of the boot program.
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
46.
WIRING METHOD FOR SEMICONDUCTOR CIRCUIT DEVICE, WIRING PROGRAM AND WIRING PROCESSING DEVICE
A wiring method of the semiconductor circuit device includes arranging a plurality of shield wiring candidates such that the plurality of shield wiring candidates adjacent to each other are arranged apart by a space for a wiring track, arranging a shield target wiring on at least one of wiring tracks between the plurality of shield wiring candidates adjacent to each other, and removing a shield wiring candidate which do not contribute as shield wiring to the shield target wiring arranged.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
47.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGING AND INVERTER SYSTEMS
The semiconductor device includes first, second and third semiconductor chips. Through non-contact communication between different potentials in the third semiconductor chip, signal transmission and reception occur between the first and second semiconductor chips. The first semiconductor chip comprises a first semiconductor substrate and a first active element. The first semiconductor substrate has a first main surface. The first active element is formed on the first main surface. The second semiconductor chip comprises a second semiconductor substrate and a second active element. The second semiconductor substrate has a second main surface. The second active element is formed on the second main surface. The third semiconductor chip comprises a third semiconductor substrate and a passive element. The third semiconductor substrate has a third main surface. The passive element is formed above the third main surface. Each of the first, second and third semiconductor substrates is formed of monocrystalline silicon.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
48.
SEMICONDUCTOR TEST APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
To provide a semiconductor test apparatus capable of improving the conductivity between a probe pin and an external terminal of a semiconductor device while suppressing the breakage of the probe pin. The semiconductor test apparatus comprises a socket base, a probe guide, and the probe pin. The socket base has a first surface and a second surface opposite the first surface in a first direction. A first opening penetrating the socket base along the first direction is provided. The probe guide is movably disposed within the first opening along the first direction. The probe guide has a first end that protrudes from the first surface when moved from the second surface to the first surface along the first direction, and a second end opposite the first end. A second opening penetrating the probe guide along the first direction is provided.
A semiconductor device includes a semiconductor substrate including a single crystal layer, a plurality of semiconductor elements formed on the single crystal layer, and an isolation film which is formed in the semiconductor substrate so as to surround each of the plurality of semiconductor elements in plan view and isolates the plurality of semiconductor elements from one another. The isolation film is made of an antiferroelectric. A minimum value of a relative dielectric constant of the isolation film is less than 2.
A semiconductor device can enhance ranging accuracy while satisfying communication standards. The baseband circuit BBC, during transmission, divides the original pulse signal into multiple divided pulse signals so that each frequency bandwidth falls within the frequency bandwidth range specified by the UWB communication standard and overlaps a common frequency range, and sequentially transmits them to the receiving terminal via the analog front-end circuit AFE at a predetermined transmission interval. On the other hand, the baseband circuit BBC, during reception, inputs multiple divided pulse signals sequentially received with a predetermined time difference, corrects the time difference as if they were received simultaneously, and further corrects the phase of the multiple divided pulse signals to be continuous in the common frequency range. Then, the baseband circuit BBC restores the original pulse signal by synthesizing the corrected multiple divided pulse signals.
H04B 1/00 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission
51.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND PRODUCT HISTORY MANAGEMENT METHOD FOR SEMICONDUCTOR DEVICE
A technique that not only suppresses cost increase but also enables traceability of semiconductor devices with high accuracy is demanded. By mapping positions of crystal defects, position information of the crystal defects on a wafer map is stored in a memory device. In each of a plurality of chip areas, a metal film is formed in a wiring layer located above a semiconductor element. In each of the plurality of chip areas, a surface morphology image of a specific area of the metal film is acquired. The position information of the crystal defects on the wafer map, a wafer identification number, position information of the plurality of chip areas, position information of the specific area in the chip area, and the surface morphology image for each of the plurality of chip areas are linked and stored in a memory device.
According to one embodiment, the semiconductor device includes: a semiconductor module including a semiconductor chip having a first surface and a second surface; and a lattice-shaped fin close to the second surface side of the semiconductor chip. The lattice-shaped fin includes a first lattice-shaped body and a second lattice-shaped body, the first lattice-shaped body including a plurality of first bars each having a bar shape extending in a first direction, and being spaced from each other in an arrangement direction, thereby forming a plurality of first trenches between the adjacent first bars, and the second lattice-shaped body including a plurality of second bars each having a bar shape extending in a second direction, and being spaced from each other in the arrangement direction, thereby forming a plurality of second trenches between the adjacent second bars. The first lattice-shaped body and the second lattice-shaped body are stacked in a stack direction.
To provide a semiconductor device that can be miniaturized. The semiconductor device includes a power transistor H_PN, L_PN that supplies current to a load, a current detection circuit that detects the current flowing through the power transistor H_PN, L_PN, a first detection current H_DI1, L_DI1 based on the current detected by the current detection circuit, a device control circuit that controls the current flowing through the power transistor H_PN, L_PN based on an input signal Inp, an overrange comparison circuit that outputs an overrange signal H_OV, L_OV when the voltage of the power transistor H_PN, L_PN exceeds a predetermined voltage,, and an abnormal signal generation circuit that outputs an abnormal signal indicating an overcurrent state of the power transistor based on a second detection current H_DI2, L_DI2 detected by the current detection circuit and the overrange signal H_OV, L_OV.
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
54.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND PRODUCT HISTORY MANAGEMENT METHOD FOR SEMICONDUCTOR DEVICE
The technique capable of preventing cost increase and performing traceability of a semiconductor device with higher accuracy is demanded. In each of a plurality of chip regions, a multilayer wiring layer having a plurality of metal films in the uppermost-layer wiring layer is formed. In each of the plurality of chip regions, a surface morphology image of a specific area of the metal films is obtained. A wafer identification number, positional information of each of the plurality of chip regions, positional information of the specific area of each of the chip regions, and the surface morphology image for each of the plurality of chip regions are associated with one another, and these pieces of information are stored in the storage device.
A semiconductor device includes a memory array. In a plan view, the memory array has a memory cell region arranged at a center portion and dummy cell regions arranged at an outer circumferential portion. In the dummy cell regions, a dummy cell connected to a word line is arranged, the dummy cell has a transistor whose gate terminal is connected to the word line and to whose drain terminal a ground voltage is supplied. At a time of performing a reading operation of the memory cell, the transistor is made in a conductive state so that the ground voltage is supplied to the source lines.
An improved cell balancing is provided. Estimating a charge state of each battery cell at each time point based on a voltage of each cell coupled in series, calculating an integrated value of a current flowing through multiple battery cells during a period between each time point, estimating a maximum capacity of each battery cell based on its charge state at each time point and the integrated value of the current, determining a reference battery cell based on the maximum capacity and charge state of each battery cell, and discharging a battery cell other than the reference battery cell.
A semiconductor device includes a semiconductor substrate, a barrier metal layer, and a contact plug. The semiconductor substrate includes a metal silicide region. A contact trench is provided in the semiconductor substrate. The barrier metal layer is formed within the contact trench. The contact plug is formed on the barrier metal layer. The metal silicide region is in contact with the barrier metal layer and includes a first metal silicide region, a second metal silicide region, and a third metal silicide region. A first thickness of the first metal silicide region is smaller than a second thickness of the second metal silicide region and is smaller than a third thickness of the third metal silicide region.
After grinding a back surface of a semiconductor substrate SB such that a thickness of a central portion of the semiconductor substrate is less than a thickness of a peripheral portion of the semiconductor substrate, a metal film including a film made of silver or copper is formed on the back surface of the semiconductor substrate. Thereafter, a dicing tape is adhered to the back surface of the semiconductor substrate via the metal film. A base material layer of the dicing tape is made of polyvinyl chloride. Also, after separating the peripheral portion from the central portion and the dicing tape, the semiconductor substrate adhered to the dicing tape is diced. Thereafter, the semiconductor substrate adhered to the dicing tape is transported.
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
59.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A write driver writes one of binary data into an OTP memory cell using a boost voltage or a regulator voltage. An OTP voltage select register causes the write driver to select one of two voltages. The trimming registers hold voltage setting values defining magnitudes of two voltages, respectively. An OTP voltage trimming step is a step of sequentially changing the voltage setting values in a high voltage direction while writing is performed into a plurality of OTP memory cells one by one using one of the two voltage setting values as a trimming target, until writing with the same voltage setting value succeeds in succession writing with the same voltage setting value is successively successful in N OTP memory cells.
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11C 17/02 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main utilisant des éléments magnétiques ou inductifs
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
60.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a trench formed in a first main surface of a semiconductor chip, in which the trench has a portion extending in a first direction and a portion extending in a second direction different from the first direction in a continuous manner in plan view. The trench has a portion extending in a third direction different from the first direction and the second direction, in which the portion extending in the third direction is located between the portion extending in the first direction and the portion extending in the second direction in plan view, the portion extending in the first direction intersects the portion extending in the third direction at an obtuse angle, and the portion extending in the second direction intersects the portion extending in the third direction at an obtuse angle.
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A design system is provided for enhancing the utilization rate of hardware accelerators during the execution of a video pipeline. The design system disclosed herein is for designing a video pipeline, which, based on a pipeline graph, job information related to multiple jobs included in the pipeline graph, hardware accelerator information related to multiple hardware accelerators included in the pipeline graph, and optimization conditions, creates a list of candidate combinations of the assignment of multiple jobs to multiple hardware accelerators, the execution order of multiple jobs, and the execution timing of each of the multiple jobs. It comprises an optimization unit that creates the list of candidate combinations and a result output unit that outputs the list of candidate combinations created by the optimization unit to the user.
A semiconductor device is provided, the semiconductor device comprises a first battery module and a second battery module connected in series, the first battery module comprising a first controlling portion controlling a first cell group where a plurality of battery cells are connected in series; and a controller communicating with a device driven when receiving a power supply from the first and second battery modules, the second battery module comprising a second controlling portion controlling a second cell group where a plurality of battery cells are connected in series; and a first measuring circuit measuring a difference in a consumed electrical amount between the first battery module and the second battery module, and discharge starts from the plurality of battery cells included in the second cell group, based on the difference in the consumed electrical amount measured by the first measuring circuit.
A semiconductor device includes a semiconductor substrate having a first surface where a source terminal and a gate electrode of a vertical transistor are formed, and a second surface where a drain terminal of the vertical transistor is formed; a bonding region formed on an upper surface of a region where the source terminal is formed on the first surface side, to which a bonding wire for supplying current to the source terminal is connected; and a plurality of recesses formed in a region on the second surface, at least including the region facing the first surface where the bonding region is formed. An extending direction of an outer peripheral side of an opening of the plurality of recesses is set in a direction mismatched with an extending direction of a side of an element pattern formed on the first surface.
A semiconductor device includes an application allocation judgement unit and an application allocation control unit. The application allocation judgement unit compares CPU usage rate data and CPU usage rate threshold pattern data, thereby predicting a state in which the CPU usage rate exceeds a threshold value and generating an application allocation change request. The application allocation control unit changes an allocation destination of an application allocated to the CPU predicting that the CPU usage rate exceeds the threshold value based on the application allocation change request.
A first region of a die pad of a semiconductor device includes: a third region having a surface facing a surface of a semiconductor chip via a die bond material; and a fourth region having a surface facing the surface of the semiconductor chip via a sealing body without interposing the die bond material between the die pad and the semiconductor chip. The die pad includes a convex portion provided in the third region and protruding from a flat surface including an upper surface of the die pad toward the semiconductor chip. The sealing body includes a plurality of filler particles. A part of the plurality of filler particles is interposed between the surface of the semiconductor chip and the upper surface, which is located in the fourth region, of the die pad.
A semiconductor device includes a controller that, in an element that connects a collector of an IGBT, a drain of a MOSFET, and a cathode of a diode and connects an emitter of the IGBT, a source of the MOSFET, and an anode of the diode, controls a first gate that is a gate of the IGBT and a second gate that is a gate of the MOSFET, in which the controller controls the first gate in a state where the second gate is turned on.
H03K 3/012 - Modifications du générateur pour améliorer le temps de réponse ou pour diminuer la consommation d'énergie
H02M 7/537 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur
H03K 17/567 - Circuits caractérisés par l'utilisation d'au moins deux types de dispositifs à semi-conducteurs, p. ex. BIMOS, dispositifs composites tels que IGBT
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
67.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film formed over the semiconductor substrate, a first wiring formed on the first interlayer dielectric film, a second interlayer dielectric film formed on the first interlayer dielectric film and including a first layer covering the first wiring and a second layer formed on the first layer, a first resistive film formed on the first layer and covered by the second layer, a first via plug formed in the first layer and electrically connecting the first wiring and the first resistive film, and a second via plug formed in the second interlayer dielectric film and electrically connected to the first wiring. The first resistive film contains silicon.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
68.
SIMULATION APPARATUS, SIMULATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM
A simulation apparatus includes a loop instruction sequence detector and an instruction computing section. The loop instruction sequence detector detects a loop instruction sequence included in a target program and generates a loop instruction sequence detection signal. When the loop instruction sequence detection signal is generated, the instruction computing section executes the loop instruction sequence once and generates a simulation elapsed time required for executing the loop instruction sequence a predetermined number of times.
A RAM stores a compensation value table in which a torque compensation value of each of discrete rotation angles that are discrete rotation angles of a motor is registered. A processor performs a step (a) of extracting a vibration component based on speed difference between a speed command value and a value of a rotation speed of the motor, and of calculating and deriving an update amount of each of the discrete rotation angles required for suppressing the vibration component. The processor further performs a step (b) of updating the compensation value table based on the update amount of each of the discrete rotation angles. The processor further performs a step (c) of calculating and deriving the torque compensation value of each any rotation angle of the motor by use of the compensation value table and a completion function, and of reflecting it to a motor control signal.
H02P 21/05 - Dispositions ou procédés pour la commande de machines électriques par commande par vecteur, p. ex. par commande de l’orientation du champ spécialement adaptés pour amortir les oscillations des moteurs, p. ex. pour la réduction du pompage
H02P 21/18 - Estimation de la position ou de la vitesse
H02P 21/22 - Commande du courant, p. ex. en utilisant une boucle de commande
H02P 27/12 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p. ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions appliquant des impulsions en guidant le vecteur-flux, le vecteur-courant, ou le vecteur-tension sur un cercle ou une courbe fermée, p. ex. pour commande directe du couple
70.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type impurity region is formed in a semiconductor substrate. A p-type well region and an n-type collector region are formed in the impurity region. An n-type emitter region and a p-type base region are formed in the well region. When a distance from a first junction surface to a second junction surface is Wb1, an impurity concentration of a part of the well region located under the first junction surface is Na1, a distance from a third junction surface to the base region is Wb2, and an impurity concentration of a part of the well region located between the third junction surface and the base region is Na2, the relationship (Na1×Wb1)≤(Na2×Wb2) is satisfied.
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
A method of manufacturing a semiconductor device according to the present disclosure includes: introducing an impurity having a first conductivity type from an upper surface of a semiconductor substrate having the upper surface and a lower surface; forming a metal layer on the upper surface; introducing hydrogen from the lower surface and forming a first semiconductor layer; performing first heat treatment on the semiconductor substrate, and donating the hydrogen introduced into the first semiconductor layer; introducing from the lower surface an impurity of a second conductivity type opposite to the first conductivity type, and forming a second semiconductor layer at a position shallower than a position of the first semiconductor layer; and performing second heat treatment on the semiconductor substrate at a temperature higher than a temperature of the first heat treatment, and applying the second conductivity type to the second semiconductor layer.
H01L 21/268 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée les radiations étant électromagnétiques, p. ex. des rayons laser
H01L 21/30 - Traitement des corps semi-conducteurs en utilisant des procédés ou des appareils non couverts par les groupes
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/60 - Distribution ou concentrations d’impuretés
72.
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF INSPECTING SEMICONDUCTOR DEVICE, AND INSPECTION DEVICE
A method of manufacturing a semiconductor device includes preparing a semiconductor device and an inspection device. In the preparing, the semiconductor device has a semiconductor element, a plurality of pads electrically connected to the semiconductor element, and a plurality of bumps arranged on each pad. The inspection device includes a probe card having a plurality of probes, a first holding portion detachably holding the semiconductor device, a cleaning substrate cleaning the probes, and a second holding portion detachably holding the cleaning substrate. The first and second holding portions are movable relatively to the probe card.
A semiconductor device includes a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate. The semiconductor substrate includes, in plan view, a coil region and a peripheral region surrounding the coil region. The multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film. The first coil and the second coil are formed in a first wiring layer being one of the plurality of wiring layers disposed on the coil region. The third coil and the fourth coil are formed in a second wiring layer being another one of the plurality of wiring layers disposed on the coil region. The second wiring layer is disposed above the first wiring layer. The third coil and the fourth coil are disposed so as to face the first coil and the second coil, respectively.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
75.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first semiconductor chip, a die attach film, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, a bonding pad, and one or more deformed bonding pads serving as alignment marks of the first semiconductor chip. In plan view, the analog circuit is located inside an outer peripheral edge of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
76.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate; an interlayer insulating film; a first and a second electrode pads; and a first and a second plating films. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate serves as an n-type drain region. The semiconductor substrate includes: an n-type source region; a p-type channel region adjacent to a side of the source region, the side being closer to the first main surface, and pn-bonded to the source region and the drain region; and a p-type well region and pn-bonded to the drain region. The interlayer insulating film is formed on the second main surface. The first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the well region, respectively.
A protection cell has a first MISFET group composed of a plurality of first MISFETs and a second MISFET group composed of a plurality of second MISFETs. The first MISFET group and the second MISFET group are provided separately from each other. The first MISFET group is electrically connected to a first power wiring group and a first ground wiring group so as to electrically short-circuit them. The second MISFET group is electrically connected to a second power wiring group and a first ground wiring group so as to electrically short-circuit them. The first MISFET group overlaps with a part of the first power wiring group and a part of the first ground wiring group in a plan view.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H01L 23/528 - Configuration de la structure d'interconnexion
78.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device is provided, which includes a boundary member between an auxiliary element and a main surface of a semiconductor substrate to reduce the step of a protective film covering the auxiliary element. A semiconductor device is provided, comprising a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in plan view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. The height from the first main surface to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.
G06T 5/20 - Amélioration ou restauration d'image utilisant des opérateurs locaux
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
80.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device is provided, the semiconductor device including: a first electrode; an N-type semiconductor layer arranged on the first electrode; a P-type semiconductor layer arranged on the N-type semiconductor layer; a first insulating layer surrounding and partitioning a first region in plan view, arranged on the P-type semiconductor layer; a second electrode arranged on the P-type semiconductor layer; a second insulating layer arranged on the first insulating layer surrounding and partitioning the first region in plan view on the second electrode; a metal plating layer arranged on the second electrode; a solder layer arranged on the metal plating layer; and a clip arranged on the solder layer, and the first region is a region where the clip is joined with the metal plating layer.
A first stacked structure and a first sidewall spacer are formed in a first region. A second stacked structure including a metal film is formed in a second region. In the first region, an epitaxial layer is formed on a semiconductor layer. The first sidewall spacer is removed. A first silicon oxide film is formed on a surface of the epitaxial layer exposed from a first insulating film. A thickness of each of the first insulating film and the first silicon oxide film is reduced by performing a cleaning treatment using an aqueous solution containing ammonia and an activator on each of the first insulating film and the first silicon oxide film. An extension region is formed in each of the semiconductor layer and the epitaxial layer by performing an ion implantation so as to pass through each of the first insulating film and the first silicon oxide film.
A radar system comprising a plurality of receivers, each receiver having its clock generator generating a clock signal with a sampling frequency for sampling a radar signal received on one or more receiving antennas and a plurality of delay estimation and compensation (DEC) blocks implemented within the corresponding plurality of receivers, wherein, each DEC block is configured to synchronise the clock generator of one receiver with every other receiver. A method in a radar comprising, generating a sync pulse in a first receiver in the plurality of receives, measuring a delay between the sync pulse and the clock signal in the first receiver, transmitting the sync pulse to other receivers in the plurality of receivers measuring a second delay between the sync pulse and the clock pulse in the other receivers and changing the frequency of the clock generator in the other receivers from the sampling frequency to first frequency for a first time duration.
G01S 13/933 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions d'aéronefs ou d'engins spatiaux
G06F 1/12 - Synchronisation des différents signaux d'horloge
A regulator includes a reference potential generation circuit that generates a reference potential serving as a reference for an intermediate potential and an intermediate potential lower than the intermediate potential, a differential amplifier to which the intermediate potential is supplied as a low potential side power supply and which amplifies a difference voltage between a feedback potential corresponding to the intermediate potential and the reference potential, and a transistor having a gate to which the amplified difference voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source that generates the intermediate potential.
G05F 1/573 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection avec détecteur de surintensité
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
A communication device includes a communication control unit. The communication control unit includes a plurality of protocol processing units and a plurality of received data storage areas. A received message that is a CAN message received by the communication device is input into the plurality of protocol processing units. In a case where the destination of the received message is a virtual machine corresponding to the protocol processing unit itself, each protocol processing unit stores the payload of the received message in the received data storage area accessible from the destination virtual machine.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
85.
METHOD OF TRANSPORTING SEMICONDUCTOR DEVICE AND CARRIER TAPE
A method of transporting a semiconductor device includes: a step of placing a semiconductor device in a pocket portion, a step of attaching the cover tape to the carrier tape so as to cover the semiconductor device placed in the pocket portion, and a step of transporting the carrier tape containing the semiconductor device. Here, the pocket portion includes: a plurality of corner portions where a step section is formed, and a plurality of side portions located between these corner portions and having a first protruding portion and a second protruding portion formed thereon. Also, a width of a tip portion of the second protruding portion is smaller than a width of the tip portion of the first protruding portion. Furthermore, a protrusion amount of the second protruding portion from the side portion is larger than a protrusion amount of the first protruding portion from the side portion.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
86.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first resistor element. The first resistor element includes a first resistor, and a second resistor electrically connected in series to the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electrical resistance value of the first resistor and a temperature coefficient of an electrical resistance value of the second resistor is a positive value. The other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor is a negative value.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
The first and third NMOS transistors are connected in series between the sense node and the fifth NMOS transistor, and the second and fourth NMOS transistors are connected in series between the sense node and the sixth NMOS transistor.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
A semiconductor device includes: a first electric-current generator circuit generating a first electric current having a positive temperature coefficient and not having dependency on a first power-supply voltage; a second electric-current generator circuit generating a second electric current having a negative temperature coefficient and not having dependency on the first power-supply voltage; and a third electric-current generator circuit generating a third electric current neither having dependency on the temperature nor the first power-supply voltage, based on the first electric current and the second electric current.
A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
G06F 13/24 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption
G06F 13/32 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant la combinaison d'interruption et de transfert par rafale
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 29/66 - Types de dispositifs semi-conducteurs
92.
SEMICONDUCTOR WAFER TRANSFER METHOD AND SEMICONDUCTOR WAFER TRANSFER DEVICE
The method for transporting the semiconductor wafer involves the steps of preparing the non-contact chuck provided with an optical sensor and the semiconductor wafer having a first main surface, positioning the non-contact chuck so that the optical sensor and the first main surface face each other with a predetermined interval therebetween, measuring a first intensity, which is the intensity of a reflected light from the first main surface, by illuminating the first main surface with a light from the optical sensor before bringing the non-contact chuck close to the first main surface, bringing the non-contact chuck close to the first main surface and maintaining the semiconductor wafer in a non-contact state by blowing gas to the first main surface from the non-contact chuck, and disengaging the non-contact chuck from the semiconductor wafer by moving the non-contact chuck away from the first main surface.
H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
A debugging system includes first and second semiconductor devices and a log analysis apparatus. Each of the first and second semiconductor devices executes software to generate a trace log, a first execution log, and a second execution log. The first semiconductor device transfers the trace log and the first execution log to the log analysis apparatus. The second semiconductor device transfers the trace log and the second execution log to the log analysis apparatus. The log analysis apparatus identifies the processing order of the first execution log and the second execution log based on time stamps given to the trace logs, the first execution log, and the second execution log transferred from the first and second semiconductor devices, and generates analysis data by combining the first and second execution logs according to the identified processing order. The analysis data is used for analyzing a cause of an error.
A semiconductor device includes: a field plate electrode formed in an inner portion of a trench through a first insulating film, the trench being formed in a semiconductor substrate; and a gate electrode formed over the field plate electrode through a second insulating film. The first insulating film includes a stacked film made of a first oxide film in contact with the semiconductor substrate and a second oxide film in contact with the field plate electrode, and an inclination of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
95.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND PROGRAM
A Semiconductor device capable of performing efficient signal processing, to provide a control method and a program of the semiconductor device. The semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The control unit includes: a detection unit that detects the process amount of the second process in which the first signal processing unit or the second signal processing unit executes; a prediction unit that predicts the process amount of the second process to be executed next based on the process amount of the detected second process; and a distribution unit that distributes the first process to the first signal processing unit and the second signal processing unit according to the process amount of the predicted second process.
A semiconductor device includes, in a gate finger region, a gate potential trench formed on a main surface side of a semiconductor substrate, predetermined potential trenches formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench, and a well region of a second conductivity type, which is a region above the drift region and formed in a second region on a side of the predetermined potential trench opposite to a side where the gate potential trench is located.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
97.
SEMICONDUCTOR DEVICE HAVING INTEGRATED TURN-ON AND TURN-OFF RESISTORS AND DIODE
The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
100.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
