A semiconductor device includes a semiconductor substrate and a multilayer wiring layer disposed on the semiconductor substrate. The semiconductor substrate includes, in plan view, a coil region and a peripheral region surrounding the coil region. The multilayer wiring layer includes a first coil, a second coil, a third coil, a fourth coil, and a metal film. The first coil and the second coil are formed in a first wiring layer being one of the plurality of wiring layers disposed on the coil region. The third coil and the fourth coil are formed in a second wiring layer being another one of the plurality of wiring layers disposed on the coil region. The second wiring layer is disposed above the first wiring layer. The third coil and the fourth coil are disposed so as to face the first coil and the second coil, respectively.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
3.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first semiconductor chip, a die attach film, a second semiconductor chip, and a resin molding member. The first semiconductor chip is attached to the second semiconductor chip via the die attach film. The second semiconductor chip includes an analog circuit, a bonding pad, and one or more deformed bonding pads serving as alignment marks of the first semiconductor chip. In plan view, the analog circuit is located inside an outer peripheral edge of the die attach film. The resin molding member seals the first semiconductor chip, the second semiconductor chip, and the die attach film.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
4.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor substrate; an interlayer insulating film; a first and a second electrode pads; and a first and a second plating films. The semiconductor substrate has a first main surface and a second main surface opposite to the first main surface. The semiconductor substrate serves as an n-type drain region. The semiconductor substrate includes: an n-type source region; a p-type channel region adjacent to a side of the source region, the side being closer to the first main surface, and pn-bonded to the source region and the drain region; and a p-type well region and pn-bonded to the drain region. The interlayer insulating film is formed on the second main surface. The first electrode pad and the second electrode pad are formed on the interlayer insulating film and are electrically connected to the source region and the well region, respectively.
An image processing device according to an embodiment includes: an image division unit dividing input image data into first division image data and second division image data having a predetermined overlap region with the first division image data according to a size of a kernel used for image processing; a reuse data determination unit determining first reuse data reused in performing the image processing to the second division image data among the first division image data; and a memory management unit, in a memory, storing first processed data of a first division image obtained by performing the image processing to the first division image data, in a region other than a region storing the first reuse data, and allocates a region storing the second division image data so as to be adjacent to the region storing the first reuse data.
G06T 5/20 - Amélioration ou restauration d'image utilisant des opérateurs locaux
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
A protection cell has a first MISFET group composed of a plurality of first MISFETs and a second MISFET group composed of a plurality of second MISFETs. The first MISFET group and the second MISFET group are provided separately from each other. The first MISFET group is electrically connected to a first power wiring group and a first ground wiring group so as to electrically short-circuit them. The second MISFET group is electrically connected to a second power wiring group and a first ground wiring group so as to electrically short-circuit them. The first MISFET group overlaps with a part of the first power wiring group and a part of the first ground wiring group in a plan view.
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H01L 23/528 - Configuration de la structure d'interconnexion
7.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device is provided, which includes a boundary member between an auxiliary element and a main surface of a semiconductor substrate to reduce the step of a protective film covering the auxiliary element. A semiconductor device is provided, comprising a semiconductor substrate having a first main surface having a first region, a second region, and a third region located between the first region and the second region in plan view, a transistor formed in the first region, an auxiliary element formed in the second region, a boundary member formed in the third region, and a protective film covering the auxiliary element and the boundary member. The height from the first main surface to the upper surface of the boundary member is lower than the height from the first main surface to the upper surface of the auxiliary element.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A semiconductor device is provided, the semiconductor device including: a first electrode; an N-type semiconductor layer arranged on the first electrode; a P-type semiconductor layer arranged on the N-type semiconductor layer; a first insulating layer surrounding and partitioning a first region in plan view, arranged on the P-type semiconductor layer; a second electrode arranged on the P-type semiconductor layer; a second insulating layer arranged on the first insulating layer surrounding and partitioning the first region in plan view on the second electrode; a metal plating layer arranged on the second electrode; a solder layer arranged on the metal plating layer; and a clip arranged on the solder layer, and the first region is a region where the clip is joined with the metal plating layer.
A first stacked structure and a first sidewall spacer are formed in a first region. A second stacked structure including a metal film is formed in a second region. In the first region, an epitaxial layer is formed on a semiconductor layer. The first sidewall spacer is removed. A first silicon oxide film is formed on a surface of the epitaxial layer exposed from a first insulating film. A thickness of each of the first insulating film and the first silicon oxide film is reduced by performing a cleaning treatment using an aqueous solution containing ammonia and an activator on each of the first insulating film and the first silicon oxide film. An extension region is formed in each of the semiconductor layer and the epitaxial layer by performing an ion implantation so as to pass through each of the first insulating film and the first silicon oxide film.
A radar system comprising a plurality of receivers, each receiver having its clock generator generating a clock signal with a sampling frequency for sampling a radar signal received on one or more receiving antennas and a plurality of delay estimation and compensation (DEC) blocks implemented within the corresponding plurality of receivers, wherein, each DEC block is configured to synchronise the clock generator of one receiver with every other receiver. A method in a radar comprising, generating a sync pulse in a first receiver in the plurality of receives, measuring a delay between the sync pulse and the clock signal in the first receiver, transmitting the sync pulse to other receivers in the plurality of receivers measuring a second delay between the sync pulse and the clock pulse in the other receivers and changing the frequency of the clock generator in the other receivers from the sampling frequency to first frequency for a first time duration.
G01S 13/933 - Radar ou systèmes analogues, spécialement adaptés pour des applications spécifiques pour prévenir les collisions d'aéronefs ou d'engins spatiaux
G06F 1/12 - Synchronisation des différents signaux d'horloge
A regulator includes a reference potential generation circuit that generates a reference potential serving as a reference for an intermediate potential and an intermediate potential lower than the intermediate potential, a differential amplifier to which the intermediate potential is supplied as a low potential side power supply and which amplifies a difference voltage between a feedback potential corresponding to the intermediate potential and the reference potential, and a transistor having a gate to which the amplified difference voltage is input, a drain connected to a ground potential via a constant current source or a resistor, and a source that generates the intermediate potential.
G05F 1/573 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final sensible à une condition du système ou de sa charge en plus des moyens sensibles aux écarts de la sortie du système, p. ex. courant, tension, facteur de puissance à des fins de protection avec détecteur de surintensité
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
A communication device includes a communication control unit. The communication control unit includes a plurality of protocol processing units and a plurality of received data storage areas. A received message that is a CAN message received by the communication device is input into the plurality of protocol processing units. In a case where the destination of the received message is a virtual machine corresponding to the protocol processing unit itself, each protocol processing unit stores the payload of the received message in the received data storage area accessible from the destination virtual machine.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
13.
METHOD OF TRANSPORTING SEMICONDUCTOR DEVICE AND CARRIER TAPE
A method of transporting a semiconductor device includes: a step of placing a semiconductor device in a pocket portion, a step of attaching the cover tape to the carrier tape so as to cover the semiconductor device placed in the pocket portion, and a step of transporting the carrier tape containing the semiconductor device. Here, the pocket portion includes: a plurality of corner portions where a step section is formed, and a plurality of side portions located between these corner portions and having a first protruding portion and a second protruding portion formed thereon. Also, a width of a tip portion of the second protruding portion is smaller than a width of the tip portion of the first protruding portion. Furthermore, a protrusion amount of the second protruding portion from the side portion is larger than a protrusion amount of the first protruding portion from the side portion.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
14.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first resistor element. The first resistor element includes a first resistor, and a second resistor electrically connected in series to the first resistor. The first resistor and the second resistor are each made of a first material. One of a temperature coefficient of an electrical resistance value of the first resistor and a temperature coefficient of an electrical resistance value of the second resistor is a positive value. The other of the temperature coefficient of the electrical resistance value of the first resistor and the temperature coefficient of the electrical resistance value of the second resistor is a negative value.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
A semiconductor device includes a variable-resistance memory cell array, a sense amplifier electrically connected to the variable-resistance memory cell array, and a clamp voltage generation circuit electrically connected to the sense amplifier. The sense amplifier includes an amplification unit that amplifies a voltage at a sense node, a first clamp circuit having first and second NMOS transistors whose gate terminals are electrically connected, a second clamp circuit having third and fourth NMOS transistors whose gate terminals are electrically connected, a fifth NMOS transistor electrically connected to the variable-resistance memory cell array, a reference resistor, and a sixth NMOS transistor electrically connected to the reference resistor.
The first and third NMOS transistors are connected in series between the sense node and the fifth NMOS transistor, and the second and fourth NMOS transistors are connected in series between the sense node and the sixth NMOS transistor.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
A semiconductor device includes: a first electric-current generator circuit generating a first electric current having a positive temperature coefficient and not having dependency on a first power-supply voltage; a second electric-current generator circuit generating a second electric current having a negative temperature coefficient and not having dependency on the first power-supply voltage; and a third electric-current generator circuit generating a third electric current neither having dependency on the temperature nor the first power-supply voltage, based on the first electric current and the second electric current.
A data transfer device that divides and transfers the transfer target data in a burst manner from a transmission-side device to a reception-side device includes a storage device and a control device that controls the storage device to store one piece of the input transfer target data, controls the storage device so that data transfer is performed at a set burst length as a data length of divided data when the one piece of the data is divided by a division number until a last part of the data is sensed, and when the last part of the data is sensed, controls the storage device to adjust the burst length so that a data length of the data coincides with a total of data lengths of data to be transferred, and to transfer the data at the adjusted burst length.
G06F 13/24 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption
G06F 13/32 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant la combinaison d'interruption et de transfert par rafale
G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée
Improve the reliability of semiconductor device. The protective cell ESD1a comprises a group of MISFETS 1QA constituted by a plurality of n-type MISFETs 1Q, and a pair of MISFET groups 2QA constituted by a plurality of p-type MISFETs 2Q. The group of MISFETs 1QA and the pair of MISFET groups 2QA are electrically connected to the power wiring and the ground wiring, respectively, to electrically short-circuit them. The pair of MISFET groups 2QA outputs a signal to turn on a plurality of MISFETs 10 to each gate electrode of the plurality of MISFETs 1Q. The group of MISFETs 1QA is provided between the pair of MISFET groups 2QA.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
A resist pattern having an opening portion that exposes a part of a conductive film located on a gate insulating film is formed on the conductive film. Next, an anisotropic etching treatment is performed using the resist pattern as a mask to selectively remove the conductive film exposed from the resist pattern and to form a gate pattern and a dummy gate pattern from the remaining conductive film. Next, an oblique ion implantation is performed using the resist pattern as a mask to form a p-type body region in a semiconductor substrate.
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 29/66 - Types de dispositifs semi-conducteurs
20.
SEMICONDUCTOR WAFER TRANSFER METHOD AND SEMICONDUCTOR WAFER TRANSFER DEVICE
The method for transporting the semiconductor wafer involves the steps of preparing the non-contact chuck provided with an optical sensor and the semiconductor wafer having a first main surface, positioning the non-contact chuck so that the optical sensor and the first main surface face each other with a predetermined interval therebetween, measuring a first intensity, which is the intensity of a reflected light from the first main surface, by illuminating the first main surface with a light from the optical sensor before bringing the non-contact chuck close to the first main surface, bringing the non-contact chuck close to the first main surface and maintaining the semiconductor wafer in a non-contact state by blowing gas to the first main surface from the non-contact chuck, and disengaging the non-contact chuck from the semiconductor wafer by moving the non-contact chuck away from the first main surface.
H01L 21/68 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le positionnement, l'orientation ou l'alignement
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
A debugging system includes first and second semiconductor devices and a log analysis apparatus. Each of the first and second semiconductor devices executes software to generate a trace log, a first execution log, and a second execution log. The first semiconductor device transfers the trace log and the first execution log to the log analysis apparatus. The second semiconductor device transfers the trace log and the second execution log to the log analysis apparatus. The log analysis apparatus identifies the processing order of the first execution log and the second execution log based on time stamps given to the trace logs, the first execution log, and the second execution log transferred from the first and second semiconductor devices, and generates analysis data by combining the first and second execution logs according to the identified processing order. The analysis data is used for analyzing a cause of an error.
A semiconductor device includes: a field plate electrode formed in an inner portion of a trench through a first insulating film, the trench being formed in a semiconductor substrate; and a gate electrode formed over the field plate electrode through a second insulating film. The first insulating film includes a stacked film made of a first oxide film in contact with the semiconductor substrate and a second oxide film in contact with the field plate electrode, and an inclination of an upper surface of the first insulating film changes at a boundary between the first oxide film and the second oxide film.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
23.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND PROGRAM
A Semiconductor device capable of performing efficient signal processing, to provide a control method and a program of the semiconductor device. The semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The control unit includes: a detection unit that detects the process amount of the second process in which the first signal processing unit or the second signal processing unit executes; a prediction unit that predicts the process amount of the second process to be executed next based on the process amount of the detected second process; and a distribution unit that distributes the first process to the first signal processing unit and the second signal processing unit according to the process amount of the predicted second process.
A semiconductor device includes, in a gate finger region, a gate potential trench formed on a main surface side of a semiconductor substrate, predetermined potential trenches formed so as to sandwich the gate potential trench on the main surface side of the semiconductor substrate, a drift region of a first conductivity type formed in a first region between the gate potential trench and the predetermined potential trench, and a well region of a second conductivity type, which is a region above the drift region and formed in a second region on a side of the predetermined potential trench opposite to a side where the gate potential trench is located.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
25.
SEMICONDUCTOR DEVICE HAVING INTEGRATED TURN-ON AND TURN-OFF RESISTORS AND DIODE
The present invention suppresses an increase in manufacturing cost and reduces switching noise. A field-effect transistor having a gate electrode embedded in a trench in an upper surface of a semiconductor substrate, a source region formed in the semiconductor substrate, and a drain region formed on a lower surface of the semiconductor substrate is provided with a gate wiring formed on the semiconductor substrate and being electrically connected to the gate electrode, a gate pad formed on the semiconductor substrate, a first resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned ON, a second resistor connected between the gate pad and the gate wiring and being configured to function when the field-effect transistor is turned OFF, and a rectifier diode included in the first resistor or the second resistor between the gate pad and the gate wiring.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Enhancing the performance of semiconductor devices by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, forming a laminated body including a paraelectric film, which is an insulating film, and the ferroelectric film made of three or more layers of ferroelectric layers to on the insulating film, and forming a metal film and a gate electrode on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers that are in contact with each other, the crystallinity of the ferroelectric film is enhanced.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A plurality of wirings included in a wiring substrate includes: a plurality of first wirings for propagating a first clock signal and a first chip select signal to first and second memory devices mounted on a front surface; and a plurality of second wirings for propagating a second clock signal and a second chip select signal to third and fourth memory devices mounted on a back surface. The plurality of first wirings is provided in a wiring layer, which is closer to the front surface, of a plurality of wiring layers, and the plurality of second wirings is provided in a wiring layer, which is closer to the back surface, of the wiring layers.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
28.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a ferroelectric memory cell, and the ferroelectric memory cell includes a select transistor and a memory transistor. A gate dielectric film of the select transistor includes a ferroelectric film, and a gate dielectric film of the memory transistor includes a ferroelectric film.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/51 - Matériaux isolants associés à ces électrodes
29.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type differing from the first conductivity type in the first semiconductor layer; a third semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the second semiconductor layer; a fourth semiconductor layer of the first conductivity type on the third semiconductor layer; a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer and having a higher impurity concentration than the fourth semiconductor layer; a sixth semiconductor layer of the second conductivity type in the second semiconductor layer and having a higher impurity concentration than the third semiconductor layer; and a seventh semiconductor layer of the second conductivity type having the same impurity concentration distribution as the third semiconductor layer in a depth direction.
H01L 27/07 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive les composants ayant une région active en commun
According to one embodiment, a semiconductor device includes: a semiconductor substrate having an upper surface and a lower surface; a first conductive layer formed above the semiconductor substrate; and a second conductive layer formed on the upper surface of the first conductive layer, in which, when viewed from above, the second conductive layer is formed in a region inside an end edge of the first conductive layer, the thickness of the second conductive layer is larger than the thickness of the first conductive layer, the thermal conductivity of the second conductive layer is larger than the thermal conductivity of the first conductive layer, and the resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a second semiconductor region surrounding the first semiconductor region in plan view, a first conductive layer formed on the first semiconductor region, a first electrode formed on the first conductive layer, a cathode region connected to the first electrode via the first conductive layer, a second conductive layer in contact with the first semiconductor region, a second electrode formed on the second conductive layer, and a first region disposed between a region in contact with the first conductive layer of the first semiconductor region and the cathode region in a direction along the upper surface of the semiconductor substrate, and the first region is in contact with a lower surface of the second conductive layer. A depth of the first region is greater than a depth of the cathode region.
On a lower layer side of a temperature sensing diode, trenches are periodically formed in a semiconductor substrate. A source field plate is arranged in the trenches via an insulating film. A P type diffusion layer is formed between adjacent trenches. The source field plate and the P type diffusion layer are connected to a source potential.
H01L 23/34 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température
G01K 7/01 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments semi-conducteurs à jonctions PN
A semiconductor device includes a processor including a first register set and a second register set. In a first period, the processor selects the second register set as an active register set, and executes a first virtual machine by use of second context data. In a second period, the processor selects the first register set as the active register set, and executes a hypervisor by use of first context data. In the second period, the processor performs a processing of saving the second context data and a processing of reading third context data. In a third period, the processor selects the second register set as the active register set, and executes a second virtual machine by use of the third context data.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A semiconductor device with high performance is provided. A semiconductor device according to the present disclosure includes a semiconductor substrate having a plurality of trenches provided along a first direction, a field plate electrode having a plurality of recess portions and a plurality of thinning-out portions which are alternately disposed in the first direction, and being provided in the trench, an oxide film provided on the field plate electrode, and a gate electrode formed on the oxide film and disposed in each of the recess portions. In the adjacent trenches, the gate electrodes are disposed to be shifted in the first direction.
A semiconductor device includes a first terminal, an oscillation circuit that generates a first clock signal and a second clock signal, an AD conversion circuit, a correction circuit that corrects the digital signal obtained by the AD conversion circuit based on a correction data stored in a memory circuit and outputs the digital signal, an averaging circuit, a sampling circuit, a current generation circuit, and a superposition circuit, the correction data is generated based on an output of the sampling circuit when a dispersion current is superposed on a detection current, and is stored in the memory circuit.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
36.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: a semiconductor chip having a source electrode pad and mounted on a die pad via a die bonding material; a wire electrically connected with the source electrode pad of the semiconductor chip; and a sealing body sealing the semiconductor chip and the wire. The wire and the source electrode pad are made of different types of metals to each other. A wire bonding layer made of sintered metal is interposed between the source electrode pad and the wire. The wire is electrically connected with the source electrode pad via the wire bonding layer.
An interrupt reception unit receives an interrupt request. In response to a received interrupt request, an interrupt processing unit performs an interrupt process of a first priority or an interrupt process of a second priority having a lower priority than the first priority. An interrupt suppression control unit controls the number of interrupt processes of the second priority processed by the interrupt processing unit in a cycle time according to a suppression condition. The suppression condition is set on the basis of a cycle in which the interrupt process of the second priority occurs and the total number of the interrupt processes of the second priority occurring within a period corresponding to the cycle.
G06F 13/26 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant l'interruption avec commande prioritaire
38.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Since an electrode formed on an insulating film may be separated from the insulating film in a semiconductor device, the present invention makes it possible to prevent the separation of the electrode from the insulating film. A semiconductor device includes a semiconductor substrate, an insulating film, and an electrode. The insulating film is formed on the semiconductor substrate. The electrode is formed on the insulating film. The semiconductor device also includes an anchor member. The anchor member is in contact with the insulating film and the electrode, at an outer peripheral portion of the electrode.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/283 - Dépôt de matériaux conducteurs ou isolants pour les électrodes
H01L 23/528 - Configuration de la structure d'interconnexion
A semiconductor device includes a semiconductor substrate, a first semiconductor region formed in the semiconductor substrate, a buried region formed in the semiconductor substrate, a second semiconductor region disposed over the buried region, a third semiconductor region disposed over the buried region, a drain region formed in the second semiconductor region, a source region formed in the third semiconductor region, and a gate electrode layer formed on an upper surface of the semiconductor substrate. The first semiconductor region includes a first region formed between the third semiconductor region and the buried region, and a second region formed between the second semiconductor region and the buried region. The semiconductor substrate, the first semiconductor region, and the second semiconductor region each have a first conductivity type. The buried region and the third semiconductor region each have a second conductivity type opposite the first conductivity type.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
A semiconductor device including: a semiconductor chip mounted on a wiring substrate such that a main surface of the semiconductor chip faces a front surface of an insulating film of the wiring substrate; and a bump electrically connecting a land and an electrode pad. Here, in cross-sectional view, a center of the land is shifted in a direction from a center of an opening portion, which exposes a part of the land, of the insulating film toward a center of the semiconductor chip is provided.
A semiconductor device includes three types of cells as a plurality of logic gates. A first cell includes a p-type MOSFET having a first threshold voltage and an n-type MOSFET having a second threshold voltage. A second cell includes a p-type MOSFET having a third threshold voltage and an n-type MOSFET having a fourth threshold voltage. A third cell includes a p-type MOSFET having the third threshold voltage and an n-type MOSFET having the second threshold voltage. An absolute value of the first threshold voltage is higher than an absolute value of the third threshold voltage, and an absolute value of the second threshold voltage is higher than an absolute value of the fourth threshold voltage.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
42.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A pad is formed on an interlayer insulating film, and an insulating film is formed to cover the interlayer insulating film and the pad. An opening is formed in the insulating film to expose a part of the pad. In the opening, a nickel plating film is formed on the pad, a first gold plating film is formed on the nickel plating film, and a second gold plating film is formed on the first gold plating film. A phosphorus concentration of the nickel plating film is 2% by mass or more and 7% by mass or less.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
C23C 18/16 - Revêtement chimique par décomposition soit de composés liquides, soit de solutions des composés constituant le revêtement, ne laissant pas de produits de réaction du matériau de la surface dans le revêtementDépôt par contact par réduction ou par substitution, p. ex. dépôt sans courant électrique
C23C 18/32 - Revêtement avec l'un des métaux fer, cobalt ou nickelRevêtement avec des mélanges de phosphore ou de bore et de l'un de ces métaux
C23C 18/44 - Revêtement avec des métaux nobles en utilisant des agents réducteurs
A semiconductor device includes fuse circuits, and each of the fuse circuits includes fuse elements and cutting transistors. The fuse elements and the cutting transistors are arranged in a first direction of a first main surface of a semiconductor substrate, respectively, and each of the fuse elements is surrounded by each of deep trench isolation parts in plan view. In plan view, each of the cutting transistors is surrounded by each of power supply parts, and the power supply parts are integrally surrounded by the deep trench isolation part. The cutting transistors are formed in a well region, and each of the power supply parts has the same conductivity type as the well region and is formed in the well region.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
44.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An n-type drift region and a p-type well region are formed in a semiconductor substrate. An n-type first drain region and an n-type second drain region are formed in the n-type drift region, and an n-type source region and an n-type semiconductor region are formed in the p-type well region. An impurity concentration of the n-type semiconductor region is lower than an impurity concentration of the n-type source region. A gate electrode includes an n-type first gate electrode portion and an n-type second gate electrode portion extending in the Y direction, and a p-type gate connection portion connecting the first gate electrode portion and the second gate electrode portion. In plan view, the n-type source region is arranged between the first gate electrode portion and the second gate electrode portion.
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H01L 21/265 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions
H01L 21/266 - Bombardement par des radiations ondulatoires ou corpusculaires par des radiations d'énergie élevée produisant une implantation d'ions en utilisant des masques
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
45.
SEMICONDUCTOR DEVICE, DEBUGGING SYSTEM, CONTROL METHOD FOR SEMICONDUCTOR DEVICE, AND DEBUGGING METHOD
A semiconductor device includes a CPU configured to execute an instruction, a first register configured to store an address of the instruction currently being executed, a second register configured to store a return address when a function branch occurs, and a generation circuit configured to generate and output function branch information indicating an address of a function branch destination when the function branch occurs. The generation circuit is configured to determine whether or not the function branch has occurred based on values of the first register and the second register before and after instruction execution by the CPU, and, when determining that the function branch has occurred, output the value of the first register after the instruction execution by the CPU as the function branch information.
A semiconductor device includes an insulating film, and a polysilicon film formed on the insulating film. The semiconductor device includes, in plan view, a first region including a first semiconductor element formed of the polysilicon film, and a second region including a second semiconductor element. A first contact hole formed in the first region extends through the polysilicon film. An ohmic contact is formed between a metal embedded in the first contact hole and the polysilicon film on a side surface of the first contact hole.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
47.
NON-TRANSITORY COMPUTER READABLE MEDIUM, CO-SIMULATION METHOD, AND CO-SIMULATION APPARATUS
A non-transitory computer readable medium stores a program for causing a co-simulation apparatus including a first simulator, a second simulator, a first communication path, and a second communication path to execute a co-simulation method. The first simulator stores first data in a first shared memory via the first communication path. In addition, the first simulator divides information related to a first address of the first shared memory in which the first data is stored into pieces of a size defined by an FMI standard, and transmits the pieces of information to the second simulator via the second communication path. The second simulator reads the first data stored in the shared memory by using the first address via the first communication path.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p. ex. des interruptions ou des opérations d'entrée–sortie
A semiconductor device includes a dummy field structure in a non-element forming region. The dummy field structure includes a deep n-type well, an n-type well, a trench, a conductor layer, a first n-type semiconductor region, a second n-type semiconductor region, and a third n-type semiconductor region. The semiconductor device includes not only a first parasitic bipolar transistor but also a second parasitic bipolar transistor.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
An IGBT includes a first trench gate electrode extending in a first width direction, and a second trench gate electrode facing the first trench gate electrode. A first position range in the first width direction of a first channel region formed by the first trench gate electrode and a second position range in the first width direction of a second channel region formed by the second trench gate electrode differ from each other.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
50.
BATTERY MANAGEMENT SYSTEM, BATTERY MANAGEMENT METHOD, AND PROGRAM
The battery management system includes a first communication connection checking unit, a second communication connection checking unit, and an estimating unit. The first communication connection checking unit checks the communication state of the first communication connection that connects the microcontroller and the battery managing unit that obtains the cell voltage and the pack temperature. The second communication connection checking unit checks the communication state of the second communication connection that connects the microcontroller and the measuring unit that measures the pack voltage and pack current. The estimating unit estimates the charge/discharge information for controlling the charge/discharge of the battery based on the information that the microcontroller MC1 can be obtained, in accordance with the communication state of the first communication connection and the second communication connection.
H01M 10/42 - Procédés ou dispositions pour assurer le fonctionnement ou l'entretien des éléments secondaires ou des demi-éléments secondaires
H01M 10/48 - Accumulateurs combinés à des dispositions pour mesurer, tester ou indiquer l'état des éléments, p. ex. le niveau ou la densité de l'électrolyte
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
51.
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor layer having an N type drift region, a P type body region on the N type drift region, and an N type source region on the P type body region; an insulating layer on the semiconductor layer; a first opening provided in the insulating layer; a second opening provided in the semiconductor layer and extending from the N type source region to the P type body region so as to overlap the first opening in plan view; an insulating film arranged on a sidewall of the second opening; a first metal layer provided on the insulating layer, on the semiconductor layer of the first opening, on the insulating film, and on the semiconductor layer of the second opening; and a second metal layer provided on the first metal layer.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
Reliability of a semiconductor device is improved. An insulating film is formed in an inner portion of a trench and on an upper surface of a semiconductor substrate. A field plate electrode is formed on the insulating film to fill the inner portion of the trench. The field plate electrode is recessed toward a bottom portion of the trench by etching process. Etching process using mixed gas containing CF4 gas and O2 gas is performed to an upper surface of the field plate electrode. A silicon oxide film is formed on the upper surface of the field plate electrode by thermal oxidation process.
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
53.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip is mounted on a die pad via a solder material. The semiconductor chip includes a plurality of corners including a first corner. A recess portion is formed in the die pad at an upper surface of the die pad. The semiconductor chip is mounted on the die pad such that the first corner is located at an inside of the recess portion. The first corner is located farthest from a center of a sealing body, among the plurality of corners. The solder material has: a first portion that is located between the semiconductor chip and a bottom surface of the recess portion; and a second portion that is located between the semiconductor chip and the upper surface of the die pad. A thickness of the solder material in the first portion is greater than a thickness of the solder material in the second portion.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A controller for controlling a power stage having a plurality of phases is presented. The controller generates a control signal; sends the control signal to the plurality of phases via a first link; receives from each phase a feedback signal via a second link; sums the plurality of feedback signals and derives an average current per phase.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
55.
NON-LINEAR TRANSIENT IMPROVEMENTS IN CURRENT MODE CONTROLLERS
A method of increasing a transient response of a current mode controller and a current mode controller with an improved transient response are provided. The current mode controller is configured to control a high side switch and a low side switch. The current mode controller includes a pulse width modulation generator.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
56.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A lower electrode is formed in a first wiring layer. In a second wiring layer located over the first wiring layer, two wirings having a thickness greater than that of the lower electrode are formed. Between the first wiring layer and the second wiring layer, a dielectric film and an upper electrode are formed over the lower electrode. A resistor element is formed over the two wirings. The lower electrode, the dielectric film, and the upper electrode function as a capacitor element.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
57.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
Reliability of a semiconductor device is improved. A resistance element and a trench form a closed path in plan view.
The semiconductor device includes: first and second contact members each electrically connecting a gate pad and the resistance element; third and fourth contact members each electrically connecting a gate wiring and the resistance element; and fifth to eighth contact members each electrically connecting a first conductive member and the resistance element. A current path passing from the gate pad to the gate wiring through the first conductive member is made of the plurality of contact members and the resistance element. The first conductive member functions together with the fifth to eighth contact members to form a bypass path for reducing the current that flows through some sections of the closed path made of the resistance element.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
A semiconductor device includes a semiconductor chip in which a plurality of circuit blocks is formed. The plurality of circuit blocks includes a plurality of logic circuits. Each of the plurality of logic circuits includes an inverter circuit. The inverter circuit outputs a signal according to the result of a logical operation of a first signal and a second signal after being precharged by a trigger signal.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
H03K 19/17704 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
H03K 19/17728 - Blocs logiques reconfigurables, p. ex. tables de consultation
H03K 19/1776 - Détails structurels des ressources de configuration pour les mémoires
A semiconductor device includes a first power supply voltage line to which a power supply voltage is supplied, a second power supply voltage line, a first impedance element provided between the first power supply voltage line and the second power supply voltage line, a first reference voltage line to which a reference voltage is supplied, a second reference voltage line, a second impedance element provided between the first reference voltage line and the second reference voltage line, an electronic circuit provided between the second power supply voltage line and the second reference voltage line and performing a predetermined processing on an input signal, and provided in series between the second power supply voltage line and the second reference voltage line, and having gates connected to drains, a first transistor which is a P-channel MOS transistor, and a second transistor which is an N-channel MOS transistor.
A silicon film in amorphous state is formed on a semiconductor substrate located in first to fourth regions. The silicon film located in the first region and the fourth region is removed such that the silicon film located in the second region and the third region is left. A polycrystalline silicon film is formed by crystallizing the silicon film by a heat treatment.
H10B 51/40 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région de circuit périphérique
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
61.
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE
Performance of a semiconductor device is improved. A semiconductor device includes a semiconductor chip, a sealing body having an upper surface and a lower surface, a plurality of leads, and a metal plate exposed from the sealing body at the upper surface of the sealing body. An outer lead portion of each of the plurality of leads includes a portion extending from the upper surface toward the lower surface in a thickness direction of the sealing body. The portion includes an end of the outer lead portion. When it is assumed that the lower surface is a reference surface in side view, in the thickness direction of the sealing body, a distance from the end of the outer lead portion to the reference surface is less than a distance from the upper surface to the reference surface.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/40 - Supports ou moyens de fixation pour les dispositifs de refroidissement ou de chauffage amovibles
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
62.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. In the semiconductor layer, an n-type semiconductor region is formed so as to surround a transistor in plan view and to reach the n-type buried layer from a main surface of the semiconductor substrate. A DTI region is formed so as to penetrate through the n-type semiconductor region and the n-type buried layer and reach the p-type substrate region.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
63.
SYSTEMS AND METHODS FOR GATE CURRENT SHAPING FOR GATE DRIVERS
Gate drivers, systems and methods are described. A gate driver can generate a gate current for driving a power switch in a system. A circuit can define a waveform shape of the gate current. The defined waveform shape of the gate current can cause a current of the power switch to have a constant slew rate.
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
64.
SEMICONDUCTOR DEVICE, SWITCHING METHOD AND PROGRAM
A semiconductor device, a switching method, and a program that can prevent an overcurrent from flowing through a winding inside the motor are provided. The semiconductor device 100a, based on at least one of the inductance value and the resistance value of the winding inside the motor 10, a determination unit 363 for determining whether the current value of the winding exceeds the threshold after a predetermined time, based on the determination result of the determination unit 363 comprising a switch unit 364 for switching the control mode of the motor 10.
H02P 29/024 - Détection d’un défaut, p. ex. court circuit, rotor bloqué, circuit ouvert ou perte de charge
H02P 23/14 - Estimation ou adaptation des paramètres des moteurs, p. ex. constante de temps du rotor, flux, vitesse, courant ou tension
H02P 27/08 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par le type de tension d'alimentation utilisant une tension d’alimentation à fréquence variable, p. ex. tension d’alimentation d’onduleurs ou de convertisseurs utilisant des convertisseurs de courant continu en courant alternatif ou des onduleurs avec modulation de largeur d'impulsions
65.
COMMUNICATION CONTROLLER AND COMMUNICATION CONTROL METHOD
A communications controller is disclosed. The communications controller includes a data transfer unit and a protocol engine. The communications controller further includes a circuit configured to control transfer of data from the data transfer unit to the protocol engine in dependence upon a process identifier which identifies a process entity requiring the protocol engine to transmit data for the process entity.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
66.
PROBE TESTING APPARATUS, PROBE TESTING SYSTEM AND PROBE CARD
A probe testing apparatus includes a wafer stage, a temperature sensor, a temperature adjustment mechanism, and a controller. The wafer stage includes a wafer mounting surface on which a semiconductor wafer is mounted. The temperature sensor includes a temperature observation point exposed on the wafer mounting surface, and directly measures a temperature of a rear surface of the semiconductor wafer mounted on the wafer mounting surface. The temperature adjustment mechanism adjusts a temperature of the wafer stage by heating or cooling the wafer stage. The controller controls the temperature adjustment mechanism in such a manner that a measured temperature by the temperature sensor becomes a target temperature.
A first conductive pattern is formed on a semiconductor substrate and formed from a first conductive film. A second conductive film having a first portion on the semiconductor substrate, a second portion on an upper surface of the first conductive pattern, and a third portion connecting the first portion and the second portion so as to cover a side surface of the first conductive pattern, is formed. The upper surface of the third portion is higher than the upper surface of the first portion. The second portion is patterned. The second portion and a part of the third portion are selectively removed. By patterning the first conductive pattern and the second conductive film, a first gate electrode is formed from a part of the first conductive pattern, and a second gate electrode is formed from a part of the first portion.
A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip. One of the first semiconductor chip and the second semiconductor chip includes a first switch. The other of the first semiconductor chip and the second semiconductor chip includes a second switch. The third semiconductor chip includes a first transformer. A signal is transmitted from the first semiconductor chip to the second semiconductor chip by the first transformer when the first switch is turned off while the second switch is turned on. A signal is transmitted from the second semiconductor chip to the first semiconductor chip by the first transformer when the second switch is turned off while the first switch is turned on.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H02M 7/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continuTransformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif
69.
SEMICONDUCTOR MEASUREMENT DEVICE AND SEMICONDUCTOR MEASUREMENT METHOD
According to an embodiment, a semiconductor measurement device includes a CBCM circuit having a first terminal and a connection terminal and a potential difference application circuit connected to the connection terminal, the potential difference application circuit having a second terminal and applying a predetermined potential difference with respect to an output of the first terminal. The semiconductor measurement device obtains the parasitic capacitance of a measurement system from a capacitance in a connected state in which the first terminal and the second terminal are connected to a transistor and a capacitance in a disconnected state in which the first terminal and the second terminal are disconnected from the transistor, and calculates the capacitance of the transistor.
G01R 27/26 - Mesure de l'inductance ou de la capacitanceMesure du facteur de qualité, p. ex. en utilisant la méthode par résonanceMesure de facteur de pertesMesure des constantes diélectriques
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
A semiconductor device includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in plan view. The second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
71.
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD AND PROGRAM
To appropriately estimate the amount and direction of movement of a moving object, an information processing apparatus has an acquisition unit that acquires each image captured at each point in time by a shooting device mounted on the moving object; a determination unit that determines the type of movement of the moving object based on the respective images; and an estimation unit that, based on a first image and a second image captured at a time interval corresponding to the type of movement from the first image, estimates the amount and direction of movement of the moving object from the first point in time when the first image was captured to the second point in time when the second image was captured.
A semiconductor device capable of verifying whether or not correct acquirement of image data from a sensor has been successful is provided. A semiconductor device includes: a reception interface circuit receiving a plurality of packets including a plurality of line data, respectively, and outputting an image composite signal generated by linking a line synchronization signal with each of the plurality of line data; and a capture circuit provided at a subsequent stage of the reception interface circuit. The capture circuit includes: a line counter receiving, as its input, the line synchronization signal included in the image composite signal, and counting the number of times of the input of the line synchronization signal; and a comparator comparing a count value counted by the line counter with a preset expected value of the number of lines, and outputting an error signal if the count value and the expected value do not match each other.
To provide a semiconductor device and a memory module capable of correctly maintaining the phase relationship between a data signal and a data strobe signal that determines the latch timing of the data signal. A variable delay circuit VDLYs_A generates respective data strobe signals DQSin, DQSin_M by delaying an input data strobe signal MDQS by delay amounts ST1, ST2. A timing adjustment circuit TMCT adjusts the delay amount ST1 based on the determination of matching/mismatching between a data signal DQo from a main slicer SLr and a data signal DQo_M from a monitor slicer SLr_M, while changing the delay amount ST2,
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
A current sense circuit is provided. The circuit includes a current mirror circuit QN1, QN2, and diode-connected QP1, QP2, QP3, and QP4 with their bases connected together, stacking such that the diode-connected side (QN1, QP1, QP3) aligns and connecting the emitter of QP2 to the collector of QP4. Furthermore, the gates of MP1 and MP2 are connected to the collector of QN2 and QP2, respectively. Additionally, the source of MP1 is connected to the drain of MP3 via the source of MP2 and also connected to the source of a Sense MOS. Moreover, the emitter of QP4 is connected to the source of MP4 via R1, and the drain of MP4 is connected to the source (OUT terminal) of a Main MOS. Furthermore, the gates of MP3 and MP4 are connected to the emitters of QN1 and QN2.
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
A semiconductor device having a semiconductor chip with a first circuit, a second circuit, a third circuit, a first protection element, and a resistor circuit, the first circuit and the third circuit mutually input and output unidirectional or bidirectional signals via the second circuit, the first protection element is electrically connected to a first node which electrically connects a first terminal and the second circuit, and the resistor circuit is provided between the first node and a second node which electrically connects the first terminal, the first circuit, and the second circuit and is located upstream of the first node.
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
76.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: a step of forming a sealing body, and a step of irradiating a laser light to a region, which is covering a part of each of the plurality of leads, of the sealing body. Each of the plurality of leads of a lead frame LF includes a first portion having a first upper surface and a first lower surface opposite the first upper surface, and a second portion having a thickness smaller than the first portion. The second portion has a second upper surface, and a second lower surface opposite the second upper surface. In the step of irradiating the laser light, the second lower surface is exposed from the sealing body by selectively irradiating the region with the laser light.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A semiconductor nonvolatile memory device or the like capable of narrowing a cell voltage distribution range while suppressing write delay is provided. The semiconductor nonvolatile memory device includes: a plurality of gate lines; a plurality of bit lines intersecting the plurality of gate lines; and a plurality of memory cells connected to respectively intersection points between the gate lines and the bit lines. The plurality of memory cells are connected to one gate line selected from among the plurality of gate lines respectively via the different bit lines, and the semiconductor nonvolatile memory device further includes a plurality of write bit line current or voltage control circuits respectively controlling bit line currents in order to simultaneously perform writing into the plurality of memory cells.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/24 - Circuits de commande de lignes de bits
A semiconductor device includes a semiconductor chip having a plurality of layers formed on a surface. Here, a power supply wiring to which a power supply voltage is supplied, a ground wiring to which a ground voltage is supplied, MOS transistors connected to the power supply and ground wirings, and a trigger circuit, which is electrically connected to a gate electrode of the MOS transistor via a first wiring, are formed in the plurality of layers. The MOS transistors and the trigger circuit are formed in a first layer, the first wiring is formed in a second layer which is an upper layer of the first layer, and the first wiring includes a first portion extending in a first direction and a second portion which extends in a second direction intersecting the first direction and is electrically connected to the first portion.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
79.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE, AND CONTROL PROGRAM
A semiconductor device according to this disclosure includes: a comparator circuit; a counter circuit; and a latch circuit that stores a count value of the counter circuit at a timing when an output signal of the comparator circuit changes, the counter circuit includes: a multiphase signal generator; and a plurality of flip-flop circuits including a first-stage flip-flop and second-stage and subsequent flip-flops, the first-stage flip-flop takes in an inverted signal of an output signal of a flip-flop in a final stage and each of the second-stage and subsequent flip-flops takes in an output signal of a flip-flop in a preceding stage in synchronization with each of the plurality of clock signals, and an output signal of each of the plurality of flip-flop circuits is output as a count signal of the count value.
H04N 25/633 - Traitement du bruit, p. ex. détection, correction, réduction ou élimination du bruit appliqué au courant d'obscurité en utilisant des pixels noirs optiques
H03K 5/24 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant l'amplitude
H03K 23/00 - Compteurs d'impulsions comportant des chaînes de comptageDiviseurs de fréquence comportant des chaînes de comptage
H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
H03L 7/089 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence engendrant des impulsions d'augmentation ou de diminution
H04N 25/40 - Extraction de données de pixels provenant d'un capteur d'images en agissant sur les circuits de balayage, p. ex. en modifiant le nombre de pixels ayant été échantillonnés ou à échantillonner
Access time from a CPU to a register can be reduced while complication of software is prevented. A semiconductor device includes: a decoder circuit determining a write-source process; a write-enable setting storage circuit storing a write-enable setting that indicates a processor enabled to execute writing into each bit of a write-destination register; a masking/merging circuit generating a value to be written back into the write-destination register on the basis of the write-enable setting and the write-source processor; and a write-back circuit writing back the value to be written back into the write-destination register.
A semiconductor device includes a non-volatile memory (NVM) capable of data-writing even after the semiconductor device is shipped. When a read request is made, the semiconductor reads and outputs the content stored in the area of the NVM in place of the replacement target data in the instruction codes stored in a read only memory. Therefore, after shipping of the semiconductor device, even if a defect such as fragility in the code used at the start of the semiconductor device is found, replacement data in place of 10 the data to be replaced it can be obtained. That is, the semiconductor device, replacement process using the modified patches of Boot ROM cord is enabled.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A method of manufacturing a semiconductor device includes, after a wire bonding step, a step of determining a quality as to whether or not a whole of an end portion of a wire is located within a bonding region. A semiconductor chip includes a plurality of position determining opening patterns arranged in a region located around a main opening portion including the bonding region in plan view. The bonding region has a rectangular shape having an area smaller than an opening area of the main opening portion in plan view. The bonding region is defined by the plurality of position determining opening patterns.
A semiconductor device is protected from glitch attacks (FIA). A reset data transfer controller RDTC executes N times of data transfer, transferring data DT stored in a first memory MEM1a to a main register REGm during the first data transfer, and transferring data DT stored in the first memory MEM1a to a sub-register REGs during the Nth data transfer. A comparison circuit CMP1 determines the match/mismatch between the data DTm transferred to the main register REGm and the data DTs transferred to the sub-register REGs, and outputs a determination result signal RS representing the determination result. A system controller SYSC activates a processor PRC when the determination result signal RS indicates a match, and causes the reset data transfer controller RDTC to execute the N times of data transfer again when it indicates a mismatch.
High speed of an analog-digital converter of a semiconductor device is achieved. A voltage quantizer circuit includes: a first comparator including a first input transistor inputting differential input voltages, and defining a value of a first bit of a digital signal; and a second comparator including a second input transistor being different from the first input transistor, and defining a value of a second bit of the digital signal. A correction code decision circuit decides a correction code for correcting a common-mode voltage of the differential input voltages, based on a conversion end signal output from the voltage quantizer circuit. A common-mode voltage regulator circuit regulates the common-mode voltage by adding or subtracting a corrected voltage based on the correction code to or from the differential input voltages.
A semiconductor device includes a semiconductor substrate, a multilayer wiring structure formed on the semiconductor substrate, a guard ring formed so as to surround a circuit formation region and penetrate the multilayer wiring structure, and a pad formed on the multilayer wiring structure. A protective film is formed so as to cover the multilayer wiring structure, the guard ring, and the pad. A trench is formed so as to penetrate the protective film and reach an inside of the multilayer wiring structure. The trench is formed so as to surround the guard ring. The guard ring includes a wiring formed on the multilayer wiring structure. The trench is spaced apart from and adjacent to the wiring. A bottom surface of the trench is inclined so as to be continuously deepened in a direction from the circuit formation region toward a peripheral region surrounding the circuit formation region.
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
86.
ON-CHIP NOISE MEASUREMENT IN A TRANSCEIVER, METHOD AND SYSTEM THEREOF
According to an aspect, a transceiver comprises a transmitter section having a first PLL (phased locked loop) providing a first reference signal to the transmitter section, a receiver section having a second PLL providing a second reference signal to the receiver section, a coupler coupling the second PLL to the transmitter section when the transceiver is operative in a test mode measuring a first noise component introduced by the first PLL. The first reference signal is coupled to the receiver section internally within the transceiver as a local reference signal to the receiver section both in the test mode and a functional mode.
A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts the fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.
Systems and methods for sensing and processing biosignals are described. An example system can include a first device configured to sense at least one biosignal and a second device. The second device can receive the at least one biosignal from the first device. The second device can receive power via a first wireless interface. The second device can charge a rechargeable battery using the received power. The second device can receive a signal via the first wireless interface, wherein the signal encodes credentials of a user. The second device can demodulate the signal to decode the user credentials. The second device can authenticate the user credentials. The second device can, in response to authentication of the user credentials, communicate the at least one biosignal to a user device via a second wireless interface.
H02J 50/20 - Circuits ou systèmes pour l'alimentation ou la distribution sans fil d'énergie électrique utilisant des micro-ondes ou des ondes radio fréquence
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
A failure detection circuit is provided in the target circuit having a first circuit area for operating in synchronization with the first clock signal, a first detection circuit for outputting a first detection result obtained by transitioning the voltage level in synchronization with the first clock signal, the first clock signal a second detection circuit for outputting a second detection result obtained by transitioning the voltage level in synchronization with, and a first comparison circuit for outputting a first comparison result by comparing the first detection result and the second detection result. Accordingly, by the failure detection circuit, it is possible to detect the failure accurately.
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
According to one embodiment, the semiconductor device 1 includes a semiconductor substrate having an upper surface and a lower surface, and an emitter wiring, wherein when viewed from the upper surface side, the semiconductor substrate has an active region including a plurality of IGBTs, a termination region, and a main junction region, wherein the semiconductor substrate of the main junction region has an N− type drift layer and a P type junction impurity layer, wherein the semiconductor substrate of the termination region has an N− type drift layer and a P type floating layer, wherein at least the main junction region has a trench electrode provided inside the trench, and a trench insulating film provided between the trench electrode and the semiconductor substrate, and wherein the trench electrode and the P type junction impurity layer are connected to the emitter wiring.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
91.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A first surface of a die pad has: a first region; a second region that includes points respectively overlapping with four corners of a semiconductor chip; and a third region that is located around the second region. Also, a plurality of grooves is formed in the die pad at the second region. Also, each of the plurality of grooves terminates at a position not reaching each of the first region and the third region. Also, the plurality of grooves includes: a plurality of first grooves each extending in an extending direction of one of two diagonal lines of the semiconductor chip; and a plurality of second grooves each extending in an extending direction of another one of the two diagonal lines. Also, in each of the plurality of first grooves is arranged so as to intersect with one or more of the plurality of second grooves.
A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.
A carrier tape includes a first layer component having a recess and a first opening in a center of the recess, and a second layer component housed in the recess, the second layer having a center arranged parallel to the recess, a step part arranged around the center by a step falling from the center, a second opening overlapping the first opening arranged in the center, and a third opening arranged in the step part.
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
A semiconductor device according to the embodiment includes a semiconductor chip having a first MOSFET formed in a first region of a semiconductor substrate, a detection element formed in a second region within the first region, a source electrode formed above the first region and connected to a source of the first MOSFET, and a source electrode material arranged to cover the detection element and stitch-bonded to the source electrode.
To reduce the time required for data writing. A semiconductor memory device is provided, comprising a memory cell having a gate electrode including a selection gate and a memory gate, a source line connected to a source, and a bit line connected to a drain, an extraction part that extracts a current flowing from the source side to the drain side during writing in the memory cell from the bit line, a discharge part that has a higher ability to pass current than the extraction part and lowers the voltage of the bit line, a charge part that has a higher ability to pass current than the discharge part and applies a voltage to the bit line, and a control part that, when starting to write to the memory cell, lowers the voltage of the bit line by the discharge part and applies a voltage to the bit line by the charge part.
Improve the reliability of a semiconductor device. A resistive element Rg is filled in a trench TR formed in a well region PW of a semiconductor substrate. The resistive element Rg and the trench TR have an endless shape in plan view. The resistive element Rg is connected to a first contact member PG that is electrically connected to a gate pad GP, and a second contact member PG that is electrically connected to a gate wiring GW. Furthermore, a third contact member PG, which electrically connects an emitter electrode EE to the well region PW, is positioned in an area surrounded by an endless shape of the resistive element Rg, between the first and second contact members PG in a Y direction.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
Providing a memory device that initializes memory cell data in a batch by specifying initialization data, or a memory device that initializes memory cell data in a batch by partially masking the initialization area. A memory device is provided that includes a control circuit that receives an initialization mode signal transmitted from an initialization control circuit and generates an internal clock and a write control signal, an IO (Input/Output) input circuit that applies a Low level to the True side or Bar side of a bit line according to initialization data transmitted from the initialization control circuit, and a selection circuit that simultaneously selects multiple word lines and multiple bit lines, and writes the initialization data simultaneously into a memory cell connected to the selected word lines and bit lines.
In plan view, an electrode pad of a semiconductor chip includes: a first region that contains a center of an exposed portion of the electrode pad; a second region that is located around the first region; and a third region that is located around the first region and that is located between the first region and the second region. Here, a first groove that separates a plurality of semiconductor elements formed in a semiconductor substrate from each other is formed in the semiconductor substrate. The semiconductor substrate includes: a fourth region that overlaps with the third region but not overlaps with each of the first region and the second region, and a fifth region that overlaps with the first region but not overlaps with the third region. And, the first groove is formed in the semiconductor substrate at the fifth region but not at the fourth region.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/498 - Connexions électriques sur des substrats isolants
99.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
The technology of improving the adhesion of the barrier metal film is provided. The semiconductor device includes: a floating region formed between a trench gate electrode and a trench emitter electrode; a stacked film formed on the floating region; an interlayer insulating film formed on the stacked film; a plug penetrating the interlayer insulating film and reaching the stacked film; a barrier metal film formed to cover the interlayer insulating film and the plug; and a metal film formed on the barrier metal film.
H01L 29/739 - Dispositifs du type transistor, c.à d. susceptibles de répondre en continu aux signaux de commande appliqués commandés par effet de champ
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/49 - Electrodes du type métal-isolant-semi-conducteur
H01L 29/66 - Types de dispositifs semi-conducteurs
A controller for controlling a power stage having one or more phases is presented. The controller includes a reference circuit that generates a reference signal; a ramp generator generating a feedback ramp signal based on a feedback signal of the power stage; and a modulator generating a control signal for controlling at least one phase of the power stage. The control signal may include a series of pulses in which each pulse is associated with a corresponding phase of the power stage.
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/00 - Détails d'appareils pour transformation
