A drive circuit can calculate an optimal phase adjustment amount by passing a current through an external load. The drive circuit includes a control circuit that outputs a first AC signal and a second AC signal from an AC signal source, and a reference voltage generation circuit that has a differential amplifier generating a first AC voltage from the first AC signal and outputs the first AC voltage to one end of an external load. It also includes a voltage-current conversion circuit that supplies an AC current to the external load from the second AC signal, and a comparator connected across both ends of the external load. The comparator compares the first AC voltage at one end of the external load with the second AC voltage at the other end of the external load and changes the output voltage when the first and second AC voltages are inverted.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
2.
METHOD, A PROGRAM, AND A COMPUTER FOR TIMING ADJUSTMENT OF A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
The timing adjustment method, program, and computer for a semiconductor integrated circuit are provided to suppress the increase in the size of layout data. The timing adjustment method for a semiconductor integrated circuit includes adding one or more dummy cells each having a plurality of dummy metals to layout data of the semiconductor integrated circuit, selecting a dummy cell to be connected to a signal wiring when the delay time of the signal wiring included in the layout data indicates a hold error, and connecting one or more of the plurality of dummy metals included in the dummy cell that has been selected in the selecting to the signal wiring.
To provide a semiconductor device and its manufacturing method capable of designing the intended delay with high precision using fewer steps. The manufacturing method of the semiconductor device disclosed herein arranges multiple circuits on a plane and connects wiring to each, comprising: a placement step of arranging a digital circuit that operates based on timing signals and a delay circuit configured with multiple delay paths having different input/output delay amounts, where one of the multiple delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay adjustment step of selecting one of the multiple delay paths by connecting a predetermined voltage as the selection signal, and selecting the delay amount so that the input/output timing of the digital circuit meets predetermined conditions.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
4.
SEMICONDUCTOR WAFER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor wafer includes a semiconductor substrate, a plurality of chip regions, a scribe region, and an interlayer insulating film. A TEG is formed in the scribe region. The TEG includes a first active region formed in the semiconductor substrate, a second active region formed in the semiconductor substrate, and adjacent to the first active region in a first direction, a gate electrode formed on the first active region and the second active region, and extending in the first direction, an insulating region adjacent to the second active region in a second direction orthogonal to the first direction, and formed in the semiconductor substrate so as not to overlap with the first gate electrode in plan view, a plug formed in the interlayer insulating film and connected to the first active region, and a dummy plug formed in the interlayer insulating film and connected to the insulating region.
The camera inspection system includes an external environment changer that receives an inspection signal and changes the imaging illumination of a camera fixed to a vehicle, thereby changing the brightness within the frame image captured by the camera. It also includes an average brightness calculator that calculates the average brightness within the image for each frame image captured within a predetermined period by the camera, and an inspector that compares the inspection signal with the average brightness within the image for each frame image and generates a fault detection signal indicating image fixation when the timing of the change in the inspection signal does not match the change in the average brightness within the image.
It can blow an electric fuse with a small blowing current. A metal film is connected to a first wiring through a first via, and is connected to a second wiring through a second via. A disconnect transistor is coupled to the second wiring. An area of a contact surface, which is in contact with the metal film, of the first via is smaller than an area of a contact surface, which is in contact with the metal film, of the second via.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
A semiconductor device includes: a plurality of pads; a plurality of redistribution wirings connected to the plurality of pads; a terminal provided on a land portion of each of the plurality of redistribution wirings; and a conductive film connected to each of the terminal and the land portion. The plurality of redistribution wirings includes: a first redistribution wiring having a first land portion; and a second redistribution wiring having a second wiring portion. A planar shape of the conductive film is circular. A planar shape of the first land portion is non-circular. In plan view, the first land portion is arranged adjacent to the second wiring portion which is extending in the Y direction. In plan view, the first land portion has a first side which is linearly extending along the second wiring portion.
To achieve desired performance, a data reception device comprises receiving unit and an adaptive equalization processing unit. The receiving unit generates a received signal based on a first wireless signal received by a first antenna and a second wireless signal received by a second antenna. The adaptive equalization processing unit performs adaptive equalization processing to asymptotically match the received signal based on the first wireless signal and the second wireless signal generated by the receiving unit to a predetermined training signal.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
9.
SILICON CARBIDE PLANAR MOSFET WITH HYBRID LINEAR AND HEXAGONAL CHANNEL ARCHITECTURE
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper and bottom surface. A drift region of the first conductivity type is located on the upper surface. Above the drift region, a channel region of a second conductivity type, opposite to the first conductivity type, is located featuring a hybrid configuration. The hybrid configuration includes a first channel segment of a first channel geometry located between and directly connected to two second channel segments of a second channel geometry. A source region of the first conductivity type is located adjacent to the channel region. A first doped semiconductor region of the second conductivity type, featuring a third geometry, is placed above the drift region and adjacent to the first channel segment. Finally, a gate electrode is located above the drift region via a gate oxide.
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
10.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A plurality of wirings is formed on the interlayer insulating film. The interlayer insulating film has a BPSG film and a PSG film formed on the BPSG film. A gettering layer containing phosphorus is formed in the PSG film. A concentration of phosphorus in the gettering layer is higher than a concentration of phosphorus in the PSG film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A gate electrode is formed on a semiconductor substrate via a second gate insulating film, and a floating gate electrode is formed on the semiconductor substrate via a first gate insulating film. A second sidewall spacer is formed on a side surface of the gate electrode, and a first sidewall spacer is formed on a side surface of the floating gate electrode. A first insulating film made of silicon oxide covers the floating gate electrode, and a second insulating film made of silicon nitride covers the gate electrode, the floating gate electrode, the second sidewall spacer, the first sidewall spacer, and the first insulating film. The first insulating film is interposed between an upper surface of the floating gate electrode and the second insulating film. A density of the upper portion of the first insulating film BL is larger than that of the lower portion of the first insulating film.
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
A semiconductor device, a control method for the semiconductor device, and a program for efficiently storing values in memory are provided. The semiconductor device 100 includes a data acquisition unit 1, a determination unit 2, and memory 3. The data acquisition unit 1 acquires a data signal SIG input from the outside at a predetermined cycle. Determination unit 2 stores a threshold. Determination unit 2 performs a threshold determination by comparing the measurement value M indicated by the data signal SIG acquired by the data acquisition unit 1 with the threshold. If, in the threshold determination, the measurement value M is determined to be an abnormal value that does not meet the predetermined criteria, the measurement value M is stored in memory 3.
A semiconductor device includes a timer control circuit (timer) and an AD converter (ADC), and generates a PWM signal by using a periodic signal of the timer on the basis of an ADC output. After receiving an AD conversion start request signal (ADR signal), the ADC starts AD conversion in synchronization with a latest AD synchronization signal. The timer outputs a timer phase signal that is a basis for starting generation of a periodic signal and the ADR signal when a phase-locked loop counter value matches a value of a timer phase register, outputs an AD synchronization phase signal that is a basis for starting generation of the AD synchronization signal when the counter value matches the value of an AD synchronization phase register, and controls a phase difference between the ADR signal and the AD synchronization signal to be constant regardless of activation timing of the device.
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Apparatuses, devices, and systems for operating a voltage converter to reduce current spike are described. A controller can measure a feedback of a current of an alternating current (AC) voltage of a switching circuit. The controller can measure a direct current (DC) voltage of the switching circuit. The controller can operate a current control loop using the feedback of the current to determine a target voltage. The controller can determine a duty cycle of the switching circuit based on the target voltage and the DC voltage. The controller can operate the switching circuit under the determined duty cycle to control the current of the AC voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
15.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an n-type offset drain region, an n-type semiconductor region, and a gate electrode. The n-type semiconductor region is arranged apart from the n-type offset drain region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device includes an n-type semiconductor substrate, a seal ring wiring formed in an annular shape so as to surround a first region and a second region of the semiconductor substrate in plan view, and a p-type impurity region formed in the semiconductor substrate. The impurity region is provided between the first region and the second region so as to extend to a position overlapping, in plan view, with the seal ring wiring. A ground potential is supplied to the impurity region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
Described herein is a method of determining visibility of predefined content in a display displaying dynamic background content. The method may comprise: after determining that the predefined content is to be overlayered on the dynamic background content for rendering in the display, obtaining at least one image representative of visual information displayed in the display; and performing a computer vision-based process based on the obtained at least one image to determine the visibility of the predefined content in the display.
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06T 19/00 - Manipulating 3D models or images for computer graphics
G06V 10/44 - Local feature extraction by analysis of parts of the pattern, e.g. by detecting edges, contours, loops, corners, strokes or intersectionsConnectivity analysis, e.g. of connected components
G06V 10/56 - Extraction of image or video features relating to colour
18.
ANALOGUE TO DIGITAL CONVERTER AND METHOD FOR CONTROLLING THE SAME
The analogue to digital converter outputs a conversion value obtained by performing analogue to digital conversion on an input signal. The non-volatile memory stores a plurality of correction values. The correction circuit selects, in response to a status affecting an offset in the conversion value of the analogue to digital converter, a correction value corresponding to the status from among the plurality of correction values as a selected correction value, and outputs an output value where the offset in the conversion value is corrected based on the selected correction value.
A differential amplification system for receiving first and second input signals, and for generating first and second differential output signals, the differential amplification system comprising a differential amplifier configured to receive the first input signal and the second input signal, provide a first output current at a first current channel, and provide a second output current at a second current channel, a cascode stage configured to receive the first and second output currents, and generate the first and second differential output signals, a detector configured to detect when the first output current flowing through the first current channel meets a first condition, and/or detect when the second output current flowing through the second current channel meets a second condition, wherein a current sink stage configured to redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the first condition is met by the first output current, and/or redirect at least a portion of the first output current and at least a portion of the second output current away from the cascode stage when the second condition is met by the second output current, wherein the first condition is met by the first output current when the first output current falls below a first threshold current value and/or the first output current rises above the first threshold current value, and the second condition is met by the second output current when the second output current falls below a second threshold current value and/or the second output current rises above the second threshold current value.
To suppress false detection of fault injection, the fault injection detector detects the fault injection. The encryption module generates the first encrypted data by encrypting the plaintext data. The controller verifies the encrypted data generated by the encryption module and determines whether the encrypted data is valid if fault injection is detected in the fault injection detector.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper surface and a bottom surface. The semiconductor structure further includes a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The upper surface having a transistor region and peripheral regions located at each corner of the transistor region. The transistor region further includes a channel region of a second conductivity type, opposite to the first conductivity type, located above the drift region and positioned on a center portion of the transistor region, a source region of the first conductivity type adjacent to the channel region, and a gate electrode located above the drift region via a gate oxide, the gate electrode surrounds the source region. Each of the peripheral regions includes a first semiconductor region of the second conductivity type formed above the drift region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
22.
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH DOUBLE SEQUENTIAL TRENCH STRUCTURE
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type, opposite to the first conductivity type, located above the drift layer, and a source region of the first conductivity type located above the channel layer. The semiconductor structure further includes a stepped shaped trench structure that extends through the source region and the channel layer until a top portion of the drift layer, a gate electrode located within the trench structure and surrounded by a gate insulating film, and a shield region of the second conductivity type covering a bottom of the trench structure such that the shield region extends laterally along the trench structure to a trench corner.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Each latch cell in a latch cell array is made of 12 MOS transistors including a first CMOS switch transferring write data and a second CMOS switch transferring read data. A test for rewriting a storage node on a write bit line side in each latch cell from a first logic level to a second logic level in a state in which the first and second CMOS switches are respectively controlled to be on in overlapping time periods is assumed. In this case, a disturb test circuit precharges a read bit line to the second logic level before the second CMOS switch is controlled to be on.
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Systems and methods for implementing multi-phase TLVR secondary voltage stress reduction are generally described. A semiconductor device can include a controller configured to map a plurality of pulse width modulation (PWM) signals in a default order as a first sequence to operate a trans-inductor voltage regulator (TLVR). The TLVR can include a primary circuit and a secondary circuit, and the primary circuit can include a plurality of phases. The semiconductor device can further include a circuit configured to map the plurality of PWM signals to a second sequence different from the first sequence. The controller can be configured to output the plurality of PWM signals in the second sequence to operate the TLVR.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Systems and methods for adaptive voltage regulation with multiple ports are described. The device can include a first voltage regulator coupled to a first port and can regulate voltages between the first port and a battery. The device can further include a second voltage regulator coupled to a second port and can regulate voltages between the second port and the battery. The device can also include a bypass switch coupled to the first voltage regulator, the first port, the second voltage regulator and the second port. The device can further include an integrated circuit configured to operate the bypass switch. When the bypass switch can be turned on, the first voltage regulator can be further configured to regulate voltages between the second port and the battery. The second voltage regulator can be further configured to regulate voltages between the first port and the battery.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H01M 10/46 - Accumulators structurally combined with charging apparatus
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
26.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To provide a semiconductor device capable of preventing a contact barrier metal film from peeling off from the trench gate lead-out electrode. In the gate wiring lead-out region MGR defined on a semiconductor substrate, a convex portion is formed on the trench gate lead-out electrode TGI, extending towards a gate lead-out contact member. The convex portion is formed by a natural oxidation film and a polysilicon film PSF. The gate lead-out contact member is formed to cover the convex portion by interposing the contact barrier metal film.
A semiconductor device includes a power device, a booster circuit, and an overcurrent detection circuit. The overcurrent detection circuit includes a sense circuit that outputs a voltage corresponding to a current flowing in the power device, and a detection current generation circuit that generates a detection current depending on an output from the sense circuit. The detection current generation circuit includes a first control circuit that operates with a boosted voltage from the booster circuit and controls a first current circuit depending on the voltage output from the sense circuit, and a second control circuit that operates with a power source voltage and controls a second current circuit depending on the voltage output from the sense circuit.
In an embodiment, a semiconductor device is disclosed that includes a buffer circuit that is configured to selectively output a charge signal to an inductor-capacitor node of a power driver to charge the inductor-capacitor node to a predetermined voltage level and an amplifier circuit that is configured to monitor a voltage differential across a capacitor of the inductor-capacitor node of the power driver. The amplifier circuit is configured to output a positive side signal and a negative side signal. The semiconductor device further includes an output that is configured to provide at least one signal based on the positive side signal and negative side signal to an analog-to-digital converter for measurement by a controller.
H02J 50/12 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling of the resonant type
H02J 50/60 - Circuit arrangements or systems for wireless supply or distribution of electric power responsive to the presence of foreign objects, e.g. detection of living beings
Systems and methods for fault detection in heads-up display are described. A processor can receive an image signal encoding image data of a virtual image to be projected on a surface of a windshield of a vehicle. The processor can select a group of pixels corresponding to a region of the virtual image. The processor can determine at least one characteristic for each pixel in the group of pixels. The processor can determine one or more group attributes representative of the group of pixels based on the at least one characteristic for each pixel in the group of pixels. The processor can determine that the one or more group attributes fails to satisfy a condition associated with a set of predefined threshold group attributes. The processor can, in response to determining that the one or more group attributes fails to satisfy the condition, generate a fault detection signal.
A method of manufacturing a semiconductor device includes: forming a diffusion source on a lower surface of a semiconductor substrate to diffuse conductive impurities into the semiconductor substrate, and irradiating the lower surface of the semiconductor substrate with laser light through the diffusion source.
H01L 21/225 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regionsRedistribution of impurity materials, e.g. without introduction or removal of further dopant using diffusion into, or out of, a solid from or into a solid phase, e.g. a doped oxide layer
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/268 - Bombardment with wave or particle radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
A semiconductor device has a die pad, a semiconductor chip mounted on the die pad via a conductive material, and a lead terminal electrically connected to a source electrode of the semiconductor chip via a bonding member. Here, the source electrode includes a detection point for detecting a value of a current flowing in a power transistor provided in the semiconductor chip, and a bonding portion to which the bonding member is bonded. Then, a sense transistor provided in the semiconductor chip, the detection point, and the bonding portion do not overlap with a first region of the die pad, but overlap with a second region of the die pad. In addition, a thickness of the conductive material provided in the second region is larger than a thickness of the conductive material provided in the first region.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
32.
SEMICONDUCTOR DEVICE AND CERTIFICATION METHOD THEREOF
Improve the tamper resistance against physical attacks on semiconductor devices. The semiconductor device according to the present disclosure includes a transition circuit that transitions the state at a predetermined Hamming distance based on the comparison result between the certification target value and the reference value, and a determination circuit that determines the validity of the certification by determining whether the Hamming distance between the state before the transition and the state after the transition matches the predetermined Hamming distance.
The time required for processing measurement data is reduced. The data processing device, according to the present disclosure, acquires reception intensity data representing a reception intensity of signals reflected at measurement points located at distances from the target vehicle for each of multiple distances. It identifies a short-range measurement point that is within a first predetermined distance from the target vehicle. If the short-range measurement point meets predetermined data reduction conditions, it specifies the data corresponding to the distance within a second predetermined distance from the target vehicle, among data indicated in the reception intensity data, as the data to be analyzed.
A semiconductor device is provided, the semiconductor device including: a RAM which stores an encryption key; a secure CPU which is permitted to access the encryption key stored in the RAM; and a first non-secure CPU which is connected to the RAM via a key access protect module and has a first user ID. The key access protect module stores user ID information of a non-secure CPU which is permitted to access the encryption key stored in the RAM, in association with the encryption key. When the first non-secure CPU tries to access the encryption key stored in the RAM, if the stored user ID information and the first user ID match each other, the key access protect module permits the first non-secure CPU to access the encryption key.
A semiconductor device capable of reducing power consumption is provided. The nMOS transistor MNo inputs the external power supply voltage Vcc into the drain and outputs the internal power supply voltage Vdd from the source. The charge pump circuit CP inputs the external power supply voltage Vcc and generates a boosted power supply voltage Vcp higher than it. The reference voltage generation circuit VREFG1 uses a replica nMOS transistor MNr formed by the same manufacturing process as the nMOS transistor MNo to generate a first reference voltage Vref1 reflecting the characteristic variations of the nMOS transistor MNo. The voltage regulator circuit VREGb applies a gate voltage VGn determined based on the first reference voltage Vref1 to the gate of the nMOS transistor MNo.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
36.
METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR WITH INTEGRATED BURIED OXIDE AND P-SHIELD LAYERS
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type, having an upper surface and a bottom surface. A drift layer of the first conductivity type is positioned on the upper surface of the semiconductor substrate. A pair of source regions of the first conductivity type is disposed on the drift layer. A first semiconductor region of the first conductivity type disposed on a center portion of the drift layer is sandwiched between the pair of source regions. Laterally abutting a bottom portion of the first semiconductor region is a pair of second semiconductor regions of a second conductivity type opposite to the first conductivity. Embedded within the first semiconductor region is a third semiconductor region of the second conductivity type. An oxide layer is located, at least partially, within the first semiconductor region, extending above an upper surface of the first semiconductor region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A discharge transistor is formed on a semiconductor substrate, and controls a power transistor to the OFF state by short-circuiting a gate of the power transistor and a reference node when being controlled to the ON state. A reverse current detection circuit detects generation of a reverse current from a power output terminal toward a power supply terminal, and asserts a reverse current detection signal in a period in which a reverse current is generated. A switch control circuit controls a first switch to the ON state and a second switch to the OFF state during the negation period of the reverse current detection signal, and controls the first switch to the OFF state and the second switch to the ON state during the assertion period of the reverse current detection signal.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
38.
SINGLE PIN IMPEDANCE MEASUREMENT SYSTEM AND PHASE OFFSET COMPENSATION FOR A SINGLE PIN IMPEDANCE MEASUREMENT SYSTEM
An impedance measurement system including: a signal generator including a memory and arranged to generate a digital test signal and at least one digital demodulation signal based on the memory, wherein the digital test signal has a first frequency and the at least one digital demodulation signal has the first frequency; a single pin for providing to a Device Under Test (DUT), an analogue test signal based on the digital test signal and measuring, in response to providing the analogue test signal to the DUT, an analogue input signal; and a demodulator configured to obtain: a first filtered digital signal based on the input signal; and the at least one digital demodulation signal to produce at least one digital demodulated signal indicative of the impedance.
A System of a wearable device powered by a battery and built to emit a digital pulse signal and a static device built to process a multilateration of the wearable device, wherein the static device comprises:
at least two receivers, both built to receive the digital pulse signal with a time difference caused by their individual distance to the wearable device;
a multilateration stage built to process a multilateration of the wearable device based on the time difference between the two received digital pulse signals;
a static device communication stage built to communicate commands and/or data with the wearable device,
and wherein the wearable device comprises:
a transmitter stage built to transmit the digital pulse signal composed of several ranging rounds, each with a sequence of digital pulses, and sleep mode periods without digital pulses between the ranging rounds,
which wearable device comprises:
a measurement stage built to measure a current provided by the battery of the wearable device to a capacitor of the wearable device, which capacitor is dimensioned that its capacitor load of the fully charged capacitor powers the wearable device during one ranging round;
a determination stage built to determine a charge time needed to fully charge the capacitor until the end of the sleep mode period based on the capacitor size and the measured current;
a wearable device communication stage built to communicate a request for a minimum extended time slot duration with the static device communication stage to fully charge the capacitor with the measured current until the end of each sleep mode period, if the determined charge time needed is longer than the duration of the sleep mode period between ranging rounds.
A semiconductor device includes a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and a plurality of FF circuits corresponding to the plurality of data lines. The semiconductor device further includes a memory array circuit including an input circuit that is supplied with a high voltage during writing and writes data to the memory cell connected to the corresponding data line according to data held in the FF circuit. The semiconductor device further includes a memory controller that supplies a data string having a number of pieces of data corresponding to a number of FF circuits to the input circuit and causes the FF circuit to hold the data string. The memory controller includes a pop counter circuit that counts a number of pieces of inverted data included in the data string, and the memory controller divides the FF circuit into a plurality of regions based on counting by the pop counter circuit so that the number of FF circuits that store inverted data is equal to or less than a predetermined number. The input circuit is controlled to select the plurality of regions at different timings and simultaneously write data held in the FF circuits arranged in the selected regions.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
41.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A gate electrode is formed in a trench. An insulating film is formed on the gate electrode so as to protrude from an upper surface of a semiconductor substrate. A sidewall spacer is formed on a side surface of the insulating film and on the upper surface of the semiconductor substrate. A hole is formed in a portion of the semiconductor substrate exposed from the insulating film and the sidewall spacer. A barrier metal film is formed in the hole. A second opening width of the hole at a second position, corresponding to a position of a junction surface between a body region and a source region, is larger than a first opening width of the hole at a first position, corresponding to a position of the upper surface of the semiconductor substrate. The barrier metal film includes a silicide film and a metal film.
A steering device for a vehicle. The device includes one or more sensors configured to detect a plurality of hand motions from an operator of the vehicle and one or more circuits coupled to the one or more sensors. The one or more circuits are configured to adjust one or more elements of the vehicle based on a hand motion detected such that the operator of the vehicle can adjust the operation of the vehicle.
A semiconductor structure includes a semiconductor substrate of a first conductivity type. The semiconductor substrate can have an upper surface and a bottom surface. The semiconductor substrate can be made of polycrystalline silicon carbide. The semiconductor structure can further include a drift region of the first conductivity type located on the upper surface of the semiconductor substrate. The semiconductor structure can further include a first region of the upper surface of the semiconductor substrate including a formation region of a transistor, and a second region of the upper surface of the semiconductor substrate, adjacent to the first region, including a formation region of a Schottky barrier diode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
A method for controlling a semiconductor device capable of ensuring robust security is provided. The method is implemented by a semiconductor device comprising an encryption key protection circuit, a processor, and a memory. It includes instructing, by the processor, the encryption key protection circuit to generate an encryption key pair, generating, by the encryption key protection circuit, the encryption key pair internally according to the instruction, encrypting, by the encryption key protection circuit, the generated encryption key pair using a common key, storing, by the processor, the encrypted encryption key pair output from the encryption key protection circuit into the memory, receiving, by the encryption key protection circuit, the encrypted encryption key pair stored in the memory when utilizing the encryption key pair, and decrypting, by the encryption key protection circuit, the encrypted encryption key pair received from the memory using the common key.
A debug system is disclosed. The debug system includes a server in communication with a host device, a physical hardware device and a simulation environment. The server is configured to determine a first debug target that includes one of the physical hardware device and the simulation environment, receive a command from the host device that has a first format generated by the host device, convert the first format to a second format that corresponds to the first debug target and transmit the command to the first debug target in the second format. The server is configured to receive a selection of a second debug target that includes the other of the physical hardware device and the simulation environment, convert the first format to a third format that corresponds to the second debug target and transmit the command to the second debug target in the third format.
G06F 3/023 - Arrangements for converting discrete items of information into a coded form, e.g. arrangements for interpreting keyboard generated codes as alphanumeric codes, operand codes or instruction codes
A design system includes a server in communication with a host device. The server is configured to obtain a compatibility request to perform a compatibility analysis from a design interface presented to a user of the host device by a web browser of the host device. The compatibility request includes design information corresponding to a plurality of blocks of an embedded hardware system design. The server is configured to execute the compatibility analysis based on the design information and a compatibility matrix including compatibility information for each of the plurality of blocks, determine that a given block of the plurality of blocks is not compatible with at least one other block of the plurality of blocks based on the compatibility analysis and transmit a response to the host device. The response includes an indication that the given block is not compatible with the at least one other block.
A system dynamically deploys an application in any of a first domain, a second domain, and a third domain to which a computing resource is allocated. The system has a judgement unit and a determination unit. The judgement unit judges a resource use rate of each domain. The determination unit determines a redeployment destination of “App C” deployed in the first domain higher in the resource use rate than a first standard. Based on information about a future fluctuation of a usage amount of the computing resource in each domain, the determination unit determines, as a redeployment destination, the third domain expected so that the usage amount does not increase.
A semiconductor device includes a wiring layer, a dielectric layer covering the wiring layer, a thin film resistor provided on the dielectric layer, and a plug electrode connecting the thin film resistor to the wiring layer. The plug electrode includes a barrier layer and a buried layer. The buried layer is configured by the filling portion filling a region surrounded by a first incline surface, and an extension portion extending from the filling portion along a second incline surface. The thin film resistor is in contact with the filling portion and the extension portion of the plug electrode. A second incline angle between the second incline surface and a main surface of a semiconductor substrate is smaller than a first incline angle between the first incline surface and the main surface of the semiconductor substrate.
H10D 1/47 - Resistors having no potential barriers
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01C 17/12 - Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thin-film techniques by sputtering
A latch circuit has a first invertor circuit and a second inverter circuit. The latch circuit further has a third pMOS transistor and a third nMOS transistor that are connected between the first invertor circuit and the second invertor circuit. A write port circuit is configurated by a transfer gate made of a fourth pMOS transistor and a fourth nMOS transistor, and transfers a write data to an inverted-side storage node. A read port circuit is configurated by a transfer gate made of a fifth pMOS transistor and a fifth nMOS transistor, and transfers read date from a non-inverted-side storage node.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
An LDMOSFET is formed at a main surface of a semiconductor substrate. The LDMOSFET includes an n-type drain region, an n-type source region, an n-type drift region, a first p-type well region, and a second p-type well region, all formed in an n-type semiconductor layer. The n-type drift region is in contact with a bottom surface of the n-type drain region, the second p-type well region is in contact with a bottom surface of the n-type source region, and the first p-type well region is in contact with a bottom surface of the n-type drift region and a bottom surface of the second p-type well region. A p-type impurity concentration in the first p-type well region is lower than a p-type impurity concentration in the second p-type well region and is lower than an n-type impurity concentration in the n-type semiconductor layer.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
51.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Improve a breakdown voltage and reliability of a semiconductor device. A plurality of semiconductor elements is formed in a cell region. A termination region surrounds the cell region in plan view. In a semiconductor substrate of the termination region, a p-type RESURF region is formed to reach a predetermined depth from an upper surface of the semiconductor substrate. The RESURF region is annularly formed in the termination region to surround the cell region in plan view. The RESURF region contains boron as an impurity.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
52.
DEVICE FOR PROTECTING DATA AND METHOD FOR PROTECTING DATA
Apparatus and method for protecting data frames at a transmission side of a frame-based communication link are described. The apparatus includes a cipher suite module. The cipher suite model receives the data frame and protects the data frame based on a first cryptographic key if the data frame is a priority data frame and protects the data frame based on a second cryptographic key if the data frame is a non-priority data frame. The non-priority data frame is a data frame for which transmission can be interrupted by a data frame that is the priority data frame. After protecting the data frame, the cipher suite module provides the protected data frame for transmission over the frame-based communication link.
A detection transistor is configured to be turned on when a counter electromotive voltage is generated at a power output terminal and then a source voltage changes in conjunction with the counter electromotive voltage. A clamp element configured to limit a gate voltage of the detection transistor to a predetermined clamp voltage with reference to the voltage of the power output terminal. A gate connection circuit comprises a resistance element configured to connect the power output terminal to the gate of the detection transistor, and an nMOS transistor configured to apply a ground power supply voltage to the gate of the detection transistor and cut off a current in a direction from the gate of the detection transistor toward the ground power supply voltage.
H03K 17/081 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
54.
SEAMLESS SWAPPING OF CHARGER FORWARD AND REVERSE MODES
Systems and methods for operating a battery charger are described. A controller can operate a battery charger under a forward mode. Under the forward mode, a power supply is connected to the battery charger to provide power to a load and to charge a battery. The controller can determine an anticipation of removal of the power supply. In response to determining the anticipation, the controller can enable a reverse mode of the battery charger. When the reverse mode is enabled, the power supply remains connected to the battery charger to provide power to the load and charging of the battery is suspended. The controller can further determine at least one configuration of the reverse mode of the battery charger.
A first chip mounting portion and a third chip mounting portion are electrically connected to each other via a first resistor element, and a second chip mounting portion and the third chip mounting portion are electrically connected to each other via a second resistor element.
A semiconductor device capable of generating a correct over-temperature detection signal for an output transistor even when a revers current from the load to the output transistor occurs. A temperature sensing diode is formed on a semiconductor substrate adjacent to the power transistor, generating a forward voltage with a magnitude reflecting a temperature of the output transistor. An over-temperature detection circuit detects over-temperature of the power transistor by comparing a magnitude of the forward voltage with a reference voltage and asserts an over-temperature detection signal. A reverse current detection circuit detects an occurrence of the reverse current in the power transistor and asserts a reverse current detection signal during occurrence period. The semiconductor device uses the reverse current detection signal to perform processes such as masking the over-temperature detection signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
G01K 3/00 - Thermometers giving results other than momentary value of temperature
Described herein is a circuitry for use with an inductive sensor. The inductive sensor comprises: a transmitter coil and two back-to-back connected receiver coils for receiving signals induced by a magnetic field generated by the transmitter coil when excited; and a movable conductive target for influencing the magnetic field. In particular, the circuitry is configured for generating a sequence of pulses for discontinuously exciting the transmitter coil.
G01D 5/22 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature differentially influencing two coils
A current sensor for use with a current carrying conductor, the current sensor including: a magnetic field sensing element; a circuit coupled to the magnetic field sensing element and configured to provide a first signal associated with a current value via the magnetic sensing element, the current value having an unknown error; and a processor configured to execute a machine learning algorithm to generate an adjusted current value.
A register set control system of the present disclosure judges whether each of a plurality of register sets included in a processor is normal or note, and updates state information representing that each register set is normal or not based on a result of the judgement. In addition, the register set control system selects the register sets, which are utilized for an interrupt processing by the processor, from among the register sets indicated as normality in the state information.
A semiconductor device includes a pulse input circuit including flip-flops constituting each of two front-stage counters having different holding states from each other and configured such that first pulses from an even-stage ring circuit are input to each of the two front-stage counters, an edge detection circuit configured to detect edges of outputs of the two front-stage counters and output a second pulse having a predetermined pulse width larger than a predetermined value based on the edge, and a counter circuit including a rear-stage counter to which the second pulse is input. The edge detection circuit is configured to output the second pulse or a stepwise signal when a pulse width of the first pulse is smaller than the predetermined value.
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03K 23/54 - Ring counters, i.e. feedback shift register counters
61.
ANALOG-TO-DIGITAL CONVERSION CIRCUIT AND AN ANALOG-TO-DIGITAL CONVERSION METHOD
To provide an analog-to-digital conversion circuit capable of shortening conversion time. An analog-to-digital conversion circuit comprising: a window comparator connected to an analog input circuit; and a comparator connected to the analog input circuit and a digital-to-analog conversion circuit, and a successive approximation register analog-to-digital conversion circuit connected to the window comparator. The successive approximation register analog-to-digital conversion circuit detects the detection range of the window comparator and converts the upper m (m is a natural number) bits using the window comparator.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
62.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
To improve performance of a semiconductor device. A semiconductor device includes a wiring substrate, a semiconductor chip mounted on a first upper surface of the wiring substrate, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring includes a first portion arranged to continuously surround a periphery of the semiconductor chip in plan view and adhering to the first upper surface of the wiring substrate, and a second portion connected to the first portion and arranged at a position spaced away from the first upper surface of the wiring substrate in plan view. The second portion of the stiffener ring partially overlaps the electronic component.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
Semiconductor devices and processes for manufacturing semiconductors are described. A semiconductor device can include a drift region formed on a Silicon Carbide substrate. The semiconductor device can include a trench that penetrates through a source region and a channel and reaches the drift region. The semiconductor device can include an oxide region lining the trench. The oxide region can include a bottom portion, a lower side portion and an upper side portion. A thickness of the bottom portion and a thickness of the lower side portion can be greater than a thickness of the upper side portion. The semiconductor device can include a gate electrode formed in the trench lined with the oxide region. The semiconductor device can include a shield region in contact with a bottom portion of the trench. A width of the semiconductor region can be less than or equal to a width of the trench.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor device having an improved bonding reliability of wire bonding is provided. The semiconductor device includes a semiconductor chip, a die pad, an inner lead, and a bonding wire. The semiconductor chip has a first lower surface, and a bonding pad provided on a first upper surface. The bonding pad has a second upper surface. The die pad has a third upper surface. The inner lead has a fourth upper surface. The semiconductor chip is mounted on the die pad such that the first lower surface faces the third upper surface. The bonding pad and the inner lead are electrically connected to each other via the bonding wire. In cross-sectional view, the second upper surface, to which the bonding wire is connected, of the bonding pad is located at the same height as the fourth upper surface, to which the bonding wire is connected, of the inner lead.
An inspection is performed to a semiconductor device including a source region formed on an upper surface side of a semiconductor substrate, a drain region formed on a lower surface side of the semiconductor substrate, a trench formed on an upper surface, and a gate electrode and a field plate electrode that are formed in the trench. In the inspection, the source electrode and the drain electrode are fixed to a ground potential, an offset voltage is applied to the field plate electrode, and a screening voltage is applied to the gate electrode. Consequently, insulation properties between the source region and the gate electrode and insulation properties between the gate electrode and the field plate electrode are inspected.
A semiconductor device capable of suppressing a bonding defect between a bump of a semiconductor chip and a land of a wiring substrate is provided. The semiconductor device includes the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a wiring layer, a protective film, a first bump and a second bump. The wiring layer is formed on the semiconductor substrate and has a first bonding pad and a second bonding pad. The first bonding pad has a first upper surface. The second bonding pad has a second upper surface. The protective film is formed on the wiring layer so as to cover the first bonding pad and the second bonding pad. The protective film has a first opening portion overlapping the first bonding pad and penetrating through the protective film, and a second opening portion overlapping the second bonding pad and penetrating through the protective film.
A content addressable memory includes a cell array capable of storing a plurality of data entries, a plurality of valid cells provided for each of the data entries and configured to store valid bits indicating valid or invalid of the data entry, an All-invalid detection circuit configured to detect that the plurality of valid bits all indicate invalid, a search unit configured to determine matching or mismatching between the plurality of data entries and search data, and a control unit configured to stop the search unit when the All-invalid detection circuit detects that the valid bits all indicate invalid.
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
G11C 16/26 - Sensing or reading circuitsData output circuits
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type. The semiconductor structure further includes a drift layer of the first conductivity type located above the semiconductor substrate, a channel layer of a second conductivity type located above the drift layer, and a source region of the first conductivity type located above the channel layer. The second conductivity type is opposite to the first conductivity type. A plurality of trenches penetrates through the source region, the channel layer and a portion of the drift region. A gate electrode is located within each of the plurality of trenches via a gate insulating film and a plurality of shielding structures of the second conductivity type is located around the gate electrode. The plurality of shielding structures covers sidewalls and a bottom of the plurality of trenches. The plurality of shielding structures is arranged in an island-like manner.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
To provide a semiconductor device capable of appropriately controlling temperature and its temperature control method. The semiconductor device according to the present disclosure includes a peripheral circuit, a CPU including a low breakdown voltage transistor for controlling the peripheral circuit, a temperature sensor including a high breakdown voltage transistor higher than the low breakdown voltage transistor, which outputs an analog signal indicating the measured temperature, an A/D converter including the high breakdown voltage transistor for converting the analog signal from the temperature sensor into a digital signal, and a control circuit including the high breakdown voltage transistor, which controls the peripheral circuit without passing through the CPU when the measured temperature indicated by the digital signal from the A/D converter exceeds a threshold temperature.
A semiconductor device includes an insulating film, a metal film, and an adhesion intermediate film arranged between the insulating film and the metal film, and the adhesion intermediate film includes a first adhesion layer, a stress control layer, a second adhesion layer, and a barrier metal layer, which are mutually different and are arranged sequentially in a direction from the insulating film toward the metal film. The insulating film may contain silicon oxide.
A built-in self-test (BIST) system for an electronic circuit is provided. The system includes test circuitry and a clock circuit. The test circuitry applies a test procedure to the electronic circuit. The clock circuit is configured to provide a clock signal to the test circuitry and to adjust a clock frequency of the clock signal.
A semiconductor substrate includes a p-type substrate region, an n-type buried layer on the p-type substrate region, and a p-type semiconductor layer on the n-type buried layer. A DTI region is formed in a trench that penetrates through the p-type semiconductor layer and the n-type buried layer, reaching the p-type substrate region. A plurality of scallops are formed at a side surface of the trench. A size of each of a plurality of first scallops formed at the side surface of the trench in the p-type semiconductor layer is larger than a size of each of a plurality of second scallops formed at the side surface of the trench in the n-type buried layer.
A manufacturing method of a semiconductor device capable of improving the accuracy of overcurrent detection is provided. The manufacturing method of a semiconductor device includes a semiconductor wafer testing process includes a first testing process to determine the resistance variation rate of the replica resistor due to manufacturing variations when manufacturing the semiconductor wafer, and a setting process to determine the variation value of the reference current based on the resistance variation rate determined in the first testing process and set the current value of the current circuit to reduce the variation value.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A reliability of a semiconductor device can be improved by measuring a value of a current flowing through a power transistor accurately. A semiconductor chip includes a power transistor and a source electrode electrically connected to a source region of the power transistor. The source electrode and a lead terminal are electrically connected to each other via a wire. The source electrode includes detection points for detecting the value of the current flowing through the power transistor. The detection points are arranged so as to sandwich a bonding point of the wire bonded to the source electrode.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
An apparatus including an electronic fuse is disclosed. An electronic fuse profile of the electronic fuse can be generated by a circuit of the apparatus. The circuit can set a direct current threshold level for a first region of the electronic fuse profile based at least in part on a first user adjustable parameter, set an over current threshold level for a third region of the electronic fuse profile based at least in part on a third user adjustable parameter and set an integration time constant for a second region of the electronic fuse profile based at least in part on a second user adjustable parameter. The second region can connect the first region to the third region in the electronic fuse profile.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
A semiconductor device of the present disclosure includes a semiconductor substrate having an element formation portion and a composite capacitor formed to surround the element formation portion in plan view. The composite capacitor has a plurality of capacitor elements electrically connected in parallel.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
77.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip has a first semiconductor layer, a second semiconductor layer formed on an upper surface of the first semiconductor layer, and a semiconductor region formed in the second semiconductor layer. A trench is formed in the semiconductor region. An insulating film is formed on each of an upper surface of the second semiconductor layer and an inner surface of the trench. A polysilicon film is formed on the insulating film so as to embed an inside of the trench. A front surface electrode made of metal is formed on the polysilicon electrode, and a back surface electrode made of metal is formed on a lower surface of the first semiconductor layer. An impurity concentration of the second semiconductor layer located between the semiconductor region and the first semiconductor layer is lower than an impurity concentration of each of the first semiconductor layer and the semiconductor region.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
Semiconductor devices, packages, and structures are described. A semiconductor structure can include a plurality of BGA pads, where a plurality of BGA balls are attached to a first surface of the plurality of BGA pads. The semiconductor structure can further include a layer of dielectrics deposited on a second surface of the plurality of BGA pads. The second surface can be opposite from the first surface. The semiconductor structure can further include at least one floating structure deposited on the layer of dielectrics. The at least one floating structure and at least two of the plurality of BGA pads can form at least two capacitors that are connected within the interposer.
H01L 23/488 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions
Provided is a semiconductor device that suppresses an increase in an area and current of a PLL. An ADPL and an SPLL are included, and an SPD that compares an input signal with a feedback signal from a CCO, a charge pump circuit that outputs a current or a voltage based on a result of the SPD, a PFD that detects a phase difference which is a comparison result between the input signal and the feedback signal, and a phase difference digitizer that changes the current output by the charge pump circuit based on a detection result of the PFD are included.
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
H03L 7/091 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
80.
SEMICONDUCTOR DEVICE INCLUDING ELECTRIC FUSE AND RESISTOR ELEMENTS AND MANUFACTURING METHOD THEREOF
An electric fuse element has a first portion, a second portion arranged on one end of the first portion, and a third portion arranged on the other end of the first portion. A resistor element is arranged separately from the electric fuse element. A material of each of the electric fuse element and the resistor element has silicon metal or nickel chromium. The electric fuse element and the resistor element are arranged in an upper layer of the first wiring and in lower layer of the second wiring. A wiring width of the second portion and a wiring width of the third portion are larger than a wiring width of the first portion.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
81.
SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING THE SAME
Without causing characteristic variations in paired elements, the increase in development cost and development period is suppressed. A plurality of MOS units 30 are arranged adjacent to each other on a main surface of a semiconductor substrate in a plan view, each of the plurality of MOS unit is comprised of at least one MOSFET and has same structure. Above the plurality of MOS units 30, a multilayer wiring layer is formed. In an uppermost wiring layer of the multilayer wiring layer, wiring M8 is formed. Each of the plurality of MOS units 3Q includes MOS unit 10 and MOS unit 20, which constitute a part of the differential circuit as paired elements. The coverage rate of MOS unit 10 covered by wiring M8 is the same as the coverage rate of MOS unit 20 covered by wiring M8 in the plan view.
H01L 23/528 - Layout of the interconnection structure
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 115/08 - Intellectual property [IP] blocks or IP cores
G06F 117/12 - Sizing, e.g. of transistors or gates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
82.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, an element region containing a semiconductor element and a peripheral region surrounding the element region in plan view. The semiconductor substrate in the peripheral region includes an N-type drift layer, an N++ type channel stop layer disposed on the upper surface side relative to the N-type drift layer, which channel stop layer is at least one annular N++ type channel stop layer surrounding the element region, and an N type guard ring layer disposed on the upper surface side relative to the N-type drift layer.
A semiconductor device includes a protection transistor connected between a power supply and GND, a trigger circuit configured to detect an application of ESD and output a drive signal to a gate of the protection transistor, and a switch provided between the power supply or the GND and the gate of the protection transistor and configured to electrically connect the power supply or the GND and the gate of the protection transistor when the ESD is applied to the GND.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A learning support device includes: an image acquisition unit acquiring a plurality of defective circuit images representing a circuit layout causing a defect extracted from an existing circuit layout and a plurality of normal circuit images representing a normal circuit layout; a virtual image acquisition unit inputting each of the plurality of defective circuit images into a generative AI (artificial intelligence), and acquiring a plurality of virtual images generated based on the plurality of defective circuit images by using the generative AI; a learning processing unit inputting the plurality of defective circuit images, the plurality of virtual images, and the plurality of normal circuit images as training data into a classification AI; and an output unit outputting a classification AI 150 having already learned.
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
Provided is a memory repair circuit including a memory built-in self-test (MBIST) circuit that generates a repair code on the basis of a test result in a market, a register that holds the generated repair code, and a path for transmitting the repair code to a repair circuit. The memory repair circuit may include a logical circuit that performs a logical operation of a repair code generated at the time of mass production and a repair code based on the test result in the market.
A method of manufacturing a semiconductor device is provided, the method including: forming an insulating film on a semiconductor substrate; selectively removing the insulating film; forming a metal film on the semiconductor substrate by leaving a damage layer of a surface of the semiconductor substrate, the damage layer being generated when the insulating film is selectively removed; forming an electrode by selectively removing the metal film; and forming polyimide on the electrode. The damage layer of the surface of the semiconductor substrate, which is generated when the insulating film is selectively removed, may be selectively removed.
An inspection method of a semiconductor device includes inspecting the semiconductor device that is included in a sample placed on a stage of an inspection apparatus. The stage includes a temperature adjustment unit. The temperature adjustment unit includes a plurality of temperature adjustment elements. The plurality of temperature adjustment elements are arranged in a plane parallel to a stage surface of the stage where the sample is placed, and a size of each of the plurality of temperature adjustment elements is smaller than or equal to a size of the semiconductor device in a plain view.
A semiconductor device includes a plurality of sample-and-hold circuits that sample voltages of an analog input signal at different timings and respectively hold them as a plurality of input voltages, a ramp signal generation circuit that generates a ramp signal whose potential changes linearly, a counter that triggers a start of the linear change in the ramp signal and perform a counting operation, a plurality of AD conversion circuits that output a count value of the counter at a timing where each of the plurality of input voltages matches the voltage of the ramp signal as a plurality of digital signals corresponding to the plurality of input voltages, and a control circuit that controls a slope of the linear change in the ramp signal and the amount of change in the count value of the counter according to the count value of the counter.
H03M 1/08 - Continuously compensating for, or preventing, undesired influence of physical parameters of noise
G06F 3/0354 - Pointing devices displaced or positioned by the userAccessories therefor with detection of 2D relative movements between the device, or an operating part thereof, and a plane or surface, e.g. 2D mice, trackballs, pens or pucks
G06F 3/038 - Control and interface arrangements therefor, e.g. drivers or device-embedded control circuitry
89.
DETECTION OF TVOCs, OZONE AND NOx CONCENTRATIONS USING A METAL-OXIDE GAS SENSOR ARRAY
An apparatus is provided that includes one or more first MOx sensors, one or more second MOx sensors, and one or more humidity and/or temperature sensors configured to detect, identify, and quantify a first gas, a second gas, and a third gas, where the first gas is a TVOC, the second gas is NO2, and the third gas is O3. At least one processor can be configured to receive resistance data, humidity data and temperature data from the one or more first MOx sensors, the one or more second MOx sensors, and the one or more humidity and/or temperature sensors. The at least one process can run a pre-trained or continuously learning neural network, or other machine learning models, to detect, identify, and quantify the first gas, the second gas, and the third gas, while mitigating humidity, temperature, and O3 influence on the overall output performance.
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
G01N 27/04 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance
90.
EMBEDDED CAPACITORS IN FINGER CONNECTORS FOR CROSSTALK CANCELLATION
Semiconductor devices are described herein. A semiconductor device can include a semiconductor package including a plurality of circuits and a plurality of connectors configured to facilitate signal transmission between the semiconductor package and a device when the semiconductor package is connected to the device via the plurality of connectors. At least a first connector among the plurality of connectors can be embedded with a capacitor. The capacitor embedded in the first connector can be connected to a second connector among the plurality of connectors.
A semiconductor device capable of improving the performance of an electrostatic protection circuit is provided. In semiconductor device 1, when trigger circuit 10 and trigger circuit 20 do not detect the application of ESD, switch SW11 electrically connects power node N12 and power node N13, switch SW12 electrically disconnects power node N11 and power node N13, switch SW13 electrically disconnects power node N12 and power node N14, and when trigger circuit 10 and trigger circuit 20 detect the application of ESD, switch SW11 electrically disconnects power node N12 and power node N13, switch SW12 electrically connects power node N11 and power node N13, and switch SW13 electrically connects power node N12 and power node N14.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
92.
SYSTEM AND METHOD FOR LIVE MONITORING OF EMBEDDED INFERENCE MODULES
A system and method are provided for monitoring inferences performed by a microcontroller (MC) in real time. An inference module embedded on the MC analyzes a data set and generates a determination value, then transmits a determination data payload representing the determination value and, in some embodiments, the data set to a monitoring subsystem. The inference module may be an AI module, which may be trained on data sets previously transmitted from the MC. The monitoring subsystem may visually represent the determination value on a user interface, generate a verification value to test the determination value for accuracy, and store the determination data payload to a memory for later refinement of the inference module.
An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
An electronic device includes a mounting board, a semiconductor device mounted on the mounting board, and a plurality of electronic components mounted on the mounting board. The semiconductor device is electrically connected to the mounting board via a plurality of terminals arranged in a grid on the wiring substrate. The terminals include a plurality of power supply terminals that is capable of supplying a power supply potential to a first circuit of the semiconductor chip. Each of the electronic components EC1 has a passive element and is electrically connected to any of the power supply terminals. At least four or more of the power supply terminals are arranged in an outermost row of the terminals, which is arranged in the grid, such that the four or more power supply terminals are arranged next to each other, and such that the four or more power supply terminals are arranged continuously.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H05K 1/11 - Printed elements for providing electric connections to or between printed circuits
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
An apparatus includes a memory slot including a certificate chain corresponding to an entity and a memory block. The memory block has protection enabled. The apparatus includes a processing device. The processing device is configured to receive a request message to clear protection for the memory block from a computing device of the entity. The request message includes a signature generated based at least in part on a private key of the entity. The processing device is configured to determine a public key corresponding to the entity based at least in part on the certificate chain, determine that the signature is valid based at least in part on the public key, determine that the protection for the memory block corresponds to the certificate chain and clear the protection for the memory block.
Semiconductor devices for synchronizing networks are described. The semiconductor device includes a timing circuit having a sub-sampling phase lock loop. The sub-sampling phase lock loop includes a radio frequency sampler circuit that is configured to generate at least one error signal corresponding to a phase difference between an output signal of a voltage-controlled oscillator and a reference signal and a transconductor circuit that is configured to generate a tuning signal based on the at least one error signal. The tuning signal is configured to tune the voltage-controlled oscillator. The sub-sampling phase lock loop further includes an adaptive bias circuit that is configured to generate a nulling signal based on an offset in the tuning signal created by the transconductor circuit and provide the nulling signal to the transconductor circuit. The transconductor circuit is configured to adjust the tuning signal based on the nulling signal.
A low-power oscillator maintains its oscillation frequency regardless of environmental conditions. The oscillator includes a reference current source, a voltage source and a ring oscillator. The reference current source outputs a reference current depending on a first power supply voltage, and the voltage source outputs a second power supply voltage depending on the reference current. The oscillation frequency of the ring oscillator depends on the second power supply voltage.
Systems for inductive positioning sensing are described. A transmission coil can generate a magnetic field. A first set of receiver coils can pick up first voltage signals from the magnetic field. A second set of receiver coils can pick up second voltage signals from the magnetic field. The first and second inductive sensors can have a fixed relation. An integrated circuit (IC) can multiplex the first and second voltage signals to process one of the first and second voltage signals using one channel at a time. The IC can convert the first voltage signals into a first digital parameter and convert the second voltage signals into a second digital parameter. The IC can output the first and second digital parameters to trigger at least one plausibility checker to determine whether the first angle position and the second angle position satisfy or fail to satisfy the fixed relation.
G01D 5/20 - Mechanical means for transferring the output of a sensing memberMeans for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for convertingTransducers not specially adapted for a specific variable using electric or magnetic means influencing the magnitude of a current or voltage by varying inductance, e.g. by a movable armature
99.
FREQUENCY CORRECTION LOOP WITH DEADZONE AND HYSTERESIS
Semiconductor devices for synchronizing networks are described. A semiconductor device can include a phase lock loop of a timing circuit. The phase lock loop includes a voltage-controlled oscillator, a sub-sampling phase lock loop circuit and a frequency correction loop circuit. The frequency correction loop circuit is configured to activate a charge pump to inject a charge into the voltage-controlled oscillator based on a phase difference between a reference signal and a feedback signal being greater in magnitude than a deadzone delay parameter plus a hysteresis delay parameter and de-activate the charge pump based on the magnitude of the phase difference between the reference signal and the feedback signal falling below the deadzone delay parameter.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/107 - Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
A manufacturing method of a semiconductor device includes preparing a semiconductor substrate having an upper surface and a lower surface, forming a first mask having a plurality of openings on the upper surface divided into a first region and a second region, forming a second mask that exposes a portion of the first mask arranged in the first region and covers a portion arranged in the second region, etching the semiconductor substrate in the first region using the first mask and the second mask as a mask, removing the second mask, and etching the semiconductor substrate in the first region and the second region using the first mask as a mask.
