A method of controlling a multilevel power converter may include measuring an input voltage at a converter input, determining a half input voltage based on the input voltage; measuring a flying capacitor voltage across the flying capacitor; determining an error voltage based on a difference between the flying capacitor voltage and the half input voltage; generating an inductor current window having an inductor peak current and a valley inductor current; modulating the inductor peak current into an upper inductor peak current and a lower inductor peak current based on the error voltage; and operating the multilevel power converter to produce an output current through an inductor to a converter output, the output current being within the inductor current window and based on a sequence of pulse width modulation states.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
2.
SERIES ADDRESSING SCHEME FOR SMART POWER STAGES OF HIGH CURRENT APPLICATIONS
A semiconductor system includes a plurality of power drivers, a voltage source and a reference potential, and an address signal line electrically coupling the plurality of power driver devices between the voltage source and the reference potential being lower than the voltage source,. Each power driver device is configured to: receive an address-related analog voltage from the address signal line; and derive an address of the power driver device based at least in part on the received analog voltage. The address signal line passes through the plurality of power driver devices.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
3.
BONDED SOI WAFER PROCESS WITH ALIGNED FRONT AND BACK SIDE PATTERNS
A method of forming a semiconductor structure includes forming a first wafer with opposing first and second surfaces. A first pattern and a trench feature are formed on the first surface, with the trench feature extending toward the second surface. A first insulating layer is formed on the first surface of the first wafer lining sidewalls and bottom of the trench feature. An inside of the trench feature is filled with a polysilicon layer via the first insulating layer. The first wafer is bonded to a second wafer having opposed first and second surfaces via the first insulating layer, aligning their first surfaces. The bonded wafers are flipped, and a thinning process is conducted on the second surface of the first wafer forming a third surface. A second pattern is formed on the third surface aligned with the first pattern through the trench feature.
An integrated circuit includes a driver stage and a final stage. The driver stage is configured to receive an input signal and provide an amplified signal. The final stage includes a splitter, a main amplifier, a peak amplifier, a main output matching network, and a peak output matching network. The splitter is configured to receive the amplified signal and split the amplified signal into a main input signal and a peak input signal. The main amplifier is configured to receive the main input signal and provide an amplified main signal. The peak amplifier is configured to receive the peak input signal to provide an amplified peak signal. The main output matching network is coupled to the main amplifier and includes a first series inductor. The peak output matching network is coupled to the peak amplifier and includes a second series inductor.
A semiconductor device provides adjustment of circuit characteristics in the field, improvement of yield without taking excessive margins during shipment testing, and reduction of test costs. The semiconductor device equipped with a ring oscillator, a delay monitor circuit that monitors the delay of the target circuit, a voltage monitor circuit that monitors the driving voltage of the target circuit, a calculation circuit that determines whether the threshold voltage of the delay monitor circuit is appropriate using the voltage monitor circuit, and a storage circuit that stores the adjustment voltage to correct the threshold voltage if it is not appropriate.
To provide a constant current source circuit with reduced temperature dependence without using bipolar transistors. To provide a constant current source circuit comprising: an operational amplifier; a first P-channel MOS transistor having a gate coupled to a output terminal of the operational amplifier; a second P-channel MOS transistor having a gate coupled to the output terminal of the operational amplifier; a first resistor element having a second terminal coupled to an inverting input terminal of the operational amplifier; a second resistor element having a second terminal coupled to a non-inverting input terminal of the operational amplifier; a third resistor element; a first N-channel MOS transistor having a drain coupled to the inverting input terminal of the operational amplifier; and a second N-channel MOS transistor having a gate coupled to the inverting input terminal of the operational amplifier and a drain coupled to the non-inverting input terminal of the operational amplifier.
G05F 3/24 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode-transistor combinations wherein the transistors are of the field-effect type only
7.
DETERMINATION DEVICE, DETERMINATION METHOD, AND DETERMINATION PROGRAM
A determination device, a determination method and a determination program each capable of accurately making determination are provided. The determination device includes: a first filter configured to perform a first filter processing to a measurement value measured by a sensor, based on a first filter property; a first determination section configured to determine a detection state of the sensor by comparing a measurement value subjected to the first filter processing with a first threshold; a second filter configured to perform a second filter processing to the measurement value, based on a second filter property; a second determination section configured to determine a detection state of the sensor by comparing a measurement value subjected to the second filter processing with a second threshold; and an output section configured to output a determination result of the first determination section or a determination result of the second determination section.
A semiconductor device includes a first power supply line configured to transmit a power supply voltage, a second power supply line to which the power supply voltage is supplied via a P type transistor controlled by a processor power control signal from a power supply manager, and an R-FF circuit including a latch circuit and a flip-flop circuit and capable of saving data stored in the flip-flop circuit to the latch circuit by a retention control signal from the power supply manager and retaining the saved data. Here, the flip-flop circuit operates using the voltage on the second power supply line as a power supply voltage, the latch circuit is connected to a signal line configured to transmit the retention control signal by diodes, and the latch circuit operates using a voltage supplied via the diodes as a power supply voltage when it retains the data.
A method for testing a standby current of a semiconductor device is disclosed. The semiconductor device includes a voltage regulator, a power terminal, and a power output terminal. The power terminal is connected to a power supply during testing, and the power output terminal is connected to an external capacitor during testing. The method includes: when switching from the testing in the normal operating mode to the testing in the low power mode, the change of the output voltage of the power output terminal causes the external capacitor to be charged; in the testing in the low power mode, before testing the standby current of the semiconductor device, causing a voltage source disposed between the semiconductor device and the external capacitor to apply a voltage to the power output terminal at the same level as the voltage of the power output terminal in the low power mode.
A RESURF region and a source wiring are each formed annularly in a termination region to surround a cell region in a plan view. An impurity region and the outer peripheral wiring are each formed annularly in the termination region to surround the RESURF region and the source wiring in a plan view. The outer peripheral wiring includes a wide portion provided at a corner of the semiconductor device. In a plan view, the width of the wide portion is wider than the width of the outer peripheral wiring other than the wide portion. An opening is provided in a protective film covering the source wiring and the outer peripheral wiring to expose a part of the wide portion. The part of the wide portion exposed in the opening of the protective film constitutes a pad for connecting an external connection terminal.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes a plurality of amplifiers configured to amplify an input phase‑modulated signal and to generate an output signal by summing respective output voltages, and an amplitude control circuit configured to output a selection signal for switching, among the plurality of amplifiers, a number of amplifiers that are simultaneously controlled to an operating state. A number of stages of change in the number of amplifiers simultaneously controlled to the operating state is defined as a switching stage number. The plurality of amplifiers include at least one first amplifier configured to change a voltage level of the output signal by an amount smaller than a unit amplitude obtained by dividing a maximum amplitude of the output signal by the switching stage number, and at least one second amplifier configured to change the voltage level of the output signal by an amount larger than the unit amplitude.
H03F 3/68 - Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
H03F 1/02 - Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
H03F 1/22 - Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/60 - Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
An electronic system comprising a printed circuit board having a conductive trace that is coupled to a voltage output is provided. A voltage regulator is disposed on the printed circuit board that includes a voltage regulator phase output terminal. Additionally, the electronic system comprises an inductor module coupled with the voltage regulator. The inductor module includes an inductor core and an inductor segment having a first and a second end, where the inductor segment first end is connected to the voltage regulator phase output terminal and the inductor segment second end is connected to the printed circuit board conductive trace. The inductor segment is configured to pass through and wrap around at least a portion of the inductor core and the voltage regulator is configured to transfer heat through the voltage regulator phase output terminal to the inductor segment and the inductor module.
A plurality of conductive patterns formed in a wiring layer of a wiring substrate of a semiconductor device includes: a plurality of bonding fingers which is respectively arranged outside a chip mounting region, and which is arranged in a Y direction; and a plurality of wirings which is respectively connected to a plurality of first bonding fingers of the plurality of bonding fingers. The plurality of conductive patterns includes a fixed potential pattern arranged between adjacent two wirings of the plurality of wirings in a first region, and connected to a transmission path for a fixed potential. The fixed potential pattern arranged between the adjacent two wirings and the plurality of wirings extend so as to across the outer edge of the chip mounting region in a X direction crossing the Y direction.
A metal film, a manufacturing method of the metal film, semiconductor device, and a manufacturing method of semiconductor device are provided with high crack resistance (higher hardness) during wire bonding. The Metal film has first metal crystal grains, and the second metal crystal grains. Each of the first metal crystal grains has dislocations. Each of the second metal crystal grains has no dislocations. The number of the first metal crystal grains having the dislocations is larger than the number of the second metal crystal grains having no dislocations.
An electronic device and a secure electronic apparatus are provided. The electronic device includes a security management system configured to control access to each of a plurality of system components based on a reconfigurable secure enclave definition. A method of controlling access to each of the plurality of system components, based on a reconfigurable secure enclave definition using a security management system of an electronic device, is also provided.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
16.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a MOS capacitive element and a MOS transistor element. The MOS capacitive element includes a first impurity region formed at a main surface of a semiconductor substrate, a first insulating film formed on the main surface of the semiconductor substrate so as to cover the first impurity region, and a first electrode facing the first impurity region with the first insulating film interposed therebetween. The MOS transistor element includes a second impurity region formed at the main surface of the semiconductor substrate, a second insulating film formed on the main surface of the semiconductor substrate so as to cover the second impurity region, and a second electrode facing the second impurity region with the second insulating film interposed therebetween. An impurity concentration in the first electrode is higher than an impurity concentration in the second electrode.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A speed detector receives a Hall signal, and calculates, each time toggling of the Hall signal occurs, a first speed detection value based on a toggle time interval. A speed correction circuit calculates a second speed detection value by correcting the first speed detection value in a decelerating direction during a correction period. The correction period is a period from when the elapsed time from toggling of the Hall signal occurs exceeds the reference time until next toggling of the Hall signal occurs when the toggle time interval based on the first speed detection value at present is set as a reference time. A speed controller calculates a torque command value of a motor based on a speed deviation between the second speed detection value and a preset speed command value.
H02P 21/04 - Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation specially adapted for very low speeds
18.
SEMICONDUCTOR DEVICE AND METHOD FOR CONTROLLING THE SEMICONDUCTOR DEVICE
A semiconductor device and a method of controlling the semiconductor device to capable suppressing access delay from the bus master are provided. The semiconductor device includes a bus master, a bus slave, a bus that connects the bus master and the bus slave via multiple paths, a bus monitor that detects access requests from the bus master to the bus slave, and a selection unit that selects the path through which the bus transfers the access request based on the latency occurring in the multiple paths when an access request is detected.
Improve communication performance between semiconductor devices. The phase detector PHD outputs N-bit phase detection data PD by latching the N-phase clock signals at the edge of the data signal. The phase judgement circuit outputs a phase selection signal indicating the selection of one of the N phases based on the phase detection data PD. The timing adjustment circuit outputs a delayed phase selection signal by delaying the phase selection signal by a delay time determined for each selected phase. The clock selection circuit selects and outputs one of the N-phase clock signals according to the delayed phase selection signal. The data latch circuit latches the data signal with the clock signal selected by the clock selection circuit.
H03L 7/081 - Details of the phase-locked loop provided with an additional controlled phase shifter
H03L 7/089 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
20.
SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
To provide a semiconductor device manufacturing apparatus capable of automatically placing wiring in a layout area accurately and quickly. According to one embodiment, the manufacturing device 50 for a semiconductor device includes an acquisition unit 51 that obtains a wiring cost table, which shows the wiring cost for arranging wiring above and between multiple cells placed in the layout area LA when designing a semiconductor device, classified according to multiple conditions. It also includes a selection unit 52 that selects a wiring cost from the multiple wiring costs shown in the wiring cost table based on predetermined conditions, a setting unit 53 that sets the selected wiring cost above and between each cell, and a calculation unit 54 that calculates the wiring cost of the wiring path where the wiring is arranged based on the set wiring cost.
A method of forming a semiconductor structure includes forming a first insulating layer extending above an upper surface of a doped region and an upper surface of a source region positioned above a drift layer on a silicon carbide substrate. A trench feature penetrates the first insulating layer to reach an upper surface of the drift layer. A gate oxide is formed within the trench feature lining the bottom and sidewalls of the trench. A gate electrode is formed within the trench feature, with a first portion extending vertically above the trench feature and a second portion filling the trench feature. The first insulating layer is selectively removed, and a second insulating layer is formed around the first portion of the gate electrode. The second insulating layer extends partially above the upper surface of the source region and has a dome-like shape.
An energy storage circuit is provided. The energy storage circuit includes a battery module formed of a plurality of battery cells, a current sense resistor, and a controller. Each battery cell is coupled to a corresponding cell resistor via a switch. The controller is operable to arrange the switches in a first configuration to perform an impedance measurement of one or more battery cells in the battery module. In the first configuration the cell resistors are coupled in series with each other and with the current sense resistor.
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
H01M 10/0525 - Rocking-chair batteries, i.e. batteries with lithium insertion or intercalation in both electrodesLithium-ion batteries
H01M 10/42 - Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
H01M 10/48 - Accumulators combined with arrangements for measuring, testing or indicating the condition of cells, e.g. the level or density of the electrolyte
A multiphase power converter is provided. The multiphase power converter includes a plurality of phases, a coupling inductor, and a sensing circuit. Each phase comprises a pair of power switches coupled to a transformer. The coupling inductor is coupled to a transformer of a chosen phase among the plurality of phases. The sensing circuit generates a first parameter related to a current through the coupling inductor.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A processing system is provided with a freedom from interference mechanism. The processing system includes a plurality of master components, a plurality slave components; a bus; and a plurality of slave registers. The processing system assigns a master identification to each master component. Each slave register stores a list of permissible master identifications that allow access to a corresponding slave component. Each slave component has a protection circuit configured to permit or prevent access to the slave component based on the master identification of the master component attempting access.
G06F 21/73 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
Systems and methods for implementing a charge pump with adaptive period shifting is generally described. The method can include sensing an output voltage from a charge pump. The output voltage is equal to a steady state voltage level of the charge pump. The method can further include, based on the sensed output voltage, determining whether the output voltage is within a voltage window centered around an input voltage or outside of the voltage window. The method can further include adjusting a period of a clock signal based on the determination of whether the output voltage is within or outside the voltage window. The clock signal drives the charge pump.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Systems and methods for implementing charge pump power conversion with non-dissipative voltage sensing is described. The device can include a charge pump configured to convert an input voltage into an output voltage. The charge pump can comprise a first phase and a second phase. The device can further include a circuit configured to receive an activation signal. The circuit can, in response to receipt of the activation signal, sample a node voltage being outputted by the second phase. The circuit can output a signal that can indicate whether the output voltage can be within a reference voltage from a steady state voltage of the load or outside of the reference voltage from the steady state voltage of the load.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
Enhance the security resistance of semiconductor memory devices against voltage glitches. The glitch detection circuit outputs a glitch detection signal when it detects voltage fluctuations. The post-detection control circuit outputs a reset request signal requesting the reset operation of the semiconductor device or an interrupt request signal for the processing of the processor when the glitch detection signal is output from the glitch detection circuit.
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
G06F 21/55 - Detecting local intrusion or implementing counter-measures
A method of manufacturing a semiconductor device includes forming a trench at an upper surface of a first semiconductor layer, introducing a first impurity of a first conductivity type into the first semiconductor layer in an element formation region, forming a first impurity region by diffusing the first impurity by heat treatment, forming a second semiconductor layer on the first semiconductor layer by epitaxial growth, introducing a second impurity of the first conductivity type into the second semiconductor layer, forming a second impurity region so as to be connected to the first impurity region by diffusing the second impurity by heat treatment, and forming a semiconductor element on the second semiconductor layer.
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
A semiconductor device includes: a first die pad; a second die pad; a third die pad; a first semiconductor chip arranged on the first die pad; a second semiconductor chip arranged on the second die pad; an insulator arranged on the third die pad via a bonding material; a metal film arranged on the insulator; a first wire; a second wire; and a sealing body sealing these members. The first wire electrically connects a first pad of the first semiconductor chip and the third die pad. The second wire electrically connects a second pad of the second semiconductor chip and the metal film.
An image processing device according to the present disclosure generates a feature map based on an image, determines whether a value of each cell of the feature map is equal to or larger than a lower limit threshold value, calculates an activation value by inputting the value of each cell of the feature map equal to or larger than the lower limit threshold value to an activation function, and generates an existence probability map indicating distribution of existence probability of an object in the image by using the activation value.
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
G06V 10/40 - Extraction of image or video features
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
To improve the temperature measurement accuracy of a semiconductor device. The semiconductor device includes a temperature sensor having a plurality of switches As, a first terminal couped to the temperature sensor via the switches As, a second terminal coupled to the temperature sensor via the switches As, a third terminal coupled to the temperature sensor via the switches As, and a fourth terminal coupled to the temperature sensor via switches As and being supplied with a predetermined voltage VCC. The fourth terminal is capable of coupling with the first terminal, the second terminal, and third terminal via the switches As.
A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed in a semiconductor substrate, a first buried region formed in the first semiconductor layer, a drain region, a drift region, a source region, and a body region formed in the second semiconductor layer, a back-gate region formed in the body region, a gate electrode formed on an upper surface of the semiconductor substrate, and a second buried region formed in the second semiconductor layer and disposed between the first buried region and the body region. A side surface of the second buried region is located between the gate electrode and the drain region in plan view. The second buried region is connected to the body region.
Techniques are provided for suppressing the accumulation of holes in floating region and improving the switching time of a semiconductor device such as an Insulated Gate Bipolar. The semiconductor device includes a trench gate and a trench emitter formed in a semiconductor substrate, and a floating region of a first conductivity type formed in the semiconductor substrate sandwiched between the trench gate and the trench emitter. The bottom of the floating region is located below the bottom of the trench gate and the trench emitter, and the floating region has a crystal defect region including crystal defects selectively formed at a position near an upper surface of the semiconductor substrate in the floating region.
A semiconductor wafer held by a Bernoulli chuck is reliably rotated. A wafer holding apparatus includes: a chuck for holding a semiconductor wafer; and a rotating mechanism for rotating the chuck. On a facing surface of the chuck facing the semiconductor wafer, a plurality of pads and a plurality of support parts are formed. The chuck holds the semiconductor wafer by jetting gas from each of the plurality of pads. The plurality of support parts is formed at positions each deviated from a center of the facing surface of the chuck. When the chuck holds the semiconductor wafer, the plurality of pads is not in contact with the semiconductor wafer while the plurality of support parts is in contact with a principal surface of the semiconductor wafer.
A method of forming a semiconductor structure includes forming a silicon carbide semiconductor substrate of a first conductivity type. A drift layer of the first conductivity type is formed above an upper surface of the semiconductor substrate. A junction field-effect transistor (JFET) region of the first conductivity type is formed above the drift layer with base regions of a second conductivity type positioned on opposite sides of a top portion of the JFET region. Each base region contacts a bottom portion of the JFET region. A hard mask is formed above the top portion of the JFET region located between the base regions. First doped regions of the first conductivity type are formed within the JFET region, at an interface between the base regions and the JFET region, extending into the JFET region such that the first doped regions reduce a width of the top portion of the JFET region.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/834 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
The semiconductor device comprises a first and a second comparator configured to compare an input voltage corresponding to a sense current detected by an output current of a power transistor with a first reference voltage and a second reference voltage respectively, the second reference voltage being lower than the first reference voltage. The semiconductor device further comprises a first and second counter respectively coupled to the first and second comparator and configured to count up and down, an adder circuit coupled to the first counter and the second counter and configured to calculate a total value of count values of the first counter and the second counter, and a detection signal output circuit configured to output a detection signal when the total value of the count values is equal to or greater than a threshold value.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H02H 1/00 - Details of emergency protective circuit arrangements
A semiconductor device includes a plurality of precharge circuits in addition to a plurality of read bit lines through which read data is transferred from a plurality of latch cells in a latch cell array. Each of the plurality of latch cells is composed of 10 or 12 MOS transistors including a first CMOS switch that transfers write data and a second CMOS switch that transfers read data. The plurality of precharge circuits precharges the plurality of read bit lines to an intermediate voltage between a high potential side power supply voltage and a low potential side power supply voltage before the second CMOS switches are controlled to turn on.
Provide a technology that can estimate a propagation length. An evaluation element includes a diffusion layer formed in a semiconductor substrate and a plurality of a pair of contacts electrically connected to the diffusion layer. The plurality of the pair of contacts are separated by a distance in the X direction. A width of the third contacts in the X direction is smaller than a width of a second contacts in the X direction. The width of the second contacts is smaller than a width of the first contacts in the X direction.
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
40.
IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, AND PROGRAM
An image processing device according to the present disclosure generates a second image by executing quantization processing on a first image, generates a feature map based on the second image, generates an existence probability map indicating distribution of existence probability of an object in the first image by using the feature map, performs matching determination processing that is processing of determining whether a value of each cell matches a fixed value for the feature map or the existence probability map, and performs dequantization processing on the feature map or the existence probability map based on a result of the matching determination processing.
G06V 10/75 - Organisation of the matching processes, e.g. simultaneous or sequential comparisons of image or video featuresCoarse-fine approaches, e.g. multi-scale approachesImage or video pattern matchingProximity measures in feature spaces using context analysisSelection of dictionaries
G06V 10/28 - Quantising the image, e.g. histogram thresholding for discrimination between background and foreground patterns
G06V 10/82 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using neural networks
41.
SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING SEMICONDUCTOR DEVICE, AND CONTROL PROGRAM
To provide a semiconductor device, a control method for the semiconductor device, and a control program that can update the initial setting values of the interface circuit after a mask ROM is implemented. The semiconductor device includes an interface circuit, the mask ROM storing initial setting values and an initialization function, a CPU (Central Processing Unit) that sets the initial setting values in the interface circuit by executing the initialization function during initialization, and non-volatile memory. The initialization function stored in the mask ROM includes a patch function that updates the initial setting values set in the interface circuit during initialization using address information of the storage area to be accessed, data-related information, and processing-related information, which are written in the non-volatile memory.
A semiconductor device including: a semiconductor substrate including a chip region; and an interlayer insulating film on the semiconductor substrate is used, the chip region having: a circuit region; and a seal ring region positioned around the circuit region. The semiconductor device includes: a first wiring formed on the interlayer insulating film in the circuit region; and a second wiring formed on the interlayer insulating film in the seal ring region. The semiconductor device further includes: an insulating film covering the first wiring and the second wiring; and an organic insulating film on the insulating film IFT. A concave portion is formed on the upper surface of the second wiring. An end portion of the organic insulating film is positioned on a first portion, which is positioned closer to an edge portion of the chip region than the concave portion, of the second wiring.
A support mark inspection equipment includes: an input unit for obtaining an inspection image of a wafer; a partial image generating unit for extracting a plurality of partial images, each including a portion where a support portion of a boat contacts the wafer, from the inspection image; a generated image obtaining unit for inputting each of the plurality of partial images into an AI (Artificial Intelligence) model and obtaining a plurality of generated images respectively corresponding to the plurality of partial images; an abnormality determination unit for determining whether a support mark is present in each of the plurality of partial images based on each of the plurality of partial images and each of the plurality of generated images; and an output unit for outputting an inspection result of the support mark.
To improve the performance of the differential circuit. Additionally, to suppress the increase in development cost and development period without causing characteristic variations in the pair elements. The plurality of MOS units 0Q are composed of at least one MOSFET, each having the same structure, and are arranged adjacent to each other on the main surface of the semiconductor substrate in plan view. The plurality of MOS units 0Q include MOS unit 1Q and MOS unit 2Q, which constitute part of the differential circuit as pair elements, and MOS unit 3Q, which functions as a capacitive element.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
G06F 115/08 - Intellectual property [IP] blocks or IP cores
G06F 119/06 - Power analysis or power optimisation
A semiconductor device including a Zener diode, includes: an n-type semiconductor substrate; a p-type well region; an n-type diffusion region; and a p-type impurity region. An impurity concentration of the p-type impurity region is higher than an impurity concentration of the p-type well region. The p-type impurity region surrounds at least a part of the n-type diffusion region in plan view. The p-type well region forms a quadrangular shape in plan view. Each corner of the p-type well region is exposed from the p-type impurity region in plan view. A cathode of the Zener diode includes the n-type diffusion region. An anode of the Zener diode includes the p-type well region and the p-type impurity region.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
46.
SILICON CARBIDE MOSFET WITH STRETCHED CONTACT AREA
A semiconductor structure includes a gate electrode disposed above a semiconductor substrate of a first conductivity type. The semiconductor structure further includes a source region of the first conductivity type positioned, at least partially, below the gate electrode, and a doped region of a second conductivity type, opposite to the first conductivity type, located adjacent to the source region. The semiconductor structure further includes a first ohmic contact positioned above and in contact with the source region and the doped region. The first ohmic contact having a length and a contact area in electrical communication with the doped region. The semiconductor structure further includes a field oxide adjacent to the doped region, with the length of the first ohmic contact extending above the doped region until a distance between the first ohmic contact and the field oxide is equal to a threshold value.
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
47.
BLOCKCHAIN-SECURED MACHINE LEARNING MODEL MANAGEMENT
Systems and methods for implementing blockchain-secured machine learning model management are described. The system can include a Machine Learning Operations (MLOps) user interface (UI), an MLOps processor, a model operation tool stack, and a model registry. The MLOps UI is configured to allow a user to interact with the system and receive a request for operating a machine learning model. The request includes a model transaction and blockchain ledger. The MLOps processor is communicatively connected to the MLOps UI. The MLOps processor is configured to manage the machine learning model and to execute workflows associated with the model transaction. The model operation tool stack is configured to perform tasks for operating the machine learning model. The model storage is configured to store encrypted machine-learning models. The model registry is configured to manage the machine learning model and the model transaction using the blockchain ledger.
A semiconductor device includes: an oscillator circuit including a plurality of logic gate groups connected in series; a frequency counter measuring an oscillation frequency of the oscillator circuit; and a comparator comparing a reference value and the oscillation frequency of the oscillator circuit measured by the frequency counter. Each of the logic gate groups includes first to third logic gates each made of a transistor and connected in series. A first fan-out number of the first logic gate is larger than a second fan-out number of the second logic gate and the third logic gate. The first to third logic gates have the same driving force from one another.
Disclosed is a technique for improving performance of a semiconductor device having a trench gate type power MOSFET. Concretely, a method of manufacturing a semiconductor device having a trench gate type power MOSFET comprising: forming a trench in a semiconductor substrate; introducing both of a p-type impurity (Boron) and carbon (C) into a bottom surface of the trench to form a p-type impurity introduced region; forming a gate electrode to fill the trench; forming a channel forming region and a source region at the side of the trench in which the gate electrode is filled; and subjecting a heat treatment to the p-type impurity introduced region to form an electric field relaxation layer having suppressed crystal defects and a controlled shape.
A wireless power apparatus may include a first planar coil having a first coil winding orientation, the first planar coil may be disposed in a plane, a second planar coil may have a second coil winding orientation that is opposite the first coil winding orientation, the second planar coil may be disposed at a distance from the first planar coil in the plane, and a conductor configured to serially connect the first planar coil with the second planar coil to form a split planar coil.
H01F 27/36 - Electric or magnetic shields or screens
H02J 50/10 - Circuit arrangements or systems for wireless supply or distribution of electric power using inductive coupling
H02J 50/70 - Circuit arrangements or systems for wireless supply or distribution of electric power involving the reduction of electric, magnetic or electromagnetic leakage fields
Systems and methods for implementing addressable SPI are described. The system includes a controller and a plurality of devices. The controller includes a SPI bus and a node address (NAD) line. The controller is configured to transmit a chip select signal and a clock signal via the SPI bus, and receive a respective node address signal via the NAD line. The plurality of devices is connected to the SPI bus of the controller. A respective device of the plurality of devices is configured to receive the chip select signal and the clock signal from the controller via the SPI bus; determines a respective node address associated with the respective device based on the chip select signal and the clock signal; generate a respective node address signal indicating the respective node address; and transmit the respective node address signal to an adjacent device in the chain or the NAD line.
Methods and apparatus for protecting data frames at a transmission side of a frame-based communication link are described. The apparatus includes a receiver module, a cipher suite module and a transmitter module. The receiver module receives the data frame and protection information for the data frame. The protection information specifies whether the data frame is to be protected. The receiver module transmits the data frame to the cipher suite module, if the protection information specifies that the data frame is to be protected. If the protection information specifies that the data frame is not to be protected, the receiver transmits the data frames the data frame to the transmitter module. The cipher suite module protects the data frame and transmits the protected data frame to the transmit module. The transmit module provides the data frame or the protected data frame for transmission over the frame-based communication link.
A wireless power apparatus may include a receiver coil with a first conductor assembly having a first conductor type, the receiver coil with a second conductor assembly having a second conductor type that may be different from the first conductor type, the first conductor assembly and the second conductor assembly may be connected in series to form a hybrid coil.
H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
H01F 41/061 - Winding flat conductive wires or sheets
H02J 50/00 - Circuit arrangements or systems for wireless supply or distribution of electric power
54.
AUTOMATIC PASS-THROUGH MODE ENTRY AND EXIT FOR POWER CONVERSION CIRCUIT
Systems and methods for implementing pass-through mode (PTM) of a power conversion circuit are described. The system can include a first stage controller and a first stage. The first stage controller is configured to monitor an input voltage and generate a PTM control signal based on the input voltage to control an operation of. The first stage is connected to the first stage controller. The first stage can include the power conversion circuit configured to convert the input voltage to a converter output voltage.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
To provide a power supply device that includes a comparison circuit in the feedback circuit and employs an optical isolator in the voltage conversion unit. The power supply device comprises a switching circuit that controls the input voltage and converts it to output voltage, a power transmission unit that transmits the output voltage to the output stage, an optical isolator connected to the power transmission unit that transmits the voltage signal of the output stage to the feedback circuit while isolating it, and a feedback circuit that generates a control signal to control the switch based on the voltage signal input from the optical isolator and outputs it to the switching circuit, wherein the feedback circuit generates the control signal using a comparison circuit that binarizes the input voltage signal.
An integrated circuit 1 comprises a processor 10, a memory 12 that holds data defined in the software 18 executed by the processor 10, a data cache 11 positioned between the processor 10 and the memory 12, and a recording circuit 13. The data cache 11 temporarily holds write data output from processor 10 to be written to memory 12. The recording circuit 13 is connected to the bus 20 between the processor 10 and the data cache 11 and records the write data.
A semiconductor device is provided that can improve heat dissipation while suppressing cracking in one of the topmost semiconductor chips among a plurality of semiconductor chips. The semiconductor device includes a plurality of semiconductor chips and a mold resin. The semiconductor chips are stacked and include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is located at the topmost position among the semiconductor chips and the second semiconductor chip is located at the bottommost position among the semiconductor chips. Each of the semiconductor chips has a lower surface and an upper surface located opposite the lower surface. The upper surface of the first semiconductor chip has, in a plan view, a peripheral region and a central region located inside the peripheral region. The mold resin is formed to cover the peripheral region and has a through-hole that at least partially exposes the central region.
A log management apparatus, an in-vehicle system, and a data transfer method for the log management apparatus are provided to preferentially transfer desired log data to a storage. The log management apparatus 1 includes a CPU 2 that outputs log data, a log buffer 41 that stores log data, and a DMA controller 3 that transfers the log data stored in the log buffer 41 to a storage 5. The DMA controller 3 includes a priority table storage unit 31 that stores a priority table including a priority set that determines a priority for each tag associated with log data, and a transfer necessity determination circuit 32 that determines which log data not to be transferred to the storage 5 from among the log data stored in the log buffer 41 based on the priority set.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
To provide a failure detection circuit for detecting abnormality within a semiconductor device that operates in synchronization with a clock signal, by detecting a signal path delay in the semiconductor device with respect to the clock signal. The failure detection circuit comprises a first flip-flop element configured to receive a first input data signal and to provide a first output data signal according to the first input data signal in response to the clock signal. The failure detection circuit also comprises a second flip-flop element configured to receive a second input data signal and to provide a second output data signal according to the second input data signal in response to the clock signal.
After a silicon oxide film is formed on a main surface of a semiconductor substrate so as to cover a floating gate electrode and a gate electrode, an isotropic etching is performed on the silicon oxide film with a photoresist pattern formed thereon used as an etching mask, and an anisotropic etching is further performed on the silicon oxide film. Accordingly, the silicon oxide film exposed from the photoresist pattern is removed, and a first insulating film made of the silicon oxide film remaining below the photoresist pattern is formed. The first insulating film covers the floating gate electrode. After a metal silicide layer is formed on the gate electrode, a second insulating film made of silicon nitride is formed on the main surface of the semiconductor substrate so as to cover the floating gate electrode, the gate electrode, the metal silicide layer, and the first insulating film.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
A semiconductor device includes a reference current generation circuit, a replica current generation circuit, a first ramp wave signal generation circuit and a second ramp wave signal generation circuit, and a correction circuit. The reference current generation circuit includes a first MOSFET and a first resistor, and is configured such that a reference current flows through the first MOSFET and the first resistor. The replica current generation circuit includes a second MOSFET through which a replica current of M times the reference current flows. A first ramp wave signal generation circuit and a second ramp wave signal generation circuit alternately generate ramp wave signals. A correction circuit that generates a voltage according to a current value of the reference current, and generates the first potential as a potential, which is shifted to a positive side, from the gate potential of the first MOSFET by the generated voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
62.
POWER AMPLIFIER, AMPLIFICATION METHOD, AND TRANSMITTER
A power amplifier that includes a power amplifier core unit that is capable of performing amplitude control in discrete integer steps, and a variable attenuator. The power amplifier core unit performs the amplitude control to reproduce an envelope of an RF signal. The variable attenuator changes an attenuation amount, and controls average transmission power by using a combination of the amplitude control performed by the power amplifier core unit and the attenuation amount of the variable attenuator.
A failure analysis device is for analyzing a failure of the semiconductor device equipped with a logic circuit and a memory circuit. It has a storage device and a processor. The storage device stores fail bit data obtained by testing the memory circuit and failure diagnosis data obtained by failure diagnosis for test results of the logic circuit. The processor extracts a fail I/O value from the fail bit data, extracts the data of the memory connection port which is the connection port to the memory circuit from among the estimated failure parts included in the failure diagnosis data, and determines match/not-match between the fail I/O value and the port ID value included in the data of the memory connection port.
Systems and methods for implementing a continuous current monitor based on a low-side pilot power device is generally described. The semiconductor device includes a first circuit to filter an output signal from a power stage to generate a filtered signal that is coherent with an inductor current through an inductor in the power stage, a second circuit to generate a calibration code, and a third circuit to monitor current from a pilot device integrated in a low-side device of the power stage. The first circuit can calibrate the filtered signal to generate a calibrated signal based on the calibration code and the current from the pilot device. The second circuit can adjust the calibration code based on the calibrated signal. A combination of samples corresponding to the calibrated signal and samples corresponding to the current from the pilot device can recreate the inductor current.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
65.
DRAIN SOURCE VOLTAGE MONITOR USING SOURCE STRAY INDUCTANCE
Semiconductor devices, systems and methods are described. A system can include a controller configured to generate a control signal, a power module and a gate driver. The gate driver can be configured to drive the power device according to the control signal. The gate driver can be further configured to measure a voltage across a source wire of the power device. The gate driver can be further configured to output the voltage across the source wire to the controller. The controller can be further configured to determine, based on at least the voltage across the source wire, an overshoot voltage associated with the power device. The controller can be further configured to determine, based on at least the overshoot voltage, a peak drain-source voltage of the power device. The controller can be further configured to adjust the control signal based on the determined peak drain-source voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
G01R 19/25 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
66.
DUAL-PROCESS OXIDE TRENCH STRUCTURE FOR SILICON CARBIDE MOSFETS
A method of forming a semiconductor device includes forming a first oxide layer having a first thickness to line a trench formed in a Silicon Carbide (SiC) substrate. The method further includes etching the first oxide layer to form a second oxide layer having the first thickness. A portion of the trench lined by the second oxide layer being less than a portion of the trench lined by the first oxide layer. The method further includes forming a third oxide layer having a second thickness on the trench and on a top surface of the second oxide layer. A combination of the second oxide layer and the third oxide layer forming an oxide region that lines different portions of the trench with different oxide thickness. The method further includes forming a gate electrode in the trench lined with the oxide region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes one or more LDMOS transistors and a semiconductor substrate having an upper surface. Each of the one or more LDMOS transistors includes: a plurality of impurity diffusion layers formed in the semiconductor substrate at the upper surface; a plurality of drain layers formed in the semiconductor substrate at the upper surface; and a plurality of insulating films formed on the upper surface. Each of the plurality of impurity diffusion layers, each of the plurality of drain layers, and each of the plurality of insulating films extend along a first direction in plan view. The plurality of impurity diffusion layers are arranged along a second direction perpendicular to the first direction in plan view while interposing a gap between two adjacent impurity diffusion layers among the plurality of impurity diffusion layers.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/60 - Impurity distributions or concentrations
To provide a semiconductor device circuit configured to switch glitchfree between a plurality of independent Ethernet clock sources for operating a network interface. The semiconductor device comprises a clock provision unit comprising at least a first circuit branch configured to receive a first clock signal from a first clock source associated with a first network interface, and a second circuit branch configured to receive a second clock signal from a second clock source associated with a second network interface, the second clock source having a different clock rate than the first clock source.
Systems and integrated circuits for implementing a low quiescent current low-dropout (LDO) regulator are described. The system can include a super follower circuit, a current limit circuit and an LDO core circuit. The super follower circuit is configured to supply a first current. The current limit circuit is configured to receive a system input voltage and supply a second current. The LDO core circuit is coupled to the super follower circuit and the current limit circuit. The LDO core circuit is configured to receive the first current from the super follower circuit and the second current from the current limit circuit. The LDO core circuit is configured to supply and regulate a system output voltage at a system output node. The LDO core circuit can include a feedforward capacitor connected between the system output node and a feedback node.
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
70.
FLASH SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH ERROR CORRECTION
Systems and methods for analog-to-digital conversion are described. A device can include a successive approximation register (SAR) analog-to-digital converter (ADC) and a flash ADC with a fractional bit resolution. The flash ADC can determine a digital code that encodes a voltage range of an input voltage, provide redundancy for digital error correction and output the digital code to the SAR ADC. The SAR ADC can decode the digital code to obtain a first set of bit values of a set of most significant bits (MSBs) of a digital output that is a digital representation of the input voltage, determine a second set of bit values of a set of least significant bits (LSBs) of the digital output, and generate the digital output based on the first set of bit values and the second set of bit values.
A variable gain amplifier has cascode stages formed of pairs of cross-coupled transistors. Each pair of cross-coupled transistors is provided with a transformer which keeps impedances presented to the cross coupled transistors constant with gain.
A configuration unit 20 includes: a storage unit 21 that stores RTL waveform data 21a, which shows the waveforms of multiple signals output from the RTL simulator 10 simulating the operation of the first model representing the target circuit; a determination unit 25A; and a generation unit 26. The multiple signals include a clock signal. The determination unit 25A determines, by analyzing the RTL waveform data 21a, a mask time period during which one or more analysis target signals, other than the clock signal, among the multiple signals do not fluctuate. The generation unit 26 generates an input signal to the model simulator 12, which simulates the operation of the second model obtained by converting the first model. The generation unit 26 generates a masked clock signal as an input signal by masking the mask time period in the clock signal.
substrate; a first insulating layer formed on the semiconductor substrate; first and second coils formed on the first insulating layer and located adjacent to each other in plan view; a first conductor pattern formed on the semiconductor substrate, extending in a second direction perpendicular to a first direction in plan view, and formed between the first coil and the second coil in the first direction; a second insulating layer formed on the first insulating layer so as to cover the first coil, the second coil, and the first conductor pattern; third and fourth coils formed on the second insulating layer and respectively overlapping the first and second coils in plan view. Here, the first direction is an arrangement direction of the first coil and the second coil. Also, the first conductor pattern is electrically connected to the semiconductor substrate.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device includes: a hole amplifier circuit; and an input terminal to which a sensor control signal generated in a period in which an image acquiring operation by an image sensor is not performed is input. In the hole amplifier circuit, a differential amplifier includes differential input nodes for input of a hole voltage from a hole sensor. One end of a plurality of capacitors is connected to the differential input nodes to determine a gain of the hole amplifier circuit. A refresh circuit causes the differential input nodes to retain correction voltages for canceling an offset voltage in accordance with a refresh signal synchronizing with a sensor control signal.
A power circuit includes one or more power supplies controlled by a controller, a sensor, and a filter. Each power supply comprises an electrical component adapted to store energy. The sensor senses a first current having a first bandwidth through the electrical component. The filter filters a signal based on the first current to obtain a filtered current having a second bandwidth that is less than the first bandwidth. The controller is configured to process the filtered current to generate an estimated current having a third bandwidth greater than the second bandwidth.
A plurality of external terminals arranged on a first bottom surface of an interposer substrate includes a plurality of power supply terminals capable of supplying a first power supply potential supplied from an external source to a first circuit. A second bottom surface includes a terminal arrangement region on which the plurality of external terminals are arranged, and a peripheral region surrounding the periphery of the terminal arrangement region. The terminal arrangement region includes a first region closest to a first edge of the interposer substrate and extending along the first edge. In the first region, only the plurality of power supply terminals among the plurality of external terminals are arranged so as to be adjacent to each other. Power consumption of the first circuit is the largest among the power consumption of each of the plurality of circuits of the semiconductor chip.
A method of manufacturing a semiconductor device includes: a step of forming a liner film so as to cover a first gate electrode and a second gate electrode; a step of forming an insulating film on the liner film; a step of exposing the liner film positioned on each of the first gate electrode and the second gate electrode by performing anisotropic dry etching to the insulating film, and forming a buried layer between the first gate electrode and the second gate electrode; a step of forming an interlayer insulating film on the buried layer; and a step of forming a contact hole in the interlayer insulating film, the buried layer and the liner film, and forming a plug electrode in the contact hole.
First and second reference current sources generate currents with opposing temperature characteristics and output a summed reference current. A ring oscillator outputs an output signal with an oscillation frequency corresponding to the reference current. The first reference current source has a first diode and first, second, and twelfth n-type transistors connected in series. A gate of the second n-type transistor is connected to a node, and a gate of the first n-type transistor is connected to a ground. The second reference current source has a third n-type transistor and a second diode in series, a fourth n-type transistor, a fifth p-type transistor, and a first resistor in series, and a sixth p-type transistor forming a current mirror with the fifth p-type transistor. Gates of the third and fourth n-type transistors are connected to an anode of the second diode. The second n-type transistor is connected to another node.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes: a semiconductor substrate having an upper surface; and wiring layers and insulating layers alternately stacked on the upper surface. The insulating layers include: a first insulating layer located between the first wiring layer located at the lowest layer among the wiring layers in cross-sectional view and the semiconductor substrate; and a second insulating layer located between a second wiring layer located at one layer above the first wiring layer among the wiring layers in cross-sectional view and the first wiring layer. The first wiring layer includes: a first coil; a first lead-out wiring electrically connected to the outermost peripheral portion of the first coil; and a second lead-out wiring electrically connected to the innermost peripheral portion of the first coil. The wiring layer located above the first wiring layer among the wiring layers in cross-sectional view includes a second coil overlapping the first coil.
A semiconductor device includes: a first semiconductor component mounted on a wiring substrate; a second semiconductor component mounted on the wiring substrate; and a lid. A height of a first upper surface of the first semiconductor component is lower than a height of a second upper surface of the second semiconductor component. A cover portion of the lid includes a portion that forms a shape protruding in a direction toward the first semiconductor component at a position facing the first semiconductor component. A third upper surface of the cover portion includes: a bottom surface that is a part of the portion; a fourth upper surface arranged at a position which is higher than the bottom surface; and a side surface connecting the bottom surface and the fourth upper surface.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A semiconductor device includes a parameter storage unit and an image processing circuit. The image processing circuit includes a scaling calculation unit that changes a size of an input image based on an enlargement ratio or reduction ratio set in scale factor setting information. The image processing circuit further includes an optimized image area calculation unit that calculates a necessary image area size for outputting an output image based on an output size of the output image and a scale factor, and an input image area comparison unit that compares the necessary image area size with the input size of the input image, selects an image area with a smaller size out of the necessary image area size and the input size, and uses the image area selected for the image processing of the input image.
According to the present disclosure, a semiconductor device includes a first electronic circuit including a first semiconductor element group having a first threshold voltage, and a second semiconductor element group having a second threshold voltage higher than the first threshold voltage, a second electronic circuit having a same logical configuration as the first electronic circuit, and in which a ratio occupied by the second semiconductor element group among the first semiconductor element group and the second semiconductor element group is greater than that in the first electronic circuit, a power supply connection portion that connects one of the first electronic circuit and the second electronic circuit to a power supply, a storage unit that stores power supply connection information, and a control circuit that controls the power supply connection portion to connect the power supply to one of the first electronic circuit and the second electronic circuit selected based on the power supply connection information read from the storage unit.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
84.
AUTONOMOUS SYSTEM SEQUENCING OF DISCRETE REGULATORS WITH CASCADED INTERFACE SIGNAL
Systems and methods for operating one or more power regulators are described. A power regulator can include an enable pin configured to receive an enable signal for enabling generation of an output voltage. The power regulator can further include a power good pin configured to output a power good signal indicating a status of the output voltage. The power regulator can further include a circuit configured to detect a presence of a fault condition. The circuit can be further configured to, in response to detecting the fault condition, de-assert the power good pin to disable a downstream device and de-assert the enable pin to disable an upstream device.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
85.
FRACTIONAL DIVIDER CALIBRATION WITH DUAL DIGITAL CONTROL DELAY CIRCUITS
Systems and methods for calibrating a fractional divider are described. A system can include a divider and a circuit. The divider can divide an input clock signal to generate an integer output divider (IOD) signal. The circuit can include a first digital control delay (DCD) circuit configured to delay the IOD signal to generate a first delayed IOD signal. The circuit can further include a second DCD circuit configured to delay the first delayed IOD signal to generate a second delayed IOD signal. The circuit can further include an edge sampler configured to compare an edge of the second delayed IOD signal with an edge of the input clock signal. The circuit can further include a controller configured to calibrate the first DCD circuit based on a result of the comparison between the edge of the second delayed IOD signal with the edge of the input clock signal.
H03L 7/197 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
H03K 23/68 - Pulse counters comprising counting chainsFrequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
An inductive sensor assembly is provided. The inductive sensor assembly includes a coil assembly and a movable conductive target. The coil assembly is discontinuously excited by a sequence of signal pulses. The coil assembly includes three coils in a predefined arrangement coupled among three terminals. The movable conductive target at least partly covers the coils during its movement. The inductive sensor assembly is configured for measuring respective currents of the coil assembly at a predetermined time synchronized with excitation of the coil assembly at respective terminals, for determining a displacement of the target.
G01B 7/30 - Measuring arrangements characterised by the use of electric or magnetic techniques for measuring angles or tapersMeasuring arrangements characterised by the use of electric or magnetic techniques for testing the alignment of axes
G01B 7/00 - Measuring arrangements characterised by the use of electric or magnetic techniques
87.
METHOD, A PROGRAM, AND A COMPUTER FOR TIMING ADJUSTMENT OF A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
The timing adjustment method, program, and computer for a semiconductor integrated circuit are provided to suppress the increase in the size of layout data. The timing adjustment method for a semiconductor integrated circuit includes adding one or more dummy cells each having a plurality of dummy metals to layout data of the semiconductor integrated circuit, selecting a dummy cell to be connected to a signal wiring when the delay time of the signal wiring included in the layout data indicates a hold error, and connecting one or more of the plurality of dummy metals included in the dummy cell that has been selected in the selecting to the signal wiring.
To achieve desired performance, a data reception device comprises receiving unit and an adaptive equalization processing unit. The receiving unit generates a received signal based on a first wireless signal received by a first antenna and a second wireless signal received by a second antenna. The adaptive equalization processing unit performs adaptive equalization processing to asymptotically match the received signal based on the first wireless signal and the second wireless signal generated by the receiving unit to a predetermined training signal.
H04B 7/08 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the receiving station
89.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An interlayer insulating film is formed on an upper surface of a semiconductor substrate. A plurality of wirings is formed on the interlayer insulating film. The interlayer insulating film has a BPSG film and a PSG film formed on the BPSG film. A gettering layer containing phosphorus is formed in the PSG film. A concentration of phosphorus in the gettering layer is higher than a concentration of phosphorus in the PSG film.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A semiconductor wafer includes a semiconductor substrate, a plurality of chip regions, a scribe region, and an interlayer insulating film. A TEG is formed in the scribe region. The TEG includes a first active region formed in the semiconductor substrate, a second active region formed in the semiconductor substrate, and adjacent to the first active region in a first direction, a gate electrode formed on the first active region and the second active region, and extending in the first direction, an insulating region adjacent to the second active region in a second direction orthogonal to the first direction, and formed in the semiconductor substrate so as not to overlap with the first gate electrode in plan view, a plug formed in the interlayer insulating film and connected to the first active region, and a dummy plug formed in the interlayer insulating film and connected to the insulating region.
It can blow an electric fuse with a small blowing current. A metal film is connected to a first wiring through a first via, and is connected to a second wiring through a second via. A disconnect transistor is coupled to the second wiring. An area of a contact surface, which is in contact with the metal film, of the first via is smaller than an area of a contact surface, which is in contact with the metal film, of the second via.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
92.
CAMERA INSPECTION SYSTEM AND CAMERA INSPECTION METHOD
The camera inspection system includes an external environment changer that receives an inspection signal and changes the imaging illumination of a camera fixed to a vehicle, thereby changing the brightness within the frame image captured by the camera. It also includes an average brightness calculator that calculates the average brightness within the image for each frame image captured within a predetermined period by the camera, and an inspector that compares the inspection signal with the average brightness within the image for each frame image and generates a fault detection signal indicating image fixation when the timing of the change in the inspection signal does not match the change in the average brightness within the image.
A semiconductor device includes: a plurality of pads; a plurality of redistribution wirings connected to the plurality of pads; a terminal provided on a land portion of each of the plurality of redistribution wirings; and a conductive film connected to each of the terminal and the land portion. The plurality of redistribution wirings includes: a first redistribution wiring having a first land portion; and a second redistribution wiring having a second wiring portion. A planar shape of the conductive film is circular. A planar shape of the first land portion is non-circular. In plan view, the first land portion is arranged adjacent to the second wiring portion which is extending in the Y direction. In plan view, the first land portion has a first side which is linearly extending along the second wiring portion.
To provide a semiconductor device and its manufacturing method capable of designing the intended delay with high precision using fewer steps. The manufacturing method of the semiconductor device disclosed herein arranges multiple circuits on a plane and connects wiring to each, comprising: a placement step of arranging a digital circuit that operates based on timing signals and a delay circuit configured with multiple delay paths having different input/output delay amounts, where one of the multiple delay paths can be selected by a selection signal; a wiring step of connecting the output of the delay circuit so that it becomes the timing signal of the digital circuit; and a delay adjustment step of selecting one of the multiple delay paths by connecting a predetermined voltage as the selection signal, and selecting the delay amount so that the input/output timing of the digital circuit meets predetermined conditions.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
A drive circuit can calculate an optimal phase adjustment amount by passing a current through an external load. The drive circuit includes a control circuit that outputs a first AC signal and a second AC signal from an AC signal source, and a reference voltage generation circuit that has a differential amplifier generating a first AC voltage from the first AC signal and outputs the first AC voltage to one end of an external load. It also includes a voltage-current conversion circuit that supplies an AC current to the external load from the second AC signal, and a comparator connected across both ends of the external load. The comparator compares the first AC voltage at one end of the external load with the second AC voltage at the other end of the external load and changes the output voltage when the first and second AC voltages are inverted.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
96.
SILICON CARBIDE PLANAR MOSFET WITH HYBRID LINEAR AND HEXAGONAL CHANNEL ARCHITECTURE
A semiconductor structure includes a silicon carbide semiconductor substrate of a first conductivity type having an upper and bottom surface. A drift region of the first conductivity type is located on the upper surface. Above the drift region, a channel region of a second conductivity type, opposite to the first conductivity type, is located featuring a hybrid configuration. The hybrid configuration includes a first channel segment of a first channel geometry located between and directly connected to two second channel segments of a second channel geometry. A source region of the first conductivity type is located adjacent to the channel region. A first doped semiconductor region of the second conductivity type, featuring a third geometry, is placed above the drift region and adjacent to the first channel segment. Finally, a gate electrode is located above the drift region via a gate oxide.
H10D 30/83 - FETs having PN junction gate electrodes
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
Apparatuses, devices, and systems for operating a voltage converter to reduce current spike are described. A controller can measure a feedback of a current of an alternating current (AC) voltage of a switching circuit. The controller can measure a direct current (DC) voltage of the switching circuit. The controller can operate a current control loop using the feedback of the current to determine a target voltage. The controller can determine a duty cycle of the switching circuit based on the target voltage and the DC voltage. The controller can operate the switching circuit under the determined duty cycle to control the current of the AC voltage.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/219 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
98.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes an n-type offset drain region, an n-type semiconductor region, and a gate electrode. The n-type semiconductor region is arranged apart from the n-type offset drain region.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device, a control method for the semiconductor device, and a program for efficiently storing values in memory are provided. The semiconductor device 100 includes a data acquisition unit 1, a determination unit 2, and memory 3. The data acquisition unit 1 acquires a data signal SIG input from the outside at a predetermined cycle. Determination unit 2 stores a threshold. Determination unit 2 performs a threshold determination by comparing the measurement value M indicated by the data signal SIG acquired by the data acquisition unit 1 with the threshold. If, in the threshold determination, the measurement value M is determined to be an abnormal value that does not meet the predetermined criteria, the measurement value M is stored in memory 3.
A semiconductor device includes a timer control circuit (timer) and an AD converter (ADC), and generates a PWM signal by using a periodic signal of the timer on the basis of an ADC output. After receiving an AD conversion start request signal (ADR signal), the ADC starts AD conversion in synchronization with a latest AD synchronization signal. The timer outputs a timer phase signal that is a basis for starting generation of a periodic signal and the ADR signal when a phase-locked loop counter value matches a value of a timer phase register, outputs an AD synchronization phase signal that is a basis for starting generation of the AD synchronization signal when the counter value matches the value of an AD synchronization phase register, and controls a phase difference between the ADR signal and the AD synchronization signal to be constant regardless of activation timing of the device.
H03M 1/06 - Continuously compensating for, or preventing, undesired influence of physical parameters
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
