An integrated circuit includes a semiconductor die including a set of conductive pads on a given side of the die. The integrated circuit also includes a set of conductive bumps. A conductive bump of the set of conductive bumps has a first end and a second end, and the first end of the conductive bump is coupled to a respective pad of the set of conductive pads. The integrated circuit additionally includes a first passivation layer around the set of conductive bumps, a redistribution layer coupled to the second end of the conductive bump, a lead, and a second passivation layer around the lead. The integrated circuit further includes a conductive via coupled, in the second passivation layer, between the redistribution layer and the lead.
Methods, apparatus, systems, and articles of manufacture are described to protect a computing device in low-power mode. An example system includes temperature monitoring circuitry operable to generate a first temperature sample and a second temperature sample; and control circuitry coupled to the temperature monitoring circuitry and operable to: increment a count in response to the first temperature sample satisfying a first temperature threshold; increase the first temperature threshold to a second temperature threshold in response to the first temperature sample satisfying the first temperature threshold; compare the second temperature sample to the second temperature threshold after increasing the first temperature threshold to the second temperature threshold; and increment the count in response to the second temperature sample satisfying the second temperature threshold.
In examples, an electronic device comprises a semiconductor package including a semiconductor die and a set of conductive members coupled to the semiconductor die, the set of conductive members coupled to a bottom surface of the semiconductor package. The package also includes a conductive terminal coupled to the semiconductor die and exposed to the bottom surface, the set of conductive members extending farther away from the bottom surface of the semiconductor die than the conductive terminal extends from the bottom surface of the semiconductor die. The electronic device includes a flexible substrate having first and second ends opposing each other, the first end having a first conductive terminal coupled to the conductive terminal. The second end has a second conductive terminal adapted to be coupled to an electronic component, the first and second conductive terminals are coupled to each other, and the flexible substrate has a bottom surface that does not extend farther away from the bottom surface of the semiconductor package than the set of conductive members extends from the bottom surface of the semiconductor package.
H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes
H10F 39/18 - Capteurs d’images à semi-conducteurs d’oxyde de métal complémentaire [CMOS]Capteurs d’images à matrice de photodiodes
4.
TWO-ROTATION GATE-EDGE DIODE LEAKAGE REDUCTION FOR MOS
An integrated circuit is fabricated by forming transistors having gates of orthogonal orientations and implanting, at two first rotations, a first pocket implant using a first dopant type with a masking pattern on a substrate surface layer, the two first rotations respectively forming two first pocket implantation angles and two first pocket implantation beam orientations, and implanting, at two second rotations, a retrograde gate-edge diode leakage (GDL) reduction pocket implant using a second dopant type with the masking pattern on the substrate surface layer, the two second rotations respectively forming two GDL-reduction implantation angles and two GDL-reduction implantation beam orientations. Owing to the different symmetries in implantation angles seen by the two orientations of transistors, leakage is reduced for transistors of both orientations and mismatch is maintained for transistors of one of the orientations, making these transistors suitable for use in analog circuits requiring matched pairs of transistors.
H10D 62/834 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé caractérisés en outre par les dopants
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
An electronic device and method of fabricating the electronic device are provided where the method includes attaching an electronic device layer on a first surface of a substrate and forming first openings in only the electronic device layer to form individual dies. A back grinding process is performed on a second surface of substrate and the substrate is placed on an isolation layer. Second openings are formed in the substrate and the isolation layer to form die assemblies comprising the individual dies, the substrate, and the isolation layer. The die assemblies are placed on a leadframe and a mold compound is formed over the die assemblies.
In examples, a semiconductor package includes a portion of a lead frame including a die pad, a package pin, and an antenna having first and second segments, with at least one of the first and second segments having a meandering portion. The package includes a semiconductor die coupled to the die pad and having a device side in which circuitry is formed, a first bond wire coupling the device side to the package pin, a second bond wire coupling the first segment to the second segment, and a third bond wire coupling the device side to the antenna. The package includes a mold compound covering the semiconductor die, at least part of the package pin, the antenna, and the first, second, and third bond wires. Portions of the first and second segments are exposed on multiple exterior lateral surfaces of the mold compound.
Fabrication methods, electronic devices and enhancement mode gallium nitride transistors include a gallium nitride interlayer between a hetero-epitaxy structure and a p-doped gallium nitride layer and/or between the p-doped gallium nitride layer and a gate structure to mitigate p-type dopant diffusion, improve current collapse performance, and mitigate positive-bias temperature instability. In certain examples, the interlayer or interlayers is/are fabricated using epitaxial deposition with no p-type dopant source. In certain fabrication process examples, epitaxial deposition or growth is interrupted after the depositing an aluminum gallium nitride layer of the hetero-epitaxy structure, after which growth is resumed to deposit the first gallium nitride interlayer over the aluminum gallium nitride layer to mitigate p-type dopant diffusion and current collapse.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
An apparatus includes an amplifier and a current source. The amplifier has a voltage reference input, a second input, an output, and a terminal coupled to a supply voltage terminal. The current source has an input coupled to the output of the amplifier, a first output coupled to the second input of the amplifier, a second output coupled to the voltage reference input of the amplifier, and a terminal coupled to the supply voltage terminal.
An example apparatus includes: first amplifier circuitry having a first output and a second output; second amplifier circuitry having an output; first transistor circuitry having a first terminal and a control terminal; second transistor circuitry having a first terminal and a control terminal, the control terminal of the second transistor circuitry coupled to the output of the second amplifier circuitry and the control terminal of the first transistor circuitry; and voltage-to-delay circuitry having a first input and a second input, the first input of the voltage-to-delay circuitry coupled to the first output of the first amplifier circuitry and the first terminal of the first transistor circuitry, the second input of the voltage-to-delay circuitry coupled to the second output of the first amplifier circuitry and the first terminal of the second transistor circuitry.
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
G04F 10/00 - Appareils pour mesurer des intervalles de temps inconnus par des moyens électriques
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés
A circuit includes first, second, third and fourth transistors, a buck control circuit, and a boost control circuit. The second transistor is coupled to the first transistor. The fourth transistor is coupled to the third transistor. The buck control circuit has a first output coupled to a control terminal of the first transistor, and a second output coupled to a control terminal of the second transistor. The boost control circuit includes a flip-flop, a first timer, and a second timer. The flip-flop has a first output coupled to a control terminal of the first transistor, a second output coupled to a control terminal of the second transistor, and an input. The first timer has an output coupled to the input of the flip-flop. The second timer has an output coupled to the input of the flip-flop.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
One example includes a digital signal isolator device. The device includes a transmitter circuit configured to receive a first signal and to provide a first current in response to the first signal and a receiver circuit configured to receive a second current and to generate a second signal in response to the first current. The device also includes a leadframe comprising a transformer. The transformer can include a first portion of the leadframe arranged as a primary of the transformer and a second portion of the leadframe arranged as a secondary of the transformer. The transmitter circuit can be configured to provide the first current on the first portion of the leadframe to inductively generate the second current in the second portion of the leadframe in response to the first current.
In a described example, a detector is configured to control a bus operating mode of a bus controller. The detector can be coupled to the bus controller. The detector includes a bus voltage detector that can be configured to provide a bus voltage detected signal indicative of a bus voltage level of a bus voltage on a communication bus. The bus controller can be configured to operate in a first bus mode. The detector can include logic that can be coupled to the bus voltage detector. The logic can be configured to determine whether the bus voltage is at a high bus voltage level or a low bus voltage level based on the bus voltage detected signal and instruct the bus controller to either continue operating in the first bus mode or to switch to operating in a second bus mode based on the determined bus voltage level.
Current sense circuitry includes: a first amplifier; a transistor; and a second amplifier. The first amplifier has a first terminal, a second terminal, and a third terminal. The transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the transistor is coupled to the third terminal of the first amplifier. The second amplifier has a first terminal, a second terminal, and a third terminal. The first terminal of the second amplifier is coupled to the second terminal of the transistor.
G01R 19/22 - Dispositions pour procéder aux mesures de courant ou de tension ou pour en indiquer l'existence ou le signe utilisant la conversion d'un courant alternatif en courant continu
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
14.
SEMICONDUCTOR DEVICES WITH CHANNEL AND JUNCTION STRUCTURES AND METHODS OF FABRICATION THEREOF
Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device [100] includes a semiconductor layer [106] including fins disposed over a planar portion, a source [116] and a drain drift region [110] disposed in the semiconductor layer, a drain region [112] disposed in the drain drift region. The planar portion and the fins of the semiconductor layer extend from the source region through the drain drift region to the drain region. The semiconductor device also includes a first epitaxial layer [130] disposed over a portion of the fins of the semiconductor layer in the drain drift region, a second epitaxial layer [132] disposed over the first epitaxial layer, the drain drift region having a first doping type and the second epitaxial layer having a second doping type, a gate electrode [126], and a field relief insulating layer [122] disposed between a portion of the gate electrode and a portion of the second epitaxial layer.
A semiconductor device includes a data bit line coupled to bit cells. A data pre-charge variable current source is structured to provide a first data pre-charge current to the data bit line, and to provide a second data pre-charge current to the data bit line that is less than the first data pre-charge current. A dummy pre-charge current source is structured to provide a dummy pre-charge current to a dummy bit line through a dummy current line. A threshold detector is structured to provide a threshold signal when the dummy current line reaches a threshold potential. A pre-charge controller is structured to cause the first data pre-charge current to be provided to the data bit line prior to receiving the threshold signal, and the second data pre-charge current after receiving the threshold signal. A sense amplifier includes an input inverter stage having a positive feedback loop.
G11C 7/12 - Circuits de commande de lignes de bits, p. ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, circuits d'égalisation, pour lignes de bits
16.
MICROELECTRONIC DEVICE PACKAGE WITH INTEGRATED TRENCH CAPACITOR DIES AND SEMICONDUCTOR DEVICE DIE
A described example includes: a semiconductor device die mounted to a die pad of a package substrate; a trench capacitor die mounted on and overlying a portion of a device side surface of the semiconductor device die, and including a trench capacitor formed in a semiconductor substrate; electrical connections that couple power bond pads of the trench capacitor die to power bond pads of the semiconductor device die and ground bond pads of the trench capacitor die to ground bond pads of the semiconductor device die, wherein the power bond pads include a first pair of bond pads and the ground bond pads include a second pair of bond pads, wherein the first pair of bond pads is interleaved with the second pair of bond pads in an alternating pattern; and mold compound covering the semiconductor device die, the trench capacitor semiconductor die, and a portion of the package substrate.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
In a described example, an apparatus includes: a multilayer package substrate including a die mount area on a die side surface and comprising power pads and ground pads on an opposing board side surface, the multilayer package substrate including post connect locations on the die side surface for receiving power post connects and for receiving ground post connects for a flip chip mounted semiconductor device, the power post connect locations and the ground post connect locations positioned in the die mount area, the power post connect locations and the ground post connect locations intermixed in the die mount area; and a semiconductor device having post connects extending from bond pads on a device side surface of the semiconductor device mounted to the die side surface of the multilayer package substrate by solder joints between the post connects and the post connect locations.
In examples, a semiconductor package includes a die pad extending in a horizontal direction and a semiconductor die coupled to the die pad, the semiconductor die having a device side in which circuitry is formed. The package includes a conductive terminal coupled to the device side of the semiconductor die by a bond wire and an antenna vertically distanced from the die pad and extending in the horizontal direction. The package includes a metal member extending from the antenna in the horizontal direction and a conductive member coupling the antenna to the conductive terminal. The package includes a mold compound contacting the die pad, the semiconductor die, the conductive terminal, the antenna, the metal member, and the conductive member. A portion of the conductive terminal and the metal member are exposed on one or more exterior lateral surfaces of the mold compound.
A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.
An apparatus includes: a package substrate having a first set of leads spaced from a first die pad, and a second set of leads spaced from a second die pad, a space between the first and the second die pad forming an electrical isolation barrier; a bobbin mounted on the second die pad; a first coil around a first portion of the bobbin and coupled to a first semiconductor die on the first die pad, and a second coil around a second portion of the bobbin coupled to a second semiconductor die on the second die pad, the first coil, the second coil and the bobbin forming a micro-transformer; and mold compound covering the first die pad, the second die pad, the micro-transformer, portions of the first set of leads, and portions of the second set of leads, the mold compound forming a body of a microelectronic device package.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
An example apparatus includes clock divider circuitry configured to divide a system clock by a pre-scaler input to generate a divided clock; counter circuitry configured to increment a system count based on the divided clock; comparison circuitry configured to determine a count difference between the system count and a real-time clock count; and controller circuitry configured to modify the pre-scaler input based on a comparison of the count difference to a threshold value.
Semiconductor devices and fabrication methods thereof are described. For example, a semiconductor device includes a semiconductor layer including fins disposed over a planar portion, a source and a drain drift region disposed in the semiconductor layer, a drain region disposed in the drain drift region. The planar portion and the fins of the semiconductor layer extend from the source region through the drain drift region to the drain region. The semiconductor device also includes a first epitaxial layer disposed over a portion of the fins of the semiconductor layer in the drain drift region, a second epitaxial layer disposed over the first epitaxial layer, the drain drift region having a first doping type and the second epitaxial layer having a second doping type, a gate electrode, and a field relief insulating layer disposed between a portion of the gate electrode and a portion of the second epitaxial layer.
A circuit includes a first transistor coupled to a first power supply terminal and an output terminal of the circuit, and a second transistor coupled to the output terminal and a second power supply terminal. A first plurality of buffers receives the output of a level shifter and has an output coupled to a control terminal of the first transistor, and a second plurality of buffers receives an input of the circuit and has an output coupled to a control terminal of the second transistor. In an example, a boost circuit has an input coupled to an output of one of the second plurality of buffers, and an output coupled to an output of one of the first plurality of buffers. In another example, the level shifter outputs a shifted input signal having a voltage swing between a voltage at the first power supply terminal and a reference voltage.
A semiconductor device includes a conductive layer including a first lead and a second lead separated by a gap. The conductive layer extends from a first conductive surface to a second conductive surface in a first direction and from a first lead outer edge of the first lead to a second lead outer edge of the second lead in a second direction. The semiconductor device also includes an insulation structure applied to the first conductive surface of the conductive layer and extending continuously from the first lead outer edge to the second lead outer edge. The insulation structure includes an adhesive layer and an insulation layer separated from the conductive layer by the adhesive layer. The semiconductor further includes a die affixed to the adhesive layer in the gap. The semiconductor device yet further includes bond wires between the die and the first lead and the second lead.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor package (100) comprises a package substrate (102). The package substrate comprises a first metal pad (104) and a second metal pad (106) on a first surface of the package substrate. The semiconductor package also comprises a first layer (116) on the first surface of the package substrate. The first layer comprises one or more trenches (134). The semiconductor package also comprises a first die (120) on the first layer and coupled to the first metal pad. The semiconductor package also comprises a second die (122) on the first layer and coupled to the second metal pad. The semiconductor package further comprises a mold compound (136) covering the first die, the second die, and the package substrate. The mold compound is in contact with the one or more trenches. The one or more trenches locates between the first die and the second die. The semiconductor package is suitable for high voltage isolation package applications.
An apparatus includes: a package substrate (430) having a first set of leads (425) spaced from a first die pad (424), and a second set of leads (427) spaced from a second die pad (426), a space (409) between the first and the second die pad forming an electrical isolation barrier; a bobbin (453) mounted on the second die pad; a first coil around a first portion of the bobbin and coupled to a first semiconductor die (231) on the first die pad, and a second coil around a second portion of the bobbin coupled to a second semiconductor die (235) on the second die pad, the first coil, the second coil, and the bobbin forming a micro-transformer (451); and mold compound (423) covering the first die pad, the second die pad, the micro-transformer, portions of the first set of leads, and portions of the second set of leads, the mold compound forming a body of a microelectronic device package (400).
A device includes a projector to project a pattern, a camera to capture an image of a reflection of the pattern, and a processor to determine multiple intersection points of first and second sets of rays in 3d space, the first set of rays corresponding to the pattern having and the second set of rays corresponding to the pattern in the captured image; determine a set of 3d point clouds responsive to the multiple intersection points and a set of values for a parameter in a parametric model of the projector or camera; compare each of the set of 3d point clouds to a target set of pixels to determine a set of residues; select a value of the set of values responsive to the set of residues; and display an image of an object in an environment of the device with the selected value assigned to the parametric model.
A system includes a radio frequency (RF) receive path, which is configured to receive a reflection of a transmitted signal. The signal may include a pulse train having rising edges and falling edges. The RF receive path may process the received signal using one or more time-to-digital converters (TDCs). The output of the TDCs may be used to reconstruct an image of the transmitted signal. The system may further include a time domain (TD) cross-correlation function circuit that is configured to perform a TD cross-correlation function on the transmitted signal and on the reconstructed image. The result of the TD cross-correlation function may indicate a time of flight.
An example apparatus includes: first voltage-to-current (V-I) circuitry having a first terminal and a second terminal; second V-I circuitry having a first terminal and a second terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the first terminal of the first V-I circuitry and the first terminal of the second V-I circuitry; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the second terminal of the first V-I circuitry and the second terminal of the second V-I circuitry; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor coupled to the second terminal of the first transistor, the second terminal of the first resistor coupled to the control terminal of the second transistor.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
G06F 3/14 - Sortie numérique vers un dispositif de visualisation
G08G 9/00 - Systèmes de commande du trafic de véhicules, dans lesquels le type de véhicule est sans importance ou d'un type non spécifié
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03L 7/08 - Détails de la boucle verrouillée en phase
30.
METHODS AND APPARATUS TO TRANSMIT A SERIAL DATA STREAM
An example apparatus includes: filter circuitry having a first output and a second output; source follower circuitry having a first input, a second input, and an output, the first input of the source follower circuitry coupled to the first output of the filter circuitry, the second input of the source follower circuitry coupled to the second output of the filter circuitry; a resistor having a first terminal and a second terminal; load circuitry having an input and an output, the input of the load circuitry coupled to the output of the source follower circuitry and the first terminal of the resistor; and combination circuitry having a first input, and a second input, the first input of the combination circuitry coupled to the second terminal of the resistor, the second input of the combination circuitry coupled to the output of the load circuitry.
H04B 3/20 - Réduction des effets d'échos ou de sifflementSystèmes à ligne de transmission Détails ouverture ou fermeture de la voie d'émissionCommande de la transmission dans une direction ou l'autre
H03F 3/19 - Amplificateurs à haute fréquence, p. ex. amplificateurs radiofréquence comportant uniquement des dispositifs à semi-conducteurs
H04B 1/10 - Dispositifs associés au récepteur pour limiter ou supprimer le bruit et les interférences
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
31.
CONTROLLER GENERATED FEEDBACK SIGNAL TO MODIFY HAPTICS DRIVE SIGNAL
A system and associated processes include an amplifier to amplify a drive signal and a haptics actuator having an input coupled to an output of the amplifier. The haptics actuator vibrates responsive to the drive signal. The system further includes a voltage sensor coupled to the input of the haptics actuator to measure a voltage measurement of the drive signal and a current sensor coupled to the input of the haptics actuator to measure a current measurement of the haptics actuator in response to the drive signal. A controller is coupled to an output of the current sensor and an output of the voltage sensor. The controller receives the voltage and current measurements and generates a feedback signal responsive to the voltage and current measurements and modifies the drive signal responsive to the feedback signal.
An IC includes a substrate including circuitry configured to provide a receiver or a transmitter circuit. A metal stack is over the semiconductor surface including a top metal layer and a plurality of lower metal layers. An isolation capacitor includes the top metal layer as a top plate that is electrically connected to a first node; and a top dielectric layer on the top plate with a top plate dielectric aperture. One of the plurality of lower metal layers provides a bottom plate that includes a plurality of spaced apart segments. A capacitor dielectric layer is between the top and bottom plate. The segments include a first segment electrically connected to a second node and at least a second segment electrically connected to a third node, with separation regions located between adjacent spaced apart segments. The top plate covers at least a portion of each of the separation regions.
Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate list size dependent coding of the merge flag in the prior art, a merge flag is always encoded in the encoded bit stream for each inter-predicted prediction unit (PU) that is not encoded using skip mode. In some methods, in contrast to the prior art that allowed the merging candidate list to be empty, one or more zero motion vector merging candidates formatted according to the prediction type of the slice containing a PU are added to the merging candidate list if needed to ensure that the list is not empty and/or to ensure that the list contains a maximum number of merging candidates.
H04N 19/139 - Analyse des vecteurs de mouvement, p. ex. leur amplitude, leur direction, leur variance ou leur précision
G01C 21/34 - Recherche d'itinéraireGuidage en matière d'itinéraire
G05D 1/69 - Commande coordonnée de la position ou du cap de plusieurs véhicules
G06Q 10/02 - Réservations, p. ex. pour billetterie, services ou manifestations
G06Q 50/40 - Procédés d’affaires s’appliquant à l’industrie du transport
G08G 1/127 - Systèmes de commande du trafic pour véhicules routiers indiquant la position de véhicules, p. ex. de véhicules à horaire déterminé à une station centrale
H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p. ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
H04N 19/13 - Codage entropique adaptatif, p. ex. codage adaptatif à longueur variable [CALV] ou codage arithmétique binaire adaptatif en fonction du contexte [CABAC]
H04N 19/159 - Type de prédiction, p. ex. prédiction intra-trame, inter-trame ou de trame bidirectionnelle
H04N 19/52 - Traitement de vecteurs de mouvement par encodage par encodage prédictif
H04N 19/577 - Compensation de mouvement avec interpolation de trame bidirectionnelle, p. ex. utilisation d’images B
H04N 19/61 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant un codage par transformée combiné avec un codage prédictif
H04N 19/70 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par des aspects de syntaxe liés au codage vidéo, p. ex. liés aux standards de compression
A method (200) includes forming (202, 204) a die attach film (DAE) on select portions of a metal substrate and forming (206, 208) lead frame features in the metal substrate while the DAF is present. A lead frame includes a metal substrate having opposite first and second sides that extend in respective first and second planes of a first direction and an orthogonal second direction, and openings extending between the first and second sides of the metal substrate in respective unit areas arranged in rows along the first direction and columns along the second direction, the respective unit areas including a prospective lead, and a DAF extending on select portions of the second side of the metal substrate.
An electronic device (100) includes a first lead (110) extending outward from a first side (101) of a package structure (108), and a second lead (122) extending outward from a second side (102) of the package structure (108). The first lead (110) has an indent (I) corresponding to a position of the second lead (122) along a second direction (Y) that is orthogonal to the first direction (X). A lead frame has unit areas in rows along a first direction and columns along an orthogonal second direction and individually including prospective first and second leads (110, 122), the first lead (110) having first and second portions (111, 112) extending outward along the first direction (X) from a third portion (113) and spaced along the second direction (Y), and the second lead (122) extending along the first direction (X) between the first and second portions (111, 112) of the first lead (110) of an adjacent unit area (310) and to the third portion (113) of the first lead (110) of the adjacent unit area (310).
Methods, apparatus, systems, and articles of manufacture are described for direct current balancing using a zero voltage detection signal. An example system includes a transformer circuit (210); a transistor (302) coupled to the transformer circuit (210); zero voltage detection circuitry (310) coupled to the transistor (302); and a controller (318) coupled to the transistor (302), coupled to the zero voltage detection circuitry (310), and configurable to: receive a signal from the zero voltage detection circuitry (310); detect that one or more pulses are missing from the signal received from the zero voltage detection circuitry (310); and control the transistor (302) in response to detecting that the one or more pulses are missing from the signal.
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 3/00 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H03K 17/13 - Modifications pour commuter lors du passage par zéro
H02M 1/40 - Moyens pour empêcher la saturation magnétique
H02M 7/48 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande
37.
REAL TIME OPTIMIZATION OF IMAGING PARAMETERS IN 3D OPTICAL DEVICES
A device (50) includes a projector (54) to project a pattern, a camera (56) to capture an image of a reflection of the pattern, and a processor (52) to determine multiple intersection points of first and second sets of rays in 3d space, the first set of rays corresponding to the pattern having and the second set of rays corresponding to the pattern in the captured image; determine a set of 3d point clouds responsive to the multiple intersection points and a set of values for a parameter in a parametric model of the projector or camera; compare each of the set of 3d point clouds to a target set of pixels to determine a set of residues; select a value of the set of values responsive to the set of residues; and display an image of an object in an environment of the device with the selected value assigned to the parametric model.
An electronic device and method of fabricating the electronic device are provided where the method (200) includes attaching (204) an electronic device layer on a first surface of a substrate and forming (208) first openings in only the electronic device layer to form individual dies. A back grinding process (214) is performed on a second surface of the substrate and the substrate is placed on an isolation layer. Second openings are formed (218) in the substrate and the isolation layer to form die assemblies comprising the individual dies, the substrate, and the isolation layer. The die assemblies are placed (222) on a leadframe and a mold compound is formed (226) over the die assemblies.
A semiconductor package comprises a package substrate. The package substrate comprises a first metal pad and a second metal pad on a first surface of the package substrate. The semiconductor package also comprises a first layer on the first surface of the package substrate. The first layer comprises one or more trenches. The semiconductor package also comprises a first die on the first layer and coupled to the first metal pad. The semiconductor package also comprises a second die on the first layer and coupled to the second metal pad. The semiconductor package further comprises a mold compound covering the first die, the second die, and the package substrate. The mold compound is in contact with the one or more trenches. The one or more trenches locates between the first die and the second die. The semiconductor package is suitable for high voltage isolation package applications.
A method includes combining a solution of tin(IV) chloride with a processing solvent to form a mixed solution and performing a first mixing process to the mixed solution for a first predetermined time period at a first predetermined temperature. A hydrolysis process is performed to add water to the mixed solution and a second mixing process is performed to the mixed solution for a second predetermined time period at a second predetermined temperature. A concentration process is performed to the mixed solution to remove the processing solvent and a calcination process is performed to the mixed solution to remove the water from the mixed solution thereby converting the mixed solution from a gel to a solid.
G01N 27/12 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de l'absorption d'un fluideRecherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps solide dépendant de la réaction avec un fluide
In some examples, a method includes determining, via a logic circuit, squelch statuses of each of multiple configuration channels. The method also includes determining, via the logic circuit, a number of missed messages for each of the configuration channels. The method also includes determining, via the logic circuit, a transmit status of a communication policy engine. The method also includes determining, via the logic circuit and based on the squelch status of the configuration channels, the number of missed messages for each of the configuration channels, and the transmit status of a communication policy engine, a configuration channel of the configuration channels to communicatively couple to the communication policy engine. The method also includes communicatively couple the determined configuration channel of the configuration channels to a physical layer circuit.
A semiconductor device comprises an NVM array including a plurality of bitcells arranged in rows and columns, each column of bitcells associated with a corresponding bitline, where a bitcell includes a select transistor and a storage transistor. The semiconductor device includes a plurality of sensing interface circuits, each sensing interface circuit disposed between a respective bitline and a corresponding sense amplifier, where a sensing interface circuit includes a sense path transistor having a node (Vdn) configurable to have a voltage modulated by a voltage-dependent resistance.
An example apparatus includes: decimation filter circuitry having an output; multiplexer circuitry having an input, a first output and a second output, the input of the multiplexer circuitry coupled to the output of the decimation filter circuitry; first delay circuitry having an input and an output, the input of the first delay circuitry coupled to the first output of the multiplexer circuitry; first filter circuitry having an input coupled to the output of the first delay circuitry; second delay circuitry having an input and an output, the input of the second delay circuitry coupled to the second output of the multiplexer circuitry; and second filter circuitry having an input coupled to the output of the second delay circuitry.
Methods, apparatus, systems, and articles of manufacture are described for direct current balancing using a zero voltage detection signal. An example system includes a transformer circuit; a transistor coupled to the transformer circuit; zero voltage detection circuitry coupled to the transistor; and a controller coupled to the transistor, coupled to the zero voltage detection circuitry, and configurable to: receive a signal from the zero voltage detection circuitry; detect that one or more pulses are missing from the signal received from the zero voltage detection circuitry; and control the transistor in response to detecting that the one or more pulses are missing from the signal.
H02M 3/335 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu avec transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrodes de commande pour produire le courant alternatif intermédiaire utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/00 - Détails d'appareils pour transformation
H02M 1/08 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques
H02M 1/38 - Moyens pour empêcher la conduction simultanée de commutateurs
Methods, apparatus, systems, and articles of manufacture are described for phase sequencing for multi-phase power converters. An example system includes interface circuitry configurable to couple to a first phase of a power converter and a second phase of the power converter; and processing circuitry coupled to the interface circuitry and configurable to: enable the first phase while the second phase is disabled; responsive to an output current of the power converter satisfying a first threshold after enabling the first phase, enable the first phase and the second phase; and responsive to the output current not satisfying the first threshold after enabling the second phase, disable the second phase while the first phase is enabled.
H02M 7/5395 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur avec commande automatique de la forme d'onde ou de la fréquence de sortie par modulation de largeur d'impulsions
A circuit includes a mixer having a first input, a second input, and an output. A clock generator has an output coupled to the second input of the mixer. An analog-to-digital converter (ADC) has an input coupled to the output of the mixer and has an output. A spur estimator has a first input, a second input, and an output. The first input of the spur estimator is coupled to the output of the ADC. A spur modification circuit has a first input, a control input and an output. The first input of the spur modification circuit is coupled to the second input of the spur estimator, and the control input is coupled to the output of the spur estimator. A transmitter has an input coupled to the output of the spur modification circuit and has an output coupled to the first input of the mixer.
In some examples, a method for manufacturing a semiconductor package comprises coupling first and second semiconductor dies to a metal frame; covering the first and second semiconductor dies and the metal frame with a mold compound; coupling first and second passive components to the first and second semiconductor dies, the first and second passive components on an external surface of the mold compound; sawing through a portion of the metal frame from a first direction to form a first vertical surface of the metal frame, the first vertical surface having a first roughness due to the sawing; and laser cutting through the mold compound and a remainder of the metal frame from a second direction opposing the first direction to form a second vertical surface on the metal frame and a third vertical surface on the mold compound, the second vertical surface having a second roughness due to the laser cutting and the third vertical surface having a third roughness due to the laser cutting.
In an example, a radar system includes a signal generator to generate frequency modulated continuous wave (FMCW) chirp signals; a digital signal processor (DSP); a memory; N transmitters, where N≥2; N phase shifters coupled between the signal generator and the N transmitters, and a temperature sensor. Each of the N phase shifters is to be programmed with a respective base phase shift, which is different for each of the N phase shifters, and each of the N phase shifters is further to be programmed with an initial offset phase shift. The DSP is configured to, in response to ambient temperature measured by the temperature sensor, adjust the initial offset phase shift based on temperature-dependent code offset information stored in the memory.
G01S 13/38 - Systèmes pour mesurer la distance uniquement utilisant la transmission d'ondes continues, soit modulées en amplitude, en fréquence ou en phase, soit non modulées avec comparaison en phase du signal reçu avec le signal transmis au même moment dans lesquels l'on utilise plusieurs fréquences de modulation
In examples, an electronic device (350) includes a semiconductor die (302); a bond pad (306) coupled to the semiconductor die; a bond wire (312) coupled to the bond pad; and an acid anhydride material (314) covering the bond wire and having a physicochemical property that varies by less than 1% throughout a volume of the acid anhydride material relative to a reference measurement of the physicochemical property in the acid anhydride material.
An example apparatus includes an inverter having a first terminal and a second terminal coupled to an enable terminal. The apparatus includes a first transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inverter, the first terminal coupled to a supply terminal. The apparatus includes a second transistor having a control terminal, a first terminal, and a second terminal, the first terminal coupled to the second terminal of the first transistor. The apparatus includes an inductor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a capacitor having a first terminal coupled to the second terminal of the second transistor and a second terminal coupled to the control terminal of the second transistor. The apparatus includes a third transistor having a control terminal, a first terminal, and a second terminal, the control terminal coupled to the first terminal of the inductor and the first terminal of the capacitor, the second terminal coupled to the second terminal of the inductor and the second terminal of the capacitor. The apparatus includes a fourth transistor having a control terminal coupled to the enable terminal, a first terminal coupled to a ground terminal, and a second terminal coupled to the first terminal of the third transistor.
H03B 5/12 - Éléments déterminant la fréquence comportant des inductances ou des capacités localisées l'élément actif de l'amplificateur étant un dispositif à semi-conducteurs
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
An electronic device includes a first lead extending outward from a first side of a package structure, and a second lead extending outward from a second side of the package structure. The first lead has an indent corresponding to a position of the second lead along a second direction that is orthogonal to the first direction. A lead frame has unit areas in rows along a first direction and columns along an orthogonal second direction and individually including prospective first and second leads, the first lead having first and second portions extending outward along the first direction from a third portion and spaced along the second direction, and the second lead extending along the first direction between the first and second portions of the first lead of an adjacent unit area and to the third portion of the first lead of the adjacent unit area.
A method includes forming a die attach film (DAF) on select portions of a metal substrate and forming lead frame features in the metal substrate while the DAF is present. A lead frame includes a metal substrate having opposite first and second sides that extend in respective first and second planes of a first direction and an orthogonal second direction, and openings extending between the first and second sides of the metal substrate in respective unit areas arranged in rows along the first direction and columns along the second direction, the respective unit areas including a prospective lead, and a DAF extending on select portions of the second side of the metal substrate.
A semiconductor device can include a supporting structure and a die that can include a surface on which wire posts can be located and coupled to die connection points. The wire posts can be coupled using solder to the supporting structure. For example, the wire posts can be formed on a wafer using a wire, which can be cut to provide the die. First and second end portions of the wire can be bonded to the wafer. A resist layer can be formed on a surface of the wafer to cover each of the first and second end portions while leaving a middle portion of the wire exposed. The middle portion of the wire can be grinded to leave the first and second wire portions of the wire embedded within the resist layer to form wire posts. The resist layer can be removed to reveal the wire posts.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 21/78 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels
In examples, an electronic device includes a semiconductor die; a bond pad coupled to the semiconductor die; a bond wire coupled to the bond pad; and an acid anhydride material covering the bond wire and having a physicochemical property that varies by less than 1% throughout a volume of the acid anhydride material relative to a reference measurement of the physicochemical property in the acid anhydride material.
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
An apparatus includes a semiconductor device having a first semiconductor layer (212) and a second semiconductor layer (208), and the first semiconductor layer (212) has dopants of opposite polarities. The semiconductor device includes a bias circuit (120) implemented in the first semiconductor layer (212). The bias circuit (120) has a first terminal (232), a second terminal (236), a third terminal (240), and a fourth terminal (244). The second terminal (236) is coupled to the first semiconductor layer (212) and the third terminal (240) is coupled to the second semiconductor layer (208). The bias circuit (120) includes a charge circuit coupled between the first terminal (232) and the third terminal (240), a discharge circuit coupled between the third terminal (240) and the second terminal (236), and a rectifying device coupled between the third terminal (240) and the fourth terminal (244).
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
G05F 3/20 - Régulation de la tension ou du courant là où la tension ou le courant sont continus utilisant des dispositifs non commandés à caractéristiques non linéaires consistant en des dispositifs à semi-conducteurs en utilisant des combinaisons diode-transistor
H02H 3/087 - Circuits de protection de sécurité pour déconnexion automatique due directement à un changement indésirable des conditions électriques normales de travail avec ou sans reconnexion sensibles à une surcharge pour des systèmes à courant continu
H03K 17/16 - Modifications pour éliminer les tensions ou courants parasites
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
56.
Integrated circuit chip with cores asymmetrically oriented with respect to each other
An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/333 - Conception en vue de la testabilité [DFT], p. ex. chaîne de balayage ou autotest intégré [BIST]
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A method is disclosed herein. The method includes forming a material layer over a dielectric layer, performing a treatment process, forming a treated material layer as a result of performing the treatment process, and forming a photoresist layer over the treated material layer. The treated material layer has an increased oxygen concentration compared to the material layer.
An example apparatus includes target signal generator circuitry to generate a target signal having a first center frequency and a bandwidth. The example apparatus additionally includes companion signal generator circuitry to generate a companion signal having a second center frequency that is less than (a) the first center frequency adjusted by a first threshold and greater than (b) the first center frequency adjusted by a second threshold, the first threshold being a first multiple of the bandwidth, the second threshold being a second multiple of the bandwidth, the first multiple different than the second multiple. In some examples, the example apparatus includes adder circuitry to combine the target signal and the companion signal to form a composite signal. Additionally, the example apparatus includes transmitter circuitry to transmit the composite signal to a target device.
An apparatus includes a semiconductor device having a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has dopants of opposite polarities. The semiconductor device includes a bias circuit implemented in the first semiconductor layer. The bias circuit has a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal is coupled to the first semiconductor layer and the third terminal is coupled to the second semiconductor layer. The bias circuit includes a charge circuit coupled between the first terminal and the third terminal, a discharge circuit coupled between the third terminal and the second terminal, and a rectifying device coupled between the third terminal and the fourth terminal.
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
60.
Module with Reversely Coupled Inductors and Magnetic Molded Compound (MMC)
An apparatus includes a base, a magnetic core, and a first inductor and a second inductor on the base. The magnetic core includes at least a first core portion. The first inductor includes a first portion at least partially wrapping around the first core portion, two second portions coupled to two sides of the first portion, and two third portions on the base and coupled to the two second portions respectively. The second inductor is reversely coupled with the first inductor. The second inductor includes a fourth portion at least partially wrapping around the first core portion, two fifth portions coupled to two sides of the fourth portion, and two sixth portions on the base and coupled to the two fifth portions respectively.
H01F 27/34 - Moyens particuliers pour éviter ou réduire les effets électriques ou magnétiques indésirables, p. ex. pertes à vide, courants réactifs, harmoniques, oscillations, champs de fuite
H01F 41/00 - Appareils ou procédés spécialement adaptés à la fabrication ou à l'assemblage des aimants, des inductances ou des transformateursAppareils ou procédés spécialement adaptés à la fabrication des matériaux caractérisés par leurs propriétés magnétiques
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
61.
NARROWBAND SENSORS BASED ON PLASMONIC METASURFACES INTEGRATED ON PIEZOELECTRIC PLATES
An optical detector system includes a light source configured to emit light having a frequency spectrum and modulated in time, and an optical detector configured to detect an intensity of the light at a wavelength range within the frequency spectrum. The optical detector includes a piezoelectric layer, a first metal layer coupled to a first surface of the piezoelectric layer, a second metal layer coupled to a second surface of the piezoelectric layer, and a plasmonic metasurface coupled to the first metal layer and configured to absorb the light at the wavelength range, the plasmonic metasurface including metal structures and a dielectric layer disposed on the first metal layer. The optical detector system further includes a voltage detector coupled to the first metal layer and the second metal layer, the voltage detector configured to detect a voltage at a frequency of the modulated light.
G02B 1/00 - Éléments optiques caractérisés par la substance dont ils sont faitsRevêtements optiques pour éléments optiques
H10N 30/30 - Dispositifs piézo-électriques ou électrostrictifs à entrée mécanique et sortie électrique, p. ex. fonctionnant comme générateurs ou comme capteurs
H10N 30/50 - Dispositifs piézo-électriques ou électrostrictifs avec une structure empilée ou multicouche
H10N 30/85 - Matériaux actifs piézo-électriques ou électrostrictifs
H10N 30/87 - Électrodes ou interconnexions, p. ex. connexions électriques ou bornes
A digital-to-time converter circuit includes a scrambling and noise shaping circuit, a digital-to-analog converter (DAC), and a buffer circuit. The scrambling and noise shaping circuit includes an input and an output. The input is coupled to a delay input terminal. The scrambling and noise shaping circuit is configured to generate a residue value signal that scrambles and noise shapes a mismatch error. The DAC includes an input and an output. The input of the DAC is coupled to the output of the scrambling and noise shaping circuit. The DAC is configured to generate a residue timing signal based on the residue value signal that scrambles and noise shapes the mismatch error. The buffer circuit includes an input and an output. The input of the buffer circuit is coupled to the output of the DAC. The output of the buffer circuit is coupled to a signal output terminal.
An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.
A circuit (125) includes a digital circuit (120), a pullup circuit (320), a first/second pulldown circuits (332/334), and a ground loss detection unit (GLDA) (160). The digital circuit (120) generates a control signal (122) for enabling/disabling an output channel (142) based on an input signal. The pullup circuit (320) enables the output channel (142) if the control signal (252) has a first value, by controlling a gate of a switch (140) that couples a power source (180) to the load (150). The first pulldown circuit (332) disables the output channel (142) if the control signal (252) has a second value, by controlling the gate. The GLDA (160) generates a ground loss triggering signal (162) by comparing a voltage associated with the ground (172) to an auxiliary voltage (192). A first value indicates loss of ground connection. The second pulldown circuit (334) pulls a gate of the switch (140) to the source of the switch (140) when the ground loss triggering signal (162) has the first value.
B60R 16/023 - Circuits électriques ou circuits de fluides spécialement adaptés aux véhicules et non prévus ailleursAgencement des éléments des circuits électriques ou des circuits de fluides spécialement adapté aux véhicules et non prévu ailleurs électriques pour la transmission de signaux entre des parties ou des sous-systèmes du véhicule
B60L 50/60 - Propulsion électrique par source d'énergie intérieure au véhicule utilisant de la puissance de propulsion fournie par des batteries ou des piles à combustible utilisant de l'énergie fournie par des batteries
Disclosed herein is a device including a first voltage rail and a second voltage rail configured to provide a first voltage. A current source component is conductively coupled to the first voltage rail and the second voltage rail and is configured to provide a first current. A voltage translator is conductively coupled to the second voltage rail and the current source component and is configured to invert the first voltage to a second voltage and provide an output signal including the first current and the second voltage.
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
An apparatus includes a current sense amplifier having an output. The current sense amplifier includes a resistor coupled to the output. The current sense amplifier is configured to produce a current through the resistor. An auto zero circuit has an input coupled to the output of the current sense amplifier. The auto zero circuit is configured to iteratively adjust a second current from the output of the current sense amplifier through the auto zero circuit based on a voltage across the resistor.
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
Disclosed embodiments relate to a streaming engine employed in, for example, a digital signal processor. A fixed data stream sequence including plural nested loops is specified by a control register. The streaming engine includes an address generator producing addresses of data elements and a steam head register storing data elements next to be supplied as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer. Parity bits are formed upon storage of data in the stream buffer which are stored with the corresponding data. Upon transfer to the stream head register a second parity is calculated and compared with the stored parity. The streaming engine signals a parity fault if the parities do not match. The streaming engine preferably restarts fetching the data stream at the data element generating a parity fault.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
G06F 12/0897 - Mémoires cache caractérisées par leur organisation ou leur structure avec plusieurs niveaux de hiérarchie de mémoire cache
G06F 13/38 - Transfert d'informations, p. ex. sur un bus
In an example, a light modulator includes an array of pixel elements grouped into blocks and arranged with a minimum pixel pitch, and configurable between ON and OFF states; reset control circuitry coupled to the pixel elements and configurable to control the states of the pixel elements; and light-blocking apparatus configured to protect the reset control circuitry from stray carriers induced by incident light. The reset control circuitry may include: banks of pixel block drivers configurable to output reset voltages for individual blocks, each bank of pixel block drivers including a bank of reset capacitors and one or more reset drivers arranged according to the minimum pixel pitch; a signal bus coupled to the banks of pixel block drivers; and one or more supply voltage generators selectively couplable to the signal bus and configurable to generate a supply voltage for one or more of the banks of pixel block drivers.
G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
G09G 3/02 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques par traçage ou balayage d'un faisceau lumineux sur un écran
G02B 26/08 - Dispositifs ou dispositions optiques pour la commande de la lumière utilisant des éléments optiques mobiles ou déformables pour commander la direction de la lumière
G02F 1/1362 - Cellules à adressage par une matrice active
A method of forming a package including a substrate, a conductive layer on a first surface of the substrate forming a set of antennas, and a semiconductor die forming communication channels for the antennas, each of the communication channels being electrically coupled to the antennas by way of a redistribution layer that includes the substrate, the semiconductor die being mounted on either the first surface or an opposing second surface of the substrate. The package further includes a set of electrical contacts on the second surface of the substrate, the redistribution layer further coupling the set of electrical contacts to the semiconductor die. The package further includes a stiffening layer over the first surface of the substrate, the stiffening layer forming gaps over the antennas such that the antennas are on an outer surface of the package.
One example includes a passive radar receiver system including an RF receiver front-end to receive a wireless source signal and a reflected signal. An antenna switch of the front-end switches a first antenna to a receiver chain during a first time to generate first radar signal data based on a combined wireless signal comprising wireless source signal and the reflected signal, and switches a second antenna to the receiver chain during a second time to generate second radar signal data based on the combined wireless signal. A signal processor generates source signal data associated with the wireless source signal based on the first and second radar signal data and generates reflected signal data associated with the reflected signal based on the first and second radar signal data, and generates target radar data associated with a target based on the source and reflected radar signal data.
G01S 1/04 - Radiophares ou systèmes de balisage émettant des signaux ayant une ou des caractéristiques pouvant être détectées par des récepteurs non directionnels et définissant des directions, situations ou lignes de position déterminées par rapport aux émetteurs de radiophareRécepteurs travaillant avec ces systèmes utilisant les ondes radioélectriques Détails
G01S 19/25 - Acquisition ou poursuite des signaux émis par le système faisant intervenir des données d'assistance reçues en provenance d'un élément coopérant, p. ex. un GPS assisté
G01S 19/30 - Acquisition ou poursuite des signaux émis par le système lié au code
A microelectromechanical system (MEMS) switch implemented with a coplanar waveguide. The MEMS switch includes an input terminal, an output terminal. The MEMS switch includes a beam extending between the input terminal and the output terminal. The beam includes a first edge and a second edge coupled to a gate of the MEMS switch. The beam includes a third edge proximate the input terminal. The first edge includes a first set of finger contacts proximate a first corner of the beam and a second set of finger contacts proximate a second corner of the beam. The beam includes a fourth edge proximate the output terminal, the fourth edge opposing the third edge. The MEMS switch has a first anchor coupled to the input terminal. The first anchor includes a first segment extending from a region proximate the input terminal to a region overlying the first set of finger contacts.
A circuit includes a digital circuit, a pullup circuit, a first/second pulldown circuits, and a ground loss detection unit (GLDA). The digital circuit generates a control signal for enabling/disabling an output channel based on an input signal. The pullup circuit enables the output channel if the control signal has a first value, by controlling a gate of a switch that couples a power source to the load. The first pulldown circuit disables the output channel if the control signal has a second value, by controlling the gate. The GLDA generates a ground loss triggering signal by comparing a voltage associated with the ground to an auxiliary voltage. A first value indicates loss of ground connection. The second pulldown circuit pulls a gate of the switch to the source of the switch when the ground loss triggering signal has the first value.
H03K 17/10 - Modifications pour augmenter la tension commutée maximale admissible
B60L 3/00 - Dispositifs électriques de sécurité sur véhicules propulsés électriquementContrôle des paramètres de fonctionnement, p. ex. de la vitesse, de la décélération ou de la consommation d’énergie
H03K 19/003 - Modifications pour accroître la fiabilité
In some examples, a device is configured to determine, at a first time, a first cell voltage of a battery cell. The device is also configured to determine, at a second time, a second cell voltage of the battery cell. The device is also configured to estimate a future cell voltage of the battery cell using the first cell voltage and the second cell voltage, the future cell voltage for a third time subsequent to the second time. The device is also configured to estimate an open circuit voltage of the battery cell using the estimated future cell voltage of the battery cell, an impedance of the battery cell, and a current measurement of the battery cell at the second time.
G01R 31/3842 - Dispositions pour la surveillance de variables des batteries ou des accumulateurs, p. ex. état de charge combinant des mesures de tension et de courant
G01R 31/389 - Mesure de l’impédance interne, de la conductance interne ou des variables similaires
A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.
A processor-implemented method includes receiving a set of shared weights and receiving first input data to a first layer of a neural network. The processor-implemented method also includes determining, based on the first input data, weights for the first layer as a first combination of the set of shared weights. The weights for the first layer can be applied to the first input data. The processor-implemented method also includes receiving second input data to a second layer of the neural network and determining, based on the second input data, weights for the second layer as a second combination of the set of shared weights. The weights for the second layer can be applied to the second input data.
In described examples, a retimer includes a reference voltage generator, first, second, third, and fourth comparators, a hit sensor, a window results comparison circuit, and a window control circuit. First inputs of the first, second, third, and fourth comparators receive samples of a data stream. First, second, third, and fourth outputs of the reference voltage generator are coupled to respective second inputs of the first, second, third, and fourth comparators. The third and fourth comparators output to, respectively, first and second inputs of the hit sensor. The hit sensor outputs to an input of the window results comparison circuit. The window results comparison circuit outputs to an input of the window control circuit. The window control circuit outputs to an input of the reference voltage generator.
H03L 7/085 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie
H03L 7/08 - Détails de la boucle verrouillée en phase
H03L 7/083 - Détails de la boucle verrouillée en phase le signal de référence étant appliqué additionnellement et directement au générateur
H03L 7/107 - Détails de la boucle verrouillée en phase pour assurer la synchronisation initiale ou pour élargir le domaine d'accrochage utilisant une fonction de transfert variable pour la boucle, p. ex. un filtre passe-bas ayant une largeur de bande variable
H04L 25/24 - Circuits à relais utilisant des tubes à décharge ou dispositifs à semi-conducteurs
Various boundary detection methods are provided, as are structure and components for carrying out the methods. Processing may be directed by instructions stored on a non-transitory computer-readable medium. In an example, processing circuitry executes instructions stored on such a medium to continuously track movement of a user within a bounded area during a boundary detection process based on radar data received by the processing circuitry; estimate locations of segments of the boundary based on initial movement data; update the estimated locations based on during the boundary detection process as new movement data is received; provide feedback to the user regarding status of the boundary detection process; and terminate the boundary detection process when the processing circuitry determines that the latest updated estimated locations are satisfactory for estimating the boundary.
A method includes detecting, by a coexistence controller of a system on a chip (SoC), an occurrence of a coexistence event of an SoC component; providing, by the coexistence controller, an indication of the occurrence of the coexistence event to a coexistence coordinator; and changing, by the coexistence controller, an operating point of the SoC from a current operating point to a new operating point responsive to receiving an operating point change request from the coexistence coordinator.
In an embodiment, a method includes identifying, by a first device, a level of degradation. The method also includes transmitting, by the first device during a communication phase, a first signal with a first signal quality based on the level of degradation. The method further includes transmitting, by the first device during a second communication phase, a second signal with a second signal quality. The second signal quality may be greater than the first signal quality.
Methods, systems, and devices are provided that reduce image artifacts, particularly during system power up from a sleep mode. In an example, a method includes receiving a system enable signal at a receiver, a bias generator and a delay circuit; ramping up, by the bias generator in response to the system enable signal, a bias current using a quick turn-on circuit of the bias generator; turning off the quick turn-on circuit at a first time after receiving the system enable signal; and transmitting, by the delay circuit to a control input of a buffer coupled to an output of the receiver, a buffer enable signal at a second time after receiving the system enable signal to enable the buffer, which is in a disabled state before receiving the buffer enable signal. The second time occurs after the first time.
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03K 5/1252 - Suppression ou limitation du bruit ou des interférences
H03K 19/003 - Modifications pour accroître la fiabilité
A circuit includes a fixed frequency controller, a constant on-time controller, a phase-frequency detector, and a voltage-to-current converter. The fixed frequency controller has a first control pulse output, and a clock output. The constant on-time controller has a second control pulse output, and a frequency control input. The phase-frequency detector has a first input coupled to the clock output, a second input coupled to the second control pulse output, and a phase control output. The voltage-to-current converter has a voltage input coupled to the phase control output, and a current output coupled to the frequency control input.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
An apparatus includes a sample-and-hold circuit having an input and an output. A switching converter has an output and an amplifier. The amplifier has first and second inputs. The output of the switching converter is coupled to the input of the sample-and-hold circuit. A switch circuit has a first switch input, a first switch output, and a second switch output. The first switch output is coupled to the first input of the amplifier, and the second switch output is coupled to the second input of the amplifier. The first switch input is coupled to the output of the sample-and-hold circuit.
An oscillator has an enable input and an oscillator output. A voltage regulator has an enable input. A logic circuit has a control input, a control output and a status output and has a counter having a clock input coupled to the oscillator output. The control output couples to the enable inputs of the oscillator and the voltage regulator. The logic circuit is configured to: in response to a first control value at the control input, assert a control signal at the control output to a first logic state to enable the oscillator, cause the counter to count, and disable the voltage regulator; and in response to the counter reaching a terminal value, set a status signal at the status output to a first logic state, and assert the control signal at the control output to a second logic state to disable the oscillator and enable the voltage regulator.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
G01R 31/392 - Détermination du vieillissement ou de la dégradation de la batterie, p. ex. état de santé
H02J 7/00 - Circuits pour la charge ou la dépolarisation des batteries ou pour alimenter des charges par des batteries
84.
INTERCONNECT TO ENHANCE RELIABILITY AND PERFORMANCE OF A SEMICONDUCTOR PACKAGE
Interconnects and semiconductor packages that include a cavity on lead pads of leads of the interconnect to contain a portion of a solder bump are discussed. One example is a method of forming a semiconductor package. The method includes applying solder to cavities on leads of an interconnect. The cavities are on a top surface of a respective lead. The method also includes mounting a molded interconnect substrate (MIS) on the interconnect. The method additionally includes mounting a semiconductor die electrically coupled to the MIS. The method further includes encapsulating the MIS, the semiconductor die and a portion of the interconnect in a mold compound.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
A method of fabricating an electronic component includes: controlling a laser cutting tool at a first pulse rate to form a first cut portion in a feature of the electronic component, the feature having opposite first and second sides spaced apart from one another along a first direction, and third and fourth sides spaced apart from one another along a second direction, the first cut portion extending from the third side toward the fourth side; controlling the laser cutting tool at a higher second pulse rate and to form a second cut portion extending from the first cut portion toward the fourth side; and controlling the laser cutting tool at a third pulse rate to form a final cut portion extending from the second cut portion toward the fourth side, the third pulse rate less than the second pulse rate.
B23K 26/38 - Enlèvement de matière par perçage ou découpage
B23K 26/0622 - Mise en forme du faisceau laser, p. ex. à l’aide de masques ou de foyers multiples par commande directe du faisceau laser par impulsions de mise en forme
B23K 26/08 - Dispositifs comportant un mouvement relatif entre le faisceau laser et la pièce
In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.
A semiconductor die (200) comprises a first bump structure (202). The first bump structure (202) comprises a pillar portion (208) and a solder portion (210) attached to the pillar portion (208). The first bump structure (202) is a signal bump structure of the semiconductor die that transmits electrical signals between the semiconductor die and a leadframe. The semiconductor die further comprises a second bump structure (204). The second bump structure (204) comprises a base portion (212), a plurality of pillar portions (214) on the base portion (212), and a plurality of solder portions (216) attached to the plurality of pillar portions (214). The second bump structure (204) is a power bump structure of the semiconductor die that transmits power between the semiconductor die and the leadframe.
An apparatus includes a voltage control circuit. A first current control circuit has a first current control circuit input coupled to the voltage control circuit's output and has a second current control circuit input. A second current control circuit has a third current control circuit input coupled to the voltage control circuit's output and has a fourth current control circuit input. A current balance circuit has a first current balance circuit output and a second current balance circuit output. The first current balance circuit output couples to the second current control circuit input. The second current balance circuit output couples to the fourth current control circuit input. The current balance circuit generates first and second currents. The first and second currents are based on a difference between a first average current of the first current control circuit and a second average current of the second current control circuit.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G09G 3/34 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante
H05B 45/325 - Modulation de la largeur des impulsions [PWM]
An electronic device includes a leadframe and one or more substrate assemblies attached to the leadframe. The one or more substrate assemblies include a first substrate layer and a second substrate layer attached to the first substrate layer. A first electronic component is formed in one or both of the first substrate layer and the second substrate layer. A second electronic component is formed in one or both of the first substrate layer and the second substrate layer such that the first electronic component and the second electronic component are interdigitated. One or more dies are attached to the leadframe and are electrically connected to the substrate assembly via wire bonds. A mold compound encapsulates the one or more substrate assemblies and the one or more dies.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Disclosed examples include microelectronic devices, e.g., integrated circuits and methods of making such devices. One example includes a microelectronic device including a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS transistor may include a high-k gate dielectric and a metal gate. The (LDMOS) transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region towards the drain region and field plate conductor layers that extend from the drain region towards the source region with gate dielectric layers and field relief dielectric layers separating the gate conductor layers from the field plate conductor layers.
A circuit includes a latch, a first variable resistor, a second variable resistor, a slew detector, and a conductor configured to provide a power supply voltage. The latch has a first latch input, a second latch input, a first latch output, and a second latch output. The first variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the first latch input, a first control input, and a second control input coupled to the first latch output. The second variable resistor has a first terminal coupled to the conductor, a second terminal coupled to the second latch input, a third control input, and a fourth control input coupled to the second latch output. The slew detector is coupled to the conductor. The slew detector has an output coupled to the first control input and the third control input.
An IC, with: a first semiconductor diode, including a first portion of a first layer having a first conductivity type, a first portion of a second layer having a second conductivity type, and a first metal portion coupled to the first portion of the first layer, the first conductivity type opposite the second conductivity type and a first interface region aligned with the first metal portion and existing along an interface between the first and second layers; a second semiconductor diode, including a second portion of the first layer, a second portion of the second layer, a second metal portion coupled to the second portion of the first layer, and a second interface region aligned with the second metal portion and existing along the interface between the first and second layers; and a resistive region within the first layer and between the first interface region and the second interface region.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
A device comprising a first planar coil and a second planar coil. The first planar coil includes a first plurality of conductive loop segments that are concentric with one another and centered on a first axis. The first axis is spaced laterally from a first side of a plane by a first distance, and the first axis extends in parallel with the plane. The second planar coil is coupled to the first planar coil. The second planar coil includes a second plurality of conductive loop segments that are concentric with one another and centered on a second axis. The second axis extends in parallel with the first axis, and is spaced laterally from a second side of the plane by the first distance. The second side is opposite from the first side. The first planar coil is symmetric to the second planar coil about the plane.
H03L 7/099 - Détails de la boucle verrouillée en phase concernant principalement l'oscillateur commandé de la boucle
H03F 3/21 - Amplificateurs de puissance, p. ex. amplificateurs de classe B, amplificateur de classe C comportant uniquement des dispositifs à semi-conducteurs
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
94.
BUMP STRUCTURES FOR FLIP CHIP ON LEADFRAME PACKAGE
A semiconductor package comprises a semiconductor die. The semiconductor die comprises a metal pad. The semiconductor package also comprises a leadframe. The semiconductor package further comprises a bump structure between the semiconductor die and the leadframe. The bump structure comprises a first solder portion. The first solder portion is in contact with the metal pad. The bump structure also comprises a second solder portion. The second solder portion is in contact with the leadframe. The bump structure further comprises a metal post between the first solder portion and the second solder portion. The bump structure could reduce stress in BEOL layer of the semiconductor die to improve reliability of the semiconductor package.
A system includes a phase locked loop (PLL), which includes a filter. The filter may include a first amplifier and a second amplifier, where a feedback current from the first amplifier and the second amplifier is based on a parallel resistance of multiple parallel feedback resistors. The feedback current may be coupled to a noninverting input of the first amplifier.
H03L 7/093 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant des caractéristiques de filtrage ou d'amplification particulières dans la boucle
An apparatus has a laminate substrate that has a first surface and a second surface opposing the first surface. A laminate transformer is located within the laminate substrate and between the first surface and the second surface. The transformer has a first coil and a second coil. A magnetic core element on the first surface overlaps a portion of the first coil. A lead frame on the first surface is spaced apart from the magnetic core element. A portion of the lead frame overlaps a portion of the first coil to provide a thermal conductive path.
An apparatus comprises a substrate, an antenna on the substrate and configured to emit electromagnetic waves, and a device mounted on the substrate. The device includes an aperture aligned with the antenna and configured to receive the electromagnetic waves from the antenna.
A sensor includes a resonator (e.g., a bulk acoustic wave (BAW) resonator) and a plasmonic metasurface coupled to the BAW resonator. The plasmonic metasurface is configured to convert incident light in a target wavelength range into thermal energy. The resonator is configurable to change its resonance frequency responsive to the thermal energy.
In described examples, an integrated circuit (IC) includes multiple subcircuits. The subcircuits include a first subcircuit that receives a current and sinks a portion of the current that is responsive to a threshold. In response to the current being greater than the threshold, the first subcircuit provides a difference between the current and the portion to a second subcircuit and asserts a signal corresponding to an ordinality of the first subcircuit. The second subcircuit is configured to repeat the actions with respect to the first subcircuit, with the second subcircuit in place of the first subcircuit and a third subcircuit in place of the second subcircuit, and with the difference in place of the current, in response to the IC comprising the third subcircuit.
G05F 3/02 - Régulation de la tension ou du courant
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
An apparatus comprises a substrate, a transceiver on a side of the substrate, an antenna on a side of the substrate and coupled to the transceiver, and a device mounted on the substrate. The device includes an aperture aligned with the antenna and configured to receive electromagnetic waves from the antenna.
G04F 5/14 - Appareils pour la production d'intervalles de temps prédéterminés, utilisés comme étalons utilisant des horloges atomiques
H03L 7/26 - Commande automatique de fréquence ou de phaseSynchronisation utilisant comme référence de fréquence les niveaux d'énergie de molécules, d'atomes ou de particules subatomiques
