A method for in-loop filtering in a video encoder is provided that includes determining filter parameters for each filtering region of a plurality of filtering regions of a reconstructed picture, applying in-loop filtering to each filtering region according to the filter parameters determined for the filtering region, and signaling the filter parameters for each filtering region in an encoded video bit stream, wherein the filter parameters for each filtering region are signaled after encoded data of a final largest coding unit (LCU) in the filtering region, wherein the in-loop filtering is selected from a group consisting of adaptive loop filtering and sample adaptive offset filtering.
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/132 - Sampling, masking or truncation of coding units, e.g. adaptive resampling, frame skipping, frame interpolation or high-frequency transform coefficient masking
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
In an example, a controller causes a first camera of a first device to capture a first image of a first subset of a projected pattern of points, and causes a second camera of a second device to capture a second image of a second subset of the pattern of points. The first and second subsets partially overlap. Based on the first and second images, the controller generates first and second point clouds having first and second coordinate systems, respectively. The controller then determines a rigid body transform to convert coordinates of points in at least one of the two point clouds to coordinates in a reference coordinate system, applies the rigid body transform to generate a transformed point cloud, and generates a corrected point cloud based on the transformed point cloud.
In an embodiment, a method (800) includes; determining a bin corresponding to a radio frequency interference (RFI) spur in a signal, the bin based on a first sampling frequency of a timing loop in a receiver (802); determining a shift of the first sampling frequency to a second sampling frequency (804); updating the bin based on the shift (806); setting a filter coefficient of a notch filter based on the updated bin (808); suppressing the RFI spur using the notch filter (810); and establishing link- up between the receiver and another device after suppressing the RFI spur (812).
H04B 1/10 - Means associated with receiver for limiting or suppressing noise or interference
H04B 1/525 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
4.
DIELECTRIC SILICON NITRIDE BARRIER DEPOSITION PROCESS FOR IMPROVED METAL LEAKAGE AND ADHESION
An electronic device includes a semiconductor die having a multilevel metallization structure including stacked levels with respective dielectric layers and metal lines, and a low leakage, low hydrogen diffusion barrier layer on one of the stacked levels. The diffusion barrier layer contacts a side of the dielectric layer and the metal line of the one of the stacked levels, and the diffusion barrier layer includes silicon nitride material having a first bond percentage ratio of ammonia to silicon nitride that is greater than a second bond percentage ratio of silicon hydride to silicon nitride.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A comparator includes a differential input, an output, a pair of first transistors coupled to the differential input, a pair of second transistors coupled to the output, and a SET protection circuit. Gate terminals of the pair of first transistors are coupled to the differential input of the comparator. The second terminals of the pair of second transistors are coupled to the second terminals of the pair of first transistors. The SET protection circuit has a current source and a transistor. The transistor of the SET protection circuit has a first terminal coupled to the body terminals of the pair of first transistors to bias the body terminals of the pair of first transistors separate from the first terminals of the pair of first transistors. A gate terminal of the transistor of the SET protection circuit is coupled to a terminal of the differential input of the comparator.
A method and apparatus for sample adaptive offset without sign coding. The method includes selecting an edge offset type for at least a portion of an image, classifying at least one pixel of at least the portion of the image into edge shape category, calculating an offset of the pixel, determining the offset is larger or smaller than a predetermined threshold, changing a sign of the offset based on the threshold determination; and performing entropy coding accounting for the sign of the offset and the value of the offset.
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/14 - Coding unit complexity, e.g. amount of activity or edge presence estimation
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
7.
PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS
A wireless transmission system included at least one user equipment and a base station. The base station is operable to form a downlink control information block, modulate the downlink control information, precode the modulated downlink control information, and transmit the precoded, modulated downlink control information on at least one demodulation reference signal antenna port to the at least one user equipment. The precoded, modulated downlink control information is mapped to a set of N1 physical resource block pairs in a subframe from an orthogonal frequency division multiplexing symbol T1 to and orthogonal frequency division multiplexing symbol T2.
Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub- circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub- circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.
Embodiments include a system having processing circuitry to execute instructions to perform a variety of activities, operate in any of multiple operating modes, as well as run any of multiple virtual machines. A register stores operating state information of the processing circuitry. The processing circuitry is further able to selectively service requests issued by a controller coupled to the processing circuitry. Each service request includes one or more fields, each of which includes data to specify a respective qualifier for servicing. Each qualifier can be enabled to make the qualifier a condition of servicing the debug request. When all enabled qualifiers are satisfied, the processing circuitry services the service request. Servicing of the request may be performed in real-time without suspending the processing circuitry.
A wafer center monitoring system associated with a semiconductor processing tool. In one example, the semiconductor processing tool may include a wafer stage and an imaging system configured to determine a spatial relationship between a processed area of a semiconductor wafer on the wafer stage and a plurality of fiducial markers placed at a corresponding plurality of locations along a perimeter of the semiconductor wafer.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
11.
POWER STAGE SAFETY AND LATCH-UP PREVENTION IN MULTI-PHASE DC-DC CONVERTER BY ENSURING SAFE PWM SEQUENCING
The techniques and circuits, described herein, include solutions for latch-up prevention in multi-phase direct current (DC) to DC converters by ensuring safe pulse width modulation (PWM) control sequencing. In some aspects a latch-up pre-detection circuit has first and second detection inputs configured to receive high-side and low-side PWM signals respectively. The latch-up pre-detection circuit is configured to monitor for a transition from a first state to a second state based on the first and second detection inputs. The transition from the first state to the second state may be associated with condition(s) favorable for latch-up. Upon detecting the transition from the first state to the second state, the latch-up pre-detection circuit can output a pulse signal to temporarily override the unsafe PWM control sequence and reduce the possibility of latch-up.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A described example includes a circuit (100). The circuit (100) can include a current sense circuit (106) having a sense input and a sense output, in which the sense input is coupled to an input terminal. A comparator (114) has a first comparator input, a second comparator input, and a comparator output, in which the first comparator input is coupled to the sense output, the second comparator input is coupled to a threshold terminal, and the comparator output is coupled to a fuse terminal. A current programming circuit (128) has a current input and a current output, in which the current input is coupled to the sense output. A first circuit (134) is coupled between the sense output and a ground terminal. A second circuit (136) is coupled between the current output and the ground terminal.
H02H 3/00 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
In an embodiment, an apparatus (112) includes: a transmitting data path configured to transmit an outgoing data packet; and a receiving data path configured to receive an incoming data packet; a controller (212) configured to determine timing information of the incoming data packet; and dithering circuitry (116) configured to dither a reference signal according to the timing information to vary a frequency of the signal over time to generate a dithered recovered signal.
Light projectors, examples of which may be used in headlight assemblies and/or other display applications. In one example, a system (110) includes a phase light modulator (202), a phosphor device (204) optically coupled to the phase light modulator (202), and a spatial light modulator (206) optically coupled the phosphor device (204).
F21S 41/64 - Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution by acting on refractors, filters or transparent cover plates by changing their light transmissivity, e.g. by liquid crystal or electrochromic devices
F21S 41/675 - Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution by acting on reflectors by moving reflectors
G02B 26/00 - Optical devices or arrangements for the control of light using movable or deformable optical elements
A method for encoding a picture of a video sequence in a bit stream that reduces slice header parsing overhead is provided. The method includes determining weighting factors that may be used for weighted prediction in encoding at least one slice of the picture, wherein a total number of the weighting factors is constrained to not exceed a predetermined threshold number of weighting factors, wherein the threshold number is less than a maximum possible number of weighting factors, and signaling weighted prediction parameters including the weighting factors in a slice header in the bit stream.
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
H04N 19/23 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using video object coding with coding of regions that are present throughout a whole video segment, e.g. sprites, background or mosaic
H04N 19/46 - Embedding additional information in the video signal during the compression process
H04N 19/503 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal prediction
A method for sample adaptive offset (SAO) filtering and SAO parameter signaling in a video encoder is provided that includes determining SAO parameters for largest coding units (LCUs) of a reconstructed picture, wherein the SAO parameters include an indicator of an SAO filter type and a plurality of SAO offsets, applying SAO filtering to the reconstructed picture according to the SAO parameters, and entropy encoding LCU specific SAO information for each LCU of the reconstructed picture in an encoded video bit stream, wherein the entropy encoded LCU specific SAO information for the LCUs is interleaved with entropy encoded data for the LCUs in the encoded video bit stream. Determining SAO parameters may include determining the LCU specific SAO information to be entropy encoded for each LCU according to an SAO prediction protocol.
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
17.
EFFICIENT REMOVAL OF STREET TEST DEVICES DURING WAFER DICING
In some examples, a method for manufacturing a semiconductor package comprises coupling a photoresist layer to a non-device side of a semiconductor wafer, the semiconductor wafer having a device side, first and second circuits formed in the device side and separated by a scribe street, a test device positioned in the scribe street. The method also comprises coupling a tape to the device side of the semiconductor wafer. The method also comprises performing a photolithographic process to form an opening in the photoresist layer and plasma etching through the semiconductor wafer to produce first and second semiconductor dies having the first and second circuits, respectively. The method also comprises removing the tape, which includes removing the test device. The method also comprises coupling the first circuit of the first semiconductor die to a conductive member. The method also comprises covering the first semiconductor die with a mold compound.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
A method of encoding a video stream in a video encoder is provided that includes computing an offset into a transform matrix based on a transform block size, wherein a size of the transform matrix is larger than the transform block size, and wherein the transform matrix is one selected from a group consisting of a DCT transform matrix and an IDCT transform matrix, and transforming a residual block to generate a DCT coefficient block, wherein the offset is used to select elements of rows and columns of a DCT submatrix of the transform block size from the transform matrix.
H04N 19/122 - Selection of transform size, e.g. 8x8 or 2x4x8 DCTSelection of sub-band transforms of varying structure or type
G06F 17/14 - Fourier, Walsh or analogous domain transformations
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/126 - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 19/156 - Availability of hardware or computational resources, e.g. encoding based on power-saving criteria
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/42 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
H04N 19/51 - Motion estimation or motion compensation
H04N 19/61 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
19.
SYSTEMS AND METHODS FOR MONITORING AN INSTRUCTION BUS
Systems and methods for validating operation of a software sequence may include: monitoring signals on a bus of a processor, comparing the contents of the signals on the bus to pre-stored information from compile time. If the comparing generates a match, that may indicate that the software sequence is operating as intended. However, if the comparing generates a mismatch, that may indicate that the software sequence is not operating as intended and may, in fact, indicate a malicious use. Further actions can be taken in response to a mismatch, including resetting a processor, issuing an interrupt, and the like.
G06F 21/52 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure
G06F 21/56 - Computer malware detection or handling, e.g. anti-virus arrangements
20.
COMMUNICATION INTERFACE WITH CALIBRATING DELAY CIRCUIT
In described examples, a device includes a transmitter, a receiver, and a control circuit. The transmitter transmits a clock signal, and the receiver receives a response signal. The control circuit is coupled to the transmitter and the receiver. The control circuit causes the transmitter to transmit a first clock signal with a first clock period, and to transmit a second clock signal with a second clock period greater than the first clock period. The control circuit determines whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock period. If the patterns are the same, the control circuit delays the clock signal with a delay responsive to the first clock period to generate a delayed clock signal. The receiver samples response signals using the delayed clock signal during normal operation of the device.
H04L 7/00 - Arrangements for synchronising receiver with transmitter
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
21.
BARRIER STRUCTURE WITHIN A MICROELECTRONIC ENCLOSURE
An example method includes applying a dielectric material on at least a first portion of a first substrate; depositing a seed metal on the dielectric material and on at least a second portion of the first substrate; depositing a plating photoresist on at least a portion of the seed metal; electroplating a metal line on the seed metal within boundaries formed by the plating photoresist; stripping at least a portion of the plating photoresist, and etching at least a portion of the seed metal; and positioning a second substrate relative to a barrier structure formed in part by the metal line to form a cavity.
A method includes obtaining a substrate layer. The method also includes forming metallic traces on the substrate layer, where the metallic traces include functional metallic traces, first dummy metallic traces, and second dummy metallic traces, where the first dummy metallic traces have a first density, the second dummy metallic traces have a second density, and the second density is different than the first density.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
An electronic device includes first and second electronic components having lateral sides, a first side attached to a substrate, and an opposite second side, a thermally conductive band having a bottom extending on the second sides of the first and second electronic components, a top, and sidewalls, the top, the bottom, and the sidewalls of the thermally conductive band defining an interior, and a package structure extending on the top side of the substrate, on the sidewalls and bottom of the thermally conductive band, and on the first side and the lateral sides of the respective first and second electronic components, and the package structure exposing a top side of the top of the thermally conductive band.
H01L 23/367 - Cooling facilitated by shape of device
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An apparatus includes: a driver circuit having a driver output, the driver circuit including a pulse width modulation (PWM) circuit configured to provide a PWM signal at the driver output at a frequency; a sensing circuit having a sense input and a sense output; and a processing circuit having a processing input and a processing output, the processing input coupled to the sense output, the processing circuit including a filter having zeros at the frequency and multiples of the frequency.
In described examples, an integrated circuit (IC) written on a substrate that includes a substrate surface includes a magnetic concentrator, a Hall sensor, a primary coil, and a secondary coil. The Hall sensor at least partially overlaps the magnetic concentrator. The primary coil at least partially overlaps the magnetic concentrator. The secondary coil at least partially overlaps the magnetic concentrator and the primary coil, and surrounds the Hall sensor.
In a described example, a circuit can include a reference controller and a gain adjuster. The reference controller is configured to sample an input voltage from an input stage of the circuit and generate a modulation signal based on a square of the input voltage and an output current of an output stage of the circuit using an error amplifier. The modulation signal is configured to modulate conduction of a switch of a power factor correction (PFC) converter of the circuit to cause an average output current of the output stage of the circuit to follow a reference proportional to the square of the input voltage. The gain adjuster is configured to adjust a gain of the error amplifier based on the input voltage.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
27.
SEMICONDUCTOR PROCESSING INTEGRATION FOR BIPOLAR JUNCTION TRANSISTOR (BJT)
The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, a bipolar junction transistor (BJT), a field effect transistor (FET), and a composite structure. The semiconductor substrate includes a BJT region, a complementary FET (CFET) region, and a transition region between the BJT region and the CFET region. The BJT is on the semiconductor substrate in the BJT region. The FET is on the semiconductor substrate in the CFET region. The composite structure is on the semiconductor substrate in the transition region. The composite structure includes a dielectric material. The dielectric material has a sidewall proximate and facing the CFET region and has a top surface that forms at least a portion of an upper surface of the composite structure.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A circuit includes first and second n-type transistors, and first and second p-type transistors. A first terminal of the second n-type transistor is coupled to a second terminal of the first n-type transistor. Control terminals of the first and second n-type transistors are coupled. A first terminal of the first p-type transistor is coupled to a first terminal of the first n-type transistor. A first terminal of the second p-type transistor is coupled to a second terminal of the first p-type transistor. A second terminal of the second p-type transistor is coupled to a second terminal of the second n-type transistor. Control terminals of the first and second p-type transistors are coupled. A control circuit has a first output coupled to the control terminals of the first and second n-type transistors, and a second output coupled to the control terminals of the first and second p-type transistors.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
The present disclosure generally relates to semiconductor processing integration for a bipolar junction transistor (BJT). In an example, a semiconductor device includes a semiconductor substrate, an etch stop layer, a pedestal dielectric layer, a BJT, and a field effect transistor (FET). The semiconductor substrate includes a BJT region and a complementary FET (CFET) region. The etch stop layer is over the semiconductor substrate in the BJT region. The pedestal dielectric layer is over the etch stop layer in the BJT region. The BJT is on the semiconductor substrate in the BJT region. At least a first portion of the BJT is in an opening through the pedestal dielectric layer and the etch stop layer. At least a second portion of the BJT is further over the pedestal dielectric layer. The FET is on the semiconductor substrate in the CFET region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
An electronic device includes a first die having a first side, a resonator along the first side, and a sidewall extending outward from the first side, the sidewall laterally spaced apart from and encircling the resonator and including a distal end spaced apart from the first side, a second die spaced apart from the first die and having a second side facing the first die, the second side engaging the distal end of the sidewall to seal a cavity defined by portions of the first and second sides and the sidewall, a trench in one of the second side and the distal end of the sidewall, and a die attach material in the trench and adhering the second side to the distal end of the sidewall to prevent outgassing of the die attach material in the cavity.
In an embodiment, an integrated circuit is provided that includes first, second, third, and fourth terminals, a power converter that includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and a controller configured to control the power converter. The first terminal is configured to be coupled to a battery. The first transistor is coupled to the first terminal, the second transistor, the third transistor, and the fourth transistor. The third transistor is coupled to the second terminal. The fourth transistor is coupled to the third terminal. The controller is coupled to the fourth and first terminals.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
A described example includes a circuit. The circuit can include a current sense circuit having a sense input and a sense output, in which the sense input is coupled to an input terminal. A comparator has a first comparator input, a second comparator input, and a comparator output, in which the first comparator input is coupled to the sense output, the second comparator input is coupled to a threshold terminal, and the comparator output is coupled to a fuse terminal. A current programming circuit has a current input and a current output, in which the current input is coupled to the sense output. A first circuit is coupled between the sense output and a ground terminal. A second circuit is coupled between the current output and the ground terminal.
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H02H 1/00 - Details of emergency protective circuit arrangements
H02H 3/36 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to difference between voltages or between currentsEmergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to phase angle between voltages or between currents involving comparison of the voltage or current values at corresponding points of different systems, e.g. of parallel feeder systems
An apparatus includes a first transistor having a control input. The apparatus also includes a driver having an output coupled to the control input. The driver includes an adaptive slew rate control circuit (210) having an input coupled to a first terminal. The adaptive slew rate control circuit (210) is configured to control the slew rate of the first transistor based on a resistor (Rextl) coupled to the first terminal.
In some examples, a circuit includes a first transistor (312), a second transistor (314), a first resistor (318), and a digital logic circuit (106). The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal (TXD) of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal (RXD) of the circuit.
An electronic device (100) includes first and second electronic components (110, 112) having lateral sides, a first side attached to a substrate (107), and an opposite second side, a thermally conductive band (120) having a bottom (121) extending on the second sides of the first and second electronic components (110, 112), a top (122), and sidewalls (123, 124), the top (122), the bottom (121), and the sidewalls (123, 124) of the thermally conductive band (120) defining an interior, and a package structure (108) extending on the top side of the substrate (107), on the sidewalls (123, 124) and bottom (121) of the thermally conductive band (120), and on the first side and the lateral sides of the respective first and second electronic components (110, 112), and the package structure (108) exposing a top side of the top (122) of the thermally conductive band (120).
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/433 - Auxiliary members characterised by their shape, e.g. pistons
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
In examples, a semiconductor package (104) comprises a substrate (109); a second semiconductor package (106) coupled to the substrate, the second semiconductor package comprising a semiconductor die including first metal contacts coupled to second metal contacts (110) of the second semiconductor package; a magnetic mold compound (122) covering the substrate and the second semiconductor package, the magnetic mold compound contacting the second metal contacts; and an inductor coil (116A, 116B) having first and second terminals (118) coupled to the substrate, the second semiconductor package in between the first and second terminals of the inductor coil.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
37.
MICROELECTRONIC DEVICE PACKAGE WITH HYBRID ISOLATION LAMINATE
An example microelectronic device package includes: a substrate (422), including core trace level conductor layers (446, 450) on opposite sides of a planar dielectric core, and prepreg layers of resin impregnated glass cloth over the trace level conductor layers on the opposite sides of the planar dielectric core. A layer of resin thermoset film (424) is formed over one of the prepreg layers, the layer of resin thermoset film cured to form a solid dielectric film layer. Film layer conductive vias (429) extend through the solid dielectric film layer (424). A surface level conductor layer (428) is formed over the solid dielectric film layer on a surface of the solid dielectric film layer. A first semiconductor die (402) and a second die (403) are flip chip mounted on the surface of the solid dielectric film layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
An example apparatus includes; first current source circuitry (270) having a terminal; a first transistor (275) having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry (200); second current source circuitry (250) having a terminal; a second transistor (260) having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor (296) having a first terminal and a second terminal; a capacitor (292) having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier (265) having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.
H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
H03K 5/156 - Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
39.
DYNAMIC RFI SUPPRESSION FOR COMMUNICATION PROTOCOLS
In an embodiment, a method includes: determining a bin corresponding to a radio frequency interference (RFI) spur in a signal, the bin based on a first sampling frequency of a timing loop in a receiver; determining a shift of the first sampling frequency to a second sampling frequency; updating the bin based on the shift; setting a filter coefficient of a notch filter based on the updated bin; suppressing the RFI spur using the notch filter, and establishing link-up between the receiver and another device after suppressing the RFI spur.
In an embodiment, an apparatus includes: a transmitting data path configured to transmit an outgoing data packet; and a receiving data path configured to receive an incoming data packet; a controller configured to determine timing information of the incoming data packet; and dithering circuitry configured to dither a reference signal according to the timing information to vary a frequency of the signal over time to generate a dithered recovered signal.
H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
H04L 47/283 - Flow controlCongestion control in relation to timing considerations in response to processing delays, e.g. caused by jitter or round trip time [RTT]
Techniques for context-adaptive binary arithmetic coding (CABAC) coding with a reduced number of context coded and/or bypass coded bins are provided. Rather than using only truncated unary binarization for the syntax element representing the delta quantization parameter and context coding all of the resulting bins as in the prior art, a different binarization is used and only part of the resulting bins are context coded, thus reducing the worst case number of context coded bins for this syntax element. Further, binarization techniques for the syntax element representing the remaining actual value of a transform coefficient are provided that restrict the maximum codeword length of this syntax element to 32 bits or less, thus reducing the number of bypass coded bins for this syntax element over the prior art.
H04N 19/184 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being bits, e.g. of the compressed video stream
H04N 19/60 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
42.
METHODS AND APPARATUS TO IMPROVE PERFORMANCE OF VOLTAGE TO DELAY CONVERTERS
An example apparatus includes programmable circuitry configured to: provide a sample signal, a time amplification (TA) signal, and a kick signal to sample and conversion circuitry; sample a differential signal for a first amount of time-based on the sample signal; charge a first capacitor for a second amount of time-based on the first kick signal; after the first amount of time and the second amount of time, charge a second capacitor, the charging based on the first TA signal, the charging to cause a falling edge in a first delay signal; and generating, a rising edge in the delay signal based on the falling edge of the O_RST signal.
In an example, a method includes obtaining, in a probing Wi-Fi device a transmit opportunity (TXOP) on a Wi-Fi channel. The method also includes transmitting a probe packet from the probing Wi-Fi device to a receiving Wi-Fi device during the TXOP with a first antenna. The method includes receiving first feedback responsive to transmitting the probe packet with the first antenna. The method also includes transmitting the probe packet from the probing Wi-Fi device to the receiving Wi-Fi device during the TXOP with a second antenna. The method includes receiving second feedback responsive to transmitting the probe packet with the second antenna. The method also includes setting, by the probing Wi-Fi device, a transmission parameters set and a selected antenna based at least in part on the first feedback or the second feedback.
A method for encoding a video sequence is provided that includes signaling in the compressed bit stream that a subset of a plurality of partitioning modes is used for inter-prediction of a portion of the video sequence, using only the subset of partitioning modes for prediction of the portion of the video sequence, and entropy encoding partitioning mode syntax elements corresponding to the portion of the video sequence, wherein at least one partitioning mode syntax element is binarized according to a pre-determined binarization corresponding to the subset of partitioning modes, wherein the pre-determined binarization differs from a pre-determined binarization for the least one partitioning mode syntax element that would be used if the plurality of partitioning modes is used for inter-prediction.
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/119 - Adaptive subdivision aspects e.g. subdivision of a picture into rectangular or non-rectangular coding blocks
H04N 19/13 - Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
H04N 19/147 - Data rate or code amount at the encoder output according to rate distortion criteria
H04N 19/15 - Data rate or code amount at the encoder output by monitoring actual compressed data size at the memory before deciding storage at the transmission buffer
H04N 19/174 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a slice, e.g. a line of blocks or a group of blocks
H04N 19/50 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
An example apparatus includes: current measurement circuitry having an output, log amplifier circuitry having an input coupled to the output of current measurement circuitry and having an output, analog to digital conversion (ADC) circuitry having an input coupled to the output of the log amplifier circuitry and an output, and programmable circuitry having an input coupled to the output of the ADC circuitry and having an output, wherein the programmable circuitry is configured to detect an arc within an Alternating Current (AC) signal provided to the current measurement circuitry.
H02H 3/16 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to fault current to earth, frame or mass
A system and method of demagnetizing a mold machine for forming a magnetic mold compound of electronic devices is provided. The method includes performing a molding process with a mold machine to form a magnetic mold compound on electronic devices and detecting magnetic fields in a mold chase of the mold machine via a gaussmeter. The molding process of the mold machine is ceased responsive to determining that a strength of at least one detected magnetic field exceeds a threshold and the mold chase is demagnetized via a demagnetizer.
H01F 13/00 - Apparatus or processes for magnetising or demagnetising
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A packaged integrated circuit (IC) including a semiconductor die having a metallization layer, the metallization layer including first metal interconnects in a first insulation material. The IC includes a first substrate on the metallization layer, the first substrate including second metal interconnects in a second insulation material different from the first insulation material, at least one of the second metal interconnects being electrically coupled to at least one of the first metal interconnects. The IC further includes a second substrate on the first substrate, the second substrate including an isolation circuit and third metal interconnects in a third insulation material different from the first insulation material, the isolation circuit being electrically coupled to the at least one of the first metal interconnects via the at least one of the second metal interconnects and at least one of the third metal interconnects.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
48.
BUS CAPACITANCE REDUCTION FOR CONTROLLER AREA NETWORK TRANSCEIVER
In some examples, a circuit includes a first transistor, a second transistor, a first resistor, and a digital logic circuit. The first transistor has a control terminal and first and second terminals. The second transistor has a control terminal and first and second terminals, the first terminal of the second transistor coupled to the second terminal of the first transistor. The first resistor has first and second terminals, the first terminal of the first resistor coupled to the control terminal of the second transistor, and the second terminal of the first resistor coupled to the first terminal of the second transistor. The digital logic circuit has an output terminal and first and second input terminals, the output terminal of the digital logic circuit coupled to the control terminal of the second transistor, the first input terminal of the digital logic circuit coupled to a data transmit input terminal of the circuit, and the second input terminal of the digital logic circuit coupled to a data receive output terminal of the circuit.
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A method for forming an integrated circuit (IC) is provided. In one example, the method includes applying a stencil to an interconnect. The stencil includes a number of openings corresponding to interconnect locations. The method also includes applying an adhesive to the interconnect through the number of openings to form an adhesive layer at an interconnect location of the interconnect locations. The method further includes performing a first cure of the adhesive layer. The method yet further includes attaching a die to the interconnect at the at least one interconnect location. The adhesive layer electrically insulates the die from the interconnect. The method includes performing a second cure of the adhesive layer.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
In an example, a method includes providing a signal to a driver for a switching voltage regulator to turn off a high-side field effect transistor (FET) of the switching voltage regulator. The method also includes reducing a voltage at a source of the high-side FET. The method includes responsive to the signal, turning off a pull-down FET coupled to a gate of the high-side FET. The method also includes commutating current from the high-side FET to a low-side FET.
In a described example, a semiconductor device package includes: a semiconductor die mounted to a device side surface of a device unit of a package substrate, the device unit having leads extending from a die mount area; electrical connections between bond pads on the semiconductor die and the leads of the device unit; and mold compound covering the semiconductor die, the electrical connections, and portions of the leads, the mold compound forming the body of a semiconductor device package for the semiconductor die having a board side surface, and opposing top side surface, and sides between the board side surface and the top side surface; wherein the leads extend outwards on two opposite sides from the body of the semiconductor device package formed by the mold compound and the leads have a board side surface that is coplanar with the board side surface of the mold compound.
An apparatus includes a first transistor having a control input. The apparatus also includes a driver having an output coupled to the control input. The driver includes an adaptive slew rate control circuit having an input coupled to a first terminal. The adaptive slew rate control circuit is configured to control the slew rate of the first transistor based on a resistor coupled to the first terminal.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
An example method includes providing a substrate that includes a first substrate surface and a die on the first substrate surface, in which the die includes active circuitry within an area at or near an exposed die surface of the die that is spaced from the first substrate surface. The method also includes placing a stencil mask over the first substrate surface, in which the stencil mask includes a stencil opening over at least a portion of the area of the die that includes the active circuitry. The method also includes urging a viscous insulating material through the stencil opening to cover at least the portion of the area of the die that includes the active circuitry.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
54.
MICROELECTRONIC DEVICE PACKAGE WITH HYBRID ISOLATION LAMINATE
An example microelectronic device package includes: a substrate, including core trace level conductor layers on opposite sides of a planar dielectric core, and prepreg layers of resin impregnated glass cloth over the trace level conductor layers on the opposite sides of the planar dielectric core. A layer of resin thermoset film is formed over one of the prepreg layers, the layer of resin thermoset film cured to form a solid dielectric film layer. Film layer conductive vias extend through the solid dielectric film layer. A surface level conductor layer is formed over the solid dielectric film layer on a surface of the solid dielectric film layer. A first semiconductor die and a second die are mounted on the surface of the solid dielectric film layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A substrate with an array of interconnects for IC (integrated circuit) includes die pads for receiving dies. The array of interconnects also includes leads arranged to circumscribe the die pads. A subset of the leads of that are proximal to a periphery of the substrate are opposed by dummy leads.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
In examples, a semiconductor package comprises a substrate; a second semiconductor package coupled to the substrate, the second semiconductor package comprising a semiconductor die including first metal contacts coupled to second metal contacts of the second semiconductor package; a magnetic mold compound covering the substrate and the second semiconductor package, the magnetic mold compound contacting the second metal contacts; and an inductor coil having first and second terminals coupled to the substrate, the second semiconductor package in between the first and second terminals of the inductor coil.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
57.
METHODS AND APPARATUS TO DRIVE INDUCTOR-CAPACITOR (LC) CIRCUITRY WITH SUBHARMONIC INJECTION
An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
In an embodiment, a system includes control circuitry to enable different clock signals. The control circuitry is configured to enable a first clock signal to drive a device-under-test coupled to a power supply. The first clock signal includes a first portion that includes a first set of clock cycles, a second portion that includes a second set of clock cycles, a third portion that includes a third set of clock cycles, a first idle portion between the first portion and the second portion, and a second idle portion between the second portion and the third portion. The control circuitry is further configured to, during the first and second idle portions, enable a second clock signal supplied to a different device coupled to the power supply.
In one example, a method of forming an electronic device includes receiving a semiconductor substrate having a dielectric layer located over an emitter region of a partially formed bipolar junction transistor. A sacrificial layer is formed over the dielectric layer. A resist layer is formed over the sacrificial layer. A first pattern is formed in the resist layer including a resist layer sidewall over the emitter region. A second pattern is formed in the sacrificial layer. The second pattern includes a sacrificial layer sidewall aligned with the resist layer sidewall. The second pattern is transferred to the dielectric layer.
A semiconductor device, comprising, a semiconductor substrate, a III-N semiconductor layer over the semiconductor substrate, a dielectric layer along the III-N semiconductor layer, first and second trenches through the dielectric layer and the at least one III-N semiconductor layer, and a fill material filling at least a portion of each of the first and second trenches and having an upper surface aligned with an upper surface of the dielectric layer.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
61.
LAYOUT AND MODELING FOR LDMOS WITH BIASED FIELD PLATE
A method of fabricating a semiconductor device includes creating a device model of a drain extended transistor with a biased field plate, simulating performance of the drain extended transistor using the device model, adjusting the device model based on the simulation to create an adjusted device model to improve a figure of merit, and creating a circuit model of the drain extended transistor based on the adjusted device model. A semiconductor device includes a drain extended transistor having a field relief dielectric layer over a drain drift region, and a biased field plate over the field relief dielectric layer where a position and bias voltage of the field plate are determined by adjusting a device model of the drain extended transistor based on simulated performance of the drain extended transistor using the device model.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Light projectors, examples of which may be used in headlight assemblies and/or other display applications. In one example, a system includes a phase light modulator, a phosphor device optically coupled to the phase light modulator, and a spatial light modulator optically coupled the phosphor device.
F21S 41/64 - Illuminating devices specially adapted for vehicle exteriors, e.g. headlamps characterised by a variable light distribution by acting on refractors, filters or transparent cover plates by changing their light transmissivity, e.g. by liquid crystal or electrochromic devices
63.
SEMICONDUCTOR DEVICE PACKAGE WITH STUB LEADS AND METHODS
In a described example, a semiconductor device package (400) includes: a semiconductor die (405) mounted to a device side surface of a device unit of a package substrate (430), the device unit having leads (409) extending from a die mount area; electrical connections (419) between bond pads on the semiconductor die and the leads of the device unit; and mold compound (423) covering the semiconductor die (405), the electrical connections, and portions of the leads, the mold compound forming the body of a semiconductor device package (400) for the semiconductor die having a board side surface (426), and opposing top side surface, and sides between the board side surface and the top side surface; wherein the leads extend outwards on two opposite sides from the body of the semiconductor device package formed by the mold compound and the leads have a board side surface that is coplanar with the board side surface of the mold compound.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
An apparatus (200A, FIG. 2A) includes: a driver circuit (280) having a driver output, the driver circuit (280) including a pulse width modulation (PWM) circuit (288) configured to provide a PWM signal at the driver output at a frequency; a sensing circuit (244A) having a sense input (246, 248) and a sense output (258); and a processing circuit (260A) having a processing input (262) and a processing output (266), the processing input coupled to the sense output (246, 248), the processing circuit (260A) including a filter (274) having zeros at the frequency and multiples of the frequency.
An electronic device (100) includes peripheral first leads (111), interior second leads (112), a first package structure (108) extending on top sides of the peripheral first leads (111) and interior second leads (112), and on upper first portions of lateral sides of the interior second leads (112), and a second package structure (109) extending laterally around lower second portions of the lateral sides of the interior second leads (112), the second package structure (109) exposing the bottom side of each of the peripheral first leads (111) and exposing one lateral side of each of the peripheral first leads (111), the second package structure (109) exposing the bottom side of each of the interior second leads (112).
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
In examples, a microelectromechanical device comprises a moveable element (604) configured to contact a portion of a surface (610), and an ionic liquid (612) on the portion of the surface.
A gate driver circuit includes a pull-up circuit, a pull-down circuit, a level shifter circuit, and a drive strength control circuit. The pull-up circuit includes a pull-up output, a first signal input, and a first enable input. The pull-up output is coupled to a gate drive output. The first signal input is coupled to a drive signal input. The pull-down circuit includes a pull-down output, a second signal input, and a second enable input. The pull-down output is coupled to the gate drive output. The second signal input is coupled to the drive signal input. The level shifter circuit includes a shifter output and a drive strength input. The shifter output is coupled to the first enable input and the second enable input. The drive strength control circuit includes a drive strength output coupled to the drive strength input.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H03K 3/012 - Modifications of generator to improve response time or to decrease power consumption
In some examples, an apparatus includes a filter, a voltage-to-current conversion circuit, a first current source, a second current source, a capacitor, a comparator, and a buffer. The filter has a first input voltage (VIN) input and a filter output. The voltage-to-current conversion circuit has a first input, a second VIN input, and a current output, the first input coupled to the filter output. The first current source is coupled between the current output and ground terminal. The second current source is coupled between a power terminal and the current output. The capacitor is coupled between the current output and ground terminal. The comparator has a comparator output, a comparator input, and a reference voltage (Vref) input, the comparator input coupled to the current output. The buffer has a buffer input and a buffer output, the buffer input coupled to the comparator output.
Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 3/017 - Adjustment of width or dutycycle of pulses
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
Methods are provided for inter-prediction candidate index coding independent of the construction of the corresponding inter-prediction candidate list, i.e., a merging candidate list or an advanced motion vector predictor list. A maximum allowed number of inter-prediction candidates for an inter-prediction candidate list is used for encoding the inter-prediction candidate index in an encoded bit stream. The maximum allowed number may be pre-determined or may be selected by the encoder and encoded in the bit stream. A decoder may then decode the index using the maximum allowed number of inter-prediction candidates independent of the construction of the corresponding inter-prediction candidate list.
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/109 - Selection of coding mode or of prediction mode among a plurality of temporal predictive coding modes
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/50 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
H04N 19/625 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding using discrete cosine transform [DCT]
An integrated circuit (IC) package includes an interconnect comprising patches of unoxidized metal that are circumscribed by a region of roughened metal formed of oxidized metal. The IC package also includes a die mounted on the interconnect. The die is conductively coupled to at least a subset of the patches of unoxidized metal.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
72.
SCROLLING LASER ILLUMINATION WITH A PHASE LIGHT MODULATOR
In an example, an apparatus includes a spatial light modulator (SLM) having a first surface; and a phase light modulator (PLM) having a second surface. In operation, the PLM receives a first illumination projection of light beams from multiple light sources, in which the first illumination projection includes first illumination patterns respectively projected on nonoverlapping regions of the second surface; and forms, based on a voltage setting, a hologram that directs the light beams from the second surface to the first surface to provide a second illumination projection of the light beams on the first surface, in which the second illumination projection includes second illumination patterns respectively projected on nonoverlapping regions of the first surface.
G02F 1/29 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the position or the direction of light beams, i.e. deflection
73.
PRE-TAP EQUALIZABLE CONTINUOUS TIME LINEAR EQUALIZER
A circuit includes first, second, third, and fourth transistors, and a capacitor. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, second terminal, and a control terminal. The capacitor has a first conductor coupled to the second terminal of the first transistor, and a second conductor coupled to the second terminal of the second transistor. The third transistor has a first terminal coupled to the first terminal of the second transistor, a second terminal, and a control terminal coupled to the control terminal of the first transistor. The fourth transistor has a first terminal coupled to the first terminal of the first transistor, a second terminal coupled to the second terminal of the third transistor, and a control terminal coupled to the control terminal of the second transistor.
An example apparatus includes quantization feedback circuitry (QFC) including an input terminal coupled to an output terminal of voltage-controlled oscillator (VCO) circuitry and an input terminal coupled to an output terminal of first frequency divider circuitry (FDC). The example apparatus also includes second FDC including an output terminal coupled to an input terminal of phase frequency detector (PFD) circuitry and an input terminal coupled to an output terminal of the first FDC. Also, the example apparatus includes masking logic circuitry including an output terminal coupled to an input terminal of the QFC, an input terminal coupled to the output terminal of the VCO circuitry, and an input terminal coupled to the output terminal of the second FDC. The example apparatus also includes adder circuitry including an input terminal coupled to an output terminal of the PFD circuitry and an input terminal coupled to an output terminal of the QFC.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
H03L 7/087 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
H03L 7/18 - Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
75.
Control System for LLC Voltage Converter Using Up-Down Counter Configured to React to Comparator Output
An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and/or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.
An inductor-inductor-capacitor (LLC) converter (100) may include a pulse width modulation (PWM) controller (170) that holds a duty cycle of control signals (CTLA, CTLB) at a desired ratio, such as 50%. The control system may include a counter (241) that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch (221). An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits (230) to add delay and/or inversion to generate multiple control signals from the output of the latch.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
77.
EXPOSING VALID BYTE LANES AS VECTOR PREDICATES TO CPU
A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.
A converter system includes a first switch and a controller configured to switch the first switch between first and second states based on input and output voltages of the converter system. The controller includes: a timer unit including a first timer configured to determine a first duration based on a target switching frequency of the converter system; and a second timer configured to determine a second duration based on a predetermined duration equal to or greater than a minimum duration of the first state of the first switch and the input and output voltages; and a control logic unit configured to switch the first switch from the second state to the first state responsive to expiration of both the first and second durations.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
79.
SWITCHING FREQUENCY CONTROL FOR INTEGRATED RESONANT HALF-BRIDGE ISOLATED DC/DC WITH BURST MODE OPERATION
A system includes a control circuit having a voltage input and a control circuit output. The control circuit produces a control voltage at the control circuit output having a magnitude inversely related to a magnitude of an input voltage at the input voltage input. A VCO has a VCO control input and a VCO clock output. The VCO control input is coupled to the control circuit output. The VCO produces a VCO clock on the VCO clock output having a frequency that is a function of the control voltage. A protection circuit has a first clock input, a second clock input, and a protection circuit output. The second clock input is coupled to the VCO clock output. The protection circuit generates a protection circuit output signal at the protection circuit output based on a difference in frequency between a clock signal at the first clock input and the VCO clock.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
In described examples, a device includes a processor and a non-transitory memory storing instructions that, when executed, cause the processor to operate in an open loop mode a motor that includes a rotor and a stator. An angle error of the rotor is determined. In response to the angle error of the rotor being less than a threshold, the processor transitions from operating the motor in the open loop mode to operating the motor in a closed loop mode by changing from using a first coordinate system based on a command rotor position to using a second coordinate system based on an estimated rotor position to determine current vectors used to control the motor; and holding constant a current vector used to control the motor while performing the changing action. After performing the changing and holding actions, the processor operates the motor in the closed loop mode.
Systems and methods for MEMS devices are disclosed. A method includes forming an opening in sacrificial material disposed on a hinge and above a substrate of a micromirror assembly to expose at least a portion of a surface of the hinge; depositing, on the exposed portion of the surface and on the sacrificial material, a first layer of material comprised of a titanium aluminum alloy; and depositing a second layer of material over the first layer of material, the second layer of material comprised of aluminum.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
B81B 3/00 - Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
82.
NETWORK SIGNALING FOR NETWORK-ASSISTED INTERFERENCE CANCELLATION AND SUPPRESSION
Embodiments of the invention are directed to a cellular communication network that can determine whether communications between one base station-UE pair may interfere with another UE that is in the same cell or a different cell. The network identifies interference parameters associated with interference signals that may be received by a UE. The interference signals may be generated by the base station itself, such as communications with other UEs, or by a neighboring base station. The base station transmits the interference parameters to the UE. The UE receives the one or more parameters comprising information about signals expected to cause intra-cell or inter-cell interference. The UE then processes received signals using the one or more parameters to suppress the intra-cell or inter-cell interference.
Techniques for signaling of sample adaptive offset (SAO) information that may reduce the coding rate for signaling such information in the compressed bit stream are provided. More specifically, techniques are provided that allow SAO information common to two or more of the color components to be signaled using one or more syntax elements (flags or indicators) representative of the common information. These techniques reduce the need to signal SAO information separately for each color component.
H04N 19/86 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression involving reduction of coding artifacts, e.g. of blockiness
H04N 19/117 - Filters, e.g. for pre-processing or post-processing
H04N 19/186 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component
H04N 19/463 - Embedding additional information in the video signal during the compression process by compressing encoding parameters before transmission
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
H04N 19/80 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation
H04N 19/82 - Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation involving filtering within a prediction loop
H04N 19/91 - Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
An isolation transformer including a ground ring with one or more gaps. The isolation transformer comprises a first coil, a second coil, a dielectric layer between the first coil and the second coil, and a ground ring around the first coil. In examples, the ground ring includes at least one gap in a region between a first winding portion of the first coil and a second winding portion of the first coil.
A semiconductor device includes a semiconductor layer over a semiconductor substrate with adjacent first and second portions, the first portion having a first conductivity type, and the second portion having a second, opposite, conductivity type, and an isolation trench extending through first and second portions and laterally surrounding the first and second portions of the semiconductor layer. A method includes implanting dopants of a first conductivity type in a first portion of a semiconductor layer, implanting dopants of a second, opposite, conductivity type in a second portion of the semiconductor layer that is adjacent to the first portion, and forming an isolation trench that extends through and laterally surrounds the first and second portions to form a junction between the interior portions of the first and second portions within the isolation trench that is approximately planar.
An example apparatus includes a first thin-film transistor (TFT) (308P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first TFT (308P) coupled to the supply terminal and the control terminal of the first TFT (308P) coupled to a first bias voltage, a second TFT (312P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second TFT (312P) coupled to the first current terminal of the first TFT (308P), the control terminal of the second TFT (312P) coupled to a second bias voltage, and the first current terminal of the second TFT (312P) coupled to the first output terminal (344), and a first capacitor (309P) coupled between the first input terminal (302) and the control terminal of the first TFT (308P).
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
87.
METHODS AND APPARATUS TO CALIBRATE ELECTROCARDIOGRAM SYSTEMS
An example apparatus includes: an adjustable capacitor having a first terminal coupled to an input terminal, a second terminal coupled to ground, and a control terminal; demodulation circuitry having an input coupled to the first terminal of the adjustable capacitor; calibration circuitry having an input coupled to an output of the demodulation circuitry and an output coupled to the control terminal of the adjustable capacitor; and driver circuitry having an input coupled to the adjustable capacitor and an output coupled to an output terminal.
A clamp circuit comprising a transistor coupled between a first current terminal and a second current terminal, the transistor having a transistor control terminal; and a driver circuit having a driver input and a driver output. The circuit includes a pull-up circuit having a first bias terminal, a pull-up control input and a pull-up output, the first bias terminal coupled to a power terminal, the pull-up control input coupled to the driver output, and the pull-up output coupled to the transistor control terminal. The first further includes a pull-down circuit having a second bias terminal, a first pull-down control input, a second pull-down control input, and a pull-down output, the second bias terminal coupled to the second current terminal, the first pull-down control input coupled to the first current terminal, the second pull-down control input coupled to the driver output, and the pull-down output coupled to the transistor control terminal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
89.
MEASUREMENT CIRCUIT HAVING FREQUENCY DOMAIN ESTIMATION OF DEVICE UNDER TEST (DUT) MODEL PARAMETERS
A circuit for determining device under test (DUT) model parameters is described. The circuit includes a parameter estimator circuit configured to: obtain initial values for DUT model parameters based on sense signal samples; execute a parameter convergence model having a regularization parameter and a cost function that accounts for error residuals; and obtain final values for the DUT model parameters by adjusting the regularization parameter in iterations of the parameter convergence model as a function of cost function improvement until the parameter convergence model converges to within a target tolerance.
G05B 13/04 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric involving the use of models or simulators
G01R 31/367 - Software therefor, e.g. for battery testing using modelling or look-up tables
G01R 31/3842 - Arrangements for monitoring battery or accumulator variables, e.g. SoC combining voltage and current measurements
G01R 31/389 - Measuring internal impedance, internal conductance or related variables
G06F 17/11 - Complex mathematical operations for solving equations
A circuit includes an amplifier, a capacitor, a resistor, a voltage controlled current source (VCCS), and a differentiator circuit. The amplifier has a feedback input, a reference input, and an error output. The capacitor has a first capacitor terminal coupled to the error output, and second capacitor terminal. The resistor has a first resistor terminal coupled to the second capacitor terminal, and a second resistor terminal. The VCCS has a first terminal coupled to the first capacitor terminal, a second terminal coupled to the second resistor terminal, and a VCCS input. The differentiator circuit has an input coupled to the second resistor terminal, and an output coupled to the VCCS input.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A controller area network (CAN) transceiver including a transmitter (200), a receiver (208), a wake-up receiver (210) including an attenuator (410), a gain stage (420), a comparator (450), a pulse filter (460), and wake-up monitor logic (470). The gain stage (420) includes an offset generation circuit (500), a common-gate amplifier (510), and first and second resistors (508H, 508L). The first and second resistors (508H, 508L) are coupled between outputs of the attenuator (410) to develop a common mode voltage (VCM). The offset generation circuit is referenced to the common mode voltage. The pulse filter can include start/stop logic (600), a transistor (602), a third resistor (604) and a first capacitor (612) coupled to one input of a second comparator (620), and a fourth resistor (604) and a second capacitor (616) coupled to another input of the second comparator.
G05F 3/10 - Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
An apparatus comprising a driver circuit having a driver supply terminal, a driver reference terminal, and a driver output. The apparatus further comprises a transistor coupled between a power terminal and the driver supply terminal; and a transistor control circuit coupled between a control terminal of the transistor and at least one of the driver supply terminal or the driver reference terminal.
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
A circuit includes first, second third, and fourth transistors coupled in series, and a control circuit coupled to the first, second, third, and fourth transistors. The control circuit includes a clock generator, a current sense circuit, and a zero current differentiation zone (ZC_DF) circuit. The clock generator is configured to generate first and second clocks. The second clock is in quadrature with the first clock. The current sense circuit is configured to sense a current flowing through the first transistor. The ZC_DF circuit is configured to define a ZC_DF interval starting at an edge of the second clock and ending at turn-on of the fourth transistor. The control circuit is configured to operate the first, second, third, and fourth transistors in a discontinuous conduction mode (DCM), and, in DCM, turn off the first transistor during the ZC_DF interval responsive to the current flowing through the first transistor being negative.
Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to a voltage regulator. An example circuit includes an output terminal; a first transistor including a current terminal and a control terminal coupled to an output terminal; a second transistor including a control terminal and a current terminal coupled to the control terminal of the first transistor; a third transistor including a first current terminal and a second current terminal, the first current terminal of the third transistor coupled to the output terminal; current mirror circuitry including a terminal coupled to the second current terminal of the third transistor; and inverter circuitry including an input terminal and an output terminal, the input terminal coupled to the terminal of the current mirror and the second current terminal of the third transistor, the output terminal coupled to the control terminal of the second transistor.
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
A leadframe strip includes a two-dimensional mechanically interconnected array of leadframe units including a plurality of leadframe unit pairs, the leadframe strip having an overall length and an overall width. The plurality of leadframe unit pairs each include a first leadframe design including a first plurality of tie bars and a plurality of first leads, and a second leadframe design that is different from the first leadframe design including a second plurality of tie bars, and a plurality of second leads. The first plurality of tie bars and the second plurality of tie bars are configured together to provide a plurality of continuous metal support networks that span an entirety of the overall length or the overall width.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
A circuit includes a first transistor having a first terminal and a second terminal. The circuit includes a second transistor having a first terminal and a second terminal. The first terminal of the second transistor is coupled to the first terminal of the first transistor. A third transistor has a first terminal and a second terminal. The second terminal of the third transistor is coupled to the second terminal of the second transistor. A charge pump has an output coupled to the first terminal of the third transistor. A capacitor has a terminal coupled to the first terminal of the first transistor and to the first terminal of the second transistor.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
97.
ILLUMINATION SOURCE HAVING ILLUMINATION DEVICES AND OPTICAL COMBINING ELEMENTS
An apparatus includes a housing having opposing first and second surfaces. A first illumination device produces first light, a second illumination device produces second light, and a third illumination device produces third light. The first, second, and third illumination devices are arranged along the first surface. The first light has a first color, the second light has a second color, and the third light has a third color. The first color is different than the second color and the third color, and the second color is different than the third color. A fourth illumination device produces fourth light, a fifth illumination device produces fifth light, and a sixth illumination device produces sixth light. The fourth, fifth, and sixth illumination devices are arranged along the second surface. The fourth light has the first color, the fifth light has the second color, and the sixth light has the third color.
In a described example, a circuit includes a comparator circuit including an input, a first output, and a second output. An offset control circuit includes a first input, a second input, a first output, and a second output, in which the first input is coupled to the first output of the comparator circuit, the second input is coupled to the second output of the comparator circuit. A first delay circuit is coupled between the first input and the first output of the offset control circuit. A second delay circuit is coupled between the second input and the second output of the offset control circuit. An offset calibration circuit has a first input and a second input, in which the first input is coupled to the first output of the offset control circuit, the second input is coupled to the second output of the offset control circuit.
A circuit includes an amplifier (110), a capacitor (202), a resistor (206), a voltage controlled current source (VCCS) (210), and a differentiator circuit (208). The amplifier (110) has a feedback input, a reference input, and an error output. The capacitor (202) has a first capacitor terminal coupled to the error output, and second capacitor terminal. The resistor (206) has a first resistor terminal coupled to the second capacitor terminal, and a second resistor terminal. The VCCS (210) has a first terminal coupled to the first capacitor terminal, a second terminal coupled to the second resistor terminal, and a VCCS input. The differentiator circuit (208) has an input coupled to the second resistor terminal, and an output coupled to the VCCS input.
H02M 1/15 - Arrangements for reducing ripples from DC input or output using active elements
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
100.
DISAMBIGUATION IN DOPPLER DIVISION MULTIPLE-ACCESS RADAR
For systems, methods, and apparatus to improve disambiguation in Doppler division multiple-access radar, an example device includes a plurality of transmit antennas. The device includes a plurality of transmitters coupled to the plurality of transmit antennas and including respective phase shifters, the respective phase shifters configured to apply respective phase changes between chirps of a frame such that a phase spectrum for the plurality of transmitters is divided into a plurality of bands, at least three of the respective phase changes being non-consecutively distributed along divisions of the phase spectrum. Other examples are described.
