Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: levels of conductive materials; levels of dielectric materials interleaved with the levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending through the levels of conductive materials and the levels of dielectric materials; a first conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the first conductive contact contacting the first conductive level, the first conductive level forming a first control gate associated with the memory cells; and a second conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the second conductive contact contacting a second conductive level, the second conductive level forming a second control gate associated with the memory cells.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
2.
MIGRATE COMMAND ASSOCIATED WITH TAGGED CAPACITY IN A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE COUPLED WITH A NONVOLATILE MEMORY EXPRESS (NVME) MEMORY DEVICE
A system can include a first memory device comprising a plurality of dynamic capacity devices, a second memory device, and a processing device, operatively coupled with the first and second memory devices. The processing device is configured to perform operations including receiving a host command to move first data associated with a first tag to the second memory device, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data; responsive to receiving the host command to move, determining a second memory section of the second memory device, wherein the second memory section is associated with a namespace of the second memory device; and storing the first data in the second memory section associated with the namespace.
A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including receiving, from a host system, a request to perform a computational operation on first file system data, wherein the request comprises an identifier of the first file system data and specifies the computational operation, wherein the first file system data is stored in a first memory section of a plurality of memory sections of a plurality of dynamic capacity devices of a memory device, wherein the first memory section is associated with a first tag; performing the computational operation on the first file system data to obtain second data; determining a second memory section of the plurality of dynamic capacity devices and associating the second memory section with a second tag; and storing the second data in the second memory section associated with the second tag.
Methods, systems, and devices for secondary interface for a memory system are described. A memory system may receive a command via a first interface that comprises a first set of one or more input/output (I/O) pins and that operates according to a first communication protocol comprising a first modulation scheme and a first data rate. The memory system may receive, via a second interface that comprises a second set of one or more I/O pins and that operates according to a second communication protocol comprising a second modulation scheme and a second data rate, a request for information from the memory system based on receiving the command. The memory system may transmit, via the second interface and in accordance with the second communication protocol, the information based on receiving the request.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
An example apparatus includes a command shifter configured to shift a first command responsive to a first clock signal to generate a second command, a first additional path coupled to the first command shifter and configured to generate a third command responsive to the first clock signal, a second additional path coupled to the first command shifter and configured to generate a fourth command responsive to a second clock signal having different phase from the first clock signal, and a first gate circuit coupled to the first and second additional paths and configured to generate a fifth command based on the third command and the fourth command.
A method and system for transferring data from a data capture device to a memory subsystem where the data is temporarily stored in a Host Memory Buffer (HMB) of a host system. The memory subsystem receives an indication from the host system that the HMB has been allocated in the host system. Responsive to the indication, the memory subsystem accesses a data structure in the HMB to determine a starting position of the data to be transferred. The memory subsystem transfers the data to the memory subsystem, and updates the starting position to reflect that the data has been transferred.
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a substrate populated with one or more semiconductor packages and a label support structure that includes an expandable filler material over the substrate.
Systems, methods, and apparatus are provided for memory device bleeder functionality. For example, some memory cells (e.g., dummy memory cells) within an array of memory cells can be configured as bleeder device, which can be selectively activated to discharge a (e.g., local) sense line to which memory cells of the array are coupled to and/or the memory cells.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
G11C 11/4099 - Traitement de cellules facticesGénérateurs de tension de référence
9.
MEMORY WITH COOLING SYSTEMS USING THROUGH-SILICON TRENCHES, AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS
Memory with cooling systems using through-silicon trenches (and associated devices and methods) are disclosed herein. In one embodiment, a high-bandwidth memory (HBM) device includes an interface die, a plurality of memory dies arranged in a stack and disposed over the interface die, and a cooling trench formed, at least in part, in two or more memory dies of the plurality. The cooling trench can extend from a top of the stack to a depth within the stack, and can be configured to receive a coolant for dissipating heat away from the two or more memory dies. In some embodiments, the cooling trench is a first cooling trench, and the HBM device can include a second cooling trench. The second cooling trench can be fluidly coupled to the first cooling trench, such as via a connector channel in a connector die that is positioned between the stack and the interface die.
H01L 23/46 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
Methods, systems, and devices for low-power boot-up for memory systems are described. A memory system may be configured to receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, wherein the first communication interface includes a plurality of conductive paths; receive, over a second conductive path of the second communication interface, a second indication whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication; and boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.
A host system can include a memory and a processing device, operatively coupled with the memory. The processing device is configured to perform operations including sending, to a memory device, data to be stored in the memory device, wherein the memory device comprises a plurality of dynamic capacity devices, wherein the plurality of dynamic capacity devices comprises a plurality of memory sections; receiving, from the memory device, a response including tag information, wherein the tag information comprises a set of tags in an order, wherein each tag of the set of tags is associated with a respective memory section of the plurality of memory sections, and wherein the respective memory section stores a respective portion of the data; mapping the tags to logical addresses of the data; and accessing the data by aggregating, in the order of the set of tags, a plurality of device physical address (DPA) ranges, wherein each DPA range of the plurality of DPA ranges is associated with a respective tag of the tags.
One or more syndromes can be preliminarily calculated utilizing at least a portion of a codeword and a portion of parity-check matrix can be calculated. The preliminarily calculated syndromes can be utilized to determine where to route the codeword among multiple decoders tailored to various and/or different goals, such as efficiency characteristics, reliability characteristics, etc. of decoding schemes.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
Methods, systems, and devices for write buffer management for a memory system are described. The described techniques provide for a memory system to receive data associated with multiple applications being executed concurrently and store the data to portions of a write buffer according to whether the data is sequential or non-sequential. For example, the memory system may receive sequential data for a first application between receiving non-sequential data for one or more second applications, and may partition a write buffer such that the sequential data is stored (e.g., sequentially) within a portion the write buffer and the non-sequential data is stored within a different portion of the write buffer. The memory system may flush portions of the write buffer to multiple-level memory cells once a portion is full, thereby storing sequential data to sequential physical addresses within the memory system.
A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including recording an error metric associated with a first tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store data; determining whether the error metric satisfies a threshold criterion of unrecoverable error; responsive to determining that the error metric satisfies the threshold criterion, excluding the first memory section from available memory sections of the plurality of dynamic capacity devices for future memory allocation; responsive to receiving a request for memory allocation in the memory device, determining whether a capacity size of the available memory sections of the plurality of dynamic capacity devices is not smaller than a capacity size specified in the request; and responsive to determining that the capacity size of the available memory sections of the plurality of dynamic capacity devices is not smaller than the capacity size specified in the request, identifying a second memory section of the plurality of dynamic capacity devices and associating a second tag with the second memory section.
Methods, systems, and devices for techniques for non-volatile initialization, such as not-and (NAND) initialization, are described. One or more dies of a memory system may perform an automatically-triggered initialization procedure prior to one or more controllers of the memory system completing a wakeup procedure. For example, the memory system may transition from an idle state to an awake. Accordingly, the one or more dies may perform an initialization procedure in response to a first voltage source, a second voltage source, or both, satisfying respective thresholds, such as by reaching a ready state. After, or in conjunction with, the initialization procedure, the one or more controllers may perform the wakeup procedure in response to the transition of the memory system from the idle state to the awake state, such that the wakeup procedure is performed after a start of, or simultaneously with, the initialization procedure at the one or more dies.
Methods, systems, and devices for predictive transfer NAND data register in multiplane cache read are described. A memory device may obtain, from memory after transferring a first set of data from a first set of latches to a second set of latches, a second set of data, where obtaining the second set of data includes loading the second set of data into the first set of latches. The memory device may initialize a counter based on receiving a quantity of commands and may transmit the first set of data from the second set of latches. The memory device may update the counter based on a quantity of the first set of data transmitted subsequent to initializing the counter and may transfer the second set of data from the first set of latches to the second set of latches based on the counter satisfying a threshold.
One or more syndromes can be preliminarily calculated utilizing at least a portion of a codeword and a portion of parity-check matrix can be calculated. These preliminarily calculated syndromes can be utilized for power adjustment associated with decoding the codeword at decoders that calculate syndromes utilizing the parity-check matrix.
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
18.
Memory Circuitry And Method Used In Forming Memory Circuitry
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. The stack comprises lower channel-material strings extending through the first tiers and the second tiers. A sacrificial plug comprises sacrificial material directly above individual of the lower channel-material strings. The sacrificial material is removed from laterally-opposing corner regions of the sacrificial plug in a greater amount diagonally than orthogonally relative to a sidewall of individual of the corner regions and than orthogonally relative to a top of the individual corner regions. Insulator material is formed in void spaces left from the removing. After forming the insulator material, remaining volume of the sacrificial plug is removed. Channel material of upper channel-material strings is formed below and against lower surfaces of the insulator material and that directly couples to channel material of the lower channel-material strings. Other embodiments, including structure, are disclosed.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
19.
INTER-DIE SIGNAL LOAD REDUCTION TECHNIQUE IN MULTI-DIE PACKAGE
Systems, methods, and devices related to techniques for reducing inter-die signal loads within a multi-die package are disclosed. The multi-die package includes a first memory die handling interfacing with a host for the package and at least one second memory die coupled to and configured to communication with the first memory die via an inter-die connection. A technique involves adding an additional wirebond pad to each die in the multi-die package. When the inter-die connections are made, the wirebond pad associated with the first memory die transmitter is connected to the wirebond pad associated with the receiver of a second memory die that is not connected to the transmitter of the second memory die. By not connecting to the transmitter of the second memory die, the first memory die transmits inter-die signals to the second memory die such that a lower signal load is achieved within the multi-die package.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
20.
Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
A memory array comprising strings of memory cells comprises a conductor tier comprising conductor material. Laterally-spaced memory blocks individually comprise a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Conducting material of a lower of the conductive tiers directly electrically coupling together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. The conducting material in the lower conductive tier comprises upper conductively-doped semiconductive material, lower conductively-doped semiconductive material, and intermediate material vertically there-between. The intermediate material is of different composition from those of the upper conductively-doped semiconductive material and the lower conductively-doped semiconductive material and comprises at least one of carbon, nitrogen, oxygen, metal, and n-type doped material also comprising boron. Other embodiments, including method, are disclosed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
21.
LOGICAL-TO-PHYSICAL MAPPING FOR ENHANCED GRANULARITY DATA STORAGE
Methods, systems, and devices for logical-to-physical (L2P) mapping for enhanced granularity data storage are described. A memory system may support write operations according to multiple different write granularities and corresponding data transfer sizes. Entries that map logical addresses to physical addresses within the memory system may include first entries associated with a first data transfer size and second entries associated with a second data transfer size that is greater than the first data transfer size. If the memory system receives a write command that indicates a size of data that is less than or equal to the first data transfer size, the system may update the first entries to indicate a mapping. Data indicated via write commands associated with larger data sizes may be mapped by the second entries. The varying entry structure may support improved write operations and throughput for storage of data at varying granularities.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
Methods, systems, and devices for supporting a cloning mode are described. A memory system may receive a first command associated with a cloning procedure for writing data to a set of memory cells of one or more memory devices, where the first command includes a first indication that indicates a set of addresses associated with the set of memory cells and a second indication that indicates a first write event or a second write event of at least two write events associated with the cloning procedure. The memory system may receive a first set of one or more first write commands to write the data to the set of memory cells, and the memory system may determine whether the first set of one or more first write commands correspond to the first write event or the second write event based on the second indication.
A system includes a memory device and a processing device operatively coupled to the memory device. The processing device is to perform operations including performing a program operation on a block of the memory device. The operations further include retrieving, from a metadata structure associated with a block of the memory device, a value reflecting a type and a corresponding number of erase operations performed on the block of the memory device. The operations further include determining a wear ratio based on the value reflecting the type and the corresponding number of erase operations and the program operation. The operations further include updating, based on the determined wear ratio, a media endurance metric value of the block of the memory device.
Methods, systems, and devices for asynchronous multi-level signal sampling are described. A system may generate a first clock signal by delaying the master clock signal by a first duration that is based on a first propagation delay associated with a first amplifier for a data signal. The system may generate a second clock signal by delaying the master clock signal by a second duration that is based on a second propagation delay associated with a second amplifier for the data signal. The system may sample, by a first sampling circuit based on the first clock signal, a first amplified data signal outputted by the first amplifier. And the system may sample, by a second sampling circuit based on the second clock signal, a second amplified data signal outputted by the second amplifier.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/133 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés utilisant une chaîne de dispositifs actifs de retard
Methods, systems, and devices for plasma-doped trenches for memory are described. A method for forming a memory device with plasma-doped trenches may include forming a stack of materials having alternating layers of polysilicon and oxide materials. A trench may be etched in the stack and doped using a plasma doping process. In some examples, the trench may be doped by applying Boron fluoride, diborane, methane, or Boron and Carbon Hydride gases diluted with Hydrogen (H2) or Helium to the sidewalls and bottom surface of the trench, which may dope portions of the polysilicon material with Boron, Carbon, Fluorine, Helium, or Hydrogen.
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
Methods, systems, and devices for devices and techniques to modify a clock signal are described. A memory system may include a delay adjustment circuit coupled with a clock signal path to compensate for changes in the delay of a clock signal due to fluctuations in a supply voltage. The delay adjustment circuit may include a current mirror, a first compensation component coupled with the clock signal path, and a second compensation component coupled with the clock signal path. The current mirror may be configured to output, based on the supply voltage, a first control signal to the first compensation component and a second control signal to the second compensation component. The compensation components may be configured to modify the clock signal along the clock signal path based on the received control signals.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
27.
MANAGING OPERATIONS PERFORMED USING AN ACCELERATOR IN A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE
A system can include a memory device and a processing device to perform operations including receiving, from a host system, a first command to configure an accelerator associated with the memory device, wherein the first command comprises one or more operations. The operations include identifying, based on metadata associated with the first command, a command type of the first command. The operations further include determining, based on the command type, a first instruction to configure the accelerator to perform the one or more operations comprised by the first command. The operations further include sending, to the accelerator, the first instruction, wherein the one or more operations are to be performed by the accelerator according to the first instruction.
Devices and methods include a first memory chip including first memory banks, a command input configured to receive a command and a chip identifier, and a decoder configured to determine whether the command is to use a clock on the second memory chip when the command matches predetermined conditions. The devices and methods also include a second memory chip including second memory banks and a clock receiver configured to receive the clock from the first memory chip to be used in memory operations on the second memory chip. The first memory chip acts a base chip for a stack of memory chips that includes the first memory chip and the second memory chip. When the command matches the predetermined conditions, the first memory chip is configured to send the chip identifier to the second memory chip to the clock receiver to activate the clock receiver before transmitting the command to the second memory chip.
G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
The disclosed memory architecture eliminates the need for the conventional queue-based work request model by allowing direct computation within memory modules in response to data writes. The system is designed to automatically update computed values, such as hashes, within a designated computational memory region in response to a write to a corresponding data set region, without explicit instructions from the host. The computation happens according to a defined policy, which may include computing a new result immediately after a write to a dataset segment, computing the result if no writes are detected to a dataset segment within a specified period of time, computing the result after a host reads an invalid compute validity bit, or the like.
Methods, systems, and devices for access pattern tracking are described. An access request associated with accessing first data stored in memory may be received. Based on receiving the access request, a hash value based on a page index indicated in the access request may be calculated. Based on the hash value, a counter associated with the hash value may be incremented. Based on incrementing the counter, an access pattern associated with access data in the memory may be indicated.
A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including receiving a host command to freeze first data associated with a first tag, wherein the first tag is associated with a first memory section of a plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data. The operations further include responsive to receiving the host command to freeze, making the first data inaccessible to the first host system; and responsive to determining that the host command indicates to free the first memory section, storing the first data in a second memory device, wherein the second memory device is not included in the plurality of dynamic capacity devices.
Methods, systems, and devices for uncorrectable error detection in memory systems are described. A memory system may perform a syndrome check to compare a first syndrome with a second syndrome, the first syndrome being generated as part of a first error control operation performed on data and the second syndrome being generated as part of a second error control operation performed on the data. Based on performing the syndrome check, the memory system may generate a first flag that indicates whether the first syndrome is equivalent to the second syndrome. The memory system may generate a second flag that indicates whether the second error control operation resulted in one or more bits of the data being modified. Based on the first and second flags, the memory system may generate a third flag that indicates whether an uncorrectable error is detected in the data during the second error control operation.
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
33.
TECHNIQUES AND SYSTEMS FOR EMULATING INCOHERENT MEMORY
In some implementations, an emulation system may store a set of data to a first memory copy location of an emulated environment that is associated with a first virtual host system. The emulation system may copy the set of data from the first memory copy location to a shared memory location of the emulated environment. The emulation system may copy the set of data from the shared memory location to a second memory copy location of the emulated environment that is associated with a second virtual host system. The emulation system may load the set of data from the second memory copy location.
Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
35.
SEMICONDUCTOR ASSEMBLIES WITH REDISTRIBUTION STRUCTURES FOR DIE STACK SIGNAL ROUTING
Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor assembly comprises a die stack including a plurality of semiconductor dies, and a routing substrate mounted on the die stack. The routing substrate includes an upper surface having a redistribution structure. The semiconductor assembly also includes a plurality of electrical connectors coupling the redistribution structure to at least some of the semiconductor dies. The semiconductor assembly further includes a controller die mounted on the routing substrate. The controller die includes an active surface that faces the upper surface of the routing substrate and is electrically coupled to the redistribution structure, such that the routing substrate and the semiconductor dies are electrically coupled to the controller die via the redistribution structure.
Methods, systems, and devices for measuring tilt in semiconductor manufacturing are described. A first set of contacts and a second set of contacts may be formed on the measurement marker. Based on forming the sets of contacts, a stack of nitride and oxide materials may be deposited over the first set of contacts. Subsequently, a set of cavities may be etched through the stack of nitride and oxide materials to the set of contacts, such that a respective cavity may be etched to the set of contacts. The set of cavities may form a hollow-core light pipe that may be used for measurements over a range of optical frequencies. As such, a light may be emitted through the set of cavities, where a measurement may be obtained at the interface between the set of contacts and the set of cavities based on the emitted light.
A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including: determining whether a workload change associated with a segment of the memory device satisfies a first threshold criterion for triggering an offset bin update; responsive to determining that the workload change satisfies the first threshold criterion, performing a calibration measurement of a center of a voltage valley for each state of each cell in the segment of the memory device; repeating the calibration measurement until a result of the calibration measurement is less than or equal to a threshold value; and updating a threshold voltage offset bin associated with the segment of the memory device based on the result of the calibration measurement.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A memory device can include an array of memory cells and an integrated inductor. The array can be provided on a first semiconductor substrate. First conductive portions of the inductor can be provided on the first semiconductor substrate, and each of the first conductive portions provides less than one revolution of a conductive path of the inductor. Second conductive portions of the inductor can be vertically separate from the first conductive portions and coupled to the first conductive portions to provide multiple revolutions of the conductive path of the inductor. The second conductive portions of the inductor can be provided on a different second semiconductor substrate. The inductor can optionally include a core region that is filled with a magnetic or non-magnetic material.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
39.
DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES
Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
40.
CONCATENATE COMMAND AND TRUNCATE COMMAND ASSOCIATED WITH TAGGED CAPACITY FOR A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE
A system can include a memory device comprising a plurality of dynamic capacity devices; and a processing device, operatively coupled with the memory device, to perform operations including: receiving a host command to combine first data associated with a first tag and second data associated with a second tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, wherein the second tag is associated with a second memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the first data and the second memory section is allocated to the first host system to store the second data; responsive to receiving the host command to combine, determining a third memory section of the plurality of dynamic capacity devices and associating a third tag with the third memory section; combining the first data and the second data into a combined data; and storing the combined data in the third memory section.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device, which includes: a first region including first levels of conductive materials interleaved with first levels of dielectric materials, and first memory cells including pillars extending through at least a portion of the first levels of conductive materials and first levels of dielectric materials; a second region including second levels of conductive materials interleaved with second levels of dielectric materials, and second memory cells including pillars extending through at least a portion of the first levels of conductive materials and first levels of dielectric materials; a third region including a dielectric structure separating the first levels of conductive materials from the second levels of conductive materials; and a conductive contact extending through at least a portion of the third region and contacting a conductive material of the first levels of conductive materials.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
42.
TECHNIQUES FOR TRANSMITTING LOGICAL-TO-PHYSICAL ADDRESS MAPPING TO A HOST SYSTEM
Methods, systems, and devices for transmitting logical-to-physical (L2P) address mapping to a host system are described. A memory system may be configured to determine portions of an L2P mapping that are sequential, and transfer indications of respective starting addresses and a respective size of such sequential mappings. For example, a memory system may be configured to transmit an indication of a starting logical address, a corresponding starting physical address (e.g., a physical address mapped to the starting logical address), and a size of a sequential mapping from the starting logical and physical addresses. In some such examples, search techniques may be adapted at the memory system, at the host system, or both to facilitate address searching with the revised L2P mapping structure (e.g., to leverage indications of starting addresses and lengths of sequential portions), such as implementing aspects of a search tree or hash table.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
43.
LATENCY REDUCTION OF BOOT PROCEDURES FOR MEMORY SYSTEMS
Methods, systems, and devices for latency reduction of boot procedures for memory systems are described. A memory system may receive a first command to perform a first reset of one or more components as part of a first phase of a boot procedure of a host system. The memory system may initiate an initialization process of a second phase of the boot procedure upon determining whether the value of a flag has been set from a first value to a second value. Upon completing the initialization process, the flag may be set to the first value. Parameters corresponding to the characteristics of the memory system may be communicated to the host system based on receiving a second command. The memory system may perform a configuration operation of a logical-to-physical mapping concurrently with communicating the parameters with the host system.
System-in-package (“SiP”) devices, and associated systems and methods, are disclosed herein. The SiP device can include an interposer, a host device, and a plurality of high-bandwidth memory (“HBM”) cubes. A first set of the HBM cubes can be positioned around a perimeter of the host device and coupled to the host device through the interposer. A second set of the HBM cubes can be positioned peripheral to the first set with respect to the host device. The HBM cubes of the second set can be coupled to the host device through a footprint of one or more the HBM cubes of the first set, such as through communication circuits in base dies of the HBM cubes of the first set and/or communication circuits formed in the interposer and/or positioned beneath the HBM cubes of the first set.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
45.
TECHNIQUES FOR FORMING A VERTICAL MEMORY ARCHITECTURE
Methods, systems, and devices for a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
Methods, systems, and devices for power rail design for a memory system are described. A host system may power a memory system using a first power rail, a second power rail, and a third power rail. The first power rail may be coupled with the memory device and configured to power one or more first components of the memory device at a first voltage level. The second power rail may be coupled with the memory device and configured to power one or more second components of the memory device at a second voltage level. The third power rail may be coupled with the memory system controller and configured to power one or more third components of the memory system controller at a third voltage level.
A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including receiving a host command to copy data associated with a first tag, wherein the first tag is associated with a first memory section of the plurality of dynamic capacity devices, and wherein the first memory section is allocated to a first host system to store the data; responsive to receiving the host command to copy. The operations further include determining a second memory section of the plurality of dynamic capacity devices, associating a second tag with the second memory section and storing the copied data associated with the first tag in the second memory section associated with the second tag.
Methods, systems, and devices for verification of a volatile memory, such as a dynamic random-access memory (DRAM), using a unique identifier (ID) are described. A memory device may store a unique ID for a DRAM component of the memory device in non-volatile memory (e.g., in the DRAM, external to the DRAM). A host device coupled with the memory device may store, to non-volatile memory at the host device, information for verifying the identity of the DRAM component, for example, based on the unique ID. The memory device and host device may perform a procedure for verification of the identity of the DRAM component using the unique ID of the DRAM and the verification information stored at the host device. If the host device detects that the DRAM has been replaced or modified based on the verification procedure, the host device may disable one or more features of the memory device.
Techniques are provided for mitigating (e.g., reducing or eliminating) the column spiking issue caused by an electrical coupling due to voltage changes on a SAN signal. The column spiking is mitigated by reducing dimensions of the contact pad (e.g., Metal0 pad) of the SAN signal. Additionally or alternatively, the column spiking is mitigated by using a voltage source (e.g., via the Metal0 layers) that provides voltage changes countering the voltage changes of the SAN signal to mitigate the total electrical coupling. By mitigating the column spiking, the memory device has improved performance, such as improved sense margin consistency, reduced peak offset and reduced variation of offset in sense amplifiers, and the like. In addition, the current technology and methods improves signal margin in the SAs as well as array efficiency (AE) in the memory devices.
Methods, systems, and devices for improved data flush for force unit access (FUA) commands are described. The described techniques provide for a memory system to determine whether to consolidate commands and flush data in accordance with the commands. In some examples, the memory system may evaluate whether a quantity of FUA write commands satisfies a threshold. If the quantity of FUA write commands satisfies the threshold, the memory system may write and flush data associated with the quantity of FUA write commands to a plurality of dies of a memory array of the memory system in accordance with a sequential write mode, a jump write mode, or both. If the quantity of FUA write commands does not satisfy the threshold, the memory system may evaluate other quantities of commands to determine whether to flush the data. The memory system may conditionally flush the data to execute the commands more efficiently.
Methods, systems, and devices for a bonding structure and related fabrication for a memory system are described. The method may include forming a first layer that includes a polysilicon material, forming, above the first layer, a second layer that includes an oxide material, and forming, above the second layer, a third layer that include the polysilicon material. Additionally, the method may include removing a first portion of the first layer, a first portion of the second layer, and a third portion of the third layer to form a first cavity. Additionally, the method may include forming the oxide material in the first cavity, forming a plurality of second cavities based on removing some of the oxide material formed in the first cavity, and forming a set of first pillars based on forming a metal material in two or more cavities of the set of second cavities.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
Methods, systems, and devices for lateral word line contacts for memory devices are described. A memory architecture may include a stack of materials including layers of word lines. The memory architecture may include array regions including memory cells coupled with the word lines. The memory architecture may include contact regions including word line contact pillars extending through the stack of materials, each coupled with a respective word line at a respective target layer of the stack of materials. The contact regions may include subsets of guard pillars extending through the stack of materials, each subset associated with isolating the respective word line contact pillar from word lines at other layers of the stack of materials different from the target layer. The memory architecture may include a staircase region and electrically isolating pillars at least partially surrounding the staircase region.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
53.
DECISION FEEDBACK EQUALIZER WITH VARIABLE GAIN AMPLIFIER
A device is provided that includes a decision feedback equalizer (DFE) with a first summer circuit and a second summer circuit. The DFE also includes a first double tail latch circuit coupled to the first summer circuit and a feedback path disposed between latches of the first double tail latch circuit and coupled to the second summer circuit to provide a tap signal to the second summer circuit. The DFE further includes another double tail latch circuit coupled to the second summer circuit and a feedback path disposed between latches of the second double tail latch circuit and coupled to the first summer circuit to provide a tap signal to the first summer circuit.
An example apparatus includes an even global command path configured to drive a first even internal command responsive to a first clock signal, an odd global command path configured to drive a first odd internal command responsive to a second clock signal, and a clock control circuit configured to control whether the first clock signal is provided to at least a portion of the even global command path or not based on a first detection signal activated when the second even internal command keeps an active state during a predetermined period of time and control whether the second clock signal is provided to at least a portion of the odd global command path or not based on the second detection signal activated when the second odd internal command keeps an active state during a predetermined period of time.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
55.
SYSTEMS AND METHODS FOR REDUCING GAPS AROUND SURFACE MOUNT DEVICES IN STACKED SEMICONDUCTOR DEVICES
Systems and methods for manufacturing semiconductor packages are disclosed herein. In some embodiments, the method includes integrating one or more capacitors and a stack of one or more semiconductor dies with an upper surface of a base substrate of the semiconductor package. The method also includes encasing each of the one or more capacitors with a first encapsulant, then depositing a second encapsulant over each of the one or more capacitors and the die stack. The first encapsulant can have a first individual particle size that is smaller than a second individual particle size of the second encapsulant. The relatively small particle size allows the first encapsulant to completely fill spaces between the capacitors and the base substrate and/or fully adhere to the surfaces of the capacitors. As a result, the first encapsulant can reduce voids in the completed semiconductor package that can cause deleterious effects.
Methods, systems, and devices for host-controlled block maintenance operations are described. A host system may receive the block status information from a memory system in response to transmitting a request for the block status information. The block status information may include an indication of a first quantity of blocks available for writing and an indication of a second quantity of blocks written with at least a threshold amount of valid data. In accordance with the block status information and a target performance metric, the host system may transmit an indication for the memory system to perform, during an idle time, a block maintenance operation in which data stored at the second quantity of blocks is copied to a subset of the first quantity of blocks and in which the second quantity of blocks are erased after the data stored at the second quantity of blocks is copied.
In some implementations, a memory system may receive multiple memory requests associated with a memory, wherein the memory is associated with multiple memory ranks, and wherein each memory request, of the multiple memory requests, includes a memory address indicating a memory rank, of the multiple memory ranks, that is to be accessed for that memory request. The memory system may group the multiple memory requests based on the multiple memory ranks. The memory system may transmit, to a memory controller associated with the memory, a scheduled set of memory requests, wherein the scheduled set of memory requests includes memory requests selected from one or more groups of memory requests associated with one or more scheduled memory ranks of the multiple memory ranks.
Methods, systems, and devices for divider and contact formation for memory cells are described. In some examples, a protective mask (e.g., a photoresist layer) may be formed over existing circuit structures above a substrate. Contact structures may be exposed when the protective mask is removed. In some examples, the protective mask may be removed using a dry etching operation. In some examples, one or more additional etching operations may be performed to expose (and subsequently fabricate) additional circuit structures.
In some implementations, an emulation system may store a set of data to a first memory copy location of an emulated environment that is associated with a first virtual host system. The emulation system may copy the set of data from the first memory copy location to a shared memory location of the emulated environment. The emulation system may copy the set of data from the shared memory location to a second memory copy location of the emulated environment that is associated with a second virtual host system. The emulation system may load the set of data from the second memory copy location.
A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/30 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire
H10B 41/48 - Fabrication simultanée de périphérie et de cellules de mémoire ne comprenant qu’un type de transistor de périphérie avec une couche diélectrique tunnel également utilisée en tant que partie du transistor périphérique
61.
FILE SYSTEM WITH TAGGED CAPACITY FOR MEMORY DEVICE
A system can include a memory device comprising a plurality of dynamic capacity devices and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including sending, to a memory device, an allocation request to allocate, for a file system, a first memory section of a plurality of memory sections of a plurality of dynamic capacity devices associated with the memory device; reserving, for the file system, a first portion of the first memory section for storing file metadata of file system data; reserving, for the file system, a second portion of the first memory section for storing file data of file system data; sending, by a first process running on the host system, to the memory device, the file metadata for storing the file metadata in the first portion of the first memory section; sending, by a second process running on the host system, to the memory device, a second request to modify the file metadata stored in the first portion of the first memory section; and receiving, from the memory device, a second response indicating an error regarding the second request.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: levels of dielectric materials interleaved with levels of conductive materials; a memory cell string including a pillar extending through the levels of conductive materials and the levels of dielectric materials, the levels of conductive materials including a first conductive level forming a first control gate associated with the memory cell string, and a second conductive level forming a second control gate associated with the memory cell string; a first conductive contact contacting the first conductive level; and a second conductive contact separated from the first conductive contact and contacting the second conductive level, at least a portion of the second conductive contact surrounding a portion of the first conductive contact.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
63.
READ OPERATION WITH BOOST MODULATION IN MEMORY DEVICES
An example system includes a memory device and a processing device operatively coupled to the memory device. The processing device is configured to: produce a first data item by performing, using a first boost voltage level, a first read strobe with respect to a set of memory cells storing encoded data item; apply an offset to the first boost voltage level to produce a second boost voltage level; produce a second data item by performing, using the second boost voltage level, a second read strobe with respect to the set of memory cells; and produce, based on the first data item and the second data item, decoded data item corresponding to the encoded data item.
Methods, systems, and devices for uncorrectable error detection in memory systems are described. A memory system may perform a syndrome check to compare a first syndrome with a second syndrome, the first syndrome being generated as part of a first error control operation performed on data and the second syndrome being generated as part of a second error control operation performed on the data. Based on performing the syndrome check, the memory system may generate a first flag that indicates whether the first syndrome is equivalent to the second syndrome. The memory system may generate a second flag that indicates whether the second error control operation resulted in one or more bits of the data being modified. Based on the first and second flags, the memory system may generate a third flag that indicates whether an uncorrectable error is detected in the data during the second error control operation.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes: levels of conductive materials; levels of dielectric materials interleaved with the levels of conductive materials, the levels of conductive materials including a first conductive level and a second conductive level; a memory cell string including a pillar extending through the levels of conductive materials and the levels of dielectric materials; a first conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the first conductive contact contacting the first conductive level, the first conductive level forming a first control gate associated with the memory cells; and a second conductive contact extending through the levels of conductive materials and the levels of dielectric materials, the second conductive contact contacting a second conductive level, the second conductive level forming a second control gate associated with the memory cells.
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
66.
Iterative bit flip decoding utilizing different bit flip states
A codeword is received and stored in a first data structure to be decoded by flipping one or more of a plurality of bits over multiple iterations by a bit flip decoder, an error check is executed on the codeword, by a controller, to identify error bits from the plurality of bits, and the state of an error bit is flipped from one of the identified error bits if parity check (PC) violations associated with the error bit meet or exceed a PC violation threshold associated with a bit flip state of the error bit, where the bit flip state is selected from one of a first bit flip state with a first PC violation threshold and a second bit flip state with a second PC violation threshold different than the first PC violation threshold. The current state of the error bit is stored in a second data structure.
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
67.
Memory sub-system initiated burst scan under low power mode
A wake up cadence at which the memory device is to wake up during a low power mode is determined. Based on the wake up cadence, a processing device determines a finite number of pages of the memory device to be scanned per wake up during the low power mode to satisfy a criterion for memory device qualification, the criterion being associated with the memory device's data retention capability. Upon detecting the low power mode, a burst scan operation is performed to scan the finite number of pages in the memory device each time the memory device wakes up at the determined cadence.
In some implementations, a device may receive, from a host device, a plurality of first data words of a request data object exchange (DOE) data object that encapsulates a request management message of a hardware device management protocol, where each data word of the plurality of first data words corresponds to a portion of the request management message. The device may construct the request management message using the plurality of first data words. The device may transmit a plurality of second data words of a response DOE data object that encapsulates a response management message of the hardware device management protocol, where each data word of the plurality of second data words corresponds to a portion of the response management message.
In some implementations, a memory device may receive a mode register command that configures a parameter in a mode register of the memory device. The memory device may receive a set of command bits that indicates a command, where configuration of the parameter in the mode register frees a switchable parameter bit, of the set of command bits, that otherwise is used to configure the parameter, and where the switchable parameter bit is used as a parity bit relating to remaining bits of the set of command bits. The memory device may perform a parity check using the switchable parameter bit that is used as the parity bit.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
70.
Vertical Ferroelectric Transistor, Ferroelectric Memory Circuitry, And Method Used In Forming A Vertical Ferroelectric Transistor
A vertical ferroelectric transistor comprises an upper source/drain region and a lower source/drain region having a channel region vertically there-between. A gate is laterally aside the channel region. Ferroelectric material is laterally aside and laterally between the gate and the channel region. Insulator material of different composition from that of the ferroelectric material is laterally aside and laterally between the gate and the ferroelectric material. The insulator material comprising (a) and (b) that are laterally aside one another and described herein. Ferroelectric memory and method are also disclosed.
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur
71.
THRESHOLD VOLTAGE COMPENSATION FOR A MEMORY SYSTEM SENSE AMPLIFIER
Methods, systems, and devices for threshold voltage compensation for a memory system sense amplifier are described. A sense amplifier may include a first transistor comprising: a gate terminal coupled with a second digit line, a drain terminal coupled with a first digit line through a first switching component, and a source terminal coupled with a node. The sense amplifier may include a second transistor comprising a source terminal coupled with the node. The sense amplifier may include a first voltage supply configured to be coupled with the node using a third transistor during an amplification phase of a sense operation for the memory cell; and a second voltage supply configured to be coupled with the node through a fourth transistor during a compensation phase of the sense operation.
In some implementations, a memory apparatus including a synchronous graphics random access memory (SGRAM) associated with a first clock signal having a first clock frequency may receive a command to initiate a read clock. The memory apparatus may generate read clock data based on one or more control parameters stored to a mode register and a second clock signal having a second clock frequency that is double the first clock frequency. The memory apparatus may output a read clock signal that is based on the read clock data, the read clock signal having a third clock frequency that is double the second clock frequency, wherein the read clock signal is associated with a memory access command for the SGRAM.
A capacitor for a microelectronic device includes a first electrode and a second electrode. The first electrode includes a first base portion at a first level, a second base portion at a second level, first base contacts extending from the first to the second base portion, first plates extending from the first base portion, second plates extending from the second base portion, and capacitor plate contacts extending from the first plates to the second plates. The second electrode includes a first base portion formed at the first level, a second base portion formed at the second level, second base contacts extending from the first to the second base portion, first plates extending from the first base portion, second plates extending from the second base portion, and capacitor plate contacts extending from the first plates to the second plates. Additional capacitors and related methods are also disclosed.
A microelectronic device includes a first memory array structure including a first array region including first memory cells within a horizontal area of the first array region, each of the first memory cells having a first access device and a first storage node device vertically underlying and coupled to the first access device, a first control circuitry structure vertically overlying and attached to the first memory array structure at a boundary of the first memory array structure vertically closer to the first access devices of the first memory cells than the first storage node devices of the first memory cells, and a first shield structure vertically interposed between the first memory cells of the first memory array structure and the first control circuitry structure.
A microelectronic device includes a stack structure, pillar structures, and insulative slot structures. The stack structure includes blocks horizontally extending in parallel in a first direction and individually having tiers respectively including conductive material and insulative material vertically neighboring the conductive material. The pillar structures vertically extend through the blocks of the stack structure. The pillar structures respectively include a void space horizontally interposed between dielectric material and additional dielectric material. The insulative slot structures horizontally extend in parallel in the first direction. The insulative slot structures respectively horizontally overlap and vertically extend into a group of the pillar structures. Related methods, memory devices, and electronic systems are also described.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
76.
ENHANCED PARITY FORMATION FOR FAULT TOLERANCE IN MEMORY DEVICES
A parity group identifier is calculated for each page of a plurality of pages of a block of a memory device storing host data based on a page number of a respective page and a wordline number derived from the page number. The page number is appended to an array of page numbers assigned to a parity group identified by the parity group identifier. Redundancy metadata is calculated for each parity group of a plurality of parity groups based on the array of page numbers assigned to a respective parity group. The redundancy metadata is stored in a page of the block identified by a last page number of the array of page numbers assigned to the respective parity group.
Methods, systems, and devices for adaptive memory status reporting are described. For example, the memory system may store one or more status indicators to a register for a host system to access. The status indicators may represent an estimated completion time for a quantity of access commands in a command queue of the memory system. The host system may use the status indicators to detect an unresponsive memory system. For example, the host system may query the register to determine whether to continue to wait for the commands to complete or to issue an abort command. Additionally, or alternatively, the host system may initiate memory management operations to assist the memory system in completing executing the commands.
A flip-flop circuit may be used to latch data responsive to an edge of a clock signal. An example flip-flop circuit includes a first latch which latches a value of the data when the clock is at a level, a NAND gate coupled to the output of the first latch and the clock signal, and a second latch which is set to provide a high logical output based on the output of the NAND gate. In this way, the second latch is set on a next rising edge of the clock signal. The flip-flop circuit may be faster and more consistent than a conventional flip-flop. In an example application, the flip-flop circuit may be used as part of a synchronizer circuit in a memory device for external write leveling.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
79.
ON-DIE ERROR DETECTION AND CORRECTION FOR META DATA
Methods, systems, and devices for on-die error detection and correction for meta data are described. A memory system may receive a write command associated with a first set of bits that includes data bits and meta data bits associated with the data bits and generate a second set of bits based on inputting the first set of bits into an error correction encoder. The second set of bits may include the data bits, the meta data bits, and parity bits. Upon generating the second set of bits, the memory system may store the meta data bits in at least a portion of a first memory space of the memory array of the memory system. The memory array may include the first memory space allocated for meta data and a second memory space allocated for data.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
80.
CLOCK SIGNAL GENERATOR GENERATING FOUR-PHASE CLOCK SIGNALS
An example apparatus includes a clock driver circuit block having a first region on which a dividing circuit generating a divided clock signal is located, a second region on which a write clock driver outputting a write clock signal is located, a third region on which a first read clock driver outputting a first read clock signal having higher frequency is located, and a fourth region on which a second read clock driver outputting a second read clock signal having lower frequency is located. The distance between the first region and the third region is longer than the distance between the first region and the second region and shorter than the distance between the first region and the fourth region.
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
81.
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
An example apparatus includes a memory cell capacitor; a memory cell transistor having diffusion regions; a redistribution structure coupled between one of the diffusion regions of the memory cell transistor and the memory cell capacitor; a first wiring; a peripheral transistor having diffusion regions; and a contact plug connected between one of the diffusion regions of the peripheral transistor and the first wiring. The first wiring is on a layer higher than that the redistribution structure is on.
Methods, apparatuses, and systems related to adjustment of circuit tests are described. A memory device may include a self-test circuit that is configured to selectively suspend collection and/or processing of test results for one or more portions of the self-test.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
Various examples are directed to systems and methods involving a memory device comprising a memory array comprising a number of memory cells arranged into a number of pages, a number of rows, and a number of columns. Each respective memory cell of the number of memory cells may be part of a column of the number of columns, a row of the number of rows, and a page of the number of pages. A first column of the number of columns may be electrically coupled to store parity data for a first portion of the number of pages and column redundancy data for a second portion of the number of pages.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
Methods, systems, and devices for weighted distributed-access across memory spaces are described. Multiple commands may be received. The multiple commands may include first commands associated with a first memory space of a memory system that is assigned a first priority of multiple priorities, second commands associated with a second memory space of the memory system that is assigned a second priority of the multiple priorities, and third commands associated with a third memory space of the memory system that is assigned a third priority of the multiple priorities. The multiple commands may be executed using an interleaving pattern that is based on the priorities of the memory spaces.
An example apparatus includes: first and second inverters cross-coupled to each other, a first transistor coupled between the first and third circuit nodes; a second transistor coupled between the second and fourth circuit nodes; a plurality of third transistors coupled in parallel between the third circuit node and the second power line; and a plurality of fourth transistors coupled in parallel between the fourth circuit node and the second power line. When the control code signal indicates a first value: at least one of the plurality of third transistors is brought into an OFF state; remaining one or ones of the plurality of third transistors are brought into an ON state; at least one of the plurality of fourth transistors is brought into an OFF state; and remaining one or ones of the plurality of fourth transistors are brought into an ON state.
Methods and apparatus are provided for double-sided storage nodes in two directions in three-dimensional memory. An array of vertically stacked memory cells can include horizontally oriented access devices electrically connected to horizontally oriented storage nodes. The horizontally oriented storage nodes can include a first electrode, including a first conductive material extending in a horizontal direction from, and in electrical contact with, an electrical interface to the second source/drain region of a given vertically stacked memory cell, the first conductive material having interior and exterior surfaces, and a second electrode separated from interior and exterior surfaces of the first conductive material by a dielectric material, wherein the second electrode is formed continuously in a vertical direction along the memory cells to form double-sided storage nodes in two directions with the interior and exterior surfaces of the first conductive material.
H10D 62/834 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé caractérisés en outre par les dopants
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory device, which includes: a first deck including first levels of conductive materials interleaved with first levels of dielectric materials; a second deck including second levels of conductive materials interleaved with second levels of dielectric materials; memory cell strings including pillars extending through at least a portion of each of the first deck and the second deck; a first conductive contact contacting a level of the first levels of conductive materials; a second conductive contact contacting a level of the second levels of conductive materials; and a dielectric pillar extending in the direction from the first deck to the second deck, the dielectric pillar including an end portion between the level of the first levels of conductive material and the level of the second levels of conductive materials.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
88.
WORD LINE STRUCTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS
Methods, systems, and devices for word line structures for three-dimensional memory arrays are described. A memory device may include word line structures that support accessing memory cells arranged in a three-dimensional level architecture. The word line structures may be arranged above a substrate and be separated from each other by respective dielectric layers. Each word line structure may include word line members and a word line plate that is connected to each word line member. Each word line plate may include a contact that may be coupled with a word line decoder operable to bias the word line plate. To couple the word line plate to the word line decoder, the memory device may include first vias that extend through holes in the word line plates and are coupled with second vias that extend from a respective contact through openings in the word line plates above the contact.
Methods, systems, and devices for techniques for concurrent host system access and data folding are described. A memory system may determine to transfer (e.g., fold) data from a set of source data blocks to a set of destination data blocks. The memory system may receive a command to access a first source data block of the set of source data blocks concurrent with the data transfer. The memory system may generate a first order for transferring respective portions of the data that is based on a second order associated with a sequential read of the data from the set of destination data blocks. Based on the accessing the first source data block being concurrent with the data transfer, the first order may exclude a first portion of the data from the first source data block such that the data transfer and the accessing may be concurrently performed.
A variety of applications can include apparatus having a memory device structured with an array of memory cells and a complementary metal-oxide-semiconductor (CMOS) device coupled to the array. The CMOS device can include a gate electrode on and contacting the polysilicon gates of a p-channel metal-oxide semiconductor (PMOS) transistor and a n-channel metal-oxide-semiconductor (NMOS) transistor of the CMOS device, where the gate electrode is a multi-metal stack. The multi-metal stack of the gate electrode can be two levels of different metal compositions.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
91.
SOLDER BASED HYBRID BONDING FOR FINE PITCH AND THIN BLT INTERCONNECTION
A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.
Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A method includes configuring a memory system with a first set of operating characteristics corresponding to a first thermal voltage model, monitoring operation of the memory system, selecting a second thermal voltage model based on the monitored operation of the memory system, configuring the memory system with a second set of operating characteristics corresponding to the second thermal voltage model, and writing data to the memory system configured with the second set of operating characteristics.
A microelectronic device is disclosed including a control logic structure that includes sense amplifiers clustered around sense amplifier exit regions; an upper memory array structure underlying the control logic structure and that includes memory cells coupled to some of the sense amplifiers of the control logic structure by way of routing extending through the sense amplifier exit regions; and a lower memory array structure underlying the upper memory array structure and that includes additional memory cells coupled to some other of the sense amplifiers of the control logic structure by way of additional routing extending through the sense amplifier exit regions.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
A memory device includes a resistor string digital to analog convertor (DAC) configured to supply one or more offset voltages to a decision feedback equalizer (DFE) based on high and low bias voltages. The memory device also includes bias voltage generation circuitry configured to generate a reference current based on an offset voltage range trim, to generate a first correction current based on a detected temperature change, generate a second correction current based on a supplied voltage, the reference voltage of the memory device, and a supply correction trim, to generate an adjusted reference current based on the reference current, the first correction current, and the second correction current, to generate the high bias voltage based on the adjusted reference current, to generate the low bias voltage based on the reference current, and to supply the high bias voltage and the low bias voltage to the resistor string DAC.
A vertical ferroelectric transistor comprises an upper source/drain region and a lower source/drain region having a channel region vertically there-between. A gate is laterally aside the channel region. Ferroelectric material is laterally aside and laterally between the gate and the channel region. Insulator material of different composition from that of the ferroelectric material is laterally aside and laterally between the gate and the ferroelectric material. The insulator material comprising (a) and (b) that are laterally aside one another and described herein. Ferroelectric memory and method are also disclosed.
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
98.
PREDICT TIMES FOR OPERATIONS TO REDUCE GARBAGE COLLECTION IN A DATA STORAGE DEVICE BASED ON FLEXIBLE DIRECT PLACEMENT
A computing device having a host system coupled to a memory sub-system, the host system having at least one processing device configured to run a garbage collection manager and a plurality of storage space tenants. The garbage collection manager can: track a history of data storage instances of data being written, according to a protocol of flexible direct placement (FDP), to reclaim units in the memory sub-system by the plurality of storage space tenants; identify, based at least in part on the history, a reclaim unit as a candidate for accelerated invalidation of valid data remaining in the reclaim unit; determine, based at least in part on the history, estimates of expiration time of the valid data; and determine, based on the estimates, whether to perform operations to accelerate invalidation of the valid data remaining in the reclaim unit.
A computing device having a host system coupled to a memory sub-system. The host system runs a garbage collection manager and a plurality of storage space tenants. The garbage collection manager can: write, to the memory sub-system according to a protocol of flexible direct placement (FDP), data of the plurality of storage space tenants to a reclaim unit in the memory sub-system; identify, after a first portion of the data stored in the reclaim unit is invalidated, first storage space tenants having a second portion of the data remaining valid in the reclaim unit; communicate with the first storage space tenants to identify estimates of expiration time of the second portion; and select, based on the estimates, the reclaim unit for acceleration of invalidation of the second portion of the data.
Various aspects of the present disclosure relate to a process for managing block stripe assignment based on block error conditions. A processing device may identify, for a plurality of block stripes associated with a memory device, respective quantities of blocks that are associated with an error condition. The processing device may designate a first block stripe of the plurality of block stripes as a single-level cell (SLC) block stripe based on a first quantity of blocks in the first block stripe that are associated with the error condition, and may designate a second block stripe of the plurality of block stripes as a quad-level cell (QLC) block stripe based on a second quantity of blocks in the second block stripe that are associated with the error condition, where the first quantity is greater than the second quantity.
