Methods, systems, and devices for evaluation of memory device health monitoring logic are described. A memory device may include health monitoring logic that is operable to be enabled in a configuration that corresponds to an output, such as an expected output, regardless of a degradation level of the memory device. Such a configuration may be enabled in a mode, such as a test mode, during which the memory device, or a host device coupled with the memory device, or some combination, may evaluate a difference between the output and an actual output of the health monitoring logic. The actual output being the same as the output may provide an indication that at least a portion of the health monitoring logic is functioning properly, and the actual output being different than the output may provide an indication that at least a portion of the health monitoring logic is not functioning properly.
In some implementations, a controller may receive and from a host device, a command to write data to a memory location. The controller may compress the data using a lossy compression operation to obtain compressed data. The controller may cause the compressed data to be written to the memory location.
A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A63B 24/00 - Commandes électriques ou électroniques pour les appareils d'exercice des groupes
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
4.
Memory Circuitry And Methods Used In Forming Memory Circuitry
Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a capacitor and a horizontally-oriented transistor. Semiconductor material is directly below the vertically-alternating tiers. A lattice structure is within the semiconductor material. The lattice structure comprises insulative first vertical walls and insulative second vertical walls that cross laterally through one another below a top of the semiconductor material. The lattice structure comprises an insulative horizontal blanket layer that is vertically between and spaced from the top and a bottom of the semiconductor material. At least one of a plurality of the first vertical walls or a plurality of the second vertical walls are individually narrower at a top of the insulative horizontal blanket layer than at a bottom of the insulative horizontal blanket layer. Other embodiments, including methods, are also disclosed.
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks. A through-array-via (TAV) region comprises TAV constructions that extend through the insulative tiers and the conductive tiers. The TAV constructions individually comprise a radially-outer insulative lining and a conductive core radially-inward of the insulative lining. The insulative lining comprises a radially-inner insulative material and a radially-outer insulative material that are of different compositions relative one another. The radially-outer insulative material is in radially-outer recesses that are in the first tiers as compared to the second tiers. The radially-inner insulative material extends elevationally along the insulative tiers and the conductive tiers. Other embodiments, including method, are disclosed.
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A system includes a memory device and a processing device coupled to the memory device. The processing device is to perform operations including determining whether a set of memory access operations performed on a first wordline of the memory device satisfies one or more criteria. The operations further include, responsive to determining that the set of memory access operations satisfies the one or more criteria, causing a memory management operation to be performed at the first wordline and a second wordline of the memory device.
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/20 - InitialisationPrésélection de donnéesIdentification de puces
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
7.
DYNAMIC PARTITION COMMAND QUEUES FOR A MEMORY DEVICE
A partition command is stored at free memory address location of the local memory corresponding to an index of an address array. The index is associated with an entry in the address array. A last entry in a linked list of entries from a tail register is obtained based on an allocation of the stored partition command to a partition command queue of a plurality of partition command queues. The tail register corresponds to the partition command queue of the plurality of partition command queues. Responsive to obtaining the last entry in the linked list, an entry to the linked list after the last entry is appended. The entry corresponds to the index of the address array associated with the stored partition command.
A semiconductor device assembly is disclosed. The semiconductor device assembly includes a semiconductor substrate having a plurality of die locations at which a plurality of semiconductor dies are implemented, a scribe area interleaved between the plurality of die locations, and a peripheral area near a periphery of the semiconductor substrate. A first passivation material is disposed at the plurality of die locations, and a second passivation material is disposed at the scribe area and the peripheral area. The first passivation material and the second passivation material implement a bonding surface of the semiconductor device assembly.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
9.
MANAGING METADATA ASSOCIATED WITH MEMORY ACCESS OPERATIONS IN A MEMORY DEVICE
A system includes a plurality of memory devices and a processing device operatively coupled with the plurality of memory devices, to perform operations including: receiving a request to perform a memory access operation at a first memory region of a first memory device; determining, based on a data structure referencing a namespace, a mapping between an identifier of the first memory region and an identifier of a metadata region associated with the first memory region; identifying, based on an operation type of the memory access operation, one or more corresponding actions associated with the metadata region; and, responsive to causing the memory access operation to be performed on a first plurality of memory cells at the first memory device, causing at least one of the one or more corresponding actions to be performed on a second plurality of memory cells corresponding to the metadata region.
A processor can determine whether the device is in an inactive state and, responsive to determining that the device is in the inactive state, can access a number of addresses of the device. The processor can monitor output data generated by the device responsive to the number of addresses to determine whether accessing one or more of the number of addresses results in an error. The output data can be provided by the device along a path. The output data can be continuously monitored when the device is in the inactive state. The processor can perform an action responsive to determining that there is an error of the device.
A security server storing a plurality of cryptographic keys to support device authentication, access control and proof of space plot farming. The cryptographic keys can include a first cryptographic key representative of an identity of a memory device, a second cryptographic key representative of a privilege to access a memory region in the memory device, and a third cryptographic key representative of a pool of proof of space plots. The security server can sign blocks in a blockchain created via plots in the pool, sign commands to access the memory region, and secure transfer of the second and/or third cryptographic key to the computer operated by an owner of the memory device.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p. ex. les mémoires adressables directement
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
12.
SEMICONDUCTOR ASSEMBLIES WITH SYSTEMS AND METHODS FOR MANAGING HIGH DIE STACK STRUCTURES
A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
13.
Asymmetric Read-Write Sequence for Interconnected Dies
Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.
A memory device includes a memory array having memory cells associated with wordlines. Control logic, operatively coupled with the memory array, causes a first set of memory cells, associated with a first wordline of the memory array, to be programmed with a first set of threshold voltage distributions. After a second set of memory cells, associated with a second wordline that is adjacent to the first wordline, has been programmed, the control logic causes the first set of memory cells to be further coarse programmed with an intermediate third set of threshold voltage distributions that is greater in number than the first set of threshold voltage distributions. The control logic causes the first set of memory cells to be fine programmed with a final third set of threshold voltage distributions.
Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.
A memory sub-system to initiate an erase operation to erase a first set of memory cells of a first memory block of a first memory plane and a second set of memory cells of a second memory block of a second memory plane of a memory device. A set of erase pulses of the erase operation are caused to be applied to the first set of memory cells of the first memory block and the second set of memory cells of the second memory block concurrently. One or more erase verify sub-operations of the erase operation are executed to verify the first set of memory cells and the second set of memory cells are erased.
Implementations described herein relate to a system that includes volatile memory and a controller. The controller may receive a command to write data to the volatile memory, where the command indicates a logical address associated with the data. The controller may compare the data to one or more duplicate data patterns to identify whether the data matches the duplicate data pattern. The controller may map, responsive to the data matching the duplicate data pattern, a physical address associated with the duplicate data pattern to the logical address, without writing the data to the volatile memory.
A computing device having a compute express link (CXL) connection between a memory sub-system and a host system and having storage access queues configured at least in part in the memory sub-system. The memory sub-system can attach, as a memory device, a portion of its fast random access memory over the connection to the host system. One or more storage access queues can be configured in the memory device. The host system can use a cache-coherent memory access protocol to communicate storage access messages over the connection to the random access memory of the memory sub-system. Optionally, the host system can have a memory with second storage access queues usable to access the storage services of the memory sub-system over the connection using a storage access protocol.
G06F 12/0815 - Protocoles de cohérence de mémoire cache
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p. ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.
This disclosure configures a memory sub-system controller to dynamically compute a select gate (SG) scan threshold. The controller accesses a default cadence criterion associated with an individual portion of a set of memory components and computes a new cadence criterion for the individual portion of the set of memory components based on the default cadence criterion. The controller determines that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion. The controller, in response to determining that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion, applies a memory operation to test reliability of the individual portion and selectively retires the individual portion based on a result of testing the reliability of the individual portion.
This disclosure configures a memory sub-system controller to dynamically compute a select gate (SG) scan threshold. The controller accesses a default cadence criterion associated with an individual portion of a set of memory components and computes a new cadence criterion for the individual portion of the set of memory components based on the default cadence criterion. The controller determines that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion. The controller, in response to determining that current cadence information for the individual portion of the set of memory components satisfies the new cadence criterion, applies a memory operation to test reliability of the individual portion and selectively retires the individual portion based on a result of testing the reliability of the individual portion.
Apparatuses for timing control in a write path are disclosed. An example apparatus includes: a clock input circuit that receives a clock signal and provides an internal clock signal; a command decoder that receives command signals and the internal clock signal, and provides an active write command signal when the command signals indicates a write operation; a write latency shifter that receives the write command signal, a latency value and a WICA value, adjusts timing of the write command signal responsive to the latency value and the WICA value, and provides a shifted write command signal; and a write DLL including a delay line that receives the shifted write command signal and provides a delayed write command signal. The write DLL provides the WICA value to set a propagation time from the clock input circuit to the write DLL to be a multiple of a period of the clock signal.
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
23.
INCOMPLETE SUPERBLOCK MANAGEMENT FOR MEMORY SYSTEMS
Aspects of the present disclosure configure a system component, such as a memory sub-system controller. to provide superblock management based on memory component reliabilities.
Methods, systems, and devices for inter-device communications for memory health monitoring are described. These communications relate to a host device that is associated with a memory device that monitors and reports health information (e.g., one or more parameters associated with a status of the memory device). The memory device may transmit the health information to the host device (e.g., a vehicle or a computer of the vehicle), which may perform one or more operations and transmit the health information to another entity of a system (e.g., ecosystem) including the host device. The host device may additionally or alternatively use the health information. In some cases, the other entity may receive the health information and transmit a signal back to the host device based on the health information. The other entity of the ecosystem may receive the health information and may make a determination based on the health information.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
25.
Integrated Circuitry Comprising A Memory Array Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating conductive tiers and insulative tiers. The stack comprises laterally-spaced memory-block regions. The lower portion comprises multiple lower of the conductive tiers and multiple lower of the insulative tiers. The lower insulative tiers comprise insulative material. The lower conductive tiers comprise sacrificial material that is of different composition from that of the insulative material. The sacrificial material is replaced with conducting material. After the replacing of the sacrificial material, the vertically-alternating conductive tiers and insulative tiers of an upper portion of the stack are formed above the lower portion. The upper portion comprises multiple upper of the conductive tiers and multiple upper of the insulative tiers. The upper insulative tiers comprise insulating material. The upper conductive tiers comprise sacrifice material that is of different composition from that of the conducting material, the insulating material, and the insulative material. The sacrifice material is replaced with conductive material. Other embodiments, including structure independent of method, are disclosed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.
H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
27.
EFFICIENT PROCESSING OF NESTED LOOPS FOR COMPUTING DEVICE WITH MULTIPLE CONFIGURABLE PROCESSING ELEMENTS USING MULTIPLE SPOKE COUNTS
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.
A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
29.
Memory Circuitry And Methods Used In Forming Memory Circuitry
Memory circuitry comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a capacitor and a horizontally-oriented transistor. Semiconductor material is directly below the vertically-alternating tiers. Insulative vertical walls extend through the vertically-alternating tiers into the semiconductor material there-below. Individual of the insulative vertical walls below a top of the semiconductor material comprise an upper portion directly above and joined with a lower portion. The individual insulative vertical walls comprise at least one external jog surface in a vertical cross-section in and below the top of the semiconductor material where the upper and lower portions join. The lower portion is wider in the vertical cross-section in the semiconductor material than the upper portion where the upper and lower portions join in the semiconductor material. Method embodiments are disclosed.
Methods, systems, and devices for a cloud architecture for tracking field entropy are described. For instance, a node of a supply chain may provide, to a verification device, a first identity of a device associated with the supply chain (e.g., a semiconductor device, a memory device). The node may also provide, to the verification device, a request for entropy. The verification device may provide, to the node, entropy based on the first identity and the request from the node, where a second identity is derived based on the entropy. The verification device may store the second identity at the verification device and the node may store the second identity at the device.
G06F 21/44 - Authentification de programme ou de dispositif
31.
Ferroelectric Transistor, Memory Circuitry Comprising Ferroelectric Transistors, And Method Used In Forming Memory Circuitry Comprising Memory Cells That Individually Comprise A Horizontal Ferroelectric Transistor
A ferroelectric transistor comprises two source/drain regions having a channel region horizontally there-between. The channel region has opposing front and back sides along a horizontal current-flow direction through the channel region. A front gate is on the front side of the channel region. A front-gate insulator is horizontally between the front gate and the front side of the channel region. The front-gate insulator comprises a dielectric material and a ferroelectric material that are each directly against the front gate. More of the ferroelectric material is directly against the front gate than is the dielectric material. Other embodiments, including methods, are disclosed.
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10B 51/10 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la configuration vue du dessus
H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
Methods, systems, and devices for an enhanced sense amplifier architecture are described. An architecture of p-type transistors in a sense amplifier may be modified to support greater accuracy of voltage sensing operations in a memory system. A shape and/or a positioning of one or more channel portions of a p-type transistor, relative to one or more gate portions of the p-type transistor, may increase an effective channel length of the p-type transistor, which may support an increased accuracy of cell voltage sensing. In some examples, a channel portion of the p-type transistor may have a non-rectangular shape to support a relatively longer electrical path between a source and a drain of the p-type transistor. In some examples, a shape of a gate portion of the p-type transistor may have a non-rectangular shape to support a relatively longer path between the source and the drain.
H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
Control circuitry (e.g., for a memory device in a system such as a CXL system) can receive counter values indicating a count of available repair resources for addressable portions of a memory device array. The control circuitry can store the counter values as repair flag tokens associated with respective corresponding portions of the addressable portions of the memory device array. Responsive to detecting an error in a first addressable portion of the addressable portions of the memory device array, the control circuitry can change the repair flag token associated with the first addressable portion where the error was detected.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
Aspects of the present disclosure configure a memory sub-system controller to perform a low-stress refresh erase (LSRE) in response to NAND detect empty page (NDEP) operations. The controller performs a first type of erase operation on a portion of a set of memory components. The controller performs a set of memory operations for detecting an empty page in the portion of the set of memory components. The controller, in response to determining that the set of memory operations for detecting the empty page in the portion of the set of memory components has failed, performs a second type of erase operation on the portion of the set of memory components.
Systems, methods, and apparatus to detect errors in data being accessed in a memory array. In one approach, a memory device includes error detection circuitry, error correction circuitry, and a controller. The controller accesses portions of the memory array. The error detection circuitry determines whether an error exists in the accessed portions. Errors are detected by comparing parity stored in each portion with the computed parity for all data stored in that portion when being accessed. If an error is detected for a portion, an address of that portion is stored in a scrub queue for later correction using the error correction circuitry.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
36.
MEMORY ARCHITECTURES WITH REPLACEMENT GATE THROUGH PIERS
Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
A memory device includes processing logic to perform operations including receiving a data (DQ) circuitry activation command via a command address (CA) bus operatively coupled with CA circuitry of the memory device, wherein the DQ circuitry activation command includes data identifying a die of the memory device, in response to receiving the DQ circuitry activation command, causing DQ circuitry of the memory device to transition from a standby state to an idle state, receiving, via the CA bus, a data transaction initialization command of a data transaction, and in response to receiving the data transaction initialization command, causing the DQ circuitry to transition from the idle state to an active state.
Aspects of the present disclosure configure a memory sub-system controller to perform a low-stress refresh erase (LSRE) in response to NAND detect empty page (NDEP) operations. The controller performs a first type of erase operation on a portion of a set of memory components. The controller performs a set of memory operations for detecting an empty page in the portion of the set of memory components. The controller, in response to determining that the set of memory operations for detecting the empty page in the portion of the set of memory components has failed, performs a second type of erase operation on the portion of the set of memory components.
Systems, apparatuses, and methods related to using memory device sensors are described. Some memory system or device types include sensors embedded in their circuitry. For instance, a device can be coupled to a memory device with an embedded sensor. The memory device can transmit the data generated by the embedded sensor using a sensor output coupled to the device. The memory device may generate, based at least in part on a characteristic of a memory device, a signal from a sensor embedded in the memory device and transmit the signal generated by the sensor from the memory device to another device coupled to the memory device.
G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level. The encoding unit and the decoding unit comprise respective circuit portions configured to be selectively activable based on the selected ECC protection level, and each circuit portion is configured to manage a respective predetermined payload and parity quantity of the codeword.
Methods, systems, and devices for memory architectures with replacement gate through piers are described. A memory architecture with relatively uniform memory cell thickness may be formed by forming a stack of materials including alternating layers of sacrificial material and dielectric material. The processing steps may include forming piers and forming cavities for pillars through the stack of materials. The pillars and electrodes may be formed within the cavities, and a subset of the piers may be removed. The layers of sacrificial material may be removed. A protective liner may be deposited around the electrodes and the remaining piers before depositing layers of metal in place of the sacrificial material. The cavities exposed by removing the subset of piers may be filled with new piers. The remaining piers are removed, and memory cells may be formed between the pillars and the electrodes. Then the removed piers are replaced.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
A command to read data stored in a block of a memory device is received. The block is determined to be a partial block based on the block having one or more unprogrammed pages. Based on the block being a partial block, a partial block offset table is accessed. The partial block offset table comprises a mapping between word line numbers and read-level voltage offsets for partial blocks. A last written page in the block is identified and a word line type is determined based on the last written page. A first read-level voltage offset for the block is determined from the partial block offset table based on the last written page and the word line type. The first read-level voltage offset is applied to the block before performing a read-level voltage calibration process that includes determining second read-level voltage offsets for the block.
A processing device receives a firmware update for a memory sub-system comprising a memory device. Based on the firmware update, the processing device stores a private key of a first device identity key pair in a non-volatile memory component of the memory sub-system such that the private key is persisted upon reset. The first device identity key pair is based on a first device identifier. Upon reset of the memory sub-system, the processing device generates a second device identifier based on the firmware update and generates a second device identity key pair based on the second device identifier. The processing device generates a new device identity certificate based on a public key of the second device identity key pair and signs the new certificate using the private key of the first device identity key pair. The processing device injects the new certificate into a certificate chain for the memory device.
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a media scan on a portion of the memory device to obtain a metrics dataset comprising a plurality of data state metric values; generating, for the metrics dataset, a plurality of data state metric bins comprising a first set of bins having a first bin width and a second set of bins having a second bin width; associating a first data state metric value of the plurality of data state metric values with a first bin of first set of bins, and a second data state metric value of the plurality of data state metric values with a second bin of the second set of bins; and generating a histogram reflecting the data associated with the plurality of data state metric bins.
Methods, systems, and devices for contact formation via a selective etch are described. For instance, a manufacturing system may form a first dielectric layer. Additionally, the manufacturing system may form a second dielectric layer on the first dielectric layer and a third dielectric layer on the second dielectric layer. The manufacturing system may etch the second dielectric layer and the third dielectric layer to form a set of first dielectric lines and a set of second dielectric lines. The manufacturing system may perform a metallization process to form a set of conductive lines and may form a contact above a subset of the set of conductive lines. A bottom surface of the contact may be above a respective top surface of a second dielectric line of the set of second dielectric lines based on forming the set of second dielectric lines.
A method includes determining a temperature and a voltage associated with a system, driving the system into an idle state responsive to determining the temperature and the voltage, measuring a leakage current of the system while in the idle state, associating the temperature and the voltage with the measured leakage current, and allocating a power token based on the temperature, the voltage, and the measured leakage current.
An example apparatus includes a command decoder configured to supply a plurality of mode parameters including a first mode parameter, a main mode register including a plurality of unit registers each configured to store an associated one of the plurality of mode parameters, a first local mode register configured to store at least a part of the first mode parameter, and a first circuit configured to be controlled by at least the part of the first mode parameter supplied from the first local mode register. A distance between the first local mode register and the first circuit is shorter than a distance between the main mode register and the first circuit. The first mode parameter supplied from the command decoder is stored in each of the main mode register and the first local mode register responsive to a mode register write signal.
The subject application relates to separate command address (SCA) protocol-based memory controllers. For instance, a method may include receiving, by a separate command address (SCA)-based memory controller, a plurality of commands, scheduling, by the SCA-based memory controller, the plurality of commands using two or more data path scheduler (DPS) request queues, converting the scheduled plurality of commands into SCA-based commands, selecting, from the scheduled SCA-based commands, one or more scheduled SCA-based commands for a sequence execution, and executing in sequence the selected one or more SCA-based commands using one or more logical units (LUNs) of a channel in a memory component.
An apparatus includes an enclosure to enclose a memory sub-system within an interior of the enclosure. The memory sub-system includes a memory device and a memory sub-system controller communicably coupled to the memory device. The enclosure includes a plurality of openings exposing at least a portion of the interior of the enclosure to an environment outside the enclosure. The enclosure further includes a plurality of fins affixed to an exterior surface of the enclosure. Each fin of the plurality of fins is disposed adjacent to at least one of the openings of the plurality of openings.
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a media scan on a portion of the memory device to obtain a metrics dataset comprising a plurality of data state metric values; generating, for the metrics dataset, a plurality of data state metric bins comprising a first set of bins having a first bin width and a second set of bins having a second bin width; associating a first data state metric value of the plurality of data state metric values with a first bin of first set of bins, and a second data state metric value of the plurality of data state metric values with a second bin of the second set of bins; and generating a histogram reflecting the data associated with the plurality of data state metric bins.
Control circuitry (e.g., for a memory device in a system such as a CXL system) can receive counter values indicating a count of available repair resources for addressable portions of a memory device array. The control circuitry can store the counter values as repair flag tokens associated with respective corresponding portions of the addressable portions of the memory device array. Responsive to detecting an error in a first addressable portion of the addressable portions of the memory device array, the control circuitry can change the repair flag token associated with the first addressable portion where the error was detected.
G11C 29/20 - Dispositifs pour la génération d'adressesDispositifs pour l'accès aux mémoires, p. ex. détails de circuits d'adressage utilisant des compteurs ou des registres à décalage à rétroaction linéaire [LFSR]
G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation
52.
CASCODED SENSE AMPLIFIERS FOR SELF-SELECTING MEMORY
Systems and methods for operating a memory include a sensing circuitry connected to a memory cell through an address decoder, a precharge circuitry configured to be connected to the sensing circuitry during a precharge stage and at least partially disconnected from the sensing circuitry during a sensing stage immediately following the precharge stage, and a reference voltage provided to the precharge circuitry, wherein the reference voltage is mirrored to the memory cell by mirroring a current flowing from the precharge circuitry with a current flowing from the sensing circuitry during the precharge stage.
A memory device includes a memory array and processing logic, operatively coupled to the memory array, to perform operations including initiating, with respect to a target cell of the memory array, a read operation, determining whether to perform the read operation as a corrective read with read level offset calibration, and in response to determining to perform the read operation as a corrective read with read level offset calibration, performing the corrective read with read level offset calibration to determine a calibrated read level offset associated with a state information bin to which the target cell is assigned.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
54.
NAMESPACE SIZE ADJUSTMENT IN NON-VOLATILE MEMORY DEVICES
A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.
A processing device in a memory sub-system receives, from a host system, a plurality of memory access requests associated with a plurality of processing threads executed by a plurality of processing cores on the host system, identifies the plurality of processing threads with which the plurality of memory access requests are associated, and tracks respective numbers of the plurality of memory access requests that are associated with each of the plurality processing threads in a given period of time. The processing device further selects, based on the tracking, a subset of the plurality of processing threads, prefetches data associated with the subset of the plurality of processing threads from a memory device and stores the data in a cache memory.
A memory device includes processing logic to perform operations including receiving a data (DQ) circuitry activation command via a command address (CA) bus operatively coupled with CA circuitry of the memory device, wherein the DQ circuitry activation command includes data identifying a die of the memory device, in response to receiving the DQ circuitry activation command, causing DQ circuitry of the memory device to transition from a standby state to an idle state, receiving, via the CA bus, a data transaction initialization command of a data transaction, and in response to receiving the data transaction initialization command, causing the DQ circuitry to transition from the idle state to an active state.
An example system includes: a memory chip having a plurality of external terminals; and a controller chip coupled to the plurality of external terminals of the memory chip and configured to issue, via some of the plurality of external terminals, a plurality of commands including a power down entry command and a refresh command. The memory chip is configured to: change an operation mode from a normal mode to a power down mode when the power down entry command is issued from the controller chip; perform a refresh operation when the refresh command is issued from the controller chip in the normal mode; and perform the refresh operation when the controller chip brings one of the plurality of external terminals into a first predetermined level in the power down mode.
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
Methods, systems, and devices for zone writing and maintenance for memory systems are described. A memory system may support a zoned write operation, where data associated with a preferred zone may be written with a first cursor, and data associated with other zones may be written with one or more second cursors. For example, a zone associated with a highest access frequency may be written using a single-level cell cursor, and other zones may be written using a higher-level cursor, such as a triple-level cursor. After writing the zones to a quantity of virtual blocks, a maintenance operation may be performed to reorder the zones within the quantity of virtual blocks according to access frequencies of the zones. Additionally, performing the maintenance operation may include performing garbage collection for the zones, such that invalid zones may be erased and valid zones may be reconsolidated within the quantity of virtual blocks.
A memory device includes a memory array and control logic, operatively coupled to the memory array, to receive, from a memory sub-system controller, a command related to execution of a memory access operation associated with one or more memory blocks of the memory device. In response to the command, a portion of a page buffer of the memory device is reserved. The memory device causes at least a portion of non-host data received from a high-performance local memory of the memory sub-system controller to be stored in the portion of the page buffer.
Apparatus and methods are disclosed, including transistors, semiconductor devices and systems. Example semiconductor devices and methods include a dielectric isolation structure located at least partially beneath a semiconductor body and between the semiconductor body and a substrate. Example semiconductor devices and methods also include an electrical contact coupling the semiconductor body to the substrate. In one example, the electrical contact reduces or eliminates a floating body effect in the semiconductor body.
A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
62.
APPARATUSES AND METHODS TO PERFORM SELF-SCRUB OPERATIONS AT A MEMORY
An exemplary system includes a memory comprising an error correction code (ECC) circuit and a scrub circuit, The ECC, during a read operation corresponding to a first read command, detects and corrects an error in read data read from a target row of a memory cell array using an ECC and to provide corrected read data and a ECC error alert (EEA) signal having a value based on a number of errors detected in the read data. The scrub circuit, during the read operation and in response to self-scrub mode being enabled, causes the corrected read data to be written back to the target row of the memory cell array in response to the EEA having a scrub required value.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A command to read data stored in a block of a memory device is received. The block is determined to be a partial block based on the block having one or more unprogrammed pages. Based on the block being a partial block, a partial block offset table is accessed. The partial block offset table comprises a mapping between word line numbers and read-level voltage offsets for partial blocks. A last written page in the block is identified and a word line type is determined based on the last written page. A first read-level voltage offset for the block is determined from the partial block offset table based on the last written page and the word line type. The first read-level voltage offset is applied to the block before performing a read-level voltage calibration process that includes determining second read-level voltage offsets for the block.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
64.
ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRAMMING DISTRIBUTION AND A PROGRAMMING DISTRIBUTION ADJACENT TO AN INITIAL PROGRAMMING DISTRIBUTION
A processing device determines a plurality of computing error metrics that are indicative of operational characteristics between programming distributions within the memory device. The processing device performs a program targeting operation on a memory cell of the memory device to calibrate one or more program verify (PV) targets associated with the programming distributions. Performing the program targeting operation comprises the processing device selecting a rule from a predefined set of rules based on the plurality of computing error metrics, wherein the predefined set of rules corresponds to an adjusting of a PV target of a last programming distribution. In addition, the processing device adjusts, based on the selected rule, the one or more PV targets of a plurality of PV targets associated with the programming distributions, wherein the one or more PV targets correspond to one or more respective voltage values for programming memory cells of the memory device.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 5/04 - Supports pour éléments d'emmagasinageMontage ou fixation d'éléments d'emmagasinage sur de tels supports
G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
The disclosed embodiments are directed to preventing the writing of malformed cryptographic keys to a memory device. In one embodiment, a system is disclosed comprising a storage array, the storage array storing a first cryptographic key; and a processor configured to: receive a command from a host processor, the command including a second cryptographic key, a first signature, a second signature, and at least one field, determine that the first signature is valid using the second cryptographic key and the at least one field, determine that the second signature is valid using the first cryptographic key, the first signature and the at least one field, and replace the first cryptographic key with the second cryptographic key after determining that both the first signature and second signature are valid.
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A method includes receiving, by a computing device, a message from a host device. In response to receiving the message, the computing device generates an identifier, a certificate, and a key. The identifier is associated with an identity of the computing device, and the certificate is generated using the message. The computing device sends the identifier, the certificate, and the key to the host device. The host device verifies the identity of the computing device using the identifier, the certificate, and the key.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A system comprising a memory device and a processing device, operatively coupled to the memory device. The processing device initializes a timer at initialization of a block family and stores a value of the timer before powering down the system while the block family is open. Upon the system powering up, the system determines a value of a data state metric associated with memory cells of the block family and estimates a time after program value of the memory cells based on the value of the data state metric. The processing device increments the value of the timer based on the time after program value and closes the block family based on the incremented value of the timer.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G01K 3/04 - Thermomètres donnant une indication autre que la valeur instantanée de la température fournissant des valeurs moyennesThermomètres donnant une indication autre que la valeur instantanée de la température fournissant des valeurs intégrées par rapport au temps
G06F 1/3228 - Surveillance d’exécution de tâches, p. ex. par utilisation de temporisations d’attente, de commandes d’arrêt ou de commandes d’attente
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
Systems, apparatuses, and methods related to a memory controller for cache bypass are described. An example memory controller can be coupled to a memory device. The example memory controller can include a cache including a cache sequence controller configured to determine a quantity of a given type of result of cache look-up operations, determine the quantity satisfies a bypass threshold, and cause performance of a bypass memory operation that bypasses the cache and accesses the memory device.
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant la mémorisation cache sélective, p. ex. la purge du cache
69.
MEMORY DEVICE COARSE THRESHOLD ESTIMATE READ UNDER MULTI-PLANE MODE
Various embodiments provide for performance of a coarse threshold estimate (CTE) read on a memory device of a memory system under multi-plane mode, such as a memory sub-system. A system comprising: a memory device comprising a plurality of memory cells across a plurality of planes; and a processing device, operatively coupled to the memory device, configured to perform operations comprising: performing a multi-plane coarse threshold estimate read on a subset of the plurality of memory cells across at least a sub-plurality of the plurality of planes, the multi-plane coarse threshold estimate read comprising: performing a read strobe using a read voltage level on the subset of the plurality of memory cells across the at least sub-plurality of planes; and determining a count of non-conducting bitlines connected to the subset of the plurality of memory cells on a single plane of the at least sub-plurality of the plurality of planes, the count of non-conducting bitlines on the single plane being representative of all of the at least sub-plurality of planes; and receiving, from the memory device, the count of non-conducting bitlines on the single planes.
Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a semiconductor die, a skeletal heat transfer structure over the semiconductor die; and a casing over the skeletal heat transfer structure that is over the semiconductor die. The skeletal heat transfer structure provides multiple thermal conduction pathways to satisfy a thermal performance threshold of the semiconductor device assembly.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
Methods, systems, and devices for triggering lane margining are described. A memory system controller may dynamically trigger the lane margining procedure based on a quantity of link recovery procedures performed at one or more input/output (I/O) ports established between a memory system and a host system. For example, the memory system controller may monitor, during a first duration, the performance of link recovery procedures performed at the one or more I/O ports. Based on a quantity of the link recovery procedures satisfying a threshold of link recovery procedures, the memory system controller may determine a rate of change between the quantity of link recovery procedures and a second quantity of link recovery procedures. If the rate of change between the quantity of link recovery procedures and the second quantity of link recovery procedures is increasing, the memory system controller may initiate the lane margining procedure.
A media management operation is initiated on a plurality of management units of one or more memory devices managed by the controller. A first error status and second error status associated with a read stage of the media management operation performed on a first management unit of the plurality of management units is received. An error correction operation on the first management unit is performed responsive to determining that the first error status and the second error status indicate a correctable error in the first management unit. An entry mapping a logical address to a physical address associated with the first management unit is locked responsive to determining that no spare management unit is available.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A memory device includes a memory array and control logic, operatively coupled to the memory array, to receive, from a memory sub-system controller, a command related to a sequence of one or more debug operations associated with a memory device. In response to the command, the sequence of the one or more debug operations associated with the memory device is executed. The memory device provides information relating to execution of the sequence of the one or more debug operations to the memory sub-system controller.
A processing device in a memory sub-system receives, from a host system, a plurality of memory access requests associated with a plurality of processing threads executed by a plurality of processing cores on the host system, identifies the plurality of processing threads with which the plurality of memory access requests are associated, and tracks respective numbers of the plurality of memory access requests that are associated with each of the plurality processing threads in a given period of time. The processing device further selects, based on the tracking, a subset of the plurality of processing threads, prefetches data associated with the subset of the plurality of processing threads from a memory device and stores the data in a cache memory.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
A method performed by a distributed computing system is described. The distributed computing system includes one or more host nodes and a main memory connected to the one or more host nodes by a fabric interconnect. The method includes receiving, by an application program interface (API) of a host node, a function call from an application of a host device, the function call including a pointer to a memory object and a level of reliability for operations involving the memory object; and configuring system reliability features included in one or both of the fabric interconnect and memory devices of the main memory according to the level of reliability in the function call.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/16 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel
An inductor is formed on-chip with a memory sub-component comprising at least one three-dimensional (3D) NAND memory component. The inductor is solenoid-like in shape with at least one turn formed of vias and connections. The inductor includes at least a first set of vias, each via in the first set of vias being conductive and having a central axis that is parallel to central axes of the other vias of the first set of vias, the first set of vias including at least a first via, a second via, and a third via. The on-chip inductor further includes a first lower connection electrically connecting the first via and the second via. The on-chip inductor further includes a first upper connection electrically connecting the second via and the third via.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
G11C 5/08 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage pour interconnecter des éléments magnétiques, p. ex. des noyaux toroïdaux
A processing device receives a firmware update for a memory sub-system comprising a memory device. Based on the firmware update, the processing device stores a private key of a first device identity key pair in a non-volatile memory component of the memory sub-system such that the private key is persisted upon reset. The first device identity key pair is based on a first device identifier. Upon reset of the memory sub-system, the processing device generates a second device identifier based on the firmware update and generates a second device identity key pair based on the second device identifier. The processing device generates a new device identity certificate based on a public key of the second device identity key pair and signs the new certificate using the private key of the first device identity key pair. The processing device injects the new certificate into a certificate chain for the memory device.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Methods, systems, and devices for parameter table protection for a memory system are described. Upon booting a memory system for a first time, the memory system or a host system may generate an error control code associated with parameter data stored to the memory system. The error control code may be stored to the memory system and may be configured to correct one or more errors in the parameter data upon subsequent boot sequences of the memory system. Accordingly, upon booting the memory system for a second or a subsequent time, the error control code may be used to identify and correct errors in the parameter data, which may reduce the quantity of copies of parameter data stored to the memory system and may prevent the memory system from experiencing a system crash.
The disclosure configures a memory sub-system controller to store data in a host memory buffer. The controller accesses data that identifies a host memory buffer (HMB) portion of a temporary storage device that has been allocated to a memory sub-system by a host. The controller generates a virtual address space associated with the memory sub-system, the virtual address space comprising a first set of physical storage locations on one or more storage devices of the memory sub-system and a second set of physical storage locations on the HMB. The controller performs one or more memory operations on user data received from the host using the virtual address space and a set of memory components of the memory sub- system.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
80.
Methods of forming nanostructures utilizing self-assembled nucleic acids
A method of forming a structure comprises forming a pattern of self-assembled nucleic acids over a material. The pattern of self-assembled nucleic acids is exposed to at least one repair enzyme to repair defects in the pattern. The repaired pattern of self-assembled nucleic acids is transferred to the material to form features therein. A method of decreasing defect density in self-assembled nucleic acids is also disclosed. Self-assembled nucleic acids exhibiting an initial defect density are formed over at least a portion of a material and the self-assembled nucleic acids are exposed to at least one repair enzyme to repair defects in the self-assembled nucleic acids. Additional methods are also disclosed.
H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
B81C 1/00 - Fabrication ou traitement de dispositifs ou de systèmes dans ou sur un substrat
B82Y 40/00 - Fabrication ou traitement des nanostructures
H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
Methods, systems, and devices for error correction disablement by a memory system are described. The method may include a memory system reading, at a first time, data from one or more memory cells of a memory device and disabling a first error correction capability based on the data comprising one or more errors of a first type. Further, the method may include the memory system reading, at a second time, the data and transmitting the data to a host device based on the data not comprising the one or more errors of the first type.
A memory subsystem that includes a memory device, a first host interface, a serial interface controller that provides host access to a boot partition of the memory device using the first host interface, a second host interface, and a high-speed interface controller that provides host access to a user partition of the memory device using the second host interface.
Systems and methods are provided for testing a 3D PHY of a memory device by using a MBIST circuit. The memory device includes a 3D PHY for communications with a host device through a customized communication interface. The memory device also includes a MBIST circuit configured to be used for testing the memory device when the customized communication interface is not available or undesired to be used for testing of the memory device. The memory device is tested by using the MIBST circuit before the memory device is coupled to the customized communication interface, which is desired, for example, for the purpose of cost saving and/or quality control of the memory device.
In some implementations, a memory device may associate a first memory stripe with a second memory stripe. The memory device may receive a first codeword associated with the first memory stripe. The memory device may identify, using the first codeword, a first error in a first set of data bits that are associated with the first memory stripe. The memory device may correct the first error using the first codeword. The memory device may receive a second codeword associated with the first memory stripe and the second memory stripe. The memory device may identify, using the second codeword, a second error in a second set of data bits that are associated with the first memory stripe and the second memory stripe. The memory device may correct the second error using the second codeword.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
85.
PARTIAL-FINE PROGRAM SCHEME FOR RELIABILITY RISK WORD LINES
In some implementations, a memory device may receive a program command. The memory device may determine whether a portion of the memory is associated with a reliability risk. The memory device may determine, based on whether the portion of the memory is associated with the reliability risk, a selected program scheme to be used to program the host data to the portion of the memory, wherein the selected program scheme is one of a single-fine program scheme or a partial-fine program scheme, wherein the single-fine program scheme includes performing a fine pulse for each level of cells being programmed, of multiple levels of cells being programmed, and wherein the partial-fine program scheme includes performing multiple fine pulses for only a subset of the multiple levels of cells being programmed. The memory device may execute the program command by performing the selected program scheme.
G11C 16/10 - Circuits de programmation ou d'entrée de données
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
86.
PROGRAMMING VIDEO DATA TO DIFFERENT PORTIONS OF MEMORY
Programming video data to different portions of memory is described herein. An example system includes a host interface, a memory device having a first portion and a second portion, and a controller coupled to the host interface and the memory device. The controller can be configured to program video data received via the host interface to the first portion of the memory device, and program video data received via the host interface to the second portion of the memory device instead of to the first portion of the memory device in response to receiving a signal that a trigger event has occurred.
Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
88.
TECHNIQUES FOR INITIATING CHECKPOINT OPERATIONS IN A MEMORY SYSTEM
Methods, systems, and devices for techniques for initiating checkpoint operations in a memory system are described. A memory system may be configured to initiate a checkpoint operation prior to the change log reaching capacity, for example, by initiating the checkpoint procedure based on whether a quantity of metadata tables to be updated during the checkpoint operation satisfies a threshold. For example, the memory system may update logical-to-physical (L2P) address mappings in volatile memory of the memory system, where each L2P address mapping may correspond to a respective metadata table. The memory system may determine whether to update the respective metadata tables based on a quantity of metadata tables associated with the updated L2P address mappings satisfying a first threshold or based on a quantity of updated L2P address mappings satisfying a second threshold. If either the first or second thresholds are satisfied, the memory system may initiate the checkpoint procedure.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
89.
INDICATION FOR EXITING REFRESH OF AN INVALID MEMORY BLOCK
Methods, systems, and devices for indication for exiting refresh of an invalid memory block are described. A memory system may store a refresh flag that indicates, during execution of a refresh operation, whether a source memory block of the refresh operation is valid. The refresh operation may be performed in portions, and the memory system may check the refresh flag during the refresh operation to determine whether to continue performing remaining portions of the refresh operation. If a controller of the memory system, or a host system, identifies that a memory block is invalid, the controller of the memory system or the host system may clear the refresh flag for the memory block. If the memory system identifies that the refresh flag is cleared during the refresh operation, the memory system may abort the refresh operation and may refrain from performing remaining portion(s) of the refresh operation.
G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
Techniques are provided for operating a memory package and more specifically to increasing bandwidth of a system having stacked memory. In an example, a system can include a storage device having a first type of volatile memory and a second type of volatile memory, and a host device coupled to the storage device. The host device can issue commands to the storage device to store and retrieve information of the system. The host device can include a memory map of the storage device and latency information associated with each command of the commands. The host can sort and schedule pending commands according to the latency information and can intermix commands for the first type of volatile memory and commands for the second type of volatile memory to maintain a high utilization or efficiency of a data interface between the host device and the storage device.
Various embodiments provide for performance of a coarse threshold estimate (CTE) read on a memory device of a memory system under multi-plane mode, such as a memory sub-system.
A method for performing automated GUI-driven OpROM validation starts with a processor executing an automated test script; and in response to executing the automated test script, the processor is caused to remotely accessing a memory sub-system using a web driver and an interface. The processor causes a BIOS terminal window of the memory sub-system to be displayed on a display screen. The processor captures a screenshot of the BIOS terminal window and generating an image based on the screenshot. The processor converts the image to text using OCR and generates an output comprising BIOS configuration details based on the text using a machine-learning algorithm. The processor then analyzes the output to validate the memory sub-system when no errors are detected in the output or to flag the memory sub-system when errors are detected in the output. Other embodiments are described herein.
G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Two of the first tiers have different vertical thicknesses relative one another. Channel-material strings of memory cells extend through the first tiers and the second tiers. Through the horizontally-elongated trenches, first conductive material is formed in void space in the two first tiers. The first conductive material fills the first tier of the two first tiers that has a smaller of the different vertical thicknesses in individual of the memory-block regions. The first conductive material less-than-fills the first tier of the two first tiers that has a larger of the different vertical thicknesses in the individual memory-block regions. Through the horizontally-elongated trenches, the first conductive material is isotropically etched from the first tier having the larger vertical thickness in the individual memory-block regions to leave the first conductive material in the first tier having the smaller vertical thickness in the individual memory-block regions. After the isotropically etching of the first conductive material and through the horizontally-elongated trenches, second conductive material is formed in the first tier having the larger vertical thickness in the individual memory-block regions. Other embodiments, including structure independent of method, are disclosed.
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
One or more data items is received by a processing device managing one or more memory devices partitioned into a plurality of die partitions. The one or more data items is determined to be written sequentially to one or more blocks within a die partition of the plurality of die partitions. Metadata associated with the one or more data items is written sequentially to one or more blocks across the plurality of die partitions.
A system includes a memory device including blocks. A first subset of the blocks is configured to store a first number of bits and a second subset of the blocks is configured to store a second number of bits, where the second number of bits is greater than the first number of bits. A processing device determines that a first block of a set of blocks of the first subset is a bad block. The processing device identifies a second block of the set blocks that is paired with the first block in association with a zone of a logical block address space of the memory device. The processing device causes an erase operation to be performed on the second block of the set of blocks to configure the second block to store the second number of bits.
Exemplary methods, apparatuses, and systems include receiving a request to perform an operation in memory. A subdivision of the memory to which the request is directed is determined. A command completion time based upon a command type for the operation and which subdivision of the memory to which the request is directed is determined. A command is sent to the memory for the operation. A request is sent to the memory for a status of the command based upon the determined command completion time.
A memory device includes a memory array comprising a plurality of planes and a plurality of independent plane driver circuits. The memory device further includes control logic to receive a request for one of the plurality of independent plane driver circuits to execute a high current event on a corresponding one of the plurality of planes in the memory device. The control logic is further to increment a counter tracking a number of high current events occurring in the memory device, and determine whether the number of high current events occurring in the memory device satisfies a threshold criterion. Responsive to determining that the number of high current events occurring in the memory device satisfies the threshold criterion, the control logic is to cause execution of the high current event to be delayed.
A memory module includes a number of memory devices which receive refresh commands. Each memory device determines if it is that device's turn in a sequence, for example by counting the refresh commands. When it is not a device's turn, it performs refresh operations at a first rate responsive to the refresh commands. When it is the device's turn, it performs refresh operations at a second, lower, rate responsive to the refresh commands, for example by skipping refresh operations.
Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/498 - Connexions électriques sur des substrats isolants
Implementations described herein relate to implementing a recovery mode for a memory device. In some implementations, the memory device may include memory and one or more components. The one or more components may be configured to receive, from a host system, an indication that the memory device is associated with a failure. The one or more components may be configured to receive, from the host system, a request to initialize a recovery of the memory device in response to the failure. The one or more components may be configured to initialize, based on the request, a reboot of the memory device. The one or more components may be configured to transmit, to the host system, status information obtained while rebooting the memory device, wherein the status information includes information associated with a current operational state of the memory device.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
