Implementations described herein relate generally to a split firmware architecture. For example, a memory system may store, in a first firmware slot at a memory system, a first firmware image associated with an operational mode of the memory system. The memory system may store, in a second firmware slot at the memory system, a second firmware image associated with a diagnostic mode of the memory system. The memory system may activate either the first firmware slot or the second firmware slot based at least in part on operating the memory system in the operational mode or in the diagnostic mode.
Control logic in a memory device selects two or more blocks of a plurality of blocks to concurrently scan during a scan operation. The control logic can further cause a first voltage to be applied to a dummy word line of each block of the two or more blocks to selectively couple a string of memory cells in each block of the two or more blocks to a different sense amplifier of a set of sense amplifiers coupled with the plurality of blocks. The control logic can cause a second voltage to be applied to a selected word line of each block of the two or more blocks to read a bit stored at a respective memory cell of the string of memory cells in each block out to the set of sense amplifier.
Processing logic maintains a data item tag hierarchy in view of user context information and identifies, from the data item tag hierarchy, a highest ranked data item tag of a plurality of data item tags associated with a data item, the plurality of data item tags representing a content of the data item. The processing logic further storing the data item on a memory device at a first shared storage location together with one or more additional data items with which the highest ranked data item tag is also associated.
A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. A ring is around individual of the channel-material strings in at least one of a lowest of the conductive tiers or a lowest of the insulative tiers. Individual of the rings have a top that is below all of the memory cells. Other embodiments are disclosed.
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
5.
SUB-WORD LINE DRIVER CIRCUITRY INCLUDING CHAIN OF TRANSISTORS TO REMOVE FLOATING WORD LINE STATES
A device comprises a number of sub-word line drivers and a chain of transistors. Each sub-word line driver includes a complementary pair of transistors coupled in parallel between a respective main word line and a respective word line. A first phase signal line is coupled to respective gates of respective N-type transistors of respective complementary pairs of transistors of the number of sub-word line drivers. A second phase signal line is coupled to respective gates of respective P-type transistors of the respective complementary pairs of transistors of the number of sub-word line drivers. Respective transistors of the chain of transistors are coupled between respective pairs of word lines of adjacent sub-word line drivers of the number of sub-word line drivers. The chain of transistors include a terminating transistor coupled between a first end word line of the number of word lines and a voltage line supplied with an inactive voltage.
Methods, systems, and devices for pillar-embedded and integrated select transistors are described. A memory die may include a substrate, a layered material stack over the substrate, and multiple pillars within the layered material stack. The pillars may be distributed throughout the layered material stack with a first pillar of the pillars positioned centrally relative to other pillars of the plurality of pillars. Each pillar may include multiple memory cells, and a select transistor coupled with the memory cells and a bit line. The select transistor may be configured to selectively couple the memory cells with the bit line. The memory die may also include multiple gate contacts formed within a spaces between the pillars. Each gate contact may be coupled with a respective gate of multiple select transistors of the pillars.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The storage-node electrode comprises a container-like shape comprising an axis. In a cross-section that is through and elongated along the axis, the storage-node electrode comprises a radially-outermost conductive surface comprising a first conductive material and a radially-innermost conductive surface comprising a second conductive material that is of different composition from that of the first conductive material. Other embodiments, including memory circuitry and method are disclosed.
An electronic device comprising a source stack comprising one or more conductive materials, and an oxide fill region within an upper portion of the source stack. A source contact is adjacent to the source stack and the oxide fill region, and a doped semiconductive material is adjacent to the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the doped semiconductive material, and pillars extend through the tiers, the doped semiconductive material, and the source contact and into the source stack. Additional electronic devices are also disclosed, as are related methods and electronic systems.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
9.
FILE SYSTEM STORAGE ALLOCATION BASED ON ZONES OF A MEMORY DEVICE
A host system includes a memory and a processing device operatively coupled with the memory. The processing device performs operations including: identifying a write request that comprises file system data for a file system, wherein the write request is stored in the memory; determining a data type associated with the file system data; identifying, among a plurality of zones maintained by a memory sub-system, a zone corresponding to the data type, wherein each zone of the plurality of zones is designated for storing a respective data type of a plurality of data types; and initiating a sequential write of the file system data at a location in the zone.
In some implementations, a memory controller may determine that an idle timer for a rank of a memory channel satisfies a first threshold. The memory controller may transition, based on determining that the idle timer for the rank satisfies the first threshold, the rank from a first power state to a second, lower power state, wherein at least one other rank of the memory channel is maintained in the first power state. The memory controller may determine that an activation trigger has occurred, wherein the activation trigger includes at least one of: determining, by the memory controller, that a reduced-power timer satisfies a second threshold, or receiving, by the memory controller, a command associated with the rank. The memory controller may transition the rank from the second power state to the first power state in response to determining that the activation trigger has occurred.
Methods, systems, and devices for split pillar memory architectures are described. A memory device may include a first pillar including a first dielectric material, a second pillar including the first dielectric material, and a third pillar positioned between the first pillar and the second pillar and including a second dielectric material. The memory device may also include a first portion of a first semiconductor material along a first side of the third pillar and a second portion of the first semiconductor material along a second side of the third pillar opposite the first side. The memory device may further include a first portion of a second semiconductor material positioned between multiple word lines and the first portion of the first semiconductor material and include a second portion of the second semiconductor material positioned between the multiple word lines and the second portion of the first semiconductor material.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Memory circuitry comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. The insulative tiers and the conductive tiers of the laterally-spaced memory blocks extend from a memory-array region into a stair-step region. Strings of memory cells comprise operative channel-material strings that extend through the insulative tiers and the conductive tiers in individual of the laterally-spaced memory blocks in the memory-array region. The operative channel-material strings directly electrically couple with conductor material of the conductor tier. The individual laterally-spaced memory blocks comprise an intermediate region between the operative channel-material strings and the stair-step region. A dummy through-array-via (TAV) extends through the insulative tiers and the conductive tiers in the intermediate region in the individual laterally-spaced memory blocks. The dummy TAV is directly electrically coupled with the operative channel-material strings in its memory block. Other embodiments are disclosed.
H10D 64/00 - Electrodes of devices having potential barriers
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A memory device may include a memory and a controller. The controller may be configured to receive a read command associated with a block of the memory. The controller may be configured to determine a block type associated with the block. The controller may be configured to identify, based on the block type, one or more read voltage offsets for a read operation associated with the block. The controller may be configured to perform the read operation based on the one or more read voltage offsets.
An example memory device includes a memory array and a processing device, operatively coupled to the memory array. The processing device is configured to perform operations, including: identifying a portion of the memory array; causing a first voltage level to be applied to one or more local bitlines of the identified portion of the memory array; causing a second voltage level to be applied to one or more local source lines of the identified portion of the memory array; causing a third voltage level to be applied to a plurality of local select gates of the identified portion of the memory array; causing the plurality of local select gates to transition to a floating state; and causing a fourth voltage level to be applied to one or more wordlines of the identified portion of the memory array.
An example apparatus includes a resistor pattern having a plurality of nodes, a plurality of transistors each having a first diffusion region coupled to an associated one of the plurality of nodes of the resistor pattern and a second diffusion region coupled in common to an output terminal. Each of the plurality of nodes of the resistor pattern is physically located over the first diffusion region of an associated one of the plurality of transistors.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
16.
STORING DATA TO HOST SYSTEM MEMORY UPON ENTRY OF A MEMORY SYSTEM NON-OPERATIONAL POWER STATE
Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a memory system may allocate a portion of a host system volatile memory as a buffer for storing data associated with the memory system when the memory system is in a non-operational power state. The memory system may determine a set of data stored in a memory system volatile memory that is to be preserved when the memory system is in the non-operational power state. The memory system may write the set of data to the buffer prior to entering the non-operational power state. Numerous other aspects are described.
Methods, systems, and devices for switch and hold biasing for memory cell imprint recovery are described. A memory device may be configured to perform an imprint recovery procedure that includes applying one or more recovery pulses to memory cells, where each recovery pulse is associated with a voltage polarity and includes a first portion with a first voltage magnitude and a second portion with a second voltage magnitude that is lower than the first voltage magnitude. In some examples, the first voltage magnitude may correspond to a voltage that imposes a saturation polarization on a memory cell (e.g., on a ferroelectric capacitor, a polarization corresponding to the associated voltage polarity) and the second voltage magnitude may correspond to a voltage magnitude that is high enough to maintain the saturation polarization (e.g., to prevent a reduction of polarization) of the memory cell.
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
18.
Track Memory Blocks of a Memory Sub-system Allocated to a Host System via a Predetermined Mapping Between a Logical Memory Space and a Logical Storage Space
A memory sub-system having: a random access memory configured to provide a memory space accessible, using a memory access protocol, by a host system over a connection between the host system and the memory sub-system; a non-volatile memory configured to provide a physical storage space accessible, via a storage access protocol, by the host system. The memory sub-system can: allocate, from the random access memory, a memory block; map the memory block to a logical memory region in a logical memory space; and establish, via a predetermined mapping between the logical storage space and the logical memory space, mapping between a logical block address, configured in a logical storage space and usable to access a portion of the non-volatile memory using the storage access protocol, and the memory block.
Methods, systems, and devices for techniques and devices to reduce bus cross talk are described. Adjacent conductive lines in a bus of a memory system may be electrically coupled if both conductive lines are concurrently driven to a high-state. For example, the bus may include a logic circuit coupled between the adjacent conductive lines, which may selectively couple the conductive lines based on the voltage applied to each conductive line. In some examples, the logic circuit may include an input coupled to the control signals of the drivers associated with the adjacent conductive lines. If both control signals are concurrently high, the logic circuit may activate a transistor to couple the conductive lines. Such electrical coupling may reduce or eliminate the capacitive coupling between the two conductive lines when both are driven to a high state, which may result in increased reliability of signals in the conductive lines.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
20.
LATERAL ETCH STOPS FOR ACCESS LINE FORMATION IN A MEMORY DIE
Methods, systems, and devices for lateral etch stops for access line formation in a memory die are described. A memory die may be formed with isolation regions that provide an etch stop to limit the extent of voids formed by removing a sacrificial material between layers of a dielectric region. For example, first trenches may be formed through a stack of alternating layers of a dielectric material and a sacrificial material, in which one or more materials may formed. Second trenches may be formed between a first trench and an array portion of the memory die, or between pairs of the first trenches, which may support the removal of at least a portion of the sacrificial material to form voids for access line formation. However, the materials formed in the first trenches may provide a boundary, or a restriction zone, that limits an extent of the material removal operation.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
G11C 16/06 - Auxiliary circuits, e.g. for writing into memory
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 41/42 - Simultaneous manufacture of periphery and memory cells
21.
METHODS FOR DEPOSITING SILICON FILMS BY ATOMIC LAYER DEPOSITION
Methods, systems, and devices for methods for depositing silicon films by atomic layer deposition are described. For instance, a device may expose a base material (e.g., multiple stacks of materials) to a first precursor to form a silicon compound on the base material, the first precursor including a silicon amidinate. The device may react a second precursor with the silicon compound and may form a layer of silicon on the base material based on exposing the base material to the first precursor and reacting the second precursor with the silicon compound.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly may include a first semiconductor pillar and a second semiconductor pillar extending vertically from a substrate. The integrated assembly may further include a first epitaxial structure extending vertically from the first semiconductor pillar and a second epitaxial structure extending vertically from the second semiconductor pillar, where the first epitaxial structure is separated from the second epitaxial structure by a gap. The integrated assembly may further include a nitride layer over the first epitaxial structure and the second epitaxial structure, where the nitride layer includes a bridge portion extending between a side portion of the first epitaxial structure and a side portion of the second epitaxial structure.
Methods, systems, and devices for diamond-based hybrid bonding for stacked semiconductor systems are described. For example, a stacked semiconductor system may be configured to implement one or more portions of diamond-form carbon (e.g., sp3 carbon, in which carbon atoms are bonded with four other carbon atoms) along a bonding interface (e.g., a hybrid bonding interface) between semiconductor components. In some examples, diamond-form carbon may be formed as a surface layer on one or both semiconductor components to be bonded, and one or more conductive paths may be formed through the one or more layers of diamond-form carbon. The diamond-form carbon may have a relatively low electrical conductivity and a relatively high thermal conductivity, and may support relatively higher bonding strength and relatively lower conductor and moisture migration rates than other techniques.
Methods, systems, and devices for pillar-embedded and integrated select transistors are described. A memory die may include a substrate, a layered material stack over the substrate, and multiple pillars within the layered material stack. The pillars may be distributed throughout the layered material stack with a first pillar of the pillars positioned centrally relative to other pillars of the plurality of pillars. Each pillar may include multiple memory cells, and a select transistor coupled with the memory cells and a bit line. The select transistor may be configured to selectively couple the memory cells with the bit line. The memory die may also include multiple gate contacts formed within a spaces between the pillars. Each gate contact may be coupled with a respective gate of multiple select transistors of the pillars.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly may include a first semiconductor pillar and a second semiconductor pillar extending vertically from a substrate. The integrated assembly may further include a first epitaxial structure extending vertically from the first semiconductor pillar and a second epitaxial structure extending vertically from the second semiconductor pillar, where the first epitaxial structure is separated from the second epitaxial structure by a gap. The integrated assembly may further include a nitride layer over the first epitaxial structure and the second epitaxial structure, where the nitride layer includes a bridge portion extending between a side portion of the first epitaxial structure and a side portion of the second epitaxial structure.
H10B 12/00 - Dynamic random access memory [DRAM] devices
26.
Logical to Physical Translation Table Adapted to Facilitate Tracking of Data of a Storage Space of a Memory Sub-System Cached or Buffered in a Memory Space of the Memory Sub-System
A memory sub-system having: memory cells of a first type to provide a memory space; and memory cells of a second type to provide a physical storage space. A controller of the memory sub-system is configured to: store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; store, the memory space, a copy of a data portion addressable in the logical storage space; configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; and store information to identify a location, in the memory space, at which the data portion is cached or buffered.
Methods, systems, and devices for stress and strain detection across a substrate of a semiconductor system using a photoelastic material are described. In some examples, a semiconductor system may include a memory module having at least one segment of a photoelastic material over and/or on a substrate of the memory module. In some examples, the segment is located proximate an area of the substrate that is subject to a stress and/or strain condition during insertion of the memory module (e.g., an edge connector of the memory module) into a socket. The photoelastic material may be configured improve detection and/or monitoring of stresses on the memory module.
G01L 1/24 - Measuring force or stress, in general by measuring variations of optical properties of material when it is stressed, e.g. by photoelastic stress analysis
A device comprises a number of sub-word line drivers, a chain of transistors, and a control signal line. Each sub-word line driver is coupled to a respective main word line of a number of main word lines and a respective word line of a number of word lines. Each sub-word line driver includes a transistor. Respective ones of the transistors of the chain are coupled between respective pairs of word lines of adjacent sub-word line drivers. The chain of transistors includes a terminating transistor coupled between a first word line and a voltage line supplied with an inactive voltage (e.g., a negative word line voltage). The control signal line is coupled to respective gates of respective transistors of the chain, to provide an enable signal to set or maintain the transistors in an on state to couple the word lines to the voltage line supplied with the inactive voltage.
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Channel openings extend through the first tiers and the second tiers in the memory-block regions. Channel material of channel-material strings is formed in the channel openings and the channel material is formed in the horizontally-elongated trenches. The channel material is removed from the horizontally-elongated trenches and the channel material of the channel-material strings is left in the channel openings. After removing the channel material from the horizontally-elongated trenches, intervening material is formed in the horizontally-elongated trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. Other embodiments, including structure independent of method, are disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
30.
TEMPERATURE CONTROLLED ZONE CREATION AND ALLOCATION
Respective temperature values for a plurality of dies of a memory device is obtained. Each respective temperature value is indicative of a temperature at a corresponding die of the plurality of dies of the memory device. The plurality of dies based on the respective temperature values, each die of the plurality of dies is ordered. A zone creation command directed to the memory device is received from a host. The zone creation command on the memory device on a die of the ordered plurality of dies is performed based on a temperature threshold.
Mapping addresses to banks can include receiving a plurality of row bits, a plurality of column bits, and a plurality of bank bits and generating a rank bit from a bank bit from the plurality of bank bits. Updated bank bits can be generated by removing the bank bit from the plurality of bank bits. The plurality of row bits, the plurality of column bits, the rank bit, and the updated bank bits can be provided to the controller to access a plurality of banks of the memory device.
Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to provide media fragmentation management. The controller receives, from a host, a file-based-optimization (FBO) entry comprising a plurality of logical block addresses (LBAs) associated with a file. The controller accesses a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components and determines a first quantity of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The controller computes a regression level for the file based on the first quantity of read operations relative to a second quantity of LBAs included in the plurality of LBAs.
A capacitor comprises a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes. The storage-node electrode comprises a container-like shape comprising an axis. In a cross-section that is through and elongated along the axis, the storage-node electrode comprises a radially-outermost conductive surface comprising a first conductive material and a radially-innermost conductive surface comprising a second conductive material that is of different composition from that of the first conductive material. Other embodiments, including memory circuitry and method are disclosed.
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An edge server may be implemented using an integrated circuit device having: a Deep Learning Accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an Artificial Neural Network executable by the Deep Learning Accelerator and second instructions of a server application executable by a Central Processing Unit; and an interface to a communication device on a computer network. The Central Processing Unit may be part of the integrated circuit device, or be connected to the integrated circuit device. The server application may be configured to provide services over the computer network based on output of the Artificial Neural Network and input received from one or more local devices via a bus, or a wired or wireless local area network.
Methods, systems, and devices for techniques for managing cross-temperature exposure in memory systems are described. A memory system controller may identify, during a boot sequence, a temperature associated with a write operation at a logical block address (LBA) of a first memory device, where the LBA is associated with a physical address of the first memory device that stores a portion of boot sequence data. The memory system controller may select a read setting based on a difference between an operating temperature of the first memory device during the boot sequence and the temperature associated with the write operation at the LBA of the first memory device. Accordingly, the memory system controller may perform a read operation to read the portion of the boot sequence data from the physical address associated with the LBA according to the read setting.
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initiate a scan operation on a plurality of block families of the memory device. Each of the plurality of block families is assigned to a voltage offset bin of a plurality of voltage offset bins. The processing device further determines that a number of scan operations to be performed in one scan interval is greater than a maximum number of scan operations to be performed in a scan interval. The processing device further determines based on the voltage offset bins of the plurality of block families and a time elapsed since execution of a previous scan operation of the plurality of block families, a scan priority of each of the plurality of block families, and schedules, based on the scan priority, a scan operation of one or more block families of the plurality of block families during one or more subsequent scan intervals. Based on the scan result, two or the plurality of block families which are scanned within the same or different intervals can be combined and thus release block family memory if their measurement results satisfy combining criterion.
A processing device obtains calibration samples for a block of a memory device from a subset of pages of the block. The processing device determines one or more calibration offsets for the block based on the calibration samples from the subset of pages of the block. The processing device applies the one or more calibration offsets during one or more read operations performed on the block of the memory device.
System-in-package devices, high-bandwidth memory devices, and associated systems and methods are disclosed herein. More specifically, a high-bandwidth memory (HBM) device according to the present technology can include a base die, a plurality of memory dies integrated with the base die, a mold compound carried by the base die surrounding the memory dies, and one or more through mold vias (TMVs) formed in the mold compound. Each of the TMVs can extend from a top surface of the mold compound to a metal layer of the base die that is thermally coupled to and/or integrally part of a physical layer interface of the base die. As a result, the TMVs can provide a thermal pathway away from the PHY through the mold compound, peripheral to the memory dies.
A memory device can include a memory array coupled with control logic. The control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. The control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. The control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. The control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.
Methods, systems, and devices for a read-only memory (ROM) bank for storing bootup code are described. A dynamic random-access memory (DRAM) device may implement at least a portion of non-volatile memory within the DRAM device for storing bootup code and/or program code. Accordingly, a host system may, upon powering on the DRAM device, directly access the bootup code and/or program code from the portion of non-volatile memory in the DRAM device. In some examples, the portion of non-volatile memory may be a mask programmable bank from a set of banks or be an electrical programmable bank. Additionally, the portion of the non-volatile memory in the DRAM device may be implemented in under-array circuitry separate from a DRAM memory array, in a separate extra array beside the DRAM array, or in a separate die electrically coupled with the DRAM memory through silicon vias or other interconnects.
Methods, systems, and devices for access line division for memory devices are described. A memory array may include transistors that divide access lines (e.g., digit lines) into first portions associated with a first address range (e.g., a first range of word lines) and second portions associated with a second address range (e.g., a second range of word lines), such as along respective lengths of the access lines. When a memory cell in the first address range is accessed, transistors coupled with first access lines may be activated while transistors coupled with second access lines may isolate portions of the second access lines in the second address range. When a memory cell in the second address range is accessed, transistors coupled with the second access lines may be activated while transistors coupled with the first access lines may isolate portions of the first digit lines in the first address range.
In some implementations, a memory device may cache a subset of one or more block family error avoidance (BFEA) lookup tables associated with a block family associated with host data in a first memory location. The block family may be based on at least one of a time window during which the host data was written or a temperature window at which the host data was written. The memory device may receive a read command associated with host data and determine, based on the block family and the subset of the one or more BFEA tables, a threshold voltage offset associated with the host data. The memory device may compute a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the host data. The memory device may read, using the modified threshold voltage, the host data from the first memory location.
Apparatuses and techniques for implementing self-refresh status indications for self-refresh exit are described. To save power, a memory device can control refresh operations, but the memory device is typically unavailable in this self-refresh mode. During self-refresh exiting, the memory device typically remains unavailable for normal array access operations while concluding any refresh operations that are already in progress. Portions of the memory array, however, are usually not performing a refresh operation. To enable a host device to perform read and write operations on these available portions during the self-refresh exit time, the memory device provides an indication of a self-refresh status in example implementations. The indication can be a Boolean variable that pertains to an entire array. Alternatively, the indication can include multiple bits that respectively correspond to multiple portions, such as memory banks or bank groups. In this way, the host device can return to normal operations sooner.
A processing device in a memory system receives, from a host system, a reference clock signal and a reset signal. The processing device determines whether the reference clock signal satisfies a first initialization criterion and the reset signal satisfies a second initialization criterion. Responsive to determining that the reference clock signal and reset bit satisfy the respective initialization criteria, the processing device initializes a data transfer interface with the host system.
Memories might include an array of memory cells, a data line having a first data line segment selectively connected to a second data line segment and selectively connected to a plurality of memory cells of the array of memory cells, and a controller for access of the array of memory cells. The controller might be configured to cause the memory to selectively enable programming of a data state of a memory cell of the array of memory cells through a first connection to the first data line segment, and to read the data state of the memory cell through a second connection, different than the first connection, to the second data line segment.
Methods, systems, and devices for link startup sequence (LSS) mode detection for memory systems are described. A memory system may determine a duration between signals associated with a LSS and may use the duration to determine whether the LSS is associated with a first speed mode or a second speed mode. In some examples, the memory system may perform the LSS in accordance with the determined speed mode in response to determining that the duration satisfies a threshold. Performing the LSS may involve initializing the memory system. Further, the memory system may initiate a timer in response to receiving a first signal and may stop the timer in response to receiving a second signal and determining that a channel has transitioned from a first state to a second state. The speed mode may be a low speed LSS mode or a high speed LSS mode.
Semiconductor packages and/or assemblies having microchannels, a microchannel module, and/or a microfluidic network for thermal management, and associated systems and methods, are disclosed herein. The semiconductor package and/or assembly can include a substrate integrated with a microchannel and a coolant disposed within the microchannel to dissipate heat from a memory device and/or a logic device of the semiconductor package and/or assembly. The microchannel can be configured beneath the memory device and/or the logic device.
Track Memory Blocks of Varying Sizes using Logical Memory Regions of a Same size in a Memory Sub-System to Facilitate Access to a Storage Space of the Memory Sub-System
A memory sub-system having: random access memory cells configured to provide a memory space accessible, via a memory access protocol, by a host system located outside of the memory sub-system; and non-volatile memory cells configured to provide a physical storage space accessible, via a storage access protocol, by the host system. The memory sub-system can: allocate, from the memory space, a plurality of memory blocks of varying sizes; establish mapping between a plurality of logical memory regions of a same size in a logical memory space and the plurality of memory blocks respectively; buffer data, addressable by the host system via a logical block address in a logical storage space according to the storage access protocol, in a memory block among the plurality of memory blocks; and establish mapping between the memory block and the logical block address via the logical memory space.
Methods, systems, and devices for array stabilization in memory architectures are described. A memory device may include a first array region with a first block of memory cells and a first selection region. The memory device may include a second array region of the memory die with a second block of memory cells and a second selection region. The first and second selection regions may include respective sets of transistors that couple memory cells of the first block and the second block with various access lines. The memory device may include an electrical isolation region positioned between the first array region and the second array region. The electrical isolation region may include first dielectric material portions having a first width between the first selection region and the second selection region and second dielectric material portions having a second width between the first selection region and the second selection region.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
51.
CHARGE TRAPPING NOT OR (NOR) FLASH MEMORY ARCHITECTURES
Methods, systems, and devices for charge trapping not or (NOR) flash memory architectures are described. The devices described herein may implement a Fowler-Nordheim charge trapping NOR memory architecture. For example, a memory system may be manufactured that includes multiple NOR memory cells in a pier and pillar architecture. In such examples, the memory system may include multiple piers, where each pier may have a plurality of first cells at a first end of the pier and a plurality of second cells at a second end of the pier. Each pier may be positioned between a first pillar and a second pillar, where such pillars may be utilized to access the memory cells at each pier. In some examples, every other pillar may not include memory cells (e.g., may be a dielectric pillar), which may enable Fowler-Nordheim programming of the memory cells.
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
52.
LOGICAL TO PHYSICAL TRANSLATION TABLE ADAPTED TO FACILITATE TRACKING OF DATA OF A STORAGE SPACE OF A MEMORY SUB-SYSTEM CACHED OR BUFFERED IN A MEMORY SPACE OF THE MEMORY SUB-SYSTEM
A memory sub-system having: memory cells of a first type to provide a memory space; and memory cells of a second type to provide a physical storage space. A controller of the memory sub-system is configured to: store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; store, the memory space, a copy of a data portion addressable in the logical storage space; configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space; and store information to identify a location, in the memory space, at which the data portion is cached or buffered.
Hybrid semiconductor devices with backside power delivery networks and associated systems and methods are disclosed herein. In some embodiments, a hybrid semiconductor device includes an array wafer, interconnect structures, a CMOS wafer, and a power delivery network. The interconnect structures can be disposed on the array wafer. The CMOS wafer can be bonded to array wafer. The power delivery network can include a backside power delivery (BPD) layer and an electrical connector. The BPD layer can be bonded to the CMOS wafer. The electrical connector can (i) extend from at least one of the interconnect structures and past the array and CMOS wafers in a first direction, and (ii) extend through the BPD layer in a second direction. The electrical connector can be operably coupled to the CMOS wafer and configured to deliver power thereto from the at least one of the interconnect structures.
Methods, systems, and devices for split pillar memory architectures are described. A memory device may include a first pillar including a first dielectric material, a second pillar including the first dielectric material, and a third pillar positioned between the first pillar and the second pillar and including a second dielectric material. The memory device may also include a first portion of a first semiconductor material along a first side of the third pillar and a second portion of the first semiconductor material along a second side of the third pillar opposite the first side. The memory device may further include a first portion of a second semiconductor material positioned between multiple word lines and the first portion of the first semiconductor material and include a second portion of the second semiconductor material positioned between the multiple word lines and the second portion of the first semiconductor material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
55.
MULTI-WORDLINE PROGRAMMING WITH DATA LOSS PREVENTION
Various example embodiments provide for multi-wordline programming of a memory device with data loss prevention, which can be used by a memory sub-system. In particular, various example embodiments use a certain sequence of memory device commands to avoid multi-wordline data loss during cache programming of a memory device.
A system including: a compute express link fabric; a plurality of memory devices connected to the compute express link fabric; at least one processor connected to the compute express link fabric; and a main memory connected to the at least one processor. The system is configured to: identify a plurality of memory regions in the main memory and the plurality of memory devices; determine runtime latency to access the plurality of memory regions; identify, based on the runtime latency and among the plurality of memory regions, a first memory region as a source region; receive a memory allocation request; and allocate, in response to the memory allocation request, a chunk of random access memory from the source region.
An integrated circuit construction comprises conductive vias that are individually directly above and directly electrically coupled to individual operative transistors. Insulator islands individually extend upwardly from individual inoperative transistors. Insulating material surrounds individual of the insulator islands and individual of the conductive vias. Insulative material is directly above the insulating material. Conducting vias individually extend through the insulative material. Some of the conducting vias are directly above and directly against individual of the conductive vias. Another some of the conducting vias are directly above individual of the insulator islands. Other embodiments, including method, are disclosed.
Methods, systems, and devices for write booster buffer and hibernate are described. The memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. In some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. The memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. The memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a semiconductor substrate and an active region in the semiconductor substrate. The integrated assembly may include a first epitaxial structure on an upper surface of the semiconductor substrate, the first epitaxial structure having a first thickness in a first direction, and a second epitaxial structure on an upper edge of the semiconductor substrate, the second epitaxial structure having a second thickness in a second direction different than the first direction, where the second direction is oblique to the semiconductor substrate, and where the second thickness is less than the first thickness.
Methods, systems, and devices for array stabilization in memory architectures are described. A memory device may include a first array region with a first block of memory cells and a first selection region. The memory device may include a second array region of the memory die with a second block of memory cells and a second selection region. The first and second selection regions may include respective sets of transistors that couple memory cells of the first block and the second block with various access lines. The memory device may include an electrical isolation region positioned between the first array region and the second array region. The electrical isolation region may include first dielectric material portions having a first width between the first selection region and the second selection region and second dielectric material portions having a second width between the first selection region and the second selection region.
A method of forming a microelectronic device includes forming an etch-selective liner on a staircase structure having steps defined by preliminary tiers respectively including insulative material and sacrificial material. First openings are formed within a horizontal area of the staircase structure and vertically extending through the etch-selective liner and the preliminary tiers. The sacrificial material of the preliminary tiers are replaced with conductive material to form tiers respectively including the insulative material and the conductive material. Portions of the etch-selective liner horizontally adjacent to the first openings are laterally recessed to form second openings. The conductive contacts are within the second openings. The conductive contacts respectively includes a first portion vertically extending through the tiers and the etch-selective liner, and a second portion outwardly horizontally projecting from and unitary with the first portion.
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Methods, systems, and devices related to sense amplifiers of a memory device serving as a Static Random Access Memory (SRAM) cache. For example, a memory array can be coupled to sense amplifiers. In a first mode, the sense amplifiers can be electrically disconnect from digit lines of the memory array. In the first mode, data and metadata of a cache line can be stored in the sense amplifiers when electrically disconnected from the number of digit lines. In the first mode, a portion of the data can be communicated, based on the metadata, from the sense amplifiers to the processing device. In a second mode, the sense amplifiers can connect to the memory array and sense data from the memory array.
A microelectronic device includes a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers, the stack structure divided into blocks by filled slot structures, each of the blocks comprising: a memory array region; staircase structures having steps; and crest regions interposed in a first horizontal direction between horizontally neighboring pairs of the staircase structures, and contact structures within the first crest region of each of the blocks and vertically extending through the stack structure to a source tier underlying the stack structure, the contact structures comprising: first contact structures in electrical communication with control logic circuitry; and second contact structures electrically isolated from the control logic circuitry, at least some the first contact structures relatively more centrally positioned with each of the blocks in a second horizontal direction orthogonal to the first horizontal direction than at least some of the second contact structures.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
A printed circuit board (PCB) land pad for a three-pin metal–oxide–semiconductor field-effect transistor (MOSFET) component comprises four pads with a split pad for a drain terminal of the MOSFET component. The PCB land pad comprises: a first pad to connect a gate terminal of the MOSFET component to a PCB; a second pad to connect a source terminal of the MOSFET component to the PCB; a third pad corresponding to connect a drain terminal of the MOSFET component to the PCB; and a fourth pad to connect the drain terminal of the MOSFET component to the PCB.
A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Implementations described herein relate to memory device hardware host read actions based on lookup operation results. In some implementations, a memory device may include one or more components configured to receive, by a hardware component of the one or more components and from a host device, a request to read data. The hardware component may be configured to perform a first lookup operation to determine whether the data is associated with a write data entry in a cache memory. The hardware component may be configured to perform a second lookup operation associated with an address of the data in a memory, where the second lookup operation is performed irrespective of a first result of the first lookup operation. The hardware component may be configured to perform one or more actions based on the first result and a second result of the second lookup operation.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
67.
MODIFICATION OF CERAMIC CAPACITOR FOR MITIGATION OF DELAMINATION IN MEMORY DEVICES
An apparatus includes a ceramic capacitor comprising a ceramic component and one or more metal components; and an encapsulation layer that encapsulates the ceramic capacitor from an external environment, wherein at least one surface of the ceramic component of the ceramic capacitor is finished to strengthen a bond capability between the at least one surface and the encapsulation layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 1/68 - Capacitors having no potential barriers
68.
SEMICONDUCTOR WAFERS WITH BURIED CONNECTORS AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor device assemblies including one or more semiconductor wafers with buried connectors and associated systems and methods are disclosed herein. In some embodiments, a semiconductor wafer includes one or more dielectric layers defining a frontside and a backside of the semiconductor wafer, integrated circuitry formed on or within the dielectric layers, and an array of connectors formed within the dielectric layers. The array of connectors can be arranged in a geometric pattern. Individual ones of the array of connectors can be oriented along a direction extending between the frontside and the backside of the semiconductor wafer. A first subset of the array of connectors can be exposed at least one of the frontside or the backside of the semiconductor wafer. A second subset of the array of connectors can be fully embedded in the one or more dielectric layers.
High-voltage semiconductor devices with extended active areas (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a high-voltage semiconductor device includes a high-voltage N-well formed in a substrate. The high-voltage N-well includes a mask edge corresponding to a location of an N-well junction formed in the substrate. The device further includes (i) an active area and (ii) a local deep trench isolation region positioned within the substrate and laterally adjacent to the high-voltage N-well. The active area can extend beyond the mask edge of the high-voltage N-well such that a region of the active area is positioned between the mask edge of the high-voltage N-well and the local deep trench isolation region. The extended active area is expected to improve breakdown voltage characteristics of the device when using local deep trench isolation.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Methods, systems, and devices for replacement policy for access granularity in memory subsystems are described. The memory system may include one or more extra capacity dies configured to store corrected data from failed memory dies. A failed memory die may include a threshold quantity of errors. The memory system may identify one or more failed memory dies and may correct errors in the stored data using a data correction scheme supported by the memory system. The memory system may select at least one extra capacity die and may write the corrected data to the selected extra capacity die. The memory system may write null data in the failed memory die to replace the data including the errors. The extra capacity die may thereby act as a replacement for at least a portion of the failed memory die.
An apparatus includes: a substrate having first conductivity type; a through-silicon via going through from the top surface to the bottom surface of the substrate; an insulating film surrounding a side surface of the through-silicon via; a first well having second conductivity type in a top portion of the substrate; and a second well having first conductivity type just below the first well in the substrate; wherein one side of the first well and the second well is substantially in contact with the insulating film.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 62/60 - Impurity distributions or concentrations
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
Methods, systems, and devices for techniques for reducing or preventing data knock out are described. A memory device includes an array of memory cells; data lines coupled to the array of memory cells; one or more sense amplifiers coupled to the data lines; and a memory controller. The memory controller is configured to perform, for data sensing operations comprising sensing at least at a first sensing level and a second sensing level: causing precharging of the data lines, causing the one or more sense amplifiers to sense, at the first sensing level, the data lines to obtain data stored in the array of memory cells, and keeping the data lines pre-charged even if at least one of the data lines is not sensed at the second sensing level.
Methods, systems, and devices for techniques for boosting bit line voltage biasing. A memory device includes bit lines and controller. The controller, during a program operation of strings of memory cells, identifies, based on a characteristic corresponding to the bit lines, first and second bit line groups. The controller, during the program operation, causes the first bit line group to receive a voltage at a first voltage level. The controller, during the program operation, causes the first bit line group to transition to a floating state such that the first bit line group is electrically isolated. The controller, during the program operation, causes the second bit line group to receive the voltage at the first voltage level. The first and second bit line groups are capacitively coupled such that the voltage level of the first bit line group is boosted from the first voltage level to a second voltage level.
Some embodiments of the disclosure provide a method for forming cell contacts of a memory device, the method comprising forming two layers in a plurality of gaps for separation of cell contacts, wherein the two layers include a first layer on surfaces of the gaps and a second layer on the first layer, the second layer filling the gaps covered by the first layer. The second layer separates cell contacts formed in cell contact halls from each other. The method effectively achieves sufficient separation of the cell contacts while at the same time achieving the sufficient cell contacts size to prevent or mitigate defects due to high resistance of the cell contacts.
Methods, systems, and devices for charge trapping not or (NOR) flash memory architectures are described. The devices described herein may implement a Fowler-Nordheim charge trapping NOR memory architecture. For example, a memory system may be manufactured that includes multiple NOR memory cells in a pier and pillar architecture. In such examples, the memory system may include multiple piers, where each pier may have a plurality of first cells at a first end of the pier and a plurality of second cells at a second end of the pier. Each pier may be positioned between a first pillar and a second pillar, where such pillars may be utilized to access the memory cells at each pier. In some examples, every other pillar may not include memory cells (e.g., may be a dielectric pillar), which may enable Fowler-Nordheim programming of the memory cells.
H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
This disclosure is directed to a system for high efficiency storage in high capacity non-volatile solid state applications. The system includes a memory device and a processing device operatively coupled to the memory device. The processing device performs operations including receiving a request to program data, storing the data by default in a first type of storage with multi-level memory cells having a first number of levels, and bypassing a second type of storage with fewer levels. Upon detecting a condition, the processing device transfers the data to a third type of storage with a greater number of levels than the first type. This method optimizes storage efficiency and performance by dynamically managing data storage based on the portion of user logical block addresses that contain user data.
A memory device comprises memory and control circuitry. The control circuitry can receive a command to access the memory. Responsive to receiving the command to access the memory, the control circuitry can provide command data of the command to pipe latch circuitry and error correction code (ECC) circuitry. The memory device further includes pipe latch circuitry to receive command data of the command from the control circuitry and maintain the command data for a period of time of a duration longer than error calculation time of the ECC circuitry.
Methods, systems, and devices for techniques to balance log structured merge trees are described. A computing system may rebalance a tree structure having an ordered set of leaf nodes by splitting or joining leaf nodes of the tree structure. To split a leaf node, the computing system may select a key to evenly partition key and value data stored in the leaf. The computing system may place each key block of the leaf node having keys less than or equal to the selected key in a first new leaf node, and may place each key block of the leaf node having keys greater than the selected key in a second new leaf node. To join leaf nodes of the tree structure, the computing system may place each key block and each value block of the leaf node and the adjacent leaf node in a new leaf node.
Methods, systems, and devices for minimum memory clock estimation procedures are described. For instance, a device, such as a host device, may truncate a value of a first parameter associated with a first duration for a clock coupled with a memory array to perform a clock cycle and may determine a value of a second parameter that is inversely proportional to a combination of the truncated first parameter and a correction factor. The device may determine a quantity of clock cycles associated with a second duration for accessing one or more memory cells of the memory array based on adjusting a third parameter associated with the second parameter. The device may access the one or more memory cells of the memory array based on the determined quantity of clock cycles.
Methods, systems, and devices for write buffer flush techniques are described. A memory system may be triggered to flush (e.g., transfer, write) data from a volatile memory device to a non-volatile memory device of the memory system. The memory system may support flushing data to blocks including single level cells (SLCs) or blocks including multiple-level memory cells. The memory system may determine whether a quantity of the data to be flushed satisfies a threshold quantity of data. If the quantity of data fails to satisfy the threshold quantity of data, the memory system may flush the data to a block including SLCs, which may be referred to as a small chunk SLC cursor. The SLC cursor may temporarily store the flushed data, such as at least until the threshold quantity of data is satisfied in the volatile memory device and/or to data recovery in case of a power loss event.
A device for deep learning acceleration with mixed precision may include a first data port configured to receive a map data segment and a second data port configured to receive a kernel data segment. The device may include a precision mode port configured to receive an indication of an input precision mode that indicates a word length for the map data segment and for the kernel data segment. The device may include a multiplier component configured to generate a multiplier component output based on the input precision mode and based on multiplying the map data segment and the kernel data segment. The device may include an adder component configured to generate an adder component output based on the input precision mode and based on the multiplier component output. The device may include an output port configured to output the adder component output.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
82.
CHARGE TRAPPING NOR FLASH MEMORY FOR STACKED MEMORY ARCHITECTURES
Methods, systems, and devices for charge trapping not-OR (NOR) flash memory for stacked memory architectures are described. A memory device may include one or more three-dimensional (3D) charge trapping NOR flash memory dies in a stack of memory dies. In some examples, the stack of memory dies may also include one or more volatile memory dies, while in other examples the stack of memory dies may primarily include charge trapping NOR memory dies. The stack of memory dies may also include a logic die configured to access each of the memory dies of the stack using one or more vias, channels, or other components associated with the stack. In some examples, the logic die may access the memory dies of the stack in response to an access command received from a graphics processing unit (GPU) or other processing circuitry of the memory device.
Methods, systems, and devices for host-side alignment to a multi-phase internal clock of a memory system are described. An apparatus may be configured to implement host-side alignment to a multi-phase internal clock of the memory system. Techniques to implement host-side alignment may include a host system issuing a synchronization pattern to the memory system. The memory system may, based on the synchronization pattern, provide a return mapping that indicates a degree of alignment between a clock of the host system and phases of a multi-phase internal clock of the memory system. Based on the indication, the host system may implement a timing offset that synchronizes the host system with the memory system, thereby enabling information that is subsequently transmitted from the host system to be decoded by the memory system.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the methods includes: a structure including a conductive region; first memory cells and first control gates associated with the first memory cells located over the structure; second memory cells and second control gates associated with the second memory cells located over the structure; and a dielectric structure between the first memory cells and the second memory cells and separating the first control gates from the second control gates. The dielectric structure extends into the conductive region and includes a liner adjacent a portion of the conductive region. The liner includes a dielectric constant different from a dielectric constant of silicon dioxide.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
85.
Memory Circuitry And Methods Used In Forming Memory Circuitry
Memory circuitry comprises vertically alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor and a capacitor electrically coupled therewith. Immediately-x-direction-adjacent channel regions of the transistors that are in the same memory-cell tier have facing z-direction sides that oppose one another in the x-direction. Insulating material is horizontally between the immediately-x-direction-adjacent channel regions. The insulating material is directly against the z-direction sides of the immediately-x-direction-adjacent channel regions and extends horizontally continuously there-between along the x-direction. Other embodiments, including method, are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. The insulative tiers comprise insulative material that is vertically between immediately-vertically-adjacent of the memory-cell tiers. A portion of the insulative material is laterally beyond digitline-side edges of access lines vertically between insulator material that is in the immediately-vertically-adjacent memory-cell tiers between immediately-x-direction-adjacent digitlines. In such circuitry, (b) is being less than (a), where (a): minimum horizontal distance between the gate insulator of immediately-horizontally-x-direction-adjacent horizontal transistors and (b): minimum vertical thickness of the insulator material where vertically between the portions of the insulative material of immediately-vertically adjacent insulative tiers. Methods are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. Immediately-vertically-adjacent of the memory-cell tiers comprise an upper memory-cell tier and a lower memory-cell tier. The insulative tiers comprise an insulator that is vertically between the immediately-vertically-adjacent memory-cell tiers. The insulator comprises a void-space that is vertically between the gate of the upper memory-cell tier and the gate of the lower memory-cell tier. Methods are disclosed.
Memory circuitry comprises vertically-alternating insulative tiers and memory-cell tiers. Memory cells in the memory-cell tiers individually comprise a horizontal transistor having a gate, a capacitor side, and a digitline side. A capacitor is electrically coupled with the horizontal transistor on the capacitor side. A digitline is electrically coupled with the horizontal transistor on the digitline side. A void-space is in individual of the memory-cell tiers laterally between the digitline and the gate. Other embodiments, including method, are disclosed.
In some implementations, a memory apparatus may obtain, from a host system, a first message comprising data and link parity information associated with the data. The memory apparatus may determine that the data includes one or more errors based on the link parity information. The memory apparatus may store a first value indicating that the data includes the one or more errors. The memory apparatus may provide, as part of a read request for the data, a second message comprising the data and a second value, the second value indicating that the data includes the one or more errors.
Systems and methods include a memory device that includes an internal voltage generator configured to receive a voltage level setting. The internal voltage generator also is configured to generate an internal voltage based at least in part on the voltage level setting. The memory device also includes ZQ calibration circuitry that is configured to receive the internal voltage from the internal voltage generator and to perform ZQ calibration using the received internal voltage.
Stealth wafer separation techniques for wafer-to-wafer bonding (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a method comprises creating, using an infrared (IR) laser, dislocations in a first wafer that delineate a first portion of the first wafer from a second portion of the first wafer; (b) bonding the first portion of the first wafer to a second wafer; and (c) separating the second portion of the first wafer from the first portion generally along the dislocations. The dislocations can include (i) a first array of dislocations that is vertically oriented with respect to the first wafer and/or (ii) a second array of dislocations that is horizontally oriented with respect to the first wafer. The dislocations can be created before or after bonding the first wafer to the second wafer.
Methods, systems, and devices for host-side alignment to a multi-phase internal clock of a memory system are described. An apparatus may be configured to implement host-side alignment to a multi-phase internal clock of the memory system. Techniques to implement host-side alignment may include a host system issuing a synchronization pattern to the memory system. The memory system may, based on the synchronization pattern, provide a return mapping that indicates a degree of alignment between a clock of the host system and phases of a multi-phase internal clock of the memory system. Based on the indication, the host system may implement a timing offset that synchronizes the host system with the memory system, thereby enabling information that is subsequently transmitted from the host system to be decoded by the memory system.
Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.
Methods, systems, and devices for charge trapping not-OR (NOR) flash memory for stacked memory architectures are described. A memory device may include one or more three-dimensional (3D) charge trapping NOR flash memory dies in a stack of memory dies. In some examples, the stack of memory dies may also include one or more volatile memory dies, while in other examples the stack of memory dies may primarily include charge trapping NOR memory dies. The stack of memory dies may also include a logic die configured to access each of the memory dies of the stack using one or more vias, channels, or other components associated with the stack. In some examples, the logic die may access the memory dies of the stack in response to an access command received from a graphics processing unit (GPU) or other processing circuitry of the memory device.
An example apparatus includes a first wiring layer including a first wiring pattern having a first end and a second end, a second wiring layer located above the first wiring layer and including a second wiring pattern and a third wiring pattern having a third end, a first via conductor coupled between the first end of the first wiring pattern and the second wiring pattern, and a second via conductor coupled between the second end of the first wiring pattern and the third end of the third wiring pattern. At least a part of the third wiring pattern extends along the first wiring pattern so as to overlap the first wiring pattern.
Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads.
Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads.
Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.
Methods, systems, and devices for selective cavity merging for isolation regions in a memory die are described. For example, formation of material structures of a memory die may include depositing a stack of alternating layers of a first material and a second material over a substrate of the memory die, forming a pattern of cavities through the stack of alternating material layers, and forming voids between layers of the first material based on removing portions of the second material. An electrical isolation region may be formed between portions of the memory die based on depositing a dielectric material in at least some of the cavities and in at least a portion of the voids between the layers of the first material.
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
During a command bus training, the bus training circuitry can receive data from a bus and latch the data at the first plurality of flip-flops. The bus training circuitry can also provide the data from the first plurality of flip-flops to the XOR circuitry and provide the data from the XOR circuitry to the second plurality of flip-flops. The bus training circuitry can further latch the data at the second plurality of flip-flops and sample the data from the second plurality of flip-flops for training of a timing of the bus.
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
Methods, systems, and devices for dynamic parity group management for memory are described. In some instances, a first set of parity bits may be generated for a first group of pagelines and may be stored to a memory system. The memory system may detect a condition (e.g., a data recovery condition) associated with a first page of the first group of pagelines and may move the data to a second page. The memory system may generate a second set of parity bits using the first set of parity bits and a representation of the data stored to the first page. In some examples, the memory system may determine that a third page of the first group of pagelines includes an error (e.g., an uncorrectable error) and may recover the associated data using the second set of parity bits.
A system and method for reducing peak power and improving performance during data transfers on a communication bus are disclosed. The system includes a staggering controller within a system controller that manages the timing of data transfers across multiple channels by enforcing a programmable timeout between the initiation of transfers. This approach mitigates the adverse effects of simultaneous data transfers, such as transient currents, by spreading out the current demand over time. In some examples, the timing window may be dynamically adjusted based on operational metrics like temperature and power consumption.
