A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.
Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material, and the channel material includes a second, different material.
G11C 5/12 - Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
6.
APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATION
Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
7.
FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE
Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.
A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.
Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.
A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method for modifying a geometry of a wafer comprises measuring a local geometry for each of a plurality edge locations of the wafer, determining, based on the measured local geometry, an amount of additional material for each of the plurality of locations of the wafer calculated to provide a desired wafer-level geometry for the wafer, and dispensing, from a printing nozzle, the determined amount of additional material at each of the plurality of locations of the wafer to provide the wafer with the desired wafer¬ level geometry.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/66 - Testing or measuring during manufacture or treatment
15.
Integrated Assemblies and Methods of Forming Integrated Assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
16.
MONOLITHIC CONDUCTIVE COLUMNS IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, a first abrupt power-loss (APL) switch, a second APL switch, and one or more power hold-off capacitors. The system may include a third APL switch between the battery and the power hold-off circuit. The third APL switch and the first APL switch may be in a closed state, and the second APL switch may be connected to the step-up regulator, when a voltage from the battery satisfies a voltage threshold. The third APL switch and the first APL switch may be in an open state, and the second APL switch may be connected to the step-down regulator, when the voltage from the battery does not satisfy the voltage threshold.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.
A wafer carrier assembly comprising a wafer carrier having a first and second side, the first side including: a circular recess configured to receive a semiconductor device wafer, and at least one cut-out arranged along the circumference of the circular recess. The first side also includes a carrier cover having a top and bottom side, the top side including: a plurality of gridlines extending to edges of the carrier cover, and a plurality of reticles extending from the top side to the bottom side where subsets of reticles are arranged to have a common center and each subset of reticles is arranged at each intersection of the plurality of gridlines.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
G03F 1/44 - Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
20.
STACKED SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR DIES OF VARIABLE SIZE
A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
21.
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND METHODS OF FORMING MICROELECTRONIC DEVICES
A microelectronic device including first insulative structures, each first insulative structure including first sections individually having a first horizontal width in a first direction, and second sections horizontally alternating with the first sections in a second direction orthogonal to the first direction, the second sections individually having a second horizontal width in the first direction greater than the first width. First conductive structures are directly adjacent the first sections of the first insulative structures in the first direction and directly adjacent the second sections of the first insulative structures in the second direction. Second insulative structures are directly adjacent the first conductive structures and the second sections of the first insulative structures in the first direction; and second conductive structures are directly adjacent the second insulative structures in the first direction.
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
24.
HYBRID MOLD CHASE SURFACE FOR SEMICONDUCTOR BONDING AND RELATED SYSTEMS AND METHODS
Mold chases for molding semiconductor devices and/or components of semiconductor devices, the resulting semiconductor devices and/or their components, and related systems and methods are disclosed herein. In some embodiments, the mold chase includes a first clamp and a second clamp having a substrate engaging surface oriented towards the first clamp. The substrate engaging surface can have a hybrid surface texture that includes a first region and a second region at adjacent the first region (on a lateral side of the first region). The first region can include a first surface texture that is relatively smooth. The second region can include a second surface texture that is relatively rough compared to the first surface texture. The first surface texture can prevent mold bleed during a molding process. The second surface texture can reduce electrostatic discharge events during an ejection from the mold chase.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
25.
METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
A processing unit can include an activation function unit. Data can be received at a plurality of registers of a processing unit of a memory sub-system. The data can be received at a multiply-accumulate (MAC) unit coupled to the plurality of registers. The first plurality of operations can be performed at the MAC unit to generate a first output. The first output can be provided to the activation function unit. The first output can be provided from the AFU to the plurality of registers utilizing a bus or a signal line that couples the plurality of registers to the AFU.
Systems, methods, and apparatus for a memory device having test mode state machines configured to perform self-testing. In one approach, a memory array has memory cells. Periphery logic of the memory device receives a command from a host device to initiate self-testing. The periphery logic generates trigger signal(s) in response to receiving the command. Control circuitry (e.g., a controller) has state machine(s) that receives the trigger signal(s) and initiates execution of a command sequence. The command sequence includes various orders of operations such as read, write, or delay. A state machine can be integrated into each of multiple partitions of the memory array.
Apparatuses and methods for performing read operations on partially programmed blocks are provided. One example apparatus can include a controller configured to apply a read voltage to the first inner word line in the array of memory cells during a read operation on the first inner word line, apply a first pass voltage to a second inner word line adjacent to the first inner word line and to a third inner word line adjacent to the first inner word line, apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells in response to determining the read request is for data stored on the first inner word line of the partially programmed block, and apply a third pass voltage to a first number of inner word lines of the number of word lines that are nonadjacent to the first inner word line.
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
The present disclosure includes apparatuses, methods, and systems for partitioning system data from user data in memory. In an example, a method can include receiving system data at a memory, assigning the system data a first address within a first range of memory addresses, storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses, receiving user data, assigning the user data a second address within a second range of memory addresses, and storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user having the second address within the second range of addresses.
Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/14 - Protection against unauthorised use of memory
G11C 8/20 - Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
33.
ELECTRONIC DEVICES INCLUDING STACKS INCLUDING CONDUCTIVE STRUCTURES ISOLATED BY SLOT STRUCTURES
An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
34.
LOGICAL BLOCK CONSTRUCTION FOR PHYSICAL BLOCKS COMPRISING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.
Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/528 - Layout of the interconnection structure
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
37.
USE MODEL STATISTICS STORAGE IN A MEMORY SUBSYSTEM
Methods, systems, and apparatuses include determining, by a memory subsystem, use model statistics for a memory portion of the memory subsystem, where the use model statistics include a count of commands received by the memory subsystem from a host system targeting the memory portion and details about the memory subsystem. It is determined that the memory subsystem is powering down. The use model statistics are stored in a use model statistics storage of the memory subsystem by the memory subsystem in response to determining that the memory subsystem is powering down.
A variety of applications can include a memory device having an array of memory cells, with each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. Access lines can be coupled to gates of the GAA transistors and digit lines can be coupled to pillar channels of the GAA transistors. A lattice can be included between the access lines and the digit lines, where the lattice has dielectric regions between and contacting non-dielectric regions. Each non-dielectric region can be positioned on and contacting a digit line and can contain digit contact junctions to the pillar channels of a set of the GAA transistors extending from the non-dielectric region. Additional devices and methods are disclosed.
A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is separated from an adjacent digit line by an airgap. Additional devices and methods are disclosed.
A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is wrapped on a sidewall of an active area of each GAA transistor of the second set. Additional devices and methods are disclosed.
In some implementations, the techniques described herein relate to a system including: an operating system; and a trusted execution environment including a controller and a write-protected storage area, wherein the controller is configured to: receive a command to modify access to trace functionality provided by the operating system, validate the command using a public key stored in the write-protected storage area, and update a register accessible by the operating system based on the command in response to validating the command, wherein the operating system is configured to allow or disallow access to trace functionality based on contents of the register.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
G06F 21/33 - User authentication using certificates
Methods, systems, and apparatuses for a memory device (e.g., DRAM) including a directed error check and scrub (ECS) procedure are described. The directed ECS procedure may include read-modify-write cycles when errors are detected in code words. In some embodiments, the memory device may perform the directed ECS procedure on a code word in which an error was previously detected (for example, in response to a read command). The directed ECS procedure described herein may facilitate correcting code word errors before too many errors, exceeding the detection and/or correction capabilities of the memory device, accumulate in the code words.
A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and an epoxy material disposed on at least one sidewall of the stack of upper semiconductor dies, wherein the epoxy material has a different material composition to the NCF material.
Apparatuses and techniques for logging a memory address associated with faulty usage-based disturbance data are described. In an example aspect, a memory device can detect, at a local-bank level, a fault associated with usage-based disturbance data. This detection enables the memory device to log a row address associated with the faulty usage-based disturbance data. To avoid increasing a complexity and/or a size of the memory device, some implementations of the memory device can perform the address logging at the multi-bank level with the assistance of an engine, such as a test engine. The memory device stores the logged address in at least one mode register to communicate the fault to a memory controller. With the logged address, the memory controller can initiate a repair procedure to fix the faulty usage-based disturbance data.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers of respective memory cells and control gates, the tier located one over another over a substrate, the control gates including a control gate closest to the substrate, the control gates including respective portions forming a staircase structure; conductive contacts contacting the control gates at a location of the staircase structure, the conductive contacts including a conductive contact contacting the control gate; a dielectric structure located on sidewalls of the control gates; and support structures adjacent the conductive contacts and having lengths extending vertically from the substrate, the support structures including a support structure closest to the conductive contact, the support structure located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure over the distance is ranging from 1.6 to 2.0.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner.
A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.
H01L 21/66 - Testing or measuring during manufacture or treatment
B41M 5/00 - Duplicating or marking methodsSheet materials for use therein
B41M 7/00 - After-treatment of printed works, e.g. heating, irradiating
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/36 - Data generation devices, e.g. data inverters
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.
Methods, systems, and devices for using a backup capacitor as an alternate energy source via dynamic APL budgeting are described. A memory system may use excess power available at an energy storage device such as a backup capacitor to improve performance under various circumstances. The amount of power reserved for the APL may be dynamically determined based on various conditions of the memory system. The energy reserved for APL recovery may be dynamically budgeted so that excess energy from the energy storage device may be used to improve operations. The energy storage device may be recharged using surplus power when the amount of energy required for operations at the SSD is less than the maximum power budget for the SSD.
A semiconductor device is presented. The semiconductor device includes a lower semiconductor die, a stack of upper semiconductor dies disposed over the lower semiconductor die, a top semiconductor die disposed over the stack of upper semiconductor dies, a non-conductive film material disposed between adjacent semiconductor dies of the lower semiconductor die and the stack of upper semiconductor dies, and a mold compound material disposed between the top semiconductor die and the stack of upper semiconductor dies, and on sidewalls of the stack of upper semiconductor dies and the top semiconductor die.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
56.
FLEXIBLE SUB-CHANNEL SELECTION IN A SHARED COMMUNICATION CHANNEL
A system performs operations including: storing a first value in a first memory location used for selecting a sub-channel of a plurality of sub-channels in a communication channel, each of the plurality of sub-channels corresponding to one or more memory components of a plurality of memory components of the memory device, wherein the first value specifies that a sub-channel selecting function is enabled; receiving, through the communication channel, a command directed to the memory device; responsive to receiving the command, storing a second value in a second memory location, wherein the second value is obtained from the command; determining that the second value matches a third value stored in a third memory location, wherein the third value stored in the third memory location comprises a preset value corresponding to a first component of the plurality of components of the memory device; and executing, by the first component, the command.
A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.
A method for modifying a geometry of a wafer comprises measuring a local geometry for each of a plurality edge locations of the wafer, determining, based on the measured local geometry, an amount of additional material for each of the plurality of locations of the wafer calculated to provide a desired wafer-level geometry for the wafer, and dispensing, from a printing nozzle, the determined amount of additional material at each of the plurality of locations of the wafer to provide the wafer with the desired wafer-level geometry.
Methods, systems, and devices for error detection signaling are described. In some examples, a memory device may include circuitry to detect one or more error conditions. As the memory device is operated, it may store or output a value (e.g., a high value, a “1”) indicating the absence of an error condition. Upon the occurrence of an error condition, the memory device may either store or output a value (e.g., a low value, a “0”), which may allow for the error to be corrected or mitigated. Because storing or driving the value signifying the error condition may require a driver of the memory device to be coupled with a power supply, storing or outputting the value signifying an absence of an error condition (e.g., unless a normal or valid condition is detected) may mitigate errors that would otherwise render a safety mechanism of the memory device ineffective.
A memory device to determine a voltage optimized to read a group of memory cells. In response to a command, the memory device reads the group of memory cells at a plurality of test voltages to determine a set of signal and noise characteristics of the group of memory cells. The memory device determines or recognizes a shape of a distribution of the signal and noise characteristics over the plurality of test voltages. Based on the shape, the memory device selects an operation in determining an optimized read voltage of the group of memory cells.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 29/50 - Marginal testing, e.g. race, voltage or current testing
61.
BLOCK ALLOCATION AND ERASE TECHNIQUES FOR SEQUENTIALLY-WRITTEN MEMORY DEVICES
A reset counter associated with a zone of the memory device is maintained. The reset counter represents a number of times the zone has been reset. In response to receiving a write command directed to the zone of the memory device, a target portion of the zone that is not open is identified. A first portion from a free portion list is identified. The program erase count of the first portion corresponds to the reset counter associated with the zone. The first portion is allocated to the zone.
Embodiments of the disclosure are drawn to apparatuses and methods for row hammer counter resets. Repeated access to an aggressor word line may cause increased data degradation in nearby victim word lines of the memory. The access count value of a given word line may be stored in counter memory cells positioned along that word line. The count values may be randomly or pseudo-randomly initialized. In some examples, a memory device may utilize residual charges that are present on the counter cells during start-up to initialize the counter memory cells. In some other examples, a memory device may utilize threshold voltage compensation (VtC) settings at start-up to initialize the counter memory cells. In some other examples, a memory device may utilize a combination of the residual charges that are present on the counter cells and VtC settings on start-up to initialize the counter memory cells.
Various embodiments provide for dynamically enabling and disabling foreground scans of blocks of a memory device, which can be part of a memory sub-system. For instance, some embodiments provide an improved methodology for triggering foreground media scans of blocks of a memory device without disturbing a maximum idea time of background media scans of blocks of the memory device.
A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. Digit lines to the memory cells can be arranged angled relative to the set of access lines at an angle different from ninety degrees. Digit shield lines can be structured between adjacent digit lines. The memory device can be arranged in a wafer-to-wafer interconnect architecture with the array on an array wafer connected to and below a control circuitry wafer in a circuit over array architecture.
H10B 12/00 - Dynamic random access memory [DRAM] devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Implementations described herein relate to various semiconductor device assemblies. In some implementations, semiconductor device assembly includes a first redistribution layer and a second redistribution layer, a first semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the first redistribution layer, and a second semiconductor die disposed between the first redistribution layer and the second redistribution layer and connected to the second redistribution layer. The first semiconductor die may have an active surface and a back surface opposite the active surface of the first semiconductor die. The second semiconductor die may have an active surface and a back surface opposite the active surface of the second semiconductor die. The second semiconductor die may be stacked on the first semiconductor die with the back surface of the second semiconductor die facing the back surface of the first semiconductor die.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Systems and methods for retaining data related to a detected collision are disclosed including receiving vehicle information from a sensor, receiving information about one or more other vehicles using a communication circuit, receiving an indication of a detected collision, and responsive to the received indication of the detected collision, storing information corresponding to the detected collision from a collision reenactment period in non-volatile memory of the first vehicle and broadcasting the information corresponding to the detected collision using the communication circuit.
G07C 5/00 - Registering or indicating the working of vehicles
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
Programming data in memory is described herein. An example apparatus includes an array of memory cells having a plurality of access lines to which the cells are coupled, and a processing device that performs a program operation on the array, including programming data to be stored in one page of cells of the array to the cells of the array coupled to a first one of the access lines, programming additional data to be stored in that page to the cells of the array coupled to a second one of the access lines adjacent to the first one of the access lines, sensing the data programmed to the cells of the array coupled to the first one of the access lines, and programming data to be stored in two pages of cells of the array to the cells of the array coupled to the first one of the access lines.
Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a first wafer having a front surface and a back surface opposite the front surface, and a second wafer having upper surface coupled to the back surface of the first wafer. The first wafer can also include one or more first alignment features. Each of the first alignment feature(s) can include a transparent material extending from the front surface to the back surface, thereby forming a window through the first wafer, allowing the location of conductive features on the front surface to be determined from the back surface using optical measurements. The second wafer can include one or more second alignment features that are positioned within a longitudinal footprint of a corresponding one of the first alignment features.
Apparatuses and techniques for handling faulty usage-based-disturbance data are described. In an example aspect, a memory device uses a report flag to indicate that an address of a row that corresponds to the faulty usage-based-disturbance data is logged at a global-bank level and is accessible by a host device. The report flag also enables the memory device to avoid reporting another error until the host device has cleared information associated with a previously-reported error. In another example aspect, the memory device temporarily prevents usage-based-disturbance mitigation from being performed based on the faulty usage-based-disturbance data. This means that if the faulty usage-based-disturbance data would otherwise trigger refreshing of one or more rows that are proximate to the row corresponding to the faulty usage-based-disturbance data, the memory device does not perform these refresh operations. This is beneficial by conserving resources for refreshing victim rows that are identified based on valid usage-based-disturbance data.
A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.
Various embodiments provide for dynamically enabling and disabling foreground scans of blocks of a memory device, which can be part of a memory sub-system. For instance, some embodiments provide an improved methodology for triggering foreground media scans of blocks of a memory device without disturbing a maximum idea time of background media scans of blocks of the memory device.
Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a first wafer having a front surface and a back surface opposite the front surface, and a second wafer having upper surface coupled to the back surface of the first wafer. The first wafer can also include one or more first alignment features. Each of the first alignment feature(s) can include a transparent material extending from the front surface to the back surface, thereby forming a window through the first wafer, allowing the location of conductive features on the front surface to be determined from the back surface using optical measurements. The second wafer can include one or more second alignment features that are positioned within a longitudinal footprint of a corresponding one of the first alignment features.
A processing device in a memory sub-system determines that an amount of host data in a first portion of a memory device configured as a program buffer satisfies a buffer threshold criterion and initiates an initial program pass of first host data from the program buffer to a second portion of the memory device configured as a primary memory. The processing device further determines that the first host data is to be evicted from the program buffer, and initiating a final program pass of the first host data from the program buffer to the primary memory.
Apparatuses and methods for per-row count based refresh target identification with sorting. A memory includes a number of word lines each associated with a row address and a count value. A targeted refresh queue stores the highest count values and their row addresses as an ordered list. For example the list may be sorted from highest count value to lowest count value. During a targeted refresh operation, the row address at a top of the queue is used for refresh operations and removed from the queue. When a row and count value are added to the queue, the queue is re-sorted.
Apparatuses and methods per row activation counter testing (PRACT). A memory includes an aggressor detector circuit, which determines a row address to be an aggressor address after the row address is accessed a number of times. In a normal mode the address is an aggressor after a first number of activations, while in a PRACT mode the address is an aggressor after a second (generally lower) number of activations. For example, when the row is accessed a first value may be added to a count in the normal mode and a second (generally larger) value in the PRACT mode. When the count crosses a threshold, the row is an aggressor.
Memories might include a plurality of strings of series-connected memory cells, each corresponding to a respective digit of a plurality of digits of a multiplicand, and might further include a controller configured to cause the memory to generate respective current flows through the plurality of strings of series-connected memory cells for each digit of a plurality of digits of a multiplier having respective current levels indicative of values of each digit of the plurality of digits of the multiplier times the multiplicand, to convert the respective current levels to respective digital values indicative of the values and magnitudes of each digit of the plurality of digits of the multiplier times the multiplicand, and to sum the respective digital value of each digit of the plurality of digits of the multiplier.
The present disclosure includes apparatuses and methods related to receiving, by a System-on-Chip (SoC) device, a command sequence and predicting a thermal event that likely corresponds to the received command sequence. The command sequence may include an instruction code that can be representative of a mode of operation of a vehicle. In one embodiment, a thermal model may be used to predict the likely thermal event that corresponds to the command sequence. A thermal option may then be implemented to address adverse thermal effects of the predicted thermal event.
An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.
A semiconductor device assembly includes a circuit substrate comprising a first substrate surface and a second substrate surface arranged opposite to the first substrate surface; at least one die arranged on the first substrate surface; a package casing disposed over the first substrate surface, wherein the package casing encapsulates the at least one die and covers at least part of the first substrate surface; and a multi-alloy ball grid array coupled to the second substrate surface. The multi-alloy ball grid array includes a first plurality of solder balls made of a first solder alloy and a second plurality of solder balls made of a second solder alloy that is different from the first solder alloy.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Methods, systems, and devices for memory block utilization in memory systems are described. A system configured to allow a memory device to group or segment a memory block into two or more sub-memory blocks, which can be independently programmed is described herein. For example, a host system may determine a configuration of a memory array, and communicate the configuration information to the memory system, and transmit a command for an operation to the memory system. In some examples, the memory system may utilize the memory array configuration information and determine to segment the blocks of memory cells into sub-blocks. By segmenting the memory block into sub-blocks, the memory device may maintain its memory block density while supporting efficient programming of blocks of the memory array.
A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations, including: determining a read voltage offset corresponding to a value of a metric reflective of a programmed state of a set of memory cells of the memory device; and performing, using the read voltage offset, a memory access operation with respect to the set of memory cells.
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
H01L 23/528 - Layout of the interconnection structure
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
83.
MEMORY DEVICE INCLUDING CALIBRATION OPERATION AND TRANSISTOR HAVING ADJUSTABLE THRESHOLD VOLTAGE
Some embodiments include apparatuses and methods using the apparatuses. One of the embodiments includes a capacitor, a transistor coupled to the capacitor, the transistor and the capacitor included in a memory cell; the transistor including a channel structure, a gate including a portion located on a side of the channel structure, and a dielectric structure between the channel structure and the gate; and on-die circuitry configured to selectively apply a stress condition to the transistor to tune a threshold voltage of the transistor.
A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.
G11C 7/16 - Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
A request can be provided, from a front-end of a memory sub-system, to a processing device of the memory sub-system and deleting the request from a buffer of the front-end of the memory sub-system. Responsive to deleting the request from the buffer, determining a first quantity of requests in the buffer and responsive to deleting the requests from the buffer, determining a second quantity of outstanding requests in the back-end of the memory sub-system. Responsive to deleting the request from the buffer and providing the request to the processing device, determining whether to provide a response to a host, wherein the response includes an indication of the quantity of requests in the buffer and of outstanding requests in a back-end of the memory sub-system, based on a comparison of the second quantity of outstanding requests to a threshold.
Methods, systems, and devices for page-by-page level shaping are described. The described techniques provide for a controller of a memory device to implement page-by-page level shaping when transferring data to a non-volatile memory device (e.g., flash memory). For example, the controller may receive a first set of bits associated with a first page of memory cells and may shape the first set of bits using a first shaping function to generate a second set of bits. Additionally, the controller may receive a third set of bits associated with a second page of memory cells and may shape the third set of bits using a second shaping function and the second set of bits to generate a fourth set of bits. In some cases, the controller may shape successive sets of bits using previously shaped bits and respective shaping functions.
Methods, systems, and devices related to firmware validation for firmware updates are disclosed. A controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.
G11C 16/12 - Programming voltage switching circuits
G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises memory arrays comprising memory cells comprising access devices and storage node devices, digit lines coupled to the access devices and extending in a first direction to a digit line exit region, and word lines coupled to the access devices and extending in a second direction to a word line exit region. The second microelectronic device structure comprises control logic devices over and in electrical communication with the memory cells. The microelectronic device further comprises contact structures individually in contact with the digit lines in the digit line exit region and in electrical communication with at least some of the control logic devices, at least one of the contact structures comprising a first cross-sectional area at an interface of the first microelectronic device structure and the second microelectronic device structure, and a second cross-sectional area at an interface of one of the digit lines and the at least one of the contact structures, the second cross-sectional area smaller than the first cross-sectional area. Related microelectronic devices, memory devices, electronic systems, and methods are also described.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H10B 12/00 - Dynamic random access memory [DRAM] devices
90.
SEMICONDUCTOR DEVICE ASSEMBLY WITH SACRIFICIAL PILLARS AND METHODS OF MANUFACTURING SACRIFICIAL PILLARS
Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.
Apparatuses, systems, and methods for shared codeword in two-pass access operations. The memory may use a read read modify write write (RRMWW) cycle to write data and metadata to the array. Metadata and a data codeword are read out as part of two read access passes and combined into a shared codeword. Error correction is performed on the shared codeword, and then the corrected shared codeword is modified with write data and metadata. Updated parity is generated based on the modified shared codeword and the modified data and updated parity and the metadata are written as two write access passes.
Methods, systems, and devices for page-by-page level shaping are described. The described techniques provide for a controller of a memory device to implement page-by-page level shaping when transferring data to a non-volatile memory device (e.g., flash memory). For example, the controller may receive a first set of bits associated with a first page of memory cells and may shape the first set of bits using a first shaping function to generate a second set of bits. Additionally, the controller may receive a third set of bits associated with a second page of memory cells and may shape the third set of bits using a second shaping function and the second set of bits to generate a fourth set of bits. In some cases, the controller may shape successive sets of bits using previously shaped bits and respective shaping functions.
Methods, systems, and devices for using a backup capacitor as an alternate energy source via dynamic APL budgeting are described. A memory system may use excess power available at an energy storage device such as a backup capacitor to improve performance under various circumstances. The amount of power reserved for the APL may be dynamically determined based on various conditions of the memory system. The energy reserved for APL recovery may be dynamically budgeted so that excess energy from the energy storage device may be used to improve operations. The energy storage device may be recharged using surplus power when the amount of energy required for operations at the SSD is less than the maximum power budget for the SSD.
An example apparatus can include a plurality of metal lines. The example apparatus can further include a cantilever, a diode, or a transistor in contact with at least a first metal line and a second metal line of the plurality of metal lines. The example apparatus can further include a circuit comprising at least one transistor or at least one diode in contact with at least the first metal line of the plurality of metal lines. The example apparatus can further include a diode or transistor in contact with at least the second metal line of the plurality of metal lines. An end of the cantilever is in contact with the first metal line through a first via and a first oxide portion. A portion of the cantilever is in contact with the second metal line through a second via and a second oxide portion.
Apparatuses, non-transitory machine-readable media, and methods associated with passive photonic physically unclonable functionality for securing an automotive powertrain control area network are described herein. One apparatus includes a first network node communicatively connected via photonic interconnections to a second network node, the first network node has a passive photonic encryption unit for encrypting data packets by utilizing a microring resonator (MR) having at least one fabrication process variation (FPV) that is unique from the MRs of the other nodes, a decryption unit having a look up table (LUT) including at least one node identifier and containing information about at least one FPV of one of the network nodes to decrypt data packets, and a processing unit that processes the contents of the decrypted data packets.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
An apparatus including a high bandwidth memory circuit and associated systems and methods are disclosed herein. The high bandwidth memory circuit can include two or more physical layer circuits to communicate with neighboring devices. The high bandwidth memory circuit can broadcast a status to the neighboring devices. The neighboring devices can be configured according to the operating demands of the high bandwidth memory circuit.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
97.
APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES
Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
A controller performs an access operation on a word line which is in a portion of a memory array in a memory device. The controller counts accesses on a portion-by-portion basis (e.g., a bank-by-bank basis, a sub-bank-by-sub-bank basis, etc.). The memory counts accesses on a word line-by-word line basis. The memory sets a refresh management (RFM) flag for a portion based on the counts associated with the word lines in that portion. The controller checks the RFM flag for a portion based on the access count for the portion. The controller issues an RFM command after checking the RFM flag if the RFM flag is set.
An example apparatus includes a data bus including a first portion having a timing domain which is controlled based on a first timing signal and further including a second portion having a timing domain which is controlled based on a second timing signal, and a data transfer circuit coupled to the data bus, the data transfer circuit including a data driver between the first portion of the data bus and the second portion of the data bus and a timing control circuit coupled to the data driver. The timing control circuit includes a variable delay to add an amount of delay to a first control signal to generate a second control signal. The data driver is configured to drive data from the second portion of the data bus to the first portion of the data bus responsive to the second control signal.
Methods, systems, and devices for techniques for staggering data burst events across channels are described. A memory system may offset data transfer events over multiple channels with a timing delay between data transfers over respective channels. For example, the memory system may initiate a first data transfer over a first channel at a first time and implement a timing delay before a second data transfer over a second channel at a second time such that the second time occurs after the first time. In some cases, the memory system may initiate one data transfer over each respective channel at a time, and in some cases, the memory system may initiate two or more data transfers over respective channels at a same time. In some cases, each channel may be associated with a respective timing delay.
