According to the various aspects, a method is provided for dicing a semiconductor panel having a glass core with topside build-up (BU) layers, backside BU layers, and interconnects. In an aspect, a hard mask is deposited on the semiconductor panel and patterned to form openings for a plurality of cut-streets. In an aspect, the dicing of the semiconductor panel includes using plasma dicing steps to form cut-streets through the topside BU layers and the backside BU layers, and using a mechanical sawing step or plasma dicing step to cut through the glass core. In another aspect, the dicing of the semiconductor panel further includes using an acid rinse to remove metal salts when cutting through the glass core during the plasma dicing step. In another aspect, a singulated die may have a first BU sidewall and a second BU sidewall having a morphology that includes semi-sphere fillers.
C03B 33/07 - Découpe de produits en verre armé ou stratifié
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
A control system for human-robot collaboration, including: a passive reactive control path implemented through a virtual damping system and configured to generate reactive control signals in response to human-applied interaction inputs; a predictive control path configured to generate predictive control signals based on predicted human performance objective inferred online from measured contact wrenches; and a signal blending component configured to combine the reactive control signals and the predictive control signals, wherein the predictive control signals are bounded in magnitude such that passivity of the reactive control path is preserved and stability of closed-loop human-robot interaction is maintained during collaboration.
B62D 57/032 - Véhicules caractérisés par des moyens de propulsion ou de prise avec le sol autres que les roues ou les chenilles, seuls ou en complément aux roues ou aux chenilles avec moyens de propulsion en prise avec le sol, p. ex. par jambes mécaniques avec une base de support et des jambes soulevées alternativement ou dans un ordre déterminéVéhicules caractérisés par des moyens de propulsion ou de prise avec le sol autres que les roues ou les chenilles, seuls ou en complément aux roues ou aux chenilles avec moyens de propulsion en prise avec le sol, p. ex. par jambes mécaniques avec des pieds ou des patins soulevés alternativement ou dans un ordre déterminé
3.
SUB-TILE-BASED GRID SAMPLING IN NEURAL VIDEO CODECS
Real-time neural video codecs face significant latency and energy bottlenecks due to pixel-level grid sampling, which requires irregular, fine-grained memory accesses and limits efficient hardware acceleration. To address this, a sub-tile-based grid sampling technique is disclosed herein. The technique determines super tile sizes using motion vector gradients, neural network parameters, and available on-chip memory. A super tile is split into sub-tiles by detecting motion boundaries through motion vector analysis, where a sub-tile has homogeneous motion vectors. For each sub-tile, a reference bounding box is computed to enable efficient block transfers of reference data, and per-pixel metadata is generated for feature interpolation. The pipelined, parallelizable solution reduces number of memory accesses and computational overhead, compared to existing pixel-based techniques.
H04N 19/43 - Matériel spécialement adapté à l’estimation ou à la compensation de mouvement
H04N 19/105 - Sélection de l’unité de référence pour la prédiction dans un mode de codage ou de prédiction choisi, p. ex. choix adaptatif de la position et du nombre de pixels utilisés pour la prédiction
H04N 19/139 - Analyse des vecteurs de mouvement, p. ex. leur amplitude, leur direction, leur variance ou leur précision
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
H04N 19/196 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par le procédé d’adaptation, l’outil d’adaptation ou le type d’adaptation utilisés pour le codage adaptatif étant spécialement adaptés au calcul de paramètres de codage, p. ex. en faisant la moyenne de paramètres de codage calculés antérieurement
H04N 19/436 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques caractérisés par les détails de mise en œuvre ou le matériel spécialement adapté à la compression ou à la décompression vidéo, p. ex. la mise en œuvre de logiciels spécialisés utilisant des dispositions de calcul parallélisées
H04N 19/55 - Estimation de mouvement avec contraintes spatiales, p. ex. au niveau des contours de l’image ou des contours des régions
4.
MICROELECTRONIC ASSEMBLIES INCLUDING A GLASS-CORE WITH POST-SINGULATION EDGE FEATURES
Disclosed herein are microelectronic assemblies and related devices and methods for alleviating crack formation and propagation in glass by providing various edge features during or after singulation of a glass panel into individual glass units. In some embodiments, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge, where a material of the protection coating includes a low-density polystyrene foam, an ionogel, a fiber reinforced resin, a pre-impregnated dielectric, a pre-impregnated fabric, a carbon nanotube reinforced epoxy resin, a metal oxide, a mold material, or a solder resist.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
5.
SYSTEMS AND METHODS FOR MULTI-LAYER OPC (OPTICAL PROXIMITY CORRECTION) METROLOGY USING ELECTRICAL TEST DATA
Systems and methods for multi-layer optical proximity correction (OPC) metrology. The OPC metrology system accesses three layers of OPC contour data, the layers of OPC data generated for a drawn integrated circuit layout characterized for a foundry process node. The three layers include a first metal layer, a second metal layer, and a via layer. A feature, such as a via, is formed in the three layers. The system receives user input defining a check (geometric analysis) for the feature, and a limit. The system performs the check on the features and generates a flag for the feature when the limit is exceeded. The system can generate output that reflects the integration of multiple checks and predicts risks and yields for the foundry process node.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
Embodiments disclosed herein include an apparatus that comprises a substrate, and the substrate includes glass. In an embodiment, an opening is provided through a thickness of the substrate, and a layer is along a sidewall of the opening. In an embodiment, the layer comprises a polymer and an electrical conductor that comprises carbon. In an embodiment, a via is provided in the opening, and the via is an electrically conductive material.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
A power delivery system is described that enables instant 20V/28V power delivery to sink devices by utilizing unique Configuration Channel (CC) resistor signatures to bypass standard power negotiation delays. The system may implement non-standard pull-down resistors (Rd) in sink devices and matching unique pull-up resistors (Rp) in source adapters to create CC voltages outside legacy USB PD specification ranges, instantly signaling full-power capability without traditional multi-step negotiations. Upon detecting such compatible unique signatures, the source may immediately apply a VBUS voltage of 20V or 28V at full current, eliminating the boot delays caused by standard USB PD negotiation processes. The system also avoids problematic sink standby (pSnkStdby) power consumption limitations that prevent dead battery boot scenarios. The system maintains backward compatibility through automatic fallback to standard USB PD negotiation when non-compliant devices are connected.
A semiconductor device and a method for fabricating a semiconductor are described. The semiconductor device includes two modules, each module including two tiers, each tier including (i) a passive die including through-silicon vias (TSVs) arranged side-by-side laterally with a core die and (ii) bumps coupling the TSVs and an overhang portion of the core die of a second tier to the TSVs the first tier, the first module further including a bottom redistribution layer (RDL) on which the first second tier of the first module is disposed and a top RDL disposed on the second tier of the first module, the bottom RDL coupled to the bumps disposed on the first tier of the first module while the top RDL configured to couple the bumps of the first tier of the second module to the TSVs of the second tier of the first module in a one-to-one manner.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
Logic may perform resource selection from a resource pool to deter-mine a set of resources from the resource pool for transmission of a reference signal. Logic may autonomously allocate the set of resources for a transmission of the reference signal within a physical sidelink shared channel (PSSCH) or as a standalone transmission. Logic may generate a control information signal to signal the set of resources for the reference signal, the control information signal comprising a source identifier field, a destination identifier field, and one or more fields to indicate automatic gain control, guard symbols, or a combination thereof. And logic may encode the control information signal for transmission to a second UE via the interface.
H04W 72/40 - Gestion des ressources pour la communication en mode direct, p. ex. D2D ou liaison secondaire
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/25 - Canaux de commande ou signalisation pour la gestion des ressources entre terminaux au moyen d’une liaison sans fil, p. ex. liaison secondaire
10.
INTEGRATED CIRCUIT PACKAGES INCLUDING A GLASS-CORE SUBSTRATE
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
11.
PACKAGE RETENTION IN A TEST SOCKET BY A PRESSURIZED FLUID
According to various aspects of the present disclosure, a semiconductor testing equipment may include a thermal head assembly having a body with a recess that is unobstructed and designed to fit over a die on the semiconductor package. A sealing member on the thermal head assembly engages a landing area on the semiconductor package to form a sealed chamber. The semiconductor package may be uniformly loaded by introducing a gas and incrementally increasing the gas pressure in the sealed chamber and increasing mechanical load on the sealing member onto the landing area to prevent leakage. Once the sealed chamber is fully sealed, the combined internal pressure from the circulating gas and a sealing perimeter load enables the proper socketing of the semiconductor package. Thereafter, the gas may be replaced with a circulating liquid refrigerant to remove the heat generated by the die during the testing of the semiconductor package.
According to the various aspects, the present methods provide for the laser-assisted dicing of semiconductor workpieces that produce semiconductor devices with glass cores having semi-transparent edges.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
Efficient data movement in neural network accelerators operating within virtualized memory systems is challenged by high address translation latency and unique data access patterns. To address this challenge, address translation prefetch (ATP) mechanisms can be implemented to proactively translate virtual memory addresses before data movement. ATP can be performed in advance of any data movement or concurrently with data movement while being throttled by page transition in the data movement request stream. The ATP mechanism can enforce quotas on outstanding ATP requests, independently for read and write streams, to preserve resources for other processes running on the neural network accelerator. In dealing with competing ATP requests, the mechanism can employ weighted arbitration to balance between different types of ATP requests, utilizing a programmable ratio. The ATP mechanisms enable scalable, high-throughput neural network inference in virtualized environments, addressing data movement bottlenecks in neural network accelerator deployments.
Systems and methods are provided for transforming audio signals captured by a throat microphone into signals emulating speech recorded with a conventional air-conduction microphone. Throat microphones employ vibration sensors positioned on the neck to capture audio, making them suitable for high-noise environments. However, throat microphone signals lack high-frequency components, reducing intelligibility and degrading automatic speech recognition performance. The techniques provided herein apply signal-processing operations and a lightweight neural network to reconstruct missing spectral details. The input signal is converted to log-Mel spectra and modeled as a smooth average spectrum (SAS) plus a residual component. A neural network predicts a conventional-microphone SAS. A vocoder synthesizes an enhanced audio signal after combining the predicted SAS with the residual component. The approach improves speech intelligibility and ASR accuracy while maintaining low computational complexity, enabling real-time, on-device processing in noisy environments and supporting hands-free communication for applications such as collaborative robotics and augmented reality.
G10L 21/057 - Compression ou expansion temporelles pour améliorer l'intelligibilité
G10L 21/0216 - Filtration du bruit caractérisée par le procédé d’estimation du bruit
G10L 21/0224 - Traitement dans le domaine temporel
G10L 21/0232 - Traitement dans le domaine fréquentiel
G10L 25/18 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par le type de paramètres extraits les paramètres extraits étant l’information spectrale de chaque sous-bande
G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
H04R 1/46 - Adaptation particulière pour usage comme microphone de contact, p. ex. sur instrument de musique, sur stéthoscope
An apparatus and method for dynamic snoop filter partitioning. One embodiment of a processor is coupled to a socket, the processor comprising: a plurality of cores; a plurality of caches to store cache lines read from memory by the plurality of cores; cache management circuitry to manage coherency of the cache lines; snoop handling circuitry comprising a snoop filter, the snoop handling circuitry to: track snoop filter allocations for local requests and remote requests to at least a first sub-partition of a first snoop filter over one or more time windows, the local requests comprising requests from the plurality of cores or other circuit blocks of the processor and the remote requests comprising requests from a different processor in a different socket; determine a victim snoop filter entry in the first snoop filter based, at least in part, on the tracked snoop filter allocations over the time windows.
Disclosed are voltage regulator embodiments with dynamically adjustable soft-switching entry (e.g., ZCD) thresholds to efficiently manage entry into soft-switching under different load conditions.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
G01R 19/175 - Indications des instants de passage du courant ou de la tension par une valeur déterminée, p. ex. de passage par zéro
H02M 1/00 - Détails d'appareils pour transformation
17.
MULTI-LAYER ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION
Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 29/66 - Types de dispositifs semi-conducteurs
18.
GENERATION OF SYNTHETIC IMAGES FOR TRAINING OF DEFECT DETECTION MODELS
Systems, apparatus, articles of manufacture, and methods to generate synthetic images for training of defect detection models are disclosed. An example system disclosed herein produces synthetic images of pallet defects to train object detection models. In some examples, a small set of real images containing defects, associated masks and textual descriptions is used to fine tune a latent diffusion model. The fine-tuned model accepts a masked input image, a mask that defines the region to be altered, and a defect description, and generates a synthetic image with the defect inpainted into the masked region. In some examples, generated synthetic images are filtered to remove outliers that do not match the real defect distribution. The filtered synthetic dataset, together with a limited set of real images, is then used to train a downstream object detection model capable of identifying pallet damage in captured images.
A wireless communication device includes at least two antennas and transmitter circuitry incorporating an attenuation circuit. The attenuation circuit has a first port coupled to a first power amplifier and a second port coupled to a second power amplifier. A matching network connects the first and second ports and comprises a pair of coupled lines. Auxiliary lines are coupled to the coupled lines to enable programmable attenuation while maintaining wideband performance. The coupled-line matching network provides compact, low-loss interstage impedance matching and supports integration into mmWave RF transmit chains. By leveraging auxiliary lines and associated attenuation control, the device achieves fine gain programmability with minimal insertion loss and negligible area overhead, improving linearity and efficiency relative to transformer-based designs. This architecture is suitable for high-frequency systems requiring robust gain control across large bandwidths, such as sub-THz and mmWave radios.
Systems, apparatus, articles of manufacture, and methods are disclosed for zero-copy tensor combination via memory management unit remapping. An example method includes identifying physical memory addresses of tensors of a machine learning model, the tensors stored in a key value cache, the tensors including a first tensor and a second tensor stored at respective physical memory addresses, creating a range of virtual addresses for a combined tensor, the combined tensor to represent a combination of the first tensor and the second tensor, and binding the physical memory addresses of the tensors to the range of virtual addresses using a memory management unit.
Embodiments herein relate to interconnects in Complementary Field-Effect Transistor (CFET) devices. In one aspect, an epitaxial silicon material is used to provide a conductive path which extends laterally between first and second CFET devices. In one example, the conductive path extends between drains of n-channel and p-channel Field-Effect Transistors (FETs) of the CFETs. In another example, the conductive path extends between gates of the n-channel and p-channel FETs of the CFETs. Each CFET may be provided in area allocated to a standard cell. In another aspect, an area of a standard cell allocated to passive devices is used for a through-silicon via which extends from a front side metal layer to a back side metal layer.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
22.
SYSTEMS, METHODS, AND APPARATUS FOR TRUSTED CONFIDENTIAL COMPUTING MESH
This disclosure relates generally to confidential computing and, more particularly, to trusted confidential computing meshes. An example apparatus for attestation verification comprises interface circuitry, machine readable instructions, and programmable circuitry to execute the machine readable instructions to obtain verification data corresponding to a network application from a server, verify the network application based on policy data included in the verification data, if verification of the network application is successful, allow network traffic between the programmable circuitry and the network application, and if the verification of the network application is not successful, at least one of isolate the network application or prevent traffic between the programmable circuitry and the network application.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
23.
Enhanced Edge Application Server Discovery Function for Service Discovery in Cellular Networks
An enhanced Edge Application Server Discovery Function (eEASDF) for service discovery in cellular networks, addresses the limitations of static and DNS-based discovery mechanisms. The eEASDF dynamically matches user equipment (UE) requests with edge application servers (EAS) based on detailed filters, such as compute resource requirements, quality-of-service objectives, and location scope. Utilizing Protocol Configuration Options (PCO), the eEASDF can facilitate efficient service discovery by integrating metadata and telemetry from a Unified Data Repository (UDR) or Service Repository Function (SRF). This functionality can support user-plane traffic steering through PDU session modifications, uplink classifier updates, and user plane function reselection. The described technology enhances latency performance, reduces rediscovery churn, and optimizes resource allocation for compute-intensive applications in next-generation networks. Primary applications can include augmented reality, real-time analytics, and AI-assisted services.
Photonics integrated circuit (PIC) dies bonded to photonics substrates, related apparatuses, systems, and methods of fabrication are disclosed. A photonics substrate and a PIC die include corresponding optical bonding regions one or both of which are surrounded by hydrophobic structures. A liquid droplet is applied to the PIC die or photonics substrate optical bonding region and the PIC die is placed on the optical bonding region of the photonics substrate. Capillary forces cause the PIC die to self-align to the optical bonding region, and an optical bond is formed by evaporating the liquid and subsequent anneal.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
25.
COMPRESSION FOR SPARSE DATA STRUCTURES UTILIZING MODE SEARCH APPROXIMATION
Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.
Disclosed herein are memory cells using Gunn diodes, and related integrated circuit (IC) structures, devices, and techniques. In one aspect, a memory cell includes a first transistor, a second transistor, a first Gunn diode coupled to the first transistor, a second Gunn diode coupled to the second transistor, and a capacitor coupled between the first Gunn diode and the second Gunn diode.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
27.
KEY-VALUE CACHE COMPRESSION BASED ON GAUGE TRANSFORMATION
KV cache for transformer models may be compressed through gauge transformation, entropy encoding, or rank-r approximation. Transformation matrices may be determined for gauge transformation of an attention layer. The query weight matrix and key weight matrix of the head may be transformed using a transformation matrix. The value weight matrix and output weight matrix of the head may be transformed using another transformation matrix. The gauge transformation may produce canonicalized weights. The attention layer may be updated with the canonicalized weights. The canonicalized model may be executed, and canonicalized KV data may be produced during the execution. A portion of the canonicalized KV data may be further compressed entropy encoding and then stored in a cold tail cache. The rest of the canonicalized KV data may be stored in a hot window cache. The canonicalized KV data may be further compressed based on rank-r approximation before or after gauge transformation.
Methods and apparatus disclosed herein introduce a comprehensive framework for distributing generative-AI workloads across diverse enterprise hardware. Multiple routing strategies disclosed herein include user-controlled, algorithm-controlled, hybrid, and dual-path routing with feedback to accommodate varying user expertise and resource availability. The routing logic is detailed for Question Answering (QA) tasks, Retrieval-Augmented Generation (RAG)-based tasks (e.g., document parsing and retrieval), and agent tasks, including evaluation of resource availability, model complexity, and content characteristics. User feedback can be obtained to continuously refine routing decisions through Large Language Model (LLM) based and traditional machine learning models. Methods and apparatus disclosed herein initiate routing decisions to maintain cost-efficiency, performance optimization, and accuracy across heterogeneous computing environments.
One embodiment of a method comprises: fetching a plurality of instructions from a memory; executing the plurality of instructions, wherein a subset of the plurality of instructions are to cause memory access operations; performing a lookup in a L1 TLB coupled to or integral to the out-of-order execution circuitry to attempt to locate first virtual to physical address translations; performing a lookup in a STLB coupled to or integral to the out-of-order execution circuitry in response to a miss at the L1 TLB; and prefetching, by prefetch circuitry, a first entry from the STLB into the L1 TLB, the prefetch circuitry to perform additional prefetches, wherein in a first operational mode, a plurality of sequential entries are to be prefetched from the STLB and, in a second operational mode, a plurality of entries indicated in a temporal pattern table entry corresponding to the first entry are to be prefetched.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]
30.
WAFER PROTECTION MATERIAL WITH LUMINESCENT BASED ADDITIVES
In the various aspects, a wafer protection/coating material is provided with luminescent additives and is deposited over a BGA or a plurality of solder bumps as a protective layer during a laser scribe, a laser full cut, and/or plasma singulation process. The inclusion of luminescent additives facilitates assessing, in-line, the coating quality, i.e., thickness, specifically the coverage of the wafer protection material on top of the solder bumps using luminescent detection metrology. In an aspect, the wafer protection material may be water-soluble and may be removed after the laser/plasma process step using water.
A device includes a port to couple to another device over an interconnect, where the port includes circuitry to generate a no operation (NOP) flit, where the NOP flit is encoded with debug information associated with an upper layer of a protocol stack. The generated NOP flit is then sent on the interconnect by the port.
According to the various aspects, a present tool assembly or apparatus includes a water delivery component configured to direct water to a workpiece, and a cutting component for removing material to form cut-streets for die singulation. The present tool assembly is configured to operate to remove build-up layers and other layers from a glass core of the workpiece in a wet environment and a dry environment, at cut-street locations, and perform methods for dicing the workpiece.
B23K 26/364 - Gravure au laser pour faire une rainure ou une saignée, p. ex. pour tracer une rainure d'amorce de rupture
B23K 26/00 - Travail par rayon laser, p. ex. soudage, découpage ou perçage
B23K 26/14 - Travail par rayon laser, p. ex. soudage, découpage ou perçage en utilisant un écoulement de fluide, p. ex. un jet de gaz, associé au faisceau laserBuses à cet effet
B23K 26/146 - Travail par rayon laser, p. ex. soudage, découpage ou perçage en utilisant un écoulement de fluide, p. ex. un jet de gaz, associé au faisceau laserBuses à cet effet l'écoulement de fluide contenant un liquide
Disclosed are techniques for fabricating transistors such as gate all around (GAA) transistors and techniques for measuring nano channel thicknesses using Raman spectroscopy.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
G01B 11/06 - Dispositions pour la mesure caractérisées par l'utilisation de techniques optiques pour mesurer la longueur, la largeur ou l'épaisseur pour mesurer l'épaisseur
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
34.
METHODS AND DEVICES TO PERFORM SHORT-RANGE WIRELESS COMMUNICATION
An apparatus of a Bluetooth (BT) communication device, the apparatus may include a memory, and a processor configured to: communicate with a peripheral device via an established BT connection between the BT communication device and the peripheral device; identify a further BT communication device that is connectable to the peripheral device; and instruct, via the established BT connection, the peripheral device to enter a discovery mode.
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
An articulated structure pose estimation system, including: a plurality of synergy space encoders, each configured to generate a respective probability distribution in a synergy space having fewer dimensions than a full joint space, the full joint space corresponding to a multi-degree-of-freedom model of an articulated structure, wherein different ones of the synergy space encoders are configured to encode different contextual or observational information related to articulated structure pose estimation; a synergy heatmap solver configured to: combine the respective probability distributions from the plurality of synergy space encoders to generate a combined probability distribution in the synergy space; and perform probabilistic inference on the combined probability distribution to determine an inferred synergy point; and a synergy decoder configured to decode the inferred synergy point into a pose representation of the articulated structure in the full joint space.
G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
G06V 10/77 - Traitement des caractéristiques d’images ou de vidéos dans les espaces de caractéristiquesDispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant l’intégration et la réduction de données, p. ex. analyse en composantes principales [PCA] ou analyse en composantes indépendantes [ ICA] ou cartes auto-organisatrices [SOM]Séparation aveugle de source
G06V 40/10 - Corps d’êtres humains ou d’animaux, p. ex. occupants de véhicules automobiles ou piétonsParties du corps, p. ex. mains
36.
INTEGRATED CIRCUIT PACKAGES INCLUDING A GLASS-CORE SUBSTRATE
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a first layer having a first dielectric, a third dielectric, and a first glass portion between the first dielectric and the third dielectric; a second layer having a second dielectric, a fourth dielectric, and a second glass portion between the second dielectric and the fourth dielectric; and a third layer between the first layer and the second layer, the third layer having a bulk glass material, and wherein the first layer physically couples to a first surface of the third layer and the second layer physically couples to a second surface of the third layer.
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
37.
SEMICONDUCTOR DEVICE AND PROCESS FOR MAKING THE SAME
In some aspects, a semiconductor device is provided. The semiconductor device includes a plurality of core dies; and a plurality of passive dies, each of the plurality of passive dies corresponding to one respective core die of the plurality of core dies, wherein each of the plurality of passive dies comprises a plurality of through-silicon vias configured to connect the plurality of core dies with a controller die, and wherein the plurality of core dies and the plurality of passive dies are arranged vertically into first to Nth tiers in a manner that each tier of the first to Nth tiers includes a core die of the plurality of core dies and a corresponding passive die of the plurality of passive die placed side-by-side horizontally.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
38.
NANOWIRE TRANSISTOR STRUCTURE AND METHOD OF SHAPING
A nanowire device includes one or more nanowire having a first end portion, a second end portion, and a body portion between the first end portion and the second end portion. A first conductive structure is in contact with the first end portion and a second conductive structure is in contact with the second end portion. The body portion of the nanowire has a first cross-sectional shape and the first end portion has a second cross-sectional shape different from the first cross-sectional shape. Integrated circuits including the nanowire device and a method of cleaning a semiconductor structure are also disclosed.
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/822 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe IV, p. ex. des hétérojonctions Si/Ge
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
This disclosure discloses a joint scheduling of data channel on multiple bandwidth parts. The disclosure provides an apparatus comprising interface circuitry; and processor circuitry coupled with the interface circuitry. The processor circuitry is to: monitor a physical downlink control channel (PDCCH) on a bandwidth part (BWP) via the interface circuitry; decode a downlink control information (DCI) in the PDCCH; and receive, in response to at least one field in the DCI indicating to schedule multiple physical downlink shared channels (PDSCHs) and/or physical uplink shared channels (PUSCHs) on a plurality of concurrently active BWPs, the PDSCHs on the plurality of concurrently active BWPs via the interface circuitry. Other embodiments are also disclosed and claimed.
H04W 72/0457 - Affectation de bande ou de débit variable
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
40.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The disclosure describes a semiconductor device and a method for fabricating a semiconductor device. The semiconductor device includes: a first module and a second module stacked vertically on the first module, each module includes multiple dies stacked vertically within an insulation layer, wherein each die higher than a lower die is laterally offset from the lower die forming a terraced structure, wherein the second module comprises vertical wires connecting the overhang portions of the terraced structure of the second module to a top dielectric layer of the first module underneath the second module, and the insulation layer of the first module further includes through-insulation vias (TIVs) connecting the top dielectric layer to a bottom dielectric layer through the insulation layer, such that the dies of the second module are coupled to the bottom dielectric layer of the first module through the top dielectric layer and TIVs.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A computing system including two or more processing units shares virtual memory for a program between the two or more processing units. Each of the processing units may include memory management circuitry to manage a respective page table corresponding to the virtual memory. A first portion of the addresses of the virtual address space of the program are mapped to addresses of physical memory associated with a first one of the two or more processing units, while a second portion of the addresses of the virtual address space are mapped to addresses in physical memory associated with a second one of the two or more processing units.
One or more inference processes may be performed in the deployment of a transformer model. For proving correctness of a transformer model inference, a ZKP may be generated in two stages. In the first stage, PoGE may be generated by canonicalizing deployed weights of the transformer model through gauge transformation to produce canonical weights. A canonical model may be generated by modifying the transformer model with the canonical weights. In the second stage, PoVI may be generated. The canonical model may be executed to generate an output from an input. The output of the canonical model may be bit-identical as the output of the transformer model for the same input despite the weight canonicalization. The ZKP for the transformer model inference may include the PoGE and PoVI. The PoGE may be generated once and used for many inference processes. The PoVI may be generated per inference.
Techniques to form semiconductor devices that include subfins that are at least partially amorphized are described. A backside dopant implantation process using dopants (e.g., germanium) may be used to create amorphous semiconductor material in the subfins. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region formed from a fin of semiconductor material. The fin includes a subfin laterally adjacent to a dielectric fill. A backside ion implantation process may be used to implant dopants such as Ge into the subfin and consequently form an amorphized portion of the subfin. In some examples, the amorphized portion is under the gate structure and laterally between a source region and a drain region. The amorphized portion may extend from a bottom surface of the subfin to just under the gate structure, and in some cases, leave a crystalline portion of subfin below the gate structure.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/778 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à deux dimensions, p.ex. transistors à effet de champ à haute mobilité électronique HEMT
The present disclosure generally relates to a method that includes providing a photomask, wherein the photomask includes a trench defined by two sidewalls which are exposed, introducing the photomask into a controlled environment, and directing (i) one or more reactive gases, (ii) a laser, (iii) one or more reactive gases and a laser, or (iv) one or more reactive gases and an electron beam, to the two sidewalls to render a passivation layer adjacent to and in contact with each sidewall. An apparatus and the photomask are also described.
B23K 26/08 - Dispositifs comportant un mouvement relatif entre le faisceau laser et la pièce
B23K 26/352 - Travail par rayon laser, p. ex. soudage, découpage ou perçage pour le traitement de surface
G03F 1/22 - Masques ou masques vierges d'imagerie par rayonnement d'une longueur d'onde de 100 nm ou moins, p. ex. masques pour rayons X, masques en extrême ultra violet [EUV]Leur préparation
An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
Methods, systems and apparatuses may provide for hardware sampler technology that determines mip region dimensions of a feedback map based on a description of the feedback map, identifies accessed texels in a texture based on a view of a resource that is paired with the feedback map, and records the accessed texels in the feedback map based on the mip region dimensions.
Embodiments include apparatuses, methods, and systems including a power control unit to control different power consumptions by one or more processors to operate different applications. The power control unit may receive power information that may include a priority information for each application to be operated on the one or more processors, determine to control, based on the power information for different applications, different power consumptions by the one or more processors to operate the different applications. Other embodiments may also be described and claimed.
Methods, apparatus, systems, and articles of manufacture are disclosed to partition neural network models for executing at distributed Edge nodes. An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions. One or more of the at least one processor circuit is to partition a neural network model into a first portion to be executed at an edge of a network and a second portion to be executed at a cloud based on a transmission metric.
H04L 41/5054 - Déploiement automatique des services déclenchés par le gestionnaire de service, p. ex. la mise en œuvre du service par configuration automatique des composants réseau
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
H04L 41/5019 - Pratiques de respect de l’accord du niveau de service
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
H04L 67/00 - Dispositions ou protocoles de réseau pour la prise en charge de services ou d'applications réseau
H04L 67/10 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau
Examples described herein relate to a device that includes: a plurality of nodes, wherein a node of the plurality of nodes comprises at least one processor and a structure comprising multiple physical layers, wherein different physical layers of the multiple physical layers are to provide communication entry points to at least some of the same nodes at different node spans by a stack of overlapping two dimensional (2D) meshes. In some examples, a first layer of the multiple layers comprises a first trace that comprises a link that connects a first span of nodes. In some examples, a second layer of the multiple layers comprises a second trace that comprises a link that connects a second span of nodes, where the first span of nodes is greater than the second span of nodes.
A device may include a first die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to generate a transmission asynchronous pattern; receive a response pattern via the data transmission interface indicating whether the transmission asynchronous pattern was received by a second die; control a data transfer between the first die and the second die via the data transmission interface based on the response pattern; and a second die, including: a data transmission interface configured to inductively transmit and receive signals; a processor configured to receive the transmission asynchronous pattern; check whether the received transmission asynchronous pattern is correct; generate a response pattern indicating whether the received transmission asynchronous pattern is correct; control a data transfer between the first die and the second die via the data transmission interface based on the check whether the received transmission asynchronous pattern is correct.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
51.
EMBEDDING NEURAL NETWORK ON SILICON THROUGH INTEGRATED RANDOM-ACCESS MEMORY MULTIPLY-ADDER
Integrated cells may perform matrix multiplication (MatMul) operations. An integrated cell may include a random-access memory (RAM) cell, dot product unit(s), multiplexer(s), adder, route-in unit, control unit, and vector machine. The RAM cell may store weights and activations. The dot product unit(s) may compute dot products from the weights and activations. The adder may accumulate the dot products. The route-in unit may facilitate data transfer from the RAM cell to the dot product unit(s) or data transfer from another integrated cell to the integrated cell. The control unit may manage memory operations and detect and repair errors in memory operations. The vector machine may provide instructions to the dot product unit(s) and multiplexers to direct the flow of multiply-accumulate operations. Counters may be used to control weight fetching from RAM cells. A MatMul operation may be decomposed, and the integrated cells may perform the MatMul operation through multiple clock cycles.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06N 3/10 - Interfaces, langages de programmation ou boîtes à outils de développement logiciel, p. ex. pour la simulation de réseaux neuronaux
Three-dimensional gaussian splatting (3DGS) is a powerful technique for three-dimensional reconstruction using multiple input images. Using 3DGS to reconstruct large-scale scenes can utilize large amounts of graphical processing unit (GPU) memory and take a long time to complete. Splitting the large-scale scene into multiple regions and applying 3DGS on multiple GPUs in parallel can reduce memory usage and improve computational time. However, it is not trivial to obtain an integrated model based on the training models produced by the parallel GPUs. To address this technical challenge, the training models are aligned, conflicting gaussian pairs are identified, and properties of the conflicting gaussian pairs are merged during the rendering process. The result is a solution that can execute 3DGS on parallel GPUs and can produce a usable and high fidelity integrated model for three-dimensional reconstruction of a large-scale scene.
Microelectronic assembly architectures including a die stack in which each die includes a redistribution layer, and the die stack is positioned such that the face of each die is perpendicular to a face of a base, are provided. Each die has a first face and a second face opposite the first face, and an edge extending between the first and second faces. A redistribution layer is deposited on the first face of each die. The faces of each die in the die stack are parallel to the faces of the other dies. The die stack is positioned on the base such that the faces of each die are orthogonal to the face of the base. Each die can have a conductive contact on a bottom edge, and the conductive contact can be coupled to the respective redistribution layer on the die and to a conductive contact on the base.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
Techniques are provided herein to form semiconductor devices that include one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure around or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors with a gate cut that extends through at least an entire thickness of the gate structure and includes dielectric material. The gate cut includes a hybrid design that is formed in two parts. A first part of the gate cut is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second part of the gate cut is formed over the first part of the gate cut and is integrated with spacer structures formed on the sidewalls of a sacrificial gate that extends over the adjacent fins.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Microelectronic assemblies with glass cores with tapered insulator edges, as well as related devices and fabrication techniques, are disclosed. In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face, and an insulator material having a bottom face, a top face opposite the bottom face, and an outer edge extending between the bottom face and the top face. The top bottom face of the insulator material is on the glass core, and the outer edge of the insulator material tapers from a first perimeter at the bottom face to a second perimeter at the top face. The taper of the outer edge results in the first perimeter being larger than the second perimeter.
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/13 - Supports, p. ex. substrats isolants non amovibles caractérisés par leur forme
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
56.
LID OR STIFFENER ATTACHMENT STRUCTURE WITH A HYBRID ADHESIVE
An embodiment may include an apparatus, that comprises a first substrate and an adhesive layer on the first substrate. In an embodiment, the adhesive layer comprises a first adhesive, where the first adhesive is a polymer that comprises silicon and oxygen, and a second adhesive, where the second adhesive is an epoxy. In an embodiment, the first adhesive is adjacent to the second adhesive. In an embodiment, the apparatus further comprises a second substrate coupled to the first substrate by the adhesive layer.
Systems and methods for adaptive prediction cost estimation in video encoding are provided. The techniques improve early cost estimation and reduce the number of candidates for the later decision stages and final RDO stage. In particular, an adaptive sum of absolute transformed differences (SATD) is determined for each candidate, and, based on the adaptive SATD values, a subset of candidates is selected for mode decision search to determine block partitioning, motion vectors, and encoding modes, The adaptive SATD combines a weighted DC component of the SATD and the AC component of the SATD. The weighting factor is selected from a DC adjustment ratio table based on the spatial variation and the QP for a respective coding tree unit. The techniques improve cost estimation accuracy, reduce encoding complexity, and are hardware-friendly for integration into video codecs such as HEVC, AV1, VVC, and AV2.
H04N 19/156 - Disponibilité de ressources en matériel ou en calcul, p. ex. codage basé sur des critères d’économie d’énergie
H04N 19/14 - Complexité de l’unité de codage, p. ex. activité ou estimation de présence de contours
H04N 19/169 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif
Examples described herein relate to adjusting a queue size based on utilization of a device and an artificial intelligence (AI) model trained on at least one or more of: data size, request priority, device congestion, device latency, device interface throughput, network throughput, queue length, queue priority, request receipt rate, number of queues allocated to receive the requests, device memory usage, and/or whether address translation prefetch mode is enabled or not enabled. In some examples, the device includes an accelerator to perform cryptographic and/or compression operations in response to the requests.
Disclosed herein is memory device that includes a printed circuit board (PCB) and a plurality of dynamic random-access memory (DRAM) devices arranged on the PCB and logically divided into four pseudo-channels. A shared command/address (C/A) bus of the device is configured to transmit command signals to all four pseudo-channels and a set of multiplexers on the device are controllable to selectively couple data signals between the four pseudo-channels and a memory controller. A control interface of the device is configured to interleave data burst transactions of the data signals across the four pseudo-channels, wherein a burst of the data burst transactions is distributed across two groups, each group comprising two of the four pseudo-channels operating in parallel.
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
60.
SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BIT FLOATING-POINT FORMAT
Disclosed embodiments relate to systems and methods for performing instructions to convert to 16-bit floating-point format. In one example, a processor includes fetch circuitry to fetch an instruction having fields to specify an opcode and locations of a first source vector comprising N single-precision elements, and a destination vector comprising at least N 16-bit floating-point elements, the opcode to indicate execution circuitry is to convert each of the elements of the specified source vector to 16-bit floating-point, the conversion to include truncation and rounding, as necessary, and to store each converted element into a corresponding location of the specified destination vector, decode circuitry to decode the fetched instruction, and execution circuitry to respond to the decoded instruction as specified by the opcode.
Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
Conductive vias for 3D integration may be formed during or after assembly to couple dies or die stacks. In one example, such conductive vias may extend through the dies or die stacks and through an interface with conductive bumps, without terminating on the bumps. Bypassing conductive bumps with a conductive via may enable improved performance, power delivery, and thermal management. In one example, an assembly includes a first IC structure (such as a substrate, interposer, or other IC structure) and a second IC structure (such as a die or die stack) over the first IC structure. The assembly includes an interface layer between the first IC structure and the second IC structure, where the interface layer includes a plurality of conductive bumps. A conductive via extends through the interface layer with the bumps and is coupled with a conductive element of the first IC structure.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
In some embodiments, a voltage regulator with circuitry to facilitate DCM to CCM transitions are provided to mitigate against excessive voltage droops.
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
64.
OVERHANG ARCHITECTURES FOR HIGH BANDWIDTH MEMORY (HBM) MULTI-DIE ASSEMBLIES AND METHODS FOR MAKING SAME
Overhang architectures for high bandwidth memory (HBM) multi-die assemblies and methods for making same. The overhang architecture places the DRAM (HBM) underneath the top IC die. The signal interconnects between the top IC die and the DRAM die are direct signal interconnects without lateral routing on a package substrate or on a motherboard.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
65.
SEQUENTIALLY CLEARING SUBSETS OF PREDICTION STATE OF PROCESSORS WHILE CONTINUING TO PROCESS INSTRUCTIONS
A method of an aspect includes processing instructions with a processor, making predictions associated with some of the instructions based on prediction state, clearing a plurality of subsets of the prediction state sequentially, and continuing the processing of the instructions while the plurality of the subsets of the prediction state are being cleared. Other methods, processors, and systems are also disclosed.
Examples include techniques associated with mapping system memory physical addresses to isolation domains for uniform memory access (UMA) by a system. Examples include mapping separate system memory physical addresses ranges associated with memory devices communicatively coupled with at least one compute die of the system through an input/output (I/O) die of the system. The separate system memory physical addresses to be mapped to isolation domains and address decoder information is generated to indicate the mapping of the separate system memory physical address ranges to the isolation domains.
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
67.
PORT SELECTION FOR HARDWARE QUEUING MANAGEMENT DEVICE
In an embodiment, a processor may include multiple processing engines and multiple hardware queue manager (HQM) devices. Each HQM device is to queue data requests for a different subset of the plurality of processing engines. At least one processing engine is to execute a first set of instructions to: detect a first enqueue instruction to enqueue data in a first HQM device of the plurality of HQM devices; in response to a detection of the first enqueue instruction, perform a look-up of the first HQM device in a data structure to determine a recommended port for the first HQM device; and transmit the first enqueue instruction using the recommended port for the first HQM device.
An apparatus to facilitate hardware support for n-dimensional matrix load and store instructions is disclosed. The apparatus includes a graphics processor comprising a general-purpose graphics execution resources, the general-purpose graphics execution resources including a matrix accelerator, the matrix accelerator configured to perform a matrix operation on a plurality of tensors stored in a memory; and circuitry configured to facilitate access to the memory by the general-purpose graphics execution resources, wherein the circuitry is configured to: receive a request to access a tensor of the plurality of tensors; and generate a n-dimensional block access message along a dimension of n>2 of the tensor, the n-dimensional block access message to enable access to the tensor by the matrix accelerator, wherein the n-dimensional block access message comprises an application programming interface (API) descriptor defining a tensor width, tensor pitch, tensor block offset, and a tensor block size of the tensor.
A host device comprising first circuitry to receive one or more packets sent by a communication device over a serial communication interface between the communication device and the host device, wherein the one or more packets comprise media configuration information stored in a memory of the communication device and an indication of a mapping of the memory of the communication device; and second circuitry to transmit data packets over the serial communication interface after the host device has been configured based on the media configuration information.
A mechanism is described for facilitating training and deploying of pose regression in neural networks in autonomous machines. A method, as described herein, includes facilitating capturing, by an image capturing device of a computing device, one or more images of one or more objects, where the one or more images include one or more training images associated with a neural network. The method may further include continuously estimating, in real-time, a present orientation of the computing device, where estimating includes continuously detecting a real-time view field as viewed by the image capturing device and based on one or more images. The method may further include applying pose regression relating to the image capturing device using the real-time view field.
A deep neural network (DNN) accelerator may execute in-place deep learning operations. The DNN accelerator may write an input tensor of a DNN layer into a memory that includes a plurality of memory entries storing input elements in the input tensor. The DNN accelerator may compute an output tensor of the layer using the input tensor and another tensor, e.g., by performing multiply-accumulate operations on the input tensor and the other tensor. The DNN accelerator may use a scatter map to write the output tensor into the memory and generate a gather map to be used for reading the output tensor in the next layer. The DNN accelerator may remove an input element from a memory entry and store an output element in the memory entry. The position of the input element in the input tensor may be different from the position of the output element in the output tensor.
An apparatus of a communication device, the apparatus may include: an interface configured to transmit a sensing signal and receive a reflected sensing signal; and a processor configured to: determine a sensing signal configuration of a further communication device;
estimate a sensing interference of the further communication device based on the sensing signal configuration; and perform an interference cancellation on the reflected sensing signal using the sensing interference.
H04W 72/541 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité en utilisant le niveau d’interférence
An apparatus including an interface configured to receive first sensor data representative of a monitoring of an environment according to a first modality and second sensor data representative of a monitoring of the environment according to a second modality; and a processor configured to provide the first sensor data to an input of a first trained generative model configured to generate first output data comprising a first extracted feature of the first sensor data in a latent space; provide the second sensor data to an input of a second trained generative model configured to generate second output data comprising a second extracted feature of the second sensor data in the latent space; and combine the first output data and the second output data to generate a combined feature.
A microelectronic assembly with a bridge die and through-assembly conductive vias may enable higher performance connectivity of dies or die stacks. In one example, an assembly includes a first IC structure (e.g., a bridge die) over and coupled with a circuit board, a second IC structure (e.g., a substrate) over the first IC structure, and a plurality of coplanar dies or die stacks between and bonded with the first IC structure and the second IC structure. Conductive vias may be formed through the dies or die stacks after attaching the dies or die stacks to the first or second IC structures, where a conductive via through a die or die stack may extend through the die or die stack so that a first portion of the conductive via is coplanar with the side or face of the die or die stack that is bonded with the first IC structure.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
Microelectronic assemblies may include through-assembly conductive vias of varying depth to couple dies or die stacks with one another via a bridge die and/or substrate. In one example, an assembly includes an interconnect structure (e.g., a bridge die) including conductive contacts on a first side and one or more integrated circuit (IC) structures bonded with a second side, where an IC structure includes one or more dies. The assembly may include a first conductive via with a first bottom end in the interconnect structure and a first top end opposite the first bottom end, and a second conductive via with a second bottom end in the interconnect structure and a second top end opposite the second bottom end, where the first top end is in a first plane and the second top end is in a second plane that is different from the first plane.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Back-end-of-line (BEOL) interconnect fuses are described. In an example, an integrated circuit structure includes a first dielectric layer having first conductive lines therein. A second dielectric layer is over the first dielectric layer and has first conductive vias and second conductive lines therein. One of the second conductive lines is a fuse element. A third dielectric layer is over the second dielectric layer and has second conductive vias and third conductive lines therein. The second dielectric layer has a lower dielectric constant than the first dielectric layer and than the third dielectric layer, or the second dielectric layer has a lower thermal conductivity than the first dielectric layer and than the third dielectric layer, or both.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
77.
STACKED SEMICONDUCTOR DIE ARCHITECTURE WITH DIES STACKED ORTHOGONAL TO A BASE DIE OR SUBSTRATE
Microelectronic assemblies with a die stack positioned such that a face of each die in the stack is orthogonal to a face of a base are disclosed. Each die has a first face and a second face opposite the first face. The die stack includes multiple dies, with the faces of each die parallel to the faces of the other dies in the die stack. The die stack is positioned on the base such that the faces of each die are substantially orthogonal to the face of the base. Each die in the die stack can have a corresponding conductive contact, and the conductive contact on each die in the die stack can be coupled to a conductive contact on the base via an interconnect. The interconnect can be a solder joint, such as a solder bump or solder ball.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
78.
PROVIDING BYTECODE-LEVEL PARALLELISM IN A PROCESSOR USING CONCURRENT INTERVAL EXECUTION
In one embodiment, an apparatus comprises: a first plurality of registers to store information of at least a main sequence; a second plurality of registers to store information of at least one concurrent interval, the at least one concurrent interval independent of the main sequence, where the second plurality of registers are accessible only by instructions of the at least one concurrent interval and the first plurality of registers are accessible by instructions of the main sequence and the at least one concurrent interval; and an execution circuit coupled to the first register file and the second register file, the execution circuit to execute the instructions of the main sequence and the at least one concurrent interval. Other embodiments are described and claimed.
An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.
H04N 13/279 - Générateurs de signaux d’images à partir de modèles 3D d’objets, p. ex. des signaux d’images stéréoscopiques générés par ordinateur les positions des points de vue virtuels étant choisies par les spectateurs ou déterminées par suivi
H04N 13/344 - Affichage pour le visionnement à l’aide de lunettes spéciales ou de visiocasques avec des visiocasques portant des affichages gauche et droit
H04N 13/383 - Suivi des spectateurs pour le suivi du regard, c.-à-d. avec détection de l’axe de vision des yeux du spectateur
Methods, apparatus, systems and articles of manufacture to identify a video decoding error are disclosed. An example apparatus includes an atlas generator to generate atlas data for one or more atlases generated from input views of video; a hash generator to: perform a hash operation on the atlas data to generate a hash value; and include the hash value in a message; and a multiplexer to combine the one or more atlases, coded atlas data corresponding to the atlas data, and the message to generate a video bitstream.
H04N 19/65 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant la tolérance aux erreurs
H04N 19/597 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage prédictif spécialement adapté pour l’encodage de séquences vidéo multi-vues
Examples described herein relate to a network interface device comprising a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry to: based on at least partial processing of packets by a transmit packet processing pipeline, perform reordering of the packets based on associated egress time stamps, wherein the partial processing of the packets by the transmit packet processing pipeline comprises at least packet parsing and provide the packets for egress from a port based on the associated egress time stamps.
Examples described herein relate to: an interface and circuitry to: monitor a bus for a particular message and based on detection of the particular message, replace the particular message with an invalid portion and provide the invalid portion to a receiver, wherein the particular message comprises a command and wherein the receiver comprises an Embedded Multi-Media Card (eMMC). In some examples, the circuitry comprises a platform root of trust (PRoT), a management controller, a multiplexer, or a host system.
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
83.
INTEGRATED MEMORY AND COMPUTE SYSTEM FOR OPTIMIZED NEURAL NETWORK COMPUTATION
An integrated circuit (IC) device may implement a deep neural network (DNN). The IC device may be a three-dimensional (3D) integrated system that includes a memory die and logic die. The memory die may include memory blocks, such as sequential random-access memory blocks or a sequential read-only memory blocks. The logic die may include an interface unit, a vector operation unit, compute units (e.g., multiply-accumulate units), and an interconnect fabric with adders. The interface unit may receive the input of the DNN and transfer the input to the vector operation unit. The vector operation unit may perform one or more vector operations of the DNN based on the input. The compute units and adders may perform matrix multiplication operations of the DNN based on the vector operation unit's output. Each memory block may be coupled with a compute unit through a via.
A deep neural network (DNN) accelerator may include one or more multi-precision converters for precision conversion during DNN execution. A multi-precision converter may include an input extractor for extracting an exponent and mantissa from an input value, an input generator for generating an intermediate exponent and an intermediate mantissa from the extracted exponent and the extracted mantissa, a group of exponent converts for converting the intermediate exponent to exponents of different input or output precisions, an exponent selector for selecting one of the exponent converters for a particular input or output precision, a group of mantissa converters for converting the intermediate mantissa to mantissas of different input or output precisions, a mantissa selector for selecting one of the mantissa converter for a particular input or output precision. An output value is generated from the exponent generated in the selected exponent converter and the mantissa generated in the selected mantissa converter.
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/552 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de puissances ou racines
G06F 7/48 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
85.
EMBEDDING A STATE SPACE MODEL ON MODELS-ON-SILICON HARDWARE ARCHITECTURE
A state space model with selective updates, also referred to as a Mamba-based block, in a Mamba-based model can be embedded onto a silicon chip. Specialized hardware modules in a models-on-silicon chip, such as an optimized selective scan unit and an optimized 1D convolution unit, can perform the operations of the selective state space model of the Mamba-based model. These modules individually and collectively enhance processing speed, power efficiency, and overall performance. The parameters such as weights of the Mamba-based model are arranged in a sequential order in one or more sequential read memories according to a predetermined timing sequence. By embedding the selective state space model onto the models-on-silicon architecture, which excels in managing larger input context sizes, this solution transforms the Mamba-based model into a highly viable and efficient option for AI tasks being performed on resource-constrained devices.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
Apparatus and method for a low-power quantum controller. For example, one embodiment of an apparatus comprises: a low-power quantum control chip to process a first portion of quantum program code associated with a quantum computing application, the low-power quantum control chip configurable within a dilution refrigeration unit, the low-power quantum control chip comprising: an interface to couple the quantum control chip to a computer which is to execute a second portion of the quantum program code associated with the quantum computing application; a Static Random Access Memory (SRAM) to store the first portion of quantum program code; a compute unit to execute the first portion of quantum program code during execution of the quantum computing application and responsively generate control signals; routing hardware logic to route the control signals; a plurality of digital signal processor (DSP) units coupled to the routing hardware logic, at least one DSP of the plurality of DSPs to receive one or more of the control signals and responsively generate analog qubit control signals to control qubits of a quantum processor.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
87.
EPITAXIAL SOURCE AND DRAIN REGIONS WITH LOW-K INNER SPACERS
Techniques are provided herein to form an integrated circuit having semiconductor devices with low-k inner dielectric spacers between semiconductor bodies (e.g., nanoribbons, nanowires, or nanosheets). The dielectric spacers may include any suitable low-k dielectric material. Additionally, the inner dielectric spacers may be formed after the formation of source or drain regions, which improves the stress profile of the source or drain regions against the semiconductor bodies. In one such example, semiconductor bodies extend in a first direction between source or drain regions and a gate structure extends in a second direction over the semiconductor bodies between the source or drain regions. Inner spacers separate the gate structure from the source or drain regions along the first direction. The inner spacers may include a low-k dielectric material, such as silicon dioxide. In some examples, the inner spacers extend outwards beyond the ends of the semiconductor bodies along the first direction.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Methods, apparatus, systems, and articles of manufacture are disclosed to synchronize tasks. An example apparatus to synchronize tasks includes at least one memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to identify a first task frequency associated with a first task, the first task executed by the computing device, the first task outputting first data at first times, identify a second task frequency associated with a second task, the second task executed by the computing device, the second task outputting second data at second times, when the second task frequency is different from the first task frequency, calculate a first difference between the second task frequency and the first task frequency, and adjust at least one of the first task frequency or the second task frequency based on the first difference such that the second times match the first times.
Techniques are provided for dynamic noise suppression. A methodology implementing the techniques according to an embodiment includes generating a magnitude spectrum and a phase spectrum of an input audio signal comprising speech and dynamic noise. The method also includes employing a temporal convolution network (TCN) to generate a separation mask based on the magnitude spectrum. The TCN comprises depth-wise (DW) convolution layers, each DW convolution layer including a state buffer to store a number of previous states of the associated DW convolution layer. The number of stored previous states is based on a dilation factor of the associated DW convolution layer. The method further includes multiplying the separation mask with the magnitude spectrum to separate the speech from the dynamic noise to obtain a denoised magnitude spectrum. The method further includes reconstructing the input audio signal with reduced dynamic noise based on the denoised magnitude spectrum and the phase spectrum.
G10L 21/0232 - Traitement dans le domaine fréquentiel
G10L 25/30 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes caractérisées par la technique d’analyse utilisant des réseaux neuronaux
G10L 25/78 - Détection de la présence ou de l’absence de signaux de voix
H04R 3/04 - Circuits pour transducteurs pour corriger la fréquence de réponse
90.
METHOD AND APPARATUS FOR HIGH-PERFORMANCE PAGE-FAULT HANDLING FOR MULTI-TENANT SCALABLE ACCELERATORS
Apparatus and method for high-performance page fault handling. For example, one embodiment of an apparatus comprises: one or more accelerator engines to process work descriptors submitted by clients to a plurality of work queues; fault processing hardware logic associated with the one or more accelerator engines, the fault processing hardware logic to implement a specified page fault handling mode for each work queue of the plurality of work queues, the page fault handling modes including a first page fault handling mode and a second page fault handling mode.
A mechanism is described for image frame rendering. An apparatus of embodiments, as described herein, includes one or more processors to receive a plurality of past image frames including a plurality of pixels, receive a predicted optical flow, generate a predicted frame and a confidence map associated with the predicted frame based on the plurality of past image frames and the predicted optical flow, render a first set of the plurality of pixels in the predicted frame based on the confidence map and adding the rendered pixels to the predicted frame to generate a final frame.
Embodiments are generally directed to a system and method for adapting executable object to a processing unit. An embodiment of a method to adapt an executable object from a first processing unit to a second processing unit, comprises: adapting the executable object optimized for the first processing unit of a first architecture, to the second processing unit of a second architecture, wherein the second architecture is different from the first architecture, wherein the executable object is adapted to perform on the second processing unit based on a plurality of performance metrics collected while the executable object is performed on the first processing unit and the second processing unit.
G06F 9/448 - Paradigmes d’exécution, p. ex. implémentation de paradigmes de programmation
G06F 16/215 - Amélioration de la qualité des donnéesNettoyage des données, p. ex. déduplication, suppression des entrées non valides ou correction des erreurs typographiques
G06T 1/20 - Architectures de processeursConfiguration de processeurs p. ex. configuration en pipeline
Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
The disclosure described herein generally relates to a foldable input/output (I/O) port of a computing device, including: a connector board electrically connected to a circuit board of the computing device; one or more I/O connectors arranged on the connector board, wherein the one or more I/O connectors are electrically connected to the connector board and capable of receiving one or more external connectors when the foldable I/O port is in an open configuration; and a housing portion, pivotably connected to the computing device, wherein the housing portion is capable of housing the connector board and the one or more I/O connectors.
Provided is a non-transitory machine-readable medium comprising machine-readable instructions which, when the carried out on an apparatus, cause the apparatus to receive first data indicating a security policy for an application to be carried out on the apparatus. The instructions further cause the apparatus to instruct, based on the security policy, a security advisor to determine a security appraiser to enforce the security policy. The instructions further cause the apparatus to instruct, upon reception of second data indicating the determined security appraiser, the determined security appraiser to determine whether third data provided for enforcing the security policy is suitable to enforce the security policy.
Systems, methods, and apparatuses relating sparsity based FMA. In some examples, an instance of a single FMA instruction has one or more fields for an opcode, one or more fields to identify a source/destination matrix operand, one or more fields to identify a first plurality of source matrix operands, one or more fields to identify a second plurality of matrix operands, wherein the opcode is to indicate that execution circuitry is to select a proper subset of FP8 data elements from the first plurality of source matrix operands based on sparsity controls from a first matrix operand of the second plurality of matrix operands and perform a FMA.
A system to support time sensitive networking (TSN) in a 5G system is described. The TSN application function (AF) sends to a device-side translator a Port Management Information Container (PMIC) and port number that has a Stream Identification type value and Stream Identification controlling parameters that depend on the Stream Identification type value for per-stream policing and filtering in a distributed bridge. During establishment of the bridge, the network-side translator port numbers are provided to the TSN AF in a Bridge Management Information Container (BMIC). Any PDU session of the bridge is able to be selected for Ethernet port and Bridge management procedures between the network-side translator and the TSN AF.
Various embodiments are generally directed to convolutional neural networks (CNN). A calibration dataset and a pretrained CNN comprising 32-bit floating point weight values may be sampled to generate an input activation tensor and a weight tensor. A transformed input activation tensor may be generated by multiplying the input activation tensor and an input matrix to generate a transformed input activation tensor. A transformed weight tensor may be generated by multiplying the weight tensor and a weight matrix. A scale factor may be computed for each transformed tensor. An 8-bit CNN model including the scale factors may be generated.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
The present disclosure provides an apparatus and method of guided neural network model for image processing. An apparatus may comprise a guidance map generator, a synthesis network and an accelerator. The guidance map generator may receive a first image as a content image and a second image as a style image, and generate a first plurality of guidance maps and a second plurality of guidance maps, respectively from the first image and the second image. The synthesis network may synthesize the first plurality of guidance maps and the second plurality of guidance maps to determine guidance information. The accelerator may generate an output image by applying the style of the second image to the first image based on the guidance information.
A user may register with a fleet system responsible for remote management of a fleet of endpoint devices. The fleet system can determine a level of trust for the user based on information associated with an email address of the user and other information and register the user if the determined level of trust is sufficient. The registered user can request an activation token to be used for provisioning an endpoint device for consent-free out-of-band management. An endpoint device can be provisioned by the user submitting the activation token to the fleet service, the fleet service sending the activation token to the endpoint device, the endpoint device generating an ownership voucher request that includes the activation token, the fleet service verifying and validating the ownership voucher request, the fleet service returning a signed ownership voucher to the endpoint device, and the endpoint device verifying the signed ownership voucher.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
