Systems and methods for background replacement in video using an occluded background prior that is dynamically maintained across frames. An input video frame is received at a separator, which reads previous background data from memory and generates a foreground matting (a per-pixel probability map indicating the foreground subject) based on the input frame and the previous background data. The system determines weights from the foreground matting and an accumulation map (a temporal exposure/confidence history), and updates the previous background data based on a weighted blending of the input frame and the previous background data. Updates for pixels classified as foreground are withheld to prevent leakage of the foreground subject into the background model. The updated background data is stored in memory for subsequent frames. Based on the foreground matting, a background replacer generates an output frame in which the foreground is preserved, and the background is replaced or modified.
Systems, apparatus, articles of manufacture, and methods to implement power control during media playback are disclosed. An example disclosed system manages power consumption of media engine circuitry in a compute device during media playback by monitoring both media playback status and human presence. Human presence may be determined through interface events and camera-based face detection combined with an engagement condition. When media playback is active and a valid human presence is detected, the media engine operates in an active state, enabling decoding, post-processing and buffering. When playback is active, but no valid human presence is detected, the media engine remains in a low power state by keeping the decoder active for frame timing but disabling post-processing and buffering, dropping frames. This selective power state control enables efficient energy use of the compute device and its display while maintaining appropriate media delivery.
Techniques for intra-bin processor differentiation. For example, an example method comprises: binning a plurality of processors across a plurality of performance bins based on detected performance characteristics; setting fuses of each processor of the plurality of processors to specify default performance values in accordance with the detected performance characteristics, the default performance values including values defining a default voltage-frequency curve; and providing a software-based or firmware-based tool to evaluate the plurality of processors, the software-based or firmware-based tool to: determine a range of performance-related capabilities of each processor of the plurality of processors within one or more bins of the plurality of performance bins, including new performance values different from the default performance values; and store the new performance values in a persistent storage, the new performance values to replace one or more of the default performance values during a system initialization process.
Embodiments attempt to solve challenges in a wireless communications system. Embodiments describe various techniques, systems, and devices to support simultaneous reception information and scheduling restriction information for user equipment in a 3GPP 5G NR or 6G system, among other wireless communications systems. Other embodiments are described and claimed.
In some embodiments, provided is a performance monitoring event relating to conditional instructions used in executing code. In some embodiments, conditional instructions may be monitored as to whether their condition was taken. Another conditional instruction event is whether a conditional instruction's condition was the last source predicate to be ready for the overall instruction execution.
The present disclosure provides a resilient (radio) access network ((R)AN) slicing framework encompassing a resource planning engine and distributed dynamic slice-aware scheduling modules at one or more network access nodes, edge compute nodes, or cloud computing service. The resilient (R)AN slicing framework includes resource planning and slice-aware scheduling, as well as signaling exchanges for provisioning resilient (R)AN slicing. The intelligent (R)AN slicing framework can realize resource isolation in a more efficient and agile manner than existing network slicing technologies. Other embodiments may be described.
Techniques are described for fan speed control with a secondary thermal management protocol. By way of example, a graphics processor includes thermal management circuitry to: thermal management circuitry to: implement a primary thermal management protocol to set a first target speed for one or more cooling fans based on a measured package temperature; implement a secondary thermal management protocol in response to detecting a temperature measurement associated with the memory or a voltage regulator exceeding a corresponding temperature threshold, the secondary thermal management protocol to set a second target speed for the one or more cooling fans or a different set of cooling fans; and revert to implementing to the primary thermal management protocol when one or more temperature measurements associated with the memory or the voltage regulator drop below the corresponding temperature threshold.
Examples include techniques to support fine-grained thread modes in a processor core. The examples include use of circuitry located at or with a front-end unit of a processor core's instruction execution pipeline circuitry. The circuitry receives an indication of whether the front-end unit is to be configured for a single thread or for multiple threads in order to process branch predictions, instruction cache lookups and instruction decoding for the single thread or for the multiple threads. The circuitry can then cause hardware resources of the front-end unit to be partitioned based on the received indication.
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to quantize a group of input data using a first quantization algorithm to form a first group of quantized data, quantize the group of input data using a second quantization algorithm to form a second group of quantized data, quantize the group of input data using a third quantization algorithm to form a third group of quantized data, the third quantization algorithm different from the first quantization algorithm and the second quantization algorithm, determine a first quantization error of the first group of quantized data, determine a second quantization error of the second group of quantized data, and determine a third quantization error of the third group of quantized data.
A method and system for deterministic communications between a plurality of interconnected semiconductor chips. The system includes a plurality of semiconductor chips, and a controller coupled to each of the plurality of semiconductor chips, respectively. The controller is configured to transfer data from one semiconductor chip to another. Each of the semiconductor chips and the controller include a respective clock, and the controller is configured to synchronize the clocks of the plurality of semiconductor chips. The controller schedules and manages data flows from and to the plurality of semiconductor chips for deterministic communications between the plurality of semiconductor chips. The controller may implement IEEE Time Sensitive Networking (TSN) protocol for scheduling and managing the data flows between the plurality of semiconductor chips.
An apparatus is disclosed. The apparatus comprises one or more processors to receive a request to trigger a system management interrupt (SMI), execute policy shim code to enforce access control policy in a first privilege level and dispatch the SMI to shield code to enforce the access security policy to perform a system management mode (SMM) and execute the shield code to perform the SMM, including retrieving an operating system (OS) memory preserved warm reset (MPWR) context, saving the context and issuing a warm reset.
Examples include techniques for portbinding micro-operations (uops) in a processor core. The examples include use of circuitry located at or with instruction execution pipeline circuitry at a processor core. The circuitry can use individual counts of uops that have been previously bound to execution ports of the process to determine a port order to bind uops included a line of uops and then bind the uops included in the line to the execution ports based on the port order and an assigned class.
Gate-all-around integrated circuit structures having a doped subfin, and methods of fabricating gate-all-around integrated circuit structures having a doped subfin, are described. For example, an integrated circuit structure includes a subfin structure having well dopants. A vertical arrangement of horizontal semiconductor nanowires is over the subfin structure. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires, the gate stack overlying the subfin structure. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires.
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
Disclosed herein is an apparatus of a communication device, the apparatus includes a processor configured to estimate noise power characteristics within a frequency band based on a received signal comprising a plurality of subcarriers within the frequency band, wherein the noise power characteristics comprises a plurality of noise samples. The processor is also configured to estimate a noise covariance matrix by averaging a number of noise samples of the plurality of noise samples. The processor is also configured to apply a whitening that is based on the noise covariance matrix to subsequent received signals.
Example apparatus disclosed herein include an array of processor elements, the array including rows each having a first number of processor elements and columns each having a second number of processor elements. Disclosed example apparatus also include configuration registers to store descriptors to configure the array to implement a layer of a convolutional neural network based on a dataflow schedule corresponding to one of multiple tensor processing templates, ones of the processor elements to be configured based on the descriptors to implement the one of the tensor processing templates to operate on input activation data and filter data associated with the layer of the convolutional neural network to produce output activation data associated with the layer of the convolutional neural network. Disclosed example apparatus further include memory to store the input activation data, the filter data and the output activation data associated with the layer of the convolutional neural network.
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
This disclosure describes systems, methods, and devices related to generating visual quality metrics for encoded video frames. A method may include generating respective first visual quality metrics for pixels of an encoded video frame; generating respective second visual quality metrics for the pixels, the respective first visual quality metrics and the respective second visual quality metrics indicative of estimated human perceptions of the encoded video frame; generating a pixel block-based weight for the respective first visual quality metrics; generating a frame-based weight for the respective second visual quality metrics; and generating, based on the respective first visual quality metrics, the pixel block-based weight, the respective second visual quality metrics, and the frame-based weight, a human visual score indicative of a visual quality of the encoded video frame.
H04N 19/196 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par le procédé d’adaptation, l’outil d’adaptation ou le type d’adaptation utilisés pour le codage adaptatif étant spécialement adaptés au calcul de paramètres de codage, p. ex. en faisant la moyenne de paramètres de codage calculés antérieurement
H04N 19/146 - Débit ou quantité de données codées à la sortie du codeur
H04N 19/159 - Type de prédiction, p. ex. prédiction intra-trame, inter-trame ou de trame bidirectionnelle
H04N 19/172 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant une image, une trame ou un champ
H04N 19/176 - Procédés ou dispositions pour le codage, le décodage, la compression ou la décompression de signaux vidéo numériques utilisant le codage adaptatif caractérisés par l’unité de codage, c.-à-d. la partie structurelle ou sémantique du signal vidéo étant l’objet ou le sujet du codage adaptatif l’unité étant une zone de l'image, p. ex. un objet la zone étant un bloc, p. ex. un macrobloc
17.
APPARATUS AND METHOD FOR WARM RESET CUSTOMIZATION ON FIRMWARE FAILURES
Apparatus and method for warm reset customization on firmware failures. For example, one embodiment of a graphics processor comprises: graphics processing circuitry process instructions (e.g., graphics and/or compute instructions); and a reset microcontroller coupled to the graphics processing circuitry, the reset microcontroller, in response to a triggering event, to load a clean firmware image in a known valid state, wherein the clean firmware image, following loading, is to be used to boot the graphics processor to an operational state.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
Examples include techniques for use of a distributed throttle architecture to mitigate voltage droop or current spikes The examples include use of circuitry distributed to portions of instruction execution pipeline circuitry capable of being arranged to execute one or more pipeline stages at a processor core, the circuitry to cause a throttle indication to be sent to the portions of the instruction execution pipeline circuitry based on received information that indicate energy events at the portions of instruction execution pipeline circuitry over a period of time.
Methods and apparatus relating to a lazy Return Stack Buffer (RSB) migration are described. In an embodiment, a processor includes a Speculative Return Stack Buffer (SRSB) and a Committed Return Stack Buffer (CRSB). The processor further includes logic circuitry to copy an entry from the SRSB (based at least in part on an SRSB read pointer) to an entry of the CRSB (based at least in part on a CRSB write pointer). The SRSB read pointer indicates a next SRSB entry to copy to the CRSB and the CRSB write pointer indicates a next CRSB entry to write to from the SRSB. Other embodiments are also disclosed and claimed.
An antenna array structure may include a plurality of end-fire antennas, the antennas are disposed next to each other in an arc shape, wherein the plurality of antennas comprises one or more directional antennas, wherein the plurality of antennas comprises one or more Yagi-Uda antennas, and wherein the plurality of antennas comprises one or more Leaky-Wave antennas.
H01Q 21/29 - Combinaisons d'unités d'antennes de types différents interagissant entre elles pour donner une caractéristique directionnelle désirée
H01Q 21/20 - Réseaux d'unités d'antennes, de même polarisation, excitées individuellement et espacées entre elles les unités étant espacées le long d'un trajet curviligne ou adjacent à celui-ci
H01Q 19/30 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant un dispositif secondaire constitué par plusieurs éléments conducteurs sensiblement rectilignes l'élément actif primaire étant alimenté par son centre et sensiblement rectiligne, p. ex. antenne Yagi
H01Q 19/10 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant des surfaces réfléchissantes
H01Q 1/42 - Enveloppes non intimement mécaniquement associées avec les éléments rayonnants, p. ex. radome
H01Q 1/27 - Adaptation pour l'utilisation dans ou sur les corps mobiles
21.
TECHNIQUES TO IMPLEMENT A DATA-AWARE CACHE REPLACEMENT POLICY
Examples include techniques to implement a data-aware cache replacement policy. The techniques include indicating, to a cache controller, that data to be included in a cache line is likely to be reused. The indication of likely-to-be-reused data is to be used by the cache controller to determine when the data is to be evicted or replaced in the cache.
G06F 12/126 - Commande de remplacement utilisant des algorithmes de remplacement avec maniement spécial des données, p. ex. priorité des données ou des instructions, erreurs de maniement ou repérage
G06F 12/0897 - Mémoires cache caractérisées par leur organisation ou leur structure avec plusieurs niveaux de hiérarchie de mémoire cache
G06F 12/123 - Commande de remplacement utilisant des algorithmes de remplacement avec listes d’âge, p. ex. file d’attente, liste du type le plus récemment utilisé [MRU] ou liste du type le moins récemment utilisé [LRU]
22.
PROGRAMMABLE GPU COMMAND BUFFERS USING MUTABLE COMMAND LISTS
Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and/or an executable jump command.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/32 - Formation de l'adresse de l'instruction suivante, p. ex. par incrémentation du compteur ordinal
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
Examples described herein relate to an interface and a core coupled to the interface, wherein based on a configuration, the core is to respond to an interrupt indicating an error by outputting error data to a management controller while permitting thread execution on the core. In some examples, based on the configuration, the core is to invoke the management controller to handle errors and not enter System Management Mode (SMM).
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p. ex. des interruptions ou des opérations d'entrée–sortie
24.
SYSTEM(S), METHOD(S) AND APPARATUS FOR JOINTLY PERFORMING RETRIEVAL AUGMENTED GENERATION AND AI MODEL FINE-TUNING
Disclosed systems and methods optimize retrieval augmented generation (RAG) pipelines and AI model fine-tuning through bidirectional feedback integration. During RAG operations, question-answer (QA) and question-context (QC) pairs are automatically generated from document ingestion and user feedback, then expert-verified for quality assurance. Accumulated verified QA pairs fine-tune large language models (LLMs), while QC pairs fine-tune embedding and re-ranker models when predefined thresholds are met. Fine-tuned models exceeding performance thresholds replace corresponding RAG pipeline components. Successfully encoded training data is optionally removed from vector databases, reducing storage requirements and retrieval latency. This disclosed method may include low-rank adaptation (LoRA) to enable low bit (e.g., INT4) operations without accuracy degradation. RAG operations generate high-quality training data to address fine-tuning's data acquisition challenge, while fine-tuned models reduce RAG's resource requirements.
Building a robust and effective knowledge graph-based retrieval-augmented generation (RAG) system has two technical challenges: (1) constructing high-quality subgraphs and (2) pruning subgraphs without losing critical information. To address these challenges, a multi-stage framework involving enhanced initial node retrieval and query-aware subgraph pruning can be implemented. Initial node retrieval can include fusing results from vector similarity search and symbolic text search to produce initial nodes that are more robust to lexical variation. Query-aware subgraph pruning can include calculating node prizes and edge prizes based on query-conditioned, learnable prize parameters to produce compact and task-relevant subgraphs. The pruned subgraphs and the query are used as inputs in a joint graph neural network and large language model inference process to produce an evidence-grounded answer to the query.
G06F 16/383 - Recherche caractérisée par l’utilisation de métadonnées, p. ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement utilisant des métadonnées provenant automatiquement du contenu
A multi-feed antenna device includes a monopole antenna, having an antenna portion; a first antenna extension of a first length, extending from the antenna portion; a second antenna extension of a second length, less than the first length, extending from the antenna portion; a slot antenna, including a first slot of third length; a second slot of a fourth length, greater than the third length; a first antenna feed, coupled to the monopole antenna; a second antenna feed, coupled to the slot antenna; and a ground plane, common to both the monopole antenna and the slot antenna.
H01Q 5/40 - Structures imbriquées ou entrelacéesDispositions combinées ou présentant un couplage électromagnétique, p. ex. comprenant plusieurs éléments rayonnants alimentés sans connexion commune
H01Q 9/30 - Antennes résonnantes avec alimentation à l'extrémité d'un élément actif allongé, p. ex. unipôle
The present disclosure generally relates to a device including a substrate, a chip including a first chip surface and a bottom chip surface which is configured orthogonal to the first chip surface, wherein the chip includes sets of chiplets spaced apart from each other, wherein each set of chiplets includes a first surface and a bottom surface, and wherein chiplets in the sets of chiplets are vertically stacked to render the first surface parallel to the first chip surface and the bottom surface parallel to the bottom chip surface, a metal redistribution layer electrically coupled to the bottom chip surface; and solder bumps configured between the metal redistribution layer and the substrate to electrically couple the metal redistribution layer to the substrate. A method is also described.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/06 - ConteneursScellements caractérisés par le matériau du conteneur ou par ses propriétés électriques
H01L 23/08 - ConteneursScellements caractérisés par le matériau du conteneur ou par ses propriétés électriques le matériau étant un isolant électrique, p. ex. du verre
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
28.
LOSSLESS COMPRESSION OF LLM PARAMETERS WITH GROUPED HUFFMAN ENCODING
Provided herein are techniques to performing lossless compression on neural network model parameters using grouped Huffman encoding. One embodiment provides a graphics processor comprising a host interface, a graphics processing cluster including a plurality of processing resources, at least one processing resource of the plurality of processing resources configured to receive a decode table and plurality of blocks of encoded parameters of a neural network model, perform a parallel Huffman decoding operation on the plurality of blocks of encoded parameters based on the decode table to concurrently decode multiple blocks of the plurality of blocks of encoded parameters, the plurality of blocks of encoded parameters decoded into a plurality of parameter groups, and unpack each of the plurality of parameter groups into a plurality of parameters of the neural network model during an inference operation performed via the neural network model.
Embodiments disclosed herein include an apparatus that includes a glass substrate with a first surface and a second surface opposite from the first surface. In an embodiment, an opening is provided through a thickness of the substrate, and a first via is in the opening. In an embodiment, a first layer is on the first surface, where the first layer fills a first portion of the opening adjacent to the first via. In an embodiment, a second via is through the first layer in the opening, and the second via is electrically coupled to the first via. In an embodiment, a second layer is on the second surface, and the second layer fills a second portion of the opening adjacent to the first via. In an embodiment, a third via is through the second layer in the opening, and the third via is electrically coupled to the first via.
Systems, apparatuses and methods may provide for technology that includes an analog compute-in-memory (CiM) circuit to determine partial sums associated with multiply accumulate (MAC) operations, a first circuit coupled to an input of the analog CiM circuit, the first circuit to conduct a first scale operation on input data to the analog CiM circuit on a per partial sum basis, and a second circuit coupled to an output of the analog CiM circuit, the second circuit to conduct a second scale operation on output data from the analog CiM circuit on the per partial sum basis.
Apparatus and method for uncertainty-aware code generation using LLMs. For example, one embodiment of a method comprises: generating, by a large language model (LLM) code generator, a plurality of RTL code blocks based on a design prompt; determining syntactical similarities and semantic similarities between pairs of the RTL code blocks; arranging the RTL code blocks into a plurality of clusters based on a combination of the syntactical similarities and the semantic similarities; generating uncertainty estimates indicating levels of uncertainty associated with one or more clusters of the plurality of clusters; and determining whether to synthesize an RTL output using one or more of the RTL code blocks based on the uncertainty estimates.
An apparatus and method for efficient matrix processing in a clustered processor core. For example, one embodiment of a processor comprises: a front end to fetch and decode a plurality of instruction strands to generate a corresponding plurality of microoperations, including matrix processing microoperations; a reservation station to schedule the microoperations for execution in accordance with a first scheduling mode; out-of-order execution circuitry to execute the microoperations; and a detector to determine a density of the matrix processing microoperations within an interval and to signal to the reservation station to implement a second scheduling mode when the density of matrix processing microoperations reaches or exceeds a first threshold.
Nanoribbon-based transistor fabrication techniques that use a sacrificial layer over the nanoribbon stack may enable more uniform deposition of the gate electrode material over the top nanoribbon in addition to protecting the top nanoribbon from damage resulting from subsequent processing. In one example, the technique may involve depositing a sacrificial layer (e.g., a dielectric material) over a stack of alternating layers of semiconductor material that will subsequently be patterned into a fin and formed into a nanoribbon stack. After patterning the stack into a fin and releasing the nanoribbons of semiconductor material, the layer of sacrificial material may act as a dummy nanoribbon over the top nanoribbon to enable deposition of the gate electrode material on two sides over the top nanoribbon.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments herein relate to solutions for zeroization of one-time programmable (OTP) fuses which store important data such as security data which should be kept inaccessible to an attacker in the case of a security event. One or more control circuits can ensure that the fuses in an array are provided in a high resistance state in response to the security event. In one approach, the fuses in the array are read to identify fuses in a low resistance state and these fuses are selectively programmed to a high resistance state. In another approach, the fuses are subject to a program bias regardless of whether they are in a low or high resistance state.
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
35.
RESTRICTING INDIRECT CONTROL FLOW TRANSFERS BASED ON COMPATIBILITY OF THE INSTRUCTION POINTERS OF THE INDIRECT CONTROL FLOW TRANSFER INSTRUCTION AND THE TARGET INSTRUCTION
A processor of an aspect includes a decode unit to decode an indirect control flow transfer instruction, the instruction to indicate a register that is to store information to indicate an instruction pointer of a target instruction. An execution unit is to perform operations corresponding to the instruction, including to determine whether at least a first set of bits of an instruction pointer of the indirect control flow transfer instruction are compatible with at least a second set of bits of the instruction pointer of the target instruction. The operations also include to either store the instruction pointer of the target instruction in an instruction pointer storage if the first and second sets of bits are determined to be compatible, or to not store the instruction pointer of the target instruction in the instruction pointer storage if the first and second sets of bits are determined to not be compatible.
Embodiments herein relate to a voltage regulator which controls an output voltage by comparing propagation speeds of signals in first and second voltage controlled oscillators (VCOs). In an example implementation, each VCO includes a chain of buffers in respective stages. One or more of the stages are evaluation stages in which the propagation speeds are compared. The comparison can include determining a stage at which the outputs of the buffers differ. Based on the comparison, an adjustment is made to a power stage, such as by turning on or off power gates of the power stage. Different weights can be associated with the different evaluation stages to affect the magnitude of the adjustment to the power stage.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
Embodiments disclosed herein include an apparatus that includes a substrate that comprises a glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and a via is in the opening. In an embodiment, the via directly contacts a sidewall of the opening at a first location, and a gap is provided between the via and the sidewall of the opening at a second location. In an embodiment, the via is electrically conductive.
Isolation circuitry to implement testing in a semiconductor device is described. In certain examples, a computing system includes a device circuit to generate a resultant and store the resultant in a resultant register; a power supply; a controller circuit to, in response to a power reset indication for the power supply, send a read command to cause the device circuit to return the resultant from the resultant register to the controller circuit; and an isolation circuit comprising a control register that when set to a first value allows the device circuit to receive the read command, and when set to a second value allows the device circuit to receive a test command to cause the device circuit to perform a test operation and ignore the read command.
An apparatus includes a host interface, a network interface, and a programmable circuitry communicably coupled to the host interface and the network interface. The programmable circuitry can include one or more processors to implement network interface functionality, and a discrete trusted platform module (dTPM) to enable the one or more processors to establish a secure boot mechanism for the apparatus, wherein the one or more processors are to instantiate a virtual TPM (vTPM) manager that is associated with the dTPM, the vTPM manager to host vTPM instances corresponding to one or more virtualized environments hosted on at least one of the programmable circuitry or a host device communicable coupled to the apparatus.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
40.
ENHANCED RADIO ACCESS NETWORK SYSTEMS AND METHODS FOR BEAM-BASED LOW-POWER WAKE-UP SIGNAL TRANSMISSION IN WIRELESS COMMUNICATIONS
This disclosure describes systems, methods, and devices for low-power wake-up signaling. A user equipment (UE) device may detect, by a low-power wake-up receiver of the UE device, a first low-power wake-up signal; detect, by the low-power wake-up receiver, a second low-power wake-up signal; and signal, by the low-power wake-up receiver, based on the second low-power wake-up signal, to the main receiver, that the main receiver is to wake up from a sleep state.
This disclosure describes systems, methods, and devices for beam signaling, beam failure recovery (BFR), a transmission configuration indicator (TCI), and multiple transmit/receive point (multi-TRP) operations. A device may set a first coresetpoolindex value for at least one physical uplink control channel (PUCCH) resource; identify a match between the first coresetpoolindex value and a second coresetpoolindex value of a beam indication in downlink control information received by the UE device; and based on the match, update a transmission configuration indicator (TCI) for the at least one PUCCH resource.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
H04W 72/231 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant des couches au-dessus de la couche physique, p. ex. signalisation RRC ou MAC-CE
42.
ASSEMBLY OF 2XD MODULE USING HIGH DENSITY INTERCONNECT BRIDGES
Embodiments disclosed herein include electronic package and methods of forming such packages. In an embodiment, an electronic package comprises a mold layer and a first die embedded in the mold layer. In an embodiment, the first die comprises first pads at a first pitch and second pads at a second pitch. In an embodiment, the electronic package further comprises a second die embedded in the mold layer, where the second die comprises third pads at the first pitch and fourth pads at the second pitch. In an embodiment, a bridge die is embedded in the mold layer, and the bridge die electrically couples the second pads to the fourth pads.
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
H10D 30/62 - Transistors à effet de champ à ailettes [FinFET]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
Examples described herein relate to a memory and a processor, to execute instructions stored in the memory, to: share data between processors by: allocation of different memory-mapped Base Address Register (BAR) windows associated with an Non-Transparent Bridge (NTB) to different memory regions, copy data from the different memory regions to the different BAR windows, and copy data from the different BAR windows to destination memory regions. In some examples, the NTB is consistent with Peripheral Component Interconnect Express (PCIe) and the NTB communicatively couples root complexes of the processors.
An electronic assembly is provided, including a substrate having a first surface and an opposing second surface; a first interconnect in the substrate extending perpendicular to the first surface and the second surface; a second interconnect in the substrate extending perpendicular to the first surface and the second surface; a third interconnect arranged between the first interconnect and the second interconnect; a first contact pad having a first recessed side and coupled to a first terminal of the first interconnect; a subsequent first contact pad having a subsequent first recessed side and coupled to an opposing second terminal of the first interconnect; a second contact pad having a second recessed side and coupled to a first terminal of the second interconnect, and a subsequent second contact pad having a subsequent second recessed side and coupled to an opposing second terminal of the second interconnect.
A system that includes a graphics processing unit (GPU) comprising at least one processor and circuitry. In some examples, the circuitry is to load one or more compressed boot image files from a storage device over an interface, wherein the circuitry is to decompress portions of the one or more compressed boot image files and store the decompressed portions of the one or more compressed boot image files for access by a boot processor.
Information pertaining to real-time sensor-based violations occurring during field operation of a failing integrated circuit component is used in conjunction with transition delay automatic test pattern generation (ATPG) test result information to diagnose the failing integrated circuit component. Real-time sensor-based violations can be captured during field operation at the integrated circuit component, with a sensor-based violation indicating that a sensor value generated by a sensor of the integrated circuit (such as a path margin monitor, temperature monitor, or voltage droop monitor) exceeds a sensor threshold value. Diagnosis of a failing integrated circuit component using real-time sensor-based violation information and transition delay ATPG test result information can aid in identifying a culprit path in the integrated circuit component that is likely responsible for causing the integrated circuit component failure.
The present disclosure generally relates to a device including a substrate including a first surface and a second surface opposite to the first surface, a base die including dies formed on the base die, wherein the base die is electrically coupled to the first surface, and a stiffener adhered to the first surface, wherein the stiffener is peripherally configured to the base die, wherein the stiffener includes a first interconnect which extends through the stiffener from a first stiffener surface to a second stiffener surface, wherein the first interconnect is electrically coupled to the base die via a metal trace embedded in the substrate. A method for forming the device is also described.
H01L 23/18 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A device is provided, including a bridge having a first input/output pin and a second input/output pin; a plurality of traces extending horizontally between the first input/output pin and the second input/output pin, the second input/output pin being coupled to a predetermined one or more of the traces; and a first programmable circuit coupled between the first input/output pin and the plurality of traces. The first programmable circuit may include at least one of a demultiplexing section or a multiplexing section. The demultiplexing section may demultiplex a multiplexed signal from the first input/output pin into at least one subset of signals, and route a respective subset of signals to a corresponding one of the traces. The multiplexing section may multiplex the at least one subset of signals from the plurality of traces into the multiplexed signal, and route the multiplexed signal to the first input/output pin.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
50.
APPARATUS AND METHOD FOR INTEGRATED DEVICES WITH TRUSTED EXECUTION ENVIRONMENT (TEE) CONFIDENTIAL COMPUTE SUPPORT
An apparatus and method for extending IO device security protocols to integrated processors. For example, an example processor package comprises: a plurality of cores to execute instructions; an interconnect fabric coupled to the plurality of cores; memory interface circuitry coupled to the interconnect fabric, the memory interface circuitry to couple the plurality of cores to one or more memories; a root complex comprising: security circuitry operable as a root of trust (ROT) and a bridge to the interconnect fabric, the security circuitry to establish secure communication with one or more Root Complex Integrated Endpoint (RCiEP) devices integral to the processor package; and a Security Protocol and Data Model (SPDM) engine of the security circuitry to provide RCiEP encryption and SPDM protocol services to establish secure communication channels with each RCiEP device.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire
G06F 21/85 - Protection des dispositifs de saisie, d’affichage de données ou d’interconnexion dispositifs d’interconnexion, p. ex. les dispositifs connectés à un bus ou les dispositifs en ligne
51.
HYBRID SPECULATIVE DECODING SYSTEM WITH MODELS ON SILICON
A speculative decoding system may include integrated circuits (ICs), a router, and a processing unit. The ICs may implement different models that can perform different types of tasks. The router may route an input prompt, which may include one or more input tokens, to an IC based on the task to be performed using the input prompt. The IC may include hardware implementations of operators in a model. The IC may generate speculative token(s) from the input prompt by running the operators in the model. The speculative token(s) may be drafted to the processing unit. The processing unit may validate the speculative token(s) and generate output token(s) by executing another model, which may be larger than the model executed by the IC. The processing unit may validate multiple speculative tokens in parallel. Key-value pairs generated by the IC may be used by the processing unit for executing the other model.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An integrated circuit (IC) device may implement a neural network model. The IC device may include stacked embedding dies, stacked attention dies, and a base die. The embedding dies may perform embedding computations in the model. Each embedding die may have an embedding dot unit that includes memories for storing precomputed embedding vectors, multiply units for performing multiplication operations on embeddings, add units for summing the results of the multiplication operations. The attention dies may perform attention computations in the model. Each attention die may have an attention dot unit that includes memories for storing intermediate values, multiply units for performing multiplication operations for attention mechanisms, add units for summing the results of the multiplication operations. The base die may coordinate the overall operation of the model and perform preprocessing, embedding, normalization, activation, and final output generation. Micro-bumps may provide electrical connections between the stacked dies, facilitating inter-die communication.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A memory module has data buffers coupled to a registered clock driver (RCD) via buffer communication (BCOM) bus. The memory module includes memory devices managed as a first pseudo channel and a second pseudo channel. The data buffers manage data transmission between the memory devices and a host based on commands received over the BCOM bus. The RCD can send a first BCOM command on the BCOM bus to the data buffer, the first BCOM command to specify a rank and a burst length for the first pseudo channel. The RCD can send a second BCOM command on the BCOM bus to the data buffer, the second BCOM command to specify a rank and a burst length for the second pseudo channel, and a timing offset relative to the first BCOM command.
Integrated circuit structures having deep via structures, and methods of fabricating integrated circuit structures having deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends into the conductive trench contact structure. The conductive via has a first width beneath the epitaxial source or drain structure less than a second width laterally adjacent to the epitaxial source or drain structure.
Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets
H01Q 1/24 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets avec appareil récepteur
H01Q 1/52 - Moyens pour réduire le couplage entre les antennesMoyens pour réduire le couplage entre une antenne et une autre structure
H01Q 19/22 - Combinaisons d'éléments actifs primaires d'antennes avec des dispositifs secondaires, p. ex. avec des dispositifs quasi optiques, pour donner à une antenne une caractéristique directionnelle désirée utilisant un dispositif secondaire constitué par un seul élément conducteur sensiblement rectiligne
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer.
Fin trim plug structures with metal for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls, wherein the top has a longest dimension along a direction. A first isolation structure is over a first end of the fin. A gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of a region of the fin. The gate structure is spaced apart from the first isolation structure along the direction. A second isolation structure is over a second end of the fin, the second end opposite the first end, the second isolation structure spaced apart from the gate structure along the direction. The first isolation structure and the second isolation structure both include a dielectric material laterally surrounding an isolated metal structure.
Gate-all-around integrated circuit structures having electrostatic discharge (ESD) clamps are described. For example, an integrated circuit structure includes a p channel device having a source structure and a drain structure. An n channel device is vertically stacked with the p channel device, the n channel device having a source structure and a drain structure. The source structure of the n channel device is electrically connected to the source structure of the p channel device. The drain structure of the n channel device is electrically connected to the drain structure of the p channel device.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
Management of data bursts in network processing are described. An example of an apparatus providing management of data bursts in network processing includes circuitry to track telemetry events in operation of a network, the network including a plurality of accelerators; circuitry to predict future occurrences of data bursts, the prediction of occurrences of data bursts being based at least in part on historical telemetry data; and circuitry to transition one or more network resources from a sleep state to an operational state, the one or more network resources to be transitioned to the operational state prior to an occurrence of a predicted data burst.
There may be provided a device which may include a main body. The main body may include a panel portion and a protrusion arrangement extending from the panel portion, the protrusion arrangement being non-parallel to the panel portion. The device may further include at least one power management component disposed at the panel portion of the main body. The device may further include an interconnect which may include a primary connection point and an auxiliary connection point. The primary connection point may be electrically coupled to the at least one power management component at the panel portion of the main body, while the auxiliary connection point is positioned away from the panel portion.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
Various aspects of an object weight estimation system are described, to enable weight estimation of an object to be transferred from an object source (e.g., a human or an ambulatory robot) that holds the object using one or more arms. One technique includes: tracking an object to be transferred from the object source to a robot; identifying, from at least one image captured by the robot, a posture of the object source; identifying respective segments of the object source from the posture of the object source; determining an estimated weight of the object based on a center of gravity of the object source, as the center of gravity of the object source is calculated in real-time from a balance of the respective segments; and causing a responsive action with the robot, based on the estimated weight of the object.
B62D 57/032 - Véhicules caractérisés par des moyens de propulsion ou de prise avec le sol autres que les roues ou les chenilles, seuls ou en complément aux roues ou aux chenilles avec moyens de propulsion en prise avec le sol, p. ex. par jambes mécaniques avec une base de support et des jambes soulevées alternativement ou dans un ordre déterminéVéhicules caractérisés par des moyens de propulsion ou de prise avec le sol autres que les roues ou les chenilles, seuls ou en complément aux roues ou aux chenilles avec moyens de propulsion en prise avec le sol, p. ex. par jambes mécaniques avec des pieds ou des patins soulevés alternativement ou dans un ordre déterminé
62.
EXECUTING FLOATING-POINT MODEL THROUGH INTEGER DATAPATH IN NEURAL PROCESSING UNIT
A neural processing unit (NPU) may perform computations in integer domains to execute a floating-point model. The NPU may include an input delivery unit (IDU), a processing engine, and a post-processing engine. The IDU may convert floating-point weights to integers, e.g., by normalizing the floating-point weights, mapping the normalized floating-point values to normalized integer values using a look-up table, and scaling up the normalized integer values into integer values. The IDU may load the integer values into the processing engine through an integer datapath in the NPU. The processing engine may compute an output tensor of a neural network operation using the integer values. The post-processing engine may perform per-channel quantization of the output tensor using channel-specific quantization parameters stored in configuration registers of the post-processing engine. The look-up table and configuration registers may be programmed with configuration parameters determined by a compiler.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
Methods, apparatus, and computer programs are disclosed for context switching. In some embodiments, a method comprises dedicating a first subset of a plurality of vector registers to a first thread of a plurality of threads for thread execution; and responsive to a context switch from the first thread to a second thread, bypassing saving a state of the first subset of the plurality of vector registers; and saving a state of a second subset of the plurality of vector registers, wherein the second subset of the plurality of vector registers is not dedicated to the first thread, and wherein the first and second subsets are mutually exclusive.
Methods, apparatus, and computer programs are disclosed for data/instruction access based on performance hints. In some embodiments, a method comprises decoding an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor. The method further comprises processing the data or code based on the one or more hints responsive to the decoded instruction.
This disclosure describes systems, methods, and devices related to optimized synchronization. A device may receive configuration information for a plurality of synchronization signal blocks, wherein the synchronization signal blocks comprise a first set of synchronization signal blocks and a second set of synchronization signal blocks. The device may determine, based on the configuration information, time and frequency resources associated with the plurality of synchronization signal blocks that overlap with a physical downlink shared channel transmission. The device may configure resource allocation as available or unavailable for a physical downlink shared channel transmission. The device may transmit the physical downlink shared channel transmission utilizing the resource allocation.
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
H04W 48/10 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant des informations radiodiffusées
This disclosure describes systems, methods, and devices related to optimized synchronization multiplexing. A device may identify one of a plurality of synchronization signal blocks (SSB) transmitted by a base station for a frequency. The device may detect, for each received SSB, the SSB is part of an always-on SSB or an on-demand SSB. The device may detect master information block (MIB) content of a received SSB based on the always-on SSB or the on-demand SSB. The device may process one or more communication signals based on the MIB content.
H04W 48/14 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant une requête de l’utilisateur
09 - Appareils et instruments scientifiques et électriques
Produits et services
computer hardware; semi-conductors; integrated circuits; integrated circuits designed for ruggedized applications; integrated circuits designed for extreme environments
An integrated circuit (IC) device may implement a contextual embedding model. The IC device may include a tokenizer unit, embedder unit, layer normalizer unit, dot unit, activator units, and flow control unit. The tokenizer unit may implement a tokenizer in the model and convert text to tokens using the vocabulary of the model. The embedder unit may implement embedders in the model and generate embeddings from the tokens. The layer normalizer unit may implement one or more layer normalizers in the model and compute embedding vectors. The dot unit may implement matrix multiplication and add operations in the encoders and pooler of the model. The activator units may implement activation functions, including tanh function, in the model. The flow control unit may orchestrate the other components of the IC device based on a timing sequence of neural network operations in the model.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
A user equipment (UE) configured for operation in a fifth-generation new radio (5G NR) network may be configured for an on-demand system information block 1 (OD-SIB1) transmission. The UE may decode signaling from a first cell indicating a physical cell identify of a Network Energy Saving Cell (NES_Cell) and an indication for receptions of synchronization signal (SS) physical broadcast channel (PBCH) (SS/PBCH) blocks on the second cell. The UE may transmit a physical random-access channel (PRACH) associated with one of the SS/PBCH blocks on the second cell to request the OD-SIB1 transmission. The UE may monitor a physical downlink control channel (PDCCH) on the second cell for scheduling of a random-access response (RA- Response) to be received during a RA-Response window. The UE may perform TypeO PDCCH monitoring of the second cell during an OD-SIB1 reception window to receive the OD-SIB1 transmission. The OD-SIB1 reception window may have a preconfigured window start offset after the RA-Response window and may have a preconfigured duration.
H04W 48/14 - Distribution d'informations relatives aux restrictions d'accès ou aux accès, p. ex. distribution de données d'exploration utilisant une requête de l’utilisateur
H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
71.
COLLISION HANDLING OF PHYSICAL UPLINK SHARED CHANNEL (PUSCH) CARRYING USER EQUIPMENT (UE) INITIATED BEAM REPORT FOR WIRELESS COMMUNICATIONS
This disclosure describes systems, methods, and devices related to establishing an uplink channel for sending a beam report to a wireless network to avoid wireless traffic collisions. A user equipment device may determine that a first dynamic grant physical layer uplink shared control channel (DG-PUSCH) of a first priority overlaps in time with a configured grant PUSCH (CG-PUSCH) of a second priority, smaller than the first priority, and carrying a UE-initiated beam report on a same carrier as the DG-PUSCH; and cancel a transmission of the CG-PUSCH based on a timeline requirement being satisfied.
H04W 72/566 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de priorité de l’information, de la source d’information ou du destinataire
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
H04W 24/10 - Planification des comptes-rendus de mesures
H04L 1/1812 - Protocoles hybridesDemande de retransmission automatique hybride [HARQ]
72.
PHYSICAL RANDOM ACCESS CHANNEL (PRACH) ADAPTATION IN WIRELESS NETWORKS
An apparatus for a user equipment (UE) operates in a New Radio (NR) network. The apparatus includes processing circuitry and memory. The processing circuitry configures the UE for physical random access channel (PRACH) adaptation. The circuitry decodes downlink control information (DCI) format received from a base station. The DCI format contains signaling that indicates that PRACH adaptation is enabled. Based on this indication, the circuitry determines one or more adaptive random access resources. These adaptive resources are distinct from legacy random-access resources. The circuitry encodes a PRACH preamble. The preamble is transmitted to the base station via the adaptive random access resources.
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
A user equipment (UE) is configured for operation in a New Radio (NR) network. The UE comprises front-end circuitry coupled to one or more antennas and processing circuitry coupled to the front-end circuitry. The processing circuitry configures the UE for UE-initiated beam reporting in the NR network. The processing circuitry encodes a physical uplink control channel (PUCCH) for transmission to a base station subsequent to a prior transmission of a first beam report via a first uplink channel. The PUCCH includes a resource request for a second uplink channel comprising a physical uplink shared channel (PUSCH). The processing circuitry decodes a downlink control information (DCI) format received from the base station. The DCI format indicates a resource for the second uplink channel. The processing circuitry encodes a UE-initiated beam report for transmission to the base station via the resource for the second uplink channel.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04W 72/232 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant de la couche physique, p. ex. signalisation DCI
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
H04W 72/1268 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison ascendante
H04W 24/10 - Planification des comptes-rendus de mesures
A method for dynamic gap management by a base station configured in a 5G New Radio (5G-NR) and beyond wireless network includes detecting a communication link to an inactive external reference clock source. The external reference clock source is configured to generate an external reference clock signal. The external reference clock signal is associated with timing a pre-configured duration of scheduled downlink (DL) transmissions and scheduled uplink (UL) receptions by the base station. An internal reference clock source is activated. The internal reference clock source generates an internal reference clock signal. Timing of a subsequent DL transmission or a subsequent UL reception is configured using the internal reference clock signal. The subsequent DL transmission or the subsequent UL reception is configured with a duration that is smaller than the pre-configured duration.
This disclosure describes systems, methods, and devices related to group addressed BUs. A device may encode a traffic indication map (TIM) element with information associated with a plurality of access points (APs) in a multiple basic service set identifications (BSSIDs) set and one or more APs of the AP MLD. The device may cause to send a beacon frame comprising the TIM element to one or more station devices (STAs).
Methods and apparatus to provide efficient tracking of computer resource utilization are disclosed. An example machine readable storage medium comprising instructions to cause programmable circuitry to determine whether at least one of a first intermediate node or a second intermediate node can satisfy a first request associated with a root node, after the determination, update at least one of a first value of the first intermediate node or a first value of the second intermediate node and a second value of the root node, determine whether a first child node can satisfy a second request associated with the first child node, and after a determination that the first child node can satisfy the second request, update a first value of the first child node, a second value of the first intermediate node, and the second value of the root node.
Systems, apparatus, articles of manufacture, and methods are disclosed to implement memory buffers. An example an integrated circuit includes a plurality of data buffers including a plurality of data ports; a registered clock driver; and a multiplexer to selectively couple to a first one of the plurality of data ports or a second one of the plurality of data ports.
Integrated circuit structures having conductive structures in fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a sub-fin. The integrated circuit structure also includes a gate structure. The gate structure includes a first gate structure portion over the vertical stack of horizontal nanowires, a second gate structure portion laterally adjacent to the first gate structure portion, wherein the second gate structure portion is not over a channel structure, and a gate cut between the first gate structure portion and the second gate structure portion.
H10D 86/00 - Dispositifs intégrés formés dans ou sur des substrats isolants ou conducteurs, p. ex. formés dans des substrats de silicium sur isolant [SOI] ou sur des substrats en acier inoxydable ou en verre
Disclosed herein are microelectronics packages and methods for manufacturing the same. The microelectronics packages may include a photonic integrated circuit (PIC), an electrical integrated circuit (EIC), and an interconnect. The interconnect may connect the EIC to the PIC. The interconnect may include a plurality of paths between the EIC and the PIC and the individual paths of the plurality of paths are less than 100 micrometers long.
G01S 7/481 - Caractéristiques de structure, p. ex. agencements d'éléments optiques
B81B 7/02 - Systèmes à microstructure comportant des dispositifs électriques ou optiques distincts dont la fonction a une importance particulière, p. ex. systèmes micro-électromécaniques [SMEM, MEMS]
G01S 17/931 - Systèmes lidar, spécialement adaptés pour des applications spécifiques pour prévenir les collisions de véhicules terrestres
80.
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH DIFFERENTIATED DIPOLE LAYERS
Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.
The present disclosure is directed to a device having a coating or liner of a polymer material that may significantly improve the mechanical performance and stability of through hole via interconnects, such as through glass vias interconnects, by damping the stresses from the expansion of copper used as a conductive material. The present lining method for the through hole vias uses selected polymers that have a low-viscosity and may be capable of in-situ polymerization, i.e., curing, after being placed in the through hole vias.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
82.
INTEGRATED CIRCUIT PACKAGES INCLUDING A SURFACE REDISTRIBUTED INTERCONNECT BRIDGE FOR DIE-TO-DIE INTERCONNECTS
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a core including conductive vias extending between a first surface and an opposing second surface of the core, the second surface of the core is planar; a substrate on the second surface of the core, the substrate including a third surface and an opposing fourth surface, the third surface of the substrate is in contact with the second surface of the core, and the fourth surface of the substrate includes conductive contacts; and a die at the second surface of the core, partially overlapping the substrate, including first conductive contacts electrically coupled to some of the conductive contacts of the substrate and second conductive contacts electrically coupled to some of the conductive vias in the core. In some embodiments, a thickness of the substrate is between 10 microns and 50 microns.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés
83.
VEHICLE MODE-BASED ALLOCATION OF RESOURCES IN A PROCESSING UNIT
A system that allocates resources of a processor in a vehicle to perform operations of a task based on vehicle mode of operation and quality of service (QoS) for the task. In some examples, the resources comprise one or more of: register allocation, cache allocation, number of allocated processor cores, memory allocation, memory bandwidth, or processor operating frequency.
A device, comprising a fan; a directional airflow shifter, configured to direct air from the fan within the device in either a first direction or a second direction; and a controller, configured to dynamically control the directional airflow shifter to direct the air from the fan in either the first direction or the second direction based on operational data.
An apparatus and system for beamspace compression of Sounding Reference Signals (SRS) in wireless communication systems are described. High-dimensional SRS data exchanged between radio units (RUs) and distributed units (DUs) are compress using spatial correlation in antenna arrays and transform bases. Compressed coefficients are allocated and quantized, and pre- and post-channel estimation SRS data are supported. Active beamspace coefficients and associated basis information are transmitted from the RU to DU. Signaling mechanisms convey configuration and assistance data, including time-offset alignment, compression thresholds, and basis selection are transmitted from the DU to RU. Dynamic control of compression ratio, spatial resolution, and basis persistence are supported and used in advanced antenna configurations such as massive multiple-input-multiple-output (MIMO) and beamforming.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
86.
METHODS AND APPARATUS TO ENABLE PRIVATE VERBAL SIDE CONVERSATIONS IN VIRTUAL MEETINGS
An example apparatus including processor circuitry to execute instructions to join a video conferencing meeting including a first audio channel, the first audio channel including first binaural audio at a first angle; in response to a user joining a second audio channel in the video conferencing meeting, select a second angle for the second audio channel and a third angle for the first audio channel; generate a superimposed binaural audio including second binaural audio and third binaural audio; and output the superimposed binaural audio such that first audio data from the first audio channel included in the third binaural audio is to appear to originate from a first position based on the third angle and second audio data from the second audio channel included in the second binaural audio is to appear to originate from a second position based on the second angle.
H04L 12/18 - Dispositions pour la fourniture de services particuliers aux abonnés pour la diffusion ou les conférences
H04N 21/439 - Traitement de flux audio élémentaires
H04N 21/4788 - Services additionnels, p. ex. affichage de l'identification d'un appelant téléphonique ou application d'achat communication avec d'autres utilisateurs, p. ex. discussion en ligne
87.
TECHNIQUES FOR DOWNLINK AND UPLINK RESOURCE MAPPING FOR FULL DUPLEX AND NON-CELL DEFINING SYNCHRONIZATION SIGNAL BLOCK
Various embodiments herein provide techniques for downlink and uplink resource mapping for full duplex communication, e.g., non-overlapping sub-band-full duplex (NOSB-FD) communication that includes a frequency resource for uplink communication and a frequency resource for downlink communication. Also described are techniques for user equipment (UE) behavior associated with a non-cell defining synchronization signal block (NCD-SSB). Other embodiments may be described and claimed.
H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c.-à-d. duplex
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes
H04W 74/0836 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes avec accès en 2 étapes
Examples described herein relate to an interface and a processor, coupled to the interface, that is configured to: offload decompression of codebook compressed data to a device, wherein the data comprises weight data, wherein the codebook compressed data comprises data represented by code values, and wherein the code values utilize less memory than the corresponding data. In some examples, the device comprises a direct memory access (DMA) engine. In some examples, the device comprises an accelerator to perform matrix multiplication or a decoder.
Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
90.
INCREMENTAL 2D-TO-3D POSE LIFTING FOR FAST AND ACCURATE HUMAN POSE ESTIMATION
Techniques related to 3D pose estimation from a 2D input image are discussed. Such techniques include incrementally adjusting an initial 3D pose generated by applying a lifting network to a detected 2D pose in the 2D input image by projecting each current 3D pose estimate to a 2D pose projection, applying a residual regressor to features based on the 2D pose projection and the detected 2D pose, and combining a 3D pose increment from the residual regressor to the current 3D pose estimate.
G06T 7/73 - Détermination de la position ou de l'orientation des objets ou des caméras utilisant des procédés basés sur les caractéristiques
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
G06V 40/10 - Corps d’êtres humains ou d’animaux, p. ex. occupants de véhicules automobiles ou piétonsParties du corps, p. ex. mains
91.
Caching Apparatus, Driver Apparatus, Transcoding Apparatus and Corresponding Devices, Methods and Computer Programs
Examples relate to a transcoding apparatus and a computer-readable medium. The transcoding apparatus comprises an interface, and processing circuitry comprising a graphics processing unit (GPU), wherein the processing circuitry is to transcode one or more textures to a selected format for execution, cache the transcoded textures for subsequent reuse.
Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.
Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etched from the backside to form inwardly tapered ends. An array of semiconductor devices each include a semiconductor region extending (e.g., in a first direction) from a source region to a drain region, with a gate structure extending (e.g., in a second direction perpendicular to the first direction) over the semiconductor region. A lower portion of the source and/or drain regions (e.g., a portion at least extending below the semiconductor region) has an inwardly tapered shape. The inward taper may be provided using a backside etching process. The tapered ends of the source and/or drain regions have an increased distance to the adjacent gate structures, thus reducing the parasitic capacitance.
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 30/43 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à une dimension, p. ex. transistors FET à fil quantique ou transistors ayant des canaux à confinement quantique à une dimension
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
94.
VISUAL SERVOING WITH REAL-TIME DIFFUSION-BASED IMAGE INPAINTING
Various aspects of visual servoing based on use of a generative diffusion model are described. One technique includes obtaining a current view image from a robot camera that captures a portion of an environment of the robot, and obtaining a spherical image from a previous view that depicts a surrounding area of the environment of the robot. The current view image is combined with the previous spherical image to produce a modified spherical image, and inpainting is performed in a mask area of the modified spherical image with a generative diffusion model. The inpainting blends the current view image with the previous spherical image, providing a view of the entire environment of the robot that can be used for visual servoing. The robot can perform path planning and visual servoing of an end effector based on the modified spherical image, independent of any use of an external positioning or localization system.
B25J 13/08 - Commandes pour manipulateurs au moyens de dispositifs sensibles, p. ex. à la vue ou au toucher
G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction
G06T 5/60 - Amélioration ou restauration d'image utilisant l’apprentissage automatique, p. ex. les réseaux neuronaux
G06T 5/77 - RetoucheRestaurationSuppression des rayures
G06V 10/26 - Segmentation de formes dans le champ d’imageDécoupage ou fusion d’éléments d’image visant à établir la région de motif, p. ex. techniques de regroupementDétection d’occlusion
G06V 10/74 - Appariement de motifs d’image ou de vidéoMesures de proximité dans les espaces de caractéristiques
G06V 10/98 - Détection ou correction d’erreurs, p. ex. en effectuant une deuxième exploration du motif ou par intervention humaineÉvaluation de la qualité des motifs acquis
95.
Conformally Plated TGVs Filled with Conductive Plug Materials
According to the various aspects, a present device may include a plurality of through hole via interconnects that are made of at least two conductive materials, which includes a conformally plated cooper layer enclosing a plug/filling of a low modulus conductive epoxy composite material to form dual material interconnects. The present dual material interconnects may reduce thermally-induced stresses on a glass substrate, as compared with the materials used in conventional through hole via interconnects.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H05K 1/11 - Éléments imprimés pour réaliser des connexions électriques avec ou entre des circuits imprimés
Described herein are techniques to enable the generation of sharing of telemetry between network devices and host devices with timestamps that are synchronized at nanosecond precision. One embodiment provides a device comprising a network interface, packet processing circuitry, and a host interface. The device facilitates the synchronization of system and/or device clocks of network and host devices to a common clock. The device is additionally configured to aggregate telemetry having timestamps that are based on the common clock and synchronize the telemetry from the network and host devices.
Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing a partial liner. In some embodiments, a microelectronic assembly may include a glass core having a first surface and an opposing second surface; a through-glass via (TGV) extending between the first surface and the second surface of the glass core, wherein the TGV includes a conductive material and has a first height; and a liner material between the glass core and the conductive material of the TGV, wherein the liner material extends from the second surface of the glass core and has a second height that is less than the first height.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
98.
MICROELECTRONIC ASSEMBLIES INCLUDING A PHOTOPOLYMER LINER IN THROUGH-GLASS VIAS
Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing a photopolymer liner. In some embodiments, a microelectronic assembly may include a glass core with a through-glass via (TGV), where the TGV includes a conductive material; and a liner material between the glass core and the conductive material of the TGV, where the liner material includes a photopolymer. In some embodiments, a microelectronic assembly may include a glass layer; a cavity in a surface of the glass layer, the cavity having sidewalls; and a liner material on the sidewalls of the cavity, where the liner includes a photopolymer.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
99.
APPARATUS AND METHODS FOR COPPER-NTE (NEGATIVE THERMAL EXPANSION) FILLED THROUGH-GLASS VIAS
Architectures and methods for through-glass vias (TGVs) filled with copper and negative thermal expansion (NTE) material in order to reduce the coefficient of thermal expansion (CTE) of the material in the TGVs. The NTE can be added to an electroplating solution. The desired or target CTE for the fill material in the TGV can be used to inform the selection of the specific NTE to use and the percentage of the NTE to use.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
System and techniques for robot position error correction are described herein. A position of a robot may be established based on measurements of an environment of the robot from a first sensor of the robot. An error value based on data from a second sensor of the robot may be obtained. A weight is selected for the error value and a weighted error value is created by combining the weight and the error value. The position and the weighted error value may be combined to create a corrected position that is used as a basis for an operation of the robot.
