Techniques are provided herein to form semiconductor devices that include one or more gate cuts that are self-aligned within the gate trench between adjacent devices. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure includes a gate dielectric and a gate electrode. The gate structure may be interrupted, for example, between two transistors with a gate cut that extends through at least a portion of the entire thickness of the gate structure and includes dielectric material to electrically isolate the portions of the gate structure on either side of the gate cut. A dielectric plug contacts a top surface of the gate cut to separate the gate structure on either side of the dielectric plug. The gate cut is self-aligned between the adjacent semiconductor devices such that it is substantially equidistant between the semiconductor devices along the gate trench.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 12/14 - Protection against unauthorised use of memory
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
G06F 15/16 - Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
G06F 15/173 - Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star or snowflake
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 16/11 - File system administration, e.g. details of archiving or snapshots
H04L 41/0668 - Management of faults, events, alarms or notifications using network fault recovery by dynamic selection of recovery network elements, e.g. replacement by the most appropriate element after failure
H04L 41/149 - Network analysis or design for prediction of maintenance
H04L 41/34 - Signalling channels for network management communication
H04L 41/40 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using virtualisation of network functions or resources, e.g. SDN or NFV entities
H04L 41/5025 - Ensuring fulfilment of SLA by proactively reacting to service quality change, e.g. by reconfiguration after service quality degradation or upgrade
H04L 43/20 - Arrangements for monitoring or testing data switching networks the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV
H04L 45/28 - Routing or path finding of packets in data switching networks using route fault recovery
H04L 45/7453 - Address table lookupAddress filtering using hashing
H04L 69/32 - Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitionsInterfaces between layers
H05K 7/14 - Mounting supporting structure in casing or on frame or rack
Methods, apparatus, systems, and articles of manufacture are disclosed for device authentication in a dedicated private network. An example apparatus includes interface circuitry, machine readable instructions, and programmable circuitry to utilize the machine readable instructions to generate first credentials associated with a first network based on second credentials associated with a second network, the first credentials including first location data corresponding to a dedicated private network (DPN), cause a mobile device to program a programmable subscriber identity module (SIM) of the mobile device based on the first credentials, and permit the mobile device to access the DPN based on a determination that second location data corresponding to the mobile device and included with the programmable SIM corresponds to the first location data.
A method comprises receiving, from a first processing node of a distributed processing cluster, an indication of an attestation result and supporting data for a second processing node of the distributed processing cluster, transmitting the indication of attestation result and supporting data for the second processing node of the distributed processing cluster to at least one additional processing node of the processing cluster, and in response to a determination that the indication of an attestation result for the second processing node of the distributed processing cluster indicated that the second processing node of the distributed processing device is secure, establishing a secure communication connection with the second processing node of the distributed processing cluster using the supporting data.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
H04L 9/30 - Public key, i.e. encryption algorithm being computationally infeasible to invert and users' encryption keys not requiring secrecy
Technologies for protocol execution include a command device to broadcast a protocol message to a plurality of computing devices and receive an aggregated status message from an aggregation system. The aggregated status message identifies a success or failure of execution of instructions corresponding with the protocol message by the plurality of computing devices such that each computing device of the plurality of computing devices that failed is uniquely identified and the success of remaining computing devices is aggregated into a single success identifier.
In one embodiment, a distributed feedback laser includes a laser comprising a waveguide, the waveguide having a variable width from a first end to a second end, the laser to generate optical energy of a plurality of lasing wavelengths. Other embodiments are described and claimed.
Systems, apparatus, articles of manufacture, and methods are disclosed to manage streaming. An example system includes interface circuitry and media access control (MAC) circuitry to route data from a network to a single address of a memory based on a memory address pointer at a scheduled rate.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
8.
Methods and Apparatus to Detect Side-Channel Attacks
Methods, apparatus, systems and articles of manufacture to identify a side-channel attack are disclosed. Example instructions cause one or more processors to generate an event vector based on one or more counts corresponding to tasks performed by a central processing unit; determine distances between the event vector and weight vectors of neurons in a self-organizing map; select a neuron of the neurons that results based on a determined distance; identify neurons that neighbor the selected neuron; and update at least one of a weight vector of the selected neuron or weight vectors of the neighboring neurons based on the determined distance of the selected neuron.
Various aspects relate to mechanisms for data object classification in connection with a memory and a processor. At an endpoint device, a classification of a data object is determined based on output from a machine learning model configured to take as input contents and metadata of the data object, wherein the classification comprises a confidence score. It is determined whether the data object requires additional review, based on the confidence score. A data object hash is computed based on the contents and the metadata of the data object. An internal structure of the machine learning model is updated based on the additional review, the data object hash, and subsequent operation of the endpoint device.
G06F 18/2413 - Classification techniques relating to the classification model, e.g. parametric or non-parametric approaches based on distances to training or reference patterns
To support flexible N:M sparsity pattern in a DCiM macro, the DCiM macro is subdivided into multiple sub-macros according to a partitioning factor P. Each sub-macro can support 1:2 sparsity ratio. Leveraging the partitioned design, the sub-macros can be grouped together to support different N:M sparsity patterns. To determine optimal N:N sparsity pattern for each layer of a neural network, an algorithm can determine the value A of a sparsity ratio A/B is based on the number of outliers in a layer, and the value B of the sparsity ratio A/B is based on the locality measure of the outliers representing the spatial distribution of the outliers. Moreover, the optimal N:M sparsity pattern that is aligned with the determined sparsity ratio A/B can be selected based on whether to prioritize latency or accuracy, or to balance both latency and accuracy.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
Techniques are provided for forming one or more well taps from through semiconductor via (TSV) structures between backside and frontside conductive layers. The well tap/TSV structures may be formed during the same fabrication process used to form other TSVs and may be located in the same general area of the device layer. The well tap/TSV structures may be nano-scale structures that extend partially or fully through the device layer. One or more first recesses through the device layer include TSVs for routing power or ground between the backside conductive layer beneath the device layer and a frontside conductive layer above the device layer without contacting the device layer. One or more second recesses through the device layer include power tap/TSV structures that can provide frontside to backside routing and that also conductively couple semiconductor material of the device layer to backside power and/or ground terminals or rails.
Techniques for forming one or more MIM trench capacitors over one or more planar MIM capacitors in an interconnect region above or below a device layer of an integrated circuit. The MIM trench capacitor(s) is in one or more interconnect layers of the interconnect region, and can have a relatively high height. The MIM trench capacitor includes a first electrode, a capacitor dielectric on the first electrode, and a second electrode on the capacitor dielectric, and runs along the outside surface of a plurality of dielectric fins, which increases the surface area of the capacitor within a relatively small plan footprint. A planar MIM capacitor is beneath the MIM trench capacitor within a same interconnect layer as the MIM trench capacitor. The planar MIM capacitor includes first and second planar electrodes separated by a capacitor dielectric, and may be electrically isolated from, or capacitively coupled to, the MIM trench capacitor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
13.
METHODS AND APPARATUS FOR HARDWARE-AWARE MACHINE LEARNING MODEL TRAINING
Methods, apparatus, systems, and articles of manufacture are disclosed for hardware-aware machine learning model training. An example apparatus includes a configuration determiner to determine a hardware configuration of a target hardware platform on which the machine learning model is to be executed, a layer generator to assign sparsity configurations to layers of the machine learning model based on the hardware configuration, and a deployment controller to deploy the machine learning model to the target hardware platform in response to outputs of the machine learning model satisfying respective thresholds, the outputs including a quantity of clock cycles to execute the machine learning model with the layers having the assigned sparsity configurations.
Systems and methods are provided for change detection in low-resolution video streams, which can be used for applications such as high resolution video restoration and processing. The techniques effectively detect changes by leveraging a large receptive field and lightweight computation, which are achieved by working with low-resolution images. In particular, the techniques include extracting features from a change detection model and a semantic segmentation model, and integrating the extracted feature outputs from the models to produce a robust change detection map. A pre-processing phase can be employed to optimize the input for each model, ensuring minimal complexity and enhanced performance. The change detection model can be implemented as a deep neural network, and methods are provided for generating ground truth (GT) data, which semantically guides the change detection neural network to perform change detection inpainting during training.
Examples described herein relate to configuring a switch in an accelerator fabric to: monitor accesses to a memory region by one or more accelerators coupled to the accelerator fabric and report the accesses to the memory region to one or more specified accelerators coupled to the accelerator fabric. In some examples, the configuration includes a call to an application programing interface (API), a configuration file, a remote procedure call (RPC), or execution of a binary.
A "models-on-silicon" chip can encapsulate Large Language Model weights and inference architecture directly onto the hardware by etching the weights onto the chip and implementing custom circuits to perform operations of a Large Language Model. The weights are stored in sequential read-only memory, and the operations are orchestrated in a feedforward manner. Each line is read at a designated time slot along with the operation that is operating on the data. The architecture eliminates the recurring task of loading weights and the model processing graph onto Graphics Processing Units each time. Moreover, the architecture frees up the need to persistently retrieve weights from memory for each computation, and the data is stored near the circuits performing the operations. Performance is improved, routing is simplified, and data is more quickly accessed. The architecture is cost-effective and can be highly scalable.
This disclosure describes systems, methods, and devices for gap management for packet data convergence protocol and radio link control count. A device may encode a first subset of packets; encode a second subset of packets based on the first subset; allocate a count for the first subset and the second subset; detect that the second subset is not to be transmitted by the device or decoded by a second device; encode, based on detecting that the first subset is not to be transmitted by the device or decoded by the second device, an indication to be transmitted to the second device to instruct the second device to skip a gap in the count based on the second subset.
An integrated circuit (IC) device may implement a contextual embedding model. The IC device may include a tokenizer unit, embedder unit, layer normalizer unit, dot unit, activator units, and flow control unit. The tokenizer unit may implement a tokenizer in the model and convert text to tokens using the vocabulary of the model. The embedder unit may implement embedders in the model and generate embeddings from the tokens. The layer normalizer unit may implement one or more layer normalizers in the model and compute embedding vectors. The dot unit may implement matrix multiplication and add operations in the encoders and pooler of the model. The activator units may implement activation functions, including tanh function, in the model. The flow control unit may orchestrate the other components of the IC device based on a timing sequence of neural network operations in the model.
Semiconductor packages including passive support wafers, and methods of fabricating such semiconductor packages, are described. In an example, a semiconductor package includes a passive support wafer mounted on several active dies. The active dies may be attached to an active die wafer, and the passive support wafer may include a monolithic form to stabilize the active dies and active die wafer during processing and use. Furthermore, the passive support wafer may include a monolith of non-polymeric material to transfer and uniformly distribute heat generated by the active dies.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
An electronic device carrier structure can include a substrate including a plurality of electrical contacts spaced apart on the substrate, a plurality of electrically conductive balls, each of the electrically conductive balls being on a respective one of the plurality of electrical contacts, solder attaching each of the electrically conductive balls to respective ones of the electrical contacts to form an attachment boundary where the solder ends on a surface of each of the plurality of electrically conductive balls, and a polymer layer extending on the substrate onto the plurality of electrically conductive balls to form a surface of the polymer layer at a contact point on the plurality of electrically conductive balls that is above the attachment boundary and below an apex of each of the plurality of electrically conductive balls.
Hybrid panels comprising one or more solid layers of glass positioned within an organic panel are automatically manufactured by a tool link comprising an alignment module, a buffer lamination module, a gap reinforcement module, and a press module. The alignment module places one or more glass layers within an organic frame to form a hybrid panel assembly. The buffer lamination module places a buffer layer on the hybrid panel assembly. The gap reinforcement module places reinforcement material strips over gaps between the frame and the layers of glass and gaps between adjacent layers of glass. Alternatively, the gap reinforcement module dispenses liquid mold material along the gaps. The buffer module performs compression molding on hybrid panel assemblies to form hybrid panels that have planar top and bottom surfaces, and upon which integrated circuit components can be fabricated.
For example, a Radio Head (RH) may include a communication interface configured to communicate with a radar processor via a communication interconnect. For example, the communication interface may be configured to receive analog synchronization information from the radar processor, and to communicate with the radar processor analog radar signals over a plurality of frequency channels. For example, the RH may include a frequency generator configured to generate a plurality of frequency signals corresponding to the plurality of frequency channels, for example based on the analog synchronization information. For example, the RH may include a plurality of radio chains to communicate radar Radio Frequency (RF) signals corresponding to the analog radar signals.
A speculative decoding system may include integrated circuits (ICs), a router, and a processing unit. The ICs may implement different models that can perform different types of tasks. The router may route an input prompt, which may include one or more input tokens, to an IC based on the task to be performed using the input prompt. The IC may include hardware implementations of operators in a model. The IC may generate speculative token(s) from the input prompt by running the operators in the model. The speculative token(s) may be drafted to the processing unit. The processing unit may validate the speculative token(s) and generate output token(s) by executing another model, which may be larger than the model executed by the IC. The processing unit may validate multiple speculative tokens in parallel. Key-value pairs generated by the IC may be used by the processing unit for executing the other model.
Disclosed herein are integrated circuit (IC) structures fabricated with techniques to reduce a gated subfin region in nanoribbon-based transistors. In one example, the technique involves depositing a film over the shallow trench insulator (STI) between adjacent subfins, where the film has a different material composition than the STI. In accordance with examples described herein, the film over the STI can protect the STI during various etch and clean processes to minimize unintentional recession of the STI and thus minimize the presence of gated subfins in the final IC structure. In some examples, the film may be present over the STI in the final IC structure in a plane with source or drain contact structures, and may also be present over the STI in a metal gate region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
Disclosed herein is a backplate assembly for mounting a component (such as a compression attached memory module (CAMM)) and a co-located component (such as a solid state drive (SSD)) to a printed circuit board (PCB). The backplate assembly includes a backplate mounted on a first face of the PCB and attached to the component on a second face of the PCB that is opposite to the first face. The backplate includes a cutout to receive the co-located component and a perimeter portion that includes a flange extending away from the backplate and the printed circuit board. The backplate assembly also includes a plate cap configured to engage with the flange to attach the plate cap to the backplate and to at least partially cover the co-located component.
This disclosure describes systems, methods, and devices related to a mechanism to enable a federated onboarding service in an OpenRoaming™ framework. A device may receive a prompt to initiate onboarding of the device to a framework. The device may the initiate a federated onboarding service process at an access network provider (ANP) that is connected to the device, wherein the federated onboarding service process is configured to onboard the device to the framework. The device may further receive a list of available identity providers (IdPs) configured for the framework and receive a selection of an IdP of the list of available IdPs. The device may then establish a connection between the IdP and the device. The device may receive an IdP-generated user-specific profile, and the device may connect to the framework using the user-specific profile.
An embodiment of the invention is a processor including execution circuitry to calculate, in response to a decoded instruction, a result of a complex multiplication of a first complex number and a second complex number. The calculation includes a first operation to calculate a first term of a real component of the result and a first term of the imaginary component of the result. The calculation also includes a second operation to calculate a second term of the real component of the result and a second term of the imaginary component of the result. The processor also includes a decoder, a first source register, and a second source register. The decoder is to decode an instruction to generate the decoded instruction. The first source register is to provide the first complex number and the second source register is to provide the second complex number.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/48 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
One embodiment provides for a graphics processing unit including a fabric interface configured to transmit gradient data stored in a memory device of the graphics processing unit according to a pre-defined communication operation. The memory device is a physical memory device shared with a compute block of the graphics processing unit and the fabric interface. The fabric interface automatically transmits the gradient data stored in memory to a second distributed training node based on an address of the gradient data in the memory device.
A system and method for accelerated tuning of hyperparameters includes receiving a multi-task tuning work request for tuning hyperparameters of a model, wherein the multi-task tuning work request includes: a full tuning task for tuning hyperparameters, wherein the full tuning task includes a first set of tuning parameters governing a first tuning operation; a partial tuning task for tuning the hyperparameters of the model, wherein the partial tuning task includes a second distinct set of tuning parameters governing a second tuning operation; executing the first tuning operation and the second tuning operation; generating a first suggestion set and a second suggestion set of one or more proposed values for the hyperparameters based on the execution of the full tuning task and the partial tuning task; and setting the partial tuning task as a proxy for the full tuning task thereby accelerating a tuning of the hyperparameters of the model.
Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.
Provided is an apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. The machine-readable instructions include instructions to receive a request to reassign a CXL device from a first host to a second host. The machine-readable instructions include instructions to transmit, to a first management controller of the first host, a request for retrieving an error record of the CXL device. The machine-readable instructions include instructions to receive, from the first management controller, the error record. The machine-readable instructions include instructions to transmit, to a second management controller of a second host, a request for storing the error record of the CXL device. The machine-readable instructions include instructions to bind the CXL device to the second host after receiving a confirmation indicating successful storing of the error record at the second host.
Various systems and methods of artificial intelligence (AI) processing using hardware acceleration within edge computing settings are described herein. In an example, processing performed at an edge computing device includes: obtaining a request for an AI operation using an AI model; identifying, based on the request, an AI hardware platform for execution of an instance of the AI model; and causing execution of the AI model instance using the AI hardware platform. Further operations to analyze input data, perform an inference operation with the AI model, and coordinate selection and operation of the hardware platform for execution of the AI model, is also described.
G06N 3/10 - Interfaces, programming languages or software development kits, e.g. for simulating neural networks
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
H04L 41/5003 - Managing SLAInteraction between SLA and QoS
33.
METHODS, SYSTEMS, ARTICLES OF MANUFACTURE, AND APPARATUS TO DECODE ZERO-VALUE-COMPRESSION DATA VECTORS
Methods, systems, articles of manufacture, and apparatus are disclosed to decode zero-value-compression data vectors. An example apparatus includes: a buffer monitor to monitor a buffer for a header including a value indicative of compressed data; a data controller to, when the buffer includes compressed data, determine a first value of a sparse select signal based on (1) a select signal and (2) a first position in a sparsity bitmap, the first value of the sparse select signal corresponding to a processing element that is to process a portion of the compressed data; and a write controller to, when the buffer includes compressed data, determine a second value of a write enable signal based on (1) the select signal and (2) a second position in the sparsity bitmap, the second value of the write enable signal corresponding to the processing element that is to process the portion of the compressed data.
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a substrate having a first layer including a first conductive pad at a first surface of the substrate; a second layer, adjacent to the first layer, including first conductive vias, wherein one or two first conductive vias are physically coupled to the first conductive pad; a third layer including second conductive vias; and a fourth layer, adjacent to the third layer, including a second conductive pad at a second surface opposite the first surface of the substrate, wherein between four and nineteen second conductive vias are physically coupled to the second conductive pad, and the first conductive pad is electrically coupled to the second conductive pad by at least the first conductive vias and the second conductive vias.
Disclosed herein are IC structures with backside power delivery (BPD) using conductive materials with preferential grain alignment. An example IC structure may include a device layer including a plurality of transistors, the device layer having a first side and a second side opposite the first side; one or more backend layers at the first side of the device layer, the one or more backend layers including backend interconnects coupled to one or more of the plurality of transistors; and a BPD arrangement that includes one or more backside layers at the second side of the device layer, wherein the one or more backside layers include an insulator material, an opening in the insulator material, the opening lined with a liner material, and a conductive material within the opening lined with the liner material, wherein the conductive material has a preferential grain alignment.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
Technologies for multiple-time reprogrammable fuses are disclosed. In an illustrative embodiment, an electronic fuse in an integrated circuit component may be written a first time, blowing the fuse. The fuse may then be read many times during normal operation. At a later time, the fuse may have a write operation performed on it again. The write operation does not further disturb the state of the fuse, allowing for the fuse to continue to be read without error, even after several write cycles.
A target neural network can be trained with a support neural network through many-to-one knowledge injection. The many-to-one knowledge injection is facilitated by two layers inserted into the target neural networks. The first layer converts a target OFM in the target neural network into an expanded feature map having more channels. The second layer converts the expanded feature map to a new feature map having the same dimensions as the target OFM. The expanded feature map can be divided into segments, each of which has the same number of channels as a support OFM in the support neural network so that the knowledge in the support OFM can be injected into each of the segment through a many-to-one injection. To train the target neural network, parameters inside the target neural network are modified to minimize a feature distance between the expanded feature map and the support OFM.
Systems, apparatuses and methods may provide for technology that includes a capacitor array to conduct multiply-accumulate (MAC) operations on first analog signals and multibit weight data, the capacitor array further to output second analog signals based on the MAC operations, a plurality of multiplexers coupled to the capacitor array, and a memory array including a plurality of columns coupled to the plurality of multiplexers, the memory array to store the multibit weight data, wherein one or more of the plurality of columns is redundant, and wherein the capacitor array is external to the memory array.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
39.
SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT MATRIX DOT PRODUCT INSTRUCTIONS
Disclosed embodiments relate to computing dot products of nibbles in tile operands. In one example, a processor includes decode circuitry to decode a tile dot product instruction having fields for an opcode, a destination identifier to identify a M by N destination matrix, a first source identifier to identify a M by K first source matrix, and a second source identifier to identify a K by N second source matrix, each of the matrices containing doubleword elements, and execution circuitry to execute the decoded instruction to perform a flow K times for each element (m, n) of the specified destination matrix to generate eight products by multiplying each nibble of a doubleword element (M,K) of the specified first source matrix by a corresponding nibble of a doubleword element (K,N) of the specified second source matrix, and to accumulate and saturate the eight products with previous contents of the doubleword element.
A graphics processor is provided that includes circuitry configured to facilitate correspondence finding for higher-order light-based effects such as shadows, objects reflecting in mirrors, waves in water or other liquids, glossy surfaces, or objects visible through transparent and/or refractive glass. The circuitry is configured to procedurally generate temporally stable tracking data for transparent and reflective surfaces during rendering of successive frames, hierarchically analyze the successive frames to detect the procedurally generated data within the successive frames, generate residual motion vectors based on the hierarchical analysis, and warp and align a frame and a successively rendered frame based on renderer supplied motion vectors and the residual motion vectors.
Embodiments described herein provide an apparatus comprising a processor to reserve a block of physical memory communicatively coupled to a processor, allocate a first portion of the block of physical memory for use with one or more processes executing on the processor, the first portion configured as a single memory page having a first page size, and in response to a determination that an amount of physical memory required by the one or more processes executing on the processor exceeds a first threshold allocate additional memory to the first portion of the block of physical memory, and increase the single memory page from a first page size to a second page size. Other embodiments may be described and claimed.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
Techniques are provided herein for forming a through-semiconductor via (TSV) that extends through an entire thickness of a frontside interconnect region to provide a connection to a backside interconnect layer. The TSV is arranged within a dielectric socket that extends through an entire thickness of multiple layers included in the frontside interconnect region. The TSV extends through the device layer of a die and through each of multiple or all frontside interconnect layers of a frontside interconnect region. According to some embodiments, a dielectric socket is first formed through the frontside interconnect region and through the device layer to provide an isolated region for the TSV. A deep recess may then be etched through the entire height of the dielectric socket from the backside of the structure and filled with a conductive material to form the TSV. A backside conductive layer may be subsequently formed to contact the TSV.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
43.
GRADED INDEX (GRIN) LENS EXPANDED BEAM (EB) COUPLER FOR DETACHABLE FIBER ARRAY UNIT (FAU)
Architectures and methods for graded index (GRIN) lens expanded beam (EB) coupler for detachable fiber array unit (FAU) for use with a photonic integrated circuit (PIC). A system to optically couple a fiber optic array (FAU) to a PIC die includes a graded index (GRIN) lens to optically couple a single mode fiber (SMF) in the FAU to a waveguide in the PIC die. The GRIN lens has a first mode field diameter (MFD) that is a function of a spot size converter of the waveguide. The SMF is a conduit for optical light with a wavelength and a second MFD. The GRIN lens has a length that is a function of a predetermined whole number of periodic cycles of the wavelength.
A head of a DNN receives an OFM from a backbone network of the DNN. The head can partition the OFM into feature groups having same sizes. The head can further generate local tensors from the features group. To generate a local tensor from a feature group, the head may further partition the feature group into two subgroups, e.g., based on a splitting factor. The spatial sizes of the subgroups depend on the splitting factor. One subgroup can be converted into an attention tensor. The other subject can be converted into a value tensor, which may have the same size as the attention tensor. The attention tensor and value tensor are mixed to produce the local tensor. The local tensors of all the feature groups can be aggregated to form a global vector, which can be fed into a classifier to output one or more classification determined by the DNN.
A point grid network is a neural network that can model graph-structured data. The point grid network receives a graph-structured data sample, which may be a graph representation of an object. The point grid network uses an assignment matrix to transform the graph representation into a grid representation of the object. The assignment matrix defines whether graph nodes in the graph representation is to be assigned to grid elements in the grid structure. The grid representation is a tensor that can be processed through convolutional operations or other types of tensor operations. The point grid network can perform convolution on the grid representation and one or more filters to generate a grid-structured feature map. Values in the filter (s) and values in the assignment matrix are determined through training the point grid network. The point grid network may further determine a condition of the object based on the grid-structured feature map.
Described herein is a graphics processor including a processing resource including a multiplier configured to multiply input associated with the instruction at one of a first plurality of bit widths, an adder configured to add a product output from the multiplier with an accumulator value at one of a second plurality of bit widths, and circuitry to select a first bit width of the first plurality of bit widths for the multiplier and a second bit width of the second plurality of bit widths for the adder.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
Disclosed herein are devices, methods, and systems for energy optimization of vehicles based on observing passengers and the interior of the vehicle. A processor is configured to determine an energy reduction scheme for a subsystem of the vehicle. The energy reduction scheme is based on a passenger status of a passenger who is within a passenger environment of the vehicle. The energy reduction scheme is configured to reduce the power consumption of the subsystem with respect to the vehicle. The processor is also configured to control a configuration setting of the subsystem of the vehicle based on the energy reduction scheme.
B60W 50/00 - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
B60W 40/08 - Estimation or calculation of driving parameters for road vehicle drive control systems not related to the control of a particular sub-unit related to drivers or passengers
A multi-floor fan (700,800,900) comprises a fan housing comprising a first floor housing (710,810,910) for accommodating a first fan impeller (730) and a second floor housing (720,820,920) for accommodating a second fan impeller (740). The second floor housing (720,820,920) is arranged on the first floor housing (710,810,910). The first fan impeller (730) is configured to provide a first floor airflow in the first floor housing, and the second fan impeller (740) is configured to provide a second floor airflow in the second floor housing. The multi-floor fan can not only take the fully utilization of chassis inner space by filing the unusable space with a fan, but also increase the maximum system thermal capacity and fan performance.
A deep neural network (DNN) accelerator may include one or more tiles, each of which has a local memory. The local memory may include memory cuts, each of which has one or more memory banks. The local memory can facilitate address swizzling transformations. The local memory may receive a request for transferring data associated with a computation in a DNN. The request may include information indicating a first memory address that points to a first memory cut in the local memory. The local memory may transform the first memory address to a second memory address that corresponds to a second memory cut in the local memory. The data associated with the computation in the neural network is to be read from or written to the second memory cut. Memory banks may include state machines that can facilitate memory scrubbing. The local memory may also detect errors in data transfer requests.
KV tensors in a transformer model may be quantized in a dual-group manner. A key tensor or value tensor may be segmented into groups along both the token dimension and the channel dimension. A group size may be determined based on hardware constraint and model accuracy. The group size may indicate the total number of tokens or the total number of channels in each group. A part of the tensor may be segmented into groups having the group size, while the rest of the attention tensor may constitute an additional group having a larger size. The larger group may include keys or values corresponding to one or more recent tokens. Different groups within the tensor are quantized to variable precision levels with group-specific scale and zero-point values. The quantized tensor may be cached and used in a matrix multiplication operation in an attention module of the transformer model.
Examples described herein relate to an interface coupled to a memory and circuitry, coupled to the interface. In some examples, the circuitry is to: based on a configuration, perform switching between packets sent by a first process to a second process by writing packets into a first region of memory and copying the packets from the first region of memory to a second region of memory. In some examples, the first region of memory is accessible to the first process via an optical interconnect and the second region of memory is accessible to the second process via a second optical interconnect.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
A “models-on-silicon” chip can encapsulate Large Language Model weights and inference architecture directly onto the hardware by etching the weights onto the chip and implementing custom circuits to perform operations of a Large Language Model. The weights are stored in sequential read-only memory, and the operations are orchestrated in a feedforward manner. Each line is read at a designated time slot along with the operation that is operating on the data. The architecture eliminates the recurring task of loading weights and the model processing graph onto Graphics Processing Units each time. Moreover, the architecture frees up the need to persistently retrieve weights from memory for each computation, and the data is stored near the circuits performing the operations. Performance is improved, routing is simplified, and data is more quickly accessed. The architecture is cost-effective and can be highly scalable.
Techniques related to multi-level optical flow estimation are discussed. Such techniques include partitioning each pair of input images into one or more partitions, separately performing optical flow estimation on the partitions, and merging the separately generated optical flow results into a final optical flow map for the pair of input images.
Disclosed herein is a compression mount connector for a memory module with an additional cluster of pins between the typical two clusters of pins. The pins of the third cluster include a first subset of pins and a second subset of pins, wherein each pin of the first subset form a partially enclosed shape (e.g., a C-shape) that opens along a direction that is oblique to the direction of the first and second pins. Each pin of the second subset also forms a partially enclosed shape that opens in a direction that is opposite to the direction of the pins of the first subset.
An apparatus includes a memory that includes a first memory subchannel and a second memory subchannel; a first memory subsystem; a multiplexer, configured to selectively connect the first memory subsystem to the first memory subchannel or the second memory subchannel; a second memory subsystem, connected to the second memory subchannel; and a processor, configured to control the multiplexer to connect the first memory subsystem to the first memory subchannel according to a first operational mode, or to selectively connect the first memory subsystem to the second memory subchannel according to a second operational mode, based on whether a defect is detected in the second memory subsystem.
A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent sources or drained coupled to different nanoribbons or subsets of nanoribbons in the stack. In previous nanoribbon transistors, source/drain regions join the ends of a stack of nanoribbons together, thus electrically shorting the source ends together and the drain ends together. To achieve a stack of semiconductor regions with independent sources or drains, adjacent nanoribbons in the stack may be set at different distances apart, or the source side and drain side may be deposited in separate deposition processes.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
58.
CFET ARCHITECTURES WITH METAL TRACE ROUTING BETWEEN STACKED TRANSISTOR DEVICES
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Described herein are memory devices based on negative differential impedance. The memory cells may be formed around vertical pillars of semiconductor material, with multiple independent gates formed along and coupled to the pillar at different heights. A region of a semiconductor with an opposite doping type from the pillar may be at the base of the pillar and coupled to a first bitline, and a highly-doped cap region with the same doping type as the pillar may be above the pillar and coupled to a second bitline.
A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent gates around subsets of nanoribbons in the stack. In previous nanoribbon transistors, a gate electrode wraps around all of the semiconductor regions and spans the areas between adjacent semiconductor regions, thus electrically coupling the centers of the semiconductor regions. To achieve a stack of semiconductor regions with independent gates, adjacent nanoribbons in the stack may be set at different distances apart, or two or more sacrificial materials may be included when forming the stack of semiconductor materials and selectively etched when forming different gates.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
Apparatus and method for thread dispatch throttle control. For example, an example processor comprises: a plurality of graphics cores to execute instructions of a plurality of compute threads; and dispatch circuitry to dispatch each compute thread for execution on a graphics core of the plurality of graphics cores, the dispatch circuitry to track a number of compute threads of the plurality of compute threads dispatched to each graphics core of the plurality of graphics cores which have not completed; the dispatch circuitry to adjust a dispatch throttling threshold value based on stall metrics associated with each graphics core of the plurality of graphics cores, the stall metrics including a number of cycles for which the one or more compute threads of the plurality of compute threads are stalled within a clock window.
Systems, apparatuses and methods may provide for technology that includes a memory array to store multibit weight data in a non-binary data format, wherein the non-binary data format includes a radix that is less than two, and a capacitor recombination network to conduct multiply-accumulate (MAC) operations on first analog signals and the multibit weight data, the capacitor recombination network further to output second analog signals based on the MAC operations.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
A semiconductor structure is disclosed. The semiconductor structure includes back end layers that include a first metallization layer, a second metallization layer, and a scalable resistor between the first metallization layer and the second metallization layer. The semiconductor structure also includes front end layers.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H10D 1/47 - Resistors having no potential barriers
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
A manifold for use in a datacenter. The manifold comprising a housing and a plunger positioned within the housing. The housing comprising an inlet for receiving a cooling fluid; an outlet for enabling an outflow of the cooling fluid; and a fluid flow passage for enabling the flow of the cooling fluid from the inlet to the outlet. The plunger including a fluid flow channel and a biasing member. The plunger moveable between first and second positions. In the first position, the fluid flow channel is misaligned with the fluid flow passage to prevent the cooling fluid from flowing from the inlet to the outlet. In the second position, the fluid flow channel is aligned with the fluid flow passage to permit the cooling fluid to flow from the inlet to the outlet. The biasing member automatically moves the plunger to the first position upon a loss of power.
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.
This disclosure describes systems, methods, and devices related to secure alert standardization. A device may receive an indication of a security event from a virtual function (VF). The device may detect a type of the security event based on security parameters and assign a unique identifier to the event. The device may transmit an alert message comprising the unique identifier and event details to a baseboard management controller (BMC) using a platform-agnostic communication protocol. The device may store the alert message in a persistent server event log maintained by the BMC.
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
67.
ENHANCED WI-FI PEER-TO-PEER SERVICE DISCOVERY AND INITIATING STATION DEVICES FOR PROXIMITY RANGING
This disclosure describes systems, methods, and devices related to fine timing measurements for Wi-Fi peer-to-peer devices. A device may send a first frame, to a second station device in a peer-to-peer connection, signaling a future role of the station device as an initiator station device and a future role of the second station device as a responder station device during a future fine timing measurement session in a channel in a 5 GHz or 6 GHz frequency band. The device may set its role as a channel owner of the channel, may exchange NDPs with the second station device using the channel during the fine timing measurement session, and may exchange location measurement reports with the second station device and using the channel during the fine timing measurement session.
Examples relate to apparatuses, devices, methods, computer programs and non-transitory computer-readable media for emulating clock stretching. A controller apparatus is configured to communicate with a target apparatus via a bus, and to emulate clock stretching based on requests to start and end clock stretching obtained via an in-band interrupt mechanism. The controller apparatus is configured to pause data or command transmissions to the target apparatus during the emulated clock stretching, and to resume the data or command transmissions to the target apparatus after the emulated clock stretching has ended.
An example apparatus includes interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to initialize a full hot expert buffer to store entire weights of an expert used with a first frequency, initialize a partial hot expert buffer to store partial weights of an expert used with a second frequency, wherein the first frequency is higher than the second frequency, identify a selected expert associated with a Mixture of Experts (MoE) layer of a Large Language Model (LLM), and perform a direct computation or a partially direct computation, the direct computation performed when the selected expert is stored in the full hot expert buffer, the partially direct computation performed when the selected expert is stored in the partial hot expert buffer.
Methods and apparatus for data access pattern profiler for memory compression scheme selection are described herein. Respective data are stored as uncompressed data and compressed data in the system memory in which data are stored using multiple compressions schemes using different chunk sizes. In conjunction with servicing memory Read request from the compressed data, access patterns are profiled to generate profiled access patterns that are used to determine compression schemes to use to selectively recompress portions of the compressed data. Virtual memory areas are allocated for storing compressible data structures and divided into compressed memory regions (cmrs). Access to sampled pages in the cmr are profiled to generate the profiled access pattern for the cmr, which is used to determine whether a cmr compression scheme should be changed and what scheme to use for recompression.
Examples described herein relate to a chiplet comprising a circuitry to store a security policy, specific to the chiplet, and a second chiplet comprising a second circuitry to store a second security policy, specific to the second chiplet. In some examples, at least two of the multiple chiplets are from different chiplet manufacturers.
Examples described herein relate to tracking identification of firmware providers to identify unauthorized firmware providers. For example, prior to sharing device secret data with a firmware provider, circuitry can store an identification of the firmware provider in one time programmable (OTP) memory to record the identifier of the firmware provider.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
An apparatus comprising a die comprising a photonic integrated circuit, the die comprising a first plurality of optical channels; an optical coupling device, the optical coupling device comprising a second plurality of optical channels aligned with the first plurality of optical channels; and a coupler attached to the optical coupling device and to at least one of the die and a package substrate attached to the die.
Apparatuses, containment structures, and techniques related to encapsulating liquid metal interconnects are discussed. A liquid metal interconnect is within a cavity defined by an electronics substrate and an opening in a confinement layer over the electronics substrate. A bilayer containment structure is on the confinement layer and over the cavity to encapsulate the liquid metal interconnect within the cavity. The bilayer includes a porous material layer over the cavity and a self-healing material on the porous material layer.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
75.
METALLIZATION STACKS WITH STAGGERED CONDUCTIVE LINES
Integrated circuit (IC) structures and related semiconductor devices including metallization stacks having metallization layers with staggered conductive lines, as well as methods of fabricating such IC structures, are disclosed. An example IC structure includes a first metallization layer with a first conductive line, a second metallization layer with a second conductive line, and a third metallization layer with a third conductive line. The first, second, and third metallization layers are stacked along a direction. The second metallization layer is between the first and third metallization layers. A projection of the first conductive line onto a plane perpendicular to the direction is offset with respect to a projection of the third conductive line onto the plane. A projection of the second conductive line onto the plane intersects the projection of the first conductive line onto the plane and the projection of the third conductive line onto the plane.
H01L 23/528 - Layout of the interconnection structure
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
76.
A SYSTEM FOR ACCESSING MULTIPLE PRIMARY CHANNELS IN A WIRELESS MEDIUM
This disclosure describes a system for accessing multiple primary channels in a wireless medium. A device may cause to send a beacon frame to one or more wireless stations (STA(s)). wherein the beacon frame comprises a notification of two or more primary channels at an access point (AP). The device may receive a first physical layer protocol data unit (PPDU) from a first STA of the one or more STAs. The device may select a first primary channel of the two or more primary channels. wherein the first primary channel is idle. The device may cause to transmit the first PPDU from the first STA on the first primary channel.
This disclosure describes systems, methods, and devices related to unlicensed national information infrastructure 4 (UNII4) channel access. A device may perform a first scan for signals from an outside basic service set (BSS) on a UNII4 frequency band. The device may generate a frame comprising an indication to allow an associated STA to perform enhanced distributed channel access (EDCA). The device may perform a second scan for signals subsequent to the associated STA performing EDCA.
This disclosure describes systems, methods, and devices related to reducing the beam sweeping factor in neighboring cell measurements may reduce user equipment measuring time. A user equipment may detect that criteria for reducing a beam sweeping factor of measurements neighboring cells has been satisfied; measure the neighboring cells using a reduced beam sweeping factor, based on detecting that the criteria has been satisfied, by simultaneously receiving multiple synchronization signal block (SSB) beams; and report measurement results of measuring the neighboring cells to a radio access network (RAN).
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.
An apparatus is described. The apparatus includes a logic chip upon which a stack of memory chips is to be placed. The stack of memory chips and the logic chip to be placed within a same package, wherein, multiple memory chips of the stack of memory chips are divided into fractions, and, multiple internal channels within the package that emanate from the logic chip are to be coupled to respective ones of the fractions. The logic chip has a multiplexer. The multiplexer is to multiplex a single input/output (I/O) channel of the package to the multiple internal channels.
Examples described herein relate to an interface and circuitry, coupled to the interface. The circuitry is to: based on receipt of a first request to access data received from an optical interface and from a process, apply a configuration to determine whether to permit the access to data from a first memory region of the memory and based on a determination to permit the access to the data, permit access to the data by the first request, wherein the first memory region of the memory is accessible to multiple processes of a tenant via optical interconnects.
Examples described herein relate to circuitry coupled to a memory configured to: report telemetry data indicative of access to a first region of the memory; and based on a first command, selectively adjust resources of the memory allocated to communications between a first process and a second process. In some examples, the first region of the memory is accessible to the first process and the second process via optical interconnects. In some examples, the resources of the memory comprise one or more of: a number of addresses in a memory region, a set of memory addresses, or memory bandwidth.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
83.
ENGINE TO ENABLE HIGH SPEED CONTEXT SWITCHING VIA ON-DIE STORAGE
In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/1036 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 16/11 - File system administration, e.g. details of archiving or snapshots
G06F 16/13 - File access structures, e.g. distributed indices
G06F 16/172 - Caching, prefetching or hoarding of files
An apparatus and system for privacy protection for Ambient Internet-of-Things (A-IoT) devices are disclosed. A-IoT devices transmit obfuscated identifiers (OIDs) instead of actual identifiers, which are de-obfuscated by the network to retrieve the original identifiers. The device identifiers are obfuscated using shared secret parameters and periodically updated configurations. Hash-based lightweight privacy mechanisms, temporary identifiers (TempIDs), and pseudonym generation may be used to ensure secure communication and prevent replay attacks.
H04L 9/06 - Arrangements for secret or secure communicationsNetwork security protocols the encryption apparatus using shift registers or memories for blockwise coding, e.g. D.E.S. systems
H04W 12/02 - Protecting privacy or anonymity, e.g. protecting personally identifiable information [PII]
85.
DYNAMIC HEALTH AND FITNESS MONITORING SYSTEM TO IMPROVE BODY SUPPORTING DEVICES
A system, including: at least one processor configured to: receive real-time data indicative of a physiological state of a user during operation of a body-support device; determine, based at least in part on the real-time data and a training plan generated from a user body model representing a current physiological state of the user, a target level of physical support for the user; generate a control signal corresponding to the target level of physical support; and dynamically adjust the control signal in response to detected changes in the user's physiological state, as indicated by the real-time data, during operation of the body-support device; and an interface configured to transmit the control signal to the body-support device to dynamically provide the target level of physical support to the user.
A63B 24/00 - Electric or electronic controls for exercising apparatus of groups
A63B 21/00 - Exercising apparatus for developing or strengthening the muscles or joints of the body by working against a counterforce, with or without measuring devices
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
87.
MICROELECTRONIC ASSEMBLIES WITH DOUBLE LINERS IN THROUGH-GLASS VIAS
A microelectronic assembly according to an embodiment of the present disclosure may include a glass core (e.g., a layer of glass or a glass structure) having a first face and a second face opposite the first face; a through-glass via (TGV) in the layer of glass, the TGV extending from the first face towards the second face and comprising a conductive material; a first liner in the TGV, between the conductive material and the layer of glass; and a second liner in the TGV, between the conductive material and the layer of glass, wherein the first liner is between the layer of glass and the second liner, and wherein a modulus of the first liner is higher than a modulus of the second liner.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An apparatus to facilitate floating point compliance verification is disclosed. The apparatus includes processing circuitry to load a design under test (DUT) into a formal equivalence checking tool; define a floating point (FP) component of interest of the DUT; based on the DUT and a reference specification, produce a set of verification properties for the FP component of interest, wherein the set of verification properties is generated for each flag having no freedom, each flag having freedom, for output data having multiple allowable outputs, and for output data having infinitely precise results; check the generated set of verification properties at the formal equivalence checking tool using the DUT and the reference specification; and generate a verification properties report at a conclusion of running the formal equivalence checking tool to detail the set of verification properties.
An apparatus including: a memory, and a processor configured to: determine, for a remote interference management reference signal, a first frequency domain sequence comprising a plurality of first frequency domain symbols, wherein each first frequency domain symbol corresponds to a subcarrier of a plurality of subcarriers; determine a second frequency domain sequence comprising a plurality of second frequency domain symbols, wherein each second frequency domain symbol at a respective subcarrier comprises a phase rotated version of the respective first frequency symbol at the respective subcarrier, in which the respective first frequency symbol is phase rotated based on the respective subcarrier and a cyclic prefix length; and instruct to send information representing the second frequency domain sequence and the first frequency domain sequence to a radio unit of a cellular network for a transmission in consecutive orthogonal frequency division multiplex symbols.
The disclosure includes receiving one or more updates to a global resource pool of a hybrid cloud and updating a local resource pool with the one or more updates to the global resource pool; intercepting a service request from an application; redirecting deployment of the service request to a resource provider of the hybrid cloud with available computing resources to fulfill the service request based at least in part on the local resource pool and by using a webhook; receiving an Internet Protocol (IP) address of the resource provider; redirecting a domain name service (DNS) of the application to the IP address of the resource provider; and sending the service request to the resource provider.
This disclosure describes systems, methods, and devices related to physical layer (PHY) convergence protocol data unit (PPDU) early termination. A device may generate a frame comprising a header portion and one or more fields to carry information associated with one or more station devices (STAs). The device may encode the frame with an indication to at least one of the one or more STAs of a response behavior based on carly termination of the frame. The device may cause to send the frame to the one or more STAs.
For example, a millimeterWave (mmWave) wireless communication station (STA) may be configured to transmit a preamble of a packet over a mmWave wireless communication channel, the preamble including a Short Training Field (STF), a Long Training Field (LTF) after the STF, and a Signal (SIG) field after the LTF, wherein the SIG field includes a presence indicator configured to indicate that the packet includes a Training (TRN) field configured for Beamforming (BF) training; and to transmit the TRN field of the packet over the mm Wave wireless communication channel, the TRN field is after the SIG field, the TRN field including a plurality of TRN subfields, wherein a TRN subfield includes at least one of the STF or the LTF.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
Technologies for two-dimensional spin qubit arrays are disclosed. In an illustrative embodiment, a quantum processor die includes a two-dimensional array of spin qubits. Single-electron transistors (SETs) are arranged near an upper and lower boundary around the two-dimensional array of spin qubits. Each SET may be positioned to be able to read, e.g., qubits from two rows, allowing for the state of four rows of qubits to be read by the SETs above and below the array of qubits. The two-dimensional array of spin qubits may allow for a large number of physical and logical qubits in communication with each other, allowing for large scale quantum computation.
Multiply-accumulate (MAC) units arranged in MAC groups. Different segments of an input vector of a neural network layer may be allocated to different MAC groups by leveraging sparsity masks. For example, each MAC group may have a separate data storage unit. The data storage units may store the input vector and sparsity masks, which each have the same length as the input vector but indicate different sparsity patterns, may also be loaded into the data storage units. Each data storage unit stores a different sparsity mask. For each MAC group, a sparsity logic may transfer a different segment of the input vector from the corresponding data storage unit to the MAC group based on the corresponding sparsity mask. The MAC groups may perform MAC operations on the received segment and compute an output. The outputs of the MAC groups may be accumulated to compute an output element of the layer.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
95.
CONFIGURATION OF UPLINK RESOURCE FOR USER EQUIPMENT INITIATED BEAM REPORTING
This disclosure describes systems, methods, and devices related to optimized beam reporting. A device may receive a first uplink control information (UCI) on a first physical uplink control channel (PUCCH) resource to indicate that a beam report is carried by a second uplink channel. The device may configure the second uplink channel as either a second physical uplink control channel (PUCCH) resource or a second physical uplink shared channel (PUSCH) resource via radio resource control (RRC) signalling. The device may receive the beam report on the second uplink channel based on the received UCI on the first PUCCH.
H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
H04W 72/1268 - Mapping of traffic onto schedule, e.g. scheduled allocation or multiplexing of flows of uplink data flows
96.
INTERCONNECT FABRIC LINK WIDTH REDUCTION TO REDUCE INSTANTANEOUS POWER CONSUMPTION
Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.
A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.
Examples described herein relate to a first circuitry, wherein the first circuitry comprises one or more of: a first memory, a first processor, or a first accelerator; a second circuitry, wherein the first circuitry and the second circuitry are communicatively coupled by optical interfaces and wherein the second circuitry comprises one or more of: a second memory, a second processor, or a second accelerator; and a switch configured to provide optical and/or electrical signal isolation between the first and second circuitries based on a configuration. In some examples, the configuration is to specify whether optical, electrical, or optical and electrical communications are permitted and an access level.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
H04B 10/85 - Protection from unauthorised access, e.g. eavesdrop protection
99.
REALLOCATION OF RESOURCES FOR ISOLATING OPTICAL COMMUNICATIONS
Examples described herein relate to a first interface coupled to a first optical interconnect and coupled to a first memory region of a memory; a second interface coupled to a second optical interconnect and coupled to a second memory region of the memory; and circuitry, coupled to the first interface and the second interface. In some examples, the circuitry is to apply a configuration to determine whether to propagate signals from the first interface and propagate signals from the second interface, based on a determination to permit propagation of signals from the first interface to the first memory region, provide access to the first memory region, and based on a determination to permit propagation of signals from the second interface to the second memory region, provide access to the second memory region.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
100.
AGENT ORCHESTRATION OF MULTIPLE EXPERT CHIPS IMPLEMENTING MODELS-ON-SILICON ARCHITECTURE
An agent chip in a multi-chip architecture orchestrates multiple specialized AI models embedded and/or etched on different chips. Implementing the agent chip effectively solves the problem of deploying multiple specialized AI models in a cost-effective and scalable manner by training and utilizing the agent chip to orchestrate multiple specialized AI models embedded on different models-on-silicon chips. Each models-on-silicon chip is optimized for a specific task or goal, and the agent chip coordinates and/or routes their activities to perform complex, multi-faceted tasks efficiently. Accordingly, the multi-chip architecture allows for efficient, scalable, and cost-effective machine learning inference, significantly reducing power consumption and latency.
