An apparatus comprises a first IC die over a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface. The first surface comprises an area of at least 5,000 mm2. A redistribution layer is on the first surface. The redistribution layer comprises a thickness of 100 μm or less. An electrical component is within a region of the glass core between the first and second surfaces. A through-glass via extends between the first and second surfaces. A second IC die is over and directly bonded to the first IC die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Examples described herein relate to a component interconnect bus comprising multiple lanes for serial data transfer between a root port and an endpoint and circuitry to refresh keys used to encrypt or decrypt data. In some examples, during utilization of a first key set to encrypt data transmitted between the root port and the endpoint using the component interconnect bus, the circuitry can add a second key set for encryption of second data for transmission between the root port and the endpoint.
In one embodiment, a computing device includes a keyboard, a plurality of openings adjacent to the keyboard with at least one light emitting element positioned below each respective opening, and a flap above the plurality of openings. The flap is moveable between a first position that is generally parallel to the keyboard and a second position that is at an angle less than 90 degrees with respect to the keyboard. The flap includes touch sensing circuitry in areas adjacent to the respective openings and a liquid crystal layer that can be controlled to be generally transparent in the first position and generally opaque in the second position. The computing device may also include photochromatic paint adjacent to the openings.
H01H 13/83 - Switches having rectilinearly-movable operating part or parts adapted for pushing or pulling in one direction only, e.g. push-button switch having a plurality of operating members associated with different sets of contacts, e.g. keyboard characterised by legends, e.g. Braille, liquid crystal displays, light emitting or optical elements
G06F 1/16 - Constructional details or arrangements
4.
OPTICAL COUPLING USING SHIFTED OUT-OF-PLANE LIGHT PROPAGATION
Devices and systems with shifted out-of-plane light propagation, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes a first optical waveguide, a second optical waveguide, and one or more passive optical components. The first and second optical waveguides are optically coupled via the passive optical components. Moreover, the passive optical components are to shift light propagation out of plane between the first and second optical waveguides.
Embodiments disclosed herein include an apparatus that includes a scraping head that has an inner cavity with open ends and an open bottom. In an embodiment, the scraping head comprises an inner wall with a port through the inner wall, and an outer wall adjacent to the inner wall. In an embodiment, a gap is provided between the inner wall and the outer wall, and a vacuum line is fluidically coupled to the gap.
Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, and a second substrate over the first substrate, where the second substrate comprises an organic buildup layer. In an embodiment, a first width of the first substrate is greater than a second width of the second substrate. In an embodiment, an edge between a first corner of the first substrate and a second corner of the first substrate comprises a curve.
3D printing material in direct contact with edge of a glass core in IC packages to additively form a frame. Multiple such cores may be reconstituted into a panel that may then be built-up with routing metallization and assembled with IC die. Layers of printed material may be built up to form a frame with approximately the same thickness as the glass core and of any desired lateral width. The printed material may be an organic polymer or inorganic composition including metallics and ceramics. Beads of different material composition may be printed in succession to vary mechanical, electrical and/or thermal properties. A portion of the protective frame may be retained on an edge of the glass core when panels are singulated into package substrate units. Frame material may also be printed upon edges of glass-cored package units after their singulation.
In one embodiment, a method includes: receiving, in a prediction circuit associated with a cache memory of a processor, a load operation to load information stored in a memory; accessing at least one prediction structure of the prediction circuit to obtain prediction information associated with the load operation, the prediction information comprising a predicted virtual address for the load operation; and dispatching the load operation to a load pipeline of the processor using the predicted virtual address for the load operation. Other embodiments are described and claimed.
Embodiments disclosed herein include an apparatus that includes a substrate that includes a glass layer. In an embodiment, a first region of the substrate has a first porosity and a second region of the substrate has a second porosity that is higher than the first porosity. In an embodiment, the second region is at an edge of the substrate. In an embodiment, the substrate further includes a via that passes through a thickness of the substrate.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
10.
INTEGRATED CIRCUIT PACKAGES INCLUDING A STRUCTURAL DIE COUPLED TO A HIGH THERMAL CONDUCTIVITY MATERIAL IN 3 DIMENSIONAL DIE STACKS
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die having a first surface and an opposing second surface, where the first surface of the second die is electrically coupled to the first die by interconnects and the first surface of the third die is electrically coupled to the first die by a bonding material, and the bonding material includes titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; a first material, around the second die and the third die, having a non-planar surface; and a second material, on the non-planar surface of the first material and on the second and third dies, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
11.
SOCKET ASSEMBLIES FOR SEMICONDUCTOR DEVICE PACKAGES WITH EDGE FEATURES
Assemblies and methods of manufacturing assemblies that include sockets and packaged semiconductor chips are provided. The packages for the semiconductor chips can include cores that are formed from a solid amorphous glass layer.
H01L 23/04 - ContainersSeals characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second and third dies having a first surface and an opposing second surface, wherein the first surfaces of the second and third dies are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second and third dies, the first material having a non-planar surface; a layer on the non-planar surface of the first material and the second surfaces of the second and third dies, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; and a substrate, on the layer, including a microchannel.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/467 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing gases, e.g. air
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
13.
IMPROVED REMOVAL OF SACRIFICIAL MATERIAL FOR MINIMIZED CHANNEL EXTENSIONS
Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.).
Integrated circuit (IC) devices having dielectric spacers between parallel channel structures (e.g., of nanoribbons, nanowires, etc.).
A transistor structure may have first and second channel layers between source and drain bodies, a gate stack with a gate metal and gate dielectric between the channel layers, and a dielectric spacer between the channel layers and between the gate dielectric and one of the source and drain bodies. The dielectric spacer may have a significant (or minimal) curvature such that a width of the dielectric spacer between the channel layers is much greater (or not much greater) than widths of the dielectric spacer at the channel layers or than a minimum distance separating the gate metal between the channel layers from one of the source and drain bodies. An added or altered etch may remove sacrificial dummy gate material from between the channel layers and the gate side of the dielectric spacer.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
An integrated circuit (IC) device having complementary dielectric plugs separating gate electrodes. An IC device includes a first gate-cut plug of silicon and nitrogen between and in contact with two gate structures of transistors of a first conductivity type and a second gate-cut plug between and in contact with two gate structures of transistors of a second conductivity type, complementary to the first conductivity type, and the second gate-cut plug has within a liner of silicon and nitrogen either an airgap or a dielectric of silicon and oxygen. Pairs of gate structures of transistors having both of the first and second conductivity types are separated by first and second gate-cut plugs.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
15.
INTEGRATED CIRCUIT PACKAGES INCLUDING A HIGH THERMAL CONDUCTIVITY MATERIAL IN 3 DIMENSIONAL DIE STACKS
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer including a second material having a thermal conductivity equal to or greater than 10 watt per meter-kelvin (W/m-K).
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
16.
APPARATUS AND METHOD FOR EFFICIENT MULTI-DIMENSIONAL DATA PROCESSING
Techniques for efficient multi-dimensional data processing. For example, front end circuitry sorts tuples across a plurality of tuple buffers to provide conflict-free access to a corresponding plurality of input data banks without memory access conflicts, each tuple to associate an input data element of a plurality of input data elements with a corresponding weight data element of a weight tensor and a corresponding output data element of an output tensor; and execution circuitry to perform multiply-accumulate operations using a subset of the tuples, the execution circuitry to perform parallel multiplications with a corresponding subset of input data elements of the plurality of input data elements and a corresponding subset of weight data elements of the weight tensor indicated by the subset of the tuples, the execution circuitry to access the subset of input data elements from different input data banks of the plurality of input data banks without memory conflicts.
This disclosure describes systems, methods, and devices related to sensing service coordination. A device may discover a Network Data Analytics Function (NWDAF) via a Network Function Repository Function (NRF). The device may send an Analytics request or subscribe to the selected NWDAF with a criteria based on a sensing data analytics ID, event ID, and event parameters. The device may select a Data Collection Coordination Function (DCCF) instance when DCCF is used for data collection, based on DCCF Serving Area Information. The device may receive sensing data or data analytics from the NWDAF after NWDAF has processed the data collected from DCCF.
H04L 41/0853 - Retrieval of network configurationTracking network configuration history by actively collecting configuration information or by backing up configuration information
For example, a controller of a mobile robot may be configured to generate a plurality of control outputs to control a plurality of actuators of a plurality of wheels of the mobile robot. For example, the controller may configure the plurality of control outputs to control deceleration of the mobile robot while maintaining a controlled trajectory of the mobile robot during a controlled safety stop. For example, during the controlled safety stop the controller may monitor rotational velocities of the plurality of wheels; and configure a first control output of the plurality of control outputs to control an actuator of a first wheel of the plurality of wheels based on a rotational velocity of the first wheel, a rotational velocity of a second wheel of the plurality of wheels, and a radius of the controlled trajectory.
Techniques and architectures for determining a target of a branch instruction. In an embodiment, a processor core detects a fall through event wherein multiple fetched instructions comprise one or more branch instructions. Based on the fall through event, a repository is provided with respective branch information for each of the one or more branch instructions. The repository functions as a cache that is available to an evaluation circuit at an instruction fetch stage of the processor core. Branch information at the repository is accessible to facilitate a relatively early identification of an instruction as being of a branch instruction type. In another embodiment, the early identification enables re-steering of a speculative execution sequence.
Methods and apparatus disclosed herein introduce a novel integration of sensing and neuromorphic computation that addresses the energy, latency, and complexity challenges of conventional event-based vision pipelines. A monolithic neuromorphic sensor fuses sensing and computation into a single neuro-transducer cell, including pixels that contain a photonic transducer, a membrane capacitor, and a Leaky Integrate-and-Fire (LIF) neuron whose membrane potential is driven directly by a raw physical stimulus rather than by an injected current. Adjacent neuro-transducers are linked by non-volatile, programmable RRAM synapses that store multi-bit weights and are updated locally via Spike-Timing-Dependent Plasticity (STDP)-compatible write pulses.
Improved breakdown test structures are provided. In some embodiments, multiple test structures may be combined into a single (e.g., two-terminal) test structure for monitoring interconnect voltage breakdown (VBD) of representative interconnect structures within scribe line regions.
Disclosed herein are microelectronic assemblies with tags disintegrated from cache memory, as well as related structures and techniques. In one aspect, a microelectronic assembly includes first and second dies stacked above one another in a stack of dies, where the first die includes cache memory with an array of memory cells and the second die includes tags for determining whether a requested piece of data is available in the cache memory. Cache memory may be implemented using DRAM cells to enable lower cost, higher memory cell density, and better power efficiency, while tags may be implemented using SRAM cells to realize higher speed and lower latency of memory operations.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 10/00 - Static random access memory [SRAM] devices
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
23.
PHOTONIC STACKS FOR MULTI-TIER PHOTONIC INTEGRATED CIRCUIT PACKAGE ASSEMBLIES
Multi-tiered photonic integrated circuit (PIC) die package assemblies, and related apparatuses, systems, and methods of fabrication are disclosed. A package assembly includes a lower tier having a base PIC die, which provides at least some functionality of a PIC core or unit. A photonics coupler is in an upper tier of the package assembly and optically connects the assembly to external optical devices. At least one middle tier of the package assembly, between the base PIC die and the photonics coupler, includes PIC die(s), electronic integrated circuit (EIC) die(s), or hybrid photonic and electronic IC (hybrid IC) die(s), or combinations thereof.
Multi-tiered photonic integrated circuit (PIC) die package assemblies, and related apparatuses, systems, and methods of fabrication are disclosed. A package assembly includes a lower tier having a base PIC die, which provides at least some functionality of a PIC core or unit. A photonics coupler is in an upper tier of the package assembly and optically connects the assembly to external optical devices. At least one middle tier of the package assembly, between the base PIC die and the photonics coupler, includes PIC die(s), electronic integrated circuit (EIC) die(s), or hybrid photonic and electronic IC (hybrid IC) die(s), or combinations thereof.
The middle tier die(s) may provide the remaining functionality of the PIC core or unit. A photonics via extends vertically through the middle tier and optically couples the PIC die and the photonics coupler.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
G02B 6/42 - Coupling light guides with opto-electronic elements
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
Disclosed herein is an amplifier device that includes a plurality of transistor sets connected in series. The plurality of transistor sets include a first set of series-connected transistors of a first conductivity type and a second set of series-connected transistors of a second conductivity type. Each transistor of the first set of transistors is differently sized from each other of the first set of transistors. A first control terminal receives a first signal varying between a first upper voltage level and a first lower voltage level. A second control terminal receives a second signal varying between a second upper voltage level and a second lower voltage level. An output terminal coupled to a second transistor of the first set and a second transistor of the second set is configured to provide an output signal varying between the first upper voltage level and the second lower voltage level.
Systems and methods are provided for detecting audio deepfakes, including synthetic speech generated using advanced artificial intelligence techniques. The disclosed techniques address the shortcomings of existing deepfake detection models, which often fail to robustly distinguish between authentic and synthetic audio and may require extensive retraining or large datasets. The deepfake detection system leverages verified audio samples of a known speaker to generate a distribution of detection scores using a speaker-independent deepfake detector, without modifying or retraining the underlying model. By segmenting the verified samples and constructing a statistical reference distribution, the system applies a statistical test to determine whether the detection scores from an unverified audio input are consistent with the reference distribution. This allows for accurate and efficient personalized deepfake detection, incorporating speaker-specific conditioning information without model retraining, and the resulting system is compatible with real-time applications.
G10L 17/06 - Decision making techniquesPattern matching strategies
G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
G10L 17/02 - Preprocessing operations, e.g. segment selectionPattern representation or modelling, e.g. based on linear discriminant analysis [LDA] or principal componentsFeature selection or extraction
In one embodiment, a housing is coupled to a device connector (e.g., an M.2-compatible expansion slot) on a circuit board. The housing may be a conductive material (e.g., metal) and sized to cover a device coupled to the connector such that the device may be substantially encompassed by the housing and the circuit board. The housing may contact, directly or indirectly, the device to provide thermal transfer. In addition, the housing may be connected to ground to provide electromagnetic interference (EMI) shielding of the device.
Technical solutions discussed herein include cooling systems for electronic devices, including low-pressure ionic blowers and electromagnetic air movers to improve thermal management in laptops. The cooling system may include multiple blower modules arranged in parallel or series configurations. The thermal solution may be a vapor chamber or a heat pipe, or may include a thin-film air-moving device integrated into an air gap. The cooling system may selectively operate between low pressure blower modules and centrifugal blowers based on cooling demands. The blower module may include an electrode configuration with a single exposed electrode. The cooling system may also incorporate an active noise cancellation system using phase-shifted signals between blower units.
For example, a computing device may be configured to process sound information received from an audio device of a user to identify first ambient sound information and second ambient sound information corresponding to a detected sound event in an environment of the audio device, and to determine direction-based information based on the first ambient sound information and the second ambient sound information. For example, the direction-based information may be based on a direction of a source of the sound event relative to a head of the user. For example, the computing device may be configured to trigger a sound event indication to be provided to the user. For example, the sound event indication may be based on the direction-based information.
H04R 1/40 - Arrangements for obtaining desired frequency or directional characteristics for obtaining desired directional characteristic only by combining a number of identical transducers
A supply voltage may be set using a local voltage regulator, such as a Digital Linear Voltage Regulators (DLVR). A DLVR may include a compensator, and the performance of the compensator may be affected by a dropout (DO) voltage. To improve the performance of a compensator, a number of compensator calculations may be pre-calculated to reduce the complexity of remaining real-time computations and enable compensator calculations to be completed within a single DLVR clock cycle. A DLVR may include a sense filter, and the DLVR transfer function (TF) may be modified using dynamic shaping of open loop gain and pole locations of a sense filter. The DO range associated with the DLVR TF may be changed according to a monitored DO(t) to reduce the sensitivity of a domain VMIN on dropout, which reduces power consumption, increases performance, and enables simplification of test flows.
G05F 1/563 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including two stages of regulation, at least one of which is output level responsive, e.g. coarse and fine regulation
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
30.
MEMORY WITH ONE ACCESS TRANSISTOR COUPLED TO MULTIPLE CAPACITORS
IC devices implementing memory with one access transistor coupled to multiple capacitors are disclosed. An example IC device includes a transistor having a region, wherein the region is either a source region or a drain region. Such an IC device further includes first and second platelines, and first and second capacitors, wherein a first capacitor electrode of the first capacitor is coupled to the region, a first capacitor electrode of the second capacitor is coupled to the region, a second capacitor electrode of the first capacitor is coupled to the first plateline, a second capacitor electrode of the second capacitor is coupled to the second plateline, the first capacitor is a three-dimensional capacitor, and the second capacitor is a planar capacitor.
In embodiments herein, a self-emissive display panel includes layer comprising a material with electrically controllable opacity, which can be switched between being substantially transparent and substantially opaque, e.g., to provide increased contrast for the display panel. The electrically switchable layer may include, for example, electrochromic glass or a layer of polymer-dispersed liquid crystals (PDLC).
Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.
Techniques are provided herein to form semiconductor devices that include forksheet transistors with a self-aligned dielectric spine having an airgap. The airgap may constitute a majority of the total volume of the dielectric spine, this lowering the dielectric constant of the dielectric spine and decreasing parasitic capacitance. In an example, first and second semiconductor devices have first and second semiconductor regions, respectively, extending in a first direction between corresponding source and drain regions. The first and second semiconductor regions may include any number of nanosheets. A dielectric spine extends in the first direction between the first and second semiconductor regions. The dielectric spine includes a dielectric liner adjacent to the sides of the first and second semiconductor regions. A remaining volume of the dielectric spine at least partially bound by the dielectric liner includes an airgap. A dielectric cap structure may be included over the airgap.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a second die having a first surface, an opposing second surface, and side surfaces between the first surface and the second surface, wherein the first surface of the second die is electrically coupled to the surface of the first die, and wherein the side surfaces of the second die are scalloped. In some embodiments, side surfaces of the second die may include a protective coating material, where the protective coating material includes an alkyl silane, a fluoroalkyl silane, a thiol, a phosphonic acid, an alkanoic acid, a siloxane, a silazane, a polyolefin, or a fluorinated polymer. In some embodiments, a microelectronic assembly may further include a dielectric material around a plurality of second dies and the dielectric material does not have an interface seam.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 29/34 - Semiconductor bodies having polished or roughened surface the imperfections being on the surface
35.
SEMICONDUCTOR CORE LAYER INCLUDING GLASS SHEET HAVING EDGE SEALANT STRUCTURE AND METHOD OF MAKING SAME
A package substrate includes: a sheet including glass; build-up layers respectively on a top surface and on a bottom surface of the sheet; structures defining electrically conductive pathways within the sheet and within the build-up layers; and a ribbon-shaped edge structure in recesses defined at lateral edges of the sheet and defined with respect to lateral edges of the build-up layers, the ribbon-shaped edge structure extending in a direction along a thickness of the sheet, having a lateral edge surface facing away from the sheet, and comprising an edge structure material not including glass and not including metal.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
36.
REACHABILITY EVALUATION USING KINEMATIC MODEL AND TRAVERSAL COSTS
The present disclosure provides a system including processors and memory storing instructions that, when executed, cause the system to receive three-dimensional data representing an environment, including navigable surfaces, points of interest, and obstacles. The system constructs a reachability graph representing connections between navigable surfaces and points of interest. The system performs motion planning using a kinematic model by assigning traversal costs to paths that intersect with obstacles while maintaining connectivity through obstacles in the reachability graph. The system evaluates reachability to points of interest based on traversal costs and generates output identifying which points of interest are reachable.
G06F 30/13 - Architectural design, e.g. computer-aided architectural design [CAAD] related to design of buildings, bridges, landscapes, production plants or roads
Embodiments herein relate to ensuring the integrity of signal paths in stacked semiconductor devices. In an example implementation, a faulty signal path between die can be repaired by re-routing the path within the affected die, in a per-layer repair approach. Also disclosed are a sequential repair process for N-stacked die prior to integration, an in-field fault detection and repair technique, a proactive in-field repair technique for preemptive die maintenance, and a technique to drive select lines of repair multiplexers to provide rerouting of signal paths.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
G01R 31/26 - Testing of individual semiconductor devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
38.
ROBOTIC INSPECTION SYSTEM WITH NON-PLANAR OPTICAL ELEMENT
The present disclosure provides a robotic inspection system including a robotic platform, a non-planar optical element mounted via a multi-degree-of-freedom actuator system configured to controllably position and orient the optical element, wherein the optical element introduces non-linear distortion into reflected images. The system further includes an imaging system with a camera mounted to the robotic platform and configured to capture images reflected from the optical element at different orientations. The system also includes a processing system configured to receive the captured images from the imaging system, receive positional information corresponding to the different orientations of the optical element and imaging system, and process the images with the positional information to compensate for non-linear distortion and generate three-dimensional depth information of a target object within the imaging system's field of view.
Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanoribbons (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanoribbons. The transistors include a gate structure vertically between the nanoribbons. The nanoribbons are doped at their opposing ends and/or gaps are laterally between the gate structure and the source and drain structures.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Gate-all-around circuit structures having differentiated release layers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Dielectric spacers are adjacent to the first gate structure and the second gate structure and vertically between adjacent ones of the first set of horizontal nanowires and the second set of horizontal nanowires. Each of dielectric spacers has a notch at a location vertically between the first set of horizontal nanowires and the second set of horizontal nanowires.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Technologies for a compact and low-crosstalk multilayer waveguide stack are disclosed. In an illustrative embodiment, a photonic integrated circuit (PIC) die includes a 3D array of waveguides arranged in a multilayer stack. Individual waveguides have a propagation constant different from the propagation constant of neighboring waveguides, which can reduce crosstalk between neighboring waveguides. In an illustrative embodiment, the propagation constant can be controlled by changing the width of individual waveguides. In other embodiments, the propagation constant can be controlled by changing any suitable parameter, such as the height of the waveguides, the core of the waveguides, the cladding of the waveguides, etc.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
42.
EDGE COATING FOR GLASS CORE SUBSTRATE WITH A FRAME
Embodiments disclosed herein may include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material. In an embodiment, a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, the apparatus may further comprise a layer surrounding a perimeter of the first substrate, the second substrate, and the third substrate, where the layer comprises a dielectric material, with a fourth edge of the layer that is substantially linear. In an embodiment, a frame surrounds and contacts the fourth edge of the layer.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded.
Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded.
Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Different memory layers are coupled to different interconnect regions. An interconnect pitch in an interconnect region is larger than the corresponding word-line or bit line pitch in the memory region.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
Disclosed are processing apparatuses and methods with a plurality of memory channels that operate at different frequency values to spread EMI emissions over a wider frequency range. The channels may or may not also employ spread spectrum clocking (SSC).
Devices and systems with interposers that do not include through-substrate vias, and methods of forming the same, are disclosed herein. In one example, a microelectronic assembly includes an interposer and one or more integrated circuit (IC) dies coupled to the interposer. The interposer includes one or more conductive traces and one or more vias, but the interposer does not include through-substrate vias. The respective IC dies are electrically coupled to the interposer via dielectric-to-dielectric and metal-to-metal bonds at the interface between the interposer and the respective IC dies.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate. In an embodiment, a portion of the first substrate extends past edge surfaces of the second substrate and the third substrate. In an embodiment, a layer surrounds the portion of the first substrate, where the layer comprises a tapered cross-sectional shape, and where a first sidewall that contacts the second substrate and the third substrate has a first height that is greater than a second height of a second sidewall that faces away from the second substrate and the third substrate.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
C03C 17/32 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with organic material with synthetic or natural resins
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
Embodiments disclosed herein include an apparatus that includes a first substrate, where the first substrate comprises a glass layer, a second substrate over the first substrate, and a third substrate under the first substrate, where the second substrate and the third substrate comprise an organic dielectric material, and where a first edge of the first substrate is offset from a second edge of the second substrate and a third edge of the third substrate. In an embodiment, a layer contacts the first substrate, the second substrate, and the third substrate, where a portion of an outer sidewall of the layer is substantially parallel to the first edge of the first substrate.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
C03C 17/00 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating
C03C 17/32 - Surface treatment of glass, e.g. of devitrified glass, not in the form of fibres or filaments, by coating with organic material with synthetic or natural resins
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a conductive pad and an electrostatic discharge (ESD) protection circuitry coupled to the conductive pad. The ESD protection circuitry includes a first diode including a first node coupled to a first supply node, and a first additional node coupled to the conductive pad; a second diode including a second node coupled to the conductive pad, and a second additional node coupled to a second supply node; a resistor including a first resistor node coupled to the conductive pad, and a second resistor node; and a switch circuit including a first node coupled to the first resistor node, and a second node coupled to the second resistor node.
Disclosed herein is method for finishing a conductive part with a sustainable coating, where the part may be a magnesium-based chassis/housing for electronic equipment. The method includes depositing electrochemically a coating material onto the conductive surface of the component, placing a thin film over the coating material, and attaching the thin film onto the component by way of a vacuum transfer process. A graphite-based coating (e.g., graphene) may also be placed between the conductive surface and the thin film. The thin film may be decorative/cosmetic thin film to provide an attractive aesthetic.
C25D 13/04 - Electrophoretic coating characterised by the process with organic material
C09D 5/44 - Coating compositions, e.g. paints, varnishes or lacquers, characterised by their physical nature or the effects producedFilling pastes for electrophoretic applications
Integrated circuit (IC) devices having glass layers in package substrates. An IC device substrate may include a solid glass layer and a polymer layer that forms a frame on sidewalls and an upper surface of the glass layer, and the glass layer may include a tab or nubbin that extends through the frame of the polymer layer. The substrate may include electrical vias through the substrate and electrical traces on one or both sides of the substrate. Portions of a glass panel (for example, along saw streets) may be removed and replaced with polymer frame materials. The glass panel may be sawn into glass substrates by sawing through the polymer and through glass bridge portions, which may be of minimal thickness.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Provided is an apparatus comprising interface circuitry, machine-readable instructions, and processing circuitry to execute the machine-readable instructions to receive first data indicating that a device is plugged into an interface. The machine-readable instructions further comprise instructions to cause output of a timestamp to the device. The machine-readable instructions further comprise instructions to receive second data indicating at least an identifier relating to the device determine, based on the timestamp and the second data, a first memory mapped input/output, MMIO, offset address for the device. The machine-readable instructions further comprise instructions to receive a second MMIO offset address for the device determined by the device. The machine-readable instructions further comprise instructions to decide on integrity of the device based on a comparison of the first and the second MMIO offset addresses.
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die; a second die and a third die electrically coupled to the first die; a dielectric material, around the second die and the third die, having a non-planar surface; a first material, on the non-planar surface of the dielectric material and on the second die and the third die, having a thermal conductivity greater than 10 watt per meter-kelvin (W/m-K) and a thickness between 1 micron and 2 microns; a second material, on the first material, including titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, or silicon, carbon, and nitrogen; and a third material, on the second material, having a thermal conductivity greater than 150 W/m-K and a thickness between 1 micron and 200 microns.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
53.
TECHNOLOGIES FOR A STACKED INTEGRATED CIRCUIT PACKAGE
Technologies for stacked integrated circuit packages are disclosed. In an illustrative embodiment, an integrated circuit package, such as a processor, includes a primary circuit board and an auxiliary circuit board. Components such as processor dies and memory packages may be mounted on the top side of the primary circuit board, and the auxiliary circuit board may be mounted on the bottom side of the primary circuit board. The auxiliary circuit board may include an array of contacts to interface with a motherboard. The top side of the primary circuit board may require a relatively large area to support the processor dies and memory packages. The auxiliary circuit board may have a smaller area due to a smaller number of contacts needed with the motherboard. The additional area on the bottom side of the primary circuit board may be used to support a stiffener or other components.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Assemblies and methods of manufacturing assemblies that include sockets and packaged semiconductor chips are provided. The package substrates for the semiconductor chips can include cores that are formed from a solid amorphous glass layer. The package substrates can have gaps around sides and alignment pins in the assemblies.
Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.
Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.
An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.
Integrated circuit (IC) devices having nonplanar transistor structures of complementary conductivity type.
An IC device may include first and second transistors with a stack of nanoribbons in a channel region of the first transistor and one or more fins in a channel region of the second transistor, and the one or more fins may be on a trench isolation over the substrate. The nanoribbons may have upper and lower (100) surfaces, and sidewalls of the one or more fins may be (110) surfaces. The fins on the isolation structure may be between stacks of nanoribbons, the nanoribbons may be over subfins of the substrate, and the isolation structure may be between the subfins.
The fins may be epitaxially grown as vertical nanoribbons from (and with a same crystal lattice and alignment as) a sidewall of the stack of nanoribbons in the first transistor.
H01L 27/092 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
H01L 21/8238 - Complementary field-effect transistors, e.g. CMOS
H01L 29/04 - Semiconductor bodies characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
Integrated circuit (IC) devices employing thermal management of heat-generating dies.
Integrated circuit (IC) devices employing thermal management of heat-generating dies.
Heat may be removed from an IC die by supplying a coolant liquid to a chamber thermally coupled to the die and by discharging the coolant from the chamber as a vapor. Measured or provided die and/or coolant parameters may be used to control coolant flow. A device includes a porous structure in a chamber thermally coupled to an IC die, the chamber in a body having a first microchannel network configured for supplying liquid coolant to the chamber and a second microchannel network configured for removing vaporized coolant from the chamber. The chamber may include multiple supply openings for directing or controlling coolant to particular areas of the chamber and one or more associated dies. The chamber may include multiple exhaust openings for removing coolant from particular areas of the chamber.
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/367 - Cooling facilitated by shape of device
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
57.
STACKS OF INTEGRATED CIRCUIT STRUCTURES WITH MEMORY AND BACK-SIDE POWER DELIVERY
IC devices with stacks of IC structures with memory and back-end power delivery are disclosed, where different IC structures of a stack are bonded together. An example IC device includes a first and a second IC structures. The first IC structure includes a layer of memory cells, a power delivery structure at the back side of the layer of memory cells, and a layer of signal interconnects at a front side of the layer of memory cells. The second IC structure is attached to the layer of signal interconnects of the first IC structure and includes a layer of memory cells and a power delivery structure at a back side of the layer of memory cells of the second IC structure. The layer of signal interconnects of the first IC structure may be configured to provide signals to memory cells of, both, the first and the second IC structures.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
58.
MASK VARIABILITY REDUCTION THROUGH LOCALITY PRESERVING PATTERN HASHES
A method includes generating a hash comprising a plurality of values based on a geometric pattern within a window that represents a portion of a physical design for a semiconductor mask layer, the window including at least a portion of a polygon; determining a displacement value for a segment of the polygon based on the hash; and modifying a position of a segment of the polygon based on the displacement value.
It is provided a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries of an apparatus, causing the one or more processing circuitries to perform locally on the apparatus a method. The method includes issuing periodic refresh commands to a memory device configured to perform refresh operations on a plurality of its memory regions. The method further comprises receiving the status value transmitted from the memory device. The method further comprises determining based on the status value whether a targeted-refresh condition is satisfied for one or more of the memory regions. The method further comprises transmitting, for each of the one or more memory regions, a number of targeted refresh commands to the memory device, the number being based on the status value of the corresponding memory region.
Techniques and mechanisms for a cache search to be performed based on a search parameter which identifies an execution domain. In an embodiment, a processor core comprises circuitry to facilitate the servicing of a memory access request by performing a cache search according to a domain-specific search mode. A criteria of the domain-specific search mode includes both an address parameter and a domain identifier parameter. The circuitry detects a mismatch condition for a given cache line where it is determined that—notwithstanding a correspondence between the address parameter and an address value for the cache line—the domain identifier parameter does not correspond to a domain identifier value which corresponds to that given cache line. In another embodiment, the processor core is operable to selectively search the cache according to either one of a domain-specific search mode or a domain-generic search mode.
In embodiments of the present disclosure, an integrated transistor device includes a gate-all-around (GAA) transistor and a FinFET transistor device on the same substrate. The FinFET transistor includes a dielectric region between the channel of the FinFET transistor and the substrate.
H01L 27/12 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
H01L 21/84 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
Embodiments disclosed herein include an apparatus that includes a substrate with an edge surface. In an embodiment, the substrate includes a glass layer, and a via is formed through a thickness of the substrate. In an embodiment, a recess is formed into the edge surface. In an embodiment, a height of the recess measured in a direction from a bottom of the substrate to a top of the substrate is greater than a depth of the recess.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers
Embodiments disclosed herein may include an apparatus that includes a substrate with a first edge surface. In an embodiment, the substrate may comprise a glass layer. In an embodiment, a via is formed through a thickness of the substrate. In an embodiment, an organic dielectric layer is provided over the substrate, and the organic dielectric layer has a second edge surface. In an embodiment, a recess is formed into the second edge surface of the organic dielectric layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
64.
METHODS AND SYSTEMS FOR FORMING INTEGRATED CIRCUIT PACKAGES COMPRISING GLASS LAYERS WITH THIN SINGULATED PORTIONS
An apparatus comprising a package substrate, the package substrate comprising a glass structure; at least one buildup layer above the glass structure; and at least one buildup layer below the glass structure; wherein the glass structure comprises a first portion having a first thickness and a second portion that extends outward from the first portion, wherein the second portion has a second thickness that is smaller than the first thickness.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
65.
SPLIT PROCESSING OF INTEGRATED CIRCUIT LAYERS WITH HIGH ACCURACY BONDING
Split processing of integrated circuit layers with high accuracy bonding is described. In an example, an integrated circuit structure includes a front-end-of-line (FEOL) stack having an uppermost surface including first conductive features and first dielectric features. A back-end-of-line (BEOL) stack is above the FEOL stack. The BEOL stack has a bottommost surface including second conductive features and second dielectric features in contact with corresponding ones of the first conductive features and first dielectric features of the uppermost surface of the FEOL stack, respectively. The second conductive features are laterally offset from the corresponding first conductive features.
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
A dynamic random-access memory (DRAM) device has a layer of backend transistors that are formed over the DRAM array. For example, the backend transistors may include channel regions or other transistor structures that are in direct contact with an etch stop layer formed over the DRAM array. The backend transistors may increase the amount of surface area that can be utilized for memory cells by moving transistors for implementing power gating, SRAM tags, or other features to a backend layer that is over the storage capacitors. Low temperature processes may be used to fabricate the backend transistors while minimizing damage to frontend structures.
A core layer of a package substrate includes a sheet including glass; structures defining electrically conductive pathways within the sheet; and a saw street structure (SSS) at one or more lateral edges of the sheet, the SSS one or more oblong bodies in respective cavities defined in one or more lateral edges of the sheet, individual ones of the one or more oblong bodies extending in a direction along a thickness of the sheet, having a lateral edge surface facing away from the sheet, and comprising a material (SSS material) including at least one of a polymer or a metal. The core layer further includes a plurality of build-up layers on at least one of a top surface or a bottom surface of the core layer, the plurality of build-up layers electrically coupled to the electrically conductive pathways of the core layer.
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
68.
APPARATUS, SYSTEM, AND METHOD OF A SAFETY-BASED MULTI-ACTUATOR DRIVER FOR A MOBILE ROBOT
For example, a safety-based multi-actuator driver may be configured to drive a plurality of actuators of a plurality of wheels of a mobile robot. For example, the safety-based multi-actuator driver may include one or more safety-sensor inputs to receive safety-sensor information from one or more safety sensors of the mobile robot; a plurality of driver outputs to provide a plurality of actuator-drive outputs to drive the plurality of actuators; and a plurality of monitoring inputs to receive actuator monitoring information corresponding to a functionality of the plurality of actuators. For example, the safety-based multi-actuator driver may include a controller to control the plurality of actuator-drive outputs for a controlled safety-stop of the mobile robot based on a sensor-based event identified based on the safety-sensor information, and to configure the plurality of actuator-drive outputs for the controlled safety-stop based on an actuator malfunction event identified based on the actuator monitoring information.
A conformal nitride-rich carbide layer located on a dielectric-on-dielectric layer (a dielectric layer located on an interlayer dielectric) and metal line cap layers in an interconnect stack of an integrated circuit structure provides for improved electromigration. The carbide layer can enable integrated circuit structures to have a reduced topography prior to etch stop stack formation. In addition to enabling improved electromigration of the metal lines the carbide layers can reduce the current leakage between metal lines and nearby vias.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
Embodiments herein relate to compute-in-memory. In one aspect, memory cells in an array include a larger, primary element and a smaller, secondary element in parallel. The memory cells are phase-change memory (PCM) cells in an example implementation. The second elements are pre-programmed to narrow a conductivity distribution of a column of cells. The pre-programming is based on a measured conductivity distribution of the primary elements of the column. In another aspect, selected memory cells in an array are read using an alternating current (AC) signal which reduces sensing noise. Different bit lines can receive signals with different frequencies and/or amplitudes.
Photonics through vias, stacked photonic integrated circuit (PIC) die package assemblies, related apparatuses, systems, and methods of fabrication are disclosed. A PIC die has a first surface and opposing second surface and an opening extending between the first and second surfaces to define a sidewall of a substrate material of the PIC die, a photonics via is within the opening and has a first material on the sidewall and an optional second material within the first material. The refractive indices of the substrate material, first material, and optional second material are selected to provide total internal reflection for light waves within the photonics via.
A waveguide, includes a first waveguide unit, which includes a first substrate, and a plurality of protrusions extending from a surface of the first substrate; a second waveguide unit, which includes a second substrate; and a plurality of protrusions extending from a surface the second substrate; wherein the first waveguide unit is configured to be assembled with the second waveguide unit such that at least a subset of the plurality of protrusions extending from the surface of the first substrate are placed between and substantially parallel to the plurality of protrusions extending from the surface of the second substrate.
H04B 1/48 - Transmit/receive switching in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter
Techniques for supporting cached and non-cached atomic operations in a scalable shared-memory system are described. In certain examples, a computing system includes a first compute socket comprising a plurality of first compute tiles that are coupled by a first interconnect and that each comprise a plurality of first tile memories, a respective plurality of first tile memory atomic operations management circuits for the plurality of first tile memories, and a plurality of compute slices that each comprise a first compute circuit, a first cache, a first cache atomic operations management circuit for the first cache, a first memory, and a first memory atomic operations management circuit for the first memory; and a second compute socket, coupled to the first compute socket, comprising a plurality of second compute tiles that are coupled by a second interconnect and that each comprise a plurality of second tile memories, a respective plurality of second tile memory atomic operations management circuits for the plurality of second tile memories, and a plurality of compute slices that each comprise a second compute circuit, a second cache, a second cache atomic operations management circuit for the second cache, a second memory, and a second memory atomic operations management circuit for the second memory, wherein a first cache atomic operations management circuit of a first compute tile of the first compute socket is to, in response to an atomic memory access request for data by a first compute circuit of the first compute tile: read a virtual address of the atomic memory access request, and in response to a field of the virtual address being set to a first value, cause a lock of the data in a first cache of the first compute tile, perform an operation on the data to generate updated data, store the updated data in the first cache, and unlock the data in the first cache in response to the store.
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
74.
Apparatus and Method to Inject Non-Canonical Addresses into Faulting Instruction Outputs to Mitigate Transient Execution Vulnerabilities
An apparatus and method for injecting non-canonical addresses into instruction outputs to mitigate transient execution vulnerabilities. For example, one embodiment of a method comprises: decoding a sequence of instructions by a decoder of a processor, the sequence of instructions including a conditional instruction; executing the conditional instruction, wherein executing includes: outputting a valid address value indicated by the conditional instruction to a destination when a condition associated with the conditional instruction is determined to be true; and setting an output fault value associated with the conditional instruction to a non-canonical address value or a truncated portion of the non-canonical address value when the condition associated with the conditional instruction is determined to be false, and outputting the non-canonical address value or truncated portion of the non-canonical address value to the destination.
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
75.
COMPENSATOR FOR INTERNAL ELECTROMAGNETIC INTERFERENCE IN SEM-BASED AC PROBING
Disclosed herein are devices, systems, and methods for cancelling an internal magnetic field caused by a test signal within a test chamber of a scanning electron microscope (SEM). A compensator device includes a set of one or more wire loops around a test chamber and an amplifier configured to drive a current in each wire loop of the set of one or more wire loops. The compensator device also includes a control circuit configured to adjust, via the amplifier, a corresponding amplitude modulation of the current in each wire loop, wherein the control circuit is configured to adjust the corresponding amplitude modulation based on a test signal within the test chamber.
Disclosed herein is zero-latency switching between two resolution and frame rate modes. The system includes receiving a trigger to switch a video data stream of frames between a first resolution and frame rate mode and a second resolution and frame rate mode. The system also includes switching, in response to the trigger, the video data stream between the first resolution and frame rate mode and the second resolution and frame rate mode, wherein a total horizontal pixel width of each frame of the video data stream in the first resolution and frame rate mode and of each frame of the video data stream in the second resolution and frame rate mode are the same, wherein a pixel clock rate of the video data stream in the first resolution and frame rate mode and the video data stream in the second resolution and frame rate mode are the same.
Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
G06T 5/20 - Image enhancement or restoration using local operators
H04N 19/85 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
78.
METHODS AND ARRANGEMENTS FOR RESOURCE ALLOCATION FOR SIDELINK POSITIONING
Logic may perform resource selection from a resource pool to deter-mine a set of resources from the resource pool for transmission of a reference signal. Logic may autonomously allocate the set of resources for a transmission of the reference signal within a physical sidelink shared channel (PSSCH) or as a standalone transmission. Logic may generate a control information signal to signal the set of resources for the reference signal, the control information signal comprising a source identifier field, a destination identifier field, and one or more fields to indicate automatic gain control, guard symbols, or a combination thereof. And logic may encode the control information signal for transmission to a second UE via the interface.
According to the various aspects, the present methods provide for the laser-assisted dicing of semiconductor workpieces that produce semiconductor devices with glass cores having semi-transparent edges.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Embodiments disclosed herein include an apparatus that comprises a substrate, and the substrate includes glass. In an embodiment, an opening is provided through a thickness of the substrate, and a layer is along a sidewall of the opening. In an embodiment, the layer comprises a polymer and an electrical conductor that comprises carbon. In an embodiment, a via is provided in the opening, and the via is an electrically conductive material.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Disclosed are voltage regulator embodiments with dynamically adjustable soft-switching entry (e.g., ZCD) thresholds to efficiently manage entry into soft-switching under different load conditions.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
G01R 19/175 - Indicating the instants of passage of current or voltage through a given value, e.g. passage through zero
Multi-layer etch stop layers are described. In an example, an integrated circuit structure includes a conductive line in a first interlayer dielectric material above a substrate. A first dielectric etch stop layer, a second dielectric layer and a third dielectric layer are on the conductive line and the first interlayer dielectric material. A second interlayer dielectric material is on the third dielectric etch stop layer. An opening is in the second interlayer dielectric material, in the third dielectric etch stop layer, and in the second dielectric etch stop layer, in the first dielectric etch stop layer. A conductive structure is in the opening, the conductive structure in direct contact with the conductive line.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
According to the various aspects, a method is provided for dicing a semiconductor panel having a glass core with topside build-up (BU) layers, backside BU layers, and interconnects. In an aspect, a hard mask is deposited on the semiconductor panel and patterned to form openings for a plurality of cut-streets. In an aspect, the dicing of the semiconductor panel includes using plasma dicing steps to form cut-streets through the topside BU layers and the backside BU layers, and using a mechanical sawing step or plasma dicing step to cut through the glass core. In another aspect, the dicing of the semiconductor panel further includes using an acid rinse to remove metal salts when cutting through the glass core during the plasma dicing step. In another aspect, a singulated die may have a first BU sidewall and a second BU sidewall having a morphology that includes semi-sphere fillers.
C03B 33/07 - Cutting armoured or laminated glass products
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Disclosed herein are microelectronic assemblies and related devices and methods. In some embodiments, a microelectronic assembly may include a glass layer having a first surface, a second surface opposite the first surface, and a side surface extending between the first surface and the second surface, wherein the side surface protrudes at a middle of the glass layer; a dielectric layer at the first surface of the glass layer; and a recess in the dielectric layer at the first surface of the glass layer. In other embodiments, a microelectronic assembly may include a dielectric layer at a surface of a glass layer and a material along a side surface of the dielectric layer, the material including a dry film photoresist, a water-soluble material, a thermal decomposable material, or a non-filled polymeric material. In other embodiments, the dielectric layer may include a conductive bulk material along a side surface.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
85.
MICROELECTRONIC ASSEMBLIES INCLUDING A GLASS-CORE WITH POST-SINGULATION EDGE FEATURES
Disclosed herein are microelectronic assemblies and related devices and methods for alleviating crack formation and propagation in glass by providing various edge features during or after singulation of a glass panel into individual glass units. In some embodiments, a microelectronic assembly includes a glass core (e.g., a layer of glass including a rectangular prism volume) having a first face, a second face opposite the first face, and an edge between an end of the first face and an end of the second face, and further includes a protection coating on the edge, where a material of the protection coating includes a low-density polystyrene foam, an ionogel, a fiber reinforced resin, a pre-impregnated dielectric, a pre-impregnated fabric, a carbon nanotube reinforced epoxy resin, a metal oxide, a mold material, or a solder resist.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
86.
SYSTEMS AND METHODS FOR MULTI-LAYER OPC (OPTICAL PROXIMITY CORRECTION) METROLOGY USING ELECTRICAL TEST DATA
Systems and methods for multi-layer optical proximity correction (OPC) metrology. The OPC metrology system accesses three layers of OPC contour data, the layers of OPC data generated for a drawn integrated circuit layout characterized for a foundry process node. The three layers include a first metal layer, a second metal layer, and a via layer. A feature, such as a via, is formed in the three layers. The system receives user input defining a check (geometric analysis) for the feature, and a limit. The system performs the check on the features and generates a flag for the feature when the limit is exceeded. The system can generate output that reflects the integration of multiple checks and predicts risks and yields for the foundry process node.
G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
According to various aspects of the present disclosure, a semiconductor testing equipment may include a thermal head assembly having a body with a recess that is unobstructed and designed to fit over a die on the semiconductor package. A sealing member on the thermal head assembly engages a landing area on the semiconductor package to form a sealed chamber. The semiconductor package may be uniformly loaded by introducing a gas and incrementally increasing the gas pressure in the sealed chamber and increasing mechanical load on the sealing member onto the landing area to prevent leakage. Once the sealed chamber is fully sealed, the combined internal pressure from the circulating gas and a sealing perimeter load enables the proper socketing of the semiconductor package. Thereafter, the gas may be replaced with a circulating liquid refrigerant to remove the heat generated by the die during the testing of the semiconductor package.
An apparatus and method for dynamic snoop filter partitioning. One embodiment of a processor is coupled to a socket, the processor comprising: a plurality of cores; a plurality of caches to store cache lines read from memory by the plurality of cores; cache management circuitry to manage coherency of the cache lines; snoop handling circuitry comprising a snoop filter, the snoop handling circuitry to: track snoop filter allocations for local requests and remote requests to at least a first sub-partition of a first snoop filter over one or more time windows, the local requests comprising requests from the plurality of cores or other circuit blocks of the processor and the remote requests comprising requests from a different processor in a different socket; determine a victim snoop filter entry in the first snoop filter based, at least in part, on the tracked snoop filter allocations over the time windows.
A semiconductor device and a method for fabricating a semiconductor are described. The semiconductor device includes two modules, each module including two tiers, each tier including (i) a passive die including through-silicon vias (TSVs) arranged side-by-side laterally with a core die and (ii) bumps coupling the TSVs and an overhang portion of the core die of a second tier to the TSVs the first tier, the first module further including a bottom redistribution layer (RDL) on which the first second tier of the first module is disposed and a top RDL disposed on the second tier of the first module, the bottom RDL coupled to the bumps disposed on the first tier of the first module while the top RDL configured to couple the bumps of the first tier of the second module to the TSVs of the second tier of the first module in a one-to-one manner.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
A control system for human-robot collaboration, including: a passive reactive control path implemented through a virtual damping system and configured to generate reactive control signals in response to human-applied interaction inputs; a predictive control path configured to generate predictive control signals based on predicted human performance objective inferred online from measured contact wrenches; and a signal blending component configured to combine the reactive control signals and the predictive control signals, wherein the predictive control signals are bounded in magnitude such that passivity of the reactive control path is preserved and stability of closed-loop human-robot interaction is maintained during collaboration.
B62D 57/032 - Vehicles characterised by having other propulsion or other ground-engaging means than wheels or endless track, alone or in addition to wheels or endless track with ground-engaging propulsion means, e.g. walking members with alternately or sequentially lifted supporting base and legVehicles characterised by having other propulsion or other ground-engaging means than wheels or endless track, alone or in addition to wheels or endless track with ground-engaging propulsion means, e.g. walking members with alternately or sequentially lifted feet or skid
A wireless communication device includes at least two antennas and transmitter circuitry incorporating an attenuation circuit. The attenuation circuit has a first port coupled to a first power amplifier and a second port coupled to a second power amplifier. A matching network connects the first and second ports and comprises a pair of coupled lines. Auxiliary lines are coupled to the coupled lines to enable programmable attenuation while maintaining wideband performance. The coupled-line matching network provides compact, low-loss interstage impedance matching and supports integration into mmWave RF transmit chains. By leveraging auxiliary lines and associated attenuation control, the device achieves fine gain programmability with minimal insertion loss and negligible area overhead, improving linearity and efficiency relative to transformer-based designs. This architecture is suitable for high-frequency systems requiring robust gain control across large bandwidths, such as sub-THz and mmWave radios.
Systems and methods are provided for transforming audio signals captured by a throat microphone into signals emulating speech recorded with a conventional air-conduction microphone. Throat microphones employ vibration sensors positioned on the neck to capture audio, making them suitable for high-noise environments. However, throat microphone signals lack high-frequency components, reducing intelligibility and degrading automatic speech recognition performance. The techniques provided herein apply signal-processing operations and a lightweight neural network to reconstruct missing spectral details. The input signal is converted to log-Mel spectra and modeled as a smooth average spectrum (SAS) plus a residual component. A neural network predicts a conventional-microphone SAS. A vocoder synthesizes an enhanced audio signal after combining the predicted SAS with the residual component. The approach improves speech intelligibility and ASR accuracy while maintaining low computational complexity, enabling real-time, on-device processing in noisy environments and supporting hands-free communication for applications such as collaborative robotics and augmented reality.
G10L 25/18 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the type of extracted parameters the extracted parameters being spectral information of each sub-band
G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks
H04R 1/46 - Special adaptations for use as contact microphones, e.g. on musical instrument, on stethoscope
A power delivery system is described that enables instant 20V/28V power delivery to sink devices by utilizing unique Configuration Channel (CC) resistor signatures to bypass standard power negotiation delays. The system may implement non-standard pull-down resistors (Rd) in sink devices and matching unique pull-up resistors (Rp) in source adapters to create CC voltages outside legacy USB PD specification ranges, instantly signaling full-power capability without traditional multi-step negotiations. Upon detecting such compatible unique signatures, the source may immediately apply a VBUS voltage of 20V or 28V at full current, eliminating the boot delays caused by standard USB PD negotiation processes. The system also avoids problematic sink standby (pSnkStdby) power consumption limitations that prevent dead battery boot scenarios. The system maintains backward compatibility through automatic fallback to standard USB PD negotiation when non-compliant devices are connected.
Real-time neural video codecs face significant latency and energy bottlenecks due to pixel-level grid sampling, which requires irregular, fine-grained memory accesses and limits efficient hardware acceleration. To address this, a sub-tile-based grid sampling technique is disclosed herein. The technique determines super tile sizes using motion vector gradients, neural network parameters, and available on-chip memory. A super tile is split into sub-tiles by detecting motion boundaries through motion vector analysis, where a sub-tile has homogeneous motion vectors. For each sub-tile, a reference bounding box is computed to enable efficient block transfers of reference data, and per-pixel metadata is generated for feature interpolation. The pipelined, parallelizable solution reduces number of memory accesses and computational overhead, compared to existing pixel-based techniques.
H04N 19/43 - Hardware specially adapted for motion estimation or compensation
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/139 - Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
H04N 19/172 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a picture, frame or field
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
H04N 19/436 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
H04N 19/55 - Motion estimation with spatial constraints, e.g. at image or region borders
Efficient data movement in neural network accelerators operating within virtualized memory systems is challenged by high address translation latency and unique data access patterns. To address this challenge, address translation prefetch (ATP) mechanisms can be implemented to proactively translate virtual memory addresses before data movement. ATP can be performed in advance of any data movement or concurrently with data movement while being throttled by page transition in the data movement request stream. The ATP mechanism can enforce quotas on outstanding ATP requests, independently for read and write streams, to preserve resources for other processes running on the neural network accelerator. In dealing with competing ATP requests, the mechanism can employ weighted arbitration to balance between different types of ATP requests, utilizing a programmable ratio. The ATP mechanisms enable scalable, high-throughput neural network inference in virtualized environments, addressing data movement bottlenecks in neural network accelerator deployments.
Systems, apparatus, articles of manufacture, and methods to generate synthetic images for training of defect detection models are disclosed. An example system disclosed herein produces synthetic images of pallet defects to train object detection models. In some examples, a small set of real images containing defects, associated masks and textual descriptions is used to fine tune a latent diffusion model. The fine-tuned model accepts a masked input image, a mask that defines the region to be altered, and a defect description, and generates a synthetic image with the defect inpainted into the masked region. In some examples, generated synthetic images are filtered to remove outliers that do not match the real defect distribution. The filtered synthetic dataset, together with a limited set of real images, is then used to train a downstream object detection model capable of identifying pallet damage in captured images.
Systems, apparatus, articles of manufacture, and methods are disclosed for zero-copy tensor combination via memory management unit remapping. An example method includes identifying physical memory addresses of tensors of a machine learning model, the tensors stored in a key value cache, the tensors including a first tensor and a second tensor stored at respective physical memory addresses, creating a range of virtual addresses for a combined tensor, the combined tensor to represent a combination of the first tensor and the second tensor, and binding the physical memory addresses of the tensors to the range of virtual addresses using a memory management unit.
In some aspects, a semiconductor device is provided. The semiconductor device includes a plurality of core dies; and a plurality of passive dies, each of the plurality of passive dies corresponding to one respective core die of the plurality of core dies, wherein each of the plurality of passive dies comprises a plurality of through-silicon vias configured to connect the plurality of core dies with a controller die, and wherein the plurality of core dies and the plurality of passive dies are arranged vertically into first to Nth tiers in a manner that each tier of the first to Nth tiers includes a core die of the plurality of core dies and a corresponding passive die of the plurality of passive die placed side-by-side horizontally.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
99.
Apparatus and Methods for Water-Assisted Singulation
According to the various aspects, a present tool assembly or apparatus includes a water delivery component configured to direct water to a workpiece, and a cutting component for removing material to form cut-streets for die singulation. The present tool assembly is configured to operate to remove build-up layers and other layers from a glass core of the workpiece in a wet environment and a dry environment, at cut-street locations, and perform methods for dicing the workpiece.
B23K 26/364 - Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
B23K 26/00 - Working by laser beam, e.g. welding, cutting or boring
B23K 26/14 - Working by laser beam, e.g. welding, cutting or boring using a fluid stream, e.g. a jet of gas, in conjunction with the laser beamNozzles therefor
B23K 26/146 - Working by laser beam, e.g. welding, cutting or boring using a fluid stream, e.g. a jet of gas, in conjunction with the laser beamNozzles therefor the fluid stream containing a liquid
Disclosed herein are memory cells using Gunn diodes, and related integrated circuit (IC) structures, devices, and techniques. In one aspect, a memory cell includes a first transistor, a second transistor, a first Gunn diode coupled to the first transistor, a second Gunn diode coupled to the second transistor, and a capacitor coupled between the first Gunn diode and the second Gunn diode.
H10B 10/00 - Static random access memory [SRAM] devices
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
