A Reduced-Capacity User Equipment (RedCap UE) may decode configuration information received from a gN-odeB (gNB) to configure the RedCap UE for UL sounding reference signal (UL SRS) transmission for positioning with transmit frequency hopping. The RedCap UE may determine whether to drop the UL SRS transmission based on priority rules when any one or more symbols of the UL SRS transmission would collide with an uplink channel transmission including a switching time for switching to or from an active bandwidth part. When the UL SRS transmission is determined to be dropped, the RedCap UE may drop the one or more symbols of the UL SRS transmission that would collide and may transmit any symbols of the UL SRS transmission that do not collide with the uplink channel transmission. The RedCap UE may be a half-duplex (HD) frequency division duplex (FDD) RedCap UE and may perform transmit frequency hopping over a bandwidth that is larger than a maximum bandwidth of the RedCap UE.
This disclosure describes systems, methods, and devices for adjusting encoder model and encoder output configuration. A user equipment (UE) device may select an encoder model based on the propagation condition; select an encoder output configuration based on the propagation condition; encode, using the encoder model and the encoder output configuration, CSI feedback indicative of the channel state information; and provide, the encoded CSI feedback and an assistance data that reflects the propagation condition and is used to select the encoder model and the encoder output configuration to a base station.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
3.
SINGLE TRP AND MULTIPLE TRP DYNAMIC SWITCHING FOR SINGLE DCI BASED PUSCH TRANSMISSIONS
Various embodiments herein relate to a technique to be performed by a user equipment (UE) in a cellular network. The technique may include identifying, in a downlink control information (DCI) received from a first transmission and reception point (TRP), an indication of whether the UE is to operate in accordance with a single-TRP physical uplink shared channel (PUSCH) mode or a multi-TRP PUSCH mode; identifying, based on the indication, one or more resources for PUSCH transmission; and transmitting, based on the indication and the one or more resources, a first repetition of the PUSCH transmission and a second repetition of the PUSCH transmission. Other embodiments may be described and/or claimed.
Systems, apparatus, articles of manufacture, and methods to apply load to a socketed integrated circuit package independent of a heatsink loading mechanism are disclosed. An example apparatus includes a load plate to interface with an integrated circuit package along a perimeter of the integrated circuit package while permitting a heatsink to interface with a central region of the integrated circuit package; and a torsion spring carried by the load plate. The torsion spring is on a first surface of the load plate. The integrated circuit package engages a second surface of the load plate, the second surface opposite the first surface. The torsion spring urges the load plate toward the integrated circuit package to provide a load to urge the integrated circuit package toward a socket on a circuit board.
This disclosure describes systems, methods, and devices related to enhanced protecting of block acknowledgement requests. A device may identify a protected frame received from a second device; determine, using a lower layer of a medium access control layer including the lower layer and an upper layer, that the protected frame is to be used to perform a block acknowledgement request; process, using the lower layer, the protected frame; perform, using the lower layer, a replay detection of the protected frame; update, using the lower layer, based on the protected frame, a lowest sequence number WinStartR indicative of a lowest sequence number position in a bitmap; and update, using the upper layer, a receive reordering buffer control record WinStart B.
H04W 72/0446 - Resources in time domain, e.g. slots or frames
H04W 72/20 - Control channels or signalling for resource management
6.
NATIVE SUPPORT FOR EXECUTION OF GET EXPONENT, GET MANTISSSA, AND SCALE INSTRUCTIONS WITHIN A GRAPHICS PROCESSING UNIT VIA REUSE OF FUSED MULTIPLY-ADD EXECUTION UNIT HARDWARE LOGIC
Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06T 1/20 - Processor architecturesProcessor configuration, e.g. pipelining
7.
THERMAL RELEASE LAYER FOR CARRIER ASSISTED BOTTOM-UP PLATING
Embodiments disclosed herein include an apparatus with a substrate that includes a glass layer. In an embodiment, an opening is provided through a thickness of the substrate, and the opening has a first end at a first surface of the substrate and a second end at a second surface of the substrate. In an embodiment, a layer is on a sidewall of the opening, and the layer is adjacent to the first end of the opening and extends along the sidewall of the opening a length that is less than ten percent of the thickness of the substrate. In an embodiment, the layer is electrically conductive. In an embodiment, a via is in the opening, and the via directly contacts the sidewall of the opening at a first location, and a gap is provided between the via and the sidewall of the opening at a second location.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
Gate-all-around integrated circuit structures having pre-spacer-deposition cut gates are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is over the first vertical arrangement of horizontal nanowires, and a second gate stack is over the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion providing a gate spacer along sidewalls of the first gate stack, a second portion providing a gate spacer along sidewalls of the second gate stack, and a third portion filling the gap, the third portion contiguous with the first and second portions.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Methods and apparatus relating to memory controller techniques. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, and a processor communicatively coupled to the cache memory and the high-bandwidth memory, the processor to manage data transfer between the cache memory and the high-bandwidth memory for memory access operations directed to the high-bandwidth memory. Other embodiments are also disclosed and claimed.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 7/58 - Random or pseudo-random number generators
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 12/0871 - Allocation or management of cache space
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0893 - Caches characterised by their organisation or structure
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
A neuro-symbolic kinematics system may include a neural network, a grounding module, and a kinematic calculation module. The neural network may be executed using an input to predict one or more motion parameters indicating a speculative movement of an object within the local area. The one or more motion parameters may be converted to one or more grounded motion parameters, which may be used to verify feasibility of the speculative movement. In response to determining that the speculative movement is infeasible, the system may modify one or more internal parameters of the neural network by training the neural network with the input as a training sample. The grounding module and kinematic calculation module may be differentiable to facilitate the training process. In response to determining that the speculative movement is feasible, the system may command the object to make the speculative movement based on the one or more grounded parameters.
A neural rendering system may receive an image capturing an object. The system may deploy a renderer network to generate a model representing a state of the object at a time stamp. The system may train a convolutional network by concurrently optimizing the convolutional neural network with a differentiable simulator through knowledge distillation. The system may deploy the convolutional network to generate new models representing news states of the object at different time stamps. The system may generate images from the new models. The images may show the object with the new states. The model generated by the renderer network may include particles representing features of the object. The convolutional network may predict new positions of the particles to generate the new models. A new model may be converted to a grid representation of the object, and the grid representation may be rendered to generate an image.
A pretrained neural network may be quantized using one or more sliding windows. A window may enclose a fixed number of layers. Weight tensors of the fixed number of layers over the window are quantized. The quantized layers may be optimized based on a loss indicating an error in the output of the last layer in the group due to the quantization. Each layer may be quantized in multiple stages by using another window that slides over a weight tensor of each layer in the group. In the first stage, a part of the weight tensor that is over the other window may be quantized. In the second stage, another part of the weight tensor of each layer may be quantized as the other window slides to the other part of the weight tensor. The group of layers may be optimized together in each stage.
One embodiment provides for a non-transitory machine readable medium storing instructions which, when executed by one or more processors, cause the one or more processors to perform operations comprising providing an interface to define a neural network using machine-learning domain specific terminology, wherein the interface enables selection of a neural network topology and abstracts low-level communication details of distributed training of the neural network.
Disclosed herein is a radio frequency circuit that includes a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.
For example, an Access Point (AP) may be configured to set Multi-Link Device (MLD) information to indicate that the AP is affiliated with a non-collocated AP MLD. For example, the non-collocated AP MLD may include at least one other AP which is not collocated with the AP in a same physical device. For example, the AP may be configured to transmit a frame including the MLD information. For example, a non-AP wireless communication station (STA) may be configured to receive the MLD information from the AP, and to determine, based on the MLD information, that the AP is affiliated with the non-collocated AP MLD. For example, the STA may be configured to transmit a Multi-Link (ML) probe request to the AP. For example, the ML probe request may be configured to request information corresponding to the non-collocated AP MLD.
Methods and apparatus implementing half width modes in DRAM and doubling of bank resources. DRAM devices, such as LPDDR6 SDRAM dies include multiple memory banks configured in memory groups and include I/O interface circuitry for first and second memory channels. A DRAM device may be selectively operated in a first half-width mode under which DQ lines for a partial memory channel operate as a first half-width DQ data bus. When operated in the first half-width mode, the partial memory channel is enabled to access all the memory banks on the DRAM. The DRAM device may also be selectively operated in a second half-width mode under which DQ lines for first and second partial memory channels operate as independent half-width DQ data buses. In this mode, each partial memory channel enables access to a respective portion of the memory banks.
Various embodiments herein provide techniques related to a user equipment (UE). In embodiments, the UE may identify a received transmission from a serving cell or another cell (CDP) that has a different physical cell identifier (PCI) than the serving cell. The UE may identify, based on a sharing factor related to the serving cell and a sharing factor related to the CDP, an updated sharing factor. The UE may perform, based on the updated sharing factor, a measurement related to the transmission. Other embodiments may be described and/or claimed.
Examples described herein relate to computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to: access a kernel source written in a shading language; select a compiler from a plurality of compilers based on the shading language; generate a kernel instruction set architecture and an associated runtime binding based on the kernel source and the selected compiler; and adapt state information to configure a graphics processing unit (GPU) based on the runtime binding to target any API runtime of choice.
Various examples relate to apparatuses, devices, methods and computer programs for an edge worker node and an edge server, to an edge worker node and an edge server, and to a system comprising an edge server and one or more edge worker nodes. An apparatus comprises processing circuitry to determine information on a network quality of a network connection between the edge worker node and an edge server, select, based on the network quality, a network configuration, the network configuration comprising at least one of a network protocol and a prioritization strategy for communicating via the network connection, and to communicate via the network connection according to the selected network configuration.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
H04L 47/24 - Traffic characterised by specific attributes, e.g. priority or QoS
20.
SUPPORTING 8-BIT FLOATING POINT FORMAT OPERANDS IN A COMPUTING ARCHITECTURE
An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
Techniques related to a method and system of audio false keyphrase rejection using speaker recognition are described herein. Such techniques use speaker recognition of a computer originated voice to omit actions triggered when a keyphrase is present in captured audio and omitted when speech of the captured audio was spoken by the computer originated voice.
Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a first memory, a first memory side cache memory, a first communication fabric, and a first memory management unit (MMU). The graphics processor includes a second graphics processing unit (GPU) having a second memory, a second memory side cache memory, a second memory management unit (MMU), and a second communication fabric that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
G06F 7/575 - Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry
G06F 7/58 - Random or pseudo-random number generators
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
G06F 12/0811 - Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
G06F 12/0866 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
G06F 12/0871 - Allocation or management of cache space
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 12/0888 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
G06F 12/0893 - Caches characterised by their organisation or structure
G06F 12/0895 - Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
G06F 12/0897 - Caches characterised by their organisation or structure with two or more cache hierarchy levels
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/128 - Replacement control using replacement algorithms adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
H03M 7/46 - Conversion to or from run-length codes, i.e. by representing the number of consecutive digits, or groups of digits, of the same kind by a code word and a digit indicative of that kind
An example system disclosed herein performs frame resolution scaling and region selective blurring in a single hardware filtering pass. A source image frame in RGBA format is supplied to the system. The alpha (A) channel of the RGBA format encodes a segmentation mask that distinguishes sharp and blur regions. For a given output pixel, the system evaluates the alpha values of the contributing source pixels, calculates a coverage metric, and classifies the output pixel as sharp, blurred, or transitional. Based on the classification, the system selects a corresponding filter coefficient set—sharp, hybrid blur, or hybrid transition—from memory. The selected coefficients drive a polyphase finite impulse response filter that simultaneously resamples and applies the appropriate blurring. The result is a scaled output frame that preserves detail in selected regions while blurring others without requiring separate filtering passes.
G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
24.
SPACER SELF-ALIGNED VIA STRUCTURES USING ASSISTED GRATING FOR GATE CONTACT OR TRENCH CONTACT
Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A corresponding one of a plurality of dielectric spacers is between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. The plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures. The conductive structure has a flat edge along a direction across the one of the plurality of gate structures or the one of the plurality of conductive trench contact structures.
A pretrained neural network may be fine-tuned using one or more elastic adapters, each of which may be inserted into the pretrained neural network at a position that is immediately after a corresponding layer of the pretrained neural network. An elastic adapter may include a first linear layer and a second linear layer. During the fine-tuning, one or more internal parameters (e.g., weights) of the elastic adapter may be updated based on a loss function, while internal parameters of the corresponding layer (e.g., pretrained weights) may be fixed. After the fine-tuning, the first linear layer may be merged with the corresponding layer to form a new layer. The new layer may replace the corresponding layer in the neural network. The updated neural network, which has the new layer and the second linear layer, may be a fine-tuned neural network and may be used to perform one or more AI tasks.
A computer vision system may receive or generate a graph sequence of an object. The graph sequence includes graphs corresponding to different times stamps. A graph includes nodes and edges connecting the nodes. The system may interpolate extra nodes among adjacent nodes in space and time at multiple orders to enrich the expressiveness of the graph sequence and encode the interpolated graph-structured sequence into a grid-patch representation of the object. For instance, the system may perform spatial interpolation and temporal interpolation on the graph sequence through linear transformations to generate an interpolated graph sequence. The system may assign nodes of the interpolated graph sequence to cells of a grid patch to generate a grid representation of the object. A convolution may be operated upon the grid to predict an action of the object.
Embodiments disclosed herein may include an apparatus with a substrate. In an embodiment, an opening is formed through the substrate. In an embodiment, a layer is provided over a sidewall of the opening, and the layer comprises a first magnetic material, and a plug is in the opening. In an embodiment, the plug comprises a second magnetic material that is different than the first magnetic material. In an embodiment, a first via is through the plug, and a second via may be formed through the plug.
Some aspects of the present disclosure relate to a non-transitory computer-readable medium storing instructions that, when executed by one or more processing circuitries, cause the one or more processing circuitries to perform a method for a computer system, the method comprising obtaining (110) a set of data, determining (120) at least one semantic descriptor characterizing a current state of the set of data, determining (130) whether the set of data is associated with a data structure comprising at least one semantic descriptor characterizing a previous state of the set of data, in response to a negative determination, creating (150) a new data structure comprising the determined at least one semantic descriptor characterizing the current state of the set of data, in response to a positive determination, computing (160) a combination of (i) a decayed version of the at least one semantic descriptor characterizing the previous state of the set of data and (ii) the at least one semantic descriptor characterizing the current state of the set of data, and updating (165) the data structure based on the combination.
Prefetch aware LRU cache replacement policy is described. An example of an apparatus includes one or more processors including a graphic processor, the graphics processor including a load store cache having multiple cache lines (CLs), each including bits for a cache line level (CL level) and one or more sectors for data storage; wherein the graphics processor is to receive one or more data elements for storage in the cache; set a CL level to track each CL receiving data, including setting CL level 1 for a CL receiving data in response to a miss in the cache and setting a CL level 2 for a CL receiving prefetched data in response to a prefetch request, and, upon determining that space is required in the cache to store data, apply a cache replacement policy, the policy being based at least in part on set CL levels for the CLs.
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
30.
OPTIMIZING LOW PRECISION INFERENCE MODELS FOR DEPLOYMENT OF DEEP NEURAL NETWORKS
Systems, apparatuses and methods may provide technology for optimizing an inference neural network model that performs asymmetric quantization by generating a quantized neural network, wherein model weights of the neural network are quantized as signed integer values, and wherein an input layer of the neural network is configured to quantize input values as unsigned integer values, generating a weights accumulation table based on the quantized model weights and a kernel size for the neural network, and generating an output restoration function for an output layer of the neural network based on the weights accumulation table and the kernel size. The technology may also perform per-input channel quantization. The technology may also perform mixed-precision auto-tuning.
Methods, apparatus, systems, and articles of manufacture are disclosed to control transactional data. An example apparatus disclosed herein includes memory, machine readable instructions, and processor circuitry to at least one of instantiate or execute the machine readable instructions to populate encrypted input data into a first portion of a data structure, populate an encryption key into a second portion of the data structure, cause the first portion of the data structure to be signed with (a) credentials corresponding to an owner of the encrypted data and (b) credentials corresponding to a transaction host, and store the data structure in a ledger.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.
Systems and methods are provided for harmonizing a foreground region with a background image during background replacement and content editing. A sensor image including a foreground region and a background region is received at an image signal processor (ISP), along with a background image having different visual characteristics. The sensor image and the background image are downscaled and processed by a harmonization neural network that predicts one or more ISP hardware block parameters. The predicted parameters are used to configure ISP hardware blocks such that the foreground region of a processed image is harmonized to match visual characteristics of the background image while preserving full sensor bit depth. The processed image is then blended with the background image to generate a harmonized output image. By performing harmonization within the ISP pipeline using low-resolution inference, the techniques reduce computational overhead and avoid quantization artifacts associated with post-processing approaches.
Integrated circuit structures having pre-epitaxial deep via structures, and methods of fabricating integrated circuit structures having pre-epitaxial deep via structures, are described. For example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate structure is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive trench contact structure is vertically over the epitaxial source or drain structure. A conductive via is vertically beneath and extends to the conductive trench contact structure. The conductive via has an uppermost surface above an uppermost surface of the epitaxial source or drain structure.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Logic may support full power operation for uplink transmissions of user equipment. Logic may identify a codebook entry with a precoding matrix for full power mode operation for an uplink communication for a set of non-coherent or partial coherent antenna ports. Logic may generate the uplink communication, generation to comprise precoding one or more data streams of the uplink communication based on the precoding matrix to associate the data streams with the set of non-coherent or partial coherent antenna ports. And logic may cause transmission of the uplink communication via the interface between processing circuitry and radio frequency circuitry.
H04W 52/14 - Separate analysis of uplink or downlink
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
36.
APPARATUS, SYSTEM AND METHOD FOR DYNAMIC MODIFICATION OF A GRAPHICAL USER INTERFACE
Methods, apparatus, systems are disclosed for altering displayed content on a display device responsive to a user's proximity. In accord with an example, a computing system includes a display, a sensor to output a signal, machine readable instructions, and programmable circuitry to be programmed in accordance with the instructions to determine a distance between the compute system and a person based on the signal, and cause a size of at least one object to be presented on the display to be adjusted based on the distance.
G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer
G06F 3/03 - Arrangements for converting the position or the displacement of a member into a coded form
G06F 3/04845 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range for image manipulation, e.g. dragging, rotation, expansion or change of colour
G06F 40/103 - Formatting, i.e. changing of presentation of documents
G06T 3/40 - Scaling of whole images or parts thereof, e.g. expanding or contracting
G06V 40/10 - Human or animal bodies, e.g. vehicle occupants or pedestriansBody parts, e.g. hands
G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions
G09G 5/00 - Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.
One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.
Disclosed examples include video frame segmenter circuitry to generate segmentation data of first video frame pixel data, the segmentation data including metadata corresponding to a foreground region and a background region, the foreground region corresponding to the first video frame pixel data. The disclosed examples also include video encoder circuitry to generate a first foreground bounding region and a first background bounding region based on the segmentation data, determine a first virtual tile of the first video frame pixel data, the first virtual tile located in the first foreground bounding region, encode the first virtual tile into a video data bitstream without encoding the first background bounding region, and transmit the video data bitstream via a network.
H04L 65/403 - Arrangements for multi-party communication, e.g. for conferences
H04N 19/70 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
40.
Systems and Methods for Java Virtual Machine Management
A virtual machine (VM) management utility tool may deploy an object model that may persist one or more virtual machine dependencies and relationships. Through a web front-end interface, for example, the VMs may be started in a specific order or re-booted, and the tool automatically determines the additional VMs that need to be re-booted in order to maintain the integrity of the environment. Through the web interface, for example, the object model may be managed and start-up orders or VM dependencies may be updated. For VMs that may not start under load, the object model may block access to the VM until the VM is fully initialized.
An apparatus to facilitate graphics rendering is disclosed. The apparatus comprises tiling hardware to perform tile based rendering of objects, including receiving a workload comprising a plurality of objects, performing batch formation to generate one or more batches of the plurality of objects, performing super tile fill sequencing for to determine one or more super tiles that are intersected by objects in each batch and compute tile fill intersects for each of the objects and performing a play sequencing of each of the objects, wherein each super tile comprises a plurality of tiles.
Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing double liner materials. In some embodiments, a microelectronic assembly may include a glass layer having a first surface and an opposing second surface; a via extending through the glass layer between the first and second surfaces, the via including a conductive material; a first liner, on a sidewall of the glass layer in the via, including a first inorganic material having a first Young's modulus; and a second liner, between the first liner and the conductive material of the via, including a second inorganic material having a second Young's modulus that is less than the first Young's modulus. In some embodiments, the first Young's modulus is between 25 Gigapascal (GPa) and 50 GPa, and the second Young's modulus is between 1 GPa and less than 25 GPa.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
43.
DOUBLE-SIDED BOTTOM-UP PLATING OF THROUGH GLASS VIAS USING A PEELABLE CORE
Double-sided bottom-up plating of through glass vias, and related packages, apparatuses, and systems are discussed. Glass substrates for use in an integrated circuit package each have a first surface, an opposing second surface, and an opening extending between the first and second surfaces. A polymeric material is formed over the first surface and covering the opening, and the polymeric material is then collapsed to expose the opening while providing an adhesive material over the first surface. Two glass substrates are attached to a metal cladding of a peelable core using the adhesive material, and the openings are filled with metal using simultaneous bottom-up plating from the metal cladding. A peelable layer of the peelable core is then exposed and the glass substrates are removed from the peelable core and deployed in the package.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Through glass via structures including via metallizations and gaps between the via metallizations and sidewalls of openings in the glass substrate, and related packages, apparatuses, and systems are discussed. Glass substrates for use in an integrated circuit package have a first surface, an opposing second surface, and an opening extending between the first and second surfaces. A sacrificial material is coated on a sidewall of the opening and a via metallization is formed within the sacrificial material. The sacrificial material is removed, leaving one or more gaps between the via metallization and the sidewall of the opening to at least partially decouple the via metallization and the glass substrate.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Bridge die interposer packages, and related apparatuses, systems, and techniques are discussed. An interposer package includes a bridge die having a routing structure to interconnect multiple integrated circuit (IC) dies of the package. Power is provided to the IC dies by a mesh power supply metallization and a mesh ground metallization that extend from outside a perimeter of the bridge die to within the perimeter and over the routing structure. The bridge die may be absent through silicon vias (TSVs) and may be hanging such that it is exposed at the bottom of the package.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
Embodiments disclosed herein include an apparatus with a substrate that comprises a glass layer. In an embodiment, a via is provided through a thickness of the substrate, and the via has a first aspect ratio. In an embodiment, the via directly contacts the substrate. In an embodiment, a layer is around an end of the via, and the layer extends down a partial length of a sidewall of the via. In an embodiment, a cavity is provided through the thickness of the substrate, and the cavity has a second aspect ratio that is smaller than the first aspect ratio. In an embodiment, a component is in the cavity, and a fill layer is around the component in the cavity.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Methods, apparatus, systems, and articles of manufacture are disclosed to control autofocus of an image capture device. An example method includes obtaining face information including a current face region from a face detection library, calculating a region difference metric between the current face region and a reference face region, extracting statistics of the current face region, controlling at least one of a scene change judgement or a dead zone to determine whether to trigger autofocus iterations, performing an autofocus iteration with lens movement controlled based on the region difference metric; and saving an in-focus face region resulting from the autofocus iteration as the reference face region.
For example, an Access Point (AP) may be configured to set a multi-AP parameter field in a Target Wake Time (TWT) parameter set field to configure multi-AP operation. For example, the multi-AP parameter field may include information to configure the multi-AP operation during a TWT Service Period (SP). For example, the AP may be configured to transmit a TWT element. For example, the TWT element may include the TWT parameter set field. For example, a wireless communication station (STA) may be configured to receive the TWT element from the AP, and to identify the multi-AP parameter field in the TWT element. For example, the STA may be configured to communicate one or more transmissions during the TWT SP based on the multi-AP parameter field.
H04W 74/0816 - Non-scheduled access, e.g. ALOHA using carrier sensing, e.g. carrier sense multiple access [CSMA] with collision avoidance
H04W 52/36 - Transmission power control [TPC] using constraints in the total amount of available transmission power with a discrete range or set of values, e.g. step size, ramping or offsets
H04W 74/0833 - Random access procedures, e.g. with 4-step access
Examples described herein relate to a network interface device comprising dataplane circuitry, when operational, is to generate a representation of aggregated network resource consumption information based on network resource consumption at the network interface device or at least one other network device and to transmit at least one packet with a multi-bit representation of the aggregated network resource consumption information to a second network interface device. In some examples, the network resource consumption information comprises one or more of: available transmit bandwidth, transmit bandwidth used by a queue or flow, queue depth, measured queueing time duration, expected queueing time duration, packet latency, or normalized in-flight bytes.
H04L 43/067 - Generation of reports using time frame reporting
H04L 47/762 - Admission controlResource allocation using dynamic resource allocation, e.g. in-call renegotiation requested by the user or requested by the network in response to changing network conditions triggered by the network
An adaptive quantization system and method for efficient storage and processing of matrix data is disclosed. The system comprises a processor with circuitry configured to divide a matrix into blocks, assign quantization formats to each block based on content, generate a super-block comprising quantized blocks and associated format information, and store the super-block in memory. The method employs an index to indicate quantization formats, typically using 3 bits per block, and can utilize shared exponents for certain formats. A metadata buffer stores compression information, allowing gradual adoption of compression. The invention optimizes matrix data storage at a fine-grained level, maintains efficient random access, adapts to varying precision requirements within a matrix, and integrates with existing memory hierarchies. This approach significantly improves compression efficiency and processing speed for large-scale matrix operations in fields such as artificial intelligence, machine learning, and high-performance computing.
A processor comprises a memory to store numeric data in bit plane format and circuitry coupled to the memory to perform matrix operations on the stored data using adders. The bit plane format allows dynamic variations in bit sizes of values. A system includes a memory to store numeric data in bit plane format, a processor coupled to the memory, and a matrix multiplication module to perform matrix multiplication using adders. A method involves storing numeric data in bit plane format, retrieving the stored data, and performing matrix operations using adders. The processor, system, and method enable faster processing and reduced memory consumption compared to consecutive aligned bit sequences.
A system and method for synchronizing multiple graphics processing units (GPUs) connected via an interconnect link. The system implements a synchronization protocol on top of memory semantics provided by the interconnect link. Each GPU maps memory apertures for other GPUs. The protocol executes a broadcast into all aperture ranges from one GPU with appropriate memory semantics and synchronizes other GPUs by waiting for the memory write to become visible. A command processor performs synchronization logic for each GPU. The method establishes communication between GPUs, implements the protocol, maps memory apertures, and executes the synchronization process. This approach leverages existing infrastructure for efficient, decentralized multi-GPU synchronization using N messages for N GPUs.
A processing system for distributing work in a computing environment arranges nodes in a network topology. Each node comprises upstream and downstream ports for receiving and sending packets, and ingress or egress ports for accepting new entries or forwarding packets to functional units. Nodes evaluate received packets for local processing, removing them for processing or forwarding to the next node. The system implements flow control at ingress ports, arbitrates between multiple ingress ports when the upstream port is idle, and distributes work locally to connected egress ports. Packets are inspected to determine suitability for processing by connected functional units. This efficient system enables flexible work distribution strategies in homogeneous and heterogeneous networks, reducing the need for repeaters and long wires on integrated circuits.
A processor executes an instruction to perform a comparison between a source value and a value stored in memory at a specified address. If the comparison passes, the processor writes the source value to memory at the specified address and writes a payload to a payload destination address in an atomic operation. The instruction includes an opcode indicating the comparison and fields specifying the source value, addresses, and payload. The payload may have arbitrary length. A Test-And-Update (TAU) operation associates the payload with the atomic operation while maintaining native bit-width for the comparison. This enables efficient handling of larger payloads without compromising performance of existing comparison logic, providing enhanced functionality for graphics and general-purpose computing applications.
A processor executes instructions for dynamic construction of opacity micro-maps (OMMs) in runtime. The processor initializes OMM bits to indicate ambiguous opacity, executes a shader when a triangle is first intersected, determines sub-triangle opacity based on shader execution, updates the OMM with opacity information, and uses the updated OMM for subsequent ray intersections. Two modes are supported: explicit mode using an API for application-defined opacity decisions, and implicit mode for compiler-based opacity analysis. The processor may cache shader results, select subdivision levels based on triangle size, and suppress or trigger shader invocations for subsequent intersections. This approach enables efficient, dynamic OMM generation and improves ray tracing performance.
Embodiments described herein provide techniques to enable an accelerator device to support a variable number of registers per-thread, where program code is associated with a register configuration selected from a plurality of register configurations, and the variable register configuration for a thread is configurable to make use of physically non-contiguous blocks of registers within a register file. The accelerator device includes circuitry to map physically non-contiguous blocks of registers into a virtual register space in which registers assigned to a thread appear contiguous to program code executed via the thread.
Implementing video manipulation that can deliver professional-quality results while maintaining real-time performance is not trivial. To address this technical challenge, a dual parallel path processing system can be implemented. In a pipeline parallel to a main image processing pipeline, low-resolution images of a video can be processed, such as by a neural network, to generate gain maps that specify spatially-varying corrections for a variety of applications such as face relighting, content emphasis/de-emphasis, graphics overlay effects, and scene tone-mapping. These gain maps are upscaled through existing image processing unit hardware, and applied on or to the full-resolution, high bit-depth images. This approach achieves superior image quality with minimal computational overhead, little to no degradation to processing latency, and minimal additional power consumption.
Embodiments disclosed herein include a package core. In an embodiment, the package core includes a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises glass. In an embodiment, a third layer is over the second layer, where the third layer comprises glass. In an embodiment, a first trace is between the first layer and the second layer. In an embodiment, a second trace is between the second layer and the third layer.
Systems, apparatus, articles of manufacture, and methods to implement attention-based noise seed selection for video diffusion models are disclosed. An example system selects an initial noise seed for a trained video diffusion model using attention data generated by the model. In some examples, the system generates multiple candidate noise seeds, runs the video diffusion model for a small number of iterations with each candidate, and extracts attention maps from one or more attention layers of the model. For each candidate seed, the system computes a similarity or difference score between the candidate's attention map(s) and those of the other candidates. The seed having the most consistent attention pattern is selected and then used to drive the remaining diffusion iterations to produce a synthetic video. The approach involves no model retraining, incurs low computational overhead, and can display interpretable attention heat maps for user inspection.
A processor includes a first model specific register (MSR); and memory encryption circuitry to receive a request to access a memory, determine if a key identifier (ID) of the request is zero, and if the key ID is zero, to bypass data encryption when the request is to write data to the memory and to bypass memory decryption when the request is to read data from the memory and when a selected bit of the first MSR is set, and if the selected bit of the first MSR is not set, to encrypt write data when the request is to write data or decrypt data in a read response when the request is to read data, with a key associated with the key ID equal to zero.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
61.
COVERAGE ENHANCEMENT FOR PHYSICAL DOWNLINK CONTROL CHANNEL WITH COMMON SEARCH SPACE
This disclosure describes systems, methods, and devices related to enhanced coverage optimization. A device may decode an indication in a master information block (MIB) that specifies whether repetition is applied for a Type 0 physical downlink control channel (PDCCH) common search space (CSS). The device may monitor PDCCH repetitions for the Type 0 PDCCH CSS during two PDCCH monitoring occasions associated with a same synchronization signal block (SSB) index. The device may select, using a spare bit in the MIB, a configuration that applies the PDCCH repetitions for the Type 0 PDCCH CSS.
Methods, apparatus, systems, and articles of manufacture are disclosed. An example apparatus includes: at least one memory; machine readable instructions; and processor circuitry to execute the machine readable instructions to: generate macroblocks from an image frame, the macroblocks to meet at a convergence point; assign compute units to the macroblocks to process pixels of the macroblocks in parallel; perform a convergent sweep of the macroblocks with the compute units, the convergent sweep to process pixels of the macroblocks starting at corners opposite the convergence point and ending at the convergence point; and perform a divergent sweep of the macroblocks with the compute units, the divergent sweep to process the pixels of the macroblocks starting from the convergence point and ending at the corners opposite the convergence point.
G06V 10/50 - Extraction of image or video features by performing operations within image blocksExtraction of image or video features by using histograms, e.g. histogram of oriented gradients [HoG]Extraction of image or video features by summing image-intensity valuesProjection analysis
G06V 10/26 - Segmentation of patterns in the image fieldCutting or merging of image elements to establish the pattern region, e.g. clustering-based techniquesDetection of occlusion
63.
HETEROGENOUS GLASS CORE VIAS FOR INTEGRATED SEMICONDUCTOR PACKAGES
Heterogenous through glass vias, and related packages, apparatuses, systems, and methods of fabrication are discussed. A glass substrate of a package has a first surface, an opposing second surface, and any number of first and second holes extending at partially between the first and second surfaces. Via metallizations within the first holes are heterogenous with respect to via metallizations within the second holes such that they have different lateral widths, lateral shapes, tapers, or any combination thereof.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
Embodiments disclosed herein may include an apparatus with a substrate that includes a hole through a thickness of the substrate. In an embodiment, the substrate comprises a glass layer, and the hole has a first width. In an embodiment, the apparatus includes a buffer layer on the substrate, and an opening passes through the buffer layer. In an embodiment, the opening is over the hole. In an embodiment, the opening has a second width that is smaller than the first width. In an embodiment, the apparatus further includes a via in the hole and the opening.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
In an embodiment, a processor includes a plurality of cores and control circuitry. The control circuitry is to: detect a selection of a deep sleep mode to be entered by a first core of the processor; in response to the detection of the selection of the deep sleep mode, determine whether a total number of cores in a shallow sleep state is less than a minimum level of a shallow sleep group of the processor; and in response to a determination that the total number of cores in the shallow sleep state is less than the minimum level of the shallow sleep group, cause the first core to enter the shallow sleep mode instead of the selected deep sleep mode. Other embodiments are described and claimed.
The application relates to Machine Learning (ML) model sharing between Network Data Analytics Functions (NWDAFs) in a wireless communication system. An apparatus used in a NWDAF entity containing Model Training Logical Function (MTLF), wherein the apparatus includes processor circuitry configured to cause the NWDAF entity containing MTLF to: receive, from another NWDAF entity containing Analytics Logical Function (AnLF) or MTLF, an ML model provision request, which comprises an access token to the NWDAF entity containing MTLF and an analytics identifier or a Machine Learning (ML) model identifier associated with an ML model file; and send, to the another NWDAF entity containing AnLF or MTLF, an ML model provision response, which comprises the analytics identifier or the ML model identifier associated with the ML model file and a container containing the ML model file or a network address associated with the ML model file.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
A processor is provided configured to traverse rays through a BVH tree; record trails of successful ray-primitive intersections from hit primitives to a root node of the BVH tree; update node visit counters, wherein the node visit counters correspond to the number of times a child node was taken on the path to the root node, based on the recorded trails; determine a traversal order for child nodes of a current node based on the node visit counters; and traverse the child nodes according to the determined traversal order.
A processor receives neural network weights and programs a lookup table based on those weights to process neural network operations. The lookup table transforms input values with a smaller bit count to output values with a larger bit count, allowing flexible distribution of accuracy. For example, 4-bit inputs can be translated to 8-bit outputs using a 16-entry lookup table. The lookup table can also replace mathematical operations like multiplication and addition. A 4-bit by 4-bit multiplication can be implemented with a 256-entry lookup table having 8 or more output bits, providing flexibility in numeric formats. This approach enables efficient processing of neural networks with programmable lookup tables that transform small bit count weights to larger internal representations.
A processor is provided to perform a raytracing process, wherein the raytracing process includes: determining a bounding volume hierarchy (BVH) structure with leaf nodes; storing a plurality of triangles as meshlets in leaf nodes; obtaining a ray tracing acceleration data structure (RTAS) comprising BVH leaf nodes and triangles; transforming vertices of the triangles into a unit ray coordinate space; perform a culling procedure on the transformed triangles; and intersect remaining triangles with a ray in the unit ray space.
A processor performs matrix multiplication operations using low bit fixed point formats. The processor encodes matrix weights to 1-bit or 2-bit formats, performs matrix multiplications using the encoded weights, and accumulates results. Supported formats include symmetric binary (1-bit, −1/+1), asymmetric binary (1-bit, 0/+1), ternary (2-bit, −1/0/+1), and quaternary (2-bit, −2/−1/+1/+2). Multiplication uses XNOR, AND, or 2-bit multiplier operations. Accumulation uses higher precision, with results rounded to the low-bit format. This enables efficient neural network inference with 2-4× performance gain over 4-bit formats.
A processor for raytracing is provided, the processor being configured to: generate a bounding volume hierarchy, quantize at least one bounding box associated with the bounding volume hierarchy, dynamically allocate a number of quantization bits for at least one of x, y, and z dimensions of the at least one bounding box, wherein a variable number of quantization bits per dimension is used in the quantization.
A system and method for updating a bounding volume hierarchy (BVH) comprises a processor, memory, BVH update module, and feedback path. The feedback path returns a BVH quality estimate during the update, enabling estimation of box overlap to determine tree degradation. The system stores one value per BVH node describing original overlap volume of children, tracks this value as the tree deforms, and sends a rebuild indication when a threshold is reached. It can store a child-child overlap matrix and gather information on preferred axis swap, aspect ratio changes, and active triangles. The feedback path provides information to avoid rebuilding undegraded tree parts. This system offers an efficient approach for deciding between BVH rebuilding or refitting
A computing system and method generate bounding boxes for objects in a three-dimensional scene. A grid generator creates a 3D grid, and a histogram generator builds a histogram of primitive intersections with grid cells. A neural network receives the histogram as input and generates bounding boxes around objects. A box optimizer minimizes the sum of surface areas of the bounding boxes. The histogram can be compressed, using a single bit per bin to indicate primitive presence. Primitives are assigned to child nodes based on proximity or fit. The system provides efficient and optimized bounding box generation for computer graphics applications.
A graphics processor accelerates rasterization using a bounding volume hierarchy (BVH) traversal unit. The unit performs intersection tests between BVH nodes and a view frustum, identifies visible nodes, and sends geometry content of visible leaf nodes to a rasterizer. Nodes are transformed into view space and clipped against the frustum. Non-intersecting nodes are discarded while traversal continues for intersecting nodes. Fully contained nodes bypass clipping. Visible leaf nodes are sorted for optimized depth testing. Non-overlapping nodes enable parallel rendering. The view frustum is subdivided into screen-aligned regions for dedicated rasterization. This approach enhances performance through efficient visibility determination and parallelism.
A processor for ray tracing is provided. The processor is configured to provide an acceleration structure including at least one junction node, obtain rays with associated detail base and detail attenuation parameters, and traverse the acceleration structure using the generated rays, wherein the junction node comprises: a junction factor, a pointer to a low level of detail acceleration structure, and a pointer to a high level of detail acceleration structure. The processor is configured to determine a junction entrance value based on the detail base parameter, the detail attenuation parameter, and a distance value, and to compare the junction entrance value to the junction factor to determine which level of detail acceleration structure to traverse.
A graphics processing system and method for ray tracing traversal in a hierarchical acceleration structure utilizes a memory and processor. The processor evaluates nodes and ray intersections with child node bounding volumes, marks nodes for reevaluation, and stores thresholds related to child node intersections. The system returns to marked nodes when current node intersections exceed thresholds. Nodes are marked using one bit in the internal structure and stored as stack offsets. Thresholds are calculated using near and far intersection points. Child nodes exceeding thresholds are placed on a stack before returning to marked nodes. This approach enables efficient traversal path selection, reducing unnecessary checks and improving ray tracing performance in complex scenes.
A processing system comprises a memory and a processor configured to store multiple data elements of non-power-of-two bit width across plural registers with power-of-two bit width. The processor stores each bit of the data elements in separate registers, with the first bit in a first register, second bit in a second register, and so on. Arithmetic operations are performed on corresponding bits across registers. The number of data elements equals the register bit width. An arithmetic logic unit concurrently operates on the data elements using bits stored across registers. The system enables efficient storage and processing of low-precision values, optimizing cache usage and reducing wasted bits. This novel approach improves performance for applications like artificial intelligence using narrow data types.
An electronic package technology is disclosed. A first active die can be mountable to and electrically coupleable to a package substrate. A second active die can be disposed on a top side of the first active die, the second active die being electrically coupleable to one or both of the first active die and the package substrate. At least one open space can be available on the top side of the first active die. At least a portion of a stiffener can substantially fill the at least one open space available on the top side of the first active die.
Systems and methods are provided for reducing loudspeaker-to-microphone leakage in audio-enabled computing platforms. The invention provides a neural network-based Loudspeaker Leakage Silencer (LLS) module, integrated within an audio processing pipeline, that processes both microphone and loopback (reference) signals to suppress non-linear echo components resulting from device playback. The LLS module uses a light RNN-Mixer architecture configured to generate an attenuation mask, which is applied to the microphone features to achieve at least a 9 dB reduction in loudspeaker leakage. The system supports both standalone operation, wherein the LLS processes raw microphone streams, and cascade operation, wherein the LLS operates in conjunction with traditional acoustic echo cancellation (AEC) modules. The neural network model is trained using augmented audio data to ensure robust performance under diverse operating conditions. The techniques provide significant improvements in audio quality, enabling superior voice communication experiences and enhanced echo suppression capabilities for computing devices.
Vertical die to die (D2D) interconnected chiplets on a glass core. The chiplets are two different integrated circuit dies, often considered “hot” dies, and called top dies herein. The glass core includes a cavity. An active I/O die is in the cavity to provide the D2D communication, its top surface flush with the upper surface of the glass core. Two different sized micro-bumps are used, the first micro-bumps have a smaller pitch (e.g., “fine pitch”) and are to attach the top dies to the top surface. The second micro-bumps are larger than the first (e.g., “coarse pitch”), and are to attach the top dies to the upper surface of the glass core. An organic build, and solder ball backside may be fabricated on the lower surface of the glass core.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT PLACEHOLDER CUT WITH DIRECT PATTERNED TRENCH CONTACT AND NON-SELECTIVE FIN TRIM ISOLATION
Integrated circuit structures having uniform grid metal gate and trench contact placeholder cut and non-selective fin trim isolation (FTI) are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires or a fin. A gate structure is over the vertical stack of horizontal nanowires or the fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure. A dielectric gate cut plug is laterally between and in contact with the gate structure and the dielectric structure. The dielectric structure has an uppermost surface above an uppermost surface of the dielectric gate cut plug.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
82.
ULTRA HIGH BANDWIDTH MEMORY WITH BACKEND TRANSISTORS
Embodiments disclosed herein include ultra high bandwidth memory (HBM) with backend transistors. In an example, a memory structure includes a package substrate. A base die is coupled to the package substrate and a memory die stack is coupled to the base die, or a memory die stack is coupled to the package substrate. Each memory die in the die stack includes one transistor one capacitor (1T1C) backend dynamic random access memory (DRAM).
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/66 - Testing or measuring during manufacture or treatment
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
83.
EXTRACTION OF BANDWIDTH WITH MULTIPLE CHANNELS IN HIGH BANDWIDTH AND HIGH CAPACITY MEMORIES
Embodiments disclosed herein include arrangements enabling extraction of bandwidth with multiple channels. In an example, a memory structure includes a package substrate. A base die is coupled to the package substrate and a memory die stack is coupled to the base die, or a memory die stack is coupled to the package substrate. A same number of through silicon vias span all memory dies in the die stack.
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
84.
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CHANNEL STRUCTURES AND ISOLATION STRUCTURES
Gate-all-around integrated circuit structures having depopulated channel structures and isolation structures are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires, the first vertical arrangement of nanowires having a dielectric structure or a conductive via in place of one or more of the nanowires, the dielectric structure having a dielectric liner and a dielectric fill. A first gate stack is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is laterally spaced apart from the first vertical arrangement of nanowires, the second vertical arrangement of nanowires having nanowires horizontally corresponding to the nanowires and the conductive via of the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
An apparatus and method for ring interconnect bandwidth scaling. In some embodiments, interfaces of first and second ring interconnects couple a plurality of cores and a plurality of cache slices. The ring interconnects provide packet-based communication in a first direction and a second direction and the interfaces include egress buffers to queue packets waiting to be transmitted over the first ring interconnect and the second ring interconnect. The plurality of interfaces are controlled to route packets between the cores and the cache slices in accordance with one of a plurality of modes, including a shortest path mode and a dynamic routing mode to be entered when the detected packet occupancy of at least one egress buffer reaches a first defined threshold.
A system for solder processing a semiconductor device can be performed with LAR (laser assisted reflow) with a low temperature matrix tray. The system includes a tray shield to shield the matrix tray from excessive heat exposure during solder reflow. The shielding prevents heat exposure past the point of warpage during reflow due to heat exposure from laser light. The LAR has a laser source that provides collimated laser light to induce solder reflow in the target semiconductor device.
Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having a stack of nanowires (i.e., semiconductor structures) contacted by epitaxial source and drain structures at opposite ends of the nanowires. The transistors include a gate structure vertically between the nanowires. Spacer structures of silicon germanium oxide separate the ends of the nanowires spacer and separate the source and drains structures from the gate structure.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
88.
SELECTIVE AREA TEMPLATE FOR TWO-DIMENSIONAL EPITAXIAL CHANNEL GROWTH ON LARGE WAFERS WITH FUNCTIONALIZED PATTERNED AREAS
Integrated circuit (IC) devices having transistors with two-dimensional channel layers, such as TMD (transition metal dichalcogenide) nanoribbon channels in gate-all-around (GAA) FETs (field-effect transistors). An IC device may include a stack of nanoribbon channel layers through a gate structure having interface layers between the channel layers and the gate dielectric layers. The interface layers may include an element not present in the gate dielectric layers or the channel layers. A channel layer may be on an underlying interface layer, between the channel layer and the underlying gate dielectric layer, but the gate dielectric layer over the channel layer may be directly on the channel layer. The material stack of gate and channel material layers may be over an electrically insulating layer that serves as an epitaxial growth template for the subsequently formed crystalline layers. A sacrificial mask layer may confine epitaxial growth to single-nucleation areas.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
89.
AREA SELECTIVE DEPOSITION OF EPI ISOLATION ENABLING FIN PITCH SCALING
Integrated circuit (IC) devices having dielectric material separating adjacent source and drain bodies. An IC device may include adjacent first and second transistor structures having adjacent source or drain bodies separated by a dielectric material on first and second sidewalls of a first of the source or drain bodies (but only on the sidewall of the second source or drain body adjacent the first source or drain body). An isolation structure of a second dielectric material may be on the first dielectric material, on the first and second source or drain bodies, and between first and second contact structures on the first and second source or drain bodies. The dielectric material on first and second sidewalls of the first source or drain body may be selectively deposited (e.g., conformally) before the second source or drain body is grown.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
An apparatus and method for predicting I/O device interrupt frequency. For example, one embodiment of a method comprises: storing metrics related to interrupts associated with an input-output (IO) device coupled to compute circuitry; evaluating the metrics to identify periodic interrupts; generating a time for a predicted next interrupt for each periodic interrupt; and initiate waking the compute circuitry from a low power state prior to the time for the predicted next interrupt to allow the compute circuitry to be in an active state when the predicted next interrupt is received.
Integrated circuit (IC) devices having transition regions between logic and memory regions. An IC device may include interconnect lines through a dielectric material in interconnect layers over a device layer, a stack of memory cells over the device layer and laterally adjacent the interconnect layers, a conductor extending vertically through the memory cells, a distance shorter than a height of the stack of memory cells separating the stack of memory cells and a sidewall of the dielectric material, and lateral surfaces of the memory cells not vertically aligned with lateral surfaces of any of the interconnect lines. A chemically metallic sidewall layer may enable a dielectric-on-dielectric process that negates the need for a large transition region between logic and memory regions.
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
H10B 53/50 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the boundary region between the core and peripheral circuit regions
92.
MULTI-THRESHOLD GATE DIELECTRIC PATTERNING SCHEME USING INDIVIDUALIZED GATE TUBS
Integrated circuit (IC) devices having gate-all-around (GAA) transistors. An IC device may include adjacent GAA transistors with gate electrodes having different gate dielectric stacks separated by a dielectric wall. The gate dielectric stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers on the inner gate dielectric layers. The inner gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Integrated circuit (IC) devices having isolation structures in metal gate cuts. An IC device may include first and second source-drain contacts in first and second transistor structures over a substrate, and a dielectric structure having first and second feet extending into the substrate, between the first and second source or drain contacts, and with a portion of the substrate between the first and second feet. The first and second feet may each have a width approximately equal to a gate length. The portion of the substrate between the first and second feet of the dielectric structure has a width approximately equal to a distance between adjacent gate electrodes. The dielectric structure may be formed in a gate cut by a self-aligned etch following a selective recess of source-drain contacts.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
94.
GERMANIUM-RICH METAL CONTACT LAYERS FOR PMOS SOURCE AND DRAIN CONTACTS
Outdiffusion of germanium from silicon-germanium source and drain regions of PMOS (p-channel metal-oxide-semiconductor) field effect transistors into metal contact layers located on the PMOS source and drain regions can reduce the concentration of germanium layer in the silicon-germanium in the vicinity of the silicon-germanium layer-metal contact layer interface. This region of reduced germanium concentration can increase the parasitic contact resistance, which can have a deleterious effect on PMOS transistor performance. Adding germanium to the metal contact layers can reduce or eliminate germanium outdiffusion and prevent parasitic contact resistance increases.
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
An apparatus comprises a push-pull regulation loop (PPRL). The PPRL comprises a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The PPRL also comprises a control circuit coupled to the PMOS transistor, the NMOS transistor, and the first plurality of capacitors. The control circuit comprises a reference terminal and is to receive a randomized voltage reference signal via the reference terminal. The control circuit further adjusts a reset voltage available at the first plurality of capacitors based on the randomized voltage reference signal.
G05F 1/595 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load semiconductor devices connected in series
G05F 1/46 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC
An integrated circuit (IC) assembly comprising a multiple IC die coupled to a module routing structure with an underfill material therebetween. A fillet of the underfill material may be confined to be in close proximity with an outer perimeter of the IC die, for example through formation of a barrier material that impedes outflow of the underfill material, or through ablation of an outer perimeter of the fillet. Through confinement of the underfill, dimensions of a multi-chip module may be reduced without exposing any portion of the underfill along a perimeter edge of the module. Following an overmold process, the IC assembly may be singulated into a multi-chip module, which may be further assembled, for example, by attaching the module routing structure to a package substrate structure.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
97.
TRANSISTOR WITH 2D CHANNEL MATERIAL CLADDING GATE STACKS
In a transistor structure, a 2D channel material is formed after fabrication of a gate insulator and gate (electrode). In accordance with some exemplary “channel-material last” embodiments, a contact area between the 2D channel material and a source terminal and/or drain terminal is much larger than an edge or layer thickness of the 2D channel material, which may only be a few nanometers, for example. This larger contact area may significantly reduce external resistance of a transistor structure. Doping and strain engineering may also be more successfully applied to the “channel-material last” transistor structures disclosed herein, further boosting transistor performance.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
98.
TRANSISTOR STRUCTURES WITH SELECTIVE SOURCE/DRAIN CONTACT METALLIZATION
Transistor structures with selectively deposited source/drain contact metallization. Through selective formation of contact metallization, damascene-type patterning of source/drain contact metallization may be avoided so that any differences in topography between transistor structures and adjacent isolation structures do not induce contact metallization shorts or other failures associated over-polishing source/drain contact metallization. In accordance with embodiments, a source/drain contact liner metallization may be deposited and/or retained only within a topographic recess over source/drain semiconductor material. Source/drain contact cap metallization may be then deposited and/or retained only on the contact liner metallization.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
99.
TRANSISTOR WITH LINER-LAST SOURCE AND DRAIN TRENCH CONTACTS, AND METHODS OF MAKING SAME
Semiconductor devices and systems with liner-last trench contacts, and methods of forming the same. The semiconductor device comprises a source region and a drain region, a source trench contact coupled to the source region, and a drain trench contact coupled to the drain region. Each trench contact resides in a contact trench and includes a contact plug, a contact metal layer below the contact plug, and a trench liner at the sidewalls of the contact trench. The uppermost surface of the contact metal layer is below the lowermost surface of the trench liner. A channel couples the source region to the drain region, and a gate couples to the channel. The trench liner includes silicon and at least one of oxygen and carbon. The device may correspond to a nanoribbon transistor, a gate-all-around (GAA) transistor, a fin field-effect transistor (FinFET), a planar transistor, or a two-dimensional transistor.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
100.
HEAT DISSIPATION STRUCTURE IN ADVANCED CHIP PACKAGE
A device including: a substrate; a chip module coupled to the substrate; a first thermal material disposed on the chip module; a second thermal material disposed on the chip module; a lid structure disposed over the chip module and coupled to the substrate with adhesive along a perimeter of the lid structure, wherein a central portion of the lid structure is in thermal contact with the first thermal material and the second thermal material; and a support structure arranged around the chip module and covered by the lid structure, the support structure extending vertically from the substrate to the lid structure.
