A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.
Embodiments include semiconductor packages and a method to form such semiconductor packages. A semiconductor package includes a plurality of dies on a substrate, and an encapsulation layer over the substrate. The encapsulation layer surrounds the dies. The semiconductor package also includes a plurality of dummy silicon regions on the substrate. The dummy silicon regions surround the dies and encapsulation layer. The plurality of dummy silicon regions are positioned on two or more edges of the substrate. The dummy silicon regions have a top surface substantially coplanar to a top surface of the dies. The dummy silicon regions include materials that include silicon, metals, or highly-thermal conductive materials. The materials have a thermal conductivity of approximately 120 W/mK or greater, or is equal to or greater than the thermal conductivity of silicon. An underfill layer surrounds the substrate and the dies, where the encapsulation layer surrounds portions of the underfill layer.
Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a wall within a metal gate cut in a transistor layer of a semiconductor device, where the wall includes a volume of a gas such as air, nitrogen, or another inert gas. Other embodiments may be described and/or claimed.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
A die package comprises a semiconductor die comprising a first face, a second face on an opposing second side, an active layer located between the first face and the second face, a first electrical pathway between the first face and the active layer, a second electrical pathway between the second face and the active layer, a first contact pad coupled to the first face and electrically connected to the first electrical pathway, and a second contact pad coupled to the second face and electrically connected to the second electrical pathway. In an example, the first electrical pathway is configured to transmit one or more signals between the first contact pad and the active layer and the second electrical pathway is configured to transmit electrical power between the second contact pad and the active layer.
An apparatus and system of providing energy saving in a network are described. A target node receives, from a source node, a handover request to handover a UE due to at least one of entry of the source node into a power saving state or mobility optimization. In response, the target node transmits a relative energy efficiency value of Bits per Joule and periodic feedback related to a status of the UE for training an AI/ML energy saving model and stops the feedback in response to a stop parameter being met. The stop parameter is a first of: a predicted period of the source node to stay in the power saving state or time for a UE to connect to the target node, a percentage of UEs handed over that enter an idle or inactive state, and a percentage of UEs handed over that are further handed to another node.
Embodiments herein relate to systems, apparatuses, or processes creating a package that includes a die embedded in a molding, where a surface of the die is coplanar with a surface of the molding. During a stage of package manufacture, the die may have a finished side that may be coupled with a component of the package, and an unfinished side. During a subsequent stage of package manufacture, molding may be placed around the die, and then the molding and at least a portion of the die may be planarized, which may involve grinding and polishing. The planarization may reveal one or more TSV at the side of the die which is now finished and ready for electrical coupling with other components. As a result, a side of the molding at a side of the die to be coplanar. Other embodiments may be described and/or claimed.
METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) AND A DATA BUFFER ON A BUFFERED DUAL IN-LINE MEMORY MODULE
System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a data buffer on the buffered DIMM enables its receivers to capture data read from DRAM integrated circuits on a MDQ/MDQS bus between the DRAM and the data buffer on the DIMM. After the MRE training has completed, the data buffer is configured to enable the data buffer receivers to receive data on the MDQ bus on the buffered DIMM during the preamble of the incoming MDQS burst from a read transaction in the DRAM. MRD training tunes the relationship between the MDQ/MDQS bus to ensure sufficient setup and hold eye margins for MDQ so that the data buffer optimally samples the data driven by the DRAM during reads of the DRAM.
Provided is a non-transitory machine-readable medium storing machine-readable program. The program is, when executed by a secure processor in a computing system comprising a host processing unit running a host operating system, OS, configured to perform, without relying on the host OS, hardware-level monitoring on at least one device, and store information obtained based on the hardware-level monitoring.
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
10.
INTER-USER EQUIPMENT (UE) COORDINATION INFORMATION FOR NEW RADIO (NR) SIDELINK COMMUNICATION
Various embodiments herein provide techniques for sending and receiving inter-user equipment (UE) coordination information for sidelink communication. The inter-UE coordination information may be provided via sidelink control information (SCI) and/or medium access control—control element (MAC-CE). Aspects regarding resource reservation and/or indication for UE coordination information are described. Additionally, new SCI formats for inter-UE coordination information are provided. Other embodiments may be described and claimed.
An electronic device includes a package substrate; a memory integrated circuit (IC) mounted on the package substrate; a mold layer including one or more chiplets and a base IC die within the mold layer, the one or more chiplets arranged on the base IC die; a top chiplet mounted on a surface of the mold layer, wherein a combined height of the mold layer and the top chiplet substantially matches a height of the memory IC; and a heat spreader having a uniform surface contacting the memory IC and the top chiplet.
A radio-head apparatus can comprise synchronization circuitry to receive transmission data and a phase correction signal. The synchronization circuitry can process the transmission data and the phase correction signal to generate digital transmitter (DTX) codes. The radio-head can further include transmission circuitry to combine the phase correction signal with transmission data codes to be provided to the DTX for transmission over an air interface. Other systems and apparatuses are described.
Embodiments described herein provide a technique to facilitate the broadcast or multicast of asynchronous loads to shared local memory of a plurality of graphics cores within a graphics core cluster. One embodiment provides a graphics processor including a cache memory a graphics core cluster coupled with the cache memory. The graphics core cluster includes a plurality of graphics cores. The plurality of graphics cores includes a graphics core configured to receive a designation as a producer graphics core for a multicast load, read data from the cache memory; and transmit the data read from the cache memory to a consumer graphics core of the plurality of graphics cores.
For example, an Access Point (AP) Multi-Link Device (MLD) and/or a non-AP MLD may be configured to utilize a mechanism configured to support link disablement of an AP. For example, the AP MLD may be configured to transmit from an AP of the AP MLD a broadcast frame including a link disable advertisement, the link disable advertisement to advertise a link disablement of the AP for all non-AP MLDs associated with the AP, the link disablement of the AP to indicate that the AP is to be unavailable for communication with all the non-AP MLDs associated with the AP; and disable communication of beacon frames and response frames from the AP based on the link disable advertisement.
A machine learning hardware accelerator architecture and associated techniques are disclosed. The architecture features multiple memory banks of very wide SRAM that may be concurrently accessed by a large number of parallel operational units. Each operational unit supports an instruction set specific to machine learning, including optimizations for performing tensor operations and convolutions. Optimized addressing, an optimized shift reader and variations on a multicast network that permutes and copies data and associates with an operational unit that support those operations are also disclosed.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 5/01 - Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.
An Internet of Things (IoT) network includes an orchestrator to issue service management requests, a service coordinator to identify components to participate in the service, and a component to perform a network service element. An IoT network includes an IoT device with service enumerator, contract enumerator, and join contract function. An IoT network apparatus includes permissions guide drafter for discovered peers, and permissions guide action executor. An IoT network apparatus includes floating service permissions guide drafter for discovered hosts, host hardware selector, floating service permissions guide executor, and service wallet value transferor. An IoT network apparatus includes permissions guide drafter for first and second discovered peers, parameter weight calculator, permissions guide term generator, and permissions guide action executor. An IoT network includes an IoT device with resource hardware component identifier, processor to process a received indication of an external module hardware requirement, an external module comparer, and deactivation signal transmitter.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 41/0806 - Configuration setting for initial configuration or provisioning, e.g. plug-and-play
H04L 41/12 - Discovery or management of network topologies
H04L 45/00 - Routing or path finding of packets in data switching networks
H04L 61/4505 - Network directoriesName-to-address mapping using standardised directoriesNetwork directoriesName-to-address mapping using standardised directory access protocols
H04L 61/5069 - Address allocation for group communication, multicast communication or broadcast communication
H04L 67/10 - Protocols in which an application is distributed across nodes in the network
H04L 67/1087 - Peer-to-peer [P2P] networks using cross-functional networking aspects
H04L 67/12 - Protocols specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
Examples described herein relate to assigning a virtual function (VF) to a processor based at least, in part, on a latency of a memory write operation. In some examples, the virtual function is to provide a process with access to a device and wherein the processor is to execute the process. In some examples, the latency is associated with a VF memory address mapped to a cache and home agent (CHA).
Various examples relate to an arrangement and to a method for forming an arrangement. The arrangement comprises a first component comprising a surface region with a first plurality of inductive elements for interfacing with a second plurality of inductive elements of a second component, and a filler material arranged on the surface region comprising the first plurality of inductive elements, so that, when the second component is arranged on the filler material, the filler material is arranged between the first and second plurality of inductive elements, wherein the filler material comprises nanoparticles configured to increase a magnetic permeability of the filler material.
Logic may parse an application function (AF) request from an AF, the AF request comprising a first set of parameters, the first set of parameters comprising a first geographical area and a sensing type. Logic may identify a radio access network (RAN) node based on the first geographical area. Logic may send a sensing request to the RAN node, the sensing request comprising a second set of parameters to identify sensing information, the second set of parameters comprising a second geographical area and a sensing type. Logic may receive a sensing result from the RAN node based on the second set of parameters. And logic may process the sensing result based on the AF request to determine a sensing report; and send, to the AF, the sensing report via the network interface.
An apparatus, including an electro-optical modulating means is for phase modulating a light signal with a range measurement code and a light beam isolation code; an electro-optical detecting means for receiving a reflected light signal of the phase modulated light signal reflected by an object and converting the received reflected light signal into an electronic data signal; and processor means for correlating the electronic data signal with the light beam isolation code and the range measurement code to obtain a range to the object.
G01S 17/32 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
23.
PIPELINING SERVICES IN NEXT-GENERATION CELLULAR NETWORKS
This disclosure describes systems, methods, and devices related to pipelining services. A device may receive from a service consumer a request for pipeline service with service orchestration chaining function (SOCF), wherein the request comprises pipeline service context information. The device may generate requirements for the pipeline service based on the pipeline service context information. The device may select Computation, Communication, and Data Control Functions (CFs) instances for the pipeline service. The device may send a pipeline policy create request to a policy control function (PCF) when the PCF is responsible for generating policies related to the pipeline service including a pipeline ID. The device may receive a pipeline policy create response from the PCF indicating results of the pipeline ID and policy generation.
H04L 41/0895 - Configuration of virtualised networks or elements, e.g. virtualised network function or OpenFlow elements
H04L 41/5054 - Automatic deployment of services triggered by the service manager, e.g. service implementation by automatic configuration of network components
H04L 61/4511 - Network directoriesName-to-address mapping using standardised directoriesNetwork directoriesName-to-address mapping using standardised directory access protocols using domain name system [DNS]
24.
FEDERATED LEARNING GROUP AUTHORIZATION OF NETWORK DATA ANALYTICS FUNCTIONS IN 5G CORE
This disclosure describes systems, methods, and devices related to federated learning (FL) group authorization. A device may receive a request for an access token from a network function (NF) service consumer to request network data analytics function (NWDAF) model training logical function (MTLF) (federated learning (FL) Server) services. The device may validate the access token associated with the NWDAF. The device may initiate an FL group based on the validated access token. The device may start the FL group for analytics identification (ID). The device may send a request to get an NF repository function (NRF) access token from an NRF. The device may perform global model updates and aggregation. The device may provide an NF service response to the NF service consumer.
An apparatus, including: an interface configured to receive image data in real-time of a surroundings of a vehicle; processing circuitry configured to: identify a point of interest within the received image data; generate modified image data based on the received image data and the identified point of interest; and transmit the modified image data to be displayed to a vehicle passenger.
G06T 11/60 - Editing figures and textCombining figures or text
B60J 3/04 - Antiglare equipment associated with windows or windscreensSun visors for vehicles adjustable in transparency
B60R 1/27 - Real-time viewing arrangements for drivers or passengers using optical image capturing systems, e.g. cameras or video systems specially adapted for use in or on vehicles for viewing an area outside the vehicle, e.g. the exterior of the vehicle with a predetermined field of view providing all-round vision, e.g. using omnidirectional cameras
G06V 10/25 - Determination of region of interest [ROI] or a volume of interest [VOI]
G06V 10/764 - Arrangements for image or video recognition or understanding using pattern recognition or machine learning using classification, e.g. of video objects
G06V 20/58 - Recognition of moving objects or obstacles, e.g. vehicles or pedestriansRecognition of traffic objects, e.g. traffic signs, traffic lights or roads
26.
Nanoribbon transistor source and drain with uniform nucleation
Described herein are nanoribbon transistors with a uniform layer of silicon material epitaxially deposited on the ends of the channel regions for the source and drain regions. The silicon is deposited over both the nanoribbon ends and dimple spacers between adjacent nanoribbons. The material may be deposited using a multicycle deposition and etch process, in which both crystalline and amorphous silicon are deposited in a low-selectivity process, and amorphous silicon is removed between deposition steps.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
An apparatus of a New Radio (NR) User Equipment (UE), includes the processing circuitry to: detect a synchronization signal block (SSB) from a NR Node B (gNB); determine a number of multiple physical random access channel (PRACH) transmissions, wherein respective PRACH transmissions of the multiple PRACH transmissions correspond to repetitions of each other and to a preamble; determine a set of valid PRACH occasions associated with the SSB, wherein respective ones of the valid PRACH occasions of the set: are in sequential respective time instances; and use same frequency resources as any immediately prior PRACH occasion of the set; and send the multiple PRACH transmissions in the set for transmission to the gNB.
Various embodiments herein provide techniques related to co-existence of ambient internet of things (A-IoT) devices with cellular network devices. Some embodiments may relate to physical channel structure and/or signaling between such devices. Some embodiments may relate to a random access channel (RACH) procedure to be performed by an A-IoT device. Other embodiments may be described and/or claimed.
A computer-readable storage medium stores instructions for execution by one or more processors of a UE. The instructions configure the UE for inter-RAT NR-EUTRAN measurement in a 5GNR and beyond network, and cause the UE to perform operations including encoding notification signaling for transmission to a base station. The notification signaling indicates a capability of the UE to perform the inter-RAT NR-EUTRAN measurement without a measurement gap. Configuration signaling received from the base station is decoded. The configuration signaling is to configure a periodicity and a minimum available time associated with an effective measurement window (EMW) that is non¬overlapping with the measurement gap. The inter-RAT NR-EUTRAN measurement is performed within the EMW and has a duration that is within the minimum available time.
A system and methods for enhancing Artificial Intelligence/Machine Learning (AI/ML) model transparency in 6th generation (6G) networks are introduced through the use of model cards. The model cards provide detailed metadata about AI/ML models, including architecture, training data, and performance metrics, in a machine-readable JSON format. The model card is exposed via network function service or retrieved via a Network Repository Function (NRF), or a dedicated model card registry network function is used to provide the model card. The model card enables visibility for service consumers into AI/ML models used, allowing for the evaluation of trustworthiness and promoting transparency and accountability in AI-driven 6G networks.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes first, second, and third sets of a plurality of transistor devices. The first set is configured to form at least one write port. The at least one write port receives digital data. The second set of the plurality of transistor devices is configured as an inverter pair that stores the digital data. The third set of the plurality of transistor devices is configured to form at least one read port. The at least one read port is used to access the digital data from the inverter pair and output the digital data on the local bitline. The plurality of transistor devices consists of an equal number of P-channel transistor devices and N-channel transistor devices.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Methods, apparatuses, and computer readable media for multi-AP coordination agreements, where a requesting AP is configured to: transmit to a responding AP, a MAPC request frame, the MAPC request frame including a MAPC negotiation information field including a MAPC element including a first MAPC schemes information field, the first MAPC schemes information field including a per-scheme profile subelement including a MAPC scheme control field, and a MAPC scheme AP parameter set field, the MAPC scheme control field indicating a MAPC scheme type, the MAPC scheme parameter set field indicating parameters for the MAPC scheme type, where the first per-scheme profile subelement indicates an agreement establishment with the parameters for the MAPC scheme type, and decode, from the responding AP, a MAPC response frame indicating the MAPC scheme type and indicating the agreement establishment is accepted.
For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.
For example, a first wireless communication device may be configured to determine a negotiated bootstrapping mechanism based on a first message-exchange including Peer-to-Peer (P2P) messages exchanged with a second wireless communication device; to pair the first wireless communication device with the second wireless communication device according to the negotiated bootstrapping mechanism; to derive a Pairwise Master Key Security Association (PMKSA) based on a second message-exchange with the second wireless communication device, e.g., after pairing with the second wireless communication device; and to determine an encryption key according to a third message exchange with the second wireless communication device based on the PMKSA. For example, the encryption key may be configured to encrypt a P2P communication with the second wireless communication device.
A controller system is configured to organize a plurality of compute kernels to execute an instance of an artificial intelligence inference pipeline, each of the compute kernels executing on a respective plurality of processing platforms; access metadata of each of the plurality of processing platforms, the metadata describing attestation data of each of the plurality of processing platforms; transmit the metadata to an evaluator system, the evaluator system to evaluate the metadata to validate that the plurality of processing platforms are compliant with a service level agreement; receive reinforcement data, the reinforcement data used to adjust at least one of the plurality of processing platforms in a later execution of the instance of the artificial intelligence inference pipeline; and communicate with a processing platform of the plurality of processing platforms to adjust a sensor configuration or an artificial intelligence model used by the processing platform.
H04L 9/00 - Arrangements for secret or secure communicationsNetwork security protocols
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
Bonding interfaces between a die and a carrier wafer are described herein. Using a bonding layer between wafers that includes metal, a doped dielectric material, and/or a semiconductor material may reduce damage from processes such as dicing. In one example, dopants are introduced into a dielectric material before bonding. In another example, the bonding layer includes a semiconductor material. In one example, a conductive material including a metal is used as a bonding interface between wafers. In some examples, the metallic bonding material may be patterned. In some examples, a conductive material including metal may replace a dielectric material as a bonding material. In other examples, the bonding interface may include a layer of conductive material and a layer of a dielectric material or a semiconductor material.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
38.
BUFFER STATUS REPORT (BSR) REPORTING WITH REDUCED LATENCY IN 5G NETWORKS
In a fifth-generation new radio (5GNR) network, a user equipment (UE) configured for single-step buffer status report (BSR) reporting encodes a BSR for transmission to a generation node B (gNB) without a separate scheduling request (SR) that requests an uplink grant for transmission of the BSR. The UE decodes an uplink grant received from the gNB in response to the BSR. The uplink grant schedules a physical uplink shared channel (PUSCH) for transmission of an amount of data indicated by the BSR. The latency associated with use of a separate SR and separate grant for transmission of the BSR is reduced.
H04W 28/02 - Traffic management, e.g. flow control or congestion control
H04W 72/21 - Control channels or signalling for resource management in the uplink direction of a wireless link, i.e. towards the network
H04W 72/231 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the layers above the physical layer, e.g. RRC or MAC-CE signalling
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
H04L 5/00 - Arrangements affording multiple use of the transmission path
39.
NUMEROLOGY, FRAME STRUCTURE, AND SIGNAL RESOURCE DIMENSIONING FOR JOINT COMMUNICATION AND SENSING SYSTEMS
An apparatus and system are described for joint communication and sensing. A sensing frame structure design is described within the next generation cellular system frame and numerology, as are the use of Positioning Reference Signals (PRS) for sensing with various expansions and adaptations. Speed/direction related measurements of a user equipment (UE) allow velocity estimation in localization/positioning. Specifics of sequence-based signal generation and initialization in which a Gold sequence is used are also described.
This disclosure describes systems, methods, and devices related to an unlicensed national information infrastructure 4 (UNII4) discovery. A device may identify a UNII4 discovery request received from a station device (STA) by a first AP of the AP MLD. The device may send the UNII4 discovery request from the first AP to a second AP of the AP MLD, wherein the second AP is capable of operating on a UNII4 frequency band. The device may send a discovery response to the discovery request from the second AP to the STA. The device may establish a first link in a multi-link operation between the second AP and the STA.
Embodiments herein relate to a machine learning (ML) management system of a cellular network. The ML management system may be configure to emulate, or facilitate emulation of, a trained ML model in an emulation environment. ML emulation may refer to performing inference using the ML model in an emulation environment that is different than an inference environment of the cellular network. Other embodiments may be described and/or claimed.
H04N 19/177 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a group of pictures [GOP]
H04N 19/105 - Selection of the reference unit for prediction within a chosen coding or prediction mode, e.g. adaptive choice of position and number of pixels used for prediction
H04N 19/159 - Prediction type, e.g. intra-frame, inter-frame or bidirectional frame prediction
H04N 19/33 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using hierarchical techniques, e.g. scalability in the spatial domain
H04N 19/593 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial prediction techniques
Methods and apparatus relating to a gold finger design for differential edge cards are described. In one embodiment, a signal finger comprises a first portion to communicate electrical signals between a signal pin of a card connector and a card; and a second portion to provide a mechanical wiping surface for the signal pin. Other embodiments are also claimed and disclosed.
Embodiments detailed herein relate to matrix (tile) operations. For example, decode circuitry to decode an instruction having fields for an opcode and a memory address; and execution circuitry to execute the decoded instruction to set a tile configuration for the processor to utilize tiles in matrix operations based on a description retrieved from the memory address, wherein a tile a set of 2-dimensional registers are discussed.
An apparatus and system of user equipment (UE) location determination using Transmission-Reception Points (TRPs) are described. Uplink angle of arrival (UL-AoA), UL relative time of arrival (UL-RTOA), and/or UL sounding reference signal reference signal received power (SRS-RSRP) measurements use an UL Antenna Reference Point (ARP) identifier (ID), which is associated with a UL ARP location (TRP panel) that is relative to the TRP geographical coordinates. The Location Management Function (LMF) requests additional path reporting for UE positioning for downlink Time Difference of Arrival (DL-TDOA), UL-TDOA, and multi-round trip time (RTT) reporting. The additional path information includes relative time difference and path quality indicator values and possibly a path RSRP value. The LMF indicates a maximum number of additional paths to be reported. The expected value and uncertainty range for each TRP is reported for downlink angle of departure (DL-AoD) measurements.
G01S 5/02 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations using radio waves
G01S 5/00 - Position-fixing by co-ordinating two or more direction or position-line determinationsPosition-fixing by co-ordinating two or more distance determinations
An apparatus can include sampling circuitry and processing circuitry coupled to the sampling circuitry. The processing circuitry can predict a next sample of an input signal and determine a predicative portion of the next sample of the input signal. The processing circuitry can subtract the predicative portion from the input signal to determine a non-predicative portion of the input signal and provide the non-predicative portion to the sampling circuitry for sampling.
A multi-link device (MLD) apparatus, including at least two transmission queues and first medium access control (MAC) circuitry and second MAC circuitry. The first MAC circuitry and the second MAC circuitry can transmit data of the at least two transmission queues over respective links responsive to receiving a trigger indicating that a transmission opportunity (TXOP) is available on the link corresponding to the respective first MAC circuitry and second MAC circuitry.
An electronic system includes a substrate and a top surface active component die. The substrate includes a glass core layer having a glass core layer active component die disposed in a cavity and a discrete passive component disposed in another cavity; a mold layer including a mold layer active component die disposed in the mold layer; and a buildup layer contacting a top surface of the glass core layer and a bottom surface of the mold layer. The buildup layer includes electrically conductive interconnect connecting the glass core layer active component die, the discrete passive component, and the mold layer active component die. The top surface of the component die is electrically connected to the mold layer active component die.
A processing engine in a neural network accelerator may include multiply-accumulate units and circle buffers. A circular buffer may be an output register file. Activations may be written to the circular buffer from a multiply-accumulate unit. Activations may be read from the circular buffer to the multiply-accumulate unit and to a post-processing engine in the neural network accelerator. The fill order and drain order for the circular buffer may be the same. A data point may be drained before all the data points of a stencil are written. The total number of entries in the circular buffer may be greater than a stencil size for a neural network but smaller than two times the stencil size. The circle buffer may be shared by different types of multiply-accumulate arrays in the processing engine. An output delivery unit may use non-linear addressing to write interleaved activations to a memory.
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/283 - Deposition of conductive or insulating materials for electrodes
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
This disclosure describes systems, methods, and devices related to generating region-based quantization parameters for video encoding. A method may include receiving, at a hardware encoder, source video comprising video frames; receiving, at the hardware encoder, from software associated with the hardware encoder, a video frame-level quantization parameter for a first video frame of the video frames; receiving, at the hardware encoder, from an application, a delta quantization parameter map, the delta quantization parameter map comprising per-pixel block quantization parameter modifications for respective pixel blocks of the first video frame; determining, by the hardware encoder, for the respective pixel blocks, respective sums of the per-pixel block quantization parameter modifications and the video frame-level quantization parameter; generating, by the hardware encoder, quantization parameters for the respective pixel blocks, the quantization parameters being the respective sums; and generating, by the hardware encoder, a bitstream based on the video frames and the quantization parameters.
H04N 19/126 - Details of normalisation or weighting functions, e.g. normalisation matrices or variable uniform quantisers
H04N 19/176 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being an image region, e.g. an object the region being a block, e.g. a macroblock
H04N 19/182 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
H04N 19/196 - Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the adaptation method, adaptation tool or adaptation type used for the adaptive coding being specially adapted for the computation of encoding parameters, e.g. by averaging previously computed encoding parameters
52.
METHOD AND SYSTEM OF AUTOMATIC CONTENT-DEPENDENT IMAGE PROCESSING ALGORITHM SELECTION
G06T 3/4053 - Scaling of whole images or parts thereof, e.g. expanding or contracting based on super-resolution, i.e. the output image resolution being higher than the sensor resolution
G06T 3/4046 - Scaling of whole images or parts thereof, e.g. expanding or contracting using neural networks
A molded ceramic layer of a multilayer cooling assembly back plate is described. The molded ceramic layer has an opening on a side of the molded ceramic layer that is to face a back side of a circuit board. The opening is aligned with a location of a back side component on the back side of the circuit board.
Optical couplers enable communication to and/or from PIC (Photonic Integrated Circuit). The optical couplers are manufactured at wafer-scale and provide detachable coupling to an array of optical fibers. A 3D waveguide structure is bonded to a PIC at the wafer level with high precision. Evanescent coupling is used to communicate optical signals between waveguides in the 3D waveguide structure and silicon waveguides within the PIC. Waveguides within the 3D waveguide structure are arranged to convert a 2D array of channels to a 3D array, with multiple stacked waveguides. This enables the connection interface to be scaled up from a 1-D array to a 2-D array, which increases the maximum number of optical channels in an interface between a PIC and a fiber array.
Techniques are provided herein to form an integrated circuit having semiconductor devices with source or drain regions that are formed using different epitaxial growth profiles. An integrated circuit includes a first semiconductor region extending in a first direction from a first source or drain region, and a second semiconductor region extending in the first direction from a second source or drain region. The second source or drain region may be wider than the first source or drain region along the first direction. The second source or drain region includes a first epitaxial region having one or more epitaxial layers and a second epitaxial region having one or more additional epitaxial layers on the first epitaxial region. Each of the first and second epitaxial regions may include at least one epitaxial layer that is doped with one or more n-type or p-type dopants and at least one layer that is substantially undoped.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A stacked wafer may include integrated dies that can implement neural network models. The stacked wafer may include a memory layer (e.g., a memory wafer) and a logic layer (e.g., a logic wafer). The memory layer and logic layer may each include dies and scribe lines. A memory die in the memory layer may include a first scribe line. The logic layer may include a second scribe line between a first logic die and a second logic die of the logic layer. The memory die and first logic die may be offset and electrically coupled through interconnects and a metal layer. The interconnects may connect the first scribe line to an input/output circuit of the first logic die. The metal layer may be the top metal layer of the memory wafer. The metal layer may facilitate both vertical electrical connectivity and horizontal electrical connectivity within the stacked wafer.
Apparatus and method for frequency-aware intelligent power control. For example, an example processor comprises: a plurality of cores; power management circuitry to control power consumption of the plurality of cores in accordance with a first power control mode or a second power control mode, the power management circuitry to enter the second power control mode when a frequency of a core of the plurality of cores has dropped below a specified minimum frequency; the power management circuitry to control power consumption of the core in the first power control mode through regulation of voltages and frequencies of the core; and the power management circuitry to control power consumption in the second power control mode by reducing dynamic capacitance (Cdyn) associated with the core while the core operates at or below the specified minimum frequency.
Microelectronic components and assemblies that have a high-density interconnect region with mixed bump widths may enable wafer sort-on-solder techniques with lower die area requirements and with improved power delivery to a high-density interconnect region. In one example, a microelectronic assembly includes two dies stacked over and coupled with one another and a plurality of conductive interconnects including a solder material (e.g., solder bumps/joints) between and coupled with the dies, where the plurality of conductive interconnects include first conductive interconnects with a first width and second conductive interconnects with a second with that is greater than the first width, and where the second conductive interconnects are coplanar and interleaved with the first conductive interconnects.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
59.
DETACHABLE OPTICAL INTERFACE WITH SELF-LOCKING MIRRORS
Optical couplers enable communication to and/or from PIC (Photonic Integrated Circuit). The optical couplers are manufactured at wafer-scale and provide detachable coupling to an array of optical fibers. A pair of lenses or mirrors on two sides of the vertical coupler provide a self-locking mechanism, which can increase the alignment tolerance of the vertical coupler compared to prior solutions.
Optical couplers enable communication to and/or from PIC (Photonic Integrated Circuit). The optical couplers are manufactured at wafer-scale and provide detachable coupling to an array of optical fibers. An angled reflector at the end of an optical channel enable vertical coupling to or from the PIC. The optical beam is expanded by a lens at the interface to increase alignment tolerance.
Optical couplers enable communication to and/or from PIC (Photonic Integrated Circuit). The optical couplers are manufactured at wafer-scale and provide detachable coupling to an array of optical fibers. An array of curved mirrors reflect beams received from the PIC towards a corresponding array of optical fibers; the curved mirrors change the direction of the beams.
Optical couplers enable communication to and/or from PIC (Photonic Integrated Circuit). The optical couplers are manufactured at wafer-scale and provide detachable coupling to an array of optical fibers. An optical coupler includes an optical bridge, where the optical bridge includes a pair of waveguides with a first pitch at a first portion of the bridge and a second pitch at a second portion of the bridge. Soft waveguides are coupled to the pair of waveguides at the first portion of the bridge by evanescent coupling.
Methods, apparatuses, and computer readable media for dynamic power save with initial control frame, where an AP is configured to: encode, for transmission, a first frame, the first frame comprising an indication that an initial Control frame (ICF) is required for the AP, transition to a low capability (LC) mode, decode, from a station (STA), a pre-association request frame, contend, after a transition delay period, for a wireless medium, encode, for transmission to the STA, a response frame to the pre-association request frame.
A method for phase correction includes determining a channel impulse response of a first component carrier associated with a first bandwidth, and determining a location of a first impulse response peak within the first bandwidth. A location of a second impulse response peak within a second bandwidth associated with the first component carrier or with a second component carrier is determined based on the location of the first impulse response peak. The second bandwidth is disjoint with the first bandwidth. A phase correction of one of a channel frequency response of the first bandwidth and a channel frequency response of the second bandwidth is performed based on the first impulse response peak and the second impulse response peak.
A compute device to manage workflow to disaggregated computing resources is provided. The compute device comprises a compute engine receive a workload processing request, the workload processing request defined by at least one request parameter, determine at least one accelerator device capable of processing a workload in accordance with the at least one request parameter, transmit a workload to the at least one accelerator device, receive a work product produced by the at least one accelerator device from the workload, and provide the work product to an application.
Examples include techniques for artificial intelligence (AI) capabilities at a network switch. These examples include receiving a request to register a neural network for loading to an inference resource located at the network switch and loading the neural network based on information included in the request to support an AI service to be provided by users requesting the AI service.
H04L 41/16 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using machine learning or artificial intelligence
H04L 41/0816 - Configuration setting characterised by the conditions triggering a change of settings the condition being an adaptation, e.g. in response to network events
H04L 41/5009 - Determining service level performance parameters or violations of service level contracts, e.g. violations of agreed response time or mean time between failures [MTBF]
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
A neural network accelerator can perform energy-efficient multiply-and-accumulate operations of a neural network by Booth encoding a stationary operand, such as weights, before a compute phase. The Booth-encoding circuitry generates and stores Booth encoded multipliers in a Booth encoded multiplier storage and a precomputed compensation value representing a sum of the compensation bits of the Booth encoded multipliers in a Booth compensation storage. Per-cycle Booth encoding and compute of the sum of the compensation bits are avoided during multiply-accumulate operations because Booth encoding is applied to stationary operands. The Booth encoder can be located at the periphery where the multiplicands are loaded onto the accelerator shared across multiple compute columns and/or tiles to amortize the Booth encoder area overhead. The Booth encoder supports reconfigurable operand bit widths (e.g., 16-, 8-, 4-, and 2-bit). The approach is applicable to single-instruction-multiple data (SIMD) arrays, systolic arrays, and analog/digital compute-in-memory arrays.
G06F 7/544 - Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state deviceMethods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using unspecified devices for evaluating functions by calculation
69.
OUTPUT ANALOG SCALING TECHNIQUE IN ANALOG COMPUTE-IN-MEMORY MACRO
To address an output accumulation precision gap issue, techniques that amplify selected signals before digitization or adaptive scaling methods that adjust the signal range based on the distribution of the accumulated output can improve the effective resolution of the analog-to-digital converter (ADC) and mitigate the impact of selected input signals on its performance. By inserting a (programmable) gain stage that provides k-bit analog signal amplification before digitization, the ADC's dynamic range can be maximized. After conversion, the output digital data can be to be right-shifted accordingly, effectively expanding the total meaningful data by k-bit with the same ADC number of bits.
Various embodiments herein are directed to remote direct memory access (RDMA) support in cellular networks. In particular, some embodiments may relate to enhancements to RDMA over cellular network (RoCN) protocols.
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
H04W 4/029 - Location-based management or tracking services
H04W 28/02 - Traffic management, e.g. flow control or congestion control
71.
INTER-CELL BEAM MANAGEMENT SCHEDULING RESTRICTION AND REPORTING
An apparatus and system are described for scheduling restriction of inter-cell Layer 1 Reference Signal Received Power (L1-RSRP) measurements when the Synchronization Signal Block (SSB) and data are scheduled in the same symbol. The scheduling restriction includes that the UE is not expected to receive downlink data or control signaling on symbols corresponding to SSB indexes configured for L1-RSRP measurement, where the data/control signals are transmitted by different cells and have the same subcarrier spacing (SCS) or have a different SCS and the UE supports simultaneousRxDataSSB-DiffNumerology. The cells include the UE serving cell and another cell that has a different physical cell identifier (PCI). For different SCS and no UE support of simultaneousRx-DataSSB-DiffNumerology, the UE is not expected to receive downlink data/control signaling or channel state information reference signals or transmit uplink data/control signaling or sounding reference signals on symbols corresponding to SSB indexes configured for L1-RSRP measurement.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
IC structures fabricated using deep via formation techniques described herein may have improved backside uniformity. In one example, a method of forming a deep via involves forming an opening that stops on the substrate, providing a mask material on the substrate in the opening, providing a liner in the opening on the sidewalls and over the mask material, removing the mask material from the opening and providing a conductive material in the partially lined opening. In one example, the partial liner on the sidewalls of the opening extends only part of the way down the via opening.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
73.
VIA, VIA PAD, AND TRACE PAIR ARRANGEMENTS FOR DIFFERENTIAL SIGNALS
An apparatus comprises a base component comprising a surface. The surface comprises a plurality of via pads and a plurality of interconnect pads arranged in a regular pattern of rows and columns orthogonal to the rows. A plurality of conductive vias extend below the surface. Each conductive via is coupled with one of the via pads. First and second interconnect pads in first and second rows in a first column are for coupling with a pair of differential signals. A first via pad in the first row intersects with the first interconnect pad. A second via pad in the second row contacts, partially overlaps, or spaced away from the second interconnect pad. The first via pad may be offset from a center line of the first row. The second via pad may be offset from a center line of the second row.
Integrated circuit structures having both spine-FET and gate-all-around (GAA) architectures are described. In an example, a structure includes a dielectric backbone. A first vertical stack of nanowires is laterally adjacent to and in contact with a first side of the dielectric backbone. A first gate electrode is around the first vertical stack of nanowires. A second vertical stack of nanowires is laterally spaced apart from the first vertical stack of nanowires, the second vertical stack of nanowires free from a dielectric backbone. A second gate electrode is around the second vertical stack of nanowires.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
75.
INTEGRATED CIRCUIT STRUCTURES HAVING HYBRID SPINE-FET ARCHITECTURE
Integrated circuit structures having hybrid spine-FET architectures are described. In an example, an integrated circuit structure includes a spine field effect transistor (SFET) including a hybrid dielectric spine. The hybrid dielectric spine includes a gate region dielectric spine, and a source or drain region dielectric spine separate and distinct from the gate region dielectric spine.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
An age monitoring approach using an oscillator circuit and an identified trip voltage for the oscillator to measure frequency degradation. The trip voltage allows for the frequency degradation to be measured without having to unreasonably take temperature into account.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 23/10 - Arrangements for measuring frequency, e.g. pulse repetition rateArrangements for measuring period of current or voltage by converting frequency into a train of pulses, which are then counted
77.
STANDARD CELL ARCHITECTURE WITH FRONTSIDE AND BACKSIDE POWER VIA CONNECTIONS
Techniques are provided herein to form an integrated circuit with a standard cell layout that can utilize both frontside and backside connections along with power vias to provide either frontside or backside power rails to the circuit. The standard cell layout may include, for example, two total transistors with one transistor being an n-channel device with the other being a p-channel device. Power vias may be arranged at the boundaries of the standard cell layout, along with both frontside and backside connections to enable either frontside or backside compatible layouts for the power delivery. In some examples, each of the devices of the standard cell may be GAA transistors that each have a number of nanoribbons or other semiconductor bodies (e.g., one to four) extending in the same direction. Other standard cell layouts may include, for example, four total transistors arranged in a NAND or a NOR configuration.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
Embodiments herein relate to battery charger circuitry for a battery-powered computing device. The circuitry can improve the efficiency of a voltage regulator in a battery charger by reducing its input voltage in response to a sensed skin temperature of the computing device exceeding a threshold. The input voltage can be reduced by negotiating a new power level with an external Universal Serial Bus (USB) adapter, for example. The input voltage can be reduced while ensuring that the required power of the device is maintained. The input voltage can also be based on a sensed charge level of the battery in the computing device.
Adjustments to edges in an integrated circuit layout are made during optical proximity correction based on trained stochastic failure prediction models. The stochastic failure prediction models generate average edge placement errors and standard deviations of edge placements for as-manufactured features that correspond to an edge in an integrated circuit layout. A defect rate model calibrated for a particular integrated circuit manufacturing process generates a predicted defect rate for a layout geometry based on information generated by the stochastic failure prediction models. Optical proximity correction can utilize multiple stochastic failure prediction models that model multiple defect modes to determine which edges of an integrated circuit layout are to be adjusted in a photomask layout to reduce the defect rate. The stochastic failure prediction models can also be used during mask validation to identify regions of the photomask layout that are predicted to have high defect rates.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
80.
CHANNEL WIDTH AND QUANTITY VARIATION IN GATE-ALL-AROUND AND FORKSHEET TRANSISTORS
Techniques to form gate-all-around (GAA) and/or forksheet semiconductor devices that have varying semiconductor channel widths and varying numbers of semiconductor channel bodies (e.g., nanoribbons, nanosheets, nanowires). The techniques can be used in any number of transistor technologies, but are particularly useful in vertically stacked transistor configurations (e.g., stacked in a vertical z-direction from the substrate surface) and/or configurations that extend laterally in a horizontal x-or-y-direction). In an example, the n-channel device and the p-channel device may both be GAA or forksheet transistors each having any number of channel bodies extending in the same direction where the n-channel device is located vertically above the p-channel device (or vice versa). Any number of adjacent devices may be patterned from a single fin to include varying channel body widths. In addition, any of the devices may include different numbers of channel bodies extending between corresponding source or drain regions.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Metal interconnect structures having modified interconnect interfaces are described. In an example, an integrated circuit structure includes a device layer including a plurality of nanowire-based devices or a plurality of fin-based devices. A conductive line is above the plurality of nanowire-based devices of the device layer or the plurality of fin-based devices. A conductive cap is on the conductive line. An inter-layer dielectric (ILD) layer is above the conductive cap. A conductive structure is in an opening in the ILD layer and the conductive cap. The conductive structure includes a conductive barrier layer and a conductive fill. The conductive barrier layer is in direct physical contact with the conductive line.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
82.
TUB ARCHITECTURE INTEGRATED CIRCUITS WITH DIELECTRIC WALLS HAVING LINERS AND CAPS OPTIONALLY FORMED IN A REFLOWABLE MATERIAL
Devices, integrated circuit structures, systems, and techniques are described herein related to a tub complementary field effect transistor architecture. Transistor structures each having vertically aligned nanowires are separated by dielectric walls. The dielectric walls may include dielectric liners and/or dielectric caps. The dielectric walls may be formed in a reflowable material used to embed the aligned nanowires. A gate structure is fabricated on each of the transistor structures by selectively by exposing the transistor structures using a patterned opening confined by the dielectric walls.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Devices, integrated circuit structures, systems, and techniques are described herein related to a tub complementary field effect transistor architecture. Transistor structures each having first and second complementary and vertically aligned nanowires are separated by dielectric walls. A sacrificial material embedding one of the transistor structures is accessed and removed using a mask having an opening at least partially over the sacrificial material. At least a portion of a gate stack is formed on the exposed transistor structure, and such processing is repeated for any number of transistor structures.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
Devices, integrated circuit structures, systems, and techniques are described herein related to die-to-die stitching interconnects formed in a carrier wafer that is used as a support during backside metallization fabrication. A device layer is between frontside interconnect metallization and backside interconnect metallization such that each of the device layer, the frontside interconnect metallization, and the backside interconnect metallization includes active regions separated by an inactive region. Stitch interconnects are above the inactive regions over the frontside interconnect metallization and extend across the inactive regions to couple the active regions and provide die-to-die interconnection therebetween.
Integrated circuit structures having dummy links for uniform grid metal gate and trench contact cut are described. A structure includes a vertical stack of horizontal nanowires or a fin. A gate electrode is over the vertical stack of horizontal nanowires of the fin. A first conductive trench contact is adjacent to a first side of the gate electrode. A second conductive trench contact is adjacent to a second side of the gate electrode. A dielectric cut plug structure is extending through the gate electrode and through the first and second conductive trench contacts, the dielectric cut plug structure having a recess laterally adjacent to first and second portions of the first conductive trench contact. A conductive link is in the recess of the dielectric cut plug structure, the conductive link connecting the first and second portions of the first conductive trench contact. A conductive structure is in a recess of the second conductive trench contact.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 30/62 - Fin field-effect transistors [FinFET]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
Integrated circuit (IC) devices having forksheet transistors. An IC device may include adjacent forksheet transistors with different gate stacks separated by a dielectric wall. The dielectric wall may be similar to, and centered between, adjacent forksheet spines that are on and between stacks of nanoribbon channels. The gate stacks may include inner gate dielectric layers on nanoribbon channels and outer gate dielectric layers both on the inner gate dielectric layers and on the dielectric wall separating the gate dielectric stacks. Either or both of the inner and outer gate dielectric layers of the adjacent transistors may have different thicknesses or material compositions. The dielectric wall between gate electrodes and gate dielectric stacks may enable independent processing of the transistors gates by dividing the nanoribbon channels into separate gate tubs.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
A prefetch circuit for page table entry (PTE) prefetching is described. In certain examples, a computing system (e.g., system on a chip) includes a system memory; a cache; an execution circuit to generate a memory access request comprising a virtual address; a page miss handler to, based on a miss of the virtual address in a translation lookaside buffer comprising a plurality of virtual address to physical address mappings, send a request to a data structure for multiple level paging in the system memory that stores a cache line that includes a page table entry to indicate a physical address for the virtual address of the memory access request, and fill the physical address for the virtual address into the translation lookaside buffer; and a prefetch circuit to, based on the miss of the virtual address in the translation lookaside buffer, cause a store of at least one other cache line of page table entries into the cache from the data structure for multiple level paging that stores the cache line.
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
88.
MIDDLE LEVEL INTERCONNECT ARCHITECTURE FOR PANEL LEVEL INTERPOSER INTEGRATION
Embodiments disclosed herein include an apparatus that comprises a component embedded in a substrate, and a first die on a first surface of the substrate. In an embodiment, a layer is on a second surface of the substrate that is opposite from the first surface. In an embodiment, a pad is on the layer, and the pad extends away from the layer. In an embodiment, a liner is on a sidewall of the pad.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
89.
PACKAGE WITH MOLD EXTENSION TO ENABLE PACKAGE-TO-PACKAGE TOPSIDE BRIDGE ATTACH
Embodiments disclosed herein include an apparatus that includes a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, a layer is on the first surface of the substrate, and a pillar is embedded in the layer. In an embodiment, a first pad is on a third surface of the layer that faces away from the substrate, where the first pad is coupled to the pillar. In an embodiment, a second pad is on the second surface of the substrate, where the first pad and the second pad share a substantially common centerline.
Embodiments disclosed herein include an apparatus that comprises a substrate with a first surface and a second surface opposite from the first surface, where the first surface has a first flatness, a first pillar on the first surface of the substrate, and a second pillar on the first surface of the substrate. In an embodiment, a component is on the first surface of the substrate, where the component is between the first pillar and the second pillar. In an embodiment, a layer is over the first surface of the substrate, where the layer embeds the first pillar, the second pillar, and the component, and where a third surface of the layer facing away from the substrate has a second flatness that is flatter than the first flatness.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
91.
CONVERSION OF METAL/METAL OXIDE MATERIALS TO SEMICONDUCTING TRANSITION METAL DICHALCOGENIDE MATERIALS IN GATE-ALL-AROUND (GAA) TRANSISTOR DEVICES
In some embodiments, a gate-all-around (GAA) transistor device includes channels comprising transition metal dichalcogenide materials. The channels are formed by converting metal or metal oxide material layers (which include, e.g., molybdenum or tungsten) of a material stack into the transition metal dichalcogenide material during a transistor fabrication process. The conversion may be performed by heating the metal/metal oxide material layers of the stack in the presence of a gas comprising, for example, sulfur, selenium, or tellurium, during the transistor fabrication process.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/383 - Diffusion of impurity materials, e.g. doping materials, electrode materials, into, or out of, a semiconductor body, or between semiconductor regions using diffusion into, or out of, a solid from or into a gaseous phase
H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
Transistor structures with source/drain contact metallization that includes an oxygen scavenging material. By incorporating the oxygen scavenging material, oxidation of a contact liner metallization that interfaces with semiconductor source/drain material may be reduced and a source/drain contact metallization structure may display improved stability.
Integrated circuitry comprising transistors having different transistor threshold voltages (Vt). In some examples, a gate electrode of the transistors with different Vt may include only one workfunction metal. Another metal, such as a fill metal, may be deposited over the workfunction metal and provide a solid-state source of fluorine that will subsequently diffuse toward the channel region(s), entering the workfunction metal. As diffused, different concentrations of fluorine may remain with workfunction metals of different transistors, thereby altering their threshold voltages. Different amounts of fluorine may be allowed to diffuse into different transistor structures to provide a range of Vt suitable for integrated circuit topologies of different performance/power metrics.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
Microelectronic integrated circuit package structures include a package structure comprising an embedded bridge interconnect structure within a substrate, the embedded interconnect bridge structure having a plurality of vias extending through a silicon layer, the silicon layer having two or more scallop structures. A non-conductive layer is on a first side of the silicon layer, and a dielectric layer is on a second side of the silicon layer. A plurality of die contacts are at least partially on a surface of the dielectric layer. A first die is over the embedded interconnect bridge structure, the first die coupled to the plurality of die contacts. A second die is over the embedded interconnect bridge structure, adjacent to the first die, the second die coupled to the plurality of die contacts.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
95.
EMBEDDED FERROELECTRIC CAPACITORS IN THE BACK END OF LINE FOR FERROELECTRIC RANDOM ACCESS MEMORY
Ferroelectric capacitors may be embedded in a stack structure of an integrated circuit device as part of on-chip ferroelectric random access memory (FeRAM). An example integrated circuit device comprises a device layer and a stack structure above the device layer. The device layer includes a first transistor. The stack structure includes a first layer with a first interconnect structure and a dielectric material, and a second layer between the device layer and the first layer. The integrated circuit device further includes a capacitor in a cavity within the stack structure. The capacitor includes a first conductive portion, a second conductive portion conductively coupled to the first transistor, and a dielectric portion comprising ferroelectric material. The dielectric portion is located between the first conductive portion of the capacitor and the second conductive portion of the capacitor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 1/68 - Capacitors having no potential barriers
96.
STRAIN ENGINEERING IN TWO-DIMENSIONAL MATERIALS FOR HIGH-PERFORMANCE TRANSISTORS
Devices and systems with strained two-dimensional (2D) materials, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes source and drain contacts, a channel extending between the source and drain contacts, and a gate over the channel. The source and drain contacts include one or more stressed metals, and the channel includes a strained 2D material.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
In one embodiment, an electrostatic discharge (ESD) detection circuit includes diodes in the front end (FE) or device layer of an integrated circuit structure and metal-insulator-metal (MIM) via fuses within interconnect metallization layers of the integrated circuit structure. The MIM via fuses include a fuse material layer between a metallization feature of a first interconnect metallization layer and a second interconnect metallization layer.
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/528 - Layout of the interconnection structure
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
98.
APPARATUS AND METHOD FOR EFFICIENT PREFETCHING USING SECURE ERROR CORRECTION CODE (ECC) ENCODING
An apparatus and method for efficient prefetching using secure ECC encodings. For example, one embodiment of an apparatus comprises: front end circuitry to fetch and decode a plurality of instructions; execution circuitry to execute the plurality of instructions, the execution circuitry to fetch a first memory line from a system memory, the first memory line comprising an identifier for a second memory line, the identifier at least partly encoded in a hidden error correction code (ECC) symbol; and prefetch circuitry to prefetch the second memory line responsive to reading the identifier from the first memory line.
A fault isolation module for detecting electrical defects through DC and/or RF thermal excitation in semiconductor devices is provided. Using a coupled thermal imaging module, thermally excited defects and thermal signatures for defects can be detected.
A User Equipment (UE) configured for operation in a fifth-generation new radio (5G NR) network, may receive an RRC handover command when the UE is in a radio-resource control (RRC) connected state with a source primary cell (PCell) (Cell1). The UE may detect a target PCell (Cell 2) and a target primary secondary cell (PSCell) (Cell 3) after receipt of the RRC handover command. In response to the RRC handover command, the UE may transmit a first physical random-access channel (PRACH) for handover to the target PCell within a first predetermined time period after receipt of the RRC handover command and transmit a second PRACH to add or change to the target PSCell within a second predetermined time period after receipt of the RRC handover command. More time may be allowed when the PSCell is transmitted within narrow bandwidth (e.g., a 12 PRB bandwidth)
