A transmission driver for serial communication includes first multiplexing circuitry configured to partially serialize a data group into data subgroups based on an in-phase clock, and to delay a quadrature clock corresponding to the in-phase clock. The delay is based on latency of the partial serialization. The transmission driver also includes second multiplexing circuitry having a source-series terminated (SST) driver configured to serialize the data subgroups into a serial data stream based on the delayed quadrature clock. The first multiplexing circuitry may be configured to partially serialize the data group into the data subgroups by arranging a four-bit data group into a pair of two-bit data groups, and the second multiplexing circuitry may be configured to serialize the data subgroups into the serial data stream by arranging the pair of two-bit data groups into the serial data stream.
A new approach is proposed that contemplates system and method to support a new network architecture for secure AI computing based on one or more secure, multi-core (SMC) data processing units (DPUs). Each of the SMC DPUs includes a gateway that ensures a secure interface and operating environment for the SMC DPU through encryption. Each of the SMC DPUs may further include a microprocessor core, one or more general purpose processing units (XPU cores) and/or customized processing units (CXPU cores), and a communications interface (COMM I/F) to external memories and other processing units. In some embodiments, a secure AI cloud cluster is constructed using multiple SMC DPUs along with one or more of switches, memories, separate XPUs, and high-speed interconnects (including optical interconnects) to ensure protection of client data for cloud-based AI services.
A communication device includes a convolutional interleaver and an encoder. The convolutional interleaver is configured to receive first codewords encoded using a first error-correcting code. The first codewords include symbols. The convolutional interleaver is configured to distribute the symbols from the first codewords into a second codeword to improve robustness to burst errors. The distribution of the symbols is performed by way of interleaving symbols from different first codewords into the second codeword. The encoder is configured to encode the second codeword using a second error-correcting code, which is different from the first error-correcting code, by appending error-correcting bits to the second codeword.
H03M 13/27 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes utilisant des techniques d'entrelaçage
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
A first communication device determines, based on information included in a first packet received from a second communication device, i) an overall frequency bandwidth of an operating channel of a WLAN and ii) one or more punctured sub-channels for the operating channel. The first communication device transmits, via a plurality sub-channels included in the operating channel of the WLAN, the plurality of sub-channels not including any of the one or more punctured sub-channels, a second packet that includes an RTS frame to initiate a TXOP of the first communication device. The first communication device receives, via a subset of the plurality of sub-channels, a third packet that includes a CTS frame, determines that the subset of sub-channels is reserved for the transmit opportunity TXOP initiated by the first communication device, and transmit a fourth packet to the second communication device during the TXOP via the subset of sub-channels.
An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
H03M 13/27 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes utilisant des techniques d'entrelaçage
H03M 13/19 - Correction d'une seule erreur sans utiliser les propriétés particulières des codes cycliques, p. ex. codes de Hamming, codes de Hamming étendus ou généralisés
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes combinant plusieurs codes ou structures de codes, p. ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
6.
LOAD BALANCING FOR WEIGHTED EQUAL COST MULTI-PATH (ECMP)
Techniques as described herein may be implemented to support selecting a transmission path in a multi-path network link. In an embodiment, respective cumulative data carrying capacities for selected network paths in a group of network paths defining a multi-path group used to forward network packets from a first network node to a second network node are computed. A cumulative capacity comparison value for a received network packet in a flow of network packets is computed based at least in part on a hash value used to distinguish the flow from other flows of network packets. A specific network path is selected from amongst the network paths of the multi-path group, over which to forward the received network packet from the first network node towards the second network node, based on comparing the cumulative capacity comparison value with at least a subset of the cumulative data carrying capacities.
Managing patching of write-limited memory with a hardware security module (HSM) comprising a plurality of one-time programmable (OTP) memory blocks where each OTP memory block is associated with a respective identification value, comprises: receiving, from a patching entity, a patch management request, the patch management request comprising a first identification value associated with an OTP memory block of the plurality of OTP memory blocks of the HSM, an identity token, a cryptographic key, and a signature object; comparing, by the HSM, the identity token and the cryptographic key to a respective identity token and a respective cryptographic key stored in the HSM; verifying, by the HSM, the signature object of the patch management request; configuring a patch code; and installing the patch code in the write-limited memory.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A new approach is proposed that contemplates system and method to support a new network architecture for secure AI computing based on one or more secure, multi-core (SMC) data processing units (DPUs). Each of the SMC DPUs includes a gateway that ensures a secure interface and operating environment for the SMC DPU through encryption. Each of the SMC DPUs may further include a microprocessor core, one or more general purpose processing units (XPU cores) and/or customized processing units (CXPU cores), and a communications interface (COMM I/F) to external memories and other processing units. In some embodiments, a secure AI cloud cluster is constructed using multiple SMC DPUs along with one or more of switches, memories, separate XPUs, and high-speed interconnects (including optical interconnects) to ensure protection of client data for cloud-based AI services.
A new approach is proposed to support SRAM less bootup of an electronic device. A portion of a cache unit of a processor is utilized as a SRAM to maintain data to be accessed via read and/or write operations for bootup of the electronic device. First, the portion of the cache unit is mapped to a region of a memory, which has not been initialized. The processor reads data from a non-modifiable storage to be used for the bootup process of the electronic device and writes the data into the portion of the cache unit serving as the SRAM. To prevent having to read or write to the uninitialized memory, any read operation to the memory region returns a specific value and any write operation to the memory region is dropped. The processor then accesses the data stored in the portion of the cache unit to bootup the electronic device.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
10.
Method and system for memory management within machine learning inference engine
A method includes receiving a machine learning (ML) network model in high-level code; generating an internal representation (IR), the IR is mapped to components in a multi-processing tile device; determining whether a first processing tile with a first on-chip memory (OCM) has a same dimension for an input/output tensor data as a second processing tile with a second OCM performing a same primitive function based on the IR; allocating a same memory address range within the first and the second OCM for the same primitive function if the first processing tile has the same dimension for the input/output tensor data as the second processing tile for the same primitive function; linking the memory address range of the first OCM to the memory address range of the second OCM to form a grouped memory space within the first and the second OCM respectively; and compiling low-level instructions based on the linking.
Link data is stored in a distributed link descriptor memory (“DLDM”) including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.
New and advanced computing tools and operations require increasingly large amounts of memory and computing power. Disclosed herein are novel apparatus and methods the provide a scalable, modular, and adaptable design that enables any desired configured of additional nodes to be connected to and used to host computing nodes. The design does not require changes to the hardware, software, or protocols of the host computing nodes which can view the additional nodes as a unitary source of supplemental compute and memory. The disclosed design includes the connection of additional nodes in a peer-to-peer topology that enables a chain interconnected of multiple additional nodes share a single connection to a host node. This avoids the limitations imposed by individual node space and configurations on the amount of compute and memory that can be provided to host nodes.
A system and corresponding method perform large memory transaction (LMT) stores. The system comprises a processor associated with a data-processing width and a processor accelerator. The processor accelerator performs a LMT store of a data set to a coprocessor in response to an instruction from the processor targeting the coprocessor. The data set corresponds to the instruction. The LMT store includes storing data from the data set, atomically, to the coprocessor based on a LMT line (LMTLINE). The LMTLINE is wider than the data-processing width. The processor accelerator sends, to the processor, a response to the instruction. The response is based on completion of the LMT store of the data set in its entirety. The processor accelerator enables the processor to perform useful work in parallel with the LMT store, thereby improving processing performance of the processor.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
15.
Reconfigurable optical receiver for use with multiple modulation techniques
In an optical receiver apparatus for use with multiple optical modulation techniques, a photodiode circuit is configured to process optical signals corresponding to multiple optical modulation techniques, including a first modulation technique and a second modulation technique different from the first modulation technique. The photodiode circuit includes: a first photodiode configured to receive a first optical signal corresponding to a first modulation technique, and a multiple-input second photodiode coupled in series with the first photodiode. The multiple-input second photodiode is configured to receive i) a second optical signal corresponding to the first modulation technique, and ii) a third optical signal corresponding to the second modulation technique. An input of a transimpedance amplifier is coupled to the first photodiode and the second photodiode via a node between the first photodiode and the second photodiode.
Methods and apparatus for beamforming in MIMO systems are disclosed. In an embodiment, a method is provided that includes associating a plurality of signal-to-noise ratio (SNR) ranges with a plurality of precoding schemes, respectively, identifying groups of user equipment (UE) that have SNRs within each SNR range, and configuring downlink transmissions to each group of UE to use a precoding scheme associated with the SNR range of that group.
A circuit and corresponding method perform resource arbitration. The circuit comprises a pending arbiter (PA) that outputs a PA selection for accessing a resource. The PA selection is based on PA input. The PA input represents respective pending-state of requesters of the resource. The circuit further comprises a valid arbiter (VA) that outputs a VA selection for accessing the resource. The VA selection is based on VA input. The VA input represents respective valid-state of the requesters. The circuit performs a validity check on the PA selection output. The circuit outputs a final selection for accessing the resource by selecting, based on the validity check performed, the PA selection output or VA selection output. The circuit addresses arbitration fairness issues that may result when multiple requesters are arbitrating to be selected for access to a shared resource and such requesters require a credit (token) to be eligible for arbitration.
A data channel on an integrated circuit device includes a non-linear equalizer having as inputs digitized samples of signals on the data channel, decoding circuitry configured to determine from outputs of the non-linear equalizer a respective value of each of the signals, and adaptation circuitry configured to adapt parameters of the non-linear equalizer based on respective ones of the value. The non-linear equalizer includes a non-linear filter portion, and a front-end filter portion configured to reduce numbers of the inputs from the digitized samples. The non-linear equalizer may be a neural network equalizer, such as a multi-layer perceptron neural network equalizer, a reduced complexity multi-layer perceptron neural network equalizer, or a radial-basis function neural network equalizer. Alternatively, the non-linear equalizer may include a linear filter and a non-linear activation function, which may be a hyperbolic tangent function.
An electro-optical modulator includes a substrate and an optical waveguide including an electro-optical thin film disposed on the substrate. The optical waveguide has an input end coupled to receive an optical signal and an output end opposite the input end. First and second electrodes are disposed on the substrate along opposite sides of the waveguide. A differential driver has first and second differential outputs coupled to apply a differential electrical signal between the first and second electrodes to modulate a polarization of the optical signal propagating in the waveguide.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers (68, 72, 76) including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers (64, 68) forming a capacitance component that is connected in series with the reverse-biased semiconductor junction. The PD further includes a first electrode (80) and a second electrode (84), configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.
H10F 30/223 - Dispositifs individuels à semi-conducteurs sensibles au rayonnement dans lesquels le rayonnement commande le flux de courant à travers les dispositifs, p. ex. photodétecteurs les dispositifs ayant des barrières de potentiel, p. ex. phototransistors les dispositifs étant sensibles au rayonnement infrarouge, visible ou ultraviolet les dispositifs ayant une seule barrière de potentiel, p. ex. photodiodes la barrière de potentiel étant du type PIN
H10F 77/122 - Matériaux actifs comportant uniquement des matériaux du groupe IV
An electro-optical modulator (100) includes a substrate (104) and an optical waveguide (106) including an electro-optical thin film (102) disposed on the substrate. The optical waveguide has an input end (105) coupled to receive an optical signal and an output end (109) opposite the input end. First and second electrodes (108, 110) are disposed on the substrate along opposite sides of the waveguide. A differential driver (124) has first and second differential outputs (126, 128) coupled to apply a differential electrical signal between the first and second electrodes to modulate a polarization of the optical signal propagating in the waveguide.
G02F 1/035 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des céramiques ou des cristaux électro-optiques, p. ex. produisant un effet Pockels ou un effet Kerr dans une structure de guide d'ondes optique
G02F 1/225 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur par interférence dans une structure de guide d'ondes optique
22.
SIMULTANEOUS BIDIRECTIONAL SIGNALING IN THROUGH-SILICON VIAS
A signal transmitter transmits a signal onto the bidirectional transmission medium of the TSV. A boost circuit is available to supplement the signal as needed. Calibration circuitry periodically activates, at an interval of time, a signal driver of the signal transmitter to transmit a test signal on the bidirectional transmission medium of the TSV. The calibration circuitry then compares a level of the test signal to a range, with different levels within the range corresponding to different logic levels. If the level of the test signal is outside an expected range, a boost circuit is activated to bring the level of the test signal into the expected range.
An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.
An optical communication system includes an optical waveguide and a photodetector (PD). The optical waveguide is arranged to receive and guide an optical signal. The PD is configured to receive the optical signal from the optical waveguide and to convert the optical signal into an electrical signal. The PD includes a stack of layers including at least (i) first layers including two or more semiconductor layers forming a reverse-biased semiconductor junction configured to produce the electrical signal in response to the optical signal impinging thereon, and (ii) second layers forming a capacitance component that in is connected with series the reverse-biased semiconductor junction. The PD further includes a first electrode and a second electrode, configured to (i) apply one or more voltages that reverse-bias the reverse-biased semiconductor junction and (ii) output the electrical signal.
H01L 31/109 - Dispositifs sensibles au rayonnement infrarouge, visible ou ultraviolet caractérisés par une seule barrière de potentiel ou de surface la barrière de potentiel étant du type PN à hétérojonction
A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.
H04B 1/38 - Émetteurs-récepteurs, c.-à-d. dispositifs dans lesquels l'émetteur et le récepteur forment un ensemble structural et dans lesquels au moins une partie est utilisée pour des fonctions d'émission et de réception
26.
Packaging electronic device with liquid thermal interface material
An electronic device includes (i) an integrated circuit (IC) die mounted on a substrate, (ii) a lid having first and second surfaces facing one another, and one or more openings formed through the lid between the first and second surfaces, the lid being disposed over at least the IC die to form a space between the IC die and the first surface of the lid, the one or more openings are configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) filling the space and being formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure extended from the first surface of the lid, the stopper structure includes one or more sidewalls configured to contain the liquid TIM at least in the space between the IC die and the first surface of the lid.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/24 - Matériaux de remplissage caractérisés par le matériau ou par ses propriétes physiques ou chimiques, ou par sa disposition à l'intérieur du dispositif complet solide ou à l'état de gel, à la température normale de fonctionnement du dispositif
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
27.
PACKAGING ELECTRONIC DEVICE WITH LIQUID THERMAL INTERFACE MATERIAL
An electronic device (11) includes (i) an integrated circuit (IC) die (22) mounted on a substrate (25), (ii) a lid (33) having first and second surfaces (32, 34) facing one another, and one or more openings (66) formed through the lid between the first and second surfaces, the lid being disposed over the IC die to form a space (23) between the IC die and the first surface (32) of the lid, the one or more openings configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) (44) filling the space and formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure (54) extended from the first surface of the lid, the stopper structure includes sidewalls (55) configured to contain the liquid TIM at least in the space between the IC die and first surface of the lid.
H01L 23/04 - ConteneursScellements caractérisés par la forme
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
28.
METHOD AND APPARATUS FOR QUIETING TRANSMISSIONS IN A COMMUNICATION NETWORK
A coordinator communication device in a communication network determines that a time period is to begin during which only the coordinator communication device will have opportunities to transmit. The time period includes a plurality of time cycles, each time cycle i) beginning with the coordinator communication device transmitting a beacon signal and ii) including a transmit opportunity that follows the beacon signal. The transmit opportunity is for the coordinator communication device. The coordinator communication device transmits one or more signals to follower communication devices in the communication network to prompt the follower communication devices to refrain from transmitting during the time period. During one or more transmit opportunities of the time period, the coordinator communication device transmits one or more time-sensitive packets.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
An electronic device includes a first integrated circuit (IC) die and a second IC die. The second IC die is mounted on the first IC die. The first IC die includes (i) a first dielectric layer having a first dielectric surface, and (ii) a first pad having a first footprint and a first pad surface, the first pad being electrically conductive and being at least partially embedded in the first dielectric layer. The second IC die includes (i) a second dielectric layer having a second dielectric surface at least partially facing the first dielectric surface, and (ii) a second pad, which is electrically conductive and is at least partially embedded in the second dielectric layer. The second pad has a second footprint, smaller than the first footprint, and a second pad surface electrically coupled to the first pad surface.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
30.
SIGNAL TRACE TRANSITION FOR HIGH DATA RATE APPLICATIONS
Systems, methods, and apparatus are described herein for maintaining high signal integrity and high bandwidth in data transmissions between an integrated circuit package and a PCB. The integrated circuit package has multiple layers. Signal pins for connecting the integrated circuit package, both physically and electrically, to the PCB are located at a first layer. A signal trace is coupled to each signal pin. The signal trace bifurcates into two branches and couples to a given signal pin at the distal end of each branch.
An interface device distributes data from a plurality of input data streams to a smaller number first data streams, and periodically inserts a set of alignment markers (AMs) into the first data streams. After using the AMs, the interface device removes the AMs and reinserts the AMs at particular positions. A forward error correction (FEC) encoder encodes data corresponding to the first data stream to generate FEC codewords and distributes data from the FEC codewords to multiple outputs streams. Within the output streams, the AMs are located at FEC codeword boundaries and bits of a first AM, among the set of AMs, are spread across multiple outputs stream. A single output data stream is generated based on the multiple output streams of the FEC encoder.
H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue
H03M 5/14 - Représentation du code, p. ex. transition, pour un élément binaire donné dépendant de l'information d'un ou de plusieurs éléments binaires adjacents, p. ex. code à modulation de durée, code à double densité
H03M 9/00 - Conversion parallèle/série ou vice versa
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
A memory device includes a plurality of memory cells. Each memory cell stores a plurality of signal levels representing a plurality of values corresponding to a respective plurality of bits, bits in corresponding respective positions of significance across the plurality of memory cells constituting respective memory pages of the memory device. The memory device also includes decoding circuitry to decode each bit value of one of the respective memory pages using bit values read from at least one other one of the respective memory pages, adjacent to the one of the respective memory pages. The plurality of signal levels may represent the plurality of values according to a Gray code. The decoding circuitry may be configured to compare each signal level to a set of voltage thresholds, and to decode a subset of the plurality of signal levels using fewer than all voltage thresholds in the set of voltage thresholds.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
A memory array circuit routes packet data to a destination within the array. The memory array includes memory devices arranged in a plurality of rows and columns, as well as passthrough channels connecting non-adjacent memory devices. Each of the memory devices includes a memory configured to store packet data, and a packet router configured to interface with at least one adjacent memory device of the memory array. The packet router determines a destination address for a packet, and, based on the destination address, selectively forwards the packet to a non-adjacent memory device via a passthrough channel of the plurality of passthrough channels. A memory interface routes the packet from a source to the memory array, and selectively forwarding the packet to one of the plurality of memory devices based on the destination address.
A machine learning (ML) hardware includes a first data format conversion block configured to receive data generated by an application source in a first data format. The first data format conversion block is configured to convert the received data from the first data format into a second data format. The first data format is different from the second data format. The ML hardware includes a plurality of processing units configured to perform one or more ML operations on the data in the second data format to generate a processed data. The ML hardware includes a second data format conversion block configured to convert the processed data to a third data format. The ML hardware further includes a transmitting component configured to output the processed data in the third data format to a memory component for use by an application destination.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
35.
METHOD AND APPARATUS FOR QUIETING TRANSMISSIONS IN A COMMUNICATION NETWORK
A coordinator communication device in a communication network determines that a time period is to begin during which only the coordinator communication device will have opportunities to transmit. The time period includes a plurality of time cycles, each time cycle i) beginning with the coordinator communication device transmitting a beacon signal and ii) including a transmit opportunity that follows the beacon signal. The transmit opportunity is for the coordinator communication device. The coordinator communication device transmits one or more signals to follower communication devices in the communication network to prompt the follower communication devices to refrain from transmitting during the time period. During one or more transmit opportunities of the time period, the coordinator communication device transmits one or more time-sensitive packets.
An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
H04L 7/033 - Commande de vitesse ou de phase au moyen des signaux de code reçus, les signaux ne contenant aucune information de synchronisation particulière en utilisant les transitions du signal reçu pour commander la phase de moyens générateurs du signal de synchronisation, p. ex. en utilisant une boucle verrouillée en phase
37.
Reliable electronic fuse based storage using error correction coding
An apparatus for reliable fuse-based storage in an Integrated Circuit (IC) includes a plurality of electronic fuses and processing logic. The electronic fuses store (i) data bits, (ii) parity bits that were generated from the data bits in accordance with an Error Correction Code (ECC) scheme, and (iii) access information required for accessing the data bits and the parity bits. The processing logic receives a read command for reading given data bits from the electronic fuses, based on the read command retrieves access information specifying given electronic fuses storing the given data bits and given parity bits associated with the given data bits, using the access information reads the given data bits and the given parity bits from the given electronic fuses, applies the ECC scheme to the given data bits and the given parity bits, using the ECC module to generate corrected data bits, and outputs the corrected data bits.
G11C 29/54 - Dispositions pour concevoir les circuits de test, p. ex. outils de conception pour le test [DFT]
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A circuit and corresponding method employ directional link (DL) credit pools. The circuit comprises the DL credit pools and transmit (TX) port logic. The DL credit pools are associated with neighboring node (NBN) TX ports of a NBN on a chip. The NBN is coupled to a node on the chip via the circuit. The node includes the circuit. The TX port logic admits a received packet to the circuit based on routing information in the received packet and produces a TX packet by updating the routing information, in the received packet admitted, to indicate a NBN TX port of the NBN TX ports. The TX port logic transmits the TX packet produced to the NBN based on a DL credit pool of the DL credit pools that is associated with the NBN TX port indicated. Use of the DL credit pool mitigates head-of-line blocking under bursty traffic conditions.
A system and corresponding method queue work within a virtualized scheduler based on in-unit accounting (IUA) of in-unit entries (IUEs). The system comprises an IUA resource and arbiter. The IUA resource stores, in association with an IUA identifier, an IUA count and threshold. The IUA count represents a global count of work-queue entries (WQEs) that are associated with the IUA identifier and occupy respective IUEs of an IUE resource. The IUA threshold limits the global count. The arbiter retrieves the IUA count and threshold from the IUA resource based on the IUA identifier and controls, as a function of the IUA count and threshold, whether a given WQE from a given scheduling group, assigned to the IUA identifier, is moved into the IUE resource to be queued for scheduling. The IUA count and threshold prevent group(s) assigned to the IUA identifier from using more than an allocated amount of IUEs.
An Ethernet Physical Layer (PHY) device includes a link interface and a transceiver. The link interface is configured to connect to a full-duplex wired Ethernet link. The transceiver is configured to receive first Ethernet signals carrying first data at a first data rate over the Ethernet link in a first direction, the first Ethernet signals occupying a first frequency band, and to transmit second Ethernet signals carrying second data at a second data rate different from the first data rate, over the Ethernet link in a second direction that is opposite the first direction, the second Ethernet signals occupying a second frequency band that is different from f the first frequency band.
H04L 5/14 - Fonctionnement à double voie utilisant le même type de signal, c.-à-d. duplex
H04B 3/23 - Réduction des effets d'échos ou de sifflementSystèmes à ligne de transmission Détails ouverture ou fermeture de la voie d'émissionCommande de la transmission dans une direction ou l'autre utilisant une reproduction du signal transmis décalée dans le temps, p. ex. par dispositif d'annulation
H04L 7/04 - Commande de vitesse ou de phase au moyen de signaux de synchronisation
41.
System and Method for Neural Network-Based Autonomous Driving
A system and corresponding method for autonomous driving of a vehicle are provided. The system comprises at least one neural network (NN) that generates at least one output for controlling the autonomous driving. The system further comprises a main data path that routes bulk sensor data to the at least one NN and a low-latency data path with reduced latency relative to the main data path. The low-latency data path routes limited sensor data to the at least one NN which, in turn, employs the limited sensor data to improve performance of the at least one NN's processing of the bulk sensor data for generating the at least one output. Improving performance of the at least one NN's processing of the bulk sensor data enables the system to, for example, identify a safety hazard sooner, enabling the autonomous driving to divert the vehicle and avoid contact with the safety hazard.
B60W 50/04 - Détails des systèmes d'aide à la conduite des véhicules routiers qui ne sont pas liés à la commande d'un sous-ensemble particulier pour surveiller le fonctionnement du système d'aide à la conduite
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
An optical communication device includes a laser, a transmitter (Tx), a receiver (Rx) and a device controller. The laser is configured to generate an optical carrier. The transmitter is configured to generate an optical Tx signal using the optical carrier and to transmit the optical Tx signal to a peer optical communication device. The receiver is configured to receive an optical Rx signal from the peer optical communication device, and to down-convert the optical Rx signal using the optical carrier. The device controller is configured to adjust a frequency of the laser to reduce a Carrier Frequency Offset (CFO) between the received optical Rx signal and the optical carrier generated by the laser, including conditionally applying to a frequency of the laser a series of frequency hops in accordance with a defined dithering sequence.
A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.
Methods and apparatus for job scheduling in a programmable mixed-radix DFT/IDFT processor. In one embodiment, a system for processing network data from a wireless communications network includes a vector pipeline, a programmable mixed radix engine, and a job scheduler. The vector pipeline is configured to scale, stage, and multiply twiddle factor to vector data from a mega-job. The programmable mixed radix engine is configurable for computing jobs bundled in the mega-job in accordance with a DFT of a particular point size. The job scheduler is operable to bundle multiple discrete Fourier transform (DFT) jobs having a substantially same point size into the mega-job after obtaining the DFT jobs.
Two pointers are initialized. The first pointer is incremented every M cycles of a monitored clock and the second pointer is incremented every N cycles of a reference clock, where M and N are determined from a frequency relationship between the clocks. If the positions of the pointers are determined to differ by more than a drift threshold, an error is detected and corrective action may be taken.
Data read from a storage medium is first processed through a first data path including a first decoder configured to decode data output from at least one first finite impulse response (FIR) filter and first FIR adaptation circuitry configured to adjust a first FIR coefficient for the at least one first FIR filter. The data is then processed through a second data path, which includes at least one second FIR filter and second FIR adaptation circuitry configured to adjust a second FIR coefficient to reach an FIR coefficient that achieves a target minimum number of errors. The second FIR adaptation circuitry is configured to reach the FIR coefficient that achieves the target minimum number of errors faster than the first FIR adaptation circuitry. A second decoder in the second data path is configured to decode data output by the at least one second FIR filter.
A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.
H04L 29/06 - Commande de la communication; Traitement de la communication caractérisés par un protocole
G06Q 20/06 - Circuits privés de paiement, p. ex. impliquant de la monnaie électronique utilisée uniquement entre les participants à un programme commun de paiement
G06Q 20/38 - Protocoles de paiementArchitectures, schémas ou protocoles de paiement leurs détails
G06Q 20/40 - Autorisation, p. ex. identification du payeur ou du bénéficiaire, vérification des références du client ou du magasinExamen et approbation des payeurs, p. ex. contrôle des lignes de crédit ou des listes négatives
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
An optoelectronic device includes a gain medium having first and second ends and configured to amplify laser radiation within a gain band having a peak at a given wavelength. A laser cavity, containing the gain medium, includes a first reflector disposed on a first side of the gain medium and a second reflector disposed on a second side of the gain medium, opposite the first side. The second reflector has a reflectance as a function of wavelength that is tunable so as to reduce a reflectance of the second reflector at the peak of the gain band, thereby broadening a spectrum of the laser radiation emitted from the gain medium through the second reflector.
H01S 5/10 - Structure ou forme du résonateur optique
H01S 3/105 - Commande de l'intensité, de la fréquence, de la phase, de la polarisation ou de la direction du rayonnement, p. ex. commutation, ouverture de porte, modulation ou démodulation par commande de la position relative ou des propriétés réfléchissantes des réflecteurs de la cavité
A system and corresponding method integrate a payment application and at least one payment hardware system module (HSM). The system comprises a payment system interface (PSI) interposed between a payment application and at least one payment hardware system module (HSM). The PSI implements a standard, payment HSM application programming interface (API) that is payment HSM vendor-agnostic. The PSI enables communication between the payment application and the at least one payment HSM based on the standard, payment HSM API implemented. Since the standard, HSM payment API is payment HSM vendor-agnostic, development effort otherwise expended to develop a connector for each vendor payment HSM integration is avoided.
G06Q 20/34 - Architectures, schémas ou protocoles de paiement caractérisés par l'emploi de dispositifs spécifiques utilisant des cartes, p. ex. cartes à puces ou cartes magnétiques
50.
Digital timing recovery in hard disk drive read channel for preamble reduction
A method of reading data from a rotating magnetic storage medium, having at least one read head, includes storing respective digitized data samples from each respective read head of the at least one read head in a respective timing buffer, determining a zero-phase start phase angle from a preamble of the digitized data samples, feeding forward the zero-phase start phase angle to an interpolator, selecting an interpolation filter based on the fed-forward zero-phase start phase angle, releasing the respective digitized data from the respective timing buffer after a duration sufficient for completion of the determining, the feeding forward and the selecting, and interpolating samples of the digitized data released from the respective timing buffer.
A first photonics integrated circuit (PIC) chip originates from a PIC wafer. The first PIC chip includes a substrate, and one or more optical communication components fabricated on the substrate. Optical testing components are also fabricated on the substrate. The optical testing components are configured to, prior to die singulation of the PIC wafer, transfer light to a second PIC chip on the PIC wafer for testing one or more operational attributes of optical components disposed on the second PIC chip Prior to die singulation of the PIC wafer, the second PIC chip was adjacent to the first PIC chip on the PIC wafer.
A method for writing data to a magnetic data storage medium includes detecting whether the duration, before occurrence of a data transition, of data to be written exceeds a predetermined threshold, and, when the duration, before the occurrence of the data transition, of the data to be written exceeds the predetermined threshold, writing the data by applying an initial pulse and then maintaining a steady-state write current for a defined interval, and when the duration, before the occurrence of the data transition, of the data to be written is at most equal to the predetermined threshold, writing the data by applying the initial pulse without applying a steady-state write current before the data transition. The predetermined threshold may be determined by size of a magnetic bubble formed when writing a single bit to the magnetic data storage medium. A subsequent pulse may be applied following the defined interval.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/012 - Enregistrement, reproduction ou effacement sur des disques magnétiques
A method for digital timing recovery from oversampled analog signals includes computing filter coefficients for digitized samples of the oversampled analog signals based on an oversampling factor of the oversampled analog signals, using the filter coefficients in a rotation filter to compensate for the oversampling factor in the digitized samples of the oversampled analog signals, deriving a starting phase and magnitude from the compensated digitized samples of the oversampled analog signals, and using the starting phase and magnitude in a timing recovery loop to recover a clock from the compensated digitized samples of the oversampled analog signals. The rotation filter may include a plurality of taps, and the circuitry may be configured to compute respective sets of coefficients for respective taps. Each set of coefficients may be dependent on another set of coefficients, or the coefficients may be approximate with each set of approximate coefficients being independent.
A method for fabricating an electronic device having two or more stacked integrated circuit (IC) dies, the method includes, disposing a first IC die on a substrate. A registration error of the first IC die between (i) a first intended position of the first IC die on the substrate, and (ii) a first actual position of the first IC die on the substrate, is determined. A second IC die is stacked on the first IC die, and at least part of the registration error of the first IC die is compensated for by shifting the second IC die, from a second intended position to a second actual position.
A network device, for use in an automotive network, includes a semiconductor die, network-device circuitry and an on-chip traffic monitor. The network-device circuitry is disposed on the die and is configured to transfer traffic of the automotive network. The on-chip traffic monitor is disposed on the die and is configured to monitor the traffic traversing the network-device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect a performance degradation in the network-device circuitry by analyzing the monitored traffic.
A silicon photonics communications device, configured for fastening thereto a fitting of an optical fiber cable, includes an integrated circuit structure having optical transducers thereon and having a first surface, and a fastening block having a bonding area of a block surface bonded to the first surface and having a cantilevered arm having a cantilever surface parallel to the first surface. The cantilever surface is configured for bonding to the fitting at a cantilever area at least as large as the bonding area, and is spaced away from the block surface by a step distance to accommodate alignment of the fitting to the optical transducers. Where the optical transducers are on a second surface perpendicular to the first surface, the arm extends beyond the second surface, and holds an end face of the fitting, at which ends of optical fibers are exposed, adjacent to the optical transducers.
A network device (18), for use in an automotive network (20), includes a semiconductor die, network-device circuitry and an on-chip traffic monitor (76). The network-device circuitry is disposed on the die and is configured to transfer traffic of the automotive network. The on-chip traffic monitor is disposed on the die and is configured to monitor the traffic traversing the network-device circuitry from one or more sources in the automotive network to one or more destinations in the automotive network, and to detect a performance degradation in the network-device circuitry by analyzing the monitored traffic.
H04L 43/026 - Capture des données de surveillance en utilisant l’identification du flux
H04L 43/028 - Capture des données de surveillance en filtrant
H04L 43/062 - Génération de rapports liés au trafic du réseau
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
A method for cancelling, from servo signals read in a read channel while a write channel is active, interference caused by write signals in the write channel, includes generating a predicted channel response signal from the write signals in a data clock domain, resampling the generated predicted channel response signal using a clock in the data clock domain having a rate corresponding to a servo clock from a servo clock domain, transferring the resampled predicted channel response signal from the data clock domain to the servo clock domain and aligning phase of the transferred resampled predicted channel response signal with phase of the servo clock, determining a domain-boundary-crossing delay incurred in the transferring, based on the domain-boundary-crossing delay, synchronizing the phase-aligned transferred resampled predicted channel response signal with the servo signals, and subtracting the synchronized phase-aligned transferred resampled predicted channel response signal from the servo signals.
A storage system including a plurality of HDDs, a cooling system, and a system controller is provided. Each of the plurality of HDDs includes a disk, a write head configured to write data to the disk, a microphone, an HDD controller configured to process a signal from the microphone determine noise detected by the microphone, and a housing that houses the disk, the write head, the microphone, and the HDD controller. The cooling system is configured to cool the plurality of the HDDs. The system controller is configured to receive data corresponding to the determined noise detected by the microphones of each of the plurality of HDD, and control a cooling level of the cooling system based on the received data and acoustic noise information associated with each of the plurality of HDDs. A method for operating the storage system is also provided.
A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
61.
System and method for generating multiple platform-dependent instruction sets from single hardware specification
A new approach of systems and methods to support automatic generation of multiple platform-dependent instruction sets from a single specification of an integrated circuit (IC). First, a specification compiler accepts as input a first instruction set of a plurality of first instructions in a specification format, wherein the first instruction set defines a design pattern of one or more specifications and/or requirements of the IC and is independent of any implementation or platform of the IC. The design tool then converts the first instruction set into a second instruction set of a plurality of second instructions in an intermediate format. A language compiler then accepts and compiles the second instruction set into a plurality of third instruction sets, wherein each of the plurality of third instruction sets comprises a plurality of third instructions in a specific language for a specific platform targeting a specific implementation or application of the IC.
An optical transceiver includes a silicon photonics substrate and multiple devices. The devices are configured to process optical signals propagating to and from the optical transceiver, and to perform at least one of an optical-to-electrical conversion of received optical signals to incoming electric signals and an electrical-to-optical conversion of outgoing electric signals to transmitted optical signals. The devices are each fabricated to include respectively a package substrate configured according to one of multiple different package substrate mounting technologies. Each package substrate among the multiple devices is mounted on the silicon photonics substrate according to mounting requirements of the respective package substrate mounting technology of that package substrate. At least two of the package substrates are mounted according to the mounting requirements of different package substrate mounting technologies.
B60G 15/02 - Suspensions élastiques caractérisées par la disposition, l'emplacement ou le type de combinaison de ressorts et d'amortisseurs de vibrations, p. ex. du type télescopique ayant un ressort mécanique
B60G 21/05 - Systèmes d'interconnexion à plusieurs roues conjuguées suspendues élastiquement, p. ex. pour stabiliser la caisse du véhicule eu égard aux forces d'accélération, de décélération ou aux forces centrifuges conjuguées en permanence mécaniquement entre roues appartenant au même essieu, mais n'étant pas disposées du même côté du véhicule, c.-à-d. la suspension de la roue gauche étant reliée à celle de la roue droite
G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques
G02F 1/313 - Dispositifs de déflexion numérique dans une structure de guide d'ondes optique
H01S 5/02 - Détails ou composants structurels non essentiels au fonctionnement laser
H01S 5/0234 - Montage à orientation inversée, p. ex. puce retournée [flip-chip], montage à côté épitaxial au-dessous ou montage à jonction au-dessous
H01S 5/12 - Structure ou forme du résonateur optique le résonateur ayant une structure périodique, p. ex. dans des lasers à rétroaction répartie [lasers DFB]
63.
Automotive data processing system with efficient generation and exporting of metadata
An automotive data processing system includes a storage subsystem and a processor. The storage subsystem is disposed in a vehicle and is configured to store at least data produced by one or more data sources of the vehicle. The processor is installed in a vehicle and is configured to apply, to the data stored in the storage subsystem or that is en route to be stored in the storage subsystem, at least one model that identifies one or more specified features-of-interest in the data, so as to generate metadata that tags occurrences of the specified features-of-interest in the stored data, and to export at least part of the metadata to an external system that is external to the vehicle.
G07C 5/08 - Enregistrement ou indication de données de marche autres que le temps de circulation, de fonctionnement, d'arrêt ou d'attente, avec ou sans enregistrement des temps de circulation, de fonctionnement, d'arrêt ou d'attente
A method for operation of a first communication device in a wireless local area network (WLAN) communication channel, having a plurality of component channels, between the first communication device and a second communication device is described. A first physical layer (PHY) protocol data unit (PPDU) and a second PPDU, distinct from the first PPDU, are generated. The first PPDU and second PPDU are transmitted simultaneously to the second communication device over the WLAN communication channel, including: transmitting the first PPDU via a first component channel within a first radio frequency (RF) channel segment that occupies a first frequency bandwidth, and transmitting the second PPDU via a second component channel within a second RF channel segment that occupies a second frequency bandwidth that does not overlap the first frequency bandwidth segment, and is separated from the first frequency bandwidth segment by a frequency gap.
A network device obtains measurement data for one or more device attributes or environmental factors, and compares the measurement data to respective ranges specified for the device attributes or the environmental factors. Different ranges for the device attributes or the environmental factors are associated with different operating regions (OREs) classified for the device. The operating state of the network device corresponds to a first ORE of the different OREs, and various tasks performed by the device in the operating state are based on configurations specified by the first ORE. Based on comparing the measurement data, the network device identifies a second ORE that includes ranges for the device attributes or the environmental factors that match the measurement data. The network device transitions the operating state to correspond to the second ORE, and adjusting the tasks performed by the device according to configurations specified by the second ORE.
A network device includes ingress queues for storing data units while the data units are being processed by ingress packet processors, and a plurality of egress buffer memories for storing data units received from the ingress queues while the data units are being processed by the egress packet processors. First circuitry controls respective rates at which data units are transferred from ingress queues to egress buffer memories. Second circuitry monitors the egress buffer memories for congestion and sends, to the first circuitry, flow control messages related to congestion resulting of egress buffer memories. The first circuitry progressively increases over time a rate at which data from each ingress queue are transferred to an egress buffer memory in response to receiving a flow control message that indicates that congestion corresponding to the egress buffer memory has ended.
H04L 47/25 - Commande de fluxCommande de la congestion le débit étant modifié par la source lors de la détection d'un changement des conditions du réseau
A communication network includes first switches interconnected with second switches. Each first switch includes a first integrated circuit (IC) switch chip, downlink ports, and uplink ports. Each second switch includes ports coupled to at least one uplink port of each of the first switches, and a second IC switch chip in an IC package. To permit each second IC switch chip to forward packets amongst a large number of first switches and to reduce a number of external interconnects of the IC package, each second IC switch chip includes sets of multiplexer/demultiplexer circuitry, each multiplexer/demultiplexer circuitry being coupled between an external interconnect, and a set of multiple internal network interfaces of the second IC switch chip. The multiplexer/demultiplexer circuitry demultiplexes a data stream from the external interconnect to multiple internal network interfaces, and multiplexes multiple data streams from the multiple internal network interfaces to the external interconnect.
H04L 49/111 - Interfaces de commutation, p. ex. détails de port
H04L 49/109 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p. ex. interrupteurs sur puce
A communication network includes first switches interconnected with second switches. Each first switch includes a first integrated circuit (IC) switch chip, downlink ports, and uplink ports. Each second switch includes ports coupled to at least one uplink port of each of the first switches, and a second IC switch chip in an IC package. To permit each second IC switch chip to forward packets amongst a large number of first switches and to reduce a number of external interconnects of the IC package, each second IC switch chip includes sets of multiplexer/demultiplexer circuitry, each multiplexer/demultiplexer circuitry being coupled between an external interconnect, and a set of multiple internal network interfaces of the second IC switch chip. The multiplexer/demultiplexer circuitry demultiplexes a data stream from the external interconnect to multiple internal network interfaces, and multiplexes multiple data streams from the multiple internal network interfaces to the external interconnect.
H04L 49/109 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p. ex. interrupteurs sur puce
H04L 49/15 - Interconnexion de modules de commutation
An automotive network system in a vehicle includes one or more non-compliant network switches, one or more validation data collectors, and a safety validator. The non-compliant network switches are installed in the vehicle but are not compliant with specified vehicle-safety requirements. The non-compliant network switches are configured to receive, process and send packets. The validation data collectors are coupled to the non-compliant network switches and are configured to derive validation data from at least some of the packets traversing the network switches. The safety validator is configured to verify whether the non-compliant network switches function in a manner that in actuality is compliant with the vehicle-safety requirements based on the validation data collected by the one or more validation data collectors.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
70.
Synchronized Control of Sensors in an Ethernet Network
An apparatus for controlling sensors over a network includes a transceiver and a processor. The transceiver is configured to communicate over the network. The processor is configured to generate a first packet including a first timestamp destined to a first sensor, and generate a second packet including a second timestamp destined to a second sensor. The first and second timestamps are indicative of first and second future times that are set to synchronize operation of the first and second sensors. The processor is further configured to send the first and second packets to the network.
Methods and systems provide for fault diagnosis in a vehicular communication network. The methods and systems utilize a trained neural network model which is downloaded to a local computer associated with the vehicular communication network of a given vehicle and which applies inputs from the given vehicle to output maintenance recommendations for the given vehicle.
G07C 5/00 - Enregistrement ou indication du fonctionnement de véhicules
G06N 3/04 - Architecture, p. ex. topologie d'interconnexion
G07C 5/08 - Enregistrement ou indication de données de marche autres que le temps de circulation, de fonctionnement, d'arrêt ou d'attente, avec ou sans enregistrement des temps de circulation, de fonctionnement, d'arrêt ou d'attente
72.
Machine Learning-Enabled Queue Management for Network Devices
The present disclosure describes apparatuses and methods for machine learning-enabled (ML-enabled) queue management for network devices. In some aspects, an ML-enabled queue manager of a network device initializes a queue management setting with a randomized value and the device processes packets through the queue based on the queue management setting. The ML-enabled queue manager measures a performance metric of the queue and provides, to an ML algorithm, an indication of the queue management setting and an indication of the performance metric of the queue. The ML-enabled queue manager then receives, from the machine learning algorithm, an updated queue management setting and configures the queue with the updated queue management setting to process subsequent packets based on the updated queue management setting. By so doing, the ML-enabled queue manager may tune one or more queue management settings of the queue to optimize performance of the network device.
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 47/32 - Commande de fluxCommande de la congestion en supprimant ou en retardant les unités de données, p. ex. les paquets ou les trames
A method of testing an integrated circuit device that includes components of first and second types, where the components of the second type consume power when clocked even when not active, includes gating off the clock signal to prevent clock signals from reaching the components of the second type, and applying test inputs to the components of the first type. Gating off the clock signals to the components of the second type may include preventing the clock signals from reaching individual components of the second type, or preventing the clock signals from reaching each clock tree branch that contains only components of the second type, or, when a clock tree serving the components of the second type supplies clock signals only to the components of the second type, preventing the clock signals from reaching the clock tree.
A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0897 - Mémoires cache caractérisées par leur organisation ou leur structure avec plusieurs niveaux de hiérarchie de mémoire cache
75.
Method and apparatus for self-destruction of device protected by a physical unclonable function generator
University of Vermont and State Agricultural College (USA)
Inventeur(s)
Hunt-Schroeder, Eric
Xia, Tian
Abrégé
A method for preventing unauthorized access to information in a semiconductor device that is secured with a security protocol that uses a first portion of the information may include in response to a verified inaccessibility-inducing signal, unlocking safety lock circuitry which is operable to prevent unintentional activation of self-destruction in the semiconductor device, and initiating the self-destruction of at least a portion of the semiconductor device. A semiconductor device is configured to prevent unauthorized access to information available therein that is secured with a security protocol that uses a first portion of the information. The semiconductor device may include safety lock circuitry operable to prevent unintentional activation of self-destruction in the semiconductor device and control circuitry operable to unlock the safety lock circuitry and to initiate the self-destruction of at least a portion of the semiconductor device in response to a verified inaccessibility-inducing signal.
H03K 17/60 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors bipolaires
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
76.
Media access control for frequency division full duplex in WLAN
A first communication device in a wireless local area network (WLAN) receives a communication frame from a second communication device. The communication frame includes one or more indications of one or more FDFD parameters for an FDFD operation that includes FDFD communications via a first frequency segment and a second frequency segment. The one or more indications includes an indication of a physical layer (PHY) transmission mode that the first communication device is to use for communication in the second frequency segment during the FDFD operation. The first communication device uses the indication of the PHY transmission mode to determine a PHY transmission mode that the first communication device is to use for communication in the second frequency segment during the FDFD operation, and transmits in the second frequency segment according to the PHY transmission mode.
An electronic device includes (i) a substrate having a first coefficient of thermal expansion (CTE), (ii) an integrated circuit (IC) die formed on the substrate and including first metal layers having a first thickness, and second metal layers having a second thickness, greater than the first thickness, the second metal layers have a second CTE, greater than the first CTE, the first and second metal layers are configured to induce, in response to an increase in a temperature of the electronic device, a first stress that acts to cause a warpage at least in the substrate, and (iii) a dielectric layer having a third CTE less than the first and second CTEs, is (a) disposed on the second metal layers, and (b) configured to induce at least in the substrate, in response to the increase in the temperature, a second stress that compensates for at least part of the warpage.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
78.
CUSTOMIZED HEAT DISSIPATION FROM DIFFERENT TYPES OF INTEGRATED CIRCUIT DIES PACKAGED ON A COMMON SUBSTRATE
An electronic device (11, 21, 31) includes: (i) first and second integrated circuit (IC) dies (44, 33) co-located on a surface of a substrate (32) in proximity to each other, (ii) a heat sink (12) disposed on the first and second IC dies, and (iii) a lid (22), which is disposed between the first IC die (44) and the heat sink (12), and the lid (22) is not disposed between the second IC die (33) and the heat sink (12).
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
79.
Customized heat dissipation from different types of integrated circuit dies packaged on a common substrate
An electronic device includes: (i) first and second integrated circuit (IC) dies co-located on a surface of a substrate in proximity to each other, (ii) a heat sink disposed on the first and second IC dies, and (iii) a lid, which is disposed between the first IC die and the heat sink, and the lid is not disposed between the second IC die and the heat sink.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A method of clocking a data channel of a storage device includes generating a single time-base frequency signal, deriving from the single time-base frequency signal, using a plurality of frequency-modification techniques, a plurality of individual clock signals, each respective one of the individual clock signals being for clocking a respective one of reading, writing and servo functions of the data channel. When the storage device is a disk storage device having a rotational frequency, generating a single time-base frequency signal may include generating a time-base frequency signal based on the rotational frequency. Deviation of the single time-base frequency from the rotational frequency may be detected, and the deviation may be compensated for. Each technique of the frequency-modification techniques may be a digital frequency-modification technique, such as a digital timing recovery technique or a digital frequency division technique.
H04L 7/00 - Dispositions pour synchroniser le récepteur avec l'émetteur
G11B 20/14 - Enregistrement ou reproduction numériques utilisant des codes auto-synchronisés
H03L 7/087 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie utilisant au moins deux détecteurs de phase ou un détecteur de fréquence et de phase dans la boucle
81.
Method and apparatus for efficient address decoding and address usage reduction
A method includes synthesizing a hardware description language (HDL) code into a netlist comprising a first a second and a third components. The method further includes allocating addresses to each component of the netlist. Each allocated address includes assigned addresses and unassigned addresses. An internal address space for a chip is formed based on the allocated addresses. The internal address space includes assigned addresses followed by unassigned addresses for the first component concatenated to the assigned addresses followed by unassigned addresses for the second component concatenated to the assigned addresses followed by unassigned addresses for the third component. An external address space for components outside of the chip is generated that includes only the assigned addresses of the first component concatenated to the assigned addresses of the second component concatenated to the assigned addresses of the third component. Internal addresses are translated to external addresses and vice versa.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Port parameters corresponding to a port of a network switching unit are received at one or more processing chips in the network switching unit. Both (i) serializer/deserializer (SerDes) parameters corresponding to the port, and (ii) transceiver parameters corresponding to the port, are obtained from a local storage based on the port parameters by the one or more processing chips. Signal processing operations of a SerDes unit are configured by the one or more processing chips using the SerDes parameters. The transceiver parameters are provided to a local platform of the network switching unit, for configuration, using the transceiver parameters, of a transceiver communicatively coupled to the port. The signal processing operations are performed by the SerDes unit, according to the SerDes parameters, on a signal received at the SerDes unit from the transceiver or on a signal transmitted from the SerDes unit to the transceiver.
The present disclosure describes aspects of codeword interleaving over magnetic media surfaces. In some aspects, segments of a codeword are spread or interleaved across multiple surfaces of magnetic storage media. Data for one or more codewords may be received by a read/write channel and, for each codeword, a respective index is selected, received, or generated. The index may indicate which sector partitions of the multiple surfaces that segments of one of the codewords are to be written. The data of the codewords can be segmented and then arranged in an interleaver based on the respective index to which the codeword corresponds. The codeword segments are written from the interleaver to sectors of the multiple surfaces of the magnetic media. By so doing, codewords may be spread across multiple surfaces, such that a loss of a portion of a segment track does not prevent readback and decoding of the codewords.
In a system with multiple host computers and one or more single-port non-volatile memory devices, a non-volatile memory switch receives memory transaction messages from different root complexes corresponding to the multiple host computers. Each of at least some of the memory transaction messages includes a host identifier that identifies a root complex from which the memory transaction was received. The non-volatile memory switch generates modified memory transaction messages at least by changing host identifiers within memory transaction messages to a common value indicative of a single root complex to present to the one or more single-port non-volatile memory devices the different root complexes as the single root complex. The non-volatile memory switch maintains associations of memory transaction messages with corresponding ones of the different root complexes, and sends the modified memory transaction messages to the one or more single-port non-volatile memory devices.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G11C 29/02 - Détection ou localisation de circuits auxiliaires défectueux, p. ex. compteurs de rafraîchissement défectueux
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
85.
System and method for systematic generation of test cases used to validate memory coherence of a multiprocessor system
A new approach is proposed to support systematic generation of a set of test cases/stimuli used to validate a multiprocessor system having a plurality of processors that supports memory coherence. A pair of two of the plurality of processors is first selected for testing one pair at a time, wherein a first of the pair is a requester requesting access to a cache associated with a second of the pair, which is a snooped requester. The test cases are automatically generated based on an algorithm-driven script, wherein the set of test cases includes an instruction set and all valid combinations of cache states of the processors. The instruction set is then executed by the pair of processors to validate memory coherence of the pair of processors. The above process is repeated so that each processor of the plurality of processors is included for memory coherence testing at least once.
A system and method for splitting a machine learning (ML) graph is disclosed. The system includes a compiler configured to receive an ML model. The compiler generates a graph associated with the ML model, wherein the graph is an internal representation of the ML model. The graph is partitioned into a first subgraph and a second subgraph. The first subgraph is associated with an ML hardware, an ML emulator, or a combination thereof, and the second subgraph is associated with a processor different from the ML hardware. A set of low-level instructions associated with the first subgraph is generated. One or more resources in the ML hardware is identified to execute the set of low-level instructions associated with the first subgraph.
A communication device maintains a first backoff counter that corresponds to a first channel segment, and a second backoff counter that corresponds to a second channel segment. The communication device determines whether the communication device is permitted to transmit via the first channel segment simultaneously with receiving via the second channel segment. In response to determining that the communication device is not permitted to transmit via the first channel segment simultaneously with receiving via the second channel segment, the communication device suspends the second backoff counter when transmitting via the first channel segment. In response to determining that the communication device is permitted to transmit via the first channel segment simultaneously with receiving via the second channel segment, the communication device counts the second backoff counter while transmitting via the first channel segment.
A first communication device transmits an NDP to a second communication device simultaneously with transmission of one or more other NDPs by the one or more third communication devices. Then, the first communication device receives a data unit that includes respective beamforming feedback data units for respective ones of the second communication device and the one or more third communication devices. The beamforming feedback data units include an aggregate media access control protocol data unit (A-MPDU) that includes a plurality of fragments of beamforming training information for the first communication device. The beamforming training information in the A-MPDU is generated by the second communication device based on the set of one or more training signals included in the NDP transmitted by the first communication device.
H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
A communication device generates a first packet to include a first indication of one or more first frequency subchannels in a first frequency segment that will be utilized to transmit the first packet. The communication device also generates a second packet to include a second indication of one or more second frequency subchannels in a second frequency segment that will be utilized to transmit the second packet. The communication device simultaneously transmits the first packet via the first frequency segment and the second packet via the second frequency segment.
H04W 72/0453 - Ressources du domaine fréquentiel, p. ex. porteuses dans des AMDF [FDMA]
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal
H04L 69/22 - Analyse syntaxique ou évaluation d’en-têtes
H04L 101/622 - Adresses de couche 2, p. ex. adresses de contrôle d'accès au support [MAC]
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
H04W 84/12 - Réseaux locaux sans fil [WLAN Wireless Local Area Network]
90.
Method and apparatus for correlating high-level code with low-level instructions for machine learning applications
A new approach is proposed to support correlating high-level code with low-level instructions of an application running on a hardware. A compiler that compiles a high-level function in the high-level code of the application into a set of low-level instructions to be executed on the hardware is configured to utilize one or more reserved fields of the set of low-level instructions to incorporate one or more IDs and an actionable item. The IDs are mapped to the high-level function, wherein such mapping is programmable by the compiler. Based on the mapped IDs and the actionable item incorporated in the set of the low-level instructions, the runtime performance of the application on the hardware can be monitored and profiled and issues related to the high-level code of the application can be identified for debugging purposes.
A programmable hardware system for machine learning (ML) operations includes a core and an inference engine. The core receives commands from a host. The commands are in a first instruction set architecture (ISA) format. The core divides the commands into a first set for performance-critical operations, in the first ISA format, and a second set of performance non-critical operations, in the first ISA format. The core executes the second set to perform the performance non-critical operations of the ML operations and streams the first set to inference engine. The inference engine generates a stream of the first set of commands in a second ISA format based on the first set of commands in the first ISA format. The first set of commands in the second ISA format programs components within the inference engine to execute the ML operations to infer data.
G06N 20/10 - Apprentissage automatique utilisant des méthodes à noyaux, p. ex. séparateurs à vaste marge [SVM]
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06N 5/04 - Modèles d’inférence ou de raisonnement
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
92.
Methods and devices for communicating in a wireless network with multiple virtual access points
A communication device associated with a physical access point (AP) receives a physical layer (PHY) data unit having a PHY preamble, which includes a basic service set (BSS) color identifier. The communication device performs a clear channel assessment (CCA) procedure to determine whether the communication device can perform a spatial reuse transmission during reception of the PHY data unit, including: determining whether the BSS color identifier is a color value corresponding to all of multiple virtual APs implemented by the physical AP, and selectively determining whether the communication device can perform the spatial reuse transmission during reception of the PHY data unit as a function of the determination of whether the BSS color identifier is the color value corresponding to all of the multiple virtual APs implemented by the physical AP.
H04W 74/0816 - Accès non planifié, p. ex. ALOHA utilisant une détection de porteuse, p. ex. accès multiple par détection de porteuse [CSMA] avec évitement de collision
H04B 7/0452 - Systèmes MIMO à plusieurs utilisateurs
H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission
H04W 4/06 - Répartition sélective de services de diffusion, p. ex. service de diffusion/multidiffusion multimédiaServices à des groupes d’utilisateursServices d’appel sélectif unidirectionnel
H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
A network device generates one or more search keys to include information retrieved from one or more fields in a header of a packet being processed by the network device. The network device performs a first-stage search in a first-stage memory to map the one or more search keys to one or more search key identifiers. Respective ones of the one or more search key identifiers are shorter than corresponding ones of the one or more search keys. The network device also performs a second-stage search in a second-stage memory based on a combination of the one or more search key identifiers to identify an entry that matches the combination of the one or more search key identifiers. The entry indicates a processing rule matched by the packet. The network device performs, with respect to the packet, an action associated with the rule.
A network device generates one or more search keys to include information retrieved from one or more fields in a header of a packet being processed by the network device. The network device performs a first-stage search in a first-stage memory to map the one or more search keys to one or more search key identifiers. Respective ones of the one or more search key identifiers are shorter than corresponding ones of the one or more search keys. The network device also performs a second-stage search in a second-stage memory based on a combination of the one or more search key identifiers to identify an entry that matches the combination of the one or more search key identifiers. The entry indicates a processing rule matched by the packet. The network device performs, with respect to the packet, an action associated with the rule.
A client station receives a first data unit from an access point (AP) of a wireless local area network (WLAN). The first data unit includes a first WLAN management frame having an indication that the AP is operating in a plurality of frequency segments. The first WLAN management frame includes respective MAC addresses utilized by the AP for operation in the respective frequency segments. Responsive to receiving the first WLAN management frame, the client station generates a second WLAN management frame. The second WLAN management frame includes, for each of multiple frequency segments among the plurality of frequency segments, respective operation information indicating respective operation parameters of the client station for the respective frequency segment. The client station transmits a second data unit having the second WLAN management frame in connection with establishing communication with the AP using the multiple frequency segments.
A first communication device receives a set of bits for transmission over a plurality of lanes of an optical communication link. The optical communication link includes a larger number of lanes than a number of lanes needed to support transmission at a particular clock rate to provide a maximum speed supported by the optical communication link. The first communication device multiplexes the set of data bits for transmission over respective lanes and transmits the multiplexed set of bits over the lanes to a second communication device. The first communication device uses the larger number of lanes for transmission of error correction code bits in addition to the set of bits at the particular clock rate over the plurality of lanes at the maximum speed supported by the optical communication link and/or uses the larger number of lanes to provide one or more redundancy lanes in the optical communication link.
An electronic network device includes: (i) an integrated circuit (IC) die disposed on a substrate and configured to exchange signals between the electronic network device and one or more other devices that are remote from the electronic network device, (ii) a plurality of transceiver dies disposed on the substrate and configured to transmit and receive the signals between the IC die and the other devices, one or more of the transceiver dies being spaced away from the IC die, and (iii) one or more decoupling capacitors configured to improve an integrity of one or more of the signals communicated within the electronic network device, the one or more decoupling capacitors being disposed in an area between the IC die and the one or more transceiver dies being spaced away from the IC die.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Write apparatus for a disk drive includes a write head, write current circuitry connected to the write head for generating a steady-state write current, overshoot current circuitry connected to the write head for generating write current overshoot pulses, and a T-coil termination network between (a) the write current circuitry and the overshoot current circuitry, and (b) a first node connected to a first input of a transmission line together with the write head. The T-coil termination network may include a first inductor connected to the first node, a second inductor coupled with the first inductor at a second node, and a first termination resistor between the first inductor and a common voltage. An output of the overshoot current circuitry may be connected to the first node, and an output of the write current circuitry may be connected to the second node.
A first communication device for communicating in a wireless local area network (WLAN) includes a WLAN network interface device and a wakeup radio (WUR) coupled to the WLAN network interface device. The WLAN network interface device is configured to receive, from a second communication device, a WLAN packet that includes a WUR identifier for a third communication device. The WUR of the first communication device is configured to receive a WUR packet that includes the WUR identifier. At least one of the WLAN network interface and the WUR are further configured to use the WUR packet to determine whether to change a WLAN association from the second communication device to the third communication device.
A physical layer transceiver (PHY) includes transmit circuitry including digital and analog transmit portions, receive circuitry including digital and analog receive portions, coupling circuitry configured to couple signals from the transmit circuitry onto a transmission medium, and to couple signals off the transmission medium to the receive circuitry, and transient error compensation circuitry coupled to the digital receive portions and to the analog transmit portions, and configured to detect transient error induced in the receive circuitry by the analog transmit portions and to subtract a transient error correction from data in the receive circuitry. The PHY may include asymmetric Energy-Efficient Ethernet (EEE) controller circuitry, and when the transmit circuitry is in the leg operating in EEE low-power-idle mode, the transient error compensation circuitry may detect transient error induced in the receive circuitry of the leg operating in full-data mode and apply a transient error correction.
