A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit and the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
This disclosure describes an apparatus that enables rapid transitions during microwave-assisted magnetic recording (MAMR) of storage media. In various aspects, the apparatus incorporates a driver circuit configured to provide a controlled bias current through separate source and sink output terminals, which respond to feedback signals. An MAMR sensor connects between the source and sink output terminals and generates microwave fields when receiving the controlled bias current from the driver circuit. A common-mode feedback (CMFB) loop connects to the source and sink output terminals, detects common-mode voltage (CMV), and delivers feedback signals to the driver circuit to maintain CMV regulation of the MAMR sensor. A differential voltage regulation loop connects to the source and sink output terminals, providing feedback signals that maintain the MAMR sensor voltage differential at a reference value. The apparatus controls the magnetic recording process of the MAMR sensor with rapid transition times.
The present disclosure describes aspects of a differential current-mode (iMode) driver for microwave-assisted magnetic recording (MAMR) application in hard-disk drives. In some aspects, an iMode driver circuitry employs a driver circuit coupled to power supply connections. The driver circuit is configured to provide a controlled differential bias current and includes separate source and sink output terminals. A MAMR sensor couples between the source and sink output terminals, through which the MAMR sensor receives the controlled differential bias current provided by the driver circuit. The MAMR sensor, which has a field-entry terminal and a field-exit terminal, generates microwave fields for the recording process. A common-mode feedback (CMFB) loop couples to the field-entry and field-exit terminals of the MAMR sensor, forming a feedback pathway with the driver circuit. This CMFB loop detects common-mode voltage (CMV) and adjusts the controlled differential bias current to maintain CMV regulation of the MAMR sensor.
G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions
G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor
G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor
6.
Double seal ring and electrical connection of multiple chiplets
A package connecting first and second circuitry components includes: a semiconductor substrate, dielectric layers formed over the semiconductor substrate, first and second substrates of the first and second circuitry components, respectively, positioned side-by-side on one of the dielectric layers, first seal ring of the first circuitry component implemented in first metal layers embedded between the first substrate and a first surface of the first circuitry component, second seal ring of the second circuitry component implemented in second metal layers embedded between the second substrate and a second surface of the second circuitry component, and a third seal ring surrounds the first and second circuitry components and embedded in the dielectric layers extrinsic to the first and second metal layers and overlaying the first and second surfaces, at least a third section of the third seal ring disposed over first and second sections of the first and second seal rings, respectively.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
7.
INTEGRATION OF BGA PACKAGE ON PCB WITH REDUCED CROSSTALK
A device includes an electrical board including a plurality of ball grid arrays (BGA) groups. Each BGA group of the plurality of BGA groups includes its respective BGA balls connected to its respective vias configured to route electrical signals between an integrated circuit to the electrical board. Vias for two adjacent BGA group of the plurality of BGA groups connect to different layers of the plurality of layers of the electrical board.
Digital signal processing (DSP) circuitry of a transceiver generates intermediate results corresponding to transmit bits that are to be transmitted. Each of at least some of the intermediate results correspond to an encoding of a respective set of multiple bits from amongst the transmit bits. The respective set of multiple bits includes bits corresponding to multiple modulation symbols to be transmitted by the transceiver. The DSP circuitry encodes, according to an FEC code, the intermediate results corresponding to the respective sets of multiple bits to generate parity bits. The DSP circuitry maps, according to a modulation technique, the transmit bits and the parity bits to modulation symbols to generate a digital transmit signal. A digital-to-analog converter (DAC) converts the digital transmit signal to an analog transmit signal.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/25 - Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
9.
MULTI-DECISION FEEDBACK EQUALIZATION IN A RECEIVER DEVICE
A receiver device receives a signal transmitted to the receiver device over an optical communication channel and equalizes the signal using a multi-decision feedback equalizer of the receiver device. Equalizing the signal includes generating, using at least one decision feedback equalizer configured with a plurality of slicing thresholds, decisions on symbols transmitted to the receiver device, detecting that a decision made by the decision feedback equalizer is unreliable. Equalizing the signal also includes, in response to detecting that the decision is unreliable, tracking, for a tracking period, multiple decision paths that generate respective possible sequences of symbols transmitted to the receiver device, determining error energies in decisions made, during the tracking period, in respective decision paths, and selecting, based on a comparison between the respective error energies, a sequence of symbols generated in one of the multiple decision paths as an output of the multi-decision feedback equalizer.
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller (132) maps, with an interleave map mode, a first portion of logical address space (406) to a first portion of the physical address space (416) of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space (408, 410) to a second portion of the physical address space (418) of the memory. Thus, the memory controller may configure some memory banks (414) with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced eXtensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on- chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
12.
Shared Memory Controller with Direct Memory Access Architecture for On-Chip Memory
The present disclosure describes System on Chip (SoC) architecture that facilitates disaggregation of memory-to-memory operations. The SoC architecture includes a host interface that communicates with a host system, processor cores, and an Advanced extensible Interface (AXI) interconnect coupling the host interface with processor cores. The SoC architecture includes an on-chip memory (OCM) subsystem coupled to the AXI interconnect, where the OCM subsystem contains memory banks, a Direct Memory Access (DMA) interconnect coupled directly with respective memories of processor cores, and a shared memory controller coupled with the AXI interconnect, memory banks, and DMA interconnect. The shared memory controller includes an OCM-internal path connecting the shared memory controller directly to memory banks within the OCM subsystem and a DMA engine that executes memory-to-memory operations by transferring data directly between memory banks through the OCM-internal path or respective memories of processor cores via a DMA interconnect.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
13.
METHOD AND SYSTEM TO SUPPORT DATA STREAMING FOR MATRIX OPERATIONS VIA A MACHINE LEARNING HARDWARE
A system comprises an on-chip memory (OCM) configured to maintain blocks of data used for a matrix operation and result of the matrix operation, wherein each of the blocks of data is of a certain size. The system further comprises a first OCM streamer configured to stream a first matrix data from the OCM to a first storage unit, and a second OCM streamer configured to stream a second matrix data from the OCM to a second storage unit, wherein the second matrix data is from an unaligned address of the OCM that is a not a multiple of the certain size. The system further comprises a matrix operation block configured to retrieve the first matrix data and the second matrix data from the first storage unit and the second storage unit, respectively, and perform the matrix operation based on the first matrix data and the second matrix data.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.
A new approach is proposed to support hardware-based update of a software (e.g., a firmware) of an electronic device in a non-functional state. Under the proposed approach, the software is stored securely on a resource (e.g., a non-volatile storge) protected by a hardware-based lock mechanism. A first agent acquires a lock and authenticate the software. When a boot failure (e.g. authentication of the software fails) of the electronic device happens, an alert indicating the failure is generated and sent to a second agent (e.g., a sideband master) through an alert mechanism. The second agent then acquires a lock from the hardware-based lock mechanism to obtain exclusive excess to the resource and update the software stored in the non-volatile storage through, e.g., block write and/or read operations. The second agent then verifies that the software has been updated successfully so that the electronic device becomes functionally again.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
16.
Setup and training of links between host devices and optical modules including menu-based and multi-stage link training
A host device includes a transmitter, an out-of-band electrical interface and a processor. The transmitter transmits in-band signals on an in-band electrical interface from the host device to an optical module. The in-band signals are data signals transmitted to test a link between the host device and the optical module. The out-of-band electrical interface transmits first out-of-band messages from the host device to the optical module, and receives second out-of-band messages from the optical module. The first and second out-of-band messages being control messages for testing the link. The processor performs tests to test the link and selects a set of transmitter settings based on the tests. The processor: i) subsequent to performing the tests, receives via the out-of-band electrical interface one of the second out-of-band messages including an indication of the selected set; and ii) in response to receiving the indication, sets the transmitter according to the selected set.
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
A packet to be forwarded over a computer network to a destination is received. A group of multiple network paths is available to forward to the packet to the destination. One or more path selection factors are determined to be used to identify a specific network load balancing algorithm to select a specific network path from the group of multiple network paths. The one or more path selection factors include at least one path selection factor determined based at least in part on a dynamic state of the computer network or a network node in the computer network. In response to selecting, by the specific network load balancing algorithm, the specific network path from among the group of multiple network paths, the packet is forwarded over the specific network path.
The present disclosure describes apparatuses and methods for hybrid logical to physical (LTP) address mapping in memory systems. In various aspects, a memory controller maps, with an interleave map mode, a first portion of logical address space to a first portion of the physical address space of a memory. The memory controller also maps, with a fixed map mode, a second portion of logical address space to a second portion of the physical address space of the memory. Thus, the memory controller may configure some memory banks with interleave address mapping and other banks with fixed address mapping. In some cases, the memory controller may reconfigure a bank of the memory from one mapping mode to the other mapping mode. By so doing, the memory controller can leverage benefits provided by either mapping mode to optimize access performance, reduce power consumption, or isolate defective areas with minimal capacity loss.
An example method of low-latency decompression includes receiving a data read request to read data stored, in a compressed storage format, in a memory, and responsive to receiving the data read request, accessing compressed data sequences, splitting the compressed data sequences into three separate streams for parallel processing, the three separate streams including (i) a literal stream, (ii) a history cache stream, and (iii) a history buffer stream, for each data sequence in the literal stream, determining a literal decompressed block offset for the data sequence, for each data sequence in the history cache stream, determining a decompressed block offset using one or more history cache pointers associated with the data sequence, for each data sequence in the history buffer stream, determining the decompressed block offset via a history buffer, and generating a data output responsive to the data read request.
Clock distribution circuitry, for distributing clocks for scan operations in an integrated circuit device in which a mission mode clock is distributed by a mesh clock structure and a scan fabric clock is distributed by a scan clock bus, includes a mesh clock source, and a local distribution structure for distributing the clocks for scan operations to a local clock domain that includes a subset of taps of the mesh clock structure. The local distribution structure includes a local controller for controlling derivation of a scan capture clock from the mesh clock source, local scan host circuitry for deriving a local scan shift clock from the scan fabric clock, and specialized integrated clock gates corresponding in number to the subset of taps of the mesh clock structure, for selecting between the scan capture clock in a scan capture mode, and the local scan shift clock in a scan shift mode.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
semiconductors; Microprocessors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; integrated circuits; Electronic chips for use in the manufacture of integrated circuits; downloadable computer software and firmware for controlling and using integrated circuits; processors, namely, data processors for downloadable computer programs using artificial intelligence, data processors for computer network servers and central gateways deployed on a network, general purpose computer data processors, data processors for high-performance computing, data processors for digital signal, data processors, programmable data processors, data processors for downloadable audio and video files; digital signal processors; ethernet transceivers; wireless integrated circuits, namely transceivers and digital signal processors; integrated circuits for controlling solid state drives; amplifiers, namely, transimpedance amplifiers; semiconductor devices, namely retimers; electronic circuits; microchips; photonic microchips; Electronic and optical communications instruments and components, namely, optical transmitters; Electronic and optical communications instruments and components, namely, digital transmitters; Electronic and optical communications instruments and components, namely, optical transceivers; power amplifiers design and development of computer software and hardware for the design and manufacture of semiconductors; design of computer hardware and integrated circuits; designing semiconductors, semiconductor chips and chip sets, integrated circuits, integrated circuit chips, integrated circuit chip sets, and software for others; design and development of computer software and hardware for the design and manufacture of semiconductor devices, namely digital signal processors, transceivers, amplifiers, retimers and microprocessors.
22.
METHOD OF USING UNIT VECTORS TO ALLOW EXPANSION AND COLLAPSE OF HEADER LAYERS WITHIN PACKETS FOR ENABLING FLEXIBLE MODIFICATIONS AND AN APPARATUS THEREOF
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of software; Non-downloadable computer software for use in monitoring circuit compliance with CMIS; Computer chip design services; Non-downloadable telemetry and data analytics software; Non-downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Scientific and electric apparatus and instruments
Goods & Services
Downloadable computer software for use in monitoring circuit compliance with CMIS; Downloadable telemetry and data analytics software; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Computer hardware; Computer chips; Computer memory hardware; Electronic circuits; semiconductors; Semiconductor chips; Semiconductor computer chips; Semiconductor integrated circuits; Electronic chips for use in the manufacture of integrated circuits; Computer firmware for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters; Computer firmware for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems; Integrated circuits for controlling hard disk drives; Integrated circuits for controlling solid state drives; Downloadable computer software for use in controlling, storing, monitoring, and managing data in processors, workload accelerators, data centers, attached storage devices and systems Design and development of computer hardware and software; Design and development of computer firmware; Computer chip design services; Non-downloadable computer software for operating mixed signal adaption, digital processing, decision feedback equalization, and advance detector parameters
26.
Physical layer transceiver with collision avoidance in high noise and interference environment
Systems and methods for using a physical layer transceiver (PHY) of an automobile to avoid data signal collision on a high noise or interference automotive multi-drop communication link are provided. A signal is received at a first PHY via a multi-drop communication link in a high noise or interference automotive environment. The received signal is separated into a first spectral component corresponding to a first logic level and into a second spectral component corresponding to a second logic level. Based on analysis of the first and second spectral components, respectively, a determination is made as to whether a second PHY device is concurrently transmitting data on the link, by determining whether both the first and second logic levels are detected in the first and second spectral components within a threshold period of time of one another. The first PHY device is permitted to transmit, or prevented from transmitting, data via the link based on whether the second PHY device is transmitting data on the link.
Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programed based on how the tiles are allocated for each lookup.
H03K 19/17728 - Reconfigurable logic blocks, e.g. lookup tables
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G11C 15/04 - Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
H04L 45/7452 - Multiple parallel or consecutive lookup operations
H04L 45/7453 - Address table lookupAddress filtering using hashing
28.
Silicon nitride-to-silicon waveguide assembly for broadband communication including concurrent propagation by TE0 and TM0 modes
A waveguide assembly includes first and second waveguides. The first waveguide includes silicon, first and second ends, an end member, and a tapered member. The end member extends from the first end. The tapered member extends from the end member to the second end. The second waveguide is optically coupled to and spaced away from the first waveguide. The second waveguide includes silicon nitride, first and second members, and a non-tapered member. The non-tapered member extends from the first member to the second member and in parallel with and opposing the tapered member. An effective refractive index of the non-tapered member matches an effective refractive index of the tapered member at a first plane. The first plane extends through the non-tapered member and the tapered member and perpendicular to a second plane. The second plane extends parallel to a direction of overlap between the first and second waveguides.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
A solid state drive (SSD) device includes a memory having a plurality of memory cells and an encoder configured to encode information using a polar code to generate encoded information to be stored in the memory. The polar code is constructed based on a plurality of channel models corresponding to different read channel scenarios, including at least a first channel model corresponding a first read channel scenario and a second channel model corresponding to a second read channel scenario, the second read channel scenario different from the first read channel scenario. The SSD device also includes a controller configured to write the encoded information to memory cells in the memory, and read the encoded information from the memory cells in the memory using a selected one of the first read channel scenario and the second read channel scenario.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
A digital signal processor (DSP) of an optical receiver processes one or more digital domain signals, which correspond to a received optical signal, to recover receive data from the one or more digital domain signals. The DSP compensates for a two-dimensional (2-D) warping of transmission symbols at a transmitter of the optical signal at least by: calculating a first adjustment of an in phase (I) component of the transmission symbol; modifying the I component of the transmission symbol using the first adjustment; calculating a second adjustment of a quadrature (Q) component of the transmission symbol; and modifying the Q component of the transmission symbol using the second adjustment
A link establishment process for establishing a network link between the first network interface device and a second network interface device is initiated at the first network interface device. During the link establishment process, the first network interface device receives from the second network interface device via the network link, one or more update messages requesting one or more changes to be applied at the first network interface device, the one or more changes for altering operation of one or both of software and firmware stored in one or more memories included in or coupled to the first network interface device. The one or more changes are applied based on the one or more update messages at the first network interface device.
An electrical circuit board assembly includes: (I) a surface, having a plurality of terminals disposed thereon for transferring a power signal to an electronic device, (II) at least first and second layers separated by at least one dielectric layer, the first and second layers being configured to (a) be connected to the power signal, and (b) electrically conduct at least a portion of the power signal, and (III) multiple vias that (i) mechanically traverse the first and second layers at respective traversal points, and (ii) are electrically connected to the terminals on the surface, the multiple vias including: first vias that, at the respective traversal points, are electrically connected to the first layer and electrically isolated from the second layer, and second vias that, at the respective traversal points, are electrically connected to the second layer and electrically isolated from the first layer.
An electronic device includes (i) a substrate, (ii) first and second stacks of integrated circuit (IC) dies, the first and second stacks being positioned adjacent to one another over the substrate and having first and second surfaces facing one another, (iii) a first plate disposed between the substrate and the first surface of the first and second stacks, and (iv) a second plate disposed over the second surface of the first and second stacks, each of the first and second plates mechanically connects the first stack to the second stack, overlaps at least a portion of a combined footprint of the first and second stacks and configured to mitigate a warpage in at least one of the first and second stacks.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
34.
PHYSICAL LAYER TRANSCEIVER WITH REDUCED VARIATION IN PACKET LATENCY
A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.
Systems and methods are described for a slave PHY device retransmitting a waking up command to a master PHY device in a low-power mode. After transmitting a wake-up command to the master PHY device, the slave PHY device starts a timer. If the timer reaches a threshold time, the slave device retransmits the wake-up command.
An optical signal transceiver includes a circuit board substrate, a silicon photonics-based interposer mounted on the circuit board substrate, the silicon photonics-based interposer including at least one of a waveguide configured to transmit optical communication signals and a photo detector configured to detect optical communication signals, and a planar lightwave circuit disposed on the circuit board substrate. The planar lightwave circuit is configured to perform at least a portion of propagation of light signals in an optical communication network, and the planar lightwave circuit is aligned with a side surface of the silicon photonics-based interposer to transmit optical communication signals between the silicon photonics-based interposer and the planar lightwave circuit. The optical signal transceiver includes at least one spacer component disposed between the planar lightwave circuit and the circuit board substrate, and epoxy material in contact with the spacer component.
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G02B 6/13 - Integrated optical circuits characterised by the manufacturing method
In a network having at least one slave node including a slave clock, a method of adjusting the slave clock relative to a master clock of a master node includes, at the slave node, correcting a time of day of the slave clock using (a) a slave pulse signal having a known slave pulse rate, (b) a time-of-day counter of the slave node, and (c) a master pulse signal, based on values of the slave clock at nearest corresponding edges of the slave pulse signal and the master pulse signal, and correcting a frequency of the slave clock using the slave pulse signal, a clock signal of the slave node, and the master pulse signal, based on values of the slave clock at nearest corresponding edges of the master pulse signal. No other clock signal from outside the slave node is used for the corrections.
An electronic device (11) includes (i) a substrate (12), (ii) first and second stacks (22a, 22b) of integrated circuit (IC) dies (24a, 24b), the first and second stacks (22a, 22b) being positioned adjacent to one another over the substrate and having first and second surfaces (28, 25) facing one another, (iii) a first plate (21) disposed between the substrate (12) and the first surface (28) of the first and second stacks (22a, 22b), and (iv) a second plate (23) disposed over the second surface (25) of the first and second stacks (22a, 22b), each of the first and second plates (21, 23) mechanically connects the first stack (22a) to the second stack (22b), overlaps at least a portion of a combined footprint of the first and second stacks (22a, 22b) and configured to mitigate a warpage in at least one of the first and second stacks (22a, 22b).
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/28 - Encapsulation, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
39.
Active cable interface with hybrid direct drive and re-timer integration
Interface circuitry for an active cable includes a first active cable interface configured for coupling to a first end of the active cable, and a second active cable interface configured for coupling to a second end of the active cable. The first active cable interface includes first transmitter circuitry including linear driving circuitry or non-linear driving circuitry, and first receiver circuitry including linear receiving circuitry or non-linear receiving circuitry. The second active cable interface includes second transmitter circuitry including linear driving circuitry when first transmitter circuitry includes non-linear receiving circuitry, and non-linear driving circuitry when first transmitter circuitry includes linear receiving circuitry. The second receiver circuitry includes linear receiving circuitry when first receiver circuitry includes non-linear driving circuitry, and non-linear receiving circuitry when first receiver circuitry includes linear driving circuitry.
An integrated circuit device having functional circuitry driven by a clock signal includes onboard clock generation circuitry. The clock generation circuitry includes an input configured to accept a frequency reference signal, at least one variable loading capacitor coupled to the input for converting the crystal resonator signal into a calibrated clock signal, and calibration circuitry configured to calibrate the at least one variable loading capacitor based on a reference voltage. The input configured to accept a frequency reference signal may be configured to accept a crystal resonator signal.
A semiconductor device includes circuitry configured for faster bitcell operation. That circuitry includes a plurality of bitcells readable as one of a ‘0’ value and a ‘1’ value, and voltage generation circuitry configured to apply an activation voltage to activate selected bitcells in the plurality of bitcells for reading. The voltage generation circuitry is further configured to switch between an overdrive mode and a steady-state mode where the voltage generation circuitry applies a first voltage during the overdrive mode and the voltage generation circuitry applies a second voltage, less than the first voltage, during the steady-state mode, interconnect circuitry configured to couple the plurality of bitcells to reading circuitry. The reading circuitry is configured to receive a differential signal from a bitcell and amplify the differential signal to a full digital logic level. The full digital logic level corresponds to one of the ‘0’ value and the ‘1’ value.
A communication device performs a first backoff operation with a first backoff counter to determine when to transmit in a first frequency segment, and performs a second backoff operation with a second backoff counter to determine when to transmit in a second frequency segment. In response to i) determining that first starts of first transmissions in the first frequency segment are to be synchronized with second starts of second transmissions in the second frequency segment, and ii) the first backoff counter expiring before the second backoff counter expires, the communication device waits to transmit a first packet in the first frequency segment for the second backoff counter to expire, and transmits the first packet in the first frequency segment and a second packet in the second frequency segment beginning at a same start time in connection with the second backoff timer expiring.
An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
H04B 10/58 - Compensation for non-linear transmitter output
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H04B 10/2507 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
An Integrated Circuit (IC) includes electronic circuitry, multiple sensors, and an Adaptive Voltage Scaling (AVS) circuit. The electronic circuitry is configured to be powered by one or more supply voltages. The multiple sensors are configured to measure values affected by the one or more supply voltages, and to produce multiple sensor outputs. The AVS circuit is configured to adaptively set the one or more supply voltages by applying to the sensor outputs an AVS model having one or more user-defined parameters, to generate performance data based on the sensor outputs, to export the performance data from the IC, to receive the one or more user-defined parameters into the IC in response to the performance data, and to configure the AVS model to operate in accordance with the received user-defined parameters.
A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.
A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.
An optical communication system includes a transceiver device and a passive multiplexer and demultiplexer (PMAD). The transceiver device transmits or receives optical signals. The PMAD has a Mach-Zehnder interferometer structure, is connected to the transceiver device, and operates as a passive multiplexer or a passive demultiplexer. The PMAD includes: a first arm including a first waveguide, the first arm having a first dimension; a second arm including i) a second waveguide, and ii) a third waveguide, the second waveguide having a second dimension, the third waveguide having a third dimension, the second dimension being based on the first dimension and finely adjusts at least one performance parameter of the passive multiplexer and demultiplexer, and the third dimension being based on the first dimension and coarsely adjusts the at least one performance parameter; and a splitter and a coupler that propagate the optical signals.
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04J 14/02 - Wavelength-division multiplex systems
48.
BACKSIDE CAPACITOR FOR REDUCING POWER DELIVERY NETWORK IMPEDANCE
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A Physical Layer (PHY) device includes an ingress transceiver, an egress transceiver and a controller. The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry and respective digital signal processing (DSP) circuitry. The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
A Physical Layer (PHY) device (100) includes an ingress transceiver (102), an egress transceiver (104) and a controller (118). The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry (106, 110)) and respective digital signal processing (DSP) circuitry (108, 112). The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
An integrated circuit device includes functional circuitry including transistors, and testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors. The testing circuitry includes at least one first test circuit having a first physical relationship relative to the physical features of the integrated circuit device, at least one second test circuit having a second physical relationship, different from the first physical relationship, relative to the physical features of the integrated circuit device, and sensing circuitry for reading outputs of the at least one first test circuit and the at least one second test circuit. Imbalance circuitry is configured to apply compensation to the functional circuitry to compensate for a sensed imbalance. There may be a plurality of instances of the first test circuit, and a plurality of instances of the second test circuit.
A method includes receiving a high-level function in a first high-level code; compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator; transmitting the first set of low-level instructions to the hardware or the simulator; receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, wherein the plurality of statistical data is performance related; determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data; recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and transmitting the second set of low-level instructions to the hardware or the simulator.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die-to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
A system includes first memory, a controller, and a processor. The controller is indirectly connected to the memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function. The processor is connected between the memory and the controller. The processor reconfigures a map before and during performance of the at least one function by the controller. The reconfiguring of the map includes changing i) a first allocated portion of the memory for program instructions, and ii) a second allocated portion of the memory for the data. The processor, based on the map, i) routes the program instructions and the data between the controller and the first memory, ii) stores the program instructions at addresses of the memory allocated for the program instructions, and iii) stores the data at addresses of the memory allocated for the data.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die- to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
58.
METHOD AND APPARATUS FOR AUTOMATIC DESIGN CONSTRAINT GENERATION FOR CHIP IP USING GENERATIVE ARTIFICIAL INTELLIGENCE
A new approach is disclosed to support automatic design constraint generation for chip IP using generative artificial intelligence (AI). A document ingress module accepts a plurality of inputs from multiple design documentation sources describing a chip IP. An LLM training module trains the one or more LLMs with targeted training materials on embodiments of the specific chip IP. A generative AI module automatically generates a set of design constraints for the chip IP using the one or more trained LLMs based on the plurality of inputs from multiple design documentation sources. Once the set of design constraints have been generated, a document egress module is configured to verify accuracy of the set of design constraints by converting the set of design constraints into a format of a human language document that includes attributes specific to design configuration of the chip IP.
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
G06F 119/12 - Timing analysis or timing optimisation
59.
METHOD AND APPARATUS FOR GENERATING ORDER OF MAGNITUDE DATA ASSOCIATED WITH TENSOR DATA
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors and generates a graph associated with the plurality of relative errors and the calculated order of magnitude associated with the first plurality of tensors. The graph is rendered.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
A silicon photonics modulator includes a substrate, a PN junction disposed on the substrate, the PN junction formed by a first L-shaped region doped with a p-type doping abutting a second L-shaped region doped with an n-type doping, a first plurality of regions each having different p-type doping concentrations greater than the first L-shaped region, and a second plurality of regions each having different n-type doping concentrations greater than the second L-shaped region. The silicon photonics modulator includes a first electrical contact on one of the first plurality of regions, a second electrical contact on one of the second plurality of regions, and multiple grating pillars doped with the n-type doping or the p-type doping, each of the multiple grating pillars spaced apart from the PN junction and spaced apart from one another.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
63.
PACKET BUFFER LATENCY MITIGATION IN A NETWORK DEVICE
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
H04L 49/25 - Routing or path finding in a switch fabric
H04L 49/50 - Overload detection or protection within a single switching element
H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
H04L 49/103 - Packet switching elements characterised by the switching fabric construction using a shared central bufferPacket switching elements characterised by the switching fabric construction using a shared memory
A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.
An integrated circuit includes current-mode circuitry implemented on a substrate. The current-mode circuitry includes i) a plurality of instances of a translinear circuit, and ii) a plurality of selection circuits coupled to respective instances of the translinear circuit, each selection circuit configured to selectively disable the respective instance of the translinear circuit. The current-mode circuitry is configured to generate a first output using one or more instances of the translinear circuit that are not disabled by one or more respective selection circuits. Drive circuitry is also implemented on the substrate and is coupled to the current-mode circuitry. The drive circuitry is configured to generate a second output using the first output of the current-mode circuitry.
A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an ‘ON’ state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
An optical modulator includes a substrate defining a plane and first, second, and third PN junctions formed on the substrate. The first PN junction is formed on the substrate by a first region doped with a p-type doping abutting a second region doped with an n-type doping. The second PN junction is formed on the substrate adjacent to the second region of the first PN junction. The third PN junction is formed on the substrate adjacent to the first region of the first PN junction.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
A Media Access Control Security (MACsec) core architecture implements flow control and bandwidth management when bandwidth is expanded internally due to encryption overhead and packet injection. External flow control requests are merged with internal flow control states and sent to a connected host.
A method for communication includes receiving first data timed by a first clock and receiving a signal including second data timed by a second clock, which is independent of the first clock, and generating a stream of data samples corresponding to the second signal. The received first data are resampled responsively to a time-varying phase shift between the first and second clocks to generate resampled data timed by the second clock. The resampled data are applied in estimating and subtracting an alien crosstalk component from the stream of data samples.
Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
An analog front-end device includes a sampler array and a clock bias circuit. The sampler array is configured to receive (i) an input signal and (ii) clock signals. The clock signals are received from a clocking circuit. The sampler array includes sampling circuits, where ones of the sampling circuits are each configured to sample and hold the input signal based on a respective one of the clock signals. The clock bias circuit is configured to adjust bias voltages of the clocking circuit to control sample timing of the sampling circuits.
A III-V semiconductor device in an optical transceiver includes a signal processing circuit. The signal processing circuit includes processing circuitry configured to receive or transmit an electrical signal corresponding to an optical signal, and feedback control circuitry communicatively coupled to the processing circuitry by a circuit loop. The feedback control circuitry is configured to sense a characteristic of the electrical signal, and based on the sensed characteristic, transmit over the circuit loop a feedback signal to the processing circuitry. The circuit loop includes a first transistor formed using a III-V semiconductor material and configured to function as a first sensing resistor having a first resistance value that limits loading applied to the processing circuitry by the feedback control circuitry.
H01S 5/068 - Stabilisation of laser output parameters
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT
An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.
A III-V semiconductor device in an optical transceiver includes a signal processing circuit. The signal processing circuit includes processing circuitry configured to receive or transmit an electrical signal corresponding to an optical signal, and feedback control circuitry communicatively coupled to the processing circuitry by a circuit loop. The feedback control circuitry is configured to sense a characteristic of the electrical signal, and based on the sensed characteristic, transmit over the circuit loop a feedback signal to the processing circuitry. The circuit loop includes a first transistor formed using a III-V semiconductor material and configured to function as a first sensing resistor having a first resistance value that limits loading applied to the processing circuitry by the feedback control circuitry.
A programmable hardware system for machine learning (ML) includes a core and a streaming engine. The core receives a plurality of commands and a plurality of data from a host to be analyzed and inferred via machine learning. The core transmits a first subset of commands of the plurality of commands that is performance-critical operations and associated data thereof of the plurality of data for efficient processing thereof. The first subset of commands and the associated data are passed through via a function call. The streaming engine is coupled to the core and receives the first subset of commands and the associated data from the core. The streaming engine streams a second subset of commands of the first subset of commands and its associated data to an inference engine by executing a single instruction.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A semiconductor device package includes a semiconductor die having two opposing faces that define a major plane, wherein the semiconductor die generates heat when in operation. The package includes a packaging lid, contacts, a crystalline pedestal, and a layer of thermal interface material (TIM). The packaging lid encloses the semiconductor die. The contacts are on a first exterior surface of the package parallel to the major plane, the first exterior surface defining a bottom of the package. The crystalline pedestal is formed of one or more crystals having an anisotropic thermal property affecting a thermal conductivity of the pedestal to dissipate the heat generated by the die when in operation, and the pedestal is disposed above the die in thermally-conductive, electrically non-conductive contact with the semiconductor die. The layer of TIM is disposed between the pedestal and the lid, wherein the TIM is thermally conductive and electrically non-conductive.
A network device includes network interfaces, and respective sets of queues. The sets of queues includes a first set corresponding to a first network interface and a second set corresponding to a second network interface. The network device receives packets via network interfaces, and processes packets to determine network interfaces via which the packets are to be transmitted. When the first network interface is not being used by the network device, the network device operates a composite queue to store packets corresponding to the second network interface. The composite queue includes a first queue from the first set and a second queue from the second set. The network device stores packet data to and reads packet data from the composite queue at a rate that is greater than a maximum rate at which the first queue and the second queue are capable of storing and reading packet data.
A network device includes network interfaces, and respective sets of queues. The sets of queues includes a first set corresponding to a first network interface and a second set corresponding to a second network interface. The network device receives packets via network interfaces, and processes packets to determine network interfaces via which the packets are to be transmitted. When the first network interface is not being used by the network device, the network device operates a composite queue to store packets corresponding to the second network interface. The composite queue includes a first queue from the first set and a second queue from the second set. The network device stores packet data to and reads packet data from the composite queue at a rate that is greater than a maximum rate at which the first queue and the second queue are capable of storing and reading packet data.
An optoelectronic device (11, 70) includes: (a) a substrate (12) having (i) a surface (15), and (ii) a recess (14) formed in the substrate (12) that extends from the surface (15) into the substrate (12), (b) an integrated circuit (IC) chip (33, 33a, 33b) facing the surface of the substrate, (c) an optical connector (21a, 21b) mounted on the substrate (12), and (d) an optical chiplet (22, 22a, 22b) embedded within the recess (14) of the substrate (12). The optical chiplet (22, 22a, 22b) being configured to exchange (i) optical signals with the optical connector (21a, 21b), and (ii) electrical signals with the integrated circuit (IC) chip (33, 33a, 33b), and to convert between the optical signals and the electrical signals.
A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch/walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch/walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.
A method for dynamically calibrating a time-interleaved digital-to-analog converter (DAC) includes receiving a digital input signal, generating, from the digital input signal, an output analog signal using DAC circuitry, generating, from the digital input signal, a model analog signal using DAC modeling circuitry, adjusting a digital model based on the model analog signal and the digital input signal, determining at least one of an offset error and a gain error based on comparing the output analog signal to the model analog signal, and generating an error correction signal based on the at least one of an offset error and a gain error.
In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.
A physical layer (PHY) device, for use in an Ethernet network, includes a cable interface, a transmitter, a receiver and a processor. The cable interface connects to an Ethernet link for communicating with a peer PHY device. The transmitter transmits outbound signals that carry outbound data to the peer PHY device over the Ethernet link. The receiver receives inbound signals that carry inbound data from the peer PHY device over the Ethernet link. The processor (i) controls the transmitter to transmit, to the peer PHY device, an outbound pre-alert signal indicating that the PHY device is about to start transmitting the outbound signals, and (ii) in response to receiving, via the receiver, an inbound pre-alert signal from the peer PHY device during a period in which the peer PHY device is abstaining from transmitting the inbound signals, controls the transmitter to abstain from transmitting the outbound signals.
An Ethernet physical layer (PHY) device, for use in an automotive network, includes a cable interface, a transmitter and a receiver. The cable interface is configured to connect to an Ethernet cable. The transmitter is configured to generate an outbound signal by modulating outbound data with a zero-disparity modulation at a first data rate, and to transmit the outbound signal to the Ethernet cable via the cable interface. The receiver is configured to receive, from the Ethernet cable via the cable interface, an inbound signal having a second data rate that is lower than the first data rate, the inbound signal at least partially overlapping the outbound signal in spectrum, and to demodulate the inbound signal to produce inbound data.
Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.
A hardware security module system, method and device including one or more security meshes that cover portions of a circuit board including the encryption/decryption component for determining if an unwanted physical access of the circuit board is occurring and disabling or erasing the hardware security module to prevent the unauthorized access of encryption data.
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors. The processor extracts features from the plurality of relative errors and the plurality of order of magnitude values and generates the error classification model based on the one or more features.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06N 3/0442 - Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors. The processor extracts features from the plurality of relative errors and the plurality of order of magnitude values and generates the error classification model based on the one or more features.
Techniques as described herein may be implemented to processing ingress packet traffic flows. A memory space that is divided into a packet buffer and an accelerated memory is defined. One or more congestion levels associated with ingress network traffic are determined. Upon enqueuing incoming packets, one or more memory locations are selected in the memory space for storing portions of each of the incoming packets based on at least one of the determined congestion levels.
An address translation system, method and device including a translation extension unit associated with a client and having a client address translation cache storing a client cache of the address translations. When virtual address of a translation request from the client is the same as the virtual address of an address translation of the client cache, the translation extension unit returns the physical address that is mapped to the virtual address according to the address translation to the client without transmitting the translation request to a memory management unit that maintains a page table of all the translations and a translation lookaside buffer with a subset of the translations.
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
92.
Hardware security module adapter system, method and device with active switch
A hardware security module system, method and device including one or more switches and a circuit board having pairs of security contact pads coupled with encryption/decryption and security components for determining if an unwanted physical access of the circuit board is occurring and disabling or erasing sensitive encryption/decryption data to prevent the unauthorized access of the data.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
Path-specific delay variations in a computer communication network between a time-sensitive nexus node and time-sensitive non-nexus nodes are determined. The time-sensitive nexus node determines, based on the path-specific delay variations, copy-specific delay alignment compensations for copies of a multi-destination communication packet to be sent by the time-sensitive nexus node to the time-sensitive non-nexus nodes respectively. The time-sensitive nexus node uses the per-copy delay alignment compensations to perform per-copy delay alignment operations with respect to the copies of the multi-destination communication packet. The time-sensitive nexus node sends each copy in the copies of the multi-destination communication packet to a respective time-sensitive non-nexus node in the time-sensitive non-nexus nodes after a respective per-copy delay alignment operation in the per-copy delay alignment operations is performed for the copy of the multi-destination communication packet.
In a virtual network environment including a virtualized host administered by a hypervisor, a first network adapter coupling the host to a storage area network (SAN), an external storage device, and a second network adapter coupling the external storage device to the SAN, where the host includes a first virtual machine, and the first network adapter and the second network adapter are configured to establish an encrypted channel between themselves, for use by a virtual machine to communicate to the external storage device, managing the encrypted channel includes instantiating an additional virtual machine for executing security software, instantiating an emulated storage device associated with the hypervisor, instantiating at the additional virtual machine a respective virtual disk corresponding the emulated storage device, and transferring messages between the security software on the additional virtual machine and the first network adapter by encoding the messages in read/write requests to the virtual disk.
A method for converting an unknown analog voltage to a digital output signal includes receiving the unknown voltage, establishing a first stability threshold to distinguish between stable and metastable measurements of a voltage difference between the unknown voltage and a reference voltage, measuring that difference, determining whether the difference is greater or less than the first stability threshold, in response to determining that the difference is greater than the first stability threshold, yielding an output indicative of which one of the unknown and reference voltages is greater, in response to determining that the difference is less than the first stability threshold, overruling the output and assigning a predetermined output value indicative of which one of the unknown and reference voltages is greater, and deriving, from the output value indicative of which one of the unknown and reference voltages is greater, at least one bit of the digital output signal.
H03M 1/34 - Analogue value compared with reference values
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
96.
Method and apparatus for determining bit-error rate in a data channel
A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
97.
Spread spectrum modulation over an asymmetric ethernet link
An automotive Ethernet physical-layer (PHY) transceiver includes an Analog Front End (AFE) and a digital processor. The AFE is coupled via a full-duplex Ethernet link to a peer transceiver. The AFE is configured to receive from the peer transceiver, over the full-duplex Ethernet link, an analog Ethernet signal conveying data symbols, at a reception data rate that is lower than a transmission data rate used in transmitting data from the PHY transceiver to the peer transceiver, the Ethernet signal being modulated by a spreading sequence having a Spreading Factor including a ratio between a spreading chip-rate and the reception data rate, and to convert the received analog Ethernet signal into a digital signal. The digital processor is configured to de-spread the digital signal using the spreading sequence to recover the data symbols.
An optical communication receiver includes: a photodiode and signal processing circuitry coupled to the photodiode. The photodiode is configured to receive a modulated optical signal conveying data and convert the modulated optical signal to an electrical signal. The photodiode includes: a waveguide configured to receive the modulated optical signal; an absorption region above the waveguide; and a capacitor electrically coupled in series with the absorption region to reduce a capacitance of the photodiode as compared to a scenario in which the capacitor is omitted from the photodiode. The signal processing circuitry is configured to process the electrical signal to extract and output the data.
H10F 30/00 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
99.
System and Method for User Devices in Cloud Computing Environment
A system and corresponding method consumerize cloud computing by incorporating consumer devices into an infrastructure of cloud computing environment. The consumer device comprises a client job manager that spawns a processing task on the consumer device responsive to a job request to perform at least a portion of a computational job. The computational job is requested by an end user device to be performed via cloud computing. The consumer device further comprises a network interface. The job request is received via the network interface from a cloud job manager of a cloud service provider system of a cloud service provider. The processing task performs the at least a portion of the computational job. The consumer device is selected by the cloud job manager based, at least in part, on proximity of the consumer device to the end user device and at least one characteristic of the consumer device. The client job manager communicates the at least one characteristic to the cloud job manager via the network interface.
H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
H04L 67/1029 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers using data related to the state of servers by a load balancer
100.
Method and system for performing a compaction/merge job using a merge based tile architecture
A hardware-based compaction accelerator may comprise two or more decoders, a merge iterator, a compaction module, and an encoder. Each of the decoders converts a sorted string table (SST) files into a corresponding key-value (KV) format data stream. The merge iterator receives a KV format data stream from each of the decoders, and combines the KV format data streams into a single KV format data stream. The compaction module receives the composite KV format data stream and produces a compacted data stream. The compacted data stream contains less data that is in the composite KV format data stream. The encoder converts the composite KV format data stream back into one or more output SST files. The compaction accelerator may be configured to perform only a subset of the processing available from the decoders, merge iterator, compaction module, and encoder, and may be configured through the Internet using a cloud-based processor.
