A communication device performs a first backoff operation with a first backoff counter to determine when to transmit in a first frequency segment, and performs a second backoff operation with a second backoff counter to determine when to transmit in a second frequency segment. In response to i) determining that first starts of first transmissions in the first frequency segment are to be synchronized with second starts of second transmissions in the second frequency segment, and ii) the first backoff counter expiring before the second backoff counter expires, the communication device waits to transmit a first packet in the first frequency segment for the second backoff counter to expire, and transmits the first packet in the first frequency segment and a second packet in the second frequency segment beginning at a same start time in connection with the second backoff timer expiring.
An optical receiver includes an error generator, a multipath interference estimator, and a combiner. The error generator is configured to receive an input comprising a received optical signal, to estimate a modulation level of samples of the received optical signal, and to generate an error signal based on the estimated modulation level of the samples, the error signal representing a difference between an actual level of the received optical signal and the estimated modulation level. The multipath interference estimator is configured to generate estimates of multipath interference (MPI) associated with the samples of the received optical signal based on the error signal. The combiner is configured to generate an MPI-mitigated signal based on a combination of the samples and the estimates of MPI.
H04B 10/58 - Compensation for non-linear transmitter output
H04B 10/00 - Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
H04B 10/2507 - Arrangements specific to fibre transmission for the reduction or elimination of distortion or dispersion
An Integrated Circuit (IC) includes electronic circuitry, multiple sensors, and an Adaptive Voltage Scaling (AVS) circuit. The electronic circuitry is configured to be powered by one or more supply voltages. The multiple sensors are configured to measure values affected by the one or more supply voltages, and to produce multiple sensor outputs. The AVS circuit is configured to adaptively set the one or more supply voltages by applying to the sensor outputs an AVS model having one or more user-defined parameters, to generate performance data based on the sensor outputs, to export the performance data from the IC, to receive the one or more user-defined parameters into the IC in response to the performance data, and to configure the AVS model to operate in accordance with the received user-defined parameters.
A first communication device determines that a trigger frame and another frame are to be transmitted to at least a second communication device. The first communication device determines whether the second communication device announced support of aggregation of buffer status report (BSRP) trigger frames with additional frames. In response to the first communication device determining that the second communication device announced support of aggregation of BSRP trigger frames with additional frames, the first communication device generates an aggregate media access control protocol data unit (A-MPDU) to include the BSRP trigger frame and the other frame, and transmits the A-MPDU within a packet. In response to the first communication device determining that the second communication device did not announce support of aggregation of BSRP trigger frames with additional frames, the first communication device transmits a packet having only the BSRP trigger frame.
A time-interleaved digital-to-analog converter for an optical transmitter includes a DAC core having a plurality of slices and current sources for converting complementary data signals to analog signals at output nodes of the DAC core, a down switch circuitry configured to connect, for each slice of the DAC core, a current from one of the current sources to a first data input path or a second data input path respectively corresponding to first complementary data signals and second complementary data signals supplied to the slice of the DAC core, an up switch circuitry configured to connect the current to the output nodes, and a data switch circuitry configured to, for each slice of the DAC core, selectively connect the current received via the down switch circuitry and either the first data input path or the second data input path.
An optical communication system includes a transceiver device and a passive multiplexer and demultiplexer (PMAD). The transceiver device transmits or receives optical signals. The PMAD has a Mach-Zehnder interferometer structure, is connected to the transceiver device, and operates as a passive multiplexer or a passive demultiplexer. The PMAD includes: a first arm including a first waveguide, the first arm having a first dimension; a second arm including i) a second waveguide, and ii) a third waveguide, the second waveguide having a second dimension, the third waveguide having a third dimension, the second dimension being based on the first dimension and finely adjusts at least one performance parameter of the passive multiplexer and demultiplexer, and the third dimension being based on the first dimension and coarsely adjusts the at least one performance parameter; and a splitter and a coupler that propagate the optical signals.
H04B 10/079 - Arrangements for monitoring or testing transmission systemsArrangements for fault measurement of transmission systems using an in-service signal using measurements of the data signal
H04J 14/02 - Wavelength-division multiplex systems
7.
BACKSIDE CAPACITOR FOR REDUCING POWER DELIVERY NETWORK IMPEDANCE
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A Physical Layer (PHY) device includes an ingress transceiver, an egress transceiver and a controller. The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry and respective digital signal processing (DSP) circuitry. The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
A die has an integrated circuit with backside decoupling capacitance that reduces impact of noise caused by a power delivery network supplying power to the integrated circuit. The integrated circuit includes a power delivery network spanning a front end of line region, a back end of line region, and a backside region. The integrated circuit includes a decoupling capacitor disposed in the backside region to provide a backside decoupling capacitance. The decoupling capacitor includes at least two respective portions of at least two of backside metal traces such that each of the at least two respective portions are electrically coupled to at least one of the front end of line region or the back end of line region by at least two respective through-silicon vias among the plurality of through-silicon vias, and a dielectric material is arranged between the at least two respective portions of the backside metal traces.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
A Physical Layer (PHY) device (100) includes an ingress transceiver (102), an egress transceiver (104) and a controller (118). The ingress transceiver and the egress transceiver each includes respective analog signal processing (ASP) circuitry (106, 110)) and respective digital signal processing (DSP) circuitry (108, 112). The controller is configured to select an operational mode, for one or both of the ingress transceiver and the egress transceiver, between (i) a digital mode in which both the ASP circuitry and the DSP circuitry are active, and (ii) an analog mode in which the ASP circuitry is active and the DSP circuitry is bypassed.
An integrated circuit device includes functional circuitry including transistors, and testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors. The testing circuitry includes at least one first test circuit having a first physical relationship relative to the physical features of the integrated circuit device, at least one second test circuit having a second physical relationship, different from the first physical relationship, relative to the physical features of the integrated circuit device, and sensing circuitry for reading outputs of the at least one first test circuit and the at least one second test circuit. Imbalance circuitry is configured to apply compensation to the functional circuitry to compensate for a sensed imbalance. There may be a plurality of instances of the first test circuit, and a plurality of instances of the second test circuit.
A method includes receiving a high-level function in a first high-level code; compiling the high-level function into a first set of low-level instructions to be executed on a hardware or a simulator; transmitting the first set of low-level instructions to the hardware or the simulator; receiving a plurality of statistical data generated by the hardware or the simulator in response to execution of the first set of low-level instructions, wherein the plurality of statistical data is performance related; determining whether to make changes to the compilation associated with the high-level function in the first high-level code based on the plurality of statistical data; recompiling the high-level function into a second set of low-level instructions to be executed on the hardware or the simulator based on the changes to the compilation; and transmitting the second set of low-level instructions to the hardware or the simulator.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die-to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A network interface device operates in a normal transmit operating mode in which the network interface device continually receives transmission symbols from a link partner via the communication link. The network interface device determines that receive circuitry of the network interface device is to transition to a low power mode in response to receiving a sleep signal from the link partner. The network interface device then operates according to a quiet/refresh cycle of the low power mode to conserve power. The quiet/refresh cycle corresponds to a time schedule that includes a refresh time window in which receive circuitry of the network interface device is to be powered to receive a refresh signal from the link partner. Immediately after transmission of the sleep signal, the network interface device transitions to a quiet time window of the time schedule in which the network interface device ignores transmissions from the link partner.
A system includes first memory, a controller, and a processor. The controller is indirectly connected to the memory, configured to perform at least one function, and configured to handle data generated or received during performance of the at least one function. The processor is connected between the memory and the controller. The processor reconfigures a map before and during performance of the at least one function by the controller. The reconfiguring of the map includes changing i) a first allocated portion of the memory for program instructions, and ii) a second allocated portion of the memory for the data. The processor, based on the map, i) routes the program instructions and the data between the controller and the first memory, ii) stores the program instructions at addresses of the memory allocated for the program instructions, and iii) stores the data at addresses of the memory allocated for the data.
A semiconductor package includes a first chip including a first die-to-die interface with a first plurality of flip-flops, and a second chip including a second die-to-die interface with a second plurality of flip-flops, and an interposer configured to provide paths for data to flow between the first die-to-die interface and the second die- to-die interface. The interposer is mechanically coupled to the first chip and to the second chip by a first hybrid bond and a second hybrid bond, respectively, the interposer including a first plurality of interposer vias coupled to the first plurality of flip-flops across the first hybrid bond, a second plurality of interposer vias coupled to the second plurality of flip-flops across the second hybrid bond, and a plurality of lateral metal traces coupling respective vias among the first plurality of interposer vias to respective vias among the second plurality of interposer vias to provide the paths.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
17.
METHOD AND APPARATUS FOR AUTOMATIC DESIGN CONSTRAINT GENERATION FOR CHIP IP USING GENERATIVE ARTIFICIAL INTELLIGENCE
A new approach is disclosed to support automatic design constraint generation for chip IP using generative artificial intelligence (AI). A document ingress module accepts a plurality of inputs from multiple design documentation sources describing a chip IP. An LLM training module trains the one or more LLMs with targeted training materials on embodiments of the specific chip IP. A generative AI module automatically generates a set of design constraints for the chip IP using the one or more trained LLMs based on the plurality of inputs from multiple design documentation sources. Once the set of design constraints have been generated, a document egress module is configured to verify accuracy of the set of design constraints by converting the set of design constraints into a format of a human language document that includes attributes specific to design configuration of the chip IP.
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
G06F 119/12 - Timing analysis or timing optimisation
18.
METHOD AND APPARATUS FOR GENERATING ORDER OF MAGNITUDE DATA ASSOCIATED WITH TENSOR DATA
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors and generates a graph associated with the plurality of relative errors and the calculated order of magnitude associated with the first plurality of tensors. The graph is rendered.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
To improve time synchronization in a communication network, a first communication device generates a measurement of a first latency of a transmit path of a communication link between the first communication device and a second communication device. The communication link also includes a receive path. The first communication device compensates for an asymmetry between the first latency of the transmit path and a second latency of the receive path using the measurement of the first latency.
A silicon photonics modulator includes a substrate, a PN junction disposed on the substrate, the PN junction formed by a first L-shaped region doped with a p-type doping abutting a second L-shaped region doped with an n-type doping, a first plurality of regions each having different p-type doping concentrations greater than the first L-shaped region, and a second plurality of regions each having different n-type doping concentrations greater than the second L-shaped region. The silicon photonics modulator includes a first electrical contact on one of the first plurality of regions, a second electrical contact on one of the second plurality of regions, and multiple grating pillars doped with the n-type doping or the p-type doping, each of the multiple grating pillars spaced apart from the PN junction and spaced apart from one another.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
22.
PACKET BUFFER LATENCY MITIGATION IN A NETWORK DEVICE
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
A network device includes a plurality of network interfaces and an ingress processor configured to process packets received by the network device to determine network interfaces, among the plurality of network interfaces, via which the packets are to be transmitted by the network device. The network device also includes a memory device configured to buffer packet data corresponding to the packets while the packets are being processed by the network device and a memory controller configured to select a buffering scheme for buffering a packet in the memory device based on a congestion state of a network interface via which the packet is to be transmitted. The buffering scheme is selected among a first buffering scheme having a first latency associated with buffering packet data and a second buffering scheme having a second latency, smaller than the first latency, associated with buffering packet data.
H04L 49/25 - Routing or path finding in a switch fabric
H04L 49/50 - Overload detection or protection within a single switching element
H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
H04L 49/103 - Packet switching elements characterised by the switching fabric construction using a shared central bufferPacket switching elements characterised by the switching fabric construction using a shared memory
A circuit and corresponding method generate a filtered timestamp. The circuit comprises recursive filter logic. The circuit generates the filtered timestamp from a received timestamp by filtering the received timestamp via the recursive filter logic. The recursive filter logic reduces jitter in the filtered timestamp relative to jitter of the received timestamp. The jitter represents a deviation of the received timestamp from a target (ideal) timestamp. The circuit outputs the filtered timestamp generated. The filtered timestamp is a more accurate representation of the target timestamp, relative to the received timestamp, due to the jitter reduced.
An integrated circuit includes current-mode circuitry implemented on a substrate. The current-mode circuitry includes i) a plurality of instances of a translinear circuit, and ii) a plurality of selection circuits coupled to respective instances of the translinear circuit, each selection circuit configured to selectively disable the respective instance of the translinear circuit. The current-mode circuitry is configured to generate a first output using one or more instances of the translinear circuit that are not disabled by one or more respective selection circuits. Drive circuitry is also implemented on the substrate and is coupled to the current-mode circuitry. The drive circuitry is configured to generate a second output using the first output of the current-mode circuitry.
A time-interleaved current-based digital-to-analog converter (current DAC) cell includes first input circuitry configured to receive a digital input signal, a first biasing voltage, a first clock, and a second clock. The first clock and the second clock having a phase offset from one another and having a common period. The current DAC also includes a first gate configured to, responsive to an ‘ON’ state of the first clock, pass the digital input signal to a second gate, the second gate being configured to, responsive to an ‘OFF’ state of the second clock, output a first DAC cell activation signal. The current DAC further includes first output circuitry configured to, responsive to the first DAC cell activation signal, output a first analog current signal based on (i) the digital input signal and (ii) the first biasing voltage.
H03M 1/68 - Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
An optical modulator includes a substrate defining a plane and first, second, and third PN junctions formed on the substrate. The first PN junction is formed on the substrate by a first region doped with a p-type doping abutting a second region doped with an n-type doping. The second PN junction is formed on the substrate adjacent to the second region of the first PN junction. The third PN junction is formed on the substrate adjacent to the first region of the first PN junction.
G02F 1/025 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
G02F 1/015 - Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulatingNon-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
A Media Access Control Security (MACsec) core architecture implements flow control and bandwidth management when bandwidth is expanded internally due to encryption overhead and packet injection. External flow control requests are merged with internal flow control states and sent to a connected host.
Disclosed are an on-chip reliability monitor and method. The monitor includes a test circuit with a test device, a reference circuit with a reference device, and a comparator circuit. The monitor periodically switches from operation in a stress mode, to operation in a test mode, and back. During each stress mode, the test device is subjected to stress conditions that emulate the operating conditions of an on-chip functional device while the reference device remains essentially unstressed. During each test mode, the comparator circuit compares a parameter of the test device to the same parameter of the reference device and outputs a status signal based on the difference between the parameters. When the status signal switches values, it is an indicator that the functional device has been subjected to a predetermined number of power-on-hours. Optionally, multiple monitors can be cascaded together to more accurately monitor stress-induced changes over time.
A method for communication includes receiving first data timed by a first clock and receiving a signal including second data timed by a second clock, which is independent of the first clock, and generating a stream of data samples corresponding to the second signal. The received first data are resampled responsively to a time-varying phase shift between the first and second clocks to generate resampled data timed by the second clock. The resampled data are applied in estimating and subtracting an alien crosstalk component from the stream of data samples.
An analog front-end device includes a sampler array and a clock bias circuit. The sampler array is configured to receive (i) an input signal and (ii) clock signals. The clock signals are received from a clocking circuit. The sampler array includes sampling circuits, where ones of the sampling circuits are each configured to sample and hold the input signal based on a respective one of the clock signals. The clock bias circuit is configured to adjust bias voltages of the clocking circuit to control sample timing of the sampling circuits.
A III-V semiconductor device in an optical transceiver includes a signal processing circuit. The signal processing circuit includes processing circuitry configured to receive or transmit an electrical signal corresponding to an optical signal, and feedback control circuitry communicatively coupled to the processing circuitry by a circuit loop. The feedback control circuitry is configured to sense a characteristic of the electrical signal, and based on the sensed characteristic, transmit over the circuit loop a feedback signal to the processing circuitry. The circuit loop includes a first transistor formed using a III-V semiconductor material and configured to function as a first sensing resistor having a first resistance value that limits loading applied to the processing circuitry by the feedback control circuitry.
H01S 5/068 - Stabilisation of laser output parameters
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
METHOD, SYSTEM AND DEVICE OF SERIALIZING AND DE-SERIALIZING THE DELIVERY OF SCAN TEST DATA THROUGH CHIP I/O TO REDUCE THE SCAN TEST DURATION OF AN INTEGRATED CIRCUIT
An integrated circuit verification system including automatic test equipment (ATE) and a device under test (DUT) having an internal test data de-serializer and test response data serializer. Specifically, the de-serializer of the DUT is able to de-serialize a test pattern or scan test data generated and received from an ATE at a general-purpose I/O pin (or functional pin) of the DUT for testing a circuit under test (CUT) of the DUT and then serialize the response to the test data with the serializer for output back to the ATE via the same or a different general-purpose I/O pin (or functional pin) of the DUT.
A III-V semiconductor device in an optical transceiver includes a signal processing circuit. The signal processing circuit includes processing circuitry configured to receive or transmit an electrical signal corresponding to an optical signal, and feedback control circuitry communicatively coupled to the processing circuitry by a circuit loop. The feedback control circuitry is configured to sense a characteristic of the electrical signal, and based on the sensed characteristic, transmit over the circuit loop a feedback signal to the processing circuitry. The circuit loop includes a first transistor formed using a III-V semiconductor material and configured to function as a first sensing resistor having a first resistance value that limits loading applied to the processing circuitry by the feedback control circuitry.
A programmable hardware system for machine learning (ML) includes a core and a streaming engine. The core receives a plurality of commands and a plurality of data from a host to be analyzed and inferred via machine learning. The core transmits a first subset of commands of the plurality of commands that is performance-critical operations and associated data thereof of the plurality of data for efficient processing thereof. The first subset of commands and the associated data are passed through via a function call. The streaming engine is coupled to the core and receives the first subset of commands and the associated data from the core. The streaming engine streams a second subset of commands of the first subset of commands and its associated data to an inference engine by executing a single instruction.
G06F 9/38 - Concurrent instruction execution, e.g. pipeline or look ahead
G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G06F 15/80 - Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
A semiconductor device package includes a semiconductor die having two opposing faces that define a major plane, wherein the semiconductor die generates heat when in operation. The package includes a packaging lid, contacts, a crystalline pedestal, and a layer of thermal interface material (TIM). The packaging lid encloses the semiconductor die. The contacts are on a first exterior surface of the package parallel to the major plane, the first exterior surface defining a bottom of the package. The crystalline pedestal is formed of one or more crystals having an anisotropic thermal property affecting a thermal conductivity of the pedestal to dissipate the heat generated by the die when in operation, and the pedestal is disposed above the die in thermally-conductive, electrically non-conductive contact with the semiconductor die. The layer of TIM is disposed between the pedestal and the lid, wherein the TIM is thermally conductive and electrically non-conductive.
A network device includes network interfaces, and respective sets of queues. The sets of queues includes a first set corresponding to a first network interface and a second set corresponding to a second network interface. The network device receives packets via network interfaces, and processes packets to determine network interfaces via which the packets are to be transmitted. When the first network interface is not being used by the network device, the network device operates a composite queue to store packets corresponding to the second network interface. The composite queue includes a first queue from the first set and a second queue from the second set. The network device stores packet data to and reads packet data from the composite queue at a rate that is greater than a maximum rate at which the first queue and the second queue are capable of storing and reading packet data.
An optoelectronic device (11, 70) includes: (a) a substrate (12) having (i) a surface (15), and (ii) a recess (14) formed in the substrate (12) that extends from the surface (15) into the substrate (12), (b) an integrated circuit (IC) chip (33, 33a, 33b) facing the surface of the substrate, (c) an optical connector (21a, 21b) mounted on the substrate (12), and (d) an optical chiplet (22, 22a, 22b) embedded within the recess (14) of the substrate (12). The optical chiplet (22, 22a, 22b) being configured to exchange (i) optical signals with the optical connector (21a, 21b), and (ii) electrical signals with the integrated circuit (IC) chip (33, 33a, 33b), and to convert between the optical signals and the electrical signals.
A network device includes network interfaces, and respective sets of queues. The sets of queues includes a first set corresponding to a first network interface and a second set corresponding to a second network interface. The network device receives packets via network interfaces, and processes packets to determine network interfaces via which the packets are to be transmitted. When the first network interface is not being used by the network device, the network device operates a composite queue to store packets corresponding to the second network interface. The composite queue includes a first queue from the first set and a second queue from the second set. The network device stores packet data to and reads packet data from the composite queue at a rate that is greater than a maximum rate at which the first queue and the second queue are capable of storing and reading packet data.
A method of reducing page walk latency resulting from a translation lookaside buffer (TLB) miss comprises providing a page fetch/walk logic module disposed between a coherent fabric and a memory controller. Upon receiving a notification of a TLB miss, performing, by the page fetch/walk logic module, a page table walk of a virtual address to produce a corresponding physical address. The method may further comprise forming, by a memory management unit, a TLB request that comprises a virtual address, and a request type field. The request type field may comprise (i) an indication that a TLB miss has occurred and (ii) a specification of a number of stages required of the page table walk.
A method for dynamically calibrating a time-interleaved digital-to-analog converter (DAC) includes receiving a digital input signal, generating, from the digital input signal, an output analog signal using DAC circuitry, generating, from the digital input signal, a model analog signal using DAC modeling circuitry, adjusting a digital model based on the model analog signal and the digital input signal, determining at least one of an offset error and a gain error based on comparing the output analog signal to the model analog signal, and generating an error correction signal based on the at least one of an offset error and a gain error.
In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.
A physical layer (PHY) device, for use in an Ethernet network, includes a cable interface, a transmitter, a receiver and a processor. The cable interface connects to an Ethernet link for communicating with a peer PHY device. The transmitter transmits outbound signals that carry outbound data to the peer PHY device over the Ethernet link. The receiver receives inbound signals that carry inbound data from the peer PHY device over the Ethernet link. The processor (i) controls the transmitter to transmit, to the peer PHY device, an outbound pre-alert signal indicating that the PHY device is about to start transmitting the outbound signals, and (ii) in response to receiving, via the receiver, an inbound pre-alert signal from the peer PHY device during a period in which the peer PHY device is abstaining from transmitting the inbound signals, controls the transmitter to abstain from transmitting the outbound signals.
An Ethernet physical layer (PHY) device, for use in an automotive network, includes a cable interface, a transmitter and a receiver. The cable interface is configured to connect to an Ethernet cable. The transmitter is configured to generate an outbound signal by modulating outbound data with a zero-disparity modulation at a first data rate, and to transmit the outbound signal to the Ethernet cable via the cable interface. The receiver is configured to receive, from the Ethernet cable via the cable interface, an inbound signal having a second data rate that is lower than the first data rate, the inbound signal at least partially overlapping the outbound signal in spectrum, and to demodulate the inbound signal to produce inbound data.
Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.
A hardware security module system, method and device including one or more security meshes that cover portions of a circuit board including the encryption/decryption component for determining if an unwanted physical access of the circuit board is occurring and disabling or erasing the hardware security module to prevent the unauthorized access of encryption data.
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors. The processor extracts features from the plurality of relative errors and the plurality of order of magnitude values and generates the error classification model based on the one or more features.
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06N 3/0442 - Recurrent networks, e.g. Hopfield networks characterised by memory or gating, e.g. long short-term memory [LSTM] or gated recurrent units [GRU]
A system includes a machine learning (ML) accelerator running a first code generated by a first compiler that generates a first plurality of tensors associated with one or more ML operations of a ML model. The system includes a processor that receives the first and the second plurality of tensors associated with the ML model. The second plurality of tensors is generated by a second code generated by a second compiler running on a hardware executing the one or more ML operations of the ML model. The processor generates a plurality of relative errors associated with the first and second plurality of tensors. The processor calculates an order of magnitude associated with the first plurality of tensors. The processor extracts features from the plurality of relative errors and the plurality of order of magnitude values and generates the error classification model based on the one or more features.
Techniques as described herein may be implemented to processing ingress packet traffic flows. A memory space that is divided into a packet buffer and an accelerated memory is defined. One or more congestion levels associated with ingress network traffic are determined. Upon enqueuing incoming packets, one or more memory locations are selected in the memory space for storing portions of each of the incoming packets based on at least one of the determined congestion levels.
An address translation system, method and device including a translation extension unit associated with a client and having a client address translation cache storing a client cache of the address translations. When virtual address of a translation request from the client is the same as the virtual address of an address translation of the client cache, the translation extension unit returns the physical address that is mapped to the virtual address according to the address translation to the client without transmitting the translation request to a memory management unit that maintains a page table of all the translations and a translation lookaside buffer with a subset of the translations.
G06F 12/0831 - Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 12/1045 - Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
51.
Hardware security module adapter system, method and device with active switch
A hardware security module system, method and device including one or more switches and a circuit board having pairs of security contact pads coupled with encryption/decryption and security components for determining if an unwanted physical access of the circuit board is occurring and disabling or erasing sensitive encryption/decryption data to prevent the unauthorized access of the data.
G06F 21/72 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
Path-specific delay variations in a computer communication network between a time-sensitive nexus node and time-sensitive non-nexus nodes are determined. The time-sensitive nexus node determines, based on the path-specific delay variations, copy-specific delay alignment compensations for copies of a multi-destination communication packet to be sent by the time-sensitive nexus node to the time-sensitive non-nexus nodes respectively. The time-sensitive nexus node uses the per-copy delay alignment compensations to perform per-copy delay alignment operations with respect to the copies of the multi-destination communication packet. The time-sensitive nexus node sends each copy in the copies of the multi-destination communication packet to a respective time-sensitive non-nexus node in the time-sensitive non-nexus nodes after a respective per-copy delay alignment operation in the per-copy delay alignment operations is performed for the copy of the multi-destination communication packet.
In a virtual network environment including a virtualized host administered by a hypervisor, a first network adapter coupling the host to a storage area network (SAN), an external storage device, and a second network adapter coupling the external storage device to the SAN, where the host includes a first virtual machine, and the first network adapter and the second network adapter are configured to establish an encrypted channel between themselves, for use by a virtual machine to communicate to the external storage device, managing the encrypted channel includes instantiating an additional virtual machine for executing security software, instantiating an emulated storage device associated with the hypervisor, instantiating at the additional virtual machine a respective virtual disk corresponding the emulated storage device, and transferring messages between the security software on the additional virtual machine and the first network adapter by encoding the messages in read/write requests to the virtual disk.
A method for converting an unknown analog voltage to a digital output signal includes receiving the unknown voltage, establishing a first stability threshold to distinguish between stable and metastable measurements of a voltage difference between the unknown voltage and a reference voltage, measuring that difference, determining whether the difference is greater or less than the first stability threshold, in response to determining that the difference is greater than the first stability threshold, yielding an output indicative of which one of the unknown and reference voltages is greater, in response to determining that the difference is less than the first stability threshold, overruling the output and assigning a predetermined output value indicative of which one of the unknown and reference voltages is greater, and deriving, from the output value indicative of which one of the unknown and reference voltages is greater, at least one bit of the digital output signal.
H03M 1/34 - Analogue value compared with reference values
H03M 1/38 - Analogue value compared with reference values sequentially only, e.g. successive approximation type
H03M 1/40 - Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
55.
Method and apparatus for determining bit-error rate in a data channel
A method for determining a bit-error rate in data received on high-speed data channel that uses a forward-error-correcting decoder includes receiving at receiver circuitry on the high-speed data channel a received predetermined data pattern, comparing, bit-wise, the received predetermined data pattern to a locally generated copy of the predetermined data pattern to derive output bits representing whether there was an error in a corresponding bit of the received predetermined data pattern, to determine error bits in the received predetermined data pattern, grouping output bits from the comparing into symbols and codewords, and for each codeword for which a count of symbols containing errors exceeds a number of symbols correctable by the forward-error-correcting decoder, counting a total number of bit errors contained in the symbols containing errors, for use in adjusting the receiver circuitry in response to the total number of bit errors.
H03M 13/01 - Coding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
56.
Spread spectrum modulation over an asymmetric ethernet link
An automotive Ethernet physical-layer (PHY) transceiver includes an Analog Front End (AFE) and a digital processor. The AFE is coupled via a full-duplex Ethernet link to a peer transceiver. The AFE is configured to receive from the peer transceiver, over the full-duplex Ethernet link, an analog Ethernet signal conveying data symbols, at a reception data rate that is lower than a transmission data rate used in transmitting data from the PHY transceiver to the peer transceiver, the Ethernet signal being modulated by a spreading sequence having a Spreading Factor including a ratio between a spreading chip-rate and the reception data rate, and to convert the received analog Ethernet signal into a digital signal. The digital processor is configured to de-spread the digital signal using the spreading sequence to recover the data symbols.
An optical communication receiver includes: a photodiode and signal processing circuitry coupled to the photodiode. The photodiode is configured to receive a modulated optical signal conveying data and convert the modulated optical signal to an electrical signal. The photodiode includes: a waveguide configured to receive the modulated optical signal; an absorption region above the waveguide; and a capacitor electrically coupled in series with the absorption region to reduce a capacitance of the photodiode as compared to a scenario in which the capacitor is omitted from the photodiode. The signal processing circuitry is configured to process the electrical signal to extract and output the data.
H10F 30/00 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
58.
System and Method for User Devices in Cloud Computing Environment
A system and corresponding method consumerize cloud computing by incorporating consumer devices into an infrastructure of cloud computing environment. The consumer device comprises a client job manager that spawns a processing task on the consumer device responsive to a job request to perform at least a portion of a computational job. The computational job is requested by an end user device to be performed via cloud computing. The consumer device further comprises a network interface. The job request is received via the network interface from a cloud job manager of a cloud service provider system of a cloud service provider. The processing task performs the at least a portion of the computational job. The consumer device is selected by the cloud job manager based, at least in part, on proximity of the consumer device to the end user device and at least one characteristic of the consumer device. The client job manager communicates the at least one characteristic to the cloud job manager via the network interface.
H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
H04L 67/1029 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers using data related to the state of servers by a load balancer
59.
Method and system for performing a compaction/merge job using a merge based tile architecture
A hardware-based compaction accelerator may comprise two or more decoders, a merge iterator, a compaction module, and an encoder. Each of the decoders converts a sorted string table (SST) files into a corresponding key-value (KV) format data stream. The merge iterator receives a KV format data stream from each of the decoders, and combines the KV format data streams into a single KV format data stream. The compaction module receives the composite KV format data stream and produces a compacted data stream. The compacted data stream contains less data that is in the composite KV format data stream. The encoder converts the composite KV format data stream back into one or more output SST files. The compaction accelerator may be configured to perform only a subset of the processing available from the decoders, merge iterator, compaction module, and encoder, and may be configured through the Internet using a cloud-based processor.
A wireless network interface of a first client station negotiates with an access point a first component channel of an operating channel via which the first client station is to receive wakeup frames from the access point. A wakeup radio of the first client station receives a wakeup packet from the access point. The wakeup packet spans the operating channel, which comprises at least four component channels, and one or more of the component channels within the operating channel are punctured so that the access point does not transmit the wakeup packet in the one or more component channels that are punctured. The wakeup packet includes a first wakeup frame for the first client station in the first component channel and one or more respective second wakeup frames for one or more second client stations in one or more respective second component channels.
An optical communication receiver includes: a photodiode and signal processing circuitry coupled to the photodiode. The photodiode is configured to receive a modulated optical signal conveying data and convert the modulated optical signal to an electrical signal. The photodiode includes: a waveguide configured to receive the modulated optical signal; an absorption region above the waveguide; and a capacitor electrically coupled in series with the absorption region to reduce a capacitance of the photodiode as compared to a scenario in which the capacitor is omitted from the photodiode. The signal processing circuitry is configured to process the electrical signal to extract and output the data.
H10F 30/223 - Individual radiation-sensitive semiconductor devices in which radiation controls the flow of current through the devices, e.g. photodetectors the devices having potential barriers, e.g. phototransistors the devices being sensitive to infrared, visible or ultraviolet radiation the devices having only one potential barrier, e.g. photodiodes the potential barrier being a PIN barrier
H10F 71/00 - Manufacture or treatment of devices covered by this subclass
H10F 77/00 - Constructional details of devices covered by this subclass
H10F 77/122 - Active materials comprising only Group IV materials
An optical communication receiver includes an optical input configured to receive from a communication link a modulated optical wave conveying data over the communication link, and a multimode waveguide, which is coupled to receive the modulated optical wave from the optical input and has a width that is selected to cause the modulated optical wave to form multiple interference maxima over an area of the multimode waveguide. The optical communication receiver further includes multiple optical detectors disposed over the multimode waveguide in alignment with respective ones of the interference maxima and configured to output electrical signals in response to optical energy absorbed by the optical detectors from the multimode waveguide, and signal processing circuitry coupled to process and demodulate the electrical signals so as to extract and output the data.
H04B 10/80 - Optical aspects relating to the use of optical transmission for specific applications, not provided for in groups , e.g. optical power feeding or optical transmission through water
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H04B 10/69 - Electrical arrangements in the receiver
64.
FLOWLET SCHEDULER FOR MULTICORE NETWORK PROCESSORS
Systems and methods of using a packet order work scheduler (POWS) to assign packets to a set of scheduler queues for supplying packets to parallel processing units. A processing unit and the associated scheduler queue are dedicated to a specific flow until a queue-reallocation event, which may correspond to the associated scheduler queue being idle for at least a certain interval as indicated by its age counter, or the queue being the least recently used, when a new flow arrives. In this case, the scheduler queue and the associated processing unit may be reallocated to the new flow and disassociated with the previous flow. As a result, dynamic packet workload balancing can be advantageously achieved across the multiple processing paths.
The present invention relates to data communication systems and methods thereof. In a specific embodiment, a receiver includes a trigger circuitry that selects a subset of encoded data blocks to measure the performance of a communication lane. Partial syndromes—based on these partial data blocks—are used in partial syndrome calculations, and they are later combined to form full syndromes. A decoder is configured to decode the full syndromes. There are other embodiments as well.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H04L 1/20 - Arrangements for detecting or preventing errors in the information received using signal-quality detector
A network devices includes multiple components including respective clocks that are synchronized with a global time. Each component includes one or more sensors and/or error detection circuitry that generate telemetry data. Each component associates the telemetry data with the global time, which enables time-correlation of telemetry data from the different components within the network device and/or from other network devices that also generate telemetry data associated with the global time.
Methods and apparatus for enhancing network data processing using compressing data streams are disclosed. The process, in one aspect, is configured to receive a data stream through a receiver via a communication network. Upon identifying compressed data and an encoder identifier carried by the data stream, a decoder database is determined in the receiver. After retrieving a decoder from the decoder database in response to the encoder identifier, the process is configured to decompress the compressed data facilitated by the decoder for generating scaler data.
A Physical Layer (PHY) transceiver includes communication circuitry and a controller. The communication circuitry includes a digital filter, and is configured to communicate signals using the digital filter over a network link. The controller is configured to monitor a temperature pertaining to the communication circuitry, and, in response to detecting an actual or predicted over-temperature condition, to degrade a functionality of the digital filter so as to reduce power dissipation in the communication circuitry.
H04B 1/38 - Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
A cable assembly includes: a first connector connecting the cable assembly to a first switch, where the first switch has a first network path to a first host device; a second connector connecting the cable assembly to a second switch, where the second switch has a second network path to the first host device; and a third connector connected to the first connector via a first cable, connected to the second connector via a second cable, and connecting the cable assembly to a second host device. Protection switching circuitry embedded in the cable assembly: establishes a communications connection to transfer data between the first and second host devices using a first data path; and responsive to determining that the first data path has been degraded, switches without external intervention the communications connection from the first data path to a second data path.
The present disclosure describes apparatuses and methods for implementing secure verification of a physical unclonable function (PUF). In various aspects, a PUF verifier generates a PUF reagent value by obtaining a key from a PUF and a message value useful for PUF verification. The PUF verifier computes a digest value of the PUF key and the message value and selects a portion of the hash digest as a PUF reagent value. The PUF verifier writes the PUF reagent value to a non-volatile memory to enable subsequent verification of the PUF. The PUF verifier may also generate error-correction code information for the PUF reagent value and write this information to the non-volatile memory to enable error correction. Upon device hardware reset, the PUF verifier can securely verify PUF operation by generating a PUF key hash digest and comparing the hash digest with the PUF reagent value without exposing the PUF key.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
A communication device, consisting of at least one semiconducting die and an electronic integrated circuit (EIC) formed on a first side of the at least one die. The device also has at least one first array of micro-light emitting diodes (micro-LEDs), mounted on a second side of the at least one die that is opposite the first side. The micro-LEDs are electrically connected to the EIC and are configured to transmit outbound optical signals to respective first optical fibers. The device also has at least one second array of photo-diodes, mounted on the second side of the at least one die. The photo-diodes are electrically connected to the EIC and are configured to receive inbound optical signals from respective second optical fibers.
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
72.
MULTI-DATAPATH SUPPORT FOR LOW LATENCY TRAFFIC MANAGER
Techniques as described herein may be implemented to support processing CT and SAF traffic. A common packet data buffer is allocated to store incoming CT and SAF packet data. SAF packet control data are directed onto a control data path with first processing engines, to arrive at a scheduler with a first latency. CT packet control data are directed onto a second control data path to arrive at the scheduler with a second latency less than the first latency after processing in the second control path by second processing engines bypassing a subset of the first processing engines. CT and SAF packet dequeue requests are generated for CT and SAF packets, respectively, using the CT and SAF packet control data and merged into a merged sequence of dequeue requests to retrieve corresponding packet data from the common packet data buffer based on the merged sequence of dequeue requests.
A communication device (22), consisting of at least one semiconducting die (38) and an electronic integrated circuit (EIC) (14A) formed on a first side (34) of the at least one die. The device also has at least one first array of micro-light emitting diodes (micro-LEDs) (50), mounted on a second side (54) of the at least one die that is opposite the first side. The micro-LEDs are electrically connected to the EIC and are configured to transmit outbound optical signals to respective first optical fibers. The device also has at least one second array of photo-diodes (60), mounted on the second side of the at least one die. The photo-diodes are electrically connected to the EIC and are configured to receive inbound optical signals from respective second optical fibers.
An optical device includes a substrate and a single-mode optical waveguide disposed on the substrate and having a first geometrical width chosen to guide optical radiation in a first optical mode within a given wavelength range through the single-mode optical waveguide. An optical ring waveguide is disposed on the substrate and optically coupled to the single-mode optical waveguide, the optical ring waveguide having a second geometrical width wider than first geometrical width and configured to maintain therewithin optical radiation in the given wavelength range in a second optical mode different from the first optical mode.
G02B 6/293 - Optical coupling means having data bus means, i.e. plural waveguides interconnected and providing an inherently bidirectional system by mixing and splitting signals with wavelength selective means
A semiconductor device includes circuitry configured for faster bitcell operation. That circuitry includes a plurality of bitcells readable as one of a ‘0’ value and a ‘1’ value, and voltage generation circuitry configured to apply an activation voltage to activate selected bitcells in the plurality of bitcells for reading. The voltage generation circuitry is further configured to switch between an overdrive mode and a steady-state mode where the voltage generation circuitry applies a first voltage during the overdrive mode and the voltage generation circuitry applies a second voltage, less than the first voltage, during the steady-state mode, interconnect circuitry configured to couple the plurality of bitcells to reading circuitry. The reading circuitry is configured to receive a differential signal from a bitcell and amplify the differential signal to a full digital logic level. The full digital logic level corresponds to one of the ‘0’ value and the ‘1’ value.
A system includes a hardware security module (HSM) configured to receive an artificial intelligence (AI) request sent by an application. The AI request is a request to perform one or more AI related operations. The HSM is configured to perform one or more cryptographical operations associated with the one or more AI related operations. The HSM is configured to send a result of the one or more cryptographical operations associated with the one or more AI related operations to an AI processor. The system also includes the AI processor configured to receive the result of the one or more cryptographical operations associated with the one or more AI related operations from the HSM. The AI processor is configured to perform the one or more AI related operations.
A hardware security module (HSM) includes a first HSM instance and a second HSM instance. The first HSM instance is configured to process a first type of service request. The second HSM instance is configured to process a second type of service request. The first HSM instance and the second HSM instance are physically on a same HSM. The first HSM instance is logically separated from the second HSM instance. The first type of service request is a service request that differs from the second type of service request.
G06Q 20/40 - Authorisation, e.g. identification of payer or payee, verification of customer or shop credentialsReview and approval of payers, e.g. check of credit lines or negative lists
78.
HEATSINK FOR CO-PACKAGED OPTICAL SWITCH RACK PACKAGE
An optical module includes a processor and light engines on a substrate and a heat sink in thermal communication with the processor and the light engines. The light engines are configured to transmit and receive optical data and are disposed at different locations around the processor on the substrate. The processor is configured to control each of the plurality of light engines. During operation, each of the processor and the light engines is operable to generate a different amount of heat relative to each other as the optical data is transmitted and received. The heatsink comprises a plurality of heat pipes non-uniformly distributed throughout the heatsink to remove, from the substrate, the different amounts of the heat generated by the processor and each of the plurality of light engines.
H05K 7/20 - Modifications to facilitate cooling, ventilating, or heating
G02B 6/42 - Coupling light guides with opto-electronic elements
G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H04Q 11/00 - Selecting arrangements for multiplex systems
79.
System and Method for User Devices in Cloud Computing Environment
A system and corresponding method consumerize cloud computing by incorporating consumer devices into an infrastructure of cloud computing environment. The consumer device comprises a client job manager that spawns a processing task on the consumer device responsive to a job request to perform at least a portion of a computational job. The computational job is requested by an end user device to be performed via cloud computing. The consumer device further comprises a network interface. The job request is received via the network interface from a cloud job manager of a cloud service provider system of a cloud service provider. The processing task performs the at least a portion of the computational job. The consumer device is selected by the cloud job manager based, at least in part, on proximity of the consumer device to the end user device and at least one characteristic of the consumer device. The client job manager communicates the at least one characteristic to the cloud job manager via the network interface.
H04L 47/783 - Distributed allocation of resources, e.g. bandwidth brokers
H04L 67/1029 - Protocols in which an application is distributed across nodes in the network for accessing one among a plurality of replicated servers using data related to the state of servers by a load balancer
80.
Delivering electrical power and data signals from the backside of integrated circuit device
An electronic device includes: (a) a substrate having transistors formed in the substrate frontside, (b) nano-vias (NVs) formed in the substrate and configured to electrically couple at least some of the transistors at least to the substrate backside, the NVs include power NVs configured to conduct at least electrical power between the substrate backside and the transistors, and signal NVs configured to conduct data signals at least between the substrate frontside and backside, (c) frontside interconnects formed on the substrate frontside and configured to conduct the data signals between the transistors and the signal NVS, and (d) backside interconnects formed on the substrate backside and configured to conduct (i) the electrical power between the power NVs and the power terminals and (ii) the data signals between the signal NVs and the signal terminals, the power terminals and the signal terminals are disposed between the backside interconnects and a package substrate.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A memory array includes a plurality of memory devices, each of which includes a memory configured to store packet data and a request arbiter configured to interface with other memory devices of the memory array. The request arbiter filters invalid requests from a plurality of requestors, and determines a bitvector representing a sequence of the plurality of requestors, the bitvector indicating whether each of the plurality of requestors has a valid request. The request arbiter outputs an indication of a first request to be serviced by the memory device, and shifts the bitvector to determine a second request to be serviced by the memory device.
A method of reducing jitter in transmission of a timestamp across a clock domain boundary includes storing N timestamps, generated in N successive clock cycles of an origin clock domain, in N parallel buffers in the origin clock domain under control of a modulo-N counter, transmitting outputs of the N parallel buffers across the clock domain boundary into a destination clock domain along with the modulo-N counter, processing the modulo-N counter in the destination clock domain to derive a selection signal that selects a stable timestamp from among the outputs of the N parallel buffers, and outputting the selected stable timestamp. The modulo-N counter may be Gray-coded modulo-N counter to reduce jitter in the modulo-N counter across the clock domain boundary.
H04J 3/16 - Time-division multiplex systems in which the time allocation to individual channels within a transmission cycle is variable, e.g. to accommodate varying complexity of signals, to vary number of channels transmitted
A first communication interface of a communication device receives a data signal having first alignment markers (AMs), and the communication device determines respective locations of the first AMs in the data signal. The communication device processes the data signal, including i) removing the first AMs from the data signal and ii) inserting second AMs in the data signal at the locations at which the first AMs were removed from the data signal. A second communication interface of the communication device transmits the data signal. The communication device measures a latency of the data signal between reception of the data signal at the first communication interface and transmission of the data signal by the second communication interface.
A first communication interface of a communication device receives a data signal having first alignment markers (AMs), and the communication device determines respective locations of the first AMs in the data signal. The communication device processes the data signal, including i) removing the first AMs from the data signal and ii) inserting second AMs in the data signal at the locations at which the first AMs were removed from the data signal. A second communication interface of the communication device transmits the data signal. The communication device measures a latency of the data signal between reception of the data signal at the first communication interface and transmission of the data signal by the second communication interface.
A hybrid electrical and optic system-on-chip (SOC) device configured for both electrical and optic communication includes a substrate, an electrical device configured for electrical communication arranged on the substrate, a photonics device configured for optic communication arranged on the substrate, and a self-test module arranged on the substrate. The self-test module is configured to receive a loop-back signal indicative of an optical signal output from the photonics device and calibrate the photonics device based on the loop-back signal.
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
G02B 6/12 - Light guidesStructural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
G06F 13/364 - Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
A network includes a first plurality of nodes operating in a first clock domain based on a first clock source, a second plurality of nodes operating in a second clock domain based on a second clock source, and synchronization circuitry accessible to both of the clock domains without requiring network traffic between the clock domains. The synchronization circuitry is configured to periodically calculate a drift rate between the time of day in the respective clock domains. Each node in one of the clock domains is configured to, when sending a message to a node in the other of the clock domains, calculate a time of day in the other of the clock domains based on an actual time of day in the one of the clock domains and the drift rate, and to include, in the message to the node in the other clock domain, the calculated time of day.
An Integrated Circuit (IC) for use in a network device includes a receiver and a Link Quality Estimation Circuit (LQEC). The receiver is configured to receive a signal over a link and to process the received signal. The LQEC is configured to predict a link quality measure indicative of communication quality over the link in the future, by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.
An optoelectronic device includes an optical gain medium having a first end and a second end and configured to amplify laser radiation within a gain band, a laser cavity containing the optical gain medium and including a first reflector disposed at the first end of the optical gain medium and a second reflector disposed at the second end of the gain medium and including an interferometer having a tunable reflectance band. The optoelectronic device further includes a controller configured to tune the reflectance band of the interferometer so as to modify a spectrum of the laser radiation emitted from the gain medium through the first reflector.
A system includes a controller configured to receive a cellular configuration data and a network traffic data. The cellular configuration data is associated with a plurality of cells within a wireless network. The system includes an on-chip shared memory configured based on the cellular configuration data into a plurality of memory bank groups. Each memory bank group includes a number of memory banks. A first subset of memory bank groups is associated with an uplink slot. A second subset of memory bank groups is associated with a downlink slot. The first subset of memory bank groups associated with the uplink slot is clocked off in response to the network traffic data being associated with a downlink slot. The second subset of memory bank groups associated with the downlink slot is clocked off in response to the network traffic data being associated with an uplink slot.
A new approach is proposed that contemplates system and method to support multiple error detection and/or correction mechanisms via flexible on-chip memory (OCM) configurations. Here, an OCM includes a plurality of memory banks, wherein each of the plurality of memory banks includes a plurality of memory instances. Under the proposed approach, a first subset of the plurality of memory banks are configured to support a first type of error detection and/or correction mechanism while a second subset of the plurality of memory banks are configured to support a second type of error detection and/or correction mechanism. Moreover, a subset of memory instances within one or more of the plurality of memory banks are configured to store data and extra code words at the same time in order to efficiently support a specific type of error detection and/or correction mechanism.
A system includes a controller that receives a data for a slot and processes the data in a first power mode and assign jobs associated with the data to one or more accelerators or one or more DSP cores. A scheduler receives the jobs assigned by the controller and schedules the jobs for execution by the at least one or more hardware accelerators and the one or more DSP cores. An event manager manages power modes for the controller. The controller transitions from the first power mode to a second power mode after the controller completes the processing of the data associated with the slot. The second power mode is a lower power mode in comparison to the first power mode when the controller is processing the data. The event manager transitions the controller from the second power mode to the first power mode in response to a triggering event.
An electronic device package, consisting of a planar package substrate defining a package footprint. The package also includes one or more micro-devices surface mounted on and configured to electrically couple to the package substrate via an array of surface mount terminals. A vapor chamber lid overlays the one or more micro-devices and the vapor chamber lid has planar dimensions that are smaller than the package footprint.
H01L 23/427 - Cooling by change of state, e.g. use of heat pipes
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
93.
Adaptive analog equalization in ADC-based receiver
An analog-to-digital converter-based serial receiver configured to tune analog equalization settings for link training is described. An analog signal from a transmitter is received and the receiver applies initial analog equalization settings. The receiver then converts the equalized analog signal into a digital signal. The receiver then measures frequency content of the analog signal and saturation at the analog-to-digital converter and determines updated analog equalization settings.
An optical transmitter includes a DAC, a timing circuit, and circuitry. The DAC includes switches configured to convert digital data into analog data that is modulated into an optical signal for transmission over an optical fiber. The timing circuit is configured to generate timing signals to control the switches of the DAC. The circuitry is configured to control an output data rate of the DAC by biasing the switches based on a logical combination of the digital data and the timing signals. An optical transmitter includes DACs and a driver. The DACs are configured to receive digital data at a first data rate and to output currents at a second data rate that is greater than the first data rate. The driver is configured to receive a combined current comprising the currents output by the DACs and to generate an output signal that is proportional to the combined current.
An access point (AP) device transmits a first downlink transmission via a first WLAN communication channel having a first radio frequency (RF) bandwidth, and transmits a second downlink transmission via a second WLAN communication channel having a second RF bandwidth. The second downlink transmission including a trigger frame configured to prompt one or more client stations to transmit one or more respective acknowledgments of one or more packets transmitted by the AP device via the first WLAN communication channel. The AP device receives one or more uplink transmissions from the one or more respective client stations. The one or more uplink transmissions from the one or more respective client stations are received via the second WLAN communication channel. The one or more uplink transmissions via the second WLAN communication channel overlap in time with the first downlink transmission via the first WLAN communication channel.
A switch device is configured to communicate with a plurality of hosts and a solid state drive (SSD). The plurality of hosts includes a first host and a second host. The switch device receives a first memory access command from the SSD, the first memory access command including an indication of the first host to indicate the first memory access command is intended for the first host. The switch device uses the indication of the first host in the first memory access command to route the first memory access command to the first host. The switch device removes the indication of the first host from the first memory access command prior to sending the first memory access command to the first host via a peripheral computer interface express (PCIe) interface of the switch device.
09 - Scientific and electric apparatus and instruments
Goods & Services
(1) Data processors used in computers, security sub-systems networking equipment, namely, hardware accelerators, offload engines, crypto chips and other networking equipment, namely, routers, switches, load-balances, web-servers, firewalls, virtual private network gateways and other computer equipment, namely, servers and work stations
98.
Meeting performance and temperature requirements in electronic circuits
An Integrated Circuit (IC) includes an electronic circuit and a controller. The electronic circuit is designed to operate at temperatures above a specified minimal temperature. The IC has a controllable operational parameter that affects a performance measure of the electronic circuit and an amount of heat produced by the electronic circuit. The controller is configured to control the operational parameter so as to meet both requirements concurrently: (i) exceeding a specified minimal performance level of the performance measure, and (ii) a local temperature of the electronic circuit exceeding the specified minimal temperature.
A new approach is proposed that contemplates system and method to support security enhancement for a hardware security module (HSM) using artificial intelligence (AI). Specifically, one or more AI models are trained with datasets of the HSM to establish a pattern of normal/typical behaviors for each of a plurality of applications requesting services of the HSM. While the HSM is running, an AI security module running on the HSM is configured to continuously monitor and analyze service requests from the plurality of applications to the HSM using the one or more trained AI models to identify security breaches/threats. If the AI models detect an anomaly or a deviation from its normal pattern of behaviors, the AI security module marks the application as a potential security threat and stops the HSM from performing a cryptographic operation requested by the application.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A network interface device operates in a normal operating mode in which the network interface device continually receives transmission symbols via a communication link. The network interface device determines that the network interface device is to transition to a low power mode, and in response transitions receiver circuitry to the low power mode. During a transition time period corresponding to determining that that the network interface device is to transition to the low power mode, the network interface device ignores signals received via the communication link.
