A method, system, and computer program product receive constraints for execution of a workload on one or more trusted execution environments from a plurality of entities. The constraints form a constraint space. An execution requirement for controlling the trusted execution environment(s) using the constraints is automatically generated. The execution requirement defines parameters for executing the workload in compliance with the constraints. The automatically generating includes adding identifiers of the constraints to the execution requirement for an attestation of constraints being complied with by the trusted execution environment(s) when executing the workload in compliance with the execution requirement. The trusted execution environment(s) are controlled in compliance with the execution requirement. The controlling includes providing the execution requirement to the trusted execution environment(s), which enables the trusted execution environment(s) to provide one or more attestation records for an attestation of the execution. The attestation records include the identifiers.
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
2.
MANAGING CONTAINERS USING DATA STRUCTURE FOR FIXING SECURITY VULNERABILITIES AND EXPOSURES
A computer-implemented method for managing containers. A processor set retrieves a container image from a container repository. The container image is retrieved by a host comprising a copy of the container image. The processor set updates the copy of the container image on the host based on filesystems in the container image retrieved from the container repository and metadata for the application packages associated with the container image retrieved from the container repository. The processor set creates a data structure comprising information for fixing security vulnerabilities and exposures for containers based on the metadata for the application packages, information associated with the application packages, and information associated with containers for the container image on the host.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/54 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par ajout de routines ou d’objets de sécurité aux programmes
3.
ON-CHIP VOLTAGE REGULATION WITH DYNAMIC SHUNT CURRENT CONTROL
Embodiments herein describe circuitry and techniques to implement shunt current control of an on-chip voltage regulator of a memory storage system using hardware components and computer software tools. Disclosed embodiments provide an on-chip voltage regulator with enhanced performance, reducing power requirements, and minimizing noise and voltage fluctuations of the regulator output, based on a cache activity signal produced by a cache controller.
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
4.
SEMICONDUCTOR DEVICE WITH GATE STRAP IN STI REGION
In an attempt to reduce congestion in the upper layers and improve efficiency in semiconductor devices, embodiments comprise a semiconductor device that comprises a substrate, a shallow trench isolation (STI) layer formed on the substrate. The semiconductor device also includes comprises a first gate, a second gate, and a gate strap connecting the first gate to the second gate. The gate strap is formed in the STI layer.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Deposit and cure, on a first heat transfer component, a porous organo-silicate material. Fill connected porosity of the deposited and cured porous organo-silicate material with a thermally conductive material. Bond the porous organo-silicate material having the filled connected porosity to a second heat transfer component.
F28F 3/06 - Éléments ou leurs ensembles avec moyens pour augmenter la surface de transfert de chaleur, p. ex. avec des ailettes, avec des évidements, avec des ondulations les moyens pouvant être fixés sur l'élément
C09K 5/14 - Substances solides, p. ex. pulvérulentes ou granuleuses
C23C 14/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques
Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a non-volatile memory unit cell. The non-volatile memory unit cell includes a top electrode in contact with a bit line. Additionally, the non-volatile memory unit cell includes a bottom electrode in contact with a select line. Further, the non-volatile memory unit cell includes a thin film electrode in contact with the bottom electrode. Additionally, the non-volatile memory unit cell includes a dielectric in contact with the top electrode and the thin film electrode. Further, the non-volatile memory unit cell includes a layer of phase change material including memristive channels. Additionally, the layer of phase change material is in contact with the dielectric. Further, the memristive channels are in contact with the top electrode, the thin film electrode, and the dielectric.
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first area having a back-end-of-line (BEOL) region that includes a first set of vias; a metal level with one metal line above the first set of vias; and a second set of vias above the metal level; and a second area having a metal stub, where a bottom surface of the metal stub is substantially aligned with a bottom surface of the first set of vias and a top surface of the metal stub is substantially aligned with either a top surface of the one metal line of the metal level or a top surface of the second set of vias, and where the metal stub has a horizontal width that is at least 10 times larger than a width of the one metal line. A method of forming the semiconductor structure is also provided.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
8.
PROACTIVE RESERVATION OF FIELD REPLACEABLE UNITS USING PREDICTIVE FAILURE ANALYSIS AND ANALYTICS
A computational device determines whether a generated system event in the computational device is a critical error or a non-critical error. In response to determining that the generated system event is a critical error caused by a first field-replaceable unit (FRU), the critical error is processed to initiate tasks that lead to replacement of the first FRU in the computational device to eliminate the critical error. In response to determining that the generated system event is a non-critical error caused by a second FRU, operations are performed to proactively reserve a substitute FRU to replace the second FRU to eliminate the non-critical error, in anticipation of the second FRU failing at a future time to cause another critical error.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
Method and apparatus for providing users role-based system log entry access are described. This can be implemented using a data controller that can read and implement a policy that determines what portion of the total system log certain users (or user groups) are permitted to access. In turn, it may curate a redacted system log and present it to the user that sent the request for the system log. The data controller may act as an intermediate layer between a user wishing to view a system log, the system log itself.
Access to log event data and corresponding source code is obtained and static code analysis is performed on the source code to produce analysis output. First vectors representing the log event data and second vectors representing the analysis output are generated. A similarity analysis is performed on the first vectors and the second vectors. A probabilistic relevance score associating a given log event with a segment of the source code is determined based on the similarity analysis. A visualization is generated for log events based on the probabilistic relevance score.
An embodiment includes detecting a future terrain metric by a vehicle. The embodiment includes responsive to detecting the future terrain metric, computing a sensor adjustment metric based on a current terrain metric and the future terrain metric. The embodiment also includes adjusting an onboard sensor of the vehicle based on the sensor adjustment metric.
A semiconductor device includes front end of line (FEOL) devices arranged in a FEOL layer defining a frontside and a backside opposite the frontside. A single composition dielectric material covers the FEOL devices and is disposed in shallow trench isolation regions between the FEOL devices. The dielectric material has voids disposed therein that provide airgaps between the FEOL devices.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A top-down inspection system and method employs a strategy using specific geometric shaped metal alignment markers on a semiconductor die and a laminate that can be inspected using an IR camera. The metal alignment markers will align at room temperature to assess the die alignment prior to reflowing it. As silicon is transparent to IR wavelengths the system allows for the IR light to pass through the die to the laminate to see alignment features on the die and the laminate concurrently. The specific markers are placed in at least two separate locations preferably >0.5*die size apart. The robust alignment markers are substantially resistant to degradation caused by semiconductor device fabrication steps. The metal alignment markers can be small geometrical shapes to provide a more symmetrical signal which is more resistant to variability in prior processing steps than the standard marker design.
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
Techniques for improved computing error analysis are provided. An error log for a computing environment is accessed, and an error analysis window is opened based on the error log, the error analysis window having an initial duration. A set of additional error logs, for the computing environment, within the error analysis window are accessed. Based at least in part on the set of additional error logs, a window extension is determined. The error analysis window is extended based on the window extension, and an error summary is generated based on one or more error logs received during the extended error analysis window.
A method of method of fabricating a semiconductor device includes providing a semiconductor structure having a sheet of vertically stacked formations including alternating semiconductor layers and sacrificial layers, surrounded by a layer of dummy gate material. The sacrificial layers are removed from the sheet leaving empty channels between the semiconductor layers. A gate oxide is deposited in the empty channels. The gate oxide wraps around the semiconductor layers in the sheet and defines layers of gate oxide. The layers of gate oxide are etched inward from a space between the vertically stacked formations, forming pockets between the layers of semiconductor. A dielectric spacer is deposited into the pockets. A source and drain formation is deposited into the space between the vertically stacked formations. The layer of dummy gate material is removed. The layers of gate oxide are removed. A gate is formed in contact with the semiconductor layers.
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A structure for extracting thermal resistance in semiconductor device includes first and second sensor arrays. Each sensor array of the first and second sensor arrays includes a heater; a first temperature sensor configured to measure temperature of the heater; and second and third temperature sensors on opposite sides of the heater. The heater and the temperature sensors of the first sensor array are along a first thermal path to ambient. The heater and the temperature sensors of the second sensor array are along a second thermal path to ambient. The first thermal path to ambient has a measurably different thermal resistance than the second thermal path to ambient.
A method, system, computer program product, and computer program for managing data in a storage system, the storage system comprising: a set of subsystems comprising: a structure comprising a set of mappings between logical and mapped addresses; and a storage device comprising a first data version at a first mapped address; the method comprising: for at least one substructure: providing, in the structure, for the first logical address, a verified pointer to the first mapped address; writing a second data version for a second mapped address, the second mapped address different from the first mapped address; providing, in the structure, for the first logical address a write-head pointer to the second mapped address; gathering the second data version to determine metadata for the second data version, the metadata associated with an indicator; in response to the indicator comprising a verify indicator; updating the verify pointer to the second mapped address.
A process includes providing a reactor containing a compound of the formula SiOx, wherein 0≤x≤2, and receiving, at the reactor, fluorinated gas. The process also includes obtaining a gaseous mixture formed at an elevated temperature in the reactor and removing silicon tetrafluoride from the gaseous mixture. An apparatus includes a reactor containing a compound of the formula SiOx, wherein 0≤x≤2, a component for receiving fluorinated gas at the reactor, a heating element for heating the compound of the formula SiOx and the fluorinated gas in the reactor, and a separation component for removing silicon tetrafluoride from a gaseous mixture formed in the reactor. A process of semiconductor manufacturing includes defluorinating exhaust gas using the process. A system for semiconductor manufacturing includes a set of components for carrying out the process.
C01B 33/027 - Préparation par décomposition ou réduction de composés de silicium gazeux ou vaporisés autres que la silice ou un matériau contenant de la silice
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
19.
Predicting Work Effort for Porting Software Projects Across Disparate Platforms
Predicting porting work effort is provided. A total porting work effort to port a software project from a source platform to a disparate target platform is predicted using a first porting work effort, a second porting work effort, and a third porting work effort. The software project is ported from the source platform to the disparate target platform based on the total porting work effort being less than a defined maximum porting work effort threshold level.
In a module of a tape head having multiple modules, a beam support member of at least one module has an alignment leg portion projecting from a body portion of the beam support member at a position displaced from the ends of the beam support member. The alignment leg of one module is matched with the alignment leg of another module to maximize glue adhesion between the legs and minimize positional drifting of the modules after glue curing in a staggered orientation. In another aspect, the support surface of a beam support member of a tape head module extends beyond the end of the wafer chiplet disposed on the beam support member to fully support the wafer chiplet. In still another aspect, one end of a beam support member of a tape head module is chamfered to facilitate mounting the tilted tape head assembly into a tape drive actuator.
G11B 5/008 - Enregistrement, reproduction ou effacement sur des bandes ou des fils magnétiques
G11B 5/187 - Structure ou fabrication de la surface de la tête en contact physique avec le milieu d'enregistrement ou immédiatement adjacente à celui-ciPièces polairesEntrefers
G11B 5/39 - Structure ou fabrication de têtes sensibles à un flux utilisant des dispositifs magnétorésistifs
21.
MULTIPLE CHIP MODULE WITH INTEGRATED MICROCHANNEL COOLING
An electronic module is provided that includes a microchannel cooler having a glass manifold contacting a first side of a microchannel chip, a plurality of functional semiconductor chips located face up on a second side of the microchannel chip. Each semiconductor chip of the plurality of functional semiconductor chips is coefficient of thermal expansion (CTE) matched, and a first redistribution layer (RDL) containing structure or organic interposer is located above and in electrical contact with the plurality of functional semiconductor chips. In either case, the first RDL containing structure and the organic imposer are not CTE matched to the functional semiconductor chips.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/46 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
22.
DISCOVERING A SCHEMA FOR A DATA LAKEHOUSE BY IDENTIFYING THE PRIMARY AND FOREIGN KEYS
Described are techniques for identifying primary and foreign keys to build a schema. A primary key of a query table of a data lakehouse, which may consist of multiple columns, is identified. The top n-similar columns of the tables of the data lakehouse are then identified to identify the joinable tables using the primary key as a query using column embeddings. A list of candidate joinable tables is then identified based on the identified top n-similar columns of tables of the data lakehouse. Joinable tables from the list of candidate joinable tables are selected that satisfy an inclusion dependency constraint. The foreign keys having full containment with the primary key of the query table are then identified from the selected joinable tables. Such identified primary and foreign keys are utilized to build/discover the schema, such as a relational schema, of the data lakehouse.
A semiconductor integrated circuit (IC) device includes a bottom wire level, a top wire level, a first region with a first vertical dimension between the bottom wire level and the top wire level, and a second region with a second vertical dimension between the bottom wire level and the top wire level that is less than the first vertical dimension. The discrepancy in the vertical dimensions between wiring levels in different regions of the semiconductor IC device may provide desired or optimized capacitance and/or resistance metrics therein and may increase overall semiconductor integrated circuit (IC) device performance.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
The present invention provides a semiconductor structure (10). The semiconductor structure (10) includes a first area (810) having a back-end-of-line (BEOL) region that includes a first set of vias (301/302); a metal level (M1) with one metal line (311/312/313) above the first set of vias (301/302); and a second set of vias (321) above the metal level (M1); and a second area (820) having a metal stub (350), where a bottom surface of the metal stub (350) is substantially aligned with a bottom surface of the first set of vias (301/302) and a top surface of the metal stub (350) is substantially aligned with either a top surface of the one metal line (311/312/313) of the metal level (M1) or a top surface of the second set of vias (321), and where the metal stub (350) has a horizontal width that is at least 10 times larger than a width of the one metal line (311/312/313). A method of forming the semiconductor structure (10) is also provided.
A semiconductor integrated circuit (IC) device includes a bottom wire level, a top wire level, a first region with a first vertical dimension between the bottom wire level and the top wire level, and a second region with a second vertical dimension between the bottom wire level and the top wire level that is less than the first vertical dimension. The discrepancy in the vertical dimensions between wiring levels in different regions of the semiconductor IC device may provide desired or optimized capacitance and/or resistance metrics therein and may increase overall semiconductor integrated circuit (IC) device performance.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
26.
FLUORINATED GAS ABATEMENT AND FLUORIDE SEQUESTRATION USING SILICON
xxxx and the fluorinated gas in the reactor, and a separation component for removing silicon tetrafluoride from a gaseous mixture formed in the reactor. A process of semiconductor manufacturing includes defluorinating exhaust gas using the process. A system for semiconductor manufacturing includes a set of components for carrying out the process.
A method, system, computer program product, and computer program for managing data in a storage system, the storage system comprising: a set of subsystems comprising: a structure comprising a set of mappings between logical and mapped addresses; and a storage device comprising a first data version at a first mapped address; the method comprising: for at least one substructure: providing, in the structure, for the first logical address, a verified pointer to the first mapped address; writing a second data version for a second mapped address, the second mapped address different from the first mapped address; providing, in the structure, for the first logical address a write-head pointer to the second mapped address; gathering the second data version to determine metadata for the second data version, the metadata associated with an indicator; in response to the indicator comprising a verify indicator; updating the verify pointer to the second mapped address.
Provided are a method, system, and computer program product in which operations are performed to establish communication with a plurality of hosts that are coupled to a plurality of storage devices over a storage area network (SAN). Further operations are performed to discover and report those hosts of the plurality of hosts that are currently or have previously been SAN booted to one or more logical unit numbers (LUNs) within one or more storage devices of the plurality of storage devices.
Embodiments of present invention provide a method of forming a semiconductor structure. The method includes providing a first dielectric layer with a metal line in a first metal level; forming a second dielectric layer on top of the first dielectric layer; creating a trench opening over a via opening in the second dielectric layer; selectively forming a dielectric liner lining sidewalls and a bottom surface of the trench opening and lining sidewalls of the via opening; and filling the trench opening and the via opening with a conductive material to form a trench directly over a via with a common conductive core. A structure formed thereby is also provided.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
In an approach to generating super resolution images, a computer selects a latent vector associated with a high resolution image from a plurality of latent vectors of a generative neural network model. A computer generates a super resolution image from the selected latent vector. A computer downscales the super resolution image to match a size of a plurality of low resolution images. A computer computes a difference between the super resolution image and each of the plurality of low resolution images. A computer determines a minimum difference of the difference between the super resolution image and each of the plurality of low resolution images. A computer determines the minimum difference meets a stopping criteria. A computer transmits the super resolution image to a user. A computer stores the super resolution image.
G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
G06T 3/4046 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement utilisant des réseaux neuronaux
31.
AUTOMATED META-LEARNING IN CLUSTERING USING A MACHINE LEARNING CLUSTERING META LEARNING MODEL
A method of creating a machine learning clustering meta learning model for use in solving a machine learning clustering problem includes obtaining a plurality of information related to the machine learning clustering problem, wherein the plurality of information includes classification datasets, machine learning transformers and clustering estimators, creating a set of clustering datasets using the classification datasets, generating trained clustering pipelines by training the set of unsupervised clustering pipelines responsive to the clustering datasets, processing the trained clustering pipelines to generate internal scores and external scores for the set of clustering datasets, creating an encoded clustering pipeline by encoding the trained clustering pipeline using the external score as a label and generating a trained supervised machine learning model by combining the internal scores and the encoded clustering pipelines.
Systems and techniques that facilitate multilingual ASR machine learning models are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory that can execute the computer executable components stored in memory. The computer executable components can comprise an automatic speech recognition machine learning model that learns shared weights across one or more languages in a set of target languages; and a training component that trains the automatic speech recognition model.
G10L 15/06 - Création de gabarits de référenceEntraînement des systèmes de reconnaissance de la parole, p. ex. adaptation aux caractéristiques de la voix du locuteur
33.
AUGMENTING A LIMITED DATASET BY LEVERAGING BOTH QUANTUM AND CLASSICAL SYSTEMS
A method, system, and computer program product for augmenting a limited dataset with data to optimize an indicator value. A quantum model is trained on a quantum computer with a known dataset to identify the relationship between the feature vectors consisting of binary data and the associated objective variables. A quantum state of the quantum model is measured by the quantum computer by employing a quantum circuit to obtain a collection of observed bitstrings. Furthermore, index values are calculated by a classical computer based on the collection of observed bitstrings. An optimal indicator value is calculated by the classical computer based on the index values and the observed bitstrings. The data point that optimizes the indicator value is then identified by the quantum computer. The dataset is then updated by the classical computer with the identified data point and the best indicator value within the updated dataset is adjusted accordingly.
Examples described herein provide a computer-implemented method that includes receiving a plurality of profiles corresponding to at least one of a plurality of virtual machines. Each of the plurality of profiles defines a validity period and an allowable variation of time. The method further includes determining, based at least in part on the validity period, a subset of the plurality of profiles that are active. The method further includes calculating a uniform distribution for virtual clocks of each of the subset of the plurality of virtual machines and determining a desired offset. The method further includes adjusting a virtual clock frequency of a virtual clock based at least in part on the desired offset and the allowable variation of time. The adjusting causes a difference between a real time-of-day clock and a virtual time-of-day clock of the at least one of the virtual clocks to increase.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
35.
DECODING AND EXECUTING MEMORY COMMAND WITH PARTIAL FRAME DATA
A computer-implemented method to decode and execute a memory command with partial frame data is provided. The computer-implemented method includes receiving the memory command during early cycles of a frame, the memory command being locatable in a template of the frame by reference to an opcode of the frame, sending the memory command to a command first-in-first-out (FIFO) unit as an unverified command once decoder logic decodes the memory command, prior to a cyclic redundancy check (CRC) and prior to arrival of full address bits of the frame in later cycles, entering the unverified command into a scheduling queue to allow for early bank activation, executing the CRC and confirming the unverified command as a verified command based on no errors being found during the CRC.
Disclosed is a method for serving by a distributed communication system a vehicle traveling from an origin to a destination. The distributed communication system comprises an initial set of computer systems. The method comprises: predicting a route of the vehicle from a current location of the vehicle to the destination. Resource information may be used for selecting from the initial set of computer systems a set of computer systems that can provide machine learning based content to the vehicle along the route. A subset of one or more computer systems of the set of computer systems may be selected for generating a predicted content. A generation of the predicted content may be offloaded to the subset of computer systems. Content delivery computer systems of the initial set of computer systems may be controlled to deliver the generated content to the vehicle in accordance with the specific set of space-time points.
An apparatus is provided for processing a digital signal for a digital-to-analog converter (“DAC”). The apparatus includes a monitoring component configured to monitor a sequence of samples of the digital signal for a predetermined pattern of signal values. Upon determining that the sequence of samples does include the predetermined pattern of signal values, then samples in the sequence of samples that include the predetermined pattern of signal values are sent to the DAC. Noise is injected into an interpolation component, and the noise is withheld from an output of the DAC.
A cross-point array includes an array of Resistive Processing Unit (RPU) devices having rows and columns interconnected at cross-points, wherein the RPU devices receive a finite duration input voltage on the rows and output a current on the columns. An input-signal matched filter is coupled to each of the columns to reduce noise in the current in accordance with the finite duration input voltage.
A computer-implemented method for automated floorplan assistance is provided. The computer-implemented method includes automating simultaneous placements of large blocks, soft blocks and ports into a grid, grouping the large blocks, the soft blocks and the ports into nodes, executing a learning flow for both coarse movements and fine movements of the nodes relative to the grid to iteratively improve a floorplan of the grid by assigning rewards associated with placement tool steering in accordance with learned attractions of the nodes toward certain areas of the grid, executing a dynamic grid size determination based on sizes of the nodes to enable handling of multiple nodes of differing sizes together and generating an output comprising a grid size in accordance with the dynamic grid size determination and node assignments for each node at grid locations associated with greatest rewards.
Automated on-demand occupant environment modulation in a data center, including: identifying, by a computing device operatively coupled to one or more computing devices in a data center, based on data from one or more sensors, a location of an individual in the data center; and modifying, by the computing device, one or more environmental parameters at the location, including modifying operation of the one or more computing devices in the data center based on the location of the individual in the data center relative to the one or more computing devices.
Examples described herein provide a computer-implemented method that includes receiving, at a dilated convolution and attention-based neural network, vector embeddings corresponding to sequence elements of sequential data. The dilated convolution and attention-based neural network includes a dilated convolutional neural network, a plurality of block-local attention blocks, and a feed-forward neural network. The method further includes generating, using the dilated convolution and attention-based neural network, a sequence of vector embeddings based at least in part on the sequential data.
A computer-implemented method and related system explore a combinatorial space. A combinatorial library and a desired output are identified. From the combinatorial library, an initial dataset is identified to be tested experimentally to create the combinatorial space. The following functions are iteratively performed: experimentally screening a set of diverse machine learning models (MLMs) using the initial data set or an augmented data set to produce experimental screening results; training the MLMs using the experimental screening results; selecting, from the MLMs, at least one MLM having a highest accuracy and performance; screening the combinatorial library; calculating a normalized similarity factor measured from top-ranked combinations; identifying, using the normalized similarity factor, an amount of the model-driven augmented data to be added to the top-ranked combinations; obtaining augmented data; and selecting the augmented data from the top-ranked combinations and the augmented combinatorial data. The iteration exits upon meeting an exit criterion.
G16B 40/00 - TIC spécialement adaptées aux biostatistiquesTIC spécialement adaptées à l’apprentissage automatique ou à l’exploration de données liées à la bio-informatique, p. ex. extraction de connaissances ou détection de motifs
Systems and techniques that facilitate creation and archiving of controlled structures are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory that can execute the computer executable components stored in memory. The computer executable components can comprise a first machine learning model that classifies a use case for an artificial intelligence product into a use case category and generates a risk score for the artificial intelligence product based on the use case category, a deployment profile and one or more compliance mandates; and a second machine learning model that performs one or more risk mitigation actions based on the assigned risk score, the deployment profile and the one or more compliance mandates.
A device includes a photonics chip and a flexible waveguide having a first end connected to the photonics chip and a second end opposite the first end, in which the second end of the flexible waveguide includes a first portion connected to a ferrule module and a second portion connected to the ferrule module. The second portion is stacked vertically over the first portion in the ferrule module.
A computer-implemented method includes parsing, by a processor set, text comprised by an alert corresponding to an information technology (IT) abnormality incident, resulting in alert data. The processor set uses a generative machine learning (ML) model to generate a natural language summary of the incident. The natural language summary includes a symptom-resource pairing corresponding to the alert and is based on the alert data and on a topology of keywords comprised by the alert. In one or more embodiments, the computer-implemented method further comprises employing, by the processor set, graph connectivity distances between elements of the topology to verify the symptom-resource pairing.
The present disclosure relates to a computer-implemented method for automatically controlling an execution of a workload on one or more trusted execution environments, while enforcing compliance with a plurality of constraints required by a plurality of entities. The method comprises receiving the plurality of constraints for the execution of the workload from the plurality of entities. An execution requirement for controlling the one or more trusted execution environments is automatically generated using the received constraints. The one or more trusted execution environments are controlled in compliance with the execution requirement.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
47.
AUTOMATED ON-DEMAND OCCUPANT ENVIRONMENT MODULATION IN A DATA CENTER
Automated on-demand occupant environment modulation in a data center, including: identifying, by a computing device operatively coupled to one or more computing devices in a data center, based on data from one or more sensors, a location of an individual in the data center; and modifying, by the computing device, one or more environmental parameters at the location, including modifying operation of the one or more computing devices in the data center based on the location of the individual in the data center relative to the one or more computing devices.
A method for serving by a distributed communication system a vehicle traveling from an origin to a destination. The distributed communication system comprises an initial set of computer systems. The method comprises: predicting a route of the vehicle from a current location of the vehicle to the destination. Resource information may be used for selecting from the initial set of computer systems a set of computer systems that can provide machine learning based content to the vehicle along the route. A subset of one or more computer systems of the set of computer systems may be selected for generating a predicted content. A generation of the predicted content may be offloaded to the subset of computer systems. Content delivery computer systems of the initial set of computer systems may be controlled to deliver the generated content to the vehicle in accordance with the specific set of space-time points.
A computer implemented method correlates a local resolver to a client. The local resolver requesting an address to a resource from an authoritative domain name server is identified. An access pattern defining servers for accessing the resource over time slices is determined. The servers are assigned to the time slices and are configured to record requests to access the resource. Sending responses from the authoritative domain name server to the local resolver is initiated using the access pattern. Each response in the responses has the address to a server assigned to a current time slice during which a request for a new address is received from the local resolver. Whether the requests to access the resource from the client match the access pattern is determined. The local resolver is associated with the client in response to the requests matching the access pattern.
According to one embodiment, a method, computer system, and computer program product for adaptive user interface amelioration during a screen sharing session is provided. The embodiment may include receiving shared content during a screen sharing session. The embodiment may also include identifying one or more device characteristics for a user device associated with a user and one or more user profile characteristics for the user. The embodiment may further include extracting topical elements within the received shared content. The embodiment may also include identifying a location of one or more objects and/or one or more text elements in the shared content. The embodiment may further include modifying a viewing area of the shared content on a display screen of the user device.
A semiconductor integrated circuit (IC) device includes a first source/drain region that is connected to a second source/drain region by one or more active channels, a backside dielectric plug that is connected to the second source/drain region, and a faux channel that is connected to the first source/drain region and that is connected to the backside dielectric plug. The backside dielectric plug adequately electrically isolates the faux channel from the second source/drain region. The fabrication of the backside dielectric plug may be utilized to modify transistors within a first region of the semiconductor IC device relative to transistors within a second region semiconductor IC device.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Power supply configuration based power capping includes determining, by a power management controller of a computing system that includes one or more power supply units, power supply configuration information for the computing system, including a total number of the power supply units, a power supply type for each of the power supply units, and a power supply input voltage for each of the power supply units. The power management controller determines, based on the power supply configuration information, a system power cap for the computing system. The power management controller controls power consumption of the computing system based on the system power cap.
A semiconductor structure that includes a plurality of memory dies in a stacked configuration, and at least one through-chip via (TCV) that extends through the plurality of memory dies where the at least one TCV is adapted to provide power to the plurality of memory dies.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
54.
ALLOCATING LOGICAL PARTITIONS IN A COMPUTING ENVIRONMENT WITH MULTIPLE PROCESSOR CORE TYPES
A method includes receiving a request to create a logical partition. The method further includes determining whether the logical partition can be implemented on a single drawer of a plurality of drawers. The method further includes, responsive to determining that the logical partition can be implemented on a single drawer of the plurality of drawers, allocating the logical partition to one of the drawers of the plurality of drawers based on a container size that can fit the logical partition. The method further includes, responsive to determining that the logical partition cannot be implemented on a single drawer of the plurality of drawers, allocating the logical partition to at least two drawers of the plurality of drawers using bitmasks, wherein each of the bitmasks represents a processor chip of a plurality of processor chips, and wherein one bitmask is generated per drawer of the plurality of drawers.
A branch prediction logic system includes a branch history table (BHT), a multi-level history table, and a prediction update queue. The BHT includes a plurality of lines, each line corresponding to at least one branch instruction and containing history information specific to the at least one branch instruction. A first pattern history table (PHT-1) stores first branch data corresponding to the at least one branch instruction included in a given line of the BHT and a second pattern history table (PHT-2) stores second branch data corresponding to the at least one branch instruction included in a given line. The prediction update queue stores a line presence bit having one of a “1” logic state or a “0” logic state. The branch prediction logic system performs a data swap between the PHT-2 and the PHT-1 based on the logic state of the line presence bit.
One or more computer processors predicting a distortion in a cast product created from a mold, utilizing a trained generative model. The one or more computer processors modify the mold associated with the predicted distortion. The one or more computer processors generate a corrective mold design for one or more material and shape conditions to remediate the predicted distortion. The one or more computer processors create a corrective mold with an appropriate specification based on the corrective mold design using a robotic system to minimize post-processing. The one or more computer processors produce a final cast product with the created corrective mold.
According to one embodiment, a method, computer system, and computer program product for performing a rail system check within an automated tape library is provided. The present invention may include moving a robot to a starting position along a rail system of the automated tape library; setting a motor velocity of the robot lower than its normal velocity; initiating a rail system check process; consistently collecting a plurality of measurement data during the rail system check process; analyzing the collected plurality of measurement data; and determining if one or more rail system problems exist in the automated tape library based on the analysis of the collected plurality of measurement data.
B65G 43/00 - Dispositifs de commande, p. ex. de sécurité, d'alarme ou de correction des erreurs
B65G 1/137 - Dispositifs d'emmagasinage mécaniques avec des aménagements ou des moyens de commande automatique pour choisir les objets qui doivent être enlevés
An embodiment includes a backup trigger by a system. The embodiment includes responsive to detecting the backup trigger, processing by a Backup Executor of the system a manifest comprising of a component for backup. The embodiment also includes orchestrating, by the Backup Executor, the backup between an adaptor proxy of the component in a first location and an adaptor of the component in a second location wherein the orchestrating comprises invoking the adaptor proxy by the Backup Executor wherein the adaptor proxy performs a get from the component in the first location and performs a put to the adaptor of the component in the second location and wherein the Backup Executor is technology agnostic.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
Embodiments herein describe circuitry and techniques to implement an enhanced PPM frequency offset detector and methods for implementing operational functions of one or more embodiments of the PPM frequency offset detector to detect a frequency offset between two clock signals. An enhanced PPM frequency offset detector of one or more embodiments reduces circuitry and power requirements, eliminating circuitry requirements of a third reference clock signal to detect the frequency offset of some traditional arrangements, and effectively and efficiently detects a PPM frequency offset between two clock signals.
A machine learning-based processor utilization prediction process is provided which includes training a processor utilization model using system log data, code feature data, and processor-associated data of a system to, at least in part, predict processor utilization to execute application code on the system. In addition, the process includes generating, using the processor utilization model, a processor utilization simulation for the system to execute the application code, and initiating an action based on the processor utilization simulation for the system to execute the application code.
Methods, apparatus, and systems for tuning a resonator array may include receiving, by a resonator array including a plurality of resonators, a signal, wherein each of the plurality of resonators is configured to attenuate sound at a specific frequency and includes a cavity and a neck coupled to the cavity, and altering, by a physical mechanism coupled to the cavities of the resonators and based on the received signal, the specific frequency of sound attenuated by each of the plurality of resonators, including altering a volume of the cavity included in each of the plurality of resonators.
G10K 11/172 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets de résonance
H03H 9/02 - Réseaux comprenant des éléments électromécaniques ou électro-acoustiquesRésonateurs électromécaniques Détails
H03H 9/205 - Détails de réalisation de résonateurs se composant de matériau piézo-électrique ou électrostrictif ayant des résonateurs multiples
A computer-implemented method, according to one approach, is performed in response to intercepting an application request. The computer-implemented method includes forwarding a first copy of the application request to a policy agent, and forwarding a second copy of the application request to a sketch algorithm. The sketch algorithm extracts metadata from the second copy of the application request. Moreover, the policy agent applies a security policy to the first copy of the application request and the metadata extracted by the sketch algorithm. Furthermore, the application request is dispositioned based at least in part on whether the first copy of the application request and/or the metadata extracted by the sketch algorithm satisfy the security policy.
Embodiments determine evaluation data from at least one message queue, determine a targeted number of messages included in the at least one message queue and a confidence value by using a trained machine learning model with the evaluation data, determine that the confidence value is greater than a predetermined threshold, perform synchronous message restoration based on the targeted number of messages and the confidence value being greater than the predetermined threshold, and perform remaining system restart functions in response to the synchronous message restoration being completed.
Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: storing into a data repository internet of things (IoT) sensor data of a plurality of IoT devices disposed within a workflow environment that includes one or more physical asset; performing a simulation to simulate operating performance of the one or more physical asset disposed within the workflow environment, wherein the performing the simulation to simulate operating performance of the one or more physical asset disposed within the workflow environment includes using historical IoT data of the IoT sensor data; detecting, in dependence on the performing the simulation, that an alert condition is present in the workflow environment; and prompting one or more worker within the workflow environment to take action in response to the detecting that the alert condition is present in the workflow environment.
A semiconductor integrated circuit (IC) device includes a first source/drain region connected to a second source/drain region by a plurality of active channels, a backside contact that is directly coupled to the first source/drain region, a frontside contact that is directly coupled to the second source/drain region, and a backside dielectric plug that is directly coupled to the second source/drain region and that is directly coupled to the backside contact. In examples, every backside contact placeholder that is associated with a source/drain region that is connected to a frontside contact is removed and replaced by a respective backside dielectric plug. Relative to the backside contact placeholder, the replacement backside dielectric plug may reduce gate-drain Miller capacitance, source/drain capacitance, and may reduce leakage current between source and drain through substrate residue that may reside due to flawed substrate removal during backside processing.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor device includes transistor devices disposed on a frontside of a dielectric layer. A thermoelectric device is disposed on a backside of the dielectric layer to dissipate heat from the transistor devices. The thermoelectric device includes pillars connected to backside power rails by backside contacts to power the thermoelectric device.
F25B 21/02 - Machines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet PeltierMachines, installations ou systèmes utilisant des effets électriques ou magnétiques utilisant l'effet Nernst-Ettinghausen
A computer-implemented method comprising: receiving, as input, a query and a source document intended for a content-grounded question-answering or multi-turn conversation task by a specified large language model (LLM) which has a context window size limit, wherein the source document has a size which exceeds the context window size limit; dividing the source document into a plurality of segments; applying a language model to each of the segments, to assign to each of the segments a relevance score; selecting the k-top segments having the highest the relevance scores; combining the selected k-top segments into a virtual document having a size which complies with the context window size limit; and feeding the virtual document as input to the specified LLM, to generate a response that is grounded in the content of the virtual document.
Systems and techniques that facilitate building a universal vocabulary of tokens from time series for training large language models are provided. For example, one or more embodiments described herein can comprise a computer system for facilitating a process to build a universal vocabulary of tokens from time series for large language model training, which can comprise one or more processors, one or more computer readable storage media, and program instructions stored on the one or more computer readable storage media, the program instructions executable by the processor resulting in the computer system to perform one or more functions, the functions comprising segmenting one or more time series based on local minima of the one or more time series. The functions can further comprise generating a universal vocabulary of tokens.
G06F 40/284 - Analyse lexicale, p. ex. segmentation en unités ou cooccurrence
G06F 16/383 - Recherche caractérisée par l’utilisation de métadonnées, p. ex. de métadonnées ne provenant pas du contenu ou de métadonnées générées manuellement utilisant des métadonnées provenant automatiquement du contenu
Embodiments herein describe a glitch detector circuit (and method of operation) for detecting glitches in a clock signal. In one embodiment, the glitch detector includes a shift register that samples the reference clock using a clock signal output by a PLL. The value in a first memory element of the shift register can be sampled to previous values that were stored (and then bit shifted) in the shift register. If there is a mismatch, the glitch detector indicates there was a clock glitch in the reference clock, and a corrective action can be performed.
G01R 31/3185 - Reconfiguration pour les essais, p. ex. LSSD, découpage
G11C 19/28 - Mémoires numériques dans lesquelles l'information est déplacée par échelons, p. ex. registres à décalage utilisant des éléments semi-conducteurs
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
H03L 7/08 - Détails de la boucle verrouillée en phase
A computer-implemented method, according to one approach, is performed in response to intercepting an application request. The computer-implemented method includes forwarding a first copy of the application request to a policy agent, and forwarding a second copy of the application request to a sketch algorithm. The sketch algorithm extracts metadata from the second copy of the application request. Moreover, the policy agent applies a security policy to the first copy of the application request and the metadata extracted by the sketch algorithm. Furthermore, the application request is dispositioned based at least in part on whether the first copy of the application request and/or the metadata extracted by the sketch algorithm satisfy the security policy.
A method that includes receiving information system tickets, generating for each information system ticket a first state of data to capture an original state of one or more end-user operational data, generating for each information system ticket a second state of data to capture a changed state of the one or more end-user operational data, storing the first state and the second state in a database, and mining the database for changes in end-user operational data between the first state and the second state to generate patterns of changes. The patterns of changes are clustered into a number of clusters with each cluster representing a different ticketing issue.
A memory device comprises a physically and electrically connected logic die and a memory die. The logic die comprises a logic dielectric layer, with a plurality of logic openings; a logic device layer is disposed on the logic dielectric layer; and a plurality of logic devices, with logic device connections, disposed on/within the logic dielectric layer. The memory die comprises a memory dielectric layer with a plurality of memory openings; a memory device layer is disposed on the memory dielectric layer; and a plurality of memory devices, with memory device connections, disposed on/within the memory device layer. A backside to backside (B2B) connection interface is disposed between the logic dielectric layer and the memory dielectric layer. Connection paths passing through the B2B connection interface enables short back-to-back connections between logic device connections and the memory device connections.
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A semiconductor structure that with a via last through-silicon-via hole that has a dielectric liner surrounds a sidewall of the top portion of the through-silicon-via hole that is above and contacting the top surface of the semiconductor substrate. A through-silicon-via encapsulation is directly on and surrounds the dielectric liner around the top portion of the through-silicon-via hole. The through-silicon-via encapsulant can be composed of a refractory metal that is electrically isolated from the completed through-silicon-via by at least the dielectric liner.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
A semiconductor structure with an annular guard ring extending through an interlayer dielectric (ILD) layer to a top surface of a semiconductor substrate. The annular guard ring surrounds a through-silicon-via (TSV). The annular guard ring is composed of layer of a liner material around a dielectric material.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A device (100) comprises a superconducting radio frequency, RF, signal generator (120) which comprises a plurality of channels. Each channel is configured to generate a corresponding RF signal (RF_1-RF_4) with a frequency that is controlled by a corresponding direct current, DC, control signal (IB1-IB4) applied to the channel.
H03K 3/38 - Générateurs caractérisés par le type de circuit ou par les moyens utilisés pour produire des impulsions par l'utilisation, comme éléments actifs, de dispositifs supraconducteurs
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
One or more computer processors predicting a distortion in a cast product created from a mold, utilizing a trained generative model. The one or more computer processors modify the mold associated with the predicted distortion. The one or more computer processors generate a corrective mold design for one or more material and shape conditions to remediate the predicted distortion. The one or more computer processors create a corrective mold with an appropriate specification based on the corrective mold design using a robotic system to minimize post-processing. The one or more computer processors produce a final cast product with the created corrective mold.
A semiconductor integrated circuit (IC) device includes a first source/drain region that is connected to a second source/drain region by one or more active channels, a backside dielectric plug that is connected to the second source/drain region, and a faux channel that is connected to the first source/drain region and that is connected to the backside dielectric plug. The backside dielectric plug adequately electrically isolates the faux channel from the second source/drain region. The fabrication of the backside dielectric plug may be utilized to modify transistors within a first region of the semiconductor IC device relative to transistors within a second region semiconductor IC device.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
78.
Reducing voltage drooping in a microelectronic chip
Disclosed are techniques for reducing voltage drooping in a microelectronic chip, including separating a scan data launch clock from a capture clock with a variable time delay depending on a delay of a succeeding scan path of the latches, where the scan data launch clock and the capture clock are based on a base clock signal. The techniques further include analyzing and categorizing the latches against the time delay into dedicated buffer group categories. The techniques further include assigning the at least two local clock buffers to the latches within the dedicated buffer group categories.
A method, computer system, and a computer program product for sustainable data storage is provided. An IOP discovers a path between each defined I/O adapter and its endpoint. Based on a system configuration and the discovered pathing, the IOP builds a table comprising each I/O adapter, endpoint, initial adapter state. The IOP creates an I/O adapter redundancy mapping from the table and assign performance thresholds to each I/O adapter. The IOP continuously monitors utilization of each I/O adapter, whereby based on utilization for the I/O adapter reaching a defined threshold, the IOP enables a redundant I/O adapter path, whereby the redundant I/O adapter is a proxy for the I/O adapter.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p. ex. canal ou processeur périphérique
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
80.
Refinement of large multi-dimensional search spaces
An embodiment includes detecting a search request of a multi-dimensional search space by a system; responsive to detecting the search request, sampling representative parameters in the multi-dimensional search space based on a sampling threshold. The embodiment includes determining a parameter range of the representative parameters in the multi-dimensional search space. The embodiment also includes transforming a part of the multi-dimensional search space based on a statistical guarantee and the parameter range, where the part of the multi-dimensional search space is a refined space for a solution of the search request.
An apparatus includes a top section, a middle section, and a bottom section of a spring actuator for a tape drive that form a C-shape of the spring actuator. The middle section includes three flexor columns, where a first writer module is bonded to a first flexor column from the three flexor columns, a reader module is bonded to a second flexor column from the three flexor columns, and a second writer module is bonded to a third flexor column from the three flexor columns.
Computer-implemented methods for testing a design of an integrated circuit are provided. Aspects include obtaining the design of the integrated circuit, simulating an operation of the integrated circuit for at least a minimum number of clock cycles, collecting two or more sets coverage data corresponding to the simulated operation of the integrated circuit, and calculating a difference between the two or more sets coverage data. Based on a determination that the difference is greater than a threshold minimum, aspects include simulating the operation of the integrated circuit for at least an additional number of clock cycles. Based on a determination that the difference is not greater than the threshold minimum, aspects include ending the simulation of the operation of the integrated circuit and outputting results of the simulation to a user.
A semiconductor device includes a through layer skip via that traverses an intermediary metal layer. The through layer skip via has a damascene metal portion and a subtractive metal portion. A dielectric spacer is disposed within a thickness of the intermediary metal layer and surrounds a top portion of the subtractive metal portion.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
Enhanced distributed tracing is provided. A set of microservices in a sequence of microservices preceding a preselected microservice in the sequence of microservices are identified. Each tracing data sample received from the set of microservices preceding the preselected microservice in the sequence of microservices is identified. Each tracing data sample corresponding to a set of selected transactions received from the set of microservices preceding the preselected microservice in the sequence of microservices that was dropped during rate-limiting sampling performed by the preselected microservice is deleted based on analysis of a result of the rate-limiting sampling of the set of selected transactions received from the preselected microservice thereby retaining a subset of tracing data samples corresponding to the set of selected transactions collected during head-based sampling.
An embodiment includes detecting an explainer model check by a system. The embodiment includes responsive to the detecting the explainer model check, computing a first result by a Data and Model Preparation of the system wherein the first result is based on a first dataset and a second data set generated by the Data and Model Preparation. The embodiment includes generating a second result by an explainer model of a Prediction and Explanation of the system based on the first dataset and the second data set. The embodiment includes computing a difference metric between a first result and a second result by a Judgment Retraining of the system. The embodiment also includes training the explainer model based on the difference metric.
Embodiments of the present disclosure provide methods, systems, and computer program products for assigning and dynamically managing a Customer Proficiency Rating for a specific customer for implementing enhanced customer support operations for a supported product or service. Disclosed embodiments provide an AI virtual support agent that receives a customer support request for a current problem, obtains a customer statement of understanding for the current problem and provides a set of questions, to obtain customer responses. In an embodiment, the AI virtual support agent evaluates the customer statement and customer responses, and calculates a customer proficiency rating for a specific customer for the support request to identify a customer skill level for the current problem. The AI virtual support agent routes customers to an optimal human support agent based on the customer proficiency rating.
G06Q 30/016 - Fourniture d’une assistance aux clients, p. ex. pour assister un client dans un lieu commercial ou par un service d’assistance après-vente
87.
DYNAMIC WORKSPACE CREATION WITH AUTOMATED OBFUSCATION AS A COMPUTING SERVICE
Mechanisms are provided for dynamically generating workspaces and provisioning them with datasets. The mechanisms store datasets in a data vault for provisioning to dynamically generated workspaces associated with users. The dynamically generated workspaces are computer environments through which the users can perform operations on the one or more datasets. The mechanisms receive a request, from a user, for access to a specified dataset, and retrieve a data usage agreement (DUA) corresponding to a pairing of the user with the specified dataset. The DUA specifies a level of obfuscation to be applied to the specified dataset when provisioning a workspace associated with the user, with the specified dataset. The mechanisms dynamically generate, on-demand, the workspace associated with the user based on the retrieved DUA. The mechanisms also automatically provision, on-demand, the dynamically generated workspace with a version of the specified dataset corresponding to the level of obfuscation specified in the DUA.
A computer-implemented method, according to one embodiment, includes determining and using a first backup plan, where the first backup plan details a first number of backup copies of source volumes that are to be created and a first time interval that the first number of backup copies are to be created. In response to a determination that a first set of conditions are met during use of the first backup plan in a data storage system, a second backup plan that details a second number of backup copies of the source volumes that are to be created and a second time interval that the second number of backup copies are to be created are determined and used. In response to a determination that a second set of conditions are met during use of the second backup plan, a reversion to use of the first backup plan is caused.
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
89.
ROBOTIC PROCESS AUTOMATION DRIVEN CONDITIONAL FORMATTING RULES FOR USER INTERFACES
Automated conditional formatting of a user interface includes a robotic process automation (RPA) agent receiving user activity via a dashboard user interface. The RPA agent automatically determines data engaged by a user from data associated with the user activity. A role of the user during an engagement with the dashboard user interface is identified. The RPA agent identifies data segments of interest. The data segments of interest and the identified role of the user are forwarded to a machine learning module. Upon receiving, via the dashboard user interface, a notification of an opening of the dashboard user interface, the machine learning module predicts a set of data segments in the dashboard user interface that will be of interest to the user. The predicted set of data segments are sent to the RPA agent. The RPA agent applies conditional formatting rules to the display of predicted set of data segments.
A method, computer program product, and computer system for reading data stored in a set associative cache. A cache read instruction that did not read the cache after being previously launched is relaunched after an effective address (EA) of the instruction was ascertained. A hash of the ascertained EA (EAHash) and a class congruence class (CCC) is determined from the ascertained EA. A search is performed for a match of the EAHash and CCC of the ascertained EA to the EAHash and CCC, respectively, of an instruction whose EAHash, CCC, and set are stored in an instruction history stream. If the match is found, only read enables associated with the stored set of the match, which is a read enable of only one class of one address group in the cache, are activated. If the match is not found, all read enables of the one address group are activated.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
91.
DYNAMIC OPTIMIZATION OF POWER CONSUMPTION IN STORAGE SYSTEMS
An embodiment for dynamic optimization of power consumption in storage systems is provided. The embodiment may include receiving historical time-series data from one or more components in a data center. The embodiment may also include predicting one or more workload metrics of the one or more components during a pre-defined time range. The embodiment may further include identifying one or more required resources for the one or more components to handle the predicted one or more workload metrics during the pre-defined time range. The embodiment may also include in response to determining at least one component of the one or more components does not require a resource allocation increase during the pre-defined time range, executing a first action to scale down at least one first resource during the pre-defined time range.
Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dielectric contact cut between a first source/drain contact of a first transistor and a second source/drain contact of a second transistor; a gate structure shared by the first and the second transistor; and a gate cap on top of the gate structure, where a top surface of the dielectric contact cut is substantially coplanar with a top surface of the gate cap and substantially coplanar with top surfaces of the first S/D contact and the second S/D contact. A method of forming the same is also provided.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
93.
ON-DIE CONTROL FOR ACTIVE INTERPOSER VOLTAGE REGULATION
On-die control for active interposer voltage regulation according to an example includes receiving, by a switch in voltage regulation circuitry in an active interposer, an input voltage. Voltage regulation control circuitry in a chip die connected to the active interposer controls the voltage regulation circuitry, including causing the switch to couple the input voltage to one or more passive components of the voltage regulation circuitry in the active interposer. The voltage regulation circuitry regulates the input voltage to generate a regulated output voltage that is output to the chip die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
94.
FREE LAYER IN MAGNETIC TUNNEL JUNCTION OF A MRAM DEVICE
Embodiments of present invention provide a magnetoresistive random-access-memory (MRAM) device. The MRAM device includes a reference layer; a tunnel barrier layer next to the reference layer; and a free layer next to the tunnel barrier layer, where the free layer includes a crystalline AIMnGe layer in a C38 structure formed on a magnetic seed layer, and the magnetic seed layer is a crystallized MnCo2Si layer or a crystallized MnCo2Ge layer having a cubic Heusler structure with a (001) texture. A method of forming the MRAM device is also provided.
Examples described herein provide a computer-implemented method that includes performing, using a cryptographic accelerator, a cryptographic operation asynchronously relative to a core pipeline. The method further includes computing a chaining value for the cryptographic operation. The method further includes, responsive to an occurrence of an error, recovering from the error using the chaining value.
A computer-implemented method, according to one approach, includes: generating lookup tables for signatures during compile time, the lookup tables having cryptographic information. A secret key is used to encrypt the lookup tables, and the secret key is stored in a secure storage which is accessible only to a secure engine. Moreover, in response to experiencing an initial boot: the lookup tables are decrypted using the secret key, and the decrypted lookup tables are stored in the secure storage. Other systems, methods, and computer program products are described in additional approaches.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
A semiconductor device includes a wafer having a frontside, a backside, and front end of line (FEOL) devices arranged on the frontside. The semiconductor device includes a first dielectric material coupled to the frontside and including frontside wiring electrically connected to the FEOL devices. The semiconductor device includes a second dielectric material coupled to the backside and including backside wiring electrically connected to the FEOL devices. The semiconductor device includes a first and second vias extending through the first dielectric material and electrically connected with the backside wiring such that a first power delivery pathway delivers power to a first FEOL device through the first via and the backside wiring and a second power delivery pathway delivers power to a second FEOL device through the second via and the backside wiring. The first power delivery pathway is shorter than the second power delivery pathway.
Mechanisms are provided for dynamically generating workspaces and provisioning them with datasets. The mechanisms store datasets in a data vault for provisioning to dynamically generated workspaces associated with users. The dynamically generated workspaces are computer environments through which the users can perform operations on the one or more datasets. The mechanisms receive a request, from a user, for access to a specified dataset, and retrieve a data usage agreement (DUA) corresponding to a pairing of the user with the specified dataset. The DUA specifies a level of obfuscation to be applied to the specified dataset when provisioning a workspace associated with the user, with the specified dataset. The mechanisms dynamically generate, on-demand, the workspace associated with the user based on the retrieved DUA. The mechanisms also automatically provision, on-demand, the dynamically generated workspace with a version of the specified dataset corresponding to the level of obfuscation specified in the DUA.
A semiconductor device includes an electrically conductive contact embedded in a region of dielectric material. The electrically conductive contact has an uppermost surface that includes a recess and a depression. The recess is recessed a first depth relative to an uppermost surface of the region of dielectric material, and the depression recessed a second depth relative to the uppermost surface of the region of dielectric material. The second depth greater than the first depth. The semiconductor device further includes a region of fill material formed in the recess and the depression of the uppermost surface of the electrically conductive contact. The fill material includes an intermetallic alloy. The intermetallic alloy may be an alloy of copper and one or more of gold, palladium, cobalt, tin, or nickel.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
An embodiment identifies, by a probabilistic black-box anomaly attribution engine, an anomalous sample in test data associated with a black-box model, the black-box model comprising a plurality of variables. The embodiment generates, by the probabilistic black-box anomaly attribution engine, a variable distribution based on the test data using a plurality of outputs generated using a plurality of perturbations. The embodiment generates, by the probabilistic black-box anomaly attribution engine based on the variable distribution, an attribution score representing a responsibility of a variable for the anomalous sample.
