Techniques are provided for training kernels for use in frequency-multiplexed readout of quantum bits. For example, a method comprises performing multiple iterations of a process which comprises setting states of a group of quantum bits using a random process, and performing a readout process to acquire a frequency-multiplexed readout signal which represents readout states of the group of quantum bits. The frequency-multiplexed readout signals that are acquired for at least a portion of the iterations are analyzed to build at least one kernel for each quantum bit of the group of quantum bits, wherein the at least one kernel for a given quantum bit is configured for use in discriminating a state of the given quantum bit in a frequency-multiplexed readout operation applied to the group of quantum bits.
An instruction includes a control mode indicator and is executed to perform an action defined by the instruction. Execution of the instruction includes checking the control mode indicator and re-defining, based on the control mode indicator being a selected value, one or more instruction areas used by the instruction to provide other functionality of the instruction. The action defined by the instruction is performed using at least a portion of the other functionality provided by the re-defining the one or more instruction areas.
An electrode probing structure includes a first array of electrodes arranged to be radially spaced apart about a spatial point. A second array of electrodes is arranged parallel to the first array of electrodes, creating a space between the first array and the second array. An inlet is disposed adjacent the first or the second array of electrodes to introduce a fluid containing particles into the space between the first and the second array of electrodes. One or more outlets are disposed adjacent the first or the second array of electrodes to remove the particles from the space between the first and second array of electrodes. Each pair of parallel electrodes of the first array of electrodes and the second array of electrodes, when provided with an electric potential, generates signals corresponding to at least one characteristic of the particles present in the space between the electrodes.
One or more systems, devices, computer program products and/or computer- implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G06F 15/167 - Communication entre processeurs utilisant une mémoire commune, p. ex. boîte aux lettres électronique
G06F 9/52 - Synchronisation de programmesExclusion mutuelle, p. ex. au moyen de sémaphores
G06F 12/0813 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec configuration en réseau ou matrice
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0853 - Mémoire cache avec matrices multiples d’étiquettes ou de données
G06F 12/0855 - Accès de mémoire cache en chevauchement, p. ex. pipeline
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant la mémorisation cache sélective, p. ex. la purge du cache
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
5.
HIERARCHICAL AND PEER PRUNING STRATEGIES FOR GENERATIVE ARTIFICIAL INTELLIGENCE MODELS IN TELECOMMUNICATIONS NETWORKS
Provided are a method, system, and computer program product for hierarchical inference utilizing a large language model (LLM). Training is performed at a central location, of a helper model and a pruned model for each layer of a hierarchy, wherein the helper model is trained to classify a request as appropriate for the pruned model, and wherein the pruned model is generated from a reduction process of the LLM. A process distributes the helper model and pruned model to different levels of the hierarchy. The process directs, by utilizing the helper model at each level of the hierarchy, inference generation to the pruned model or to another model at a higher tier.
A write chip comprising an array of write transducers and writer bond pads is obtained, each write transducer of the array of write transducers connected to a pair of bond pads of the writer bond pads via electrically conducting signal wires, the write chip comprising a write notch. A read chip comprising an array of read transducers and reader bond pads is obtained, each read transducer of the array of read transducers connected to a pair of bond pads of the reader bond pads via electrically conducting signal wires, the read chip comprising a read notch. The read chip and the write chip are secured together such that a distance between the write transducer array and the read transducer array is less than 100 microns, an orientation of the write notch exposes the reader bond pads, and an orientation of the read notch exposes the writer bond pads.
An instruction is executed to generate a message digest for a message. The message digest is to be used in authentication of the message. Executing the instruction includes obtaining from the instruction a control indicator and determining, based on the control indicator, an initial chaining value to be used to generate the message digest. The message digest is generated using the initial chaining value and the message digest is provided to be used in the authentication of the message.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
8.
INSTRUCTION TO ACCELERATE HASH-BASED MESSAGE AUTHENTICATION CODE PROCESSING
An instruction is executed to generate an authentication code. Executing the instruction includes performing a plurality of operations of the instruction to generate the authentication code. The plurality of operations includes performing a sequence of hash operations on a message to generate an intermediate message digest, and performing an outer-key padding and hashing operation using the cryptographic key to generate another output chaining value to be used in generating a final output message digest based on a final input message digest produced using the intermediate message digest. The final output message digest being a resulting authentication code. The performing the sequence of hash operations and the outer-key padding and hashing operation are performed as part of a single invocation of the instruction.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 9/46 - Dispositions pour la multiprogrammation
9.
AUTOMATIC TILE TENSOR RESHAPING FOR EXECUTION PARALLELIZATION
Mechanisms are provided for parallel execution of an application. The application is partitioned into slices. For each slice, a simulation of an execution of the slice with regard to pairings of tile tensor shape for input data to the corresponding slice, and number of available devices to execute the slice, is executed, which generates a plurality of simulation results, each having performance metric(s) for a corresponding pairing. A set of one or more tile tensor shapes for one or more slices in the plurality of slices is generated based on one or more simulation results in the plurality of simulation results. The selected tile tensor shape for each slice is used to pack data for input to a corresponding slice in the one or more slices. Furthermore, the application is executed using the selected set of one or more tile tensor shapes for the one or more slices.
A magnetic tape defined with one or more data partitions and one or more parity partitions is obtained, wherein each of the data partitions is separated from each of the parity partitions corresponding to the given data partition by a given minimum distance, wherein the given minimum distance is greater than a length of the magnetic tape affected by a permanent error and wherein each data partition comprises data information and each parity partition comprises in-line erasure coding information. The magnetic tape is written based on the one or more data partitions and the one or more parity partitions.
An instruction to perform cryptographic processing is executed. Executing the instruction includes performing a plurality of operations to generate a cryptographic result. Based on performing at least multiple operations of the plurality of operations, an access exception condition for a storage location used by an instrumentation counter is detected. Based on detecting the access exception condition, execution of the instruction is interrupted. The instruction is re-executed to obtain access to the instrumentation counter. The re-executing the instruction starts from where execution was interrupted and includes updating the instrumentation counter, based on the storage location used for the instrumentation counter being validated.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
12.
HEAT SPREADING AND THERMAL HEAT REMOVAL STRUCTURES
Semiconductor structures are provided in which heat spreading and thermal heat removal are improved by providing one or more heat removal paths in which heat spreading and thermal heat removal occurs leveraging horizontal direction and vertical directions and through reduced resistance of heat removal paths. Notably, heat is spread horizontally to the edges of the semiconductor structures and then the heat is removed vertically (up and/or down) from the semiconductor structures.
The invention relates to a method of organizing distribution of information related to a domain name system, DNS, in a computer network, the method comprising, by a first node of the computer network: performing a container-based execution of a first instance of a software application, thereby aggregating DNS information specific to the software application; generating a DNS message indicative of the DNS information; and transmitting the DNS message to a second node of the computer network for usage of the DNS information by a container-based execution of a second instance of the software application.
H04L 61/4511 - Répertoires de réseauCorrespondance nom-adresse en utilisant des répertoires normalisésRépertoires de réseauCorrespondance nom-adresse en utilisant des protocoles normalisés d'accès aux répertoires en utilisant le système de noms de domaine [DNS]
14.
COHERENT COMMUNICATION BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
One or more systems, devices, computer program products and/or computer- implemented methods of use provided herein relate to communication between a processor core and an accelerator. For example, a system can comprise a memory that can store computer executable components. The system can further comprise a processor that can execute the computer executable components stored in the memory, wherein the computer executable components can comprise a tracking component that can track a running state of an accelerator during execution of one or more functions by the accelerator. The computer executable components can further comprise an installation component that can install, via the accelerator, a message in a cache accessible to a processor core, wherein a cache line comprised within the cache can be updated based on installation of the message in the cache.
G06F 12/084 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec mémoire cache partagée
G06F 15/173 - Communication entre processeurs utilisant un réseau d'interconnexion, p. ex. matriciel, de réarrangement, pyramidal, en étoile ou ramifié
G06F 12/0813 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec configuration en réseau ou matrice
G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
G06F 12/0853 - Mémoire cache avec matrices multiples d’étiquettes ou de données
G06F 12/0855 - Accès de mémoire cache en chevauchement, p. ex. pipeline
G06F 12/0888 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant la mémorisation cache sélective, p. ex. la purge du cache
15.
REFINEMENT OF LARGE MULTI-DIMENSIONAL SEARCH SPACES
An embodiment includes detecting a search request of a multi-dimensional search space by a system; responsive to detecting the search request, sampling representative parameters in the multi-dimensional search space based on a sampling threshold. The embodiment includes determining a parameter range of the representative parameters in the multi- dimensional search space. The embodiment also includes transforming a part of the multi-dimensional search space based on a statistical guarantee and the parameter range, where the part of the multi-dimensional search space is a refined space for a solution of the search request.
A computer-implemented method, according to one approach, includes: computing a first cryptographic term in response to receiving a session request from a user. The first cryptographic term is split into an initial portion and a remainder portion, where the remainder portion includes at least one bit. The initial portion of the first cryptographic term is sent to the user, and two or more different potential second cryptographic terms are received from the user. The at least one bit in the remainder portion is used to determine a correct one of the potential second cryptographic terms. Moreover, the correct one of the potential second cryptographic terms is used to compute a third cryptographic term. Furthermore, the third cryptographic term is sent to the user.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
Holographic storage hardware enabled locking includes directing a first reference beam associated with a first process at a storage location in a holographic data storage medium, and detecting, with a detector while the first reference beam is directed at the storage location, whether a second reference beam associated with a second process is also directed at the storage location. Based on the detecting, a signal is generated indicating whether the storage location is locked.
G11C 13/04 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou utilisant des éléments optiques
G03H 1/26 - Procédés ou appareils adaptés spécialement pour produire des hologrammes multiples ou pour en obtenir des images, p. ex. procédés pour l'holographie à plusieurs couleurs
G03H 1/04 - Procédés ou appareils pour produire des hologrammes
G11B 7/0065 - Enregistrement, reproduction ou effacement en utilisant des dessins d'interférence optique, p. ex. des hologrammes
An instruction is executed to generate a message digest for a message. The message digest is to be used in authentication of the message. Executing the instruction includes obtaining from the instruction a control indicator and determining, based on the control indicator, an initial chaining value to be used to generate the message digest. The message digest is generated using the initial chaining value and the message digest is provided to be used in the authentication of the message.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
19.
CONTRASTIVE MULTI-OMICS ASSOCIATION LEARNING FOR COMPLEX DISEASES
A plurality of data pairs are created by matching an element from a first modality with an element from a second modality. Each element from the first modality and each element from the second modality are tokenized to obtain first modality tokens and second modality tokens. A model is trained based on the plurality of data pairs, the training comprising learning a first embedding from the first modality tokens via a first attention-based encoder for the first modality and a second embedding from the second modality tokens via a second attention-based encoder for the second modality, calculating a cosine similarity between the first embedding and the second embedding for each data pair and computing a loss between predicted items and ground truth based on the cosine similarity. The predicted items with a minimal loss are validated to obtain at least one candidate therapeutic.
G16H 20/40 - TIC spécialement adaptées aux thérapies ou aux plans d’amélioration de la santé, p. ex. pour manier les prescriptions, orienter la thérapie ou surveiller l’observance par les patients concernant des thérapies mécaniques, la radiothérapie ou des thérapies invasives, p. ex. la chirurgie, la thérapie laser, la dialyse ou l’acuponcture
G16H 50/20 - TIC spécialement adaptées au diagnostic médical, à la simulation médicale ou à l’extraction de données médicalesTIC spécialement adaptées à la détection, au suivi ou à la modélisation d’épidémies ou de pandémies pour le diagnostic assisté par ordinateur, p. ex. basé sur des systèmes experts médicaux
A computer-implemented method, according to one approach, includes: computing a first cryptographic term in response to receiving a session request from a user. The first cryptographic term is split into an initial portion and a remainder portion, where the remainder portion includes at least one bit. The initial portion of the first cryptographic term is sent to the user, and two or more different potential second cryptographic terms are received from the user. The at least one bit in the remainder portion is used to determine a correct one of the potential second cryptographic terms. Moreover, the correct one of the potential second cryptographic terms is used to compute a third cryptographic term. Furthermore, the third cryptographic term is sent to the user.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/30 - Clé publique, c.-à-d. l'algorithme de chiffrement étant impossible à inverser par ordinateur et les clés de chiffrement des utilisateurs n'exigeant pas le secret
Embodiments of the present disclosure are directed to L-shaped stacked field effect transistor (SFET) processing methods and resulting structures having separate top and bottom self-aligned contact (SAC) caps. In a non-limiting embodiment, a first nanosheet stack having a first nanosheet and a second nanosheet stack having a second nanosheet are vertically stacked. A gate is formed around a channel region of the first nanosheet and a channel region of the second nanosheet. The gate includes a first portion recessed to a first gate height and a second portion recessed to a second gate height less than the first gate height. A bottom self-aligned contact cap is formed on the second portion of the gate and a top self-aligned contact cap is formed on the first portion of the gate.
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Dynamically controlling access to confidential data is provided. The method comprises receiving input of a user security profile that specifies data access privileges for a user. Natural language processing is used to analyze a number of documented communications among authorized personnel regarding work related to the confidential data. From the analysis of the documented communications, a task is identified for the user that requires access privileges to the confidential data that the user security profile does not authorize. An urgency score for the task is calculated from the analysis of the documented communications. Responsive to a determination that the urgency score exceeds a specified threshold, an access control workflow is automatically initiated that is routed to an authorizing agent. Authorization is received in near real-time from the authorizing agent, wherein the user security profile is updated to allow access to the confidential data for a specified duration.
An instruction to perform cryptographic processing is executed. Executing the instruction includes performing a plurality of operations to generate a cryptographic result. Based on performing at least multiple operations of the plurality of operations, an access exception condition for a storage location used by an instrumentation counter is detected. Based on detecting the access exception condition, execution of the instruction is interrupted. The instruction is re-executed to obtain access to the instrumentation counter. The re-executing the instruction starts from where execution was interrupted and includes updating the instrumentation counter, based on the storage location used for the instrumentation counter being validated.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
Holographic storage hardware enabled locking includes directing a first reference beam associated with a first process at a storage location in a holographic data storage medium, and detecting, with a detector while the first reference beam is directed at the storage location, whether a second reference beam associated with a second process is also directed at the storage location. Based on the detecting, a signal is generated indicating whether the storage location is locked.
An exemplary stacked semiconductor structure includes a first integrated device structure having a first frontside and a first backside in which the first backside comprises a first backside power distribution network, a seconded integrated device structure having a second frontside and a second backside in which the second backside comprises a second backside power distribution network, a plurality of hybrid bond connections between the first frontside and the second frontside, at least one first power bump on the first frontside configured to deliver power to the first backside power distribution network, and at least one second power bump on the second backside configured to deliver power to the second backside power distribution network.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
26.
USING METADATA TO SELECTIVELY PERFORM DATA PRESTAGING
A computer-implemented method, according to one approach, includes: receiving a read request for data in memory and analyzing metadata from volumes that contain the requested data. The metadata maps sequential logical addresses of the requested data to their corresponding physical addresses. The computer-implemented method also includes determining whether the corresponding physical addresses storing the requested data are sequential. In response to determining that at least a predetermined number of the corresponding physical addresses are sequential, the requested data is prestaged from the sequential ones of the physical addresses. However, in response to determining that fewer than the predetermined number of the corresponding physical addresses are sequential, the computer-implemented method includes intentionally refraining from prestaging any of the requested data from the physical addresses.
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
27.
SOCKET DOWNSTOP CREEP DETECTION WITH IN-LINE ELECTRICAL MEASUREMENTS
Methods, systems, and products for socket downstop creep detection includes enabling a current source on a creep detection circuit coupled to one or more creep detection pins within a PCB socket coupled to a module, tracking one or more resistance values associated with the creep detection circuit, and detecting socket downstop creep associated with the module based on determining that the one or more resistance values have changed by more than a threshold amount.
According to one embodiment, a method, computer system, and computer program product for deploying mobile charging units for electric vehicles. The embodiment may include receiving data from a set of Internet-of-Things (IoT) enabled electric vehicles (EVs). The data includes a current percentage of remaining battery power for an IoT enabled EV of the set of IoT enabled EVs. In response to determining that the current percentage of remaining battery power for the IoT enabled EV falls below a specified EV battery threshold, the embodiment may include selecting at least one IoT enabled mobile charging unit (MCU) from a set of IoT enabled MCUs. The embodiment may include deploying the selected at least one IoT enabled MCU to a determined geographic location. The embodiment may include notifying a user of the IoT enabled EV of availability of the selected at least one IoT enabled MCU at the determined geographic location.
An image feature vector for a given video frame is generated from a given video and an audio feature vector for audio of the given video is generated. A textual description of the given video frame is generated and textual feature vectors are generated from the textual description. A first set of audio features of the audio feature vector and visual features of the image feature vector are fused to generate fused audio-visual features. A second set of audio features of the audio feature vector and the textual feature vectors are fused to generate fused audio-text features. A final mask is generated based on the fused audio-visual features and the fused audio-text features.
G06V 10/80 - Fusion, c.-à-d. combinaison des données de diverses sources au niveau du capteur, du prétraitement, de l’extraction des caractéristiques ou de la classification
G06V 20/40 - ScènesÉléments spécifiques à la scène dans le contenu vidéo
Method and apparatus of forming a flex circuit to a three dimensional shape using pressurized airflow. In one embodiment, pressurized airflow creates an air flow between the forming fixture and the flex circuit which avoids or mitigates problems that arise during traditional methods of shaping the forming fixture. An air flow allows an even distribution of pressure that can more evenly shape the flex circuit to a desired shape. An air flow between the forming fixture and the flex circuit distributes pressure evenly.
A multiple input linear voltage regulator includes an output port configured to supply an output voltage to one or more processor components; a first regulating transistor operable to receive a first input voltage from a first supply and provide a first regulated voltage range to the output port; a second regulating transistor operable to receive a second input voltage from a second supply and provide a second regulated voltage range to the output port, wherein the first input voltage is different from the second input voltage; and a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage.
G05F 1/59 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de réglage final pour une charge unique
G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
32.
POWDER FUSION THREE-DIMENSIONAL ADDITIVE MANUFACTURING SYSTEM CONFIGURED TO DYNAMICALLY ADJUST ALIGNMENT OF POWDER BED POSITION IN REAL TIME
A powder fusion three-dimensional (3D) additive manufacturing (AM) system is provided. The powder fusion 3D AM system implements a plurality of robotic stages and a plurality of robotic barriers. The plurality of robotic stages have an adjustable upper surface. Each of the robotic stages is configured to self-align themselves to form a foundation of a modular powder bed. The plurality of robotic barriers have vertical walls. Each of the robotic barriers are configured to self-align with the foundation established by the robotic stages. An upper surface of at least one of the robotic stages is adjusted to set an initial height of the modular powder bed configured to receive an AM powder.
B29C 64/153 - Procédés de fabrication additive n’utilisant que des matériaux solides utilisant des couches de poudre avec jonction sélective, p. ex. par frittage ou fusion laser sélectif
A device comprises a first semiconductor structure disposed on a second semiconductor structure, and a plurality of metal structures at an interface portion of the first semiconductor structure and the second semiconductor structure. The first semiconductor structure comprises a first part of an inductor structure and the second semiconductor structure comprises a second part of the inductor structure. The plurality of metal structures connect the first part of the inductor structure with the second part of the inductor structure.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
34.
[DATA COMPARISON WITHOUT INTERRUPTION TO A DATABASE MANAGEMENT SYSTEM
Tables are selected based on timestamp columns to obtain tables changed during a given time period and the selected tables are split into data blocks based on given partition ranges. Changes to data of the data blocks are incrementally copied into datasets. One or more tablespaces identified using a first structured query language query corresponding to a specified timestamp are unloaded based on output of the incrementally copying changes operation. Data of a source site and a target site are compared based on data blocks having the specified timestamp.
G06F 16/215 - Amélioration de la qualité des donnéesNettoyage des données, p. ex. déduplication, suppression des entrées non valides ou correction des erreurs typographiques
G06F 16/22 - IndexationStructures de données à cet effetStructures de stockage
35.
GENERATING A VIEW OF A DATASET IN A DATA LAKEHOUSE BASED ON USER INTENT
Described are techniques for generating a query based view of appropriate datasets in a data lakehouse. A query for data contained in the data lakehouse is received. A similarity between the query and a description of each table in the lakehouse is computed. Any description of a table with a similarity to the query that is greater than a threshold value results in the table potentially being included in a view. As a result, such a table is selected. A subset of the selected tables is then identified and joined to create a new view of a dataset. After generating a description of the new view based on headers and values of the dataset, a similarity between the query and the description of the new view is computed. If the similarity measure exceeds a threshold value, then the newly constructed view is displayed to the user.
Parallelizing functions in deep learning models within homomorphic encryption environments is provided. The method comprises arranging layers in a deep learning model architecture. The layers comprise a first layer computed using a sign function and a second layer having components that can be pre-computed or ignored once computing the sign function on the second layer, wherein the first layer and second layer are adjacent within the deep learning model architecture. The deep learning model architecture is trained with a number of hyper-parameters, and the trained deep learning model architecture is run under homomorphic encryption.
Semiconductor devices include a first bottom field effect transistor (FET) having a bottom source/drain (S/D) structure. A top FET is above the bottom FET and has a top S/D structure. A backside top contact is in electrical contact with a bottom surface and a side surface of the top S/D structure and extends below the bottom FET. A dielectric liner, disposed along sidewalls of the backside top contact, separates the backside top contact from the bottom S/D structure.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A write chip comprising an array of write transducers and writer bond pads is obtained, each write transducer of the array of write transducers connected to a pair of bond pads of the writer bond pads via electrically conducting signal wires, the write chip comprising a write notch. A read chip comprising an array of read transducers and reader bond pads is obtained, each read transducer of the array of read transducers connected to a pair of bond pads of the reader bond pads via electrically conducting signal wires, the read chip comprising a read notch. The read chip and the write chip are secured together such that a distance between the write transducer array and the read transducer array is less than 100 microns, an orientation of the write notch exposes the reader bond pads, and an orientation of the read notch exposes the writer bond pads.
A PCM memory structure having extended projection liner material portion to reduce conductance value in a SET state and increase power efficiency. The projection liner material layer includes bottom and vertically extending liner sidewall portions. A phase change material (PCM) layer positioned above the projection liner material layer also has vertically extended PCM sidewall portions that are shorter than the vertically extending liner sidewall portions, thereby increasing the length of the liner relative to a length of the PCM layer. In a RESET state, current flow bypasses an amorphous volume to reduce the device non-idealities yet leverage the in-plane resistivity of the liner to provide projection in the RESET states and to lower the conductance in the SET states of the device thereby reducing current and power dissipation and power consumption will be lowered when in a SET state.
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
An apparatus including a plurality of vertically oriented insulating substrates, each substrate having a planar surface including a looped metal coil structure forming a planar inductor. Each of the substrates and formed planar inductors arranged in parallel and oriented vertically and adjacent each other in a series configuration for increased inductance. The formed inductor and substrate disposed vertically with respect to a horizontal axis and is inclined at an angle with respect to a vertical axis, the angle ranging between less than 90 degrees and greater than 0 degrees. A first magnetic material plate is disposed adjacent the planar inductor at a first planar surface of the substrate, and a second magnetic material plate disposed adjacent a second planar surface having a conductive trace connecting one end of the planar inductor, each first and second plate extending to limit a spatial extent of the magnetic fields created by the inductor.
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
Methods, computer program products, and systems are presented. The method computer program products, and systems can include, for instance: training a machine learning model in dependence on traffic between at least a first service and a second service defining an application; querying the machine learning model; generating service characterizing data that characterizes at least one service defining the application, wherein the generating the service characterizing data is in dependence on the querying of the machine learning model; and modifying a performance attribute of the application in dependence on characterizing data of the service characterizing data.
An exemplary system comprises a memory that stores and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise an optimizing component that generates a fleet-level solution for maintaining a vehicle-to-grid (V2G) system by a fleet of electric vehicles (EVs), and a scheduling component that constructs a schedule for bidirectional charging of a portion of the fleet by disaggregating the fleet-level solution based on a multi-class classification resulting from an execution of a quantum algorithm, based on a covariant quantum kernel, on a quantum system. In one or more embodiments, the multi-class classification comprises classes of charging, discharging, and no bidirectional charging.
H02J 3/46 - Dispositions pour l’alimentation en parallèle d’un seul réseau, par plusieurs générateurs, convertisseurs ou transformateurs contrôlant la répartition de puissance entre les générateurs, convertisseurs ou transformateurs
B60L 53/63 - Surveillance et commande des stations de charge en réponse à la capacité du réseau
B60L 53/64 - Optimisation des coûts énergétiques, p. ex. en répondant aux tarifs d'électricité
B60L 53/68 - Surveillance ou commande hors site, p. ex. télécommande
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
H02J 3/32 - Dispositions pour l'équilibrage de charge dans un réseau par emmagasinage d'énergie utilisant des batteries avec moyens de conversion
A structure comprising: a back-end-of-line portion on top of a device, wherein the device comprises a hot circuit and a cold circuit; a wafer on top of the back-end-of-line portion; a backside power distribution network on a side of the wafer; a thermal sink underneath the device and the backside power distribution network; and one or more scaling balls underneath the thermal sink and on top of a laminate.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
44.
EXTENDED GATE AND STANDARD GATE INTEGRATION SCHEME
Embodiments of the invention include a semiconductor structure having a first transistor including first channel regions, a high-k dielectric layer on the first channel regions, and gate material on the high-k dielectric layer. A second transistor includes second channel regions, a nitride layer on the second channel regions, the high-k dielectric layer on the nitride layer, and the gate material on the high-k dielectric layer. The first and second channel regions include a corresponding number of semiconductor layers.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/51 - Matériaux isolants associés à ces électrodes
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
An interconnect structure includes hybrid-bonded first and second interposers. The first interposer has a first surface including a layer of insulation and a BEOL below the layer of insulation. The layer of insulation has a first recess in the layer exposing a metal conductor of the BEOL, and the first recess is filled with a material changing from nonconducting to conducting upon being heated above a predetermined temperature. The layer of insulation has a second recess in the layer exposing a metal conductor of the BEOL, and the second recess is filled with metal. The second interposer has a similar construction. Upon hybrid bonding, the material that changes from non-conducting to conducting forms an anti-fuse.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A multi-directional heatsink cooling system for cooling a device including a heatsink base in a first plane. The heatsink base is connected to a device requiring cooling. A plurality of heatsink fins attach to the heatsink base in a perpendicular or parallel orientation to the first plane. The plurality of heatsink fins are arranged to accept external cooling in multiple directions. A plurality of heat pipes extend through the plurality of heatsink fins. The plurality of heat pipes are connected to the heatsink base. Two or more air diverters, each air diverter associated with cooling the plurality of heatsink fins in a single air path of a plurality of air paths. Each air path is associated with exactly one of the multiple directions of the heatsink fins and thereby cool the plurality of heatsink fins.
An electrode probing structure includes a first array of electrodes arranged to be radially spaced apart about a spatial point. A second array of electrodes is arranged parallel to the first array of electrodes, creating a space between the first array and the second array. An inlet is disposed adjacent the first or the second array of electrodes to introduce a fluid containing particles into the space between the first and the second array of electrodes. One or more outlets are disposed adjacent the first or the second array of electrodes to remove the particles from the space between the first and second array of electrodes. Each pair of parallel electrodes of the first array of electrodes and the second array of electrodes, when provided with an electric potential, generates signals corresponding to at least one characteristic of the particles present in the space between the electrodes.
G01N 15/12 - Recherche de particules individuelles en mesurant des effets électriques ou magnétiques en observant des changements de résistance ou d’impédance à travers des fentes traversées par des particules individuelles, p. ex. en utilisant le principe de Coulter
48.
WRAP AROUND CONTACT WITH SELF-ALIGNED GATE ISOLATION
Semiconductor devices with self-aligned gate isolation and wrap around source/drain contacts are provided. In one aspect, a semiconductor device includes: at least a first FET (FET1) and a second FET (FET2), adjacent to one another on a wafer; a dielectric bar between gates of the FET1 and the FET2, and between source/drain regions of the FET1 and the FET2; and wrap around source/drain contacts that at least partially surround the source/drain regions of the FET1 and the FET2. A shallow trench isolation (STI) region can be present between the FET1 and the FET2 and the dielectric bar can be centered over, and directly contact the STI region. Portions of the dielectric bar between the gates and between the source/drain regions can have a height H1 and H2, respectively, where H1>H2. A method of fabricating the present semiconductor device is also provided.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a deep via connecting a first source/drain (S/D) to a backside power rail (RB) below the first S/D, a dielectric etch stop inner spacer below the first S/D, and an RB sidewall surrounding the RB comprising an edge laterally overlapping the dielectric etch stop inner spacer.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
An embodiment detects, using a sensor installed within a building, a first position of a first noise source. The embodiment generates a first noise control configuration comprising a first directional acoustic loudspeaker and a first frequency and first amplitude of a first acoustic tone, the first frequency and first amplitude of the first acoustic tone, when generated by the first directional acoustic loudspeaker, selected to attenuate the first noise source at a first distance from the first position. The embodiment generates, according to the first noise control configuration, the first acoustic tone.
G10K 11/178 - Procédés ou dispositifs de protection contre le bruit ou les autres ondes acoustiques ou pour amortir ceux-ci, en général utilisant des effets d'interférenceMasquage du son par régénération électro-acoustique en opposition de phase des ondes acoustiques originales
G06F 40/58 - Utilisation de traduction automatisée, p. ex. pour recherches multilingues, pour fournir aux dispositifs clients une traduction effectuée par le serveur ou pour la traduction en temps réel
According to one embodiment, a method, computer system, and computer program product for adjusting speech rate for an audio input is provided. The present invention may include applying syllable onset analysis to speech input in a buffer period; determining an average inter-syllable time for the buffer period; determining a rate adjustment required for the average inter-syllable time of the buffer period to conform to a target speech rate; applying a smoothing filter to smooth the rate adjustments across multiple sequential buffer periods; and adjusting the buffer period based on the smoothed rate adjustment.
Provided are techniques for training and using machine learning models to provide counterfactual explanations of predictions. An Artificial Intelligence (AI) predictive model is trained. The AI predictive model is used to generate a prediction label for each item of a plurality of input items. A target item with an initial prediction label. For a morphological segment, a source item is identified from the plurality of input items, where the source item shares common structural features with the target item and has a different prediction label. A recombined item is generated by: masking the morphological segment in the target item and adding the morphological segment of the source item. The AI predictive model is used to generate a new prediction label for the recombined item. It is determined that the new prediction label is different from the initial prediction label and that the recombined item is a counterfactual item.
An instruction is executed to generate an authentication code. Executing the instruction includes performing a plurality of operations of the instruction to generate the authentication code. The plurality of operations includes performing a sequence of hash operations on a message to generate an intermediate message digest, and performing an outer-key padding and hashing operation using the cryptographic key to generate another output chaining value to be used in generating a final output message digest based on a final input message digest produced using the intermediate message digest. The final output message digest being a resulting authentication code. The performing the sequence of hash operations and the outer-key padding and hashing operation are performed as part of a single invocation of the instruction.
A system comprises a memory that stores and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise an identification component that identifies a target partition definition for a quantum processor comprising a plurality of qubits, and a mapping component that directs a controller of a quantum system, comprising the quantum processor, to apply the target partition definition to control electronics at the quantum system for subsequent of an operation at the quantum processor, wherein the target partition definition corresponds to a quantum system resource, of the quantum system, associated with a target qubit of the plurality of qubits.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
55.
COAXIAL THROUGH-INSULATOR VIA (TIV) WITH LATERAL METAL FOOTING CONNECTION FOR CHIPLET POWER SIGNAL CONNECTION
A semiconductor structure includes a first wiring region including interconnected first metal lines and first vias; an insulator outward of same; and a first circuitry element, located in the insulator, and connected to at least a first one of the first vias. A coaxial through dielectric via is located in the insulator, which includes an inner conductor, a dielectric layer surrounding the inner conductor, and an outer conductor outward of the dielectric layer. The outer conductor includes inner and outer footing structures. A second wiring region is outward of the insulator, and includes a signal line connected to the inner conductor and a power line connected to the outer footing structure. The inner conductor is connected to at least a second one of the first vias and the inner footing structure is connected at least a third one of the first vias.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
56.
HIERARCHICAL AND PEER PRUNING STRATEGIES FOR GENERATIVE ARTIFICIAL INTELLIGENCE MODELS IN TELECOMMUNICATIONS NETWORKS
Provided are a method, system, and computer program product for hierarchical inference utilizing a large language model (LLM). Training is performed at a central location, of a helper model and a pruned model for each layer of a hierarchy, wherein the helper model is trained to classify a request as appropriate for the pruned model, and wherein the pruned model is generated from a reduction process of the LLM. A process distributes the helper model and pruned model to different levels of the hierarchy. The process directs, by utilizing the helper model at each level of the hierarchy, inference generation to the pruned model or to another model at a higher tier.
Structures including semiconductor chips (including chiplets and stacked chips/chiplets) are provided in which thermal heat removal is enhanced. The enhanced thermal heat removal is provided by utilizing interlayer dielectric (ILD) materials in at least one of the frontside back-end-of-the-line (BEOL) structure or the backside BEOL structure that have a high thermal conductivity.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
58.
SEMICONDUCTOR DEVICE WITH BACKSIDE SUBSTRATE CUT UNDER THE STI STRUCTURE
A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source/drain region, a second portion of the first substrate extending vertically below a second source/drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through the horizontal portion of the first substrate and connected to the first STI and the BSPDN, and an oxide trench wall over sidewalls of a backside contact.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor device includes a passive device including a set of P-type doped regions, a set of N-type doped regions, a first N-well region and a second N-well region below the set of P-type doped regions and the set of N-type doped region, respectively, a first shallow trench isolation (STI) between the first N-well region and the second N-well region, a substrate below the first STI; and a dielectric break within the substrate. The dielectric break is vertically extended from the first STI to a bottom interlayer dielectric (BILD) below the substrate.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A determination is made of whether a network attack is suspected. In response to determining that the network attack is suspected, a generation of a snapshot of volumes of data is requested via a low latency link. The snapshot of the volumes of data is generated while the volumes of data are blocked from access and prior to an occurrence of an effect of the network attack on the volumes of data.
Mechanisms are provided for training an Automatic Speech Recognition (ASR) model. An automatic speech recognition (ASR) computer model is trained based on full utterance training data, the ASR computer model having an audio encoder, text predictor, and a joint network which combines outputs of both the audio encoder and the text predictor. Fine-tuning training of the ASR computer model is performed by a knowledge distillation framework at least by: executing a chunking operation on full utterance data to generate a plurality of data chunks corresponding to full utterances in the full utterance data; and executing a knowledge distillation operation with two encoder embeddings. A first encoder embedding is obtained from the full utterance data and a second encoder embedding is obtained from the data chunks. Operational parameters of the trained ASR model are updated based on a loss determined from the first encoder embedding and second encoder embedding.
G10L 15/06 - Création de gabarits de référenceEntraînement des systèmes de reconnaissance de la parole, p. ex. adaptation aux caractéristiques de la voix du locuteur
G10L 15/01 - Estimation ou évaluation des systèmes de reconnaissance de la parole
A magnetic tape defined with one or more data partitions and one or more parity partitions is obtained, wherein each of the data partitions is separated from each of the parity partitions corresponding to the given data partition by a given minimum distance, wherein the given minimum distance is greater than a length of the magnetic tape affected by a permanent error and wherein each data partition comprises data information and each parity partition comprises in-line erasure coding information. The magnetic tape is written based on the one or more data partitions and the one or more parity partitions.
A semiconductor structure includes a first set of vertically stacked contacts, a second set of vertically stacked contacts, a first set of stacked transistor devices associated with the first set of vertically stacked contacts, and a second set of stacked transistor devices associated with the second set of vertically stacked contacts. The second set of stacked transistor devices is adjacent to the first set of stacked transistor devices, and a dielectric isolation pillar is disposed between the first set of vertically stacked contacts and the second set of vertically stacked contacts.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor has a gate line with a gate line opening flanked by a pair of source/drains. In the gate line opening are a bottom transistor and a top transistor. The bottom transistor includes a bottom set of nanosheets wrapped by a bottom workfunction material while the top transistor includes a top set of nanosheets wrapped by a top workfunction material. A dielectric structure separates the bottom transistor and the top transistor. The dielectric structure includes a middle dielectric portion (which can be L-shaped), a first plug laterally contacting a first side of the middle dielectric portion and a second plug laterally contacting a second side of the middle dielectric portion.
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Managing per-thread stop-the-world garbage collection is provided. A set of threads of a plurality of threads is transitioned from a normal thread state to a no-read-no-write thread state at a first safepoint of a pair of contiguous safepoints using a first set of thread transition code inserted in program code of an application at the first safepoint. Execution of any remaining threads of the plurality of threads having a normal thread state is suspended at the first safepoint. Stop-the-world garbage collection of a memory heap dedicated to the application is performed while allowing the set of threads of the plurality of threads having the no-read-no-write thread state to continue execution in a region within the program code between the pair of contiguous safepoints based on a special status tag of the first safepoint of the pair of contiguous safepoints.
A set of candidate drugs is selected based on one or more outcomes related to one or more diseases and variants linked with the selected set of candidate drugs are obtained. One or more protein sequences related to the selected set of candidate drugs are collated. Pairs of variants and protein sequences are generated for each drug of the set of candidate drugs. A contrastive learning model is trained using the generated pairs of variants and protein sequences and a downstream task is performed using the contrastive learning model.
G16C 20/50 - Conception moléculaire, p. ex. de médicaments
G16B 30/00 - TIC spécialement adaptées à l’analyse de séquences impliquant des nucléotides ou des aminoacides
G16B 40/00 - TIC spécialement adaptées aux biostatistiquesTIC spécialement adaptées à l’apprentissage automatique ou à l’exploration de données liées à la bio-informatique, p. ex. extraction de connaissances ou détection de motifs
67.
HEAT SPREADING AND THERMAL HEAT REMOVAL STRUCTURES
Semiconductor structures are provided in which heat spreading and thermal heat removal are improved by providing one or more heat removal paths in which heat spreading and thermal heat removal occurs leveraging horizontal direction and vertical directions and through reduced resistance of heat removal paths. Notably, heat is spread horizontally to the edges of the semiconductor structures and then the heat is removed vertically (up and/or down) from the semiconductor structures.
H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An instruction includes a control mode indicator and is executed to perform an action defined by the instruction. Execution of the instruction includes checking the control mode indicator and re-defining, based on the control mode indicator being a selected value, one or more instruction areas used by the instruction to provide other functionality of the instruction. The action defined by the instruction is performed using at least a portion of the other functionality provided by the re-defining the one or more instruction areas.
Managing container images is provided. A number of a set of changed files included in a plurality of upgraded files is determined in response to identifying the set of changed files. It is determined whether the number of the set of changed files included in the plurality of upgraded files is greater than a defined file change threshold level. In response to determining that the number of the set of changed files included in the plurality of upgraded files is not greater than the defined file change threshold level, a new increment file layer that is in addition to an original file layer of a plurality of original layers is generated in an upgraded container image of an original container image. The set of changed files is copied in the new increment file layer of the upgraded container image.
Provide an initial structure including a bottom electrode layer, a phase change material layer outward of the bottom electrode, a top electrode layer outward of the phase change material layer, and a patterned hard mask outward of the phase change material layer. Etch the initial structure using a first halogen plasma etchant at high wafer temperature to partially remove portions of the top electrode layer not protected by the patterned hard mask to produce an intermediate structure. Etch the intermediate structure using a second halogen plasma etchant at low wafer temperature to remove a remaining portion of the top electrode layer down to the phase change material layer, leaving a web of top electrode layer material under the patterned hard mask. Etch portions of the phase change material layer not protected by the web of top electrode layer material down to the bottom electrode layer, and remove the patterned mask.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
Computer implemented methods, systems, and computer program products include program code executing on a processor(s) monitors query execution within the database system within the multiple databases and by the multiple query optimization engines. The program code retains statistical information from the monitoring in a centralized database. The program code obtains, at a query optimization engine of the database system, a new query. The program code predicts, based on accessing the statistical information in the centralized database, that executing the new query with the query optimization engine at a designated execution time comprises a suboptimal execution of the new query. The program code alters a planned execution of the new query at the designated execution time with the query optimization engine to optimize execution of the query within the database system.
Provided are a computer program product, system, and method for a machine learning model trained to not output data to unlearn. A query is processed at a first set of layers of the L layers of the machine learning model to determine interim output. The interim output is classified as data to unlearn or data to keep. The interim output is processed at a second set of layers of the L layers of the machine learning model to produce a first output in response to classifying the interim output as data to keep. The interim output is inputted to an edited machine learning model formed from the second set of layers to output second output in response to classifying the interim output as the data to unlearn from the machine learning model. The first output or the second output is returned as a response to the query.
An integrated circuit includes at least three vertically arranged device layers, which are separated from one another by a horizontal space and at least one vertically extending device column. A semiconductor device is disposed in each of the at least three device layers and is aligned vertically in the device column. At least one vertically extending first-type signal line column includes a plurality of first-type signal line pairs that extend through the horizontal space to establish a first electrical connection with the at least one semiconductor device disposed in the at least three device layers. At least one second-type signal line column extends vertically and includes at least one second-type signal line that establishes a second electrical connection with the at least one semiconductor device disposed in the at least three device layers.
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
A memory device comprising: a first electrically conductive structure (14); a metal cap (18) located on the first electrically conductive structure; a magnetic tunnel junction-containing, MTJ-containing, pillar located above the metal cap; a bottom electrode (26) having a serpentine pattern located between the metal cap and the MTJ-containing pillar, wherein the bottom electrode has a bottommost surface that is in contact with the metal cap and a topmost surface in contact with the MTJ-containing pillar; a top electrode (38) located on the MTJ-containing pillar; and a second electrically conductive structure (48) electrically connected to the top electrode.
An exemplary system comprises a memory that stores and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise an obtaining component that intercepts a semantic source from being submitted to a retrieval augmented generation (RAG) architecture, and a transforming component that transforms the semantic source into a transformed source by identifying and converting prompt-misleading text of the semantic source into prompt-non-misleading text. In one or more embodiments, the semantic source is a semantic query having been submitted to the RAG architecture and/or a retrieved source having been retrieved by the RAG architecture in a process of providing a prompt. In one or more embodiments, the prompt- misleading text originated in connection with an origination of the semantic source and/or was caused by an adversarial attack corresponding to the semantic source.
A cipher instruction is executed. The executing the cipher instruction includes encrypting a confidential value to provide an encrypted confidential value and generating a mask value using the encrypted confidential value. A cipher operation is performed on at least a portion of a message specified by the cipher instruction. The performing the cipher operation on the at least the portion of the message uses the mask value. A result of the cipher operation is provided.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
77.
PROTECTION OF CRYPTOGRAPHIC PARAMETERS USED IN CRYPTOGRAPHIC PROCESSING
A cipher instruction is executed that includes encrypting a confidential value. A power block sequencing value is obtained as input to the cipher instruction, and a mask value is generated using the encrypted confidential value and the power block sequencing value. A cipher operation is performed on at least a portion of a message specified by the cipher instruction using the mask value. The power block sequencing value is updated, based on performing the cipher operation of the at least the portion of the message, to provide an updated power block sequencing value to be used in re-execution of the cipher instruction based on the cipher instruction being interrupted. The updated power block sequencing value is to be provided as input to the cipher instruction based on the cipher instruction being re-executed to re-generate the mask value to be used in continuing the cipher operation of the message.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
78.
ADDING POLICY CODING TO PACKET HEADERS FOR A USER AT A CLIENT DEVICE TO USE TO ACCESS RESOURCES IN A SECURE NETWORK
Provided are a computer program product, system, and method for adding policy coding to packet headers for a user at a client device to use to access resources in a secure network. Packets are received from a user at a client device. A determination is made of policy information for the user defining user permissions to access resources in the secure network. Packets from the user are decapsulated and policy information is included in packet headers of the decapsulated packets to transmit within the secure network. An enforcement point applies policy rules to the policy information in the packet headers to determine whether to forward the packets to a destination resource.
A device comprising a connector configured to electrically connect a measurement device on an annular ring on a first side of a Plated Through Hole (PTH), a probe connected to the measurement device and configured to touch an interior wall of the PTH at a first location, a motor control and a motor to move the probe in the PTH, and a sensor, in the measurement device, to detect electrical measurements through the PTH from the connector to the probe.
Aspects of utilizing formate shells for metal structures on integrated circuit components include an integrated circuit device component including one or more metal interconnect structures and a formate shell on each of the one or more metal interconnect structures.
An embodiment of the present invention includes a system for detecting and mitigating vulnerabilities in machine learning models. The system produces, via a machine learning model, responses to input data. The input data includes data that causes the machine learning model to produce proper and improper responses. Information associated with the input data and responses is maintained. The information includes timing information for the responses. A probability for a time to an improper response for the machine learning model is determined based on the maintained information. A hazard level for the machine learning model is identified based on the probability for the time to an improper response. Embodiments of the present invention further include a method and computer program product for detecting and mitigating vulnerabilities for machine learning models in substantially the same manner described above.
A method of this disclosure may comprise receiving a task described at least in part with natural language; instructing a public language model to split the task into a plurality of sub-tasks based on a capability of an operation pool which includes a plurality of private services, and to pair the plurality of sub-tasks with respective private services; and instructing the respective private services to perform the plurality of sub-tasks so as to complete the task.
The present disclosure relates to a qubit device comprising a first superconducting loop containing one Josephson junction, and a second superconducting loop having an inductance higher than an inductance of the first superconducting loop.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
A method, computer program product, and computer system optimizing a scheduling instance for a work process and performing the work process in accordance with the optimized scheduling instance. A pool P of C candidate tasks of a work process is generated. The work process is characterized by an initial scheduling instance that includes tasks. A total of k output scenarios are generated, where k≥2. Each output scenario includes b tasks selected from the pool P, where b≥2. A modified schedule instance (MSI) for each output scenario is generated and key performance indicators (KPIs) associated with each MSI are generated. The generated MSIs and KPIs are outputted. One MSI of the generated MSIs is selected. The work process is performed in accordance with the selected one MSI, wherein the KPIs associated with the selected one MSI improve the work process.
A method, computer system, and a computer program product for sustainable data storage is provided. A sustainable storage program receives raw data comprising data access statistics and power consumption of data currently in storage tiers. The received data is tagged by a usage model based on data context. The tagged data is vectorized, whereby the vectorizing includes clustering data types, and identifying a storage tier for each data type. The vectorized and tagged data is stored in a vector database. Incoming data is assigned to a storage tier based on a similarity search of the vector database, whereby the similarity measures the proximity or distance of two vectors in the vector database. The usage model and the vector database are continuously updated and monitored.
A device comprising a connector configured to electrically connect a measurement device on an annular ring on a first side of a Plated Through Hole (PTH), a probe connected to the measurement device and configured to touch an interior wall of the PTH at a first location, a motor control and a motor to move the probe in the PTH, and a sensor, in the measurement device, to detect electrical measurements through the PTH from the connector to the probe.
A computer-implemented method (CIM), according to one embodiment, includes, in response to receiving a first packet from a first application, performing a predetermined process for determining a low carbon emission transmission route along a source to a target. The predetermined process includes predicting for each of a plurality of devices between the source and the target, carbon emissions that would result from using the device for transmitting the first packet, and generating a carbon emission map. The predetermined process further includes selecting, from the carbon emission map, a first transmission route that hops along at least one of the devices, where the first transmission route is selected over a second transmission route based on the second transmission route having a greater carbon emission than the first transmission route. The CIM further includes causing the first packet to be transmitted from the source to the target along the first transmission route.
An integrated circuit includes at least three vertically arranged device layers, which are separated from one another by a horizontal space and at least one vertically extending device column. A semiconductor device is disposed in each of the at least three device layers and is aligned vertically in the device column. At least one vertically extending first-type signal line column includes a plurality of first-type signal line pairs that extend through the horizontal space to establish a first electrical connection with the at least one semiconductor device disposed in the at least three device layers. At least one second-type signal line column extends vertically and includes at least one second-type signal line that establishes a second electrical connection with the at least one semiconductor device disposed in the at least three device layers.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
A magnetoresistive-random-access-memory (MRAM) cell includes a bottom electrode, a first layer is located on top of the bottom electrode, a magnetic-tunnel-junction (MTJ) is located on top of the first layer, a top electrode is located on top of the MTJ. A first spacer is located around the bottom electrode, the first layer, the MTJ, and a portion of the top electrode. A second spacer is located around the first spacer. The second spacer is located around the side surfaces and the top surface of the top electrode. A contact is connected to the top electrode, where the contact extends through the second spacer to contact the top electrode.
Migrating data to cloud storage includes identifying, by a storage control unit, data to be migrated to cloud storage. The storage control unit determines unit, that local storage space has reached a threshold. The storage control unit, in response to determining that the local storage space has reached the threshold, migrates data from local storage to cloud storage.
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p. ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
91.
IMPLEMENTING QUANTUM FAN-OUT OPERATION USING DYNAMIC QUANTUM CIRCUITS
A method, system, and computer program product for implementing a quantum fan-out operation. A fan-out gate is constructed using ladders of CNOT gates in a constant depth using a dynamic quantum circuit. Constant depth refers to the depth or number of time steps being independent of the number of qubits. A dynamic quantum circuit is a quantum circuit with mid-circuit measurements and feed-forward classical operations which allows such circuits to be adaptive on-the-fly. The quantum fan-out operation is implemented by the fan-out gate using ancilla qubits and feed-forward operations. In this manner, the quantum fan-out operation can be implemented on superconducting devices at a reduced depth (constant depth) with fewer CNOT gates as well as using fewer ancilla qubits.
H03K 19/195 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des dispositifs supraconducteurs
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
H10N 69/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comportant au moins un élément supraconducteur couvert par le groupe
92.
DEMULTIPLEXING STORAGE VOLUME BOUNDARIES WITHIN VIRTUAL STORAGE BLOCK DEVICE
An architecture for demultiplexing volumes in a storage device includes a virtual machine. A guest operating system is in the virtual machine. The architecture further includes a storage pool of virtual storage blocks and a hypervisor. The hypervisor is configured to organize the storge pool of virtual storage blocks into a plurality of virtual storage partition tables. Device addresses are assigned to the plurality of virtual storage partition tables. The plurality of virtual storage partition tables and the devices addresses are organized into a virtual storage device. The device addresses are presented to the guest operating system in the virtual machine.
A NOR decoder for large decode structures includes a first NOR decode circuit connected by a first node to an evaluation circuit. The first NOR decode circuit is configured to receive a first set of three or more inputs. The evaluation circuit is connected to a second node. The NOR decoder also includes a second NOR decode circuit connected by a third node to the evaluation circuit. The second NOR decode circuit is configured to receive a second set of three or more inputs. The evaluation circuit is configured to change a state of the second node in response to an active clock signal and all inputs in the first set and the second set having the same logical value.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
H03M 7/30 - CompressionExpansionÉlimination de données inutiles, p. ex. réduction de redondance
A semiconductor IC device is presented and includes a first region and a second region. The first region includes a first fin upon a backside interlayer dielectric (ILD) comprising a first fin height or a first effective channel width. The second region includes a second fin upon the backside ILD comprising a second fin height or a second effective channel width that is less than the first fin height or the second effective channel width, respectively. The reduced second fin height or a second effective channel width may be provided by processing the second fin from the backside of the semiconductor IC device.
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
95.
INSTRUCTION TO ACCELERATE CRYPTOGRAPHIC PROCESSING
A cipher instruction is executed. The executing the cipher instruction includes encrypting a confidential value to provide an encrypted confidential value and generating a mask value using the encrypted confidential value. A cipher operation is performed on at least a portion of a message specified by the cipher instruction. The performing the cipher operation on the at least the portion of the message uses the mask value. A result of the cipher operation is provided.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
96.
ADVANCED MULTI-LAYER ACCESS CONTROL POLICY ENFORCEMENT IN A MULTI-TENANT CLOUD ENVIRONMENT
An approach is provided for multi-layer access control policy enforcement in a multi-tenant cloud environment. An advanced policy service is defined in a data container The advanced policy service provides management and validation of an access control policy at multiple levels including an application layer and a low layer, which is at a level lower than the application layer. Using the advanced policy service, a policy definition of the application layer is mapped to an access validation and authorization policy of the low layer. Rules are generated using an analysis of data packets by an eBPF program Using the eBPF program, the policy definition and the rules are applied to a request received from a SaaS application to access a data source. Based on the application of the policy definition and the rules, a data vulnerability is identified and the request is rejected.
A cipher instruction is executed that includes encrypting a confidential value. A power block sequencing value is obtained as input to the cipher instruction, and a mask value is generated using the encrypted confidential value and the power block sequencing value. A cipher operation is performed on at least a portion of a message specified by the cipher instruction using the mask value. The power block sequencing value is updated, based on performing the cipher operation of the at least the portion of the message, to provide an updated power block sequencing value to be used in re-execution of the cipher instruction based on the cipher instruction being interrupted. The updated power block sequencing value is to be provided as input to the cipher instruction based on the cipher instruction being re-executed to re-generate the mask value to be used in continuing the cipher operation of the message.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
98.
UTILIZING FORMATE SHELLS FOR METAL STRUCTURES ON INTEGRATED CIRCUIT COMPONENTS
Aspects of utilizing formate shells for metal structures on integrated circuit components include an integrated circuit device component including one or more metal interconnect structures and a formate shell on each of the one or more metal interconnect structures.
Methods, systems, and products for sustainable Reliability, Availability, and Serviceability (RAS) balancing based on predictive models includes predicting, based on one or more predictive models, a potential failure within a computing system, and provisioning, based on the potential failure, one or more redundant resources for failover.
G06F 11/20 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage actif du défaut, p. ex. en déconnectant les éléments défaillants ou en insérant des éléments de rechange
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p. ex. des interruptions ou des opérations d'entrée–sortie
100.
SYNTHETIC DATA GENERATION QUALITY USING IMMUTABLE TOKENS
Systems, methods, and computer program products are disclosed herein. A method comprises receiving a dataset comprising a plurality of text entities; determining one or more candidate immutable tokens from the dataset; determining one or more immutable tokens from the one or more candidate immutable tokens, based on a predetermined rule or a subject matter expert analysis; generating synthetic data, using a large language model, wherein the large language model is instructed to maintain the one or more immutable tokens; and filtering the generated synthetic data based on compliance with the one or more immutable tokens and the associated rules.
