An embodiment includes detecting by an artificial intelligence system a feature of a machine learning model. The embodiment includes responsive to detecting the feature of the machine learning model, computing by a Counterfactual Engine of the artificial intelligence system a counterfactual objective based on modifying a product of a weight and a perturbation of the feature. The embodiment also includes transforming by the Counterfactual Engine a counterfactual based on the counterfactual objective.
A method, computer system, and a computer program product for code evaluation are provided. Knowledge bases in first and/or second programming languages are searched to find code and associated natural language explanations that correspond to code generated by a machine learning model. Additionally and/or alternatively, the code generated by the machine learning model undergoes code-to-natural language translation by another machine learning model and text summarization via an additional machine learning model. Machine learning semantic comparison of (A) an original prompt submitted to the first machine learning model to generate the code and (B) a natural language explanation obtained via one or more of the above approaches is performed. The machine learning semantic comparison generates a first semantic correctness score which is presented.
A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. A bottom power rail is disposed on the bottom side between source/drain regions of the field effect transistors, and a top power rail is disposed on the top side between source/drain regions of the field effect transistors.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
An intermediate global lower-level machine learning model is generated by executing federated learning model training using data from an identified first set of lower-level non-Byzantine client computers which are characterized as being non-Byzantine for the lower-level system. A global lower-level machine learning model is generated by executing the federated learning model training using data from an identified second lower-level set of non-Byzantine client computers which are characterized as being non-Byzantine for the lower-level system. An intermediate global upper-level machine learning model is generated by executing the federated learning model training using data from an identified first upper-level set of non-Byzantine client computers which are characterized as being non-Byzantine for an upper-level system. A global upper-level machine learning model is generated by executing the federated learning model training using data from a second upper-level set of client computers which are characterized as being non-Byzantine for the upper-level system.
One or more computer-implemented methods, computer systems and/or computer program products of use provided herein relate to employing a task attention mechanism for context window augmentation of a large language model (LLM). In various embodiments, a computer-implemented method comprises receiving, at a machine learning model, first text data. The computer-implemented method further comprises determining, via the machine learning model, a token length of the first text data. The computer-implemented method further comprises in response to determining that the token length is greater than a threshold token length of a first language machine learning model, generating via the machine learning model a first logical graph from the first text data, wherein the first logical graph incorporates tokens exceeding the threshold token length of the first language machine learning model without a portion of the first text data becoming eliminated, and the first logical graph is incorporated within the machine learning model.
Computer-implemented methods for deploying a workload in a cloud computing system are provided. Aspects include identifying resource utilization levels for processors and memory of each of the plurality of compute nodes, calculating, for each nodes, an idle power level, an activation power level, and a dynamic power level, and identifying characteristics of the workload to be deployed. Aspects also include identifying a plurality of locations that are suitable for deployment of the workload, wherein each of the plurality of locations is one of the plurality of compute nodes, calculating, for each of the plurality of locations based on a simulated deployment of the workload at a corresponding location, an estimated power consumption of the Cloud computing system, and deploying the workload on a first compute node, where the first compute node corresponds to a location associated with a lowest estimated power consumption of the Cloud computing system.
Systems and techniques that facilitate controlling TLS via on-chip filtering to prevent qubit energy loss are provided. In various embodiments, a system can comprise a quantum device including a qubit device on a substate. In various embodiments, the quantum device can include an electrode placed in proximity to the qubit device. In various embodiments, an electrical filter can be connected to the electrode. In various embodiments, the quantum device can comprise a voltage source that can be connected to the electrode via the electrical filter. In various embodiments, the voltage source can control a voltage to the electrode to shift a resonant frequency of one or more defects to reduce two level system (TLS) impact on the qubit device.
H10N 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
Aspects of the invention include techniques for providing a large language model with elastic resources. A non-limiting example method includes training a large language model within a parallelized training environment that includes a set of training resources. The large language model is split into a plurality of pieces and each training resource trains over one piece. Baseline metrics are collected for the parallelized training environment. The method includes determining whether a current number of available training resources is an integer multiple of a minimum threshold of training resources and initializing one or more try-runs to evaluate vertical scaling and/or horizontal scaling responsive to the determination. A try-run having a highest improvement metric is identified and, responsive to the highest improvement metric being greater than a predetermined threshold, a training pattern is updated using one or both of a vertical scaling and a horizontal scaling of the set of training resources.
Systems and techniques that facilitate trimmable inductors for qubit frequency tuning are provided. In various embodiments, a device can comprise a Josephson junction. In various aspects, the Josephson junction can be shunted by a capacitor, and a trimmable inductor can couple the Josephson junction to a pad of the capacitor. In various cases, the trimmable inductor can comprise a first conductive path that includes a severable and/or weldable superconducting bridge and a second conductive path that is in parallel with the first conductive path. In various aspects, severing and/or welding the severable and/or weldable superconducting bridge can controllably change an inductance of the trimmable inductor, which can commensurately change a resonant frequency of a qubit formed by the Josephson junction and the capacitor.
An embodiment of the present invention includes a system for controlling access and usage of data. The system comprises one or more memories, and at least one processor coupled to the one or more memories. The system generates a data usage configuration from a document specifying requirements for a dataset in a natural language. The data usage configuration indicates access and operations for the dataset. The dataset is retrieved from a data storage unit in accordance with the data usage configuration. The operations performed on the dataset are controlled based on the data usage configuration. Embodiments of the present invention further include a method and computer program product for controlling access and usage of data in substantially the same manner described above.
Embodiments are related to providing systematic delayering of chips, such as finFET chips, along with performing field failure and material investigation. Techniques include receiving information from a gyroscope unit, a vacuum stage being connected to a sample, the vacuum stage being configured to maintain a position of the sample to a polishing table. Techniques include adjusting the position of the sample based, at least in part, on the information received from the gyroscope unit.
Computer-implemented methods for runtime sharing of multiple neural network models in a computing system are provided. Aspects include receiving a request to store first neural network model (NNM) in the computing system, obtaining parameters of the first NNM, and identifying a base model, from a model database, corresponding to the first NNM. Aspects also include identifying duplicate parameters of the first NNM and the base model and generating a delta file corresponding to non-duplicate parameters of the first NNM and the base model. Aspects further include identifying a physical memory device in the computing system that includes a shared region that includes at least a portion of the base model and loading, in a private region of the physical memory device, the parameters from the delta file.
According to an embodiment of the present invention, a pressurized sleeve for routing of linear components is provided. The pressurized sleeve is disposed to at least partially surround a flexible line object. A plurality of pouches is disposed in the robotic cable sleeve. At least two pouches of the plurality of pouches have different predetermined hydrostatic pressures from one another which induce axial movement of at least a portion of the robotic cable sleeve and a corresponding portion of the at least partially surrounded linear component.
According to an embodiment of the present invention, a method is provided for pressurized routing linear components. The method includes obtaining data related to a project. Features are extracted from the obtained project data. The extracted features include linear component characteristics and project environment characteristics. A project design is obtained based on at least one of user input and predetermined extracted features from the extracted features from the obtained project data. The project design includes installation or uninstallation of a linear component in relation to an apparatus. Pressurization is calculated of a plurality of pouches disposed in a pressurized sleeve for the installation or uninstallation of the linear component in relation to the apparatus based on the project design. The calculated pressurization of the plurality of pouches disposed in the pressurized sleeve is implemented.
A printed circuit board (PCB), vertical conductive structures (VeCSs) for the PCB, and a method of fabricating a printed circuit board (PCB). The VeCS includes a VeCS slot at least partially defined in a dielectric substrate. A vertical signal trace is positioned on a first side of the VeCS slot and a vertical reference trace is positioned on a second side of the VeCS slot opposite the vertical signal trace. The VeCS has a predetermined impedance. A plurality of signal ground planes is positioned at a respective predetermined distance from the vertical signal trace. Each signal ground plane defines a cutout.
A semiconductor structure comprises at least one bias structure comprising a first diffusion region having a designated doping type, and at least one protection diode comprising a second diffusion region having the designated doping type, wherein the at least one bias structure is connected to the at least one protection diode through at least one contact line.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
Computer technology for providing shortcuts for user interface interactive elements. The method analyzes user interaction frequency with interactive elements of a user interface display and determines a number of most frequently used interactive elements in the display. The method assigns defined shortcut user inputs for the number of most frequently used interactive elements by mapping a shortcut to the interactive element in the display to interact with the interactive element when the shortcut is entered and displays the defined shortcut user inputs for the interactive elements in the display.
G06F 3/0481 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect
G06F 3/04892 - Dispositions pour commander la position du curseur fondée sur des codes indiquant les pas de déplacement du curseur d’une position à une autre, p. ex. en utilisant des touches de commande du curseur associées à des directions différentes ou en utilisant le tabulateur
G06F 9/451 - Dispositions d’exécution pour interfaces utilisateur
Reconfigurable testing of an integrated circuit includes storing, in a register, one or more values indicating at least a partial order in which a plurality of built-in self-test (BIST) engines are to respectively test a corresponding plurality of sets of memory arrays. A logic circuit coupled to the register causes the plurality of BIST engines to test the plurality of sets of memory arrays based on the one or more values stored in the register.
A computer-implemented method (CIM), according to one embodiment, includes validating code blocks in a software document by performing a first validation process. The first validation process includes iterating through lines in the software document to identify the code blocks, extracting the identified code blocks, and determining an amount of a codebase that the code blocks cover, where the codebase is associated with the software document. The first validation process further includes executing the code blocks, and determining whether the code blocks execute correctly. The method further includes generating a report characterizing the software document. The report includes a project coverage metric that indicates the amount of the codebase that the code blocks cover, and an instruction validity metric that indicates an amount of the code blocks that executed correctly during execution of the code blocks. The instruction validity metric is based on a validation of the code blocks.
A method of branch prediction in a processor includes: generating a new line index and an intraline index; generating a first output of a pattern-based predictor structure using the new line index; generating a second output of the pattern-based predictor structure using the intraline index; selecting one of the first output and the second output based on a result of a prediction pipeline; and predicting a direction of a branch using the selected one of the first output and the second output.
According to one embodiment, a method, computer system, and computer program product for distributed edge resilience enhancement is provided. The embodiment may include identifying an adversarial jammer is causing an impact on a wireless system. The embodiment may also include generating a risk assessment of impact caused by the adversarial jammer to a user. The embodiment may further include identifying an action to apply based on the risk assessment. The embodiment may also include performing the identified action.
A semiconductor substrate can be loaded into a plasma chamber, the semiconductor substrate having a through opening within a mask layer disposed over the semiconductor substrate. Using a plasma process, a through substrate via can be formed within the semiconductor substrate. The through substrate via can have a circular shape or an annulus shape with an inner semiconductor core. The plasma process can include exposing the through opening to a plasma chemistry formed from a gas mixture comprising boron, chlorine, fluorine, carbon, and sulfur.
H01L 21/3213 - Gravure physique ou chimique des couches, p. ex. pour produire une couche avec une configuration donnée à partir d'une couche étendue déposée au préalable
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
A release mechanism is provided to connect to a cable connector, with the cable connector being latchable to a connector receptacle. The release mechanism includes a pull release to operatively couple to a latching mechanism of the cable connector to selectively release a latch of the latching mechanism from latching the cable connector to the connector receptacle when operatively coupled to the connector receptacle. The pull release is adapted to, at least in part, break apart in operation in response to a predetermined excess stress event on the pull release to facilitate protecting the cable connector from excessive stress due to the stress event.
H01R 13/633 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz pour la séparation uniquement
A semiconductor device includes a stacked transistor structure having field effect transistors on two levels. The two levels include a top side and bottom side. A bottom power rail is disposed on the bottom side between source/drain regions of the field effect transistors, and a top power rail is disposed on the top side between source/drain regions of the field effect transistors.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
An embodiment establishes a virtual representation of a network configuration, wherein the virtual representation of the network configuration comprises a plurality of layers corresponding to the network configuration. The embodiment generates a plurality of workloads to simulate with the virtual representation. The embodiment generates a plurality of workload statuses to simulate with the virtual representation. The embodiment simulates the plurality of workloads. The embodiment simulates the plurality of workloads statuses. The embodiment receives simulation results responsive to simulating the plurality of workloads and from simulating the plurality of workload statuses.
H04L 41/40 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p. ex. des réseaux de commutation de paquets en utilisant la virtualisation des fonctions réseau ou ressources, p. ex. entités SDN ou NFV
H04L 43/0876 - Utilisation du réseau, p. ex. volume de charge ou niveau de congestion
Aspects of the present disclosure relate to recovery of a target database system. The method comprises receiving multiple batches of database transactions to form the target database system. The method further comprises generating a single recovery bookmark before beginning processing of a current batch, wherein the single recover bookmark comprises: an earliest open entry for a previous batch, a latest commit entry for the previous batch, an earliest open entry for the current batch, a latest commit entry for the current batch, a transactional identifier, and list of tables to be processed; performing the sequence of database transactions; replacing the list of tables from the single recovery bookmark with a flag value upon completion; detecting a fault condition during the performance of the sequence of database transactions; recovering the target database system using the single recovery bookmark; and resuming the sequence of database transactions.
G06F 7/00 - Procédés ou dispositions pour le traitement de données en agissant sur l'ordre ou le contenu des données maniées
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 17/00 - Équipement ou méthodes de traitement de données ou de calcul numérique, spécialement adaptés à des fonctions spécifiques
Mechanisms are provided for writing files to tape storage. A set of files to be written to the tape storage are identified and, for each file, metadata associated with the file indicating identifiers of users associated with the file is retrieved. For each file, a predicted frequency metric, specifying a predicted frequency of access of the file, is determined based on the identifiers of users associated with the file specified in the associated metadata. The files are sorted to generate a ranked set of files in which each file is ranked relative to the other files in the set of files based on their corresponding predicted frequency metric. The ranked set of files is written to the tape storage in descending order of predicted frequency metric such that files having relatively larger predicted frequency metrics are written relatively closer to a starting boundary of a partition of the tape storage.
A system is provided which includes a first carriage assembly to support a first cable connector of a cable, and a second carriage assembly to support a second cable connector of the cable. The first carriage assembly and the second carriage assembly move along a guide. Further, the system includes a controller to monitor and adjust position of at least the second carriage assembly to maintain a tension on the cable within a specified range during an automated cabling operation of the system.
H02G 1/14 - Méthodes ou appareils spécialement adaptés à l'installation, entretien, réparation, ou démontage des câbles ou lignes électriques pour la jonction ou la terminaison de câbles
H01R 13/58 - Moyens pour atténuer l'effort de tension sur le câble de connexion, p. ex. serre-câble
29.
CONTROLLING SPECULATIVE ACTIONS BASED ON A HIT/MISS PREDICTOR
Processing within a computing environment is facilitated by using cache hit-miss predictions. A cache hit-miss prediction is determined for a memory access instruction using a predictor. One or more speculative actions are controlled, based on determining the cache hit-miss prediction is a miss. The controlling is further based on a type of cache design.
An embodiment determines a set of object parameters. The embodiment produces an object from a ferrofluidic viscoelastic material according to the object parameters. The embodiment generates a magnetic field to maintain a structure of the object. The embodiment captures physical feedback from a user interacting with the object through detecting a change in the magnetic field. The embodiment adjusts a strength of the magnetic field to continue to maintain the structure of the object. The embodiment receives an input command to cease maintaining the structure of the object. The embodiment adjusts the strength of the magnetic field to deform the object into a fluid.
H01F 7/06 - Électro-aimantsActionneurs comportant des électro-aimants
G05B 15/02 - Systèmes commandés par un calculateur électriques
H01F 1/44 - Aimants ou corps magnétiques, caractérisés par les matériaux magnétiques appropriésEmploi de matériaux spécifiés pour leurs propriétés magnétiques en liquides magnétiques, p. ex. ferrofluides
A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor device includes a multi-stacked transistor structure comprising a first stacked transistor structure and a second stacked transistor structure. The first stacked transistor structure includes a first lower transistor device and a first upper transistor device, and the second stacked transistor structure includes a second lower transistor device, a second upper transistor device, and a third upper transistor device.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
One or more computer processors training a model with historical incidents, wherein each historical incident is associated with group information and system event properties. The one or more computer processors responsive to a new incident, extract group information from one or more users and extracting system event property information from the new incident. The one or more computer processors calculate a notification priority score for each user utilizing the extracted system event property information and the extracted group information. The one or more computer processors generate a notification based on the new incident. The one or more computer processors transmit the generated notification to the one or more users at a determined interval based on the calculated respective notification priority score for each user and a notification strategy.
H04L 51/224 - Surveillance ou traitement des messages en fournissant une notification sur les messages entrants, p. ex. des poussées de notifications des messages reçus
A semiconductor structure includes a semiconductor layer, one or more channel layers disposed over the semiconductor layer, a first dielectric liner surrounding sidewalls of a first region of the semiconductor layer proximate the one or more channel layers, a second dielectric liner surrounding sidewalls of a second region of the semiconductor layer below the first region of the semiconductor layer, and a shallow trench isolation region surrounding the first dielectric liner and the second dielectric liner, where the first dielectric liner and the second dielectric liner are different materials.
A gate-all-around transistor includes a gate structure having sidewalls; a first and a second gate spacer positioned laterally on each sidewall, wherein the gate structure has a gate length between the sidewalls of the gate structure, the gate length having a midpoint; a first inner spacer under the first gate spacer; and a second inner spacer under the second gate spacer. A channel layer extends from below the first inner spacer, across the gate length to below the second inner spacer. The channel layer includes a first region having a first thickness and located below each of the gate spacers; and a second region having a continuously variable thickness, the second region located laterally between the first regions and being symmetrical in reference to the midpoint of the gate length.
H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A method, by an intelligent access control system, of implementing access control to a controlled area having a plurality access areas divided by at least one access point includes the following operations. A security token is generated. The security token is transmitted to a client module executing on a client device associated with a first user, and the client module is caused to pair with an access control device associated with the first user. The client module is caused to transfer the security token to the access control device. A physical location of the client device within the controlled area is monitored. A determination is made, by an access control system and based upon the physical location, that the first user is to be revalidated. The client module causes, based upon the determining, the client device to generate an alert.
G07C 9/28 - Enregistrement de l’entrée ou de la sortie d'une entité isolée comportant l’utilisation d’un laissez-passer le laissez-passer permettant le repérage ou signalant la présence
G07C 9/20 - Enregistrement de l’entrée ou de la sortie d'une entité isolée comportant l’utilisation d’un laissez-passer
G07C 9/21 - Enregistrement de l’entrée ou de la sortie d'une entité isolée comportant l’utilisation d’un laissez-passer muni d’un code d’accès variable
37.
FILE PATH TRACING AND BEHAVIORAL REMEDIATION ON PATH REVISION
Embodiments of the present invention provide computer-implemented methods, computer program product, and computer systems. One or more processors can monitor file revision history of a filesystem. The one or more processors generate a remedial action based on previous user interaction behavior in response to detecting a failed interaction with a file in the filesystem. The one or more processors execute the remedial action that retrieves the file.
An embodiment for optimally organizing and dispatching workloads in systems having multiple processor types. The embodiment may retrieve processor information and historical task data associated with a target system. The embodiment may calculate and map, for tasks performable by the target system during a series of candidate timeslots, average expected processor usage values for a series of different processor types available within the target system. The embodiment may construct, based on the calculated and mapped average expected processor usage values for the tasks performable by the target system, a workload dispatch graph for a candidate workload to be performed by the target system, the workload dispatch graph including dispatch strategies. The embodiment may determine, for the candidate workload, based on the constructed workload dispatch graph, an optimal dispatch strategy having a lowest expected processor cost value.
A computer implemented method, system and product for gradually altering compute resources allocated to workloads in a cloud computing environment is described. A fixed percentage per increment is determined by which to alter a current allocation of at least one of a set of compute resources allocated to at least one of a set of workloads in a cloud computing environment during a selected period of time to incrementally switch the current allocation of the at least one of the set of compute resources allocated to the at least one of the set of workloads in the cloud computing environment from an original allocation to a target allocation. The current allocation is switched incrementally by the fixed percentage per increment the current allocation from the original allocation to the target allocation during the selected period of time.
An embodiment establishes a virtual representation of a network configuration, wherein the virtual representation of the network configuration comprises a plurality of layers corresponding to the network configuration. The embodiment generates a plurality of workloads to simulate with the virtual representation. The embodiment generates a plurality of workload statuses to simulate with the virtual representation. The embodiment simulates the plurality of workloads. The embodiment simulates the plurality of workloads statuses. The embodiment receives simulation results responsive to simulating the plurality of workloads and from simulating the plurality of workload statuses.
H04L 41/0895 - Configuration de réseaux ou d’éléments virtualisés, p. ex. fonction réseau virtualisée ou des éléments du protocole OpenFlow
H04L 41/082 - Réglages de configuration caractérisés par les conditions déclenchant un changement de paramètres la condition étant des mises à jour ou des mises à niveau des fonctionnalités réseau
An approach for assisting in the generation of quantum source code. The approach may include receiving a quantum source code input with a specification of constraints of a quantum unit on which the quantum source code input is to be run, wherein the constraints include available quantum qubits or gates and/or available quantum parameters. The method creates a variation of the quantum source code input by analyzing the quantum source code input against trained models, wherein the variation includes adjustment of the quantum unit constraints depending on the specification of constraints the quantum unit. The method provides a recommendation based on the variation to assist in quantum source code generation.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
Mechanisms are provided for scanning container images for vulnerabilities. With these mechanisms, a container image is received for inclusion in a container image registry and each layer of the container image is scanned to generate file signatures for each file referenced in each layer. Vulnerability signature(s) are applied to each layer, based on the file signatures of the layer, to determine if criteria of the vulnerability rule(s) of the vulnerability signature(s) are satisfied by at least one layer of the container image. Registration of the container image in the container image registry is accepted or denied based on results of the application of the vulnerability signature(s). Each vulnerability signature comprises one or more vulnerability rules generated from a scanning and indexing of layers of one or more other container images.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
A 3D chip stack is provided including a first chip (including core units, cache units and power elements) and a second chip (including core units, cache units and heat spreader elements) that are stacked one on top of the other in a staggered manner and a power via is present that connects one of the power elements of the first chip to one of the core units of the second chip, and a thermal via is present that connects one of the core units of the first chip to one of the heat spreader elements of the second chip.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
44.
THERMAL COMPRESSION BONDING WITH CONTACT AREA ADJUSTMENT
A thermal compression bonding apparatus and assembly are provided in which the contact area between a thermal compression bonding head nozzle and a semiconductor component that is closest to the thermal compression bonding head nozzle has been modified/adjusted to mitigate temperature non-uniformity from the center to the corner of the semiconductor component. This mitigation in temperature non-uniformity improves the uniformity of bonding quality across the semiconductor package.
A release mechanism is provided to connect to a cable connector, with the cable connector being latchable to a connector receptacle. The release mechanism includes a pull release to operatively couple to a latching mechanism of the cable connector to selectively release a latch of the latching mechanism from latching the cable connector to the connector receptacle when operatively coupled to the connector receptacle. The pull release is adapted to, at least in part, break apart in operation in response to a predetermined excess stress event on the pull release to facilitate protecting the cable connector from excessive stress due to the stress event.
H01R 13/633 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz pour la séparation uniquement
According to one embodiment, a method, computer system, and computer program product for language development is provided. The embodiment may include identifying one or more speech goals of a user within input of the user to a conversational chatbot. The embodiment may include forwarding the identified speech goals and the input of the user to a large language model (LLM) utilized by the conversational chatbot. Based on the identified one or more speech goals and the input of the user, the embodiment may include retrieving expert-crafted prompts for use with the LLM. The embodiment may include generating, via the LLM in combination with the retrieved expert-crafted prompts, a response to the user. The response addresses an identified speech goal of the user. The embodiment may include sending, via the conversational chatbot, the response to the user.
G06F 40/40 - Traitement ou traduction du langage naturel
H04L 51/02 - Messagerie d'utilisateur à utilisateur dans des réseaux à commutation de paquets, transmise selon des protocoles de stockage et de retransmission ou en temps réel, p. ex. courriel en utilisant des réactions automatiques ou la délégation par l’utilisateur, p. ex. des réponses automatiques ou des messages générés par un agent conversationnel
Computer-implemented methods for a pipeline query transformation system are disclosed herein. Aspects include validating an input query of business logic in a pipeline query language using a pipeline dialect by a pipeline processor of a pipeline query transformation system. Aspects also include parsing the input query into pipeline operators. Aspects further include processing the pipeline operators using the pipeline dialect by the pipeline processor. Aspects include generating a query context by processing the pipeline operators. Aspects also include generating an SQL query from the query context.
A processor set receives data detected from sensor devices associated with an online conference session. The processor set, based on analyzing the data, determines a contribution score for each of a plurality of participants attending the online conference, which is being conducted via the video stream. The contribution score indicates a participant's level of contribution during the online conference session. The processor set controls performing of an automatic close-up of a camera view in the online conference session to a participant having a highest contribution score among the plurality of participants attending the online conference being conducted via the video stream.
H04N 23/60 - Commande des caméras ou des modules de caméras
G10L 15/18 - Classement ou recherche de la parole utilisant une modélisation du langage naturel
G10L 25/57 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation pour le traitement des signaux vidéo
H04L 12/18 - Dispositions pour la fourniture de services particuliers aux abonnés pour la diffusion ou les conférences
H04N 23/69 - Commande de moyens permettant de modifier l'angle du champ de vision, p. ex. des objectifs de zoom optique ou un zoom électronique
Mechanisms are provided for performing homomorphic cryptographic operations. The mechanisms receive a specification of a homomorphic encryption (HE) operation to be performed on workloads comprising one or more input ciphertexts and generate a circuit of HE computations for performing the HE operation. The circuit comprises authentication tag checking logic at one or more inputs of the circuit, and nullification logic inserted into the circuit. The nullification logic operates to nullify one or more HE encrypted ciphertexts generated by the circuit. The mechanisms process the workloads by the circuit of HE computations to generate one or more output ciphertexts that are results of the HE operation executed on the one or more input ciphertexts, which are returned to a source computing system. The nullification logic masks an input ciphertext of the one or more input ciphertexts which, based on authentication information associated with the input ciphertext, cannot be authenticated.
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
A forksheet transistor includes a tapered channel that has an interfacial surface that is directly connected to an isolation pillar. The tapered channel has a region in which its cross-sectional vertical dimension reduces in thickness toward its end surface that is in direct contact with the isolation pillar. The tapered channel may improve electrostatic control by the gate of the forksheet transistor over the tapered channel, which may improve the functionality and/or efficiency of the forksheet transistor.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
51.
GENERATING ENGAGEMENT SCORES USING MACHINE LEARNING MODELS FOR USERS INTERACTING WITH VIRTUAL OBJECTS
Provided are a computer program product, system, and method for generating engagement scores using machine learning models for users interacting with virtual objects. Movement parameters are received from tracking devices from a user in a real-world while the user is interacting with a virtual object in the extended-reality environment. The movement parameters are processed to determine a first engagement score indicating user interest in the real-world entity represented by the virtual object. A determination is made of on user information access requests with respect to the real-world entity. The information on the user information access requests is inputted to an engagement machine learning model to output a second engagement score indicating user interest in the real-world entity. The first engagement score and the second engagement score are outputted to provide information on an efficacy of the virtual object in promoting interest in the real-world entity.
A flat flexible cable including a first conductive layer with a plurality of traces, a second conductive layer with a second plurality of traces, a first non-conductive layer disposed between the first conductive layer and the second conductive layer, and a second non-conductive layer disposed between the second conductive layer and a conductive ground layer, where the first conductive layer, the second conductive layer, and the conductive ground layer are electrically connected.
H01R 12/59 - Connexions fixes pour circuits imprimés flexibles, câbles plats ou à rubans ou structures similaires
H01R 12/77 - Dispositifs de couplage pour circuits imprimés flexibles, câbles plats ou à rubans ou structures similaires
H01R 12/78 - Dispositifs de couplage pour circuits imprimés flexibles, câbles plats ou à rubans ou structures similaires se raccordant à d'autres circuits imprimés flexibles, à des câbles plats ou à rubans ou à des structures similaires
A computer-implemented method and device to optimize structured rules in data processing. The method includes filtering and selecting one rule from a plurality of rules. An expression of the one rule is vectorized with different dimensions. A cluster model of rules is built from at least some of the plurality of rules having a vector distance that is replaced by a specific vector distance. The building of the cluster model of rules is based on identifying a tree-similarity related distance of some of the plurality of rules from the selected one rule.
A representation of a rock capillary network is obtained and initial and boundary conditions of fluid flow and mineral precipitation process simulations for the rock capillary network are set. One or more instances of a geometry evolution simulation are performed, each geometry evolution simulation comprising obtaining fluid flow vectors for the rock capillary network, identifying one or more hotspots of nucleation in the rock capillary network, starting a mineral precipitation analysis and estimating a mineral accumulation over a given time interval for at least the identified hotspots of nucleation, adjusting a pore geometry to an effect of mineral precipitation for the rock capillary network, and iteratively repeating each of the one or more geometry evolution simulations until corresponding stop criteria are met for each geometry evolution simulation. A resulting rock under analysis property is computed from an aggregate of results of the one or more geometry evolution simulations.
G06F 30/28 - Optimisation, vérification ou simulation de l’objet conçu utilisant la dynamique des fluides, p. ex. les équations de Navier-Stokes ou la dynamique des fluides numérique [DFN]
55.
MULTI-DIRECTIONAL MONITORING AND CONTROL OF CABLE CONNECTOR(S) TO FACILITATE AUTOMATED CABLING
A system is provided which includes a first carriage assembly (630) to support a first cable connector (611) of a cable (610), and a second carriage assembly (640) to support a second cable connector (612) of the cable (610). The first and second carriage assemblies move along a guide (620). Further, the system includes a controller (602) to monitor and adjust position of at least the second carriage assembly (640) to maintain tension on the cable (610) within a specified range during an automated cabling operation of the system.
H01R 43/26 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour engager ou séparer les deux pièces d'un dispositif de couplage
A dynamic delay control is provided operatively coupled to control delay of a signal for a memory array based, in part, on an operating voltage (VDD) of the memory array. The dynamic delay control includes at least one diode limited delay element to dynamically adjust the delay of the signal with a change in the operating voltage to enhance tracking of the signal to performance of a memory cell operation of the memory array as the operating voltage changes.
According to the embodiment of the present invention, a semiconductor device includes a first nanodevice including a plurality of first transistors and a second nanodevice including a plurality of second transistors. The first nanodevice includes a first source/drain contact having a first bulge towards a backside of the first source/drain contact. The second nanodevice is located adjacent to and parallel to the first nanodevice along an x-axis. The first bulge is located between the first nanodevice and the second nanodevice. A backside via extends downwards from a backside of the first nanodevice and the second nanodevice to connect to a backside of the first bulge.
H01L 27/12 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant autre qu'un corps semi-conducteur, p.ex. un corps isolant
58.
PERPENDICULAR SPIN-ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY
A SOT MRAM structure having a perpendicular magnetic free layer magnetization is provided The structure includes a spin conductor charge insulator layer having a horizontal portion and a vertical portion, and a spin conductor layer contacting the horizontal portion of the spin conductor charge insulator layer, and a first sidewall of the vertical portion of the spin conductor charge insulator layer. The structure further includes a MTJ structure having a magnetic free layer in direct physical contact with the spin conductor layer, a MTJ cap, a MRAM electrode-containing hard mask, and an I-shaped SOT channel located on a second sidewall of the vertical portion of the spin conductor charge insulator layer. The structure further includes a dielectric pillar located adjacent to, and in direct contact with, the I-shaped SOT channel.
An approach for governing responses generated by a language learning model (LLM) model. The approach defines a reference set of inputs and output pairs for the LLM wherein the reference set of inputs and output pairs are actual inputs and reference outputs. The approach defines a set of metadata associated with the reference set of input and output pairs and assigns the metadata to each pair of the reference set of inputs and output pairs. The approach also defines a set of evaluation criteria, assigns the evaluation criteria to organizational risk framework and associates the set of metadata to the evaluation criteria.
A cutting tool with an integrated thermoelectric power generation (TEPG) module includes a body and a cutting blade. The cutting tool with the TEPG module further includes the TEPG module disposed in a cavity of the body of the cutting tool. A method for utilizing the cutting tool with the TEPG module includes identifying a cutting operation and monitoring temperature for one or more sensors for the cutting tool with the integrated TEPG module. The method further includes determining a temperature threshold has been reached for at least one sensor from the one or more sensors and activating coolant fluid flow towards the cutting tool with the integrated TEPG module. The method further includes generating, by the TEPG module, power based on a temperature difference from heat generated by the cutting operation and a coolant fluid temperature.
H10N 10/13 - Dispositifs thermoélectriques comportant une jonction de matériaux différents, c.-à-d. dispositifs présentant l'effet Seebeck ou l'effet Peltier fonctionnant exclusivement par les effets Peltier ou Seebeck caractérisés par les moyens d'échange de chaleur à la jonction
B23B 27/10 - Outils de coupe avec une disposition particulière pour le refroidissement
61.
SYSTEM AND METHOD FOR AUTOMATICALLY REDEPLOYING CONTAINERS ON MULTIPLE NODES IN AN INFORMATION TECHNOLOGY INFRASTRUCTURE BASED ON PATCHES
A method for automatically redeploying containers on multiple nodes in an IT infrastructure based on patches includes installing a FixPackID attribute, a Sync Patch command, an Image Specific Patch Relation Directed Graph Producer (ISPRDGP) module and an Image Specific Patch Relation Directed Graph Consumer (ISPRDGC) module into an automated deployment software having an automated deployment software configuration/deployment tool, running the automated deployment software configuration/deployment tool to update the FixPackID attribute into a metadata file of a new layer, update the FixPackID in a manifest item, and push the manifest item and the new layer to a repository and running the automated deployment software configuration/deployment tool to install the FixPackID into a manifest list, identify a FixPackID whose parentID is a target layer, confirm a patch type, implement a CORE for the new layer located within a production environment and install the new patch onto the production environment.
A computer-implemented method according to one approach, is for determining fairness of a workload shifting policy. The CIM includes receiving execution logs from a system implementing the workload shifting policy, and inspecting the execution logs. A model is developed that replicates how the workload shifting policy is applied by the system. Moreover, a desired metric of interest is defined. A probabilistic model checker is used to evaluate the model and the desired metric of interest, and a quantitative measure of the fairness of the workload shifting policy is produced.
A computer-implemented method for retrieving, by a second integration server from a queuing system, a first state message comprising a flow correlation identification (ID). The method further includes initializing, by the second integration server, an integration flow based on the flow correlation ID and processing, by the second integration server, the integration flow as a backup integration server to a first integration server. In response to determining that the first integration server has failed, the method further includes processing, by the second integration server, the integration flow as a primary integration server.
H04L 69/40 - Dispositions, protocoles ou services de réseau indépendants de la charge utile de l'application et non couverts dans un des autres groupes de la présente sous-classe pour se remettre d'une défaillance d'une instance de protocole ou d'une entité, p. ex. protocoles de redondance de service, état de redondance de protocole ou redirection de service de protocole
H04L 47/62 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement
An apparatus for computing a conditional conformal prediction interval for a machine learning point prediction regression model and calibration point predictions forming a distribution of an error around the point prediction regression model in an input space. The apparatus includes a conformal regions circuit configured to compute a quantile regression of the error to compute an approximation of a quantile of the error. The conformal regions circuit is further configured to identify a set of regions in the input space where the distribution within each region in the set of regions is interpretably constant. In one embodiment, the apparatus also includes a conformal prediction circuit configured to compute the conditional conformal prediction interval for the point prediction regression model conditioned on the identified set of regions and the corresponding computed quantile of the error for each region in the set of regions.
A semiconductor structure includes at least one interconnect wiring level between a first device layer and a second device layer, wherein the at least one interconnect wiring level includes a first set of wires that are spaced apart from each other at a first minimum pitch, and a second set of wires that are spaced apart from each other at a second minimum pitch that is different than the first minimum pitch. The first set of wires comprises a first cross-sectional area and the second set of wires comprises a second cross-sectional area that is different than the first cross-sectional area.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
66.
REDUCING THE TIME TO SWITCH BETWEEN THE REDUNDANT CLOCK SIGNALS APPLIED TO A PHASE LOCK LOOP
A circuit for reducing a time to switch between the redundant clock signals applied to a phase lock loop. The circuit includes a phase frequency detector of the phase lock loop that detects a shift in the phase of a reference clock signal relative to the phase of a feedback clock signal. The circuit further includes a coarse tuning mechanism configured to delay the feedback clock signal until the feedback clock signal is aligned with a backup reference clock signal. Furthermore, the circuit includes a fine tuning mechanism configured to align the edge of the feedback clock signal with the edge of the backup reference clock signal, such as by utilizing a series of delay elements to delay the backup reference clock signal at different points in time and selecting the appropriate delayed backup reference clock signal whose edge is aligned with the edge of the feedback clock signal.
H03K 5/14 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de lignes à retard
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
Container migration is provided. A comparison of a second image and a third image is performed to detect data changes made by write input/output operations occurring between a second timestamp and a third timestamp. It is determined whether a set of data changes exists in the third image that occurred between the second timestamp and the third timestamp. In response to determining that the set of data changes does exist in the third image that occurred between the second timestamp and the third timestamp, a copy of the set of data changes is sent to a second host node. The set of data changes are merged into the second host node. The write input/output operations are resumed to the second host node using previously queued write input/output operations and new incoming write input/output operations so that the second host node is processing read input/output operations and the write input/output operations.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
68.
Decentralized Digital Identity Exchange for Fraud Detection
A decentralized digital identity exchange (IDX) is provided. In response to receiving a request for identity verification of a user, the IDX transmits, to a digital wallet associated with the user, a request for current biometric data. The current biometric data is received from the digital wallet and a biometric liveness check is performed. In response to the biometric liveness check succeeding, the IDX generates a verification transaction ID (VTID) and a verifiable credential for the user. The VTID is a unique identifier that comprises a representation of when the identity of the user was verified by the IDX. The verifiable credential and VTID are transmitted to the digital wallet which sends them to a relying party computing system to verify the identity of the user to the relying party computing system.
G06Q 20/40 - Autorisation, p. ex. identification du payeur ou du bénéficiaire, vérification des références du client ou du magasinExamen et approbation des payeurs, p. ex. contrôle des lignes de crédit ou des listes négatives
G06Q 20/36 - Architectures, schémas ou protocoles de paiement caractérisés par l'emploi de dispositifs spécifiques utilisant des portefeuilles électroniques ou coffres-forts électroniques
A semiconductor device includes a gate contact over a first gate channel of two adjacent gate channels, and a first dielectric layer encapsulating a lower portion of a second dielectric layer and covering a first side of the second dielectric layer. The first dielectric layer is extended vertically between two adjacent gate channels, and the gate contact is connected to an upper portion of the first side of the second dielectric layer.
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
Embodiments are related to providing systematic delayering of chips, such as finFET chips, along with performing field failure and material investigation. Techniques include receiving information from a gyroscope unit, a vacuum stage being connected to a sample, the vacuum stage being configured to maintain a position of the sample to a polishing table. Techniques include adjusting the position of the sample based, at least in part, on the information received from the gyroscope unit.
H01L 21/304 - Traitement mécanique, p. ex. meulage, polissage, coupe
H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants
H01L 21/687 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension en utilisant des moyens mécaniques, p. ex. mandrins, pièces de serrage, pinces
Techniques are provided for key server and storage deadlock control. In an embodiment, a method is provided that includes determining a location identifier of a key server. The method further includes determining a first storage identifier based on the location identifier, where the first storage identifier identifies a storage volume that stores cryptographic keys of the key server. The method further includes determining a second storage identifier that identifies a storage device or storage system that stores data at rest encrypted by the cryptographic keys. The method further includes identifying a potential deadlock between the key server and the storage device or storage system based on the first storage identifier and the second storage identifier. The method further includes controlling the key server based on the potential deadlock.
Computer-implemented methods for runtime sharing of multiple neural network models in a computing system are provided. Aspects include receiving a request to store first neural network model (NNM) in the computing system, obtaining parameters of the first NNM, and identifying a base model, from a model database, corresponding to the first NNM. Aspects also include identifying duplicate parameters of the first NNM and the base model and generating a delta file corresponding to non-duplicate parameters of the first NNM and the base model. Aspects further include identifying a physical memory device in the computing system that includes a shared region that includes at least a portion of the base model and loading, in a private region of the physical memory device, the parameters from the delta file.
An approach is provided for managing library dependencies. Requests to publish multiple libraries to a public library repository are received. The requests include specifications of respective sets of one or more dependencies of the libraries and respective validation scripts. A dependency version tree that includes the specifications of the respective sets of one or more dependencies is built. A request to upload a new version of a library to the public library repository is received. A validation component using the dependency version tree and the validation scripts validates a compatibility between the library and one or more libraries dependent upon the library.
A semiconductor device is provided and includes an active region, first, second and third gate regions disposed across the active region, a first source/drain (S/D) epitaxial region interposed between the first and second gate regions, a second S/D epitaxial region interposed between the second and third gate regions, backside metallization, a first backside contact to connect the first S/D epitaxial region to the backside metallization, a second backside contact to connect the second S/D epitaxial region to the backside metallization and backside insulation disposed to isolate the first and second backside contacts from one another.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
75.
GENERATION OF USER-SPECIFIC ELECTRONIC PROMPTS FOR A COMPUTING-BASED PROCESS
An intelligent workflow process is provided to facilitate generating electronic prompt(s) for a user of a computing system to provide customized assistance to the user in carrying out a computing-based process. Generating the prompt(s) includes identifying, by an artificial intelligence agent with reference to user data, the computing-based process initiated by the user, where the user data includes historical data relevant to the computing-based process. In addition, the generating includes determining, by the artificial intelligence agent using a machine learning model and the user data, one or more typical actions of the user relevant to the computing-based process, and producing, based on the one or more typical actions of the user relevant to the computing-based process, the electronic prompt(s) for the user. In addition, the electronic prompt(s) are provided, to the user's computing system to facilitate the customized assistance to the user in carrying out the computing-based process.
G06F 18/2413 - Techniques de classification relatives au modèle de classification, p. ex. approches paramétriques ou non paramétriques basées sur les distances des motifs d'entraînement ou de référence
According to an embodiment of the present invention, a method for detecting allergens using smart tooth and IoT is provided. The method includes obtaining real-time environmental allergen context data, wherein the obtained real-time environmental allergen context data includes visual data and sensor data. Features are extracted from the obtained real-time environmental allergen context data, including at least one detected environmental allergen type, an environmental allergen exposure pathway, and an environmental allergen concentration. A real-time unique allergic reaction risk score is generated for a user based on analysis of a user allergic risk profile and the extracted features from the obtained real-time environmental allergen context data. A real-time warning is generated to the user when the generated unique allergic reaction risk score exceeds a predetermined threshold.
A61B 5/00 - Mesure servant à établir un diagnostic Identification des individus
G16H 50/30 - TIC spécialement adaptées au diagnostic médical, à la simulation médicale ou à l’extraction de données médicalesTIC spécialement adaptées à la détection, au suivi ou à la modélisation d’épidémies ou de pandémies pour le calcul des indices de santéTIC spécialement adaptées au diagnostic médical, à la simulation médicale ou à l’extraction de données médicalesTIC spécialement adaptées à la détection, au suivi ou à la modélisation d’épidémies ou de pandémies pour l’évaluation des risques pour la santé d’une personne
77.
TABLE STRUCTURE RECOGNITION USING OPTIMAL TRANSPORT
A computer-implemented method receives a first table and a second table into a table evaluation system. Each of a plurality of cells of the first table and the second table are converted into a two-dimensional point with a cell weight related to the size of the cell. An edit distance matrix is computed between the cells of the first table and the cells of the second table, where the edit distance matrix being obtained is based on contents of cells. An optimal transport distance matrix is calculated between the cells of the first table and the cells of the second table by using the two-dimensional point and the cell weight for each of the plurality of cells. An output is generated that indicates a correspondence between cells in the first table and cells in the second table by using the edit distance matrix and the optimal transport distance matrix.
G06V 30/412 - Analyse de mise en page de documents structurés avec des lignes imprimées ou des zones de saisie, p. ex. de formulaires ou de tableaux d’entreprise
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
A semiconductor structure including a backside gate connector formed in a backside metal layer of the semiconductor structure. The backside gate connector directly contacts the bottom surface of two or more two gates where only a single gate contact connects one of the two or more gates to a layer of the front side interconnect wiring above the two or more gates. At least one source/drain residing between the two or more gates has a source/drain contact connecting a layer of the front side interconnect wiring. The backside gate connector connecting two or more gates resides below the two or more gates and any source/drains that are between the two or more gates.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
According to an embodiment of the present invention, a pressurized sleeve for routing of linear components is provided. The pressurized sleeve is disposed to at least partially surround a flexible line object. A plurality of pouches is disposed in the robotic cable sleeve. At least two pouches of the plurality of pouches have different predetermined hydrostatic pressures from one another which induce axial movement of at least a portion of the robotic cable sleeve and a corresponding portion of the at least partially surrounded linear component.
F15B 15/10 - Dispositifs actionnés par fluides pour déplacer un organe d'une position à une autreTransmission associée à ces dispositifs caractérisés par la structure de l'ensemble moteur le moteur étant du type à diaphragme
F16L 11/12 - Manches, c.-à-d. tuyaux flexibles en caoutchouc ou en matériaux plastiques flexibles avec agencements pour usages particuliers, p. ex. spécialement profilés, avec couche protectrice, chauffés, conducteurs d'électricité
80.
LINEAR COMPONENT INSTALLATION/UNINSTALLATION USING PRESSURIZED SLEEVE
According to an embodiment of the present invention, a method is provided for pressurized routing linear components. The method includes obtaining data related to a project. Features are extracted from the obtained project data. The extracted features include linear component characteristics and project environment characteristics. A project design is obtained based on at least one of user input and predetermined extracted features from the extracted features from the obtained project data. The project design includes installation or uninstallation of a linear component in relation to an apparatus. Pressurization is calculated of a plurality of pouches disposed in a pressurized sleeve for the installation or uninstallation of the linear component in relation to the apparatus based on the project design. The calculated pressurization of the plurality of pouches disposed in the pressurized sleeve is implemented.
A semiconductor device includes a conductive structure. The conductive structure has a primary conductor including a predominantly crystalline material having anisotropic Fermi velocities. A direction of a higher Fermi velocity of the primary conductor is aligned with a direction of electric current flow within the primary conductor.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
Mechanisms are provided for performing ciphertext nullification operations. The mechanisms receive a ciphertext in nullification logic of a cryptographic circuit, where the cryptographic circuit comprises one or more cryptographic functions to be performed on the ciphertext. The mechanisms determine, by the nullification logic, whether the received ciphertext is to be nullified. In response to the determination indicating that the ciphertext is to be nullified, the mechanisms generate, by the nullification logic, a nullified ciphertext and output the nullified ciphertext. In response to the determination indicating that the ciphertext is not to be nullified, the nullification logic outputs the received ciphertext.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
A computer-implemented method may include: monitoring historical query data comprising a search query and a search result; extracting, by the processor set, a user's real-time context; correlating, via a machine learning module, the user's real-time context to the historical query data; predicting, via the machine learning module, a user preference based on the correlating the user's real-time context to the historical query data; calculating a correlation score for the search result in a list of returned search results based on the user preference; re-ranking the search result in the list of returned search results based on the correlation score; and rendering a re-ranked search result as a second list of search results based on the re-ranking.
A computer-implemented method can determine a linguistic boundary condition for synthetic data generation in a multi-class classification problem. The method includes analyzing empirical labelled data using linguistic and vector representation techniques. The method further includes deriving a synthetic boundary conditional (SBC) model based on the analysis of the empirical labelled data and identifying a boundary location for performant synthetic data generation using the SBC model.
An embodiment computes, using a trained embedding model, a query embedding representing an input query, the input query comprising a request for a recommended model and a recommended prompt template for use with the recommended model. An embodiment selects a set of nearest neighbor embeddings with a distance less than a threshold distance from the query embedding in an embedding space. An embodiment predicts, using a trained confidence predictor model, a confidence value of each model-prompt template pair represented by a nearest neighbor embedding in the set of nearest neighbor embeddings, the predicting resulting in a set of predicted confidence values. An embodiment constructs a response to the input query, the response comprising a model-prompt template pair selected using the predicted confidence values.
Provided are a decoder unit, a decompressor unit, and method for a decoder of multiple stages of adders to decode delta encoded data. A decoder unit implemented in a cache memory having a cache memory cell array comprises a first stage of adder circuits to add, in parallel, pairs of encoded items transformed using a delta encoding, wherein the encoded items include a plurality of deltas of neighbors of sequential source items. The decoder unit further comprises at least one successive stage of adder circuits to add, in parallel in each stage, pairs of outputs from a previous stage of adder circuits, wherein each successive stage has fewer adder circuits than the previous stage, and wherein output from a last of the at least one successive stage comprises the sequential source items.
Mechanisms are provided for recovering a worker node that is in a not ready state. A first worker node of a cluster is configured with a first debug utility that comprises a debug node agent that monitors an operating state of the first worker node. In response to the debug node agent detecting the first worker node being not ready, the debug node agent sends a request to a debug proxy of a second debug utility associated with a second worker node that is in a ready state, to create a debug worker node for the first worker node based on a customer resource definition from a master node, where the debug worker node has a minimum configuration for handling debug commands. The debug commands from a user are processed via the debug worker node to return the first worker node to a ready state.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
A technique of testing recovery paths for potential security vulnerabilities includes a processor executing a code testing service and a program under test. The code testing service forces a recovery path in the program under test, and the program under test causes program checks. The operating system creates notifications regarding the program checks. The processor processes the notifications utilizing a code monitor to detect potential security vulnerabilities in the recovery path of the program under test. The code monitor generates and stores a report of the potential security vulnerabilities in the program under test.
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
90.
IDENTIFICATION OF SYMBOL DRIFT IN WRITTEN DISCOURSE
An embodiment establishes a text corpus database based at least in part on text data received from a written discourse. The embodiment extracts a first set of terms from the text corpus database and a first set of collocations for each term of the first set of terms. The embodiment constructs a summation model based at least in part on the first set of terms and the first set of collocations for each term of the first set of terms. The embodiment inputs additional text data into the summation model to determine a probability score that defines the probability that a term stored on the text corpus database will change meaning. The embodiment displays the probability score on a user interface.
A structure that includes at least one chiplet, a heat spreader located over the at least one chiplet, a laminate located under the at least one chiplet, and at least one pin extending between the heat spreader and the laminate and located near the at least one chiplet. The at least one pin is adapted to dissipate heat from the at least one chiplet.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A semiconductor device includes a first gate structure having a gate metal. A gate contact is connected to the gate metal of the first gate structure. The gate contact is disposed between first source/drain contacts and has a height greater than the first source/drain contacts to overlap the first source drain contacts. A second gate structure has a gate metal. A gate tie-down is connected to the gate metal of the second gate structure and one of a pair of second source/drain contacts. The gate tie-down has a height greater than the pair of second source/drain contacts to overlap the other of the pair of the second source drain contacts.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A computer-implemented process for modifying one or more of a plurality of data pipelines within a computer architecture that processes data from a plurality of datasets includes the following operations. Real-time observability data regarding the plurality of data pipelines and the plurality of datasets is ingested. A dataset from the plurality of datasets is classified based upon usage and reliability to generate a classification of the dataset. Based upon the classification, a recommendation to modify at least one of the plurality of data pipelines or the quality of one of the plurality of datasets is generated.
G06F 16/215 - Amélioration de la qualité des donnéesNettoyage des données, p. ex. déduplication, suppression des entrées non valides ou correction des erreurs typographiques
G06F 16/28 - Bases de données caractérisées par leurs modèles, p. ex. des modèles relationnels ou objet
An embodiment includes detecting by a Detection Component of an Image Monitoring System an image of a subject. The embodiment includes responsive to detecting the image, sharding by a Sharding Component of the Image Monitoring System the image into an image shard based on a key point. The embodiment includes training by a Processor Component of the Image Monitoring System a machine learning model to generate an image score of the image shard based on a parameter and the image shard where the subject is anonymous to the Processor Component. The embodiment also includes determining by a Score Aggregator Component of the Image Monitoring System a monitoring action of the subject based on the image score.
G06V 40/16 - Visages humains, p. ex. parties du visage, croquis ou expressions
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06V 10/82 - Dispositions pour la reconnaissance ou la compréhension d’images ou de vidéos utilisant la reconnaissance de formes ou l’apprentissage automatique utilisant les réseaux neuronaux
A transistor includes a channel that has sidewall that consists of an angular indent that is directly connected to the source/drain region without a channel extension region therebetween. For example, the transistor may be a p-type transistor in which the channel may be composed of silicon germanium (SiGe) and may be directly connected to a p-type source/drain region. Unlike some traditional pFETs, there is not a traditional channel extension region (e.g., a Si channel extension region) between the SiGe channel and the p-type source/drain regions. As such, the resistance between the channel and the source/drain is relatively reduced.
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A computer-implemented method, according to one embodiment, includes causing a first fault injection configuration to be injected into a first node of a first edge site of a cloud environment, where the first edge site includes a plurality of nodes, and the cloud environment includes a second edge site. The method further includes computing a first minimum cost maximum flow value for the first fault injection configuration, and causing a second fault injection configuration to be injected into a second node of the second edge site for causing a second fault injection. A second minimum cost maximum flow value is computed for the second fault injection configuration. In response to a determination that a difference of the minimum cost maximum flow values is less than a predetermined threshold, one of the fault injection configurations is retained and the other fault injection configuration is discarded.
H04L 43/062 - Génération de rapports liés au trafic du réseau
H04L 43/0817 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux en vérifiant la disponibilité en vérifiant le fonctionnement
In an embodiment, a semiconductor structure is provided that includes a stacked structure of a first device level and a second device level. A middle back end of the line (BEOL) level is positioned between the first device level and the second device level. The middle back end of the line (BEOL) level includes a first wiring layer in electrical communication with the first device level and a second wiring layer in electrical communication with the second device level, wherein a second pitch for metal lines in the second wiring layer is greater than a first pitch for metal lines in the first wiring layer. The semiconductor device structure further includes a frontside back end of the line (BEOL) level above the second device level.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A computer-implemented method (CIM), according to one embodiment, includes, tuning a plurality of Large Language Models (LLMs) to debate one another to determine solutions for incidents, and causing data associated with a first incident to be input into the LLMs. The method further includes incorporating solutions output by the LLMs into a recommendation for resolving the first incident. The recommendation weighs trade-offs of different possible resolutions for solving the first incident. The method further includes outputting the recommendation to a user interface of a user device. A computer program product (CPP), according to another embodiment, includes a set of one or more computer-readable storage media, and program instructions, collectively stored in the set of one or more storage media, for causing a processor set to perform the foregoing method.
Provided are techniques for cognitive data repatriation and data removal. An event that triggers review of a file is received. A classification of the file is identified. The classification of the file is used to identify a data review ruleset. A process selected from a group consisting of repatriation of data in the file and removal of the data in the file is performed based on the event and the data review ruleset.
An exemplary hybrid bonded semiconductor structure includes a lower semiconductor build, an upper semiconductor build on the lower semiconductor build, a joining interface where the lower and upper semiconductor builds meet, a first e-fuse terminal at least partially in the lower semiconductor build, a second e-fuse terminal at least partially in the upper semiconductor build, and an e-fuse link between the first and second e-fuse terminals wherein the e-fuse link comprises a lower portion in the lower semiconductor build and an upper portion in the upper semiconductor build and the e-fuse link extends across the joining interface.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
