Advantest Corporation

Japon

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Type PI
        Brevet 1 825
        Marque 28
Juridiction
        États-Unis 957
        International 892
        Europe 2
        Canada 2
Propriétaire / Filiale
[Owner] Advantest Corporation 1 829
Advantest America, Inc 20
w2bi, Inc. 4
Date
Nouveautés (dernières 4 semaines) 10
2025 juillet (MACJ) 3
2025 juin 10
2025 mai 8
2025 avril 4
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Classe IPC
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux 549
G01R 31/26 - Test de dispositifs individuels à semi-conducteurs 212
G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie 178
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement 107
G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes 66
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Classe NICE
09 - Appareils et instruments scientifiques et électriques 25
42 - Services scientifiques, technologiques et industriels, recherche et conception 9
07 - Machines et machines-outils 4
37 - Services de construction; extraction minière; installation et réparation 3
41 - Éducation, divertissements, activités sportives et culturelles 2
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Statut
En Instance 131
Enregistré / En vigueur 1 722
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1.

ANTENNA DEVICE FOR OTA DEVICE TESTING USING AUTOMATED TEST EQUIPMENT

      
Numéro d'application 19092008
Statut En instance
Date de dépôt 2025-03-27
Date de la première publication 2025-07-10
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Moreira, José
  • Churkin, Sergey
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Artemenko, Alexey

Abrégé

Embodiments of the present invention provide a novel antenna device for OTA testing and measurement using an antenna disposed in a socket of automatic test equipment (ATE) that provides high bandwidth for devices testing and measurement. The antenna device can include a printed circuit board (PCB) including an opening with at least two probes disposed on or in the printed circuit board orthogonally to each other and a cavity between a portion of the PCB carrying the probes and a waveguide backshort. The cavity forms a dual-polarized waveguide between the portion of the PCB carrying the probes and the waveguide backshort, which is typically a reflective termination placed at the end of the waveguide. According to some embodiments, the cavity has a depth of a quarter wavelength, λ/4, plus an integer multiple of a half wavelength, within a tolerance of +/− 1/16 of the wavelength.

Classes IPC  ?

  • G01R 29/08 - Mesure des caractéristiques du champ électromagnétique
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

2.

SOCKET ASSEMBLY AND ELECTRONIC COMPONENT TEST APPARATUS

      
Numéro d'application 18850431
Statut En instance
Date de dépôt 2022-03-24
Date de la première publication 2025-07-03
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Shiota, Natsuki
  • Kato, Yasuyuki
  • Moreira, Jose

Abrégé

A socket assembly used in an electronic component test apparatus for testing a device under test (DUT) having a first device antenna, includes a socket in which the DUT is mounted, a pressing portion, disposed between an antenna unit and the socket, that presses the DUT toward the socket, the antenna unit having a first measuring antenna opposed to the socket, and a reinforcement frame on which the pressing portion is stacked. A material in the pressing portion has a lower dielectric constant than a material in the reinforcement frame.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
  • G01R 29/10 - Diagrammes de rayonnement d'antennes

3.

SEMICONDUCTOR DEVICE HANDLING APPARATUS AND SEMICONDUCTOR DEVICE TESTING APPARATUS

      
Numéro d'application 19004834
Statut En instance
Date de dépôt 2024-12-30
Date de la première publication 2025-07-03
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Kikuchi, Aritomo

Abrégé

A semiconductor device handling apparatus handles a device under test (DUT) to bring a terminal disposed on a first surface of the DUT into contact with a contact portion of a tester comprising a tester transmitter. The semiconductor device handling apparatus includes a holder that holds a second surface of the DUT. The holder includes a holder transmitter that transmits a signal between an optical connection portion disposed on the second surface of the DUT and the tester transmitter. The holder transmitter inputs and outputs an optical signal to and from the optical connection portion.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • H04B 17/10 - SurveillanceTests d’émetteurs

4.

PUSHER FOR USE IN AN AUTOMATED TEST EQUIPMENT, A TEST ARRANGEMENT COMPRISING THE PUSHER AND A METHOD FOR MECHANICALLY PUSHING THE DEVICE UNDER TEST WITH AN ANTENNA INTO A DEVICE UNDER TEST SOCKET

      
Numéro d'application 19078442
Statut En instance
Date de dépôt 2025-03-13
Date de la première publication 2025-06-26
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Hesselbarth, Jan
  • Moreira, José

Abrégé

An embodiment according to the invention comprises a pusher for use in an automated test equipment to mechanically push a device under test, DUT, comprising an antenna or an antenna array into a DUT socket. The pusher comprise relatively higher permittivity dielectric regions and relatively lower permittivity dielectric regions. The relatively higher permittivity dielectric regions and the relatively lower permittivity dielectric regions are forming a structure of higher permittivity dielectric predominantly parallel columns, e.g., rods or pillars or poles, with lower permittivity dielectric regions between these columns. Alternatively, the relatively higher permittivity dielectric regions and the relatively lower permittivity dielectric regions are forming a structure of a higher permittivity dielectric block with lower permittivity dielectric predominantly parallel filled or unfilled holes. The higher permittivity dielectric columns or the lower permittivity dielectric holes extend in a first direction, which is within ±45° of a pushing direction.

Classes IPC  ?

  • G01R 29/08 - Mesure des caractéristiques du champ électromagnétique

5.

PUSHER FOR USE IN AN AUTOMATED TEST EQUIPMENT, A TEST ARRANGEMENT COMPRISING THE PUSHER AND A METHOD FOR MECHANICALLY PUSHING THE DEVICE UNDER TEST WITH A SINGLE-LINEARLY POLARIZED ANTENNA INTO A DEVICE UNDER TEST SOCKET

      
Numéro d'application 19078433
Statut En instance
Date de dépôt 2025-03-13
Date de la première publication 2025-06-26
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Hesselbarth, Jan
  • Moreira, José

Abrégé

An embodiment according to the invention has a pusher for use in an automated test equipment (ATE) to mechanically push a device under test having an antenna or an antenna array into a DUT socket. The pusher has a structure, in which there are alternating parallel layers of relatively higher dielectric permittivity and relatively lower dielectric permittivity. The layers of higher dielectric permittivity and lower dielectric permittivity extend in a first direction, which is within ±45° of a pushing direction.

Classes IPC  ?

  • G01R 29/08 - Mesure des caractéristiques du champ électromagnétique

6.

APPARATUS, METHOD, AND PROGRAM

      
Numéro d'application JP2024036108
Numéro de publication 2025/126642
Statut Délivré - en vigueur
Date de dépôt 2024-10-09
Date de publication 2025-06-19
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sugawara Toshihiro
  • Osumi Taro
  • Asami Koji

Abrégé

This apparatus comprises an acquiring unit that acquires a response waveform output from a device in response to an input signal, and an identifying unit that identifies parameters of an exponential function that approximates the response waveform, wherein: the identifying unit identifies the parameters of the exponential function by means of parameters calculated by linearly approximating a relationship between the logarithm of the signal value of the response waveform and time; and the identifying unit calculates parameters a and b by fitting the logarithm Log (f) of the signal value f of the response waveform and time t by means of the least squares method using the relational expression Log (f)=a-bt, and identifies a parameter A and a parameter T of the exponential function f=A·exp(-t/T) as A=EXP(a) and T=1/b.

Classes IPC  ?

  • G01R 31/26 - Test de dispositifs individuels à semi-conducteurs

7.

POWER SUPPLY FILTER CIRCUIT, POWER SUPPLY ARRANGEMENT, AUTOMATED TEST EQUIPMENT AND METHOD FOR ACTIVELY FILTERING A SUPPLY VOLTAGE

      
Numéro d'application EP2023085761
Numéro de publication 2025/124716
Statut Délivré - en vigueur
Date de dépôt 2023-12-14
Date de publication 2025-06-19
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Späth, Florian

Abrégé

55 Power Supply Filter Circuit, Power Supply Arrangement, Automated Test Equipment and Method for Actively Filtering a Supply Voltage Abstract 5 A power supply filter circuit (100), comprises a transistor (120), a control capacitor (130) and a stabilization capacitor (140). A load path of the transistor is coupled between an input (110) of the power supply filter circuit and an output (112) of the power supply filter circuit. The control capacitor is coupled between a control terminal of the transistor and a reference potential conductor (GND). The stabilization capacitor is coupled between a source terminal 10 of the transistor and the reference potential conductor. The power supply filter circuit is configured to regulate a voltage across the load path of the transistor or a voltage between an input of the power supply filter circuit and an output of the power supply filter circuit. A Power Supply Arrangement, an Automated Test Equipment and Method for Actively Filtering a Supply Voltage are also described. 15 Figure 1

Classes IPC  ?

  • G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
  • H02M 1/00 - Détails d'appareils pour transformation
  • H03H 11/12 - Réseaux sélectifs en fréquence à deux accès utilisant des amplificateurs avec contre-réaction
  • H02M 1/15 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu utilisant des éléments actifs

8.

AMPLIFIER ARRANGEMENT AND METHOD FOR AMPLIFIER ARRANGEMENT WITH SET CURRENT AT CONTROL INPUT OF THE AMPLIFIER ARRANGEMENT IN DEPENDENCE ON AN OUTPUT CURRENT OF THE AMPLIFIER ARRANGEMENT

      
Numéro d'application 19070732
Statut En instance
Date de dépôt 2025-03-05
Date de la première publication 2025-06-19
Propriétaire Advantest Corporation (Japon)
Inventeur(s) Bauer, Rudi

Abrégé

Embodiments according to the invention comprise an amplifier arrangement the amplifier arrangement including an amplifier, wherein the amplifier is configured to be controlled by a voltage at a control input of the amplifier arrangement and a current adjustment circuit, wherein the current adjustment circuit is configured to set, a current at the control input of the amplifier arrangement in dependence on, an output current of the amplifier arrangement.

Classes IPC  ?

  • H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
  • H03F 1/52 - Circuits pour la protection de ces amplificateurs

9.

TESTING DEVICE, TESTING METHOD, AND PROGRAM

      
Numéro d'application JP2024036639
Numéro de publication 2025/120999
Statut Délivré - en vigueur
Date de dépôt 2024-10-15
Date de publication 2025-06-12
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Kawabata Masayuki
  • Nagatomo Hisao
  • Saiki Masahiro

Abrégé

Provided is a testing device comprising a voltage generating unit that generates an offset voltage, a control unit that controls the offset voltage and the timing at which the offset voltage is changed, a signal amplifying unit that amplifies the difference between an analog input signal input from a device under test and the offset voltage controlled by the control unit and outputs an analog amplified signal, a measuring unit that measures the analog amplified signal, and a restoring unit that uses the voltage value of the offset voltage to restore the voltage value of the analog input signal from the voltage value measured by the measuring unit, wherein the voltage generating unit changes the offset voltage such that an expected voltage value of the analog input signal is included in a measurement window of a predetermined voltage range.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G06F 3/05 - Entrée numérique utilisant l'échantillonnage d'une quantité analogique à intervalles réguliers de temps

10.

TEST APPARATUS AND TEST METHOD

      
Numéro d'application JP2024037707
Numéro de publication 2025/121020
Statut Délivré - en vigueur
Date de dépôt 2024-10-23
Date de publication 2025-06-12
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Chiba Noriaki
  • Kambayashi Hironori

Abrégé

Provided is a test apparatus comprising an input unit that is connected to a device under test and receives a signal to be tested from the device under test, and a function test unit that tests a function of the device under test on the basis of the signal to be tested, the function test unit having a timing measurement unit that measures the timing of an edge of the input signal, the input unit having a current measurement unit that outputs a current measurement signal corresponding to the current value of the signal to be tested, and a first input switching unit that switches whether or not to input the current measurement signal to the function test unit, and the timing measurement unit measuring the pulse width of the current measurement signal on the basis of the timing of the edge of the current measurement signal that is input to the function test unit.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 31/316 - Test de circuits analogiques

11.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING A FITTING APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Numéro d'application 19050905
Statut En instance
Date de dépôt 2025-02-11
Date de la première publication 2025-06-05
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Chejanovsky, Natan
  • Yoshino, Takatoshi
  • Chen, Tse-Kun

Abrégé

An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks using a fitting approach. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

12.

CONTACT TERMINAL, TERMINAL ASSEMBLY, AND DEVICE TESTING APPARATUS

      
Numéro d'application 18914788
Statut En instance
Date de dépôt 2024-10-14
Date de la première publication 2025-06-05
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Saeki, Wataru
  • Abe, Yoshihiro

Abrégé

A contact terminal includes one or more contact parts that contact a conductive member, a pressing member that presses the one or more contact parts relative to the conductive member, and an electrical connection member, independent from the pressing member, including one or more conductive paths connected to the one or more contact parts.

Classes IPC  ?

  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes

13.

AUTOMATED TEST EQUIPMENT, METHOD FOR TESTING A DEVICE UNDER TEST AND COMPUTER PROGRAM USING AN ITERATIVE APPROACH TO OBTAIN TEMPERATURE CONTROL INSTRUCTIONS

      
Numéro d'application 19050915
Statut En instance
Date de dépôt 2025-02-11
Date de la première publication 2025-06-05
Propriétaire Advantest Corporation (Japon)
Inventeur(s) Chejanovsky, Natan

Abrégé

An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks. An automated test equipment, ATE, for testing a device under test, DUT, is configured to obtain a testing profile indicating an evolution of a DUT temperature during an execution of a given test flow. The automated test equipment is configured to analyze the testing profile, in order determine an information describing a plurality of temperature peaks. The automated test equipment is configured to obtain a plurality of temperature control instructions for an execution of a test flow on the basis of the information describing the plurality of temperature peaks. Moreover, the automated test equipment is configured to iteratively obtain the temperature control instructions.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

14.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST IN A DEVICE-UNDER-TEST SOCKET

      
Numéro d'application 19038974
Statut En instance
Date de dépôt 2025-01-28
Date de la première publication 2025-05-29
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abrégé

A test arrangement for over-the-air testing an angled device under test is described, wherein the test arrangement has a carrier structure, wherein the test arrangement has a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test.

Classes IPC  ?

  • G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
  • G01R 29/10 - Diagrammes de rayonnement d'antennes
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

15.

OPTICAL WAVEGUIDE AND MANUFACTURING METHOD OF OPTICAL WAVEGUIDE

      
Numéro d'application 19040870
Statut En instance
Date de dépôt 2025-01-30
Date de la première publication 2025-05-29
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • National Institute of Information and Communications Technology (Japon)
Inventeur(s)
  • Seki, Atsushi
  • Otomo, Akira
  • Tominari, Yukihiro

Abrégé

Provided is an optical waveguide, comprising: an optical propagation path containing an organic electro-optic polymer material; and a stacked structure covering at least a portion of the optical propagation path, having a first layer to prevent oxygen from permeating into the optical propagation path from outside, and a second layer to prevent moisture from permeating into the first layer from the outside. The first layer may contain Al2O3, and the second layer may contain SiO2. The stacked structure may have a three-layer structure consisting of the second layer, the first layer, and a third layer that prevents moisture permeation from the optical propagation path to the first layer, stacked in sequence.

Classes IPC  ?

  • G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
  • G02F 1/00 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire

16.

DEVICE HANDLING APPARATUS AND DEVICE TESTING APPARATUS

      
Numéro d'application 18963384
Statut En instance
Date de dépôt 2024-11-27
Date de la première publication 2025-05-29
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Kikuchi, Aritomo

Abrégé

A device handling apparatus that handles a device under test (DUT), the DUT including a main body portion including a die, an optical fiber having one end connected to the main body portion, and a connector connected to the other end of the optical fiber, the device handling apparatus includes a holding head that holds the DUT while the optical fiber is separated from the holding head and a moving device that moves the holding head. The holding head includes a first holding portion that holds the main body portion and a second holding portion that holds the connector.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes

17.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST USING A CARRIER STRUCTURE WITH AN OPENING

      
Numéro d'application 19038983
Statut En instance
Date de dépôt 2025-01-28
Date de la première publication 2025-05-29
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abrégé

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure and a device-under-test socket which is coupled to the carrier structure. The device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The carrier structure comprises an opening extending away from the device-under-test socket in a direction of an outward surface normal of a first outer surface of the angled device-under-test.

Classes IPC  ?

  • G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes
  • G01R 29/10 - Diagrammes de rayonnement d'antennes
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

18.

TEST ARRANGEMENT FOR OVER-THE-AIR TESTING AN ANGLED DEVICE UNDER TEST THAT IS TILTED RELATIVE TO A SURFACE OF A CARRIER STRUCTURE

      
Numéro d'application 19038992
Statut En instance
Date de dépôt 2025-01-28
Date de la première publication 2025-05-29
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Moreira, José
  • Takasu, Hiromitsu
  • Shiota, Natsuki
  • Kikuchi, Aritomo
  • Kato, Yasuyuki
  • Mineo, Hiroyuki

Abrégé

The invention relates to a test arrangement for over-the-air testing an angled device under test, wherein the test arrangement comprises a carrier structure. The test arrangement comprises a device-under-test socket which is coupled to the carrier structure, wherein the device-under-test socket is configured to establish an electrical contact with an inner surface of the angled device under test or with a connector which is arranged on the inner surface of the angled device under test. The device-under-test socket is configured to position the angled device-under-test such that a first outer surface of the angled device-under-test is tilted by at least 15 degrees with respect to a surface of the carrier structure.

Classes IPC  ?

  • G01R 29/10 - Diagrammes de rayonnement d'antennes
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • H04B 17/29 - Tests de performance

19.

OPTICAL CONNECTOR

      
Numéro d'application 18898950
Statut En instance
Date de dépôt 2024-09-27
Date de la première publication 2025-05-22
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Hara, Hideo
  • Suzuki, Kengo

Abrégé

An optical connector includes one ferrule and a ferrule position retaining portion. The ferrule position retaining portion holds the one ferrule at a predetermined position. The predetermined position is a position of the one ferrule at which the one ferrule is connected with an other ferrule. The ferrule position retaining portion is arranged to hold the one ferrule such that the one ferrule is movable before and after the one ferrule is connected with the other ferrule.

Classes IPC  ?

  • G02B 6/38 - Moyens de couplage mécaniques ayant des moyens d'assemblage fibre à fibre

20.

COOLING PLATE, WIRING BOARD ASSEMBLY AND DEVICE TESTING APPARATUS

      
Numéro d'application 18949857
Statut En instance
Date de dépôt 2024-11-15
Date de la première publication 2025-05-22
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Yoda, Yasufumi
  • Yasuno, Hidehiko
  • Sugai, Katsushi
  • Doi, Atsuyuki

Abrégé

A cooling plate cools an electronic component for testing mounted on a wiring board used for testing a device under test (DUT), and includes: a first plate having a main surface having a first groove that forms a flow path through which a cooling liquid passes; a second plate disposed on the main surface of the first plate; and an adhesive part that bonds the first plate and the second plate.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

21.

TESTING DEVICE, TESTING METHOD, AND COMPUTER PROGRAM PRODUCT

      
Numéro d'application JP2024037032
Numéro de publication 2025/089175
Statut Délivré - en vigueur
Date de dépôt 2024-10-17
Date de publication 2025-05-01
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Kusaka Takashi

Abrégé

The present invention provides a testing device for detecting the optical power of individual wavelengths of input light including n (n is a natural number) mutually different wavelengths emitted from a device under test, the testing device comprising: a propagation unit capable of switching between n or more mutually different propagation wavelength characteristics with respect to the input light and propagating input light including n wavelengths from the device under test according to n propagation wavelength characteristics; an optical power detection unit for detecting the optical power of n beams of propagated light propagated from the propagation unit according to the n propagation wavelength characteristics; and an optical power computation unit for calculating the optical power for each of the n wavelengths included in the input light, from the optical power of the n beams of propagated light detected by the optical power detection unit, on the basis of the n propagation wavelength characteristics.

Classes IPC  ?

  • G01M 11/00 - Test des appareils optiquesTest des structures ou des ouvrages par des méthodes optiques, non prévu ailleurs

22.

PATTERN-GENERATING DEVICE

      
Numéro d'application JP2023037487
Numéro de publication 2025/083771
Statut Délivré - en vigueur
Date de dépôt 2023-10-17
Date de publication 2025-04-24
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Akita Tokunori
  • Kawakami Takeshi
  • Fujiwara Masaki

Abrégé

Provided is a pattern-generating device comprising a timing generation unit for generating a clock signal, a data generation unit for generating multi-bit data used for generating a multi-value signal having three or more levels, and a control unit for controlling generation of data by the data generation unit. The control unit outputs a trigger signal for triggering generation of data by the data generation unit on the basis of the clock signal. The data generation unit outputs the multi-bit data to at least one edge among a rising edge and a falling edge of the clock signal in accordance with the trigger signal.

Classes IPC  ?

  • G11C 29/56 - Équipements externes pour test de mémoires statiques, p. ex. équipement de test automatique [ATE]Interfaces correspondantes
  • G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier

23.

SiConic

      
Numéro d'application 1850284
Statut Enregistrée
Date de dépôt 2025-02-26
Date d'enregistrement 2025-02-26
Propriétaire ADVANTEST CORPORATION (Japon)
Classes de Nice  ? 09 - Appareils et instruments scientifiques et électriques

Produits et services

Semiconductor testing machines; computer software for semiconductor testing machines.

24.

SYSTEM AND METHOD FOR TESTING DEVICES, COMPUTER READABLE MEDIUM

      
Numéro d'application EP2023077780
Numéro de publication 2025/073382
Statut Délivré - en vigueur
Date de dépôt 2023-10-06
Date de publication 2025-04-10
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Rottacker, Markus
  • Mohr, Joerg-Walter
  • Mueller, Detlef
  • Rohmann, Peter
  • Monda, Peter
  • Matuszczak, Dirk

Abrégé

The present invention relates to a system and method for testing devices. Moreover, the present invention relates to a corresponding computer readable medium. In particular, the present invention discloses a system for testing devices, the system comprising: a DUT-interface (10) comprising a plurality of DUT-ports (1,…,8); a distribution matrix unit (20) having an input side configured to be connected to the plurality of DUT-ports (1,…,8) and an output side configured to be connected to one or more measurement units (M1, M2); and a test processor (30). The test processor (30) is configured to: receive test setting data; control the distribution matrix unit (20) such that, according to the test setting data, at least one of the plurality of DUT-ports (1,…,8) is connected to at least one of the measurement units (M1, M2); and control one or more of the measurement units (M1, M2) to perform a respective measurement.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

25.

TEST DEVICE, TEST METHOD, AND PROGRAM

      
Numéro d'application JP2023034643
Numéro de publication 2025/069125
Statut Délivré - en vigueur
Date de dépôt 2023-09-25
Date de publication 2025-04-03
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Akita Tokunori
  • Kawakami Takeshi
  • Fujiwara Masaki

Abrégé

Provided is a test device comprising: a pattern generation unit that generates a protocol pattern that is for testing a device to be tested, and that has a plurality of cycles which each include a predetermined number of designated patterns; and a sequence control unit that controls the pattern generation unit in accordance with a first command having a plurality of steps and a second command having a plurality of steps. The pattern generation unit generates the protocol pattern such that at least one of the plurality of cycles includes a signal pattern corresponding to at least one of the steps of the first command and a signal pattern corresponding to at least one of the steps of the second command.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

26.

SIGNAL SOURCE SPECIFYING APPARATUS, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Numéro d'application 18710798
Statut En instance
Date de dépôt 2022-09-21
Date de la première publication 2025-03-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Yanagida, Tomonori
  • Ogata, Yuji

Abrégé

A signal source specifying apparatus receives measurement results from a plurality of sensors that receive, from a plurality of signal sources, signals represented by vectors each having a predetermined direction and measure triaxial components orthogonal to each other to specify positions of the signal sources and the vectors. The signal source specifying apparatus includes a relational matrix recording section, and a position/vector deriving section. The relational matrix recording section records a relational matrix representing a relationship between the measurement results summarized per axis by a number of the sensors and the vectors. The position/vector deriving section derives the positions of the signal sources and the vectors that offer a minimum cost function based on the measurement results and the relational matrix. The positions of the signal sources and the vectors are specified based on a result of derivation by the position/vector deriving section.

Classes IPC  ?

  • G01R 33/00 - Dispositions ou appareils pour la mesure des grandeurs magnétiques

27.

APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM

      
Numéro d'application 18971433
Statut En instance
Date de dépôt 2024-12-06
Date de la première publication 2025-03-20
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Braun, Michael
  • Welch, Klaus
  • Hensel, Frank
  • Müller, Nico
  • Gerlach, Arndt
  • Knoch, Ulrich

Abrégé

A test apparatus for testing a device under test, is configured to receive a pattern from the device under test, which comprises information from a plurality of functional blocks of the device under test. The test apparatus is configured to separate errors within the received pattern associated with different functional blocks of the device under test during an execution of a test program, or the test apparatus is configured to separate errors within the received pattern associated with different blocks of one or more bits during an execution of a test program. A method and a computer program are also described.

Classes IPC  ?

  • G01R 31/3177 - Tests de fonctionnement logique, p. ex. au moyen d'analyseurs logiques

28.

TESTING APPARATUS

      
Numéro d'application 18770898
Statut En instance
Date de dépôt 2024-07-12
Date de la première publication 2025-03-13
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Watanabe, Daisuke

Abrégé

A testing apparatus includes a driver and a test signal providing section. The driver is connected electrically to a device under test and arranged to provide a test signal to the device under test. The test signal providing section is arranged to provide the test signal to the driver. The driver is closer than the test signal providing section to the device under test. A bandwidth of communication between the driver and the test signal providing section is broader than a bandwidth of communication between the driver and the device under test.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 31/308 - Test sans contact utilisant des rayonnements électromagnétiques non ionisants, p. ex. des rayonnements optiques

29.

SECRETION COMPONENT MEASURING DEVICE

      
Numéro d'application JP2024015440
Numéro de publication 2025/052710
Statut Délivré - en vigueur
Date de dépôt 2024-04-18
Date de publication 2025-03-13
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • MEIJI UNIVERSITY (Japon)
Inventeur(s)
  • Nakamura Kiyoto
  • Kudo Hiroyuki

Abrégé

This secretion component measuring device comprises a first flow passage, a measuring instrument, and a second flow passage. The first flow passage is disposed on the skin, and liquid flowing in from a first flow inlet flows toward a first flow outlet together with secretions from the skin. The measuring instrument measures a component within the secretions. In the second flow passage, the liquid flows from a second flow inlet connected to the first flow outlet toward a second flow outlet. A portion of the measuring instrument is disposed inside the second flow passage. The second flow inlet is disposed directly above the first flow outlet.

Classes IPC  ?

  • G01N 1/00 - ÉchantillonnagePréparation des éprouvettes pour la recherche
  • G01N 27/327 - Électrodes biochimiques
  • G01N 27/416 - Systèmes
  • G01N 33/50 - Analyse chimique de matériau biologique, p. ex. de sang ou d'urineTest par des méthodes faisant intervenir la formation de liaisons biospécifiques par ligandsTest immunologique
  • G01N 37/00 - Détails non couverts par les autres groupes de la présente sous-classe

30.

ELECTROMAGNETIC WAVE MEASURING APPARATUS, METHOD, AND RECORDING MEDIUM

      
Numéro d'application 18673739
Statut En instance
Date de dépôt 2024-05-24
Date de la première publication 2025-03-06
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sakurai, Takao
  • Takahashi, Nobutaka
  • Kikuchi, Yoshinori

Abrégé

An electromagnetic wave measuring apparatus irradiates an irradiation target having a measuring target with a pre-irradiation electromagnetic wave and, based on a post-irradiation electromagnetic wave obtained, measures the measuring target. The post-irradiation electromagnetic wave has a response component from the measuring target and a background component corresponding to the pre-irradiation electromagnetic wave. The electromagnetic wave measuring apparatus includes a first frequency spectrum acquiring section, a second frequency spectrum acquiring section, and a subtracting section. The first frequency spectrum acquiring section acquires a frequency spectrum of a first signal that includes the background component and the response component of the post-irradiation electromagnetic wave. The second frequency spectrum acquiring section acquires a frequency spectrum of a second signal that includes the background component of the post-irradiation electromagnetic wave. The subtracting section subtracts the frequency spectrum of the second signal from the frequency spectrum of the first signal.

Classes IPC  ?

  • G01N 21/3586 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge en utilisant la lumière de l'infrarouge lointainCouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge en utilisant un rayonnement térahertz par spectroscopie térahertz dans le domaine temporel [THz-TDS]
  • G01N 21/3504 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge pour l'analyse des gaz, p. ex. analyse de mélanges de gaz
  • G01N 22/00 - Recherche ou analyse des matériaux par l'utilisation de micro-ondes ou d'ondes radio, c.-à-d. d'ondes électromagnétiques d'une longueur d'onde d'un millimètre ou plus

31.

COAXIAL CABLE AND SEMICONDUCTOR DEVICE TESTING APPARATUS

      
Numéro d'application 18751658
Statut En instance
Date de dépôt 2024-06-24
Date de la première publication 2025-03-06
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Saeki, Wataru

Abrégé

A coaxial cable includes an inner conductor including a central part and a conductive layer surrounding the central part, an insulator surrounding the inner conductor, and an outer conductor surrounding the insulator. The central part includes either a cavity or a portion made of resin material.

Classes IPC  ?

  • H01B 11/18 - Câbles coaxiauxCâbles analogues ayant plusieurs conducteurs intérieurs dans un conducteur extérieur commun

32.

SEMICONDUCTOR DEVICE HANDLING APPARATUS AND SEMICONDUCTOR DEVICE TESTING APPARATUS

      
Numéro d'application 18776540
Statut En instance
Date de dépôt 2024-07-18
Date de la première publication 2025-03-06
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Kikuchi, Aritomo
  • Hara, Hideo

Abrégé

A semiconductor device handling apparatus that moves a device under test (DUT) so that a terminal on a first surface of the DUT contacts a contact part of a semiconductor device testing apparatus, the semiconductor device handling apparatus includes a holding part that holds a second surface of the DUT and an optical probe that inputs and outputs an optical signal to and from an optical connection part on the second surface of the DUT.

Classes IPC  ?

  • G01R 31/311 - Test sans contact utilisant des rayonnements électromagnétiques non ionisants, p. ex. des rayonnements optiques de circuits intégrés
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

33.

SEMICONDUCTOR WAFER HANDLING APPARATUS AND SEMICONDUCTOR WAFER TESTING SYSTEM

      
Numéro d'application 18816814
Statut En instance
Date de dépôt 2024-08-27
Date de la première publication 2025-03-06
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Kikuchi, Aritomo
  • Kiyokawa, Toshiyuki

Abrégé

A semiconductor wafer handling apparatus that moves a semiconductor wafer including a device under test (DUT) and presses a terminal of the DUT against a contactor of a probe card, the semiconductor wafer handling apparatus includes an optical probe that inputs and outputs an optical signal to and from an optical connection part of the DUT. The terminal is disposed on a first surface of the semiconductor wafer. The optical connection part is disposed on a second surface of the semiconductor wafer.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 1/073 - Sondes multiples

34.

SEMICONDUCTOR WAFER HANDLING APPARATUS AND SEMICONDUCTOR WAFER TESTING SYSTEM

      
Numéro d'application 18817872
Statut En instance
Date de dépôt 2024-08-28
Date de la première publication 2025-03-06
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Kikuchi, Aritomo
  • Kiyokawa, Toshiyuki

Abrégé

A semiconductor wafer handling apparatus moves a semiconductor wafer including a first surface on which a terminal of one or more device under tests (DUTs) is disposed and presses the terminal against a contactor of a probe card. The semiconductor wafer handling apparatus includes: a holder that holds the semiconductor wafer such that the first surface and a second surface of the semiconductor wafer are at least partially exposed; a first moving device that relatively moves the holder with respect to the probe card; a temperature adjusting device that contacts the second surface of the semiconductor wafer and adjusts a temperature of the DUTs; and a second moving device that relatively moves the temperature adjusting device with respect to the semiconductor wafer held by the holder.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

35.

AUTOMATED TEST EQUIPMENT AND METHOD USING A TRIGGER GENERATION

      
Numéro d'application 18946120
Statut En instance
Date de dépôt 2024-11-13
Date de la première publication 2025-02-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sauer, Matthias
  • Pöppe, Olaf

Abrégé

An automated test equipment comprises a main test flow control configured to operate a test flow in multiple device communication units and/or to provide the trigger configuration information to a local compute unit. The automated test equipment further comprises a device communication unit comprising a trigger generation unit configured to generate a trigger signal. The trigger generation unit further configured to extract payload data from a protocol-based data stream received from the device under test, and to generate the trigger signal in response to the extracted payload data or in response to one or more protocol events. A method and a computer program for testing one or more devices under test in an automated test equipment are also disclosed.

Classes IPC  ?

  • G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
  • G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie

36.

OPTICAL MEASUREMENT DEVICE

      
Numéro d'application JP2023029888
Numéro de publication 2025/041201
Statut Délivré - en vigueur
Date de dépôt 2023-08-18
Date de publication 2025-02-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Hara Hideo

Abrégé

The present invention reduces loss of light between an optical probe and an optical measurement part. An optical measurement device 1 measures incident light applied to the light receiving end 21e of an optical element 2 and emitted light emitted from the emission end 22e of the optical element 2. The optical measurement device 1 comprises an incident optical probe 11 which is close to the light receiving end 21e and emits incident light, an emission optical probe 12 which is close to the emission end 22e and receives emitted light, an incident optical waveguide 141 which applies incident light to the incident optical probe 11, an emission optical waveguide 142 which receives the emitted light from the emission optical probe 12, an incident light measurement instrument 143 which measures incident light traveling through the incident optical waveguide 141, and an optical measurement part 14 which has an emitted light measurement instrument 144 which measures emitted light traveling through the emission optical waveguide 142. The incident optical probe 11, the emission optical probe 12, and the optical measurement part 14 are disposed on the same substrate 16. The incident optical probe 11 and the incident optical waveguide 141 are directly connected. The emission optical probe 12 and the emission optical waveguide 142 are directly connected.

Classes IPC  ?

  • G01M 11/00 - Test des appareils optiquesTest des structures ou des ouvrages par des méthodes optiques, non prévu ailleurs

37.

VARIABLE ATTENUATOR, STEP ATTENUATOR, AND TEST DEVICE

      
Numéro d'application JP2023030182
Numéro de publication 2025/041272
Statut Délivré - en vigueur
Date de dépôt 2023-08-22
Date de publication 2025-02-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Tsushima Takahiro
  • Abe Takaya

Abrégé

The present invention provides a variable attenuator comprising: a transmission line having an open stub connected between an input and an output of the variable attenuator; a first switch connected between the input and a reference potential; and a second switch connected between the output and the reference potential.

Classes IPC  ?

  • H03H 11/24 - Atténuateurs indépendants de la fréquence

38.

TEST APPARATUS AND TEST METHOD

      
Numéro d'application JP2023030205
Numéro de publication 2025/041281
Statut Délivré - en vigueur
Date de dépôt 2023-08-22
Date de publication 2025-02-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Kimura Hiroki

Abrégé

Provided is a test apparatus comprising: a first power source that outputs a first voltage of a predetermined magnitude or a first current of a predetermined magnitude; a first switch unit that connects, to the first power source, a connection terminal of a device under test to be tested among connection terminals of a plurality of devices under test; a first measurement unit that measures electrical characteristics of the device under test to be tested in response to the first power source being connected to the device under test to be tested; and a second voltage source that outputs a second voltage of a predetermined magnitude with respect to the connection terminal of at least one device under test, which is different from the device under test to be tested among the plurality of devices under test.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

39.

TESTING APPARATUS, TESTING METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

      
Numéro d'application 18738071
Statut En instance
Date de dépôt 2024-06-10
Date de la première publication 2025-02-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Miyauchi, Koji
  • Hasegawa, Kotaro

Abrégé

Provided is a testing apparatus including: a light source; an electrical measurement unit which measures a photoelectric signal obtained by a test target light emitting element photoelectrically converting light radiated from the light source; and a calculation unit which calculates pseudo external quantum efficiency having a correlation with inherent external quantum efficiency of the test target light emitting element, based on irradiation intensity of light radiated from the light source to the test target light emitting element, a light emission wavelength relating to light emission of the test target light emitting element, and the photoelectric signal being measured of the test target light emitting element.

Classes IPC  ?

  • G01R 31/311 - Test sans contact utilisant des rayonnements électromagnétiques non ionisants, p. ex. des rayonnements optiques de circuits intégrés

40.

SICONIC

      
Numéro de série 79421868
Statut En instance
Date de dépôt 2025-02-26
Propriétaire ADVANTEST CORPORATION (Japon)
Classes de Nice  ? 09 - Appareils et instruments scientifiques et électriques

Produits et services

Semiconductor testing machines; computer software for semiconductor testing machines.

41.

COOLING SHROUD AND ENCLOSURE FOR CONSUMER ELECTRONIC MEMORY DEVICE FOR OPTIMIZED PERFORMANCE THEREOF

      
Numéro d'application 18750720
Statut En instance
Date de dépôt 2024-06-21
Date de la première publication 2025-02-13
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Glasgow, Justin
  • Emberger, Brad
  • Ayyawar, Kapil

Abrégé

Embodiments of the present invention provide memory device (e.g., SSD) enclosures and shrouds that can receive and house SSDs of a specific form factor width, and can advantageously be selectively adapted to house and cool SSDs of a narrower form factor width using an adapter. The SSD shrouds described herein can guide SSDs into the correct position and orientation to be housed by the enclosure for quick and convenient installation, and advantageously redirect the air flow for effective cooling during operation to increase performance of the drive, optionally using internal fins to guide the airflow. Micro fans can be disposed on the top and/or bottom of the enclosure to improve air intake or exhaust. The SSD enclosures and adapters of the present invention obviate the need for differently sized SSD enclosures for specific device form factors and widths, which reduces costs and overhead when running multiple SSDs.

Classes IPC  ?

  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
  • G06F 1/20 - Moyens de refroidissement

42.

CONNECTING DEVICE, TESTING DEVICE, AND COMMUNICATION DEVICE

      
Numéro d'application 18931093
Statut En instance
Date de dépôt 2024-10-30
Date de la première publication 2025-02-13
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Tsushima, Takahiro

Abrégé

A connecting device, including: a first connecting unit that switches a connection between a first terminal and a second terminal; and a second connecting unit that switches a connection between the first terminal or the second terminal and a third terminal, wherein the first connecting unit has: a first transmission line; a first connection switching unit that switches the connection between the first terminal and the second terminal via the first transmission line; and a first ground switching unit that switches a connection of each of three or more first connection points at different positions in the first transmission line to a reference potential.

Classes IPC  ?

  • H01P 1/15 - Dispositifs commutateurs ou interrupteurs utilisant des dispositifs à semi-conducteurs
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

43.

OPTICAL CIRCUIT AND METHOD

      
Numéro d'application 18929665
Statut En instance
Date de dépôt 2024-10-29
Date de la première publication 2025-02-13
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Uekusa, Kouichiro

Abrégé

Provided is an optical circuit comprising: an optical switch that outputs an incident light that is polarized in a first polarization direction to any of a first optical path or a second optical path while keeping a polarization state; a polarization rotation coupling element that is arranged on an output side of each of the first optical path and the second optical path, and converts the incident light that is input from the second optical path into polarized light in a second polarization direction that is orthogonal to the first polarization direction, to output the light from an output port, while outputting, from the output port, the incident light that is input from the first optical path while keeping the polarization state.

Classes IPC  ?

  • G02B 6/35 - Moyens de couplage optique comportant des moyens de commutation

44.

IMAGE OUTPUT APPARATUS, METHOD, PROGRAM, AND RECORDING MEDIUM

      
Numéro d'application 18720061
Statut En instance
Date de dépôt 2023-01-23
Date de la première publication 2025-02-06
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Yanagida, Tomonori
  • Ogata, Yuji

Abrégé

An image output apparatus includes a signal source specifying section, and a signal source image adding section. The signal source specifying section is arranged to receive measurement results from a plurality of sensors that receive, from a plurality of signal sources, signals represented by vectors each having a predetermined direction and measure triaxial components orthogonal to each other to specify positions of the signal sources and the directions of the vectors. The signal source image adding section is arranged to add images showing the signal sources to portions of an imaging result from an imaging section arranged to image the signal sources, the portions corresponding to the positions of the signal sources that are specified by the signal source specifying section.

Classes IPC  ?

  • G01R 33/02 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques
  • G01N 27/72 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant des variables magnétiques

45.

PHASE CHANGE MATERIAL SWITCH AND MANUFACTURING METHOD

      
Numéro d'application JP2024015667
Numéro de publication 2025/027952
Statut Délivré - en vigueur
Date de dépôt 2024-04-22
Date de publication 2025-02-06
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sato Taku
  • Yamashita Koji

Abrégé

Provided is a phase change material switch comprising a substrate, a phase change film formed above the substrate, first and second electrodes formed apart from each other on the phase change film, and a heater formed above at least a portion of a channel region between the first and second electrodes in the phase change film.

Classes IPC  ?

  • H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
  • H10B 63/10 - Dispositifs RAM à changement de phase [PCRAM, PRAM]
  • H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors

46.

INDUCTOR

      
Numéro d'application JP2024009972
Numéro de publication 2025/022712
Statut Délivré - en vigueur
Date de dépôt 2024-03-14
Date de publication 2025-01-30
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Takayanagi Fumikazu

Abrégé

The inductor comprises a magnetic core and a coil. The magnetic core has an end surface and a side surface that intersects the end surface, and is formed on a substrate. The coil is wound around the side surface. The end surface has a plurality of protrusions. An interval between the protrusions is smaller than the wavelength of an electromagnetic wave that is generated by an eddy current that occurs in the end surface. The depth of the protrusions is deeper than a predetermined depth at which the electric current density of the eddy current is attenuated to a predetermined ratio.

Classes IPC  ?

  • H01F 10/13 - Alliages métalliques amorphes, p. ex. métaux vitreux
  • H01F 10/16 - Métaux ou alliages contenant du cobalt
  • H01F 17/00 - Inductances fixes du type pour signaux
  • H01F 17/04 - Inductances fixes du type pour signaux avec noyau magnétique

47.

THREE-DIMENSIONAL DEVICE AND MANUFACTURING METHOD THEREOF

      
Numéro d'application 18908714
Statut En instance
Date de dépôt 2024-10-07
Date de la première publication 2025-01-23
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sugatani, Shinji
  • Ohba, Takayuki

Abrégé

When testing a memory chip, the memory chip is determined to be defective if even a portion of the memory chip is defective, and is discarded, which lowers the yield of the three-dimensional memory device. A three-dimensional device is provided comprising a plurality of stacked circuit chips each having one or more circuit blocks in each of a plurality of divided regions obtained by dividing a circuit plane and an interconnect portion communicatively connected, for each group of circuit blocks included in each of the divided regions overlapping in a stacking direction in the plurality of circuit chips, to a predetermined number of circuit blocks sorted from the circuit blocks within the group.

Classes IPC  ?

  • H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
  • G11C 29/12 - Dispositions intégrées pour les tests, p. ex. auto-test intégré [BIST]
  • H01L 21/50 - Assemblage de dispositifs à semi-conducteurs en utilisant des procédés ou des appareils non couverts par l'un uniquement des groupes ou
  • H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
  • H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
  • H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

48.

METHOD, APPARATUS, AND NON-TRANSITORY COMPUTER MEDIUM FOR DETECTING DEFECTS OF A DEVICE UNDER TEST USING TIME-DOMAIN REFLECTOMETRY

      
Numéro d'application 18355395
Statut En instance
Date de dépôt 2023-07-19
Date de la première publication 2025-01-23
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Shang, Yang
  • Hashimoto, Masaichi
  • Shinohara, Makoto

Abrégé

A method, apparatus, and/or system for soft defects modeling of measurements using time-domain reflectometry. Electro-Optic Sampling based Time-Domain Reflectometry (EOS-TDR) may quickly detect soft defects in a chip under test. For example, EOS-TDR may detect soft defects in each pin from a trace-structure point at a relatively high resolution. To interpret the results in a time sensitive manner, a reference model for chips may be established from chips that are known to have met the expected quality standards. Through automated analysis of the features of the device under test waveform, soft defects of a chip may be detected that would be otherwise undetectable under time constraints, temperature variations, applied current variations, applied voltage variations, vibration variations, moisture variations, or any other kind of possible variation.

Classes IPC  ?

  • G01R 31/11 - Localisation de défauts dans les câbles, les lignes de transmission ou les réseaux en utilisant des méthodes de réflexion d'impulsion

49.

TEMPERATURE ADJUSTMENT SYSTEM AND ELECTRONIC COMPONENT TESTING APPARATUS

      
Numéro d'application 18708854
Statut En instance
Date de dépôt 2021-11-09
Date de la première publication 2025-01-23
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s)
  • Yamada, Yuya
  • Jeserer, Guenther

Abrégé

A temperature adjustment system for adjusting a temperature of a DUT electrically connected to a socket includes a first temperature adjustment device that supplies a fluid to an internal space in either the socket or a contact member that contacts the DUT when the DUT is pressed against the socket and a second temperature adjustment device that adjusts a temperature of an atmosphere in a chamber in which the socket and the contact member are disposed. The first temperature adjustment device includes a first supplier that supplies a first fluid and includes one or more connectors connected to one or more supply sources that supply the first fluid and a heat exchanger disposed between the one or more connectors and the internal space. The heat exchanger has a heat exchange part exposed in the chamber and exchanges heat between the first fluid and the atmosphere in the chamber.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

50.

SWITCHABLE ROUTING CIRCUIT AND METHOD FOR ROUTING A SIGNAL

      
Numéro d'application EP2023070192
Numéro de publication 2025/016545
Statut Délivré - en vigueur
Date de dépôt 2023-07-20
Date de publication 2025-01-23
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Bianchi, Giovanni

Abrégé

The invention relates to a switchable routing circuit (2) comprising: - a plurality of ports including a common input (P1) port and two selection ports (P2, P3); - at least one resistor (R); - a plurality of switching elements (SW0, SW2, SW3), wherein each of the ports (P1, P2, P3) is connected to a respective one of the plurality of switching elements (SW0, SW2, SW3); and - a coupling element (C1), which is coupled between the plurality of ports (P1, P2, P3); wherein the switchable signal routing circuit (2) is configured to couple the common input port (P1) to one or both of the selection ports (P2, P3) by: - varying the even and odd characteristic impedances of the coupling element (C1); and - switching the respective one of the switching elements (SW0, SW2, SW3) between a short-circuit-state and an open-circuit-state.

Classes IPC  ?

  • H01P 1/12 - Dispositifs commutateurs ou interrupteurs utilisant un vibreur mécanique
  • H01P 1/15 - Dispositifs commutateurs ou interrupteurs utilisant des dispositifs à semi-conducteurs
  • H01P 5/16 - Dispositifs à accès conjugués, c.-à-d. dispositifs présentant au moins un accès découplé d'un autre accès

51.

ANTENNA DEVICE WITH CURVED RIDGES

      
Numéro d'application EP2023068801
Numéro de publication 2025/008076
Statut Délivré - en vigueur
Date de dépôt 2023-07-06
Date de publication 2025-01-09
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • RADIO GIGABIT INC. (USA)
Inventeur(s)
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Zhuravleva, Olga
  • Kirillova, Margarita
  • Churkin, Sergey

Abrégé

The invention relates to an antenna device and an automated test equipment comprising a double-ridged waveguide structure with a first and a second ridge and a circular polarization antenna structure coupled to the double-ridged waveguide and extending between the double-ridged waveguide structure and a radiating aperture of the antenna device. The circular polarization antenna structure comprises a third ridge having a first curved extension and transitioning into the first ridge and a fourth ridge having a second curved extension different from the first curved extension and transitioning into the second ridge.

Classes IPC  ?

  • H01Q 13/02 - Cornets de guide d'onde
  • H01Q 13/08 - Terminaisons rayonnantes de lignes de transmission micro-ondes à deux conducteurs, p. ex. lignes coaxiales ou lignes micro-rayées

52.

MICROFLUIDIC DEVICE AND MICROPARTICLE MEASUREMENT SYSTEM

      
Numéro d'application 18757669
Statut En instance
Date de dépôt 2024-06-28
Date de la première publication 2025-01-09
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Washizu, Nobuei
  • Takada, Takeaki
  • Taguchi, Hoshito
  • Oinuma, Kosuke
  • Maniwa, Hitomi

Abrégé

A microfluidic device has a microfluidic chip. The microfluidic chip has a channel formed in an in-plane direction thereof. The microchannel has a gate with a narrowed width, and a first part and a second part separated by the gate. With the length of the gate denoted as L, and with the width of the gate denoted as W, a relational expression 1≤L/W<2 is satisfied.

Classes IPC  ?

  • B01L 3/00 - Récipients ou ustensiles pour laboratoires, p. ex. verrerie de laboratoireCompte-gouttes

53.

REDUCED HEADER SIGNAL INFORMATION TESTING SYSTEMS AND METHODS

      
Numéro d'application 18759721
Statut En instance
Date de dépôt 2024-06-28
Date de la première publication 2025-01-09
Propriétaire Advantest Corporation (Japon)
Inventeur(s) Seminario, Max

Abrégé

Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In some embodiments a signal processing test method comprises: selecting a signal processing mode between a header included mode, a reduced header training mode, and a reduced header mode; performing a signal processing information determination process in accordance with a result of the selecting a signal process mode; and performing modulation/demodulation related processes in accordance with results of the signal processing information determination process. In a reduced header mode, a process is performed on a communication signal where header information is not initially readily available in the communication signal itself, and demodulation parameter information is advantageously derived/developed/extrapolated from other information in the communication signal.

Classes IPC  ?

  • H04L 43/50 - Disposition de test
  • H04L 27/26 - Systèmes utilisant des codes à fréquences multiples
  • H04L 27/34 - Systèmes à courant porteur à modulation de phase et d'amplitude, p. ex. en quadrature d'amplitude

54.

TEST APPARATUS, TEST METHOD, AND COMPUTER-READABLE STORAGE MEDIUM

      
Numéro d'application 18895298
Statut En instance
Date de dépôt 2024-09-24
Date de la première publication 2025-01-09
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Hasegawa, Kotaro
  • Miyauchi, Kouji
  • Utamaru, Go

Abrégé

A test apparatus includes: an electrical connection unit to be electrically connected to a terminal of each of a plurality of light emitting devices to be tested; a light source unit for collectively irradiating the plurality of light emitting devices with light; a measuring unit for measuring a photoelectric signal obtained by photoelectrically converting light irradiated by the light source unit and output via the electrical connection unit by each light emitting device; an acquisition unit for acquiring a correction map including a correction value for correcting a variation in intensity of light with which a position of each light emitting device is irradiated by the light source unit; and a determination unit for determining a quality of each light emitting device on a basis of a measurement result by the measuring unit and the correction map acquired by the acquisition unit.

Classes IPC  ?

  • G01R 31/26 - Test de dispositifs individuels à semi-conducteurs
  • G01R 31/317 - Tests de circuits numériques
  • H05B 45/12 - Commande de l'intensité de la lumière à l'aide d'un retour optique
  • H05B 45/22 - Commande de la couleur de la lumière à l'aide d'un retour optique
  • H05B 45/50 - Circuits pour faire fonctionner des diodes électroluminescentes [LED] réagissant aux dysfonctionnements des LED ou à un comportement indésirable des LEDCircuits pour faire fonctionner des diodes électroluminescentes [LED] sensibles à la vie des LEDCircuits de protection

55.

METHOD AND APPARATUS FOR DETERMINING AND INFORMATION ABOUT CHARACTERISTICS OF ONE OR MORE DEVICES UNDER TEST, DUTs, USING A STATISTICALLY SIGNIFICANT DISSIMILARITY VALUE

      
Numéro d'application 18760029
Statut En instance
Date de dépôt 2024-07-01
Date de la première publication 2025-01-02
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Rivoir, Jochen

Abrégé

Embodiments comprise methods and apparatuses for determining an information about characteristics of one or more devices under test (DUTs) using measurement data from an automated test equipment (ATE), the measurement data comprising a plurality of measurement results and information describing corresponding measurement conditions of the devices under test (DUTs).

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

56.

TESTING ARRANGEMENT AND METHOD FOR DETERMINING AN OPTIMIZED DISTANCE BETWEEN A DEVICE UNDER TEST AND AN ANTENNA OF A TESTING ARRANGEMENT

      
Numéro d'application EP2023066507
Numéro de publication 2024/260540
Statut Délivré - en vigueur
Date de dépôt 2023-06-19
Date de publication 2024-12-26
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Moreira, José

Abrégé

A method and a testing arrangement for determining an optimized distance between a device under test and an antenna of a testing arrangement are presented. The method comprises obtaining first measurement data, wherein the first measurement data represent a plurality of far field measurement results characterizing the device under test for a set of frequencies, or wherein the first measurement data are based on a plurality of far field measurement results characterizing the device under test for a set of frequencies, obtaining second measurement data, wherein the second measurement data represent a plurality of near field measurement results characterizing the device under test for the set of frequencies, or wherein the second measurement data are based on a plurality of near field measurement results characterizing the device under test for the set of frequencies; wherein at least two of the near field measurement results are captured at different distances between the device under test and an antenna of the testing arrangement; and determining the optimized distance between the device under test and the antenna of the testing arrangement based on the first and second measurement data.

Classes IPC  ?

  • G01R 29/08 - Mesure des caractéristiques du champ électromagnétique

57.

OPTICAL INPUT/OUTPUT DEVICE

      
Numéro d'application JP2023023383
Numéro de publication 2024/262028
Statut Délivré - en vigueur
Date de dépôt 2023-06-23
Date de publication 2024-12-26
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Hara Hideo

Abrégé

The present invention facilitates alignment of an end surface of an optical waveguide, with an optical probe. An optical input/output device 1 inputs and outputs light to and from an object 10 to be measured, the object 10 comprising: a substrate 4 having a groove 4a; and an optical element 2 arranged on the substrate 4, and the object 10 having an optical waveguide 21 arranged in the optical element 2. The optical input/output device 1 comprises: an optical probe 11 arranged close to an end surface 21e of the optical waveguide 21 exposed at a side surface 2s of the optical element 2; a fixing member 12 to which the optical probe 11 is fixed; and a downward pressing member 14 that presses the fixing member 12 toward the substrate 4. The fixing member 12 has a projection 12a that fits into the groove 4a. The groove 4a extends toward the side surface 2s of the optical element 2. The optical input/output device 1 further includes a lateral pressing member 18 that presses the optical probe 11 toward the end surface 21e of the optical waveguide 21 after the projection 12a is fitted into the groove 4a.

Classes IPC  ?

  • G01M 11/00 - Test des appareils optiquesTest des structures ou des ouvrages par des méthodes optiques, non prévu ailleurs

58.

FINE PARTICLE MEASUREMENT DEVICE AND FINE PARTICLE MEASUREMENT METHOD

      
Numéro d'application JP2024019658
Numéro de publication 2024/252999
Statut Délivré - en vigueur
Date de dépôt 2024-05-29
Date de publication 2024-12-12
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Imai Yasuharu
  • Sato Hiroshi
  • Oinuma Kosuke
  • Washizu Nobuei

Abrégé

A fine particle measurement device 1 is used together with a pore device 100. The pore device 100 has a first liquid chamber 122 and a second liquid chamber 124 that are separated by a partition having pores. A measurement instrument 200 measures an electric current signal flowing between a first electrode E1 provided in the first liquid chamber 122 and a second electrode E2 provided in the second liquid chamber 124. When clogging of the pore device 100 is detected during measurement, a pressure control device 400 generates a pressure difference between the first liquid chamber 122 and the second liquid chamber 124.

Classes IPC  ?

  • G01N 15/13 - Détails portant sur les fentes
  • G01N 15/12 - Recherche de particules individuelles en mesurant des effets électriques ou magnétiques en observant des changements de résistance ou d’impédance à travers des fentes traversées par des particules individuelles, p. ex. en utilisant le principe de Coulter

59.

MICROPARTICLE MEASUREMENT APPARATUS

      
Numéro d'application JP2024019659
Numéro de publication 2024/253000
Statut Délivré - en vigueur
Date de dépôt 2024-05-29
Date de publication 2024-12-12
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sato Hiroshi
  • Imai Yasuharu
  • Washizu Nobuei

Abrégé

This microparticle measurement device 1 is used together with a pore device 100. The pore device 100 comprises a first liquid chamber 122 and a second liquid chamber 124 that are separated by a partition which has pores. A measurement instrument 200 measures a current signal flowing between a first electrode E1 provided in the first liquid chamber 122 and a second electrode E2 provided in the second liquid chamber 124. When clogging of the pore device 100 is detected during measurement, a pressure control device 400 generates a pressure difference between the first liquid chamber 122 and the second liquid chamber 124.

Classes IPC  ?

  • G01N 15/13 - Détails portant sur les fentes
  • G01N 15/12 - Recherche de particules individuelles en mesurant des effets électriques ou magnétiques en observant des changements de résistance ou d’impédance à travers des fentes traversées par des particules individuelles, p. ex. en utilisant le principe de Coulter

60.

TEMPERATURE ADJUSTING SYSTEM, CONTROLLER, ELECTRONIC DEVICE HANDLING APPARATUS, TESTER, AND ELECTRONIC DEVICE TESTING APPARATUS

      
Numéro d'application 18678474
Statut En instance
Date de dépôt 2024-05-30
Date de la première publication 2024-12-05
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Yamada, Yuya

Abrégé

A temperature adjusting system includes a temperature adjuster that adjusts a temperature of a device under test (DUT) and a first acquirer that acquires a first digital signal and outputs a second digital signal. The first digital signal is output from a first temperature detecting circuit in the DUT and indicates an internal temperature of the DUT. The temperature adjusting system includes a controller that controls the temperature adjuster using the second digital signal.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

61.

Market Life Cycle Based Manufacturing Input Component Systems and Methods

      
Numéro d'application 18204201
Statut En instance
Date de dépôt 2023-05-31
Date de la première publication 2024-12-05
Propriétaire Advantest Corporation (Japon)
Inventeur(s) Du, Jack Hongtao

Abrégé

Efficient and effective life cycle manufacturing input control systems and methods are presented. In one embodiment, a life cycle manufacturing input control method comprises: accessing market life cycle information associated with an input component to a manufacturing process, performing a KPI process, wherein the KPI process produces a KPI score, and configuring utilization of an input component to a manufacturing process based upon the KPI score. The KPI process can include: determining life cycle stage of the input component, assigning a confidence factor to the life cycle stage; and establishing a KPI score in the manufacture of test equipment.

Classes IPC  ?

  • G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations
  • G06Q 10/0639 - Analyse des performances des employésAnalyse des performances des opérations d’une entreprise ou d’une organisation
  • G06Q 50/04 - Fabrication

62.

SEMICONDUCTOR TEST RESULT ANALYSIS DEVICE, SEMICONDUCTOR TEST RESULT ANALYSIS METHOD, AND RECORDING MEDIUM

      
Numéro d'application 18753303
Statut En instance
Date de dépôt 2024-06-25
Date de la première publication 2024-11-28
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ikeda, Kosuke
  • Sugimura, Hajime

Abrégé

A condition data acquirer acquires first data (condition data) of a plurality of items related to a test process of a plurality of semiconductor chips. A test result acquirer acquires second data (test result data) indicating test results of the plurality of semiconductor chips in the test process. A decision tree generator generates a decision tree with each item of the condition data as a feature amount and the test result data as a target value. An analysis result outputter outputs, as an item having a large influence on the test results, information of a feature amount having a relatively high importance in the decision tree.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

63.

SEMICONDUCTOR TEST RESULT ANALYSIS DEVICE, SEMICONDUCTOR TEST RESULT ANALYSIS METHOD, AND RECORDING MEDIUM

      
Numéro d'application 18753355
Statut En instance
Date de dépôt 2024-06-25
Date de la première publication 2024-11-28
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ikeda, Kosuke
  • Gunya, Tatsuaki

Abrégé

A condition data acquirer acquires first data of a plurality of items related to a test process of a plurality of semiconductor chips. A test result acquirer acquires second data indicating test results of the plurality of semiconductor chips in the test process. In a region in which a plurality of items of the condition data are arranged on one axis and a plurality of values of the respective items is arranged in a direction orthogonal to the axis, a graph generator generates a graph image in which corresponding values are connected by lines over the plurality of items for each group of a plurality of semiconductor chips having the same test environment. The graph generator changes a form of the lines for each group in the graph image according to a ratio of the semiconductor chips whose test results have been failed in each group.

Classes IPC  ?

  • G01R 31/26 - Test de dispositifs individuels à semi-conducteurs

64.

INTEGRATED CIRCUIT, AUTOMATED TEST EQUIPMENT AND METHOD FOR TESTING A DEVICE UNDER TEST, USING ON-CHIP CONNECTIONS BETWEEN VOLTAGE PROVIDER CIRCUITS

      
Numéro d'application EP2023063984
Numéro de publication 2024/240349
Statut Délivré - en vigueur
Date de dépôt 2023-05-24
Date de publication 2024-11-28
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Bauer, Rudi
  • Rottner, Franz
  • Thalmaier, Alois
  • Stieglbauer, Korbinian

Abrégé

Embodiments according to the invention comprise an integrated circuit for testing a device under test, comprising a first voltage provider circuit configured to provide a first voltage and a second voltage provider circuit configured to provide a second voltage, wherein the first voltage provider circuit is configured to regulate the first voltage with respect to a first reference signal, which is present on a first reference signal line, wherein the second voltage provider circuit is configured to regulate the second voltage with respect to a second reference signal, which is present on a second reference signal line and wherein the second voltage provider circuit is configured to switchably couple the second reference signal line with a first power sense input of the first voltage provider circuit via an on-chip connection, such that the second reference signal is determined by a potential of the first power sense input of the first voltage provider circuit. Furthermore, respective automated test equipments and methods for testing a device under test are disclosed.

Classes IPC  ?

  • G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie
  • G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
  • G01R 31/3167 - Tests de circuits analogiques et numériques combinés

65.

EVALUATION APPARATUS, EVALUATION METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Numéro d'application 18646654
Statut En instance
Date de dépôt 2024-04-25
Date de la première publication 2024-11-21
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Matsuzaki, Yasunori
  • Nagata, Koichiro
  • Saito, Yuko

Abrégé

Provided is an evaluation apparatus comprising: a result acquisition unit which acquires a test result of each of a first plurality of devices under test; an estimation unit which, based on the test result of each of the first plurality of devices under test, estimates an increasing degree of failure for when determining whether to retest a device under test of which the test result has been a failure using a predetermined determination criterion with respect to when the device under test of which the test result has been the failure is to be retested; and an evaluation unit which evaluates the determination criterion based on the increasing degree of failure.

Classes IPC  ?

66.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING AN ACKNOWLEDGE SIGNALING

      
Numéro d'application 18658472
Statut En instance
Date de dépôt 2024-05-08
Date de la première publication 2024-11-07
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abrégé

An automated test equipment for testing one or more devices under test is configured to receive, from a device under test or from a test case, a command requesting an update of one or more tester resources. The automated test equipment is configured to update one or more tester resources in response to the command provided by the device under test or by the test case. The automated test equipment is configured to provide an acknowledge signaling to the device under test or to the test case, to thereby signal a completion of a tester resource update requested by the device under test or by the test case. A device under test, methods and a computer program are also described.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test
  • G01R 31/319 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie

67.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING A TRIGGER LINE

      
Numéro d'application 18658506
Statut En instance
Date de dépôt 2024-05-08
Date de la première publication 2024-11-07
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abrégé

An automated test equipment for testing a device under test comprises a trigger line which is controllable by the device under test (or, equivalently, by a test case which may, for example, be executed on the device under test). The automated test equipment is configured to update one or more tester resources in response to an activation of the trigger line by the device under test (or, equivalently, by a test case which may, for example, be executed on the device under test). A device under test, methods and a computer program are also described

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

68.

AUTOMATED TEST EQUIPMENT, DEVICE UNDER TEST, TEST SETUP METHODS USING A MEASUREMENT REQUEST

      
Numéro d'application 18658537
Statut En instance
Date de dépôt 2024-05-08
Date de la première publication 2024-11-07
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Hilliges, Klaus-Dieter
  • Bücker, Markus
  • Schulze-Westenhorst, Marcus
  • Pöppe, Olaf
  • Glos, Thomas

Abrégé

An automated test equipment for testing one or more devices under test is configured to receive, from a device under test, a command requesting a measurement of one or more physical quantities. The automated test equipment is configured to perform or initiate the measurement of the one or more physical quantities in response to the command provided by the device under test, and the automated test equipment is configured to provide a measurement result signaling to the device under test, to thereby signal a measurement result requested by the device under test. A device under test, methods and a computer program are also described.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

69.

APPARATUS AND METHOD FOR CONDENSATION PREVENTION FOR 2-PHASE COOLING OF TEST ARRAY

      
Numéro d'application 18140448
Statut En instance
Date de dépôt 2023-04-27
Date de la première publication 2024-10-31
Propriétaire Advantest Corporation (Japon)
Inventeur(s) Zheng, Peter Weixiang

Abrégé

Embodiments of the present invention provide cooling for a test array (e.g., a semiconductor test array) using a 2-phase refrigerant. Testing can be performed without any added insulation, which improves test site density significantly. The refrigerant can be provided by any suitable refrigerant source, such as a pump or valve-controlled pressure chamber, for example, and can be provided to a cold plate of a test site, for example. The cold plate can include a flow field or flow channels for guiding the refrigerant to evenly cool surfaces and/or prevent condensation forming on outer surfaces of the cold plate or test site.

Classes IPC  ?

  • G01R 1/44 - Modifications des instruments pour la compensation des variations de température
  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

70.

MICROPARTICLE MEASUREMENT APPARATUS

      
Numéro d'application JP2024016138
Numéro de publication 2024/225338
Statut Délivré - en vigueur
Date de dépôt 2024-04-24
Date de publication 2024-10-31
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Imai Yasuharu
  • Washizu Nobuei

Abrégé

A pore device 100 comprises a first liquid chamber 122 and a second liquid chamber 124 that are separated by a separation wall having pores. A measurement instrument 200 measures a current signal flowing between a first electrode E1 provided in the first liquid chamber 122 and a second electrode E2 provided in the second liquid chamber 124. A pressure control device 500 generates a pressure difference between the first liquid chamber 122 and the second liquid chamber 124. A tank 514 is connected between a pump 512 and the pore device 100. The pump 512 is stopped during measurement.

Classes IPC  ?

  • G01N 15/13 - Détails portant sur les fentes
  • G01N 15/12 - Recherche de particules individuelles en mesurant des effets électriques ou magnétiques en observant des changements de résistance ou d’impédance à travers des fentes traversées par des particules individuelles, p. ex. en utilisant le principe de Coulter
  • G01N 33/49 - Analyse physique de matériau biologique de matériau biologique liquide de sang

71.

TEST APPARATUS AND METHOD FOR OPERATING A TEST APPARATUS

      
Numéro d'application EP2023058215
Numéro de publication 2024/199654
Statut Délivré - en vigueur
Date de dépôt 2023-03-29
Date de publication 2024-10-03
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Latty, Raphaël
  • Rivoir, Jochen

Abrégé

Disclosed is a test apparatus for performing a set of tests on a device under test, the test apparatus comprising: a test data processor configured for producing a test data set for each of the tests, wherein the test data set comprises a plurality of test variables and at least one test result; a first variable selection processor configured for producing a reduced test data set for each of the test data sets; a function value processor configured for producing one or more function values for each of the reduced test data sets; a supplemented data processor configured for producing a supplemented data set for each of the reduced test data sets; and a second variable selection processor configured for producing a reduced supplemented data set for each of the supplemented data sets.

Classes IPC  ?

  • G01R 31/3183 - Génération de signaux d'entrée de test, p. ex. vecteurs, formes ou séquences de test

72.

MINUTE PARTICLE MEASUREMENT DEVICE AND MINUTE PARTICLE MEASUREMENT METHOD

      
Numéro d'application JP2024007400
Numéro de publication 2024/202876
Statut Délivré - en vigueur
Date de dépôt 2024-02-28
Date de publication 2024-10-03
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Imai Yasuharu
  • Washizu Nobuei

Abrégé

A pore device 100 has a first liquid chamber 122 and a second liquid chamber 124 which are separated by a separation wall having pores 112. A measuring instrument 200 measures a current signal flowing between a first electrode E1 provided in the first liquid chamber 122 and a second electrode E2 provided in the second liquid chamber 124. A pressure control device 400, during the measurement, switches between a first state φ1 in which the pressure of the first liquid chamber 122 is higher than the pressure of the second liquid chamber 124, and a second state φ1 in which the pressure of the first liquid chamber 122 is lower than the pressure of the second liquid chamber 124.

Classes IPC  ?

73.

MAGNETIC SIGNAL NOISE MEASURING APPARATUS, METHOD, AND RECORDING MEDIUM

      
Numéro d'application 18413516
Statut En instance
Date de dépôt 2024-01-16
Date de la première publication 2024-09-19
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ogata, Yuji
  • Yanagida, Tomonori

Abrégé

A magnetic signal noise measuring apparatus includes a magnetic measuring section, a tensor decomposing section, and a signal noise segregating section. The magnetic measuring section measures magnetic noise and a magnetic signal generated by a magnetic signal source as a tensor of second or higher order. The tensor decomposing section tensor-decomposes a measurement result from the magnetic measuring section. The signal noise segregating section segregates a decomposition result from the tensor decomposing section into one representing the magnetic signal and one representing the magnetic noise.

Classes IPC  ?

  • G01R 33/02 - Mesure de la direction ou de l'intensité de champs magnétiques ou de flux magnétiques

74.

SEMICONDUCTOR WAFER TESTING APPARATUS, SEMICONDUCTOR WAFER TESTING SYSTEM, FLATNESS MEASURING DEVICE, AND METHOD OF ADJUSTING FLATNESS OF WIRING BOARD

      
Numéro d'application 18278813
Statut En instance
Date de dépôt 2021-02-24
Date de la première publication 2024-09-12
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Mori, Yuto

Abrégé

A semiconductor wafer testing apparatus tests a device under test (DUT) on a semiconductor wafer. The semiconductor wafer testing apparatus includes a first wiring board including first connectors and that is electrically connected to a probe card having probes that contact the DUT, second wiring boards each including a second connector configured to be fitted to a respective one of the first connectors, and adjusting mechanisms that adjust a flatness of the first wiring board by changing a position of the second wiring boards along a normal direction of the first wiring board when the first connectors are fitted to the second connectors.

Classes IPC  ?

  • G01R 1/073 - Sondes multiples
  • G01B 21/30 - Dispositions pour la mesure ou leurs détails, où la technique de mesure n'est pas couverte par les autres groupes de la présente sous-classe, est non spécifiée ou est non significative pour mesurer la rugosité ou l'irrégularité des surfaces

75.

DEVICE COOLING ENCLOSURE AND ADAPTER FOR HOUSING DEVICES OF DIFFERENT WIDTHS

      
Numéro d'application 18443184
Statut En instance
Date de dépôt 2024-02-15
Date de la première publication 2024-09-12
Propriétaire Advantest Corporation (Japon)
Inventeur(s)
  • Emberger, Brad
  • Glasgow, Justin
  • Ayyawar, Kapil

Abrégé

Embodiments of the present invention provide a DUT air duct shroud that can receive and house DUTs of a specific form factor, and can advantageously be adapted to house and cool DUTs of a different (e.g., narrower) form factor. The DUT shrouds described herein guide the DUT into the correct position and orientation to be received by the test system for quick and convenient installation, and advantageously redirect the air flow to the narrower form factor for effective cooling during testing. The DUT shrouds can be used in conjunction with device interface boards and similar components used to test memory devices and computer hardware using active cooling systems, and embodiments are also operable to house and cool consumer memory devices of different form factors.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

76.

RAW MILK MEASURING APPARATUS AND METHOD OF MANUFACTURING THE SAME

      
Numéro d'application 18574967
Statut En instance
Date de dépôt 2022-03-09
Date de la première publication 2024-09-05
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Yamazaki, Makoto
  • Taguchi, Hoshito
  • Kurosawa, Tomio

Abrégé

A raw milk measuring apparatus includes a flow path. a surfactant. and an electrode. Raw milk flows through the flow path. The surfactant is placed on a side wall of the flow path. The electrode is at least partially disposed within the flow path. The surfactant is at least partially placed upstream the electrode.

Classes IPC  ?

  • G01N 33/04 - Produits laitiers
  • G01N 11/02 - Recherche des propriétés d'écoulement des matériaux, p. ex. la viscosité, la plasticitéAnalyse des matériaux en déterminant les propriétés d'écoulement en mesurant l'écoulement du matériau

77.

TEMPERATURE CONTROL APPARATUS, TEST APPARATUS, TEMPERATURE CONTROL METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

      
Numéro d'application 18632311
Statut En instance
Date de dépôt 2024-04-11
Date de la première publication 2024-08-29
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Kikuchi, Aritomo
  • Ranganathan, Karthik

Abrégé

Provided is a temperature control apparatus, comprising: a mounting unit including a mounting surface for mounting a board-shaped test object on which a plurality of devices are formed; a plurality of heaters provided for each of a plurality of zones into which the mounting surface is divided, which heats corresponding one of the plurality of zones; a device temperature acquiring unit which acquires device temperature data according to a temperature measurement value in a device under test connected to a probe for an operation test among the plurality of devices of the test object; and a temperature control unit which controls two or more of the heaters corresponding to two or more of the zones on each of which at least part of the device under test is mounted, thereby closing a gap between a temperature indicated by the device temperature data and a first target temperature.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

78.

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD

      
Numéro d'application 18481203
Statut En instance
Date de dépôt 2023-10-04
Date de la première publication 2024-08-29
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • TOKYO INSTITUTE OF TECHNOLOGY (Japon)
Inventeur(s)
  • Sugatani, Shinji
  • Takakuwa, Masaki
  • Uehara, Shuji
  • Ohba, Takayuki

Abrégé

A manufacturing method of a semiconductor apparatus in which a semiconductor chip is joined to a target object, the manufacturing method including forming, in a joining region between the semiconductor chip and the target object where the semiconductor chip and the target object should be joined to each other, a plurality of metal paste patterns with a gap being provided in at least a part along a thickness direction between one another, and joining the semiconductor chip and the target object by sintering the plurality of metal paste patterns sandwiched between the semiconductor chip and the target object in a state where the gap exists between one another.

Classes IPC  ?

  • H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension

79.

SYSTEM AND METHOD FOR CALIBRATING A DEVICE-UNDER-TEST INTERFACE

      
Numéro d'application EP2023054752
Numéro de publication 2024/175211
Statut Délivré - en vigueur
Date de dépôt 2023-02-24
Date de publication 2024-08-29
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Kojima, Shoji

Abrégé

A System (2) for calibrating a device-under-test interface (6), comprises: - a test head (4) comprising a signal generator (8) and a measuring unit (10), wherein the signal generator (8) and the measuring unit (10) are removably, directly and electrically connectable or connected to each other via a first signal line (12); - a DUT-unit (16) comprising a loadboard (18), wherein the loadboard (18) comprises an input port (44) and an output port (46); wherein the input port (44) and the output port (46) are electrically connected with each other via a second signal line (28); and - a calculation unit (11); wherein - the signal generator (8) is configured to generate a first calibration signal (S 1) and the system (2) is configurable to transmit the first calibration signal (S1) to the measuring unit (10) and to the input port (24); - the measuring unit (10) is configured to: - measure a second calibration signal (S2) based on the first calibration signal (S1) received from the signal generator (8); and - measure a third calibration signal (S3) based on the first calibration signal (S1) received from the DUT-unit (16) via the output port (46); - the calculation unit (11) is configured to calculate a main calibration signal based on the first, second and third calibration signal (S1, S2, S3) and further to calibrate the device under test interface (6) based on the calculated main calibration signal.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe

80.

DEVICE UNDER TEST SOCKET AND METHOD FOR TESTING A DEVICE UNDER TEST

      
Numéro d'application EP2023070381
Numéro de publication 2024/170107
Statut Délivré - en vigueur
Date de dépôt 2023-07-21
Date de publication 2024-08-22
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Shiota, Natsuki
  • Nettles, Roger

Abrégé

Embodiments according to the invention comprise a device-under-test socket for testing a device under test, comprising a base structure and a lid. The lid is configured to be fixable to the base structure by a rotation of the lid and the lid is configured to push a pusher towards a device under test portion of the base structure. Furthermore, a central portion of the lid is open and/or comprises a low dielectric constant material. In addition, embodiments comprise a method for testing a device under test.

Classes IPC  ?

  • G01R 1/04 - BoîtiersOrganes de supportAgencements des bornes

81.

INDEPENDENT THERMAL CONTROLLER FOR MEMORY DEVICES AND DEVICE INTERFACE BOARDS

      
Numéro d'application 18424501
Statut En instance
Date de dépôt 2024-01-26
Date de la première publication 2024-08-08
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Glasgow, Justin
  • Emberger, Brad
  • Ayyawar, Kapil
  • Tsuji, Soma
  • Tallarico, Joseph L.
  • Turna, Manroop

Abrégé

Systems and methods of independent thermal control of devices under test (DUTs) (e.g., memory devices) are disclosed herein. DUTs are coupled to dedicated cooling channels that include one or more controllable fans. The fans can be controlled independently according to temperature information of the DUTs, which is typically measured by an internal temperature sensor disposed in the DUTs. The fans of the cooling channels can be top-mounted (e.g., downdraft), bottom-mounted (e.g., updraft), or mounted on the front side of a DUT. Each cooling channel also has an exhaust channel on the front, top, and/or bottom of the channel for releasing heat. Advantageously, the air in the channel is guided by a shroud or cover placed over the DUT that can include internal vectored louvres, ridges, fins, ducts, chambers, etc., for directing air across surfaces of the DUT to evenly and efficiently cool the DUT during testing.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

82.

SEMICONDUCTOR INTEGRATED CIRCUIT AND MODULE THEREOF

      
Numéro d'application JP2023003407
Numéro de publication 2024/161595
Statut Délivré - en vigueur
Date de dépôt 2023-02-02
Date de publication 2024-08-08
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ikemoto Junichi
  • Hayase Yusuke
  • Yoda Yasufumi

Abrégé

According to the present invention, a pin electronics IC 400 is formed on a semiconductor chip 500. The pin electronics IC 400 comprises two dummy areas 502, 504 which are positioned at opposite sides in a first direction of the semiconductor chip 500 and in which no transistor that generates heat is disposed. A main circuit 508 of the pin electronics IC 400 is formed in a region 506 sandwiched by the two dummy areas 502, 504.

Classes IPC  ?

  • H01L 27/04 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur
  • H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium

83.

OPTICAL COMB MEASURING APPARATUS

      
Numéro d'application 18387966
Statut En instance
Date de dépôt 2023-11-08
Date de la première publication 2024-08-01
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Sakurai, Takao

Abrégé

An optical comb measuring apparatus that measures an irradiation target having multiple types of measuring targets, includes: an interference signal acquiring section; and a frequency spectrum measuring section. The interference signal acquiring section acquires an interference signal between a post-irradiation signal comb obtained by irradiating the irradiation target with a pre-irradiation signal comb and a local comb set to be different from a repetition frequency of the pre-irradiation signal comb by a predetermined differential frequency. The frequency spectrum measuring section measures a frequency spectrum of a result of acquisition by the interference signal acquiring section. Either one or both of the post-irradiation signal comb and the local comb provided to the interference signal acquiring section have only components within a plurality of required bands including all of predetermined frequencies. Frequency bands of the interference signal corresponding to the plurality of respective required bands have no areas overlapping each other.

Classes IPC  ?

  • G01N 21/45 - RéfringencePropriétés liées à la phase, p. ex. longueur du chemin optique en utilisant des méthodes interférométriquesRéfringencePropriétés liées à la phase, p. ex. longueur du chemin optique en utilisant les méthodes de Schlieren
  • G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes

84.

SWITCH DEVICE AND TESTING DEVICE

      
Numéro d'application JP2023001065
Numéro de publication 2024/154209
Statut Délivré - en vigueur
Date de dépôt 2023-01-16
Date de publication 2024-07-25
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Tsushima Takahiro

Abrégé

A switch device comprising: a plurality of routing circuits each configured to switch whether to electrically connect between a first port and each of a plurality of second ports; and a plurality of clamp circuits, wherein each of the plurality of routing circuits comprises: a connection switching circuit configured to switch whether to electrically connect between the first port and a corresponding second port among the plurality of second ports; and at least one ground switching circuit configured to switch whether to ground a wiring between the first port and the corresponding second port among the plurality of second ports, and wherein each of the plurality of clamp circuits is electrically connected between a node on a wiring between the corresponding second port among the plurality of second ports and the connection switching circuit of a corresponding routing circuit among the plurality of routing circuits, and a reference potential.

Classes IPC  ?

  • H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
  • H03K 17/693 - Dispositifs de commutation comportant plusieurs bornes d'entrée et de sortie, p. ex. multiplexeurs, distributeurs

85.

MAGNETICALLY RETAINED REPLACEABLE CYLINDER COMPONENT FOR PICK-AND-PLACE TEST HEAD UNIT

      
Numéro d'application 18379063
Statut En instance
Date de dépôt 2023-10-11
Date de la première publication 2024-07-11
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Sherman, Patrick
  • Wagner, Don
  • Akiya, Moritoshi

Abrégé

Embodiments of the present invention provide a magnetically retained replaceable contact plate assembly. The magnetically retained replaceable contact plate assembly includes a contact chuck interface. The contact chuck is configured to physically mate with a device under test (DUT). The magnetically retained replaceable contact plate assembly also includes a DUT layout unit interface (DLU). The DLU is configured to couple to multiple magnetically retained replaceable contact plate assemblies and to a semiconductor handler unit. The DLU is configured to move DUTs within a test environment, and the magnetically retained replaceable contact plate assembly is configured to magnetically attach to said DLU.

Classes IPC  ?

  • B25J 15/04 - Têtes de préhension avec possibilité pour l'enlèvement ou l'échange à distance de la tête ou de parties de celle-ci
  • B25J 15/06 - Têtes de préhension avec moyens de retenue magnétiques ou fonctionnant par succion
  • B65G 47/91 - Dispositifs pour saisir et déposer les articles ou les matériaux comportant des pinces pneumatiques, p. ex. aspirantes

86.

SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS

      
Numéro d'application 18450420
Statut En instance
Date de dépôt 2023-08-16
Date de la première publication 2024-07-11
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • Tokyo Institute of Technology (Japon)
Inventeur(s)
  • Sugatani, Shinji
  • Ohba, Takayuki
  • Sakui, Koji
  • Chujo, Norio

Abrégé

To provide a semiconductor apparatus including a transistor element layer having a plurality of transistors which are multi-gate transistors of a floating body structure, a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors, the first wiring layer being laminated on the side of one surface of the transistor element layer, and a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors, the second wiring layer being laminated on the side of another surface of the transistor element layer.

Classes IPC  ?

  • H01L 23/528 - Configuration de la structure d'interconnexion
  • H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
  • H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
  • H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
  • H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
  • H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique

87.

MAGNETICALLY RETAINED REPLACEABLE CHUCK ASSEMBLY FOR PICK-AND-HOLD TEST HEAD UNIT

      
Numéro d'application 18379073
Statut En instance
Date de dépôt 2023-10-11
Date de la première publication 2024-07-11
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Sherman, Patrick

Abrégé

Embodiments of the present invention provide a contact chuck test head for a handler of an integrated circuit tester system. The contact chuck test head comprises a magnetically held DUT contact unit that can be replaced by a technician without requiring any tool or special equipment. The contact chuck test head t is mounted to an automated handler. Magnets are employed at an interface between the DUT contact unit and contact chuck base. This allows the DUT contact unit to be brought into close proximity to the contact chuck base portion and magnetic forces act to both align and mate the two parts together. Since the DUT contact unit requires change out to accommodate different sizes and types of DUTs, it is advantageous to provide an easy swap-out mechanism.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
  • B65G 47/90 - Dispositifs pour saisir et déposer les articles ou les matériaux

88.

STACKED CHIP AND FABRICATION METHOD OF STACKED CHIP

      
Numéro d'application 18450435
Statut En instance
Date de dépôt 2023-08-16
Date de la première publication 2024-07-11
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • Tokyo Institute of Technology (Japon)
Inventeur(s)
  • Sugatani, Shinji
  • Ohba, Takayuki
  • Chujo, Norio
  • Sakui, Koji
  • Fukuda, Tadashi

Abrégé

A stacked chip is provided comprising a first semiconductor chip and a second semiconductor chip, wherein the first semiconductor chip has a first supporting substrate and a first circuit layer including a first region in which a first circuit is formed and a second region in which a second circuit is formed, the second semiconductor chip has a second supporting substrate, a second circuit layer including a third region that corresponds to a position of the first region and a fourth region that corresponds to a position of the second region and in which the second circuit is formed, a first embedded portion embedded in a first hole portion penetrating through the third region and extending to an inside of the second supporting substrate, and a first through via that penetrates through the first embedded portion and the second supporting substrate, and is electrically conducted with the first circuit.

Classes IPC  ?

  • H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
  • H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
  • H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
  • H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées

89.

OPTICAL CIRCUIT, OPTICAL INTEGRATED CIRCUIT, AND METHOD FOR PROVIDING POLARIZATION-INDEPENDENT OUTPUT LIGHT

      
Numéro d'application 18442106
Statut En instance
Date de dépôt 2024-02-15
Date de la première publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Uekusa, Kouichiro
  • Ishida, Masahiro

Abrégé

An optical circuit includes: a polarization rotation/separation element that spatially separates and outputs a first component which is a component in a first polarization direction, out of input light, and a second component obtained by converting a component in a second polarization direction orthogonal to the first polarization direction, out of the input light, into a component in the first polarization direction; a multiplexer that is disposed on an output side of the polarization rotation/separation element, and multiplexes the first component and the second component; and at least one attenuation element that is disposed on the output side of the polarization rotation/separation element, and attenuates any optical power of one of the first component and the second component, both of the first component and the second component, and multiplexed light multiplexed by the multiplexer.

Classes IPC  ?

  • G02B 6/27 - Moyens de couplage optique avec des moyens de sélection et de réglage de la polarisation
  • G02B 6/293 - Moyens de couplage optique ayant des bus de données, c.-à-d. plusieurs guides d'ondes interconnectés et assurant un système bidirectionnel par nature en mélangeant et divisant les signaux avec des moyens de sélection de la longueur d'onde
  • G02B 6/35 - Moyens de couplage optique comportant des moyens de commutation

90.

MAGNETICALLY RETAINED REPLACEABLE CONTACT PLATE FOR SEMICONDUCTOR HANDLER

      
Numéro d'application US2023035167
Numéro de publication 2024/144852
Statut Délivré - en vigueur
Date de dépôt 2023-10-14
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Sherman, Patrick

Abrégé

A magnetically retained replaceable and/or removable contact plate assembly includes a contact chuck interface. The contact chuck is configured to physically mate with a device under test (DUT). The magnetically retained replaceable contact plate assembly also includes a DUT layout unit (DLU) interface. The DLU is configured to couple to multiple magnetically retained replaceable contact plate assemblies and to a semiconductor handler unit. The DLU is configured to position DUTs within a test environment. The magnetically retained replaceable contact plate assembly is configured to magnetically attach to the DLU.

Classes IPC  ?

  • G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux

91.

FLUORESCENCE DETECTION DEVICE

      
Numéro d'application JP2023039159
Numéro de publication 2024/142584
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Satomura Hiroaki
  • Hosaka Tomoya

Abrégé

00; a scope 10 that is inserted at least partially into an abdominal cavity 1a of a subject 1, the scope having a light transmission optical fiber 12 for guiding the excitation light outputted from the light source 34 to emit the excitation light toward tissue in the abdominal cavity of the subject and at least one light reception optical fiber 13 for guiding fluorescence γ emitted from the tissue due to the excitation light irradiation; and a detector 35 that detects the fluorescence collected by the scope. Since the scope has the light reception optical fiber 13 independent from the light transmission optical fiber 12, it is possible to detect fluorescence guided by the light reception optical fiber 13 without detecting excitation light reflected on the light emitting end surface of the light transmission optical fiber 12.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • A61B 1/07 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments avec dispositifs d'éclairement utilisant des moyens conduisant la lumière, p. ex. des fibres optiques
  • G01N 21/64 - FluorescencePhosphorescence

92.

FLUORESCENCE DETECTION APPARATUS

      
Numéro d'application JP2023039160
Numéro de publication 2024/142585
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ichikawa Masayoshi
  • Hosaka Tomoya
  • Satomura Hiroaki
  • Yokota Kazuyuki

Abrégé

A fluorescence detection apparatus 100 comprises: a light source 34 that generates excitation light γ0; a scope 10 that is optically connected to the light source, that is for irradiating tissue in the abdominal cavity 1a of a subject 1 by guiding the excitation light, and that condenses fluorescence γ emitted from the tissue by irradiation with the excitation light; a detector 35 that detects the fluorescence condensed by means of the scope; and a display unit 36c that acquires a laparoscope image from a laparoscope device 200 for imaging inside of the abdominal cavity of the subject and performs display control for displaying a fluorescence detection result by the detector, together with the laparoscope image. The fluorescence detection result is displayed together with the laparoscope image, whereby a user can operate the scope of the fluorescence detection apparatus while viewing the laparoscope image and/or the fluorescence detection result, to thereby detect in detail the fluorescence emitted by a drug 2 in the abdominal cavity.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • A61B 1/045 - Leur commande
  • G01N 21/64 - FluorescencePhosphorescence

93.

FLUORESCENCE DETECTION APPARATUS

      
Numéro d'application JP2023039161
Numéro de publication 2024/142586
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ichikawa Masayoshi
  • Hosaka Tomoya
  • Satomura Hiroaki
  • Yokota Kazuyuki

Abrégé

0gg in a visible light region; a scope 10 that is optically connected to the excitation light source and the guide light source, that is for irradiating tissue in the abdominal cavity of a subject by guiding the guide light together with the excitation light, and that condenses fluorescence emitted from the tissue by irradiation with the excitation light; and a display unit 36c that acquires a captured image of the abdominal cavity from a laparoscope device 200 for imaging the abdominal cavity of the subject and performs display control on the captured image. By superposing the guide light on the excitation light by the scope when performing the irradiation of the tissue in the abdominal cavity of the subject, it is possible to operate a probe while visually confirming an irradiation site on the captured image of the abdominal cavity.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • G01N 21/64 - FluorescencePhosphorescence

94.

FLUORESCENCE DETECTION DEVICE

      
Numéro d'application JP2023039163
Numéro de publication 2024/142588
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s) Satomura Hiroaki

Abrégé

A fluorescence detection device 100 comprises: an excitation light source 34a that produces excitation light γ0; a scope 10 that is optically connected to the excitation light source and is inserted at least partially into an abdominal cavity 1a of a subject 1 to irradiate tissue in the abdominal cavity of the subject with the excitation light outputted from the excitation light source and collect fluorescence γ emitted from the tissue due to the excitation light irradiation; a detector 35 that detects the fluorescence collected by the scope; a distance detection unit 36e that detects the distance between the tissue and the scope; and an analysis unit 36b that analyzes the fluorescent state of the tissue by correcting the result of the detection by the detector on the basis of the result of the detection of the distance. As such, the result of the detection of the fluorescence γ is corrected on the basis of the result of the detection of the distance between the tissue of the subject being examined and the scope, and thus it is possible to analyze the fluorescence state with constant sensitivity regardless of the distance of the scope.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • G01N 21/64 - FluorescencePhosphorescence

95.

PROTECTIVE CIRCUIT AND SWITCH CONTROL DEVICE

      
Numéro d'application 18558285
Statut En instance
Date de dépôt 2022-04-28
Date de la première publication 2024-07-04
Propriétaire ADVANTEST Corporation (Japon)
Inventeur(s) Kasahara, Kiyotaka

Abrégé

A protective circuit that protects a semiconductor switch includes a group of terminals consisting of either one or more input terminals and two or more output terminals, or one or more output terminals and two or more input terminals, a first resistive circuit, connected to one of the terminals, comprising a resistor having a first temperature coefficient of resistance; and a second resistive circuit, connected to another one of the terminals, comprising a resistor having a second temperature coefficient of resistance different in temperature characteristics from the first temperature coefficient of resistance. The protective circuit is electrically connected to a control terminal of the semiconductor switch, and shuts off a passing current of the semiconductor switch when a temperature of the semiconductor switch is equal to or higher than a current shut-off temperature.

Classes IPC  ?

  • H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
  • G01R 1/20 - Modifications des éléments électriques fondamentaux en vue de leur utilisation dans des appareils de mesures électriquesCombinaisons structurelles de ces éléments avec ces appareils
  • H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension

96.

FLUORESCENCE DETECTION DEVICE

      
Numéro d'application JP2023039158
Numéro de publication 2024/142583
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ichikawa Masayoshi
  • Hosaka Tomoya
  • Satomura Hiroaki
  • Yokota Kazuyuki

Abrégé

A fluorescence detection device 100 comprises: a light source 34 that produces excitation light γ0; a scope 10 that is optically connected to the light source and is inserted at least partially into an abdominal cavity 1a of a subject 1 to irradiate tissue in the abdominal cavity of the subject with the excitation light outputted from the light source and collect fluorescence γ emitted from the tissue due to the excitation light irradiation; a detector 35 that detects the fluorescence collected by the scope; and an analysis unit that analyzes the fluorescent state of the tissue by processing the result of the detection by the detector. Since the scope is inserted at least partially into an abdominal cavity of a subject to irradiate tissue in the abdominal cavity with excitation light outputted from the light source and collect fluorescence emitted out of the tissue by a drug administered into the subject due to the excitation light irradiation, the detector detects the fluorescence, and the analysis unit analyzes the fluorescent state by processing the result of the detection, it is possible to quantify location-specific drug concentrations and temporal changes thereof in the abdominal cavity.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • G01N 21/64 - FluorescencePhosphorescence

97.

FLUORESCENCE DETECTION DEVICE

      
Numéro d'application JP2023039162
Numéro de publication 2024/142587
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ichikawa Masayoshi
  • Hosaka Tomoya
  • Satomura Hiroaki
  • Yokota Kazuyuki

Abrégé

A fluorescence detection device 100 according to the present embodiment comprises: a light source 34 that generates excitation light γ0 modulated according to a modulation pattern defined in advance; a scope 10 optically connected to the light source, the scope 10 guiding the excitation light outputted from the light source and irradiating tissue in the abdominal cavity 1a of a subject 1 with the excitation light, and condensing fluorescence γ emitted by the tissue due to being irradiated with the excitation light; a detector 35 for detecting the fluorescence condensed by the scope; and an analysis unit 36b that uses the modulation pattern to remove a background light component from the fluorescence detection result and analyzes the fluorescence state of the tissue. It thereby becomes possible, by using the modulation pattern to remove the background light component from the fluorescence detection result, to detect fluorescence at a high accuracy and obtain highly accurate fluorescence information.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • A61B 1/06 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments avec dispositifs d'éclairement
  • G01N 21/64 - FluorescencePhosphorescence

98.

FLUORESCENCE DETECTION DEVICE

      
Numéro d'application JP2023039164
Numéro de publication 2024/142589
Statut Délivré - en vigueur
Date de dépôt 2023-10-30
Date de publication 2024-07-04
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Ichikawa Masayoshi
  • Hosaka Tomoya
  • Satomura Hiroaki
  • Yokota Kazuyuki

Abrégé

A fluorescence detection device 100 comprises: a light source 34 that produces excitation light γ0; a scope 10 that is optically connected to the light source and guides the excitation light outputted from the light source to irradiate tissue in an abdominal cavity 1a of a subject 1 with the excitation light and collect fluorescence γ emitted from the tissue due to the excitation light irradiation; a detector 35 that detects the fluorescence collected by the scope; and an interlocking device 50 that detects whether or not the scope is connected to the light source and prevents the light source from producing excitation light if the scope is not connected. Accordingly, the interlocking device detects whether or not the scope is connected to the light source and allows the light source to operate if the scope is connected, and thus excitation light is produced only when the scope is correctly connected to the light source, thereby increasing safety.

Classes IPC  ?

  • A61B 1/00 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments
  • A61B 1/06 - Instruments pour procéder à l'examen médical de l'intérieur des cavités ou des conduits du corps par inspection visuelle ou photographique, p. ex. endoscopesDispositions pour l'éclairage dans ces instruments avec dispositifs d'éclairement
  • G01N 21/64 - FluorescencePhosphorescence

99.

AN ANTENNA DEVICE AND AN AUTOMATED TEST EQUIPMENT WITH A RIDGED BLIND MATING WAVEGUIDE FLANGE

      
Numéro d'application EP2022087139
Numéro de publication 2024/132122
Statut Délivré - en vigueur
Date de dépôt 2022-12-20
Date de publication 2024-06-27
Propriétaire ADVANTEST CORPORATION (Japon)
Inventeur(s)
  • Shiota, Natsuki
  • Lam, Daniel
  • Liu, Yuchang

Abrégé

The invention relates to an antenna device for establishing a wireless coupling to a device under test, comprising an antenna structure, and a first blind mating waveguide flange coupled to the antenna structure, wherein the first waveguide flange comprises a ridged waveguide structure with at least two ridges.

Classes IPC  ?

100.

AN ANTENNA DEVICE AND AN AUTOMATED TEST EQUIPMENT COMPRISING AN ORTHOMODE TRANSDUCER

      
Numéro d'application EP2022087140
Numéro de publication 2024/132123
Statut Délivré - en vigueur
Date de dépôt 2022-12-20
Date de publication 2024-06-27
Propriétaire
  • ADVANTEST CORPORATION (Japon)
  • RADIO GIGABIT INC. (USA)
Inventeur(s)
  • Churkin, Sergey
  • Muravyev, Maxim
  • Bulygin, Nikita
  • Mozharovskiy, Andrey
  • Zhuravleva, Olga

Abrégé

The invention relates to an antenna device comprising a quad-ridged waveguide, an open end of which is configured to act as a radiating aperture, and an orthomode transducer, OMT, configured to couple the quad-ridged waveguide to two feed structures.

Classes IPC  ?

  • H01P 1/161 - Sélecteurs de mode, p. ex. pour empêcher ou favoriser la propagation suivant un mode donnéConvertisseurs de mode fonctionnant selon deux modes orthogonaux indépendants, p. ex. transducteurs orthomodes
  • H01Q 13/02 - Cornets de guide d'onde
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