An apparatus includes one or more control circuits configured to connect to a plurality of nonvolatile memory cells. The control circuits are configured to count a number of pulses sent to switches of a charge pump, record a count of the number of pulses sent to the switches and send the count of the number of pulses in response to a request for the count of the recorded number of pulses.
In a tape drive comprising a tape head module, a tape contacts the tape head module during operation. The tape head module comprises a substrate, a plurality of data heads disposed adjacent to the substrate at a media facing surface (MFS), and a closure disposed adjacent to the plurality of data heads. The closure comprises a first side portion disposed at a leading edge, a second side portion disposed at the leading edge, the first and second side portions being recessed from the MFS, and a central portion disposed between the first and second side portions at the leading edge. In some embodiments, the central portion is recessed from the MFS. The central portion may comprise a notch, a taper, or one or more steps. The first and second side portions may be tapered, rounded, or comprise one or more steps to reduce contact of a tape during operation.
G11B 5/187 - Structure ou fabrication de la surface de la tête en contact physique avec le milieu d'enregistrement ou immédiatement adjacente à celui-ciPièces polairesEntrefers
G11B 5/008 - Enregistrement, reproduction ou effacement sur des bandes ou des fils magnétiques
Rather than disposing a cap layer on a rear soft bias (RSB) of a DFL read head prior to the patterning of the RSB and TMR sensor, disclosed is a decoupling layer disposed on the RSB and TMR sensor after they undergo patterning, with the decoupling layer undergoing its own subsequent patterning. The RSB and the TMR sensor can thus be patterned (defined) together without a RSB cap layer adversely affecting the patterning. As the decoupling layer undergoes its separate patterning, its cross-track width can be flexibly optimized to be greater than that of both the RSB and the TMR sensor. In some embodiments, the decoupling layer's extra width will help it completely decouple the RSB and TMR sensor from the top shield. The side shields will be partially decoupled from the top shield due to the extra width, but will still retain partial coupling to the top shield.
A device structure includes a first field effect transistor, a second field effect transistor, and a local interconnect structure. The local interconnect structure includes a first semiconductor pillar structure contacting a top surface of an active region of the first field effect transistor, a metallic structure contacting a top surface of the first semiconductor pillar structure, and a second semiconductor pillar structure contacting an electrical node of the second field effect transistor.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
A head gimbal assembly (HGA) for a hard disk drive includes a carriage arm having a swaging hole, first and second suspensions, and respective first and second swage plates to which the first and second suspensions are respectively coupled. Each swage plate includes a respective series of intermittent swage boss structures extending from a baseplate, where the swage boss structures of each swage plate are relatively positioned, extending from a respective side of the arm into the swaging hole, such each of the one series of swage boss structures interposes with the other series of swage boss structures. With both series of interposed swage boss structures occupying the same swaging hole height, the height of each swage boss can be effectively doubled and a higher retention torque of the swage coupling is enabled even in view of a thinner arm tip and shorter corresponding swaging hole.
A convolutional neural network (CNN) system is provided that includes a flexible accelerator configured to convert an input feature map into a set of input sub-feature maps, each having a similar amount of sparsity. The system allows each of the sub-feature maps to be processed independently while taking advantage of the sparsity. In some aspects, the CNN system is configured with an index processor that receives data value indexes and weight indexes and generates data path processor commands for processing by a separate data path processor. In other aspects, unroll circuitry is configured to unroll feature maps to provide index-value compression. The unroll/compression scheme allows an input feature map to be read sequentially (tile-by-tile) so that an accumulate buffer can be implemented with a single read-only path and single write-only path. This can simplify memory control design, eliminating requirements for expensive cache-like structures while also reducing power.
A memory card is provided with various pad layouts to prevent a data signal pad from contacting a power contact in a host during insertion and removal of the memory card. The memory card can have a form factor and features that accommodate a relatively-large memory with relatively-high performance and accompanying thermal conditions. An efficient card lock mechanism is also provided.
A storage device identifies a die with a defective temperature sensor and excludes the die temperature from thermal calculations. The storage device includes a memory device with multiple dies. Each die includes a temperature sensor. A controller on the storage device executes a defective temperature sensor scheme to obtain a temperature for a first die in the memory device. The controller compares the first die temperature against a benchmark. The controller determines that the first die includes a defective temperature sensor if there is a temperature variance in the first die temperature and the benchmark and if the temperature variance is greater than a die temperature variation threshold.
G11C 7/24 - Circuits de protection ou de sécurité pour cellules de mémoire, p. ex. dispositions pour empêcher la lecture ou l'écriture par inadvertanceCellules d'étatCellules de test
A multi-function universal serial bus (USB) device may include a plurality of USB interfaces, including a first USB interface and a second USB interface. The USB device may include a plurality of memories including a first memory and a second memory. The USB device may include a controller coupled to the first memory and the second memory, the controller configured to: identify which one of the first USB interface and the second USB interface is coupled to a host device; and perform operations on one of the first memory or the second memory based on which one of the first USB interface and the second USB interface is identified to be coupled to the host device.
Disclosed herein are devices, systems, and methods for sequencing nucleic acids using a nanopore. A nucleic acid molecule is fragmented into smaller portions (e.g., individual nucleotides), which are then routed through a nanopore for detection. A device for single-nucleotide sequencing may include a fluidic channel, a disintegrator configured to cleave off portions of a nucleic acid in the fluidic channel, a nanopore coupled to the fluidic channel, and first and second electrodes situated to apply an electrostatic force on the portions of the nucleic acid to divert them out of the fluidic channel and through the nanopore.
A convolutional neural network (CNN) system is provided that includes a flexible accelerator configured to convert an input feature map into a set of input sub-feature maps, each having a similar amount of sparsity. The system allows each of the sub-feature maps to be processed independently while taking advantage of the sparsity. In some aspects, the CNN system is configured with an index processor that receives data value indexes and weight indexes and generates data path processor commands for processing by a separate data path processor. In other aspects, unroll circuitry is configured to unroll feature maps to provide index-value compression. The unroll/compression scheme allows an input feature map to be read sequentially (tile-by-tile) so that an accumulate buffer can be implemented with a single read-only path and single write-only path. This can simplify memory control design, eliminating requirements for expensive cache-like structures while also reducing power.
A semiconductor structure includes a first-tier alternating stack of first-tier insulating layers and first-tier electrically conductive layers, a second-tier alternating stack of second-tier insulating layers and second-tier electrically conductive layers that overlies the first-tier alternating stack, a memory opening vertically extending through the first-tier alternating stack and the second-tier alternating stack, a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor channel, a first contact via structure contacting one of the first-tier electrically conductive layers, a first-tier tubular dielectric spacer including a first inner sidewall contacting the first contact via structure and contacting each first-tier electrically conductive layer that overlies said one of the first-tier electrically conductive layers, and a first-tier pillar structure vertically extending through each first-tier electrically conductive layer and having a top surface that is coplanar with a topmost surface of the first-tier alternating stack.
H01L 23/528 - Configuration de la structure d'interconnexion
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
13.
METHODS AND SYSTEMS FOR NUCLEIC ACID SEQUENCING USING NANOPORES
A method of performing nucleic acid sequencing may comprise using a disintegrator situated in a fluidic channel of a sequencing device to cleave off a portion of a nucleic acid molecule in the fluidic channel; applying an electrostatic force to divert the portion of the nucleic acid molecule through a nanopore; detecting an ionic current through the nanopore; and determining an identity of at least one nucleotide of the portion of the nucleic acid molecule based at least in part on the ionic current. A system for sequencing nucleic acids may comprise an array comprising a plurality of sequencing devices, each comprising a fluidic channel, a disintegrator embedded in the fluidic channel, and a nanopore coupled to an exit end of the fluidic channel; and detection circuitry coupled to the array and configured to detect ionic currents through the nanopores.
With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.
A storage device updates optimal parameters associated with a Thermal Region Tag (TRT). A controller on the storage device assigns a TRT to blocks programmed at a given temperature range and updates an optimal TRT parameters by obtaining a set of representative wordlines and a set of indicative wordlines for a block assigned to the TRT. The controller performs a bit error rate (BER) estimation on indicative wordlines in the set until a valid indicative wordline is found. The controller determines whether a BER Estimation Scan (BES) check is to be performed when the valid indicative wordline is found. In performing the BES check, the controller performs the BER estimation on representative wordlines in the set until a valid representative wordline is found. When a valid representative wordline is found, the controller obtains the optimal TRT parameter and updates the optimal TRT parameter.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.
As block sizes in NAND memory continue to increase in size and density, in can be useful to access less than all of the block, such as sub-block or subset of the blocks NAND strings, in order to reduce read disturbs, reduce power consumption, and increase operating speeds. Although this sort of separation of sub-block can be achieved by independently biasable select gates, the sort of select gate structure can face processing difficulties, particularly at the source side of three dimensional NAND structures. To avoid these difficulties while still providing individually selectable sub-blocks, the following introduces word line based selectors, where multiple word lines of a blocks are programmed with different sets of threshold voltages, allowing them to be biased for individual access of sub-blocks.
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/10 - Circuits de programmation ou d'entrée de données
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
Redundancy bits can be used to more effectively manage address translation cache (ATC) in data storage devices. The data storage device maintains a table of redundancy bits. When a request for an address translation arrives, the redundancy bits are calculated and compared to redundancy bits in the table. If there is a match, then the relevant ATC entry is retrieved and compared to the untranslated addresses. The same process is repeated for each redundancy bits match until finding a match in the ATC. In so doing, the translated address can be requested much earlier than normal by requesting the translated address upon the redundancy bits not matching. The earlier retrieval reduces throughput of the memory device without reducing performance. Furthermore, the unique structure of the internal ATC allows most of the ATC to be located in SRAM/DRAM while simply the redundancy bits are stored in flops.
The present disclosure generally relates to a tape and a tape drive comprising a tape head and a controller. The tape drive comprises a tape comprising three data bands and four servo tracks, a servo track of the four servo tracks being disposed between adjacent data bands, one or more tape head modules, each tape head module comprising a plurality of data elements and two or more servo element pairs, and a controller configured to control each of the one or more tape head modules to write data to and read data from the tape. Each data band has a width of about one-third a total width of the tape, such as about 3800 μm to about 3900 μm. The three data bands and four servo tracks span the total width of the tape.
G11B 5/588 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'une bande par commande de la position des têtes rotatives
G11B 5/008 - Enregistrement, reproduction ou effacement sur des bandes ou des fils magnétiques
20.
WORD LINE BIAS DURING STRIPE ERASE IN A MEMORY DEVICE
The memory device includes a memory block with an array of memory cells that are arranged in edge word lines and non-edge word lines. Some of the word lines are in a first group to be erased in a first pulse and the others are in a second group to be erased in a second pulse. Circuitry is configured to erase the memory cells. In the first erase pulse, the circuitry applies a first inhibit voltage to the non-edge word lines of the second group and applies a higher second inhibit voltage to the edge word lines of the second group. In the second erase pulse, the circuitry applies the first inhibit voltage to the non-edge word lines of the first group and applies the higher second inhibit voltage to the edge word lines of the second group.
G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
21.
Dynamic DC Field Compensator for MAMR Recording Head
The present disclosure generally relates to a magnetic recording system comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises a field generation layer (FGL) spaced a distance of about 2 nm to about 3 nm from the main pole, a first spacer layer disposed on the FGL, a spin torque layer (STL) disposed on the first spacer layer, a second spacer layer disposed on the STL, and a negative polarization layer (NPL) disposed between the second spacer layer and the shield. The spintronic device has a length of about 17 nm to about 21. During operation, the STL has a magnetization precession of about 16 degrees to about 170 degrees, and the FGL has a magnetization precession of about 60 degrees to about 70 degrees.
G11B 5/31 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction utilisant des films minces
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
An external data storage device, without a battery, provides a user-selectable low power mode. The external data storage device includes storage media for storing data and a data port for receiving power and transmitting data to a host device. The external storage data device includes control circuitry configured to negotiate delivery of a first amount of power from the host device in response to connecting the external data storage device to the host device, receive the first amount of power from the host device, receive a selection, via an input device, of a reduced power mode from a user, and reduce power consumption from the host device to a second amount of power lower than the first amount of power in response to receiving the selection of the reduced power mode.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache
23.
MULTI-TIER ERROR CORRECTION CODES FOR DNA DATA STORAGE
Example systems and methods for using a multi-tier error correction code distributed among oligos for DNA data storage are described. A data unit may be encoded as a set of codewords where each codeword is distributed as symbols on different oligos. The codewords may include a set of first tier codewords that include CRC and ECC redundancy data and one or more additional tiers of codewords that include permuted data and corresponding ECC redundancy data. Decoding may include a sequence of decoding iterations between the first tier of codewords and additional tiers of codewords.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G16B 50/00 - TIC pour la programmation d’outils ou de systèmes de bases de données spécialement adaptées à la bio-informatique
24.
Dual FGL and Dual SPL Spintronic Device To Reduce Perpendicular Field At Writing Location
The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.
G11B 5/31 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction utilisant des films minces
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/127 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction
G11B 5/235 - Emploi de matériaux spécifiés pour remplir l'entrefer
25.
Spintronic Device Comprising Dual FGL and Dual SPL To Reduce Perpendicular Field At Writing Location
The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a hot seed layer, and a spintronic device disposed between the main pole and the hot seed layer. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The second SPL of the spintronic device drives the second FGL. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.
G11B 5/31 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction utilisant des films minces
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/127 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction
G11B 5/235 - Emploi de matériaux spécifiés pour remplir l'entrefer
26.
DATA STORAGE DEVICE WITH FLEXIBLE LOGICAL TRACKS AND RADIUS-INDEPENDENT DATA RATE
Various illustrative aspects are directed to a data storage device, comprising one or more disks; at least one actuator mechanism configured to position at least a first head proximate to a first disk surface and a second head proximate to a second disk surface; and one or more processing devices. The one or more processing devices are configured to: assign logical tracks to physical tracks of the disk surfaces such that a respective logical track comprises: at least a portion of sectors of a primary physical track, the primary physical track being on the first disk surface; and at least a portion of sectors of a donor physical track, the donor physical track being on the second disk surface. The one or more processing devices are configured to perform, using the first head and the second head, a data access operation with at least one of the logical tracks.
The present disclosure is generally related to a deep neural network (DNN) device comprising a plurality of spin-orbit torque (SOT) cells. The DNN device comprises an array comprising n rows and m columns of nodes, each row of nodes coupled to one of n first conductive lines, each column of nodes coupled to one of m second conductive lines, each node of the n rows and m columns of nodes comprising a plurality of SOT cells, each SOT cell comprising: at least one SOT layer, at least one ferromagnetic (FM) layer, and a controller configured to store at least one corresponding weight of an n×m array of weights of a neural network in each of the SOT cell. The FM layer may comprise two or more domains, two or more elliptical arms, or two or more states.
Methods and apparatus for power management in data storage devices are provided wherein conformal prediction is employed to determine correction terms for applying to power-per-processing event (P/PE) values. One such data storage device includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine a P/PE value for each of the set of processing engines based on total power consumption measurements using a least squares procedure. A conformalization procedure is applied to sequences of P/PE values to calibrate the P/PE values by determining correction terms for applying to the P/PE values to provide guaranteed power prediction intervals. Delivery of power to the processing engines is then controlled based on the corrected P/PE event values in accordance with a power budget. On-line and off-line examples are provided.
Methods and apparatus for energy management in data storage devices are provided. One such data storage device (DSD) includes a non-volatile memory (NVM), a set of hardware processing engines, and a power sensor to detect a total power consumption of the set of hardware processing engines. A processor is configured to determine an energy-per-processing event value for each of the set of processing engines based on total power consumption measurements and processing event duration values, then control energy delivery to the processing engines based on the energy-per-processing event values in accordance with an energy budget. In some examples, the DSD employs a least-squares procedure to estimate power-per-processing event values so the values can be determined without needing to measure individual power consumption of the processing engines. The power-per-processing event values are converted to energy-per-processing event values based on corresponding processing event durations. A recursive least-squares update procedure is also described.
An electronics backplane assembly includes respective first and second floating backplane connector assemblies each having a backplane connector coupled to a corresponding backplane plate movably coupled with a chassis wall, and a pair of stepped stoppers coupled to the chassis wall and positioned on each side of each backplane plate. Each stepped stopper pair includes a step at a different distance from the chassis wall and positioned to provide a reactive force to the corresponding backplane plate for incrementally engaging respective backplane connectors of an electronics module with a corresponding floating backplane connector. Each floating backplane connector assembly may include a pair of guide stoppers having a stopper structure at respective positions, coupled to the chassis wall and protruding through holes in each backplane plate, where each backplane plate is positioned for connector engagement between the step structure of each stepped stopper and the stopper structure of each guide stopper.
H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti
H01R 13/629 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz
09 - Appareils et instruments scientifiques et électriques
14 - Métaux précieux et leurs alliages; bijouterie; horlogerie
16 - Papier, carton et produits en ces matières
17 - Produits en caoutchouc ou en matières plastiques; matières à calfeutrer et à isoler
18 - Cuir et imitations du cuir
24 - Tissus et produits textiles
25 - Vêtements; chaussures; chapellerie
28 - Jeux, jouets, articles de sport
35 - Publicité; Affaires commerciales
37 - Services de construction; extraction minière; installation et réparation
38 - Services de télécommunications
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Personal identification tags of metal; nonluminous and non-mechanical metal signs; trophies of common metal; metal hardware, namely, general use wall and ceiling mounts for audio, video or computer equipment. Backup drives for computers; blank flash memory cards; blank usb flash drives; cases for data storage devices; computer disk drives; computer hardware and software for data storage; computer hardware; computer memories; computer memory devices; computer network hardware; computer peripherals; computer software to enable retrieval of data; computer software; data cables; data compression software; downloadable mobile applications; electronic circuit cards; electronic memories; encryption software; flash card adapters; flash card readers; flash memory card; flash memory drives; flash memory; hard disk drives; integrated circuit chips; magnetic data carriers, recording discs; memory card cases; memory cards; memory cards for video game machines; portable flash memory devices; portable music players; power cables; secure digital (SD) memory cards; semiconductor memory devices; software for operating and administering data storage devices; solid state drives; usb flash drives; wafers for integrated circuits; scientific apparatus and instruments; calibrating rings; diagnostic apparatus, not for medical purposes; measuring apparatus. Watches, clocks, jewelry, trophies; pins being jewelry; Key chains comprised of split rings with decorative fobs or trinkets; Key rings comprised of split rings with decorative fobs or trinkets; medals and medalions. Cardboard boxes; catalogues; computer hardware reference manuals; computer manuals; instruction sheets; instructional and teaching materials (other than apparatus); manuals for computer software; manuals for instructional purposes; Packaging materials of paper; paper boxes; paper for wrapping and packaging; paper labels; plastic bags for packing; plastic film for packaging; printed booklets; printed brochures; printed informational flyers; printed informational sheets; printed publications; printed leaflets; printed manuals; printed matter; printed newsletters; printed pamphlets; signboards of paper or cardboard; writing instruments; pens [office requisites]; pencils; notebooks; stationery; stickers [stationery]; paper; copying paper [stationery]. Articles made from rubber, namely bags, pouches and carrying cases for computer storage devices. Articles made from leather and imitations of leather, namely, bags, pouches and carrying cases for computer storage devices, tablets, smartphones, data storage devices, and media players; backpacks, carry all bags and travel bags; umbrellas; plastic key chain tags, plastic luggage tags. Textiles and textile goods; towels. Clothing, jackets, shirts, sweaters, sweatshirts, t-shirts, tops, pants, footwear, hats, and headwear. Video and handheld game consoles; plush toys; stress relief exercise toys; golf balls, tees, and markers; bean bag throwing toys, bean bag toy balls; puzzles; toy figures. Advertising services; computerized file management; providing business information; retail services in relation to cases for data storage devices; retail services in relation to computer hardware; retail services in relation to computer peripherals; retail services in relation to computer software; retail services in relation to portable media players; updating and maintenance of data in computer databases. Installation, maintenance and repair of computer hardware, computer peripherals, computer storage devices, computer networks, data storage centers, and media players; upgrading and updating of computer hardware and peripherals; office machines and equipment installation, maintenance and repair; consulting services in the field of physical maintenance of computer hardware, computer peripherals, computer storage devices, computer networks and data storage centers; technical support services, namely, trouble shooting in the nature of the repair of computer hardware; installation of computer systems; technical support services, namely, providing technical advice related to the installation of computer hardware and peripherals. Telecommunication services; electronic transmission of data and documents via computer networks; data transmission for others; computer data transmission services; digital transmission of data. Provision of online training; Organisation of webinars; Arranging and conducting of workshops and seminars; Provision of educational information; Providing electronic publications [not downloadable]; Publishing of newsletters; Publication of manuals; Providing on-line videos, not downloadable. Scientific and technological services; cloud computing; computer programming; computer software consultancy; data migration services; design and development of computer hardware; design and development of computer software; design, development and updating services of software for data hard disk drives, solid-state drives and computer storage devices; design, maintenance, development and updating of computer firmware and software; electronic data storage; electronic storage services for archiving databases, images and other electronic data; information technology [IT] consultancy; off-site data backup; providing information on computer technology and programming; providing technical advice relating to computer hardware and software; providing technical information in the fields of computer hardware, computer data storage, information storage, computer networking and networking interfaces, disk drives, computer disk drives, and electronic memories; recovery of computer data; research services; technical consultancy services relating to information technology; technical support services in the field of data storage, data management and backup of electronic data, on-premises and in the cloud; technical support services, namely, migration of datacenter, server and database applications; troubleshooting of computer software problems.
32.
Highly Textured 001 BiSb And Materials for Making Same
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
G11B 5/39 - Structure ou fabrication de têtes sensibles à un flux utilisant des dispositifs magnétorésistifs
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable and recorded computer software and mobile applications for aggregation of data and electronic media from distributed sources and datasets; downloadable and recorded computer software and mobile applications for the transmission and display of data and electronic media featuring collaboration and information sharing tools; downloadable and recorded computer software and mobile applications for the synchronization, back-up, and encryption and decryption of digital files; downloadable and recorded computer software and mobile applications for accessing media and data stored on distributed computer storage devices; downloadable and recorded computer software and mobile applications for encrypting data; downloadable and recorded computer software and mobile applications for managing data and data storage, for cloud-based network storage, and for use in accelerating the performance and scalability of computing platforms; none of the aforesaid relating to vehicles Providing non-downloadable computer software and mobile applications for aggregation of data and electronic media from distributed sources and datasets; Providing non-downloadable computer software and mobile applicationsfor the transmission and display of data and electronic media featuring collaboration and information sharing tools; Providing nondownloadable computer software and mobile applications for the synchronization, back-up, and encryption and decryption of digital files; Providing non-downloadable computer software and mobile applications for accessing media and data stored on distributed computer storage devices; Providing non-downloadable computer software and mobile applications for encrypting data; Providing nondownloadable computer software and mobile applications for managing data and data storage, for cloud-based network storage, and for use in accelerating the performance and scalability of computing platforms; none of the aforesaid relating to vehicles
34.
Topological Insulator Based Spin Torque Oscillator Reader
The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.
Methods of detecting molecules using an apparatus comprising a plurality of magnetic sensors are disclosed. A method may include binding a first molecule to a proximal wall of a fluid chamber of the apparatus, and adding, to the fluid chamber, a magnetically-labeled molecule comprising a cleavable magnetic label, wherein the magnetically-labeled molecule is configured to bind to or be incorporated by the first molecule. The method may use at least one address line and at least one selector element of the apparatus to detect a characteristic of at least a portion of the plurality of magnetic sensors, wherein the characteristic indicates whether the magnetically-labeled molecule has bound to or been incorporated by the first molecule.
G01N 27/08 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un liquide qui coule sans interruption
G01N 27/74 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant des variables magnétiques des fluides
G01N 33/58 - Analyse chimique de matériau biologique, p. ex. de sang ou d'urineTest par des méthodes faisant intervenir la formation de liaisons biospécifiques par ligandsTest immunologique faisant intervenir des substances marquées
36.
Doping Process To Refine Grain Size For Smoother BiSb Film Surface
The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.
Techniques are provided for optimizing the power consumption of a data storage device included in a battery-operated device. The battery-operated device (e.g., portable devices like wearable devices, smartwatches, and mobile phones) can access certain data stored on the data storage device more frequently when the device operates on battery power as compared to when the device does not operate on battery power. Techniques are provided for identifying and classifying data into different classifications, for example, power sensitive data and non-power sensitive data. Then the device can optimize the battery power consumption of the data storage device by storing or relocating data stored at the data storage device based on the classification of the data.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
39.
PHASE-COHERENT IN-LINE VCSEL ARRAY WITH SLIDER TRAILING MOUNT FOR HAMR
The present disclosure relates to pretreating a magnetic recording head assembly for magnetic media drive. The magnetic recording head assembly comprises a slider having a media facing surface (MFS), a top surface disposed opposite the MFS, a trailing edge surface disposed adjacent to the top surface, and an optical grating disposed on the trailing edge surface. A vertical cavity surface emitting laser (VCSEL) device is mounted to the trailing edge surface of the slider. The VCSEL device is aligned with the optical grating. A magnetic recording head comprising a waveguide and a near field transducer (NFT) coupled to the waveguide is disposed on the trailing edge surface of the slider. The VCSEL device is capable of emitting a plurality of lasers that are phase coherent on to the optical grating. The optical grating is capable of directing the emitted lasers about 90 degrees to the waveguide.
G11B 13/08 - Enregistrement utilisant simultanément ou sélectivement des procédés ou des moyens entrant dans des groupes principaux différentsSupports d'enregistrement correspondantsReproduction simultanée ou sélective correspondante utilisant des interactions ou des moyens de transduction en champ proche et au moins un autre procédé ou moyen pour l'enregistrement ou la reproduction
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
40.
NEAR-FIELD TRANSDUCER FOR HEAT ASSISTED MAGNETIC RECORDING COMPRISING OF THERMALLY STABLE MATERIAL LAYER
The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a main pole, a waveguide disposed adjacent to the main pole, a near field transducer (NFT) coupled between the main pole and the waveguide at a media facing surface (MFS), a thermal shunt disposed on the NFT, the thermal shunt being recessed from the MFS, and a stable material disposed on the NFT at the MFS. In some embodiments, the stable material is wedge-shaped or triangular-shaped. In another embodiment, the stable material comprises a first portion and a second portion, where the first and second portions may each by linear, or where the first portion is triangular-shaped and the second portion is square-shaped. The stable material may be in contact with the thermal shunt, or spaced from the thermal shunt.
G11B 13/08 - Enregistrement utilisant simultanément ou sélectivement des procédés ou des moyens entrant dans des groupes principaux différentsSupports d'enregistrement correspondantsReproduction simultanée ou sélective correspondante utilisant des interactions ou des moyens de transduction en champ proche et au moins un autre procédé ou moyen pour l'enregistrement ou la reproduction
G11B 5/31 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction utilisant des films minces
G11B 5/00 - Enregistrement par magnétisation ou démagnétisation d'un support d'enregistrementReproduction par des moyens magnétiquesSupports d'enregistrement correspondants
41.
Magnetic Control of Molecule Translocation Speed Through a Nanopore
A system for controlling a translocation speed of a molecule through a nanopore may include a fluid chamber containing a solution with a magnetic susceptibility that is different from the magnetic susceptibility of the molecule, a nanopore situated in the fluid chamber, and at least one magnetic component configured to create a magnetic field gradient within the solution to control the translocation speed of a molecule through the nanopore. A system for controlling a translocation speed of a molecule through a nanopore may include a nanopore at least one magnetic component situated to create a magnetic field that causes the molecule to experience a rotational torque as it passes through the nanopore.
A system for controlling a translocation speed of a molecule through a nanopore may include a fluid chamber containing a solution with a magnetic susceptibility that is different from the magnetic susceptibility of the molecule, a nanopore situated in the fluid chamber, and at least one magnetic component configured to create a magnetic field gradient within the solution to control the translocation speed of a molecule through the nanopore. A system for controlling a translocation speed of a molecule through a nanopore may include a nanopore at least one magnetic component situated to create a magnetic field that causes the molecule to experience a rotational torque as it passes through the nanopore.
Embodiments of the present technology provide non-volatile memory devices comprising memory dies that natively generate “exclusive OR (XOR) data pages” that can be used to recover data pages corrupted by UECC errors. Through memory die native-XOR data page generation, embodiments can recover data pages corrupted by UECC errors more efficiently, more rapidly, and with fewer resources than potential alternative technologies.
G06F 11/00 - Détection d'erreursCorrection d'erreursContrôle de fonctionnement
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
The present disclosure generally relate to an integrated circuit utilizing spin orbital-spin orbital (SO-SO) logic. The integrated circuit comprises a plurality of SO-SO logic cells, where each SO-SO logic cell comprises a first spin orbit torque (SOT1 ) layer, a second spin orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layer. Each SO-SO logic cell is configured for: a first current path that is in plane to a plane of the SOT1 layer, and a second current path that is perpendicular to a plane of the SOT2 layer, the second current path being configured to extend into the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices, the one or more interconnects connecting the adjacent SOT devices together.
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
45.
HIGHLY TEXTURED BUFFER LAYER TO GROW YBIPT (110) FOR SPINTRONIC APPLICATIONS
Spot size converter (SSC) in a HAMR magnetic recording head assembly have a plurality of split assist core structures. Each split assist core structure includes multiple assist cores and a main waveguide. Each split core may also include one or more side waveguides such that the main waveguide is sandwiched between the side waveguides and top and bottom assist cores. Adjacent split assist core structures, may share assist cores. The split assist core structures reduce light source power utilized to write data to magnetic media.
G11B 13/04 - Enregistrement utilisant simultanément ou sélectivement des procédés ou des moyens entrant dans des groupes principaux différentsSupports d'enregistrement correspondantsReproduction simultanée ou sélective correspondante par procédé magnétique et procédé optique
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 5/31 - Structure ou fabrication des têtes, p. ex. têtes à variation d'induction utilisant des films minces
47.
FILM AND METHOD FOR BISBX (012) TEXTURE FOR SOT DEVICES
The present disclosure generally relates to spin-orbit torque (SOT) device comprising a bismuth antimony (BiSb) layer. The SOT device comprises a seed layer and a BiSb layer having a (012) orientation. The seed layer comprises at least one of an amorphous/nanocrystalline material with a nearest neighbor x-ray diffraction peak with a d-spacing in the range of about 2.02 Å to about 2.20 Å; a polycrystalline material having a (111) orientation and an a-axis of about 3.53 Å to about 3.81 Å; and a polycrystalline material having a cubic (100) or tetragonal (001) orientation and an a-axis of about 4.1 Å to about 4.7 Å. When the seed layer comprises an amorphous material or a polycrystalline material having a (111), the BiSb layer is doped, and the seed layer has a lower a/c ratio than when the seed layer comprises polycrystalline material having a cubic (100) or tetragonal (001) orientation.
H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
A server includes at least one local memory and communicates with one or more network devices that provide an external shared memory. A kernel space of the server is used to monitor memory usage by different applications executed by the server. A memory kernel module adjusts usage of the at least one local memory and the external shared memory by the different applications based at least in part on the monitored memory usage. In another aspect, a memory access profiling server receives memory information and application usage information added to packets sent between servers and one or more memory devices. The memory access profiling server analyzes the memory information and application usage information to determine memory placement information that is sent to at least one server to adjust usage of the external shared memory.
Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory openings vertically extending through the alternating stack, memory-opening-free areas located in the array of the memory openings in a plan view, an array of memory opening fill structures located in the array of memory openings, and layer contact assemblies located within the memory-opening-free areas in the plan view. Each of the memory opening fill structures includes a respective vertical semiconductor channel and respective memory elements located at levels of the electrically conductive layers. Each of the layer contact assemblies includes a respective layer contact via structure contacting a respective one of the electrically conductive layers, and a respective insulating spacer that laterally surrounds the respective layer contact via structure.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
51.
SHOCK ABSORBER ASSEMBLY FOR A PRINTED CIRCUIT BOARD
A shock absorber for a printed circuit board (PCB) includes a first portion and a second portion. The first portion is positioned on a first side of the PCB at or near a connector that extends from the PCB. The second portion is positioned on a second side of the PCB, opposite the first portion. The first and second portions prevent the PCB from moving when the PCB is coupled to a host device. As the PCB is subjected to various movements, strains and stresses, the shock absorber prevents the PCB from cracking or breaking, especially at or near the connector, which is susceptible to cracking and breaking.
A data storage device and method are provided for using a dynamic floating flash region to secure a firmware update. In one embodiment, a data storage device is provided comprising a first non-volatile memory, a second non-volatile memory, and a controller. The controller is configured to communicate with the first and second non-volatile memories and further configured to: determine addresses in the second non-volatile memory to store portions of a firmware update, wherein the addresses are determined on-the-fly as opposed to being predetermined; and store the portion of the firmware update in the addresses in the second non-volatile memory. Other embodiments are provided.
G06F 8/71 - Gestion de versions Gestion de configuration
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
G06F 21/78 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
A memory device includes an alternating stack of insulating layers and electrically conductive layers containing stepped surfaces in a contact region, a first stepped dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending at least through each layer within the alternating stack, a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel, and a bundled contact via structure vertically extending through the first stepped dielectric material portion and through a plurality of bottommost electrically conductive layers of the electrically conductive layers, and laterally contacting each of the plurality of the bottommost electrically conductive layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
A device carrier mechanism configured for attachment to an electronic device such as a hard disk drive includes a pair of rotatable handles interlocked at a common first pivot at a proximal end of each handle and a respective second pivot at a distal end, a pair of pin mechanisms each coupled at the second pivot of a respective handle and having a protruding latch pin, and a frame with which each pin mechanism is translatably coupled. Such a linkage system operates as an over-center mechanism, in a device handling state responsive to an upward handling force and with the latch pins in a retracted position within the frame, a neutral state with the latch pins in an extended position extending external to the frame, and a locked over-center state with the latch pins clamped in the extended position for locking into a data storage system.
A method of manufacturing hard disk drives (HDDs) includes assembling a first HDD including a first slider having a first air bearing surface (ABS) configuration, configuring the first HDD to rotate its disk media at a first revolutions-per-minute (RPM), and sealing the first HDD with a first internal pressure level. Continuing, the method includes assembling a second HDD including a second head slider having the same first ABS configuration, configuring the second HDD to rotate its disk media at a second RPM that is lower than the first RPM, and sealing the second HDD with a second internal pressure level that is higher than the first pressure level. Thus, in the context of using a common slider among different RPM drives, a higher internal pressure for the lower RPM drive can compensate for loss in fly height that might otherwise occur due to the lower operational RPM.
A semiconductor structure includes a logic die containing a word line switching circuit containing a fin field effect transistor having at least one semiconductor fin, and a planar field effect transistor, and a memory die containing a three-dimensional memory device bonded to the logic die.
H01L 23/528 - Configuration de la structure d'interconnexion
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
57.
CROSS-POINT MAGNETORESISTIVE MEMORY ARRAY CONTAINING CARBON-BASED LAYER AND METHOD OF MAKING THE SAME
A device structure includes first electrically conductive lines that are laterally spaced apart from each other, second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other, a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, and each of the MRAM pillars includes a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer, and a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars.
A device carrier mechanism configured for attachment to an electronic device such as a hard disk drive includes a pair of rotatable handles interlocked at a common first pivot at a proximal end of each handle and a respective second pivot at a distal end, a pair of pin mechanisms each coupled at the second pivot of a respective handle and having a protruding latch pin, and a frame with which each pin mechanism is translatably coupled. Such a linkage system operates as an over-center mechanism, in a device handling state responsive to an upward handling force and with the latch pins in a retracted position within the frame, a neutral state with the latch pins in an extended position extending external to the frame, and a locked over-center state with the latch pins clamped in the extended position for locking into a data storage system.
A semiconductor structure includes a memory die including a three-dimensional memory device, and a logic die bonded to the memory die. The logic die includes a word line switching circuit containing a fin field effect transistor including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further includes a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.
H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
60.
ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A MEMORY DEVICE
The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.
G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
A storage device is communicatively coupled to a host that stores data on a primary memory package on the storage device. A controller on the storage device may monitor the temperature of components on the storage device and determine when the temperature exceeds a thermal temperature limit. When the temperature exceeds a thermal temperature limit, the controller may suspend certain operations on the primary memory package and write host data to the secondary memory package on the storage device. The controller may continue to monitor the temperature on the storage device, determine when the temperature on the storage device returns to an acceptable level, transfer data from the secondary memory package to the primary memory package, and resume writing host data to primary memory package.
Performance on a storage device may be improved when executing a write command with sequential host data. The storage device optimizes logical-to-physical table updates for fixed granularity logical-to-physical tables that are populated when writing the sequential host data. A host interface module on the storage device may receive, from a host, a command to store the host data on a memory device and classify the host data as sequential host data or random host data. A flash translation layer on the storage device predetermines open contiguous blocks on the memory device where the sequential host data is to be written and provides a beginning address of the open contiguous blocks to the host interface module. The host interface module populates an address translation table with logical-to-physical mappings starting at the beginning address with an appropriate offset. Each entry in the address translation table corresponds to a fixed granularity.
A memory device includes layer stacks, each including a respective alternating stack of respective insulating layers and respective electrically conductive layers and a respective contact-level dielectric layer, memory openings vertically extending through a respective one of the alternating stacks. memory opening fill structures located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and dielectric bridges structures located within access trenches that laterally separate the layer stacks. Each of the dielectric bridge structures includes a respective pair of contoured sidewalls. Each contoured sidewall of the dielectric bridge structures includes at least two vertically-straight and horizontally-convex surface segments that are adjoined by a vertically-extending edge. Access trench fill structures are located in the access trenches and each access trench fill structure embed a respective subset of the dielectric bridge structures.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
64.
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING ION IMPLANTED ETCH STOP LAYER ON A SACRIFICIAL FILL MATERIAL
A method includes forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate, forming a first in-process inter-tier dielectric layer over the first alternating stack, forming a first memory opening through the first in-process inter-tier dielectric layer and the first alternating stack, forming a sacrificial memory opening fill structure in the first memory opening, doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species, forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack, forming a second memory opening through the second alternating stack by performing an anisotropic etch process, and removing the sacrificial memory opening fill structure.
H01L 23/528 - Configuration de la structure d'interconnexion
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10B 41/10 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la configuration vue du dessus
H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
65.
THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first dielectric material portion overlying first stepped surfaces of the first alternating stack, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a first contact via structure vertically extending through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.
H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.
A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.
A data storage device includes a non-volatile memory device, a capacitor bank, and a power regulator electrically coupled to the capacitor bank and configured to provide power to the non-volatile memory device. The data storage device further includes a controller configured to discharge the capacitor bank from a first voltage to a second voltage at a first constant current and determine a first discharge time. controller is further configured to discharge the capacitor bank from the first voltage to the second voltage at a second constant current and determine a second discharge time. A voltage holdup time of the capacitor bank is then determined based on at least the first discharge time and the second discharge time.
G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.
A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.
A non-volatile memory system is configured to perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes. Based on that multiplane erase process, the memory system determines that a first group of memory cells in a first plane of the multiple planes is slow to erase. As a result, the system will perform one or more multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase process(es).
G11C 16/14 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
A data storage device and method for host-assisted efficient handling of multiple versions of data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive, from a host, identification of different versions of data that are to deleted together; store the different versions of the data in areas of the memory that are erasable in parallel; receive, from the host, a command to erase the different versions of the data; and erase the different versions of the data in parallel. Other embodiments are provided.
A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
The present disclosure generally relates improved key-per IO (KIPO) processing for multiple tenants. Rather than when a tenant requests a key change to stop tenants from working, indirect-double-indexing can be used to prevent bandwidth loss in tenants during adaptions for other tenants. When a tenant requests to manipulate the key-index table, the system will keep working. The current key index list will be duplicated. While the duplicated key-index list is manipulated according to the request, all tenants may still work on their current key-index tables until the request is complete. Once the request is complete, the tenant with the request will switch to the new table, while the old table is updated. Once the old table is updated, the tenant will switch to the updated table for continued work. No tenant, including the tenant that makes the request, continues working as the request is completed.
A data storage device and method for host-assisted deferred defragmentation and system handling are provided. In one embodiment, the data storage device comprises a memory and a controller. The controller is configured to receive, from a host, a plurality of write commands and a grouping identifier associated with the plurality of write commands, wherein the plurality of write commands comprise a plurality of non-sequential logical block addresses and a plurality of sequential segments of a file; and in response to the grouping identifier being associated with the plurality of write commands, execute the plurality of write commands by storing the plurality of sequential segments of the file sequentially in the memory even though the logical block addresses associated with the segments of the file are non-sequential. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. Machine learning modeling is used to reconstruct the data for the untested cylinders. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges. In a test mode, some portion of the cylinders is chosen for testing. Each wedge in the chosen cylinders is tested and labeled defective or non-defective. The test data for each defective wedge is run through a machine learning defect management logic, and inferences are made for the defective/non-defective status of the untested wedges.
G11B 19/04 - Dispositions prévenant, évitant ou signalant la surimpression sur le même support, ou d'autres fonctionnements défectueux de l'enregistrement ou de la reproduction
G11B 5/596 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'un disque
78.
MACHINE LEARNING DEFECT MANAGEMENT IN STORAGE DEVICES
Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. A bag of machine learning models is used to reconstruct the data for the untested cylinders. A defect file for the HDD is generated, a classifier model may be applied to the defect file, and one or more neural network models may be applied. If the defects are unsuitable for use by the models, then a scan of the entire HDD is run instead. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges.
The present disclosure generally relates to improved wait time notifications from SSDs to host systems. Rather than assuming on when to restart an SSD after an asynchronous event notification (AEN) is sent, issuing a cool-off wait time. When an SSD is overheating, an AEN is sent from the SSD. An AEN may either be a warning event or a critical event. Once the AEN is received, a host may issue a banner with a cool-off wait time. The cool-off wait time is a predetermined time that will begin if the SSD is not detected by host systems. A non-detectable SSD means that the SSD is in a thermal shut down mode, which is initiated by a PMIC. In the thermal shut down mode, the cool-off wait timer will begin at host side. After the time has elapsed the SSD can then be restarted either manually by user or automatically by host.
An AON module on a storage device periodically obtains the temperatures of the storage device and memory device. A controller uses the temperatures obtained by the AON module to determine a calculated temperature. The controller determines when the calculated temperature is above a thermal threshold and causes the storage device to enter the thermal sleep state where normal operations on the storage device are suspended. In the thermal sleep state, power to the AON module is maintained and the power to other components is modified. The AON module starts a cool-off timer and after a cool-off time expires, the AON module causes power to at least one component on the storage device to be turned on to determine whether the temperature of the storage device is below a first thermal throttling threshold and to cause the storage device to resume normal operations.
A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
G11B 5/725 - Revêtements protecteurs, p. ex. antistatiques contenant un lubrifiant
G11B 5/71 - Supports d'enregistrement caractérisés par l'emploi d'un matériau spécifié comportant une ou plusieurs couches de particules magnétisables mélangées de façon homogène avec un produit de liaison sur une couche de base caractérisés par le lubrifiant
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
A data storage device and method for dynamic controller memory buffer allocation are disclosed. In one embodiment, a data storage device is provided comprising a memory and a controller with a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; receive a request from the host to modify the size of the controller memory buffer during operation of the data storage device; and determine whether to grant the request to modify the size of the controller memory buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.
The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.
Systems and methods are disclosed for providing multi-channel capacitive sensors for detecting user gestures. In certain embodiments, a data storage device includes a non-volatile memory; a plurality of metal pieces configured to form one or more heat sinks of the data storage device and to form a plurality of capacitive pads of a capacitive sensor configured to detect a user gesture; and a controller configured to: detect a gesture of a user in proximity of the plurality of capacitive pads using the capacitive sensor; and perform a command associated with the data storage device based on the detected gesture.
A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.
G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
This disclosure a smart card device that provides a bus interface, such as a USB-C bus interface, printed on a portion of a PCB that forms a base layer of the smart card device. The smart card device can provide the bus interface without having to mount a traditional socket. By leveraging the portion of the PCB to provide a printed bus interface and excluding the traditional socket, the bus interface can be easily manufactured using well-known PCB manufacturing techniques while significantly reducing manufacturing costs. Furthermore, the smart card device can have a thickness that conforms to known card form factor standards, enabling the smart device to fit within a standard wallet. To enhance durability of the portion of the PCB from wear-and-tear, a metal core can be added to the PCB as an additional layer. The portion may also be reinforced with edge plating.
Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.
A process of assembling a voice coil motor (VCM), such as for a hard disk drive, includes creating an opening in a yoke, attaching a primary magnet to an inside surface of the yoke, installing through the opening in the yoke a cross-flux magnet into a channel of the primary magnet, and installing a plug into the opening in the yoke. Thus, part count is minimized and the manufacturing process is readily incorporated into existing VCM manufacturing processes.
A semiconductor device includes semiconductor dies formed with through silicon vias (TSVs). The TSVs are coupled to contact pads in a surface of the semiconductor die by coils forming inductance loops at a number of contact pads. These inductance loops serve to distribute the capacitance at each bond pad along transmission lines, which distribution of the capacitance allows for a marked increase in read/write bandwidth for the semiconductor die.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01F 17/00 - Inductances fixes du type pour signaux
Devices and methods to implement semantic searching on SSD through a computational SSD system that distributes computing to each NAND flash die of the SSD while the SSD controller handles the results aggregation with new on-die computation logic circuits to provide on device file semantic search are disclosed herein. The computational SSD system can read file feature vectors from multiple dies to the SSD controller, and if needed, these feature vectors may be buffered in DRAM and controller handles distance computing. Local, on-die AI/ML processing units may perform, for example, computation and comparison operations and pass the processing scores and results to the SSD controller. The SSD controller aggregates results from all dies and returns the result to the host. The feature vector store size, circuitry and number of on-die AI/ML processing units may be configured as needed to adapt to different tasks, system constraints, and/or feature vector sizes.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 16/11 - Administration des systèmes de fichiers, p. ex. détails de l’archivage ou d’instantanés
G06F 16/172 - Mise en cache, pré-extraction ou accumulation de fichiers
A data storage device includes a memory device and a controller coupled to the memory device. When a command is received by the controller from a host device, the controller determines whether the command size is greater than a threshold size. If the command is not greater than the threshold size, the command is sent to a first queue, otherwise, the command is sent to a second queue. Commands are executed from the first queue until a command size tracker value, which increases by a size representative of each command executed from the first queue, equals or exceeds a threshold value. When the command size tracker value equals or exceeds the threshold value, a command from the second queue is executed and the command size tracker value decreases by a size representative of the command from the second queue. Completion messages are sent at specific intervals based on the executing.
A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.
Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.
Disclosed herein are devices, systems, and methods that can improve the SNR of nanopore measurements by mitigating the effect of parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, a feedback circuit is used to inject a charge into the sense electrode to at least partially cancel the parasitic capacitance between the sense electrode and the counter electrode. In some embodiments, bootstrapping of a signal from the amplifier output or from the sense electrode is used to inject a charge on the counter electrode to substantially cancel the parasitic capacitance.
G01N 27/22 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la capacité
G01N 33/487 - Analyse physique de matériau biologique de matériau biologique liquide
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
A media playback device is configured to control access to a plurality of files. The media playback device includes memory configured to store a plurality of files, the plurality of files including at least a first set of files and a second set of files, the second set of files having a higher security level the first set of files. The media playback device also includes control circuitry that can be configured to receive a first login from a user, determine that the first login is associated with a user profile associated with the first set of files and the second set of files, provide access to the first set of files in response to validating the first login while keeping the second set of files locked, receive a second login, and provide access to the second set of files in response to validating the second login.
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
G06F 21/46 - Structures ou outils d’administration de l’authentification par la création de mots de passe ou la vérification de la solidité des mots de passe
A semiconductor device package includes a first substrate and receiving ports electrically connected to the first substrate. First semiconductor dies are electrically connected to and mounted directly on the first substrate. A second substrate is electrically connected to the first substrate via a corresponding receiving port and is oriented generally perpendicular to the first substrate. Second semiconductor dies are electrically connected to and mounted directly on the second substrate. A housing substantially encloses each of the above mentioned components. The receiving ports allow for additional substrates carrying semiconductor memory dies to be connected to the first substrate thereby increasing the total storage capacity of the semiconductor device package while conforming to a predefined form factor.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/04 - ConteneursScellements caractérisés par la forme
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/32 - Supports pour maintenir le dispositif complet pendant son fonctionnement, c.-à-d. éléments porteurs amovibles
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
Technology for a memory device having memory dies flip-chip bonded to one or more interposers that are mounted to a system board is disclosed. The memory device may be an SSD and the system board may be an M.2 board. A memory controller die may be bonded to one of the interposer boards. In one aspect, the memory controller die is flip-chip bonded to the interposer board. In one aspect, a heat sink is attached to a top surface of the flip-chip bonded controller die and to top surfaces of a group of the memory dies. Neither the memory dies nor the interposers are covered with a mold compound. Performance of the memory device is improved by, for example, lower inductance and improved heat dissipation.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
99.
DATA STORAGE DEVICE AND METHOD FOR SWAP DEFRAGMENTATION
A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.
Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The one or more processing devices are configured to generate a map of laser mode hop effects across the corresponding disk surface, for the selected head. The one or more processing devices are further configured to apply a laser mode hop mitigation in operating the selected head, based on the map of laser mode hop effects.
G11B 7/1263 - Commande de la puissance pendant la transduction, p. ex. par surveillance
G11B 5/588 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'une bande par commande de la position des têtes rotatives
