Western Digital Technologies, Inc.

United States of America

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IPC Class
G06F 3/06 - Digital input from, or digital output to, record carriers 400
G06F 12/02 - Addressing or allocationRelocation 184
G06F 12/00 - Accessing, addressing or allocating within memory systems or architectures 118
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens 99
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09 - Scientific and electric apparatus and instruments 163
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1.

Data Storage Device and Method for Identifying a Failing Area of Memory Based on a Cluster of Bit Errors

      
Application Number 18230982
Status Pending
Filing Date 2023-08-07
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Sharon, Eran
  • Linnen, Daniel J.
  • Tom, James
  • Yanuka, Nika
  • Eliash, Tomer
  • Thomson, Preston
  • Periyannan, Kirubakaran

Abstract

For bit errors caused by intrinsic cell variations, the bit errors are scattered across a page of memory. However, for bit errors caused by a physical issue in memory, the bit errors cluster together within the same memory area. In an example data storage device, a page of memory is divided into sections, and counters are used to count the number of errors in each section. A physical error location is detected if the number exceeds a parameter, and as compared to the number of errors in the other sections. In another example data storage device having an error correction code (ECC) engine, a histogram and binomial probability are used to detect physical errors. This has the advantage of detecting weak memory blocks that are about to fail, so the blocks can be retired early as a grown bad block.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens

2.

ADDRESS TRANSLATION SERVICE FOR HOST QUEUES

      
Application Number 18447813
Status Pending
Filing Date 2023-08-10
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor Benisty, Shay

Abstract

Instead of using address translation cache (ATC) to translate addresses for host queues, bypass the ATC and directly use translated addresses. When creating the submission queues (SQ) or completion queues (CQ), the controller receives the untranslated addresses from the host, and the device is responsible for translating the untranslated addresses before accessing the host queues. The host queue pointers will directly use the translated addresses while bypassing the ATC. When bypassing the ATC, different flows can be used such as create queue command flow and invalidate operations. In a create queue command flow, the firmware (FW) performs address translation by interacting with a translation agent (TA) to receive the translated addresses. With an invalidate flow, the controller scans all untranslated addresses provided by the host at the queue creation time and compares the untranslated addresses against the invalidated address.

IPC Classes  ?

  • G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
  • G06F 12/10 - Address translation

3.

FIVE LEVEL CELL PROGRAM ALGORITHM WITH APPENDED BIT LEVEL ERASE FOR ADDITIONAL THRESHOLD VOLTAGE BUDGET

      
Application Number 18232010
Status Pending
Filing Date 2023-08-09
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Wang, Ming
  • Li, Liang
  • Tian, Xuan

Abstract

A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and configured to store a threshold voltage. A control means is coupled to the plurality of word lines and is configured to apply at least one programming pulse of a program voltage to selected ones of the plurality of word lines during at least one programming loop of a programming operation. The control means is also configured to reduce the threshold voltage of the memory cells targeted for an erased state during a bit-level erase operation following the programming operation.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups

4.

Highly Textured 001 BiSb And Materials for Making Same

      
Application Number 18933330
Status Pending
Filing Date 2024-10-31
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Liu, Xiaoyong
  • Gribelyuk, Michael A.
  • Xu, Xiaoyu
  • Simmons, Randy G.
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

The present disclosure generally relates to spin-orbit torque (SOT) device comprising a first bismuth antimony (BiSb) layer having a (001) orientation. The SOT device comprises a first BiSb layer having a (001) orientation and a second BiSb layer having a (012) orientation. The first BiSb layer having a (001) orientation is formed by depositing an amorphous material selected from the group consisting of: B, Al, Si, SiN, Mg, Ti, Sc, V, Cr, Mn, Y, Zr, Nb, AlN, C, Ge, and combinations thereof, on a substrate, exposing the amorphous material to form an amorphous oxide surface on the amorphous material, and depositing the first BiSb layer on the amorphous oxide surface. By utilizing a first BiSb layer having a (001) orientation and a second BiSb having a (012) orientation, the signal through the SOT device is balanced and optimized to match through both the first and second BiSb layers.

IPC Classes  ?

  • H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • C23C 8/12 - Oxidising using elemental oxygen or ozone
  • C30B 29/52 - Alloys
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor
  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/85 - Materials of the active region
  • H10N 52/00 - Hall-effect devices
  • H10N 52/01 - Manufacture or treatment
  • H10N 52/80 - Constructional details

5.

WRITE AGGREGATION BASED ON NAND WEAR LEVEL

      
Application Number 18447806
Status Pending
Filing Date 2023-08-10
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

Instead of using programmable block size aggregation, a lower multiple of page, and down to a page size aggregation is used. A bad block prediction unit in a controller is able to predict when a programmable block has a bad page. The bad block prediction unit can lower the aggregation size of a programmable block by monitoring the life cycle of the programmable block through bad block statistic collection. When the accumulation size passes a threshold, the bad block prediction unit lowers the aggregation size. The bad block prediction unit can also predict when to lower aggregation size based on the number of reconstructions. An aggregate size level is set at a page boundary, and once the number of reconstructions reaches that page boundary, the bad block prediction unit lowers the aggregation size to page aggregation. The bad block prediction unit is able to predict both life cycle threshold changes and reconstructions changes.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

6.

NON-VOLATILE MEMORY WITH SUB-BLOCK MODE AND FULL BLOCK MODE

      
Application Number 18366572
Status Pending
Filing Date 2023-08-07
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Yuan, Jiahui
  • Chin, Henry
  • Chen, Changyuan

Abstract

A non-volatile memory is configured to transition blocks of non-volatile memory cells between full block mode and sub-block mode.

IPC Classes  ?

  • G11C 16/16 - Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
  • G11C 16/10 - Programming or data input circuits
  • G11C 16/20 - InitialisingData presetChip identification
  • G11C 16/28 - Sensing or reading circuitsData output circuits using differential sensing or reference cells, e.g. dummy cells

7.

STATE-DEPENDENT FAIL BIT COUNT CRITERIA FOR MEMORY APPARATUS PROGRAM PERFORMANCE GAIN

      
Application Number 18231368
Status Pending
Filing Date 2023-08-08
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Guo, Jiacen
  • Yang, Xiang
  • Chin, Henry

Abstract

A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and configured to retain a threshold voltage corresponding to data states. A control means applies verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines and counts the memory cells having the threshold voltage below each of the program verify voltages targeted for each of the memory cells being programmed during each of a plurality of verify loops of a program-verify operation. The control means terminates the plurality of verify loops for the memory cells targeted for one of the data states in response to the count of the memory cells exceeding a predetermined count threshold. The predetermined count threshold is different for at least one of the data states compared to other ones of the data states.

IPC Classes  ?

  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/08 - Address circuitsDecodersWord-line control circuits
  • G11C 16/10 - Programming or data input circuits

8.

Programmable Telemetry and Alerts for Storage Devices

      
Application Number 18366381
Status Pending
Filing Date 2023-08-07
First Publication Date 2025-02-13
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Mackey, Grant
  • Lamberts, Bernd
  • Bjorling, Matias

Abstract

A streaming data interface or a ‘telemetry tap’ in conjunction with a host defined telemetry program is used to regulate the type and amount of telemetry data sent to the host device. The amount of telemetry data provided to the host is based on a request. The controller will receive and execute valid host generated programs which define which telemetry operations should occur and be forwarded to the host via the streaming telemetry mechanism. The controller will use the user/host programmable mechanisms that will collaborate with internal drive logging mechanisms. The controller will watch for the host-defined programmable mechanisms and send the requested amount of telemetry data to the host once the programmable mechanisms have executed.

IPC Classes  ?

  • G06F 11/30 - Monitoring
  • G06F 11/32 - Monitoring with visual indication of the functioning of the machine

9.

EDGEROVER

      
Serial Number 99027065
Status Pending
Filing Date 2025-02-03
Owner Western Digital Technologies, Inc. ()
NICE Classes  ?
  • 09 - Scientific and electric apparatus and instruments
  • 42 - Scientific, technological and industrial services, research and design

Goods & Services

Downloadable and recorded computer software and mobile applications for aggregation of data and electronic media from distributed sources and datasets; downloadable and recorded computer software and mobile applications for the transmission and display of data and electronic media featuring collaboration and information sharing tools; downloadable and recorded computer software and mobile applications for the synchronization, back-up, and encryption and decryption of digital files; downloadable and recorded computer software and mobile applications for accessing media and data stored on distributed computer storage devices; downloadable and recorded computer software and mobile applications for encrypting data; downloadable and recorded computer software and mobile applications for managing data and data storage, for cloud-based network storage, and for use in accelerating the performance and scalability of computing platforms; none of the aforesaid relating to vehicles Providing non-downloadable computer software and mobile applications for aggregation of data and electronic media from distributed sources and datasets; Providing non-downloadable computer software and mobile applicationsfor the transmission and display of data and electronic media featuring collaboration and information sharing tools; Providing nondownloadable computer software and mobile applications for the synchronization, back-up, and encryption and decryption of digital files; Providing non-downloadable computer software and mobile applications for accessing media and data stored on distributed computer storage devices; Providing non-downloadable computer software and mobile applications for encrypting data; Providing nondownloadable computer software and mobile applications for managing data and data storage, for cloud-based network storage, and for use in accelerating the performance and scalability of computing platforms; none of the aforesaid relating to vehicles

10.

Topological Insulator Based Spin Torque Oscillator Reader

      
Application Number 18893605
Status Pending
Filing Date 2024-09-23
First Publication Date 2025-01-09
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Liu, Xiaoyong
  • Li, Zhanjie
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.

IPC Classes  ?

  • G11B 5/39 - Structure or manufacture of flux-sensitive heads using magneto-resistive devices
  • G11B 5/11 - Shielding of head against electric or magnetic fields

11.

Doping Process To Refine Grain Size For Smoother BiSb Film Surface

      
Application Number 18889747
Status Pending
Filing Date 2024-09-19
First Publication Date 2025-01-09
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Le, Quang
  • Hwang, Cherngye
  • York, Brian R.
  • Simmons, Randy G.
  • Liu, Xiaoyong
  • Ho, Kuok San
  • Takano, Hisashi
  • Gribelyuk, Michael A.
  • Xu, Xiaoyu

Abstract

The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.

IPC Classes  ?

  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/85 - Materials of the active region
  • H10N 52/00 - Hall-effect devices
  • H10N 52/01 - Manufacture or treatment
  • H10N 52/80 - Constructional details

12.

Dual Free Layer TMR Reader With Shaped Rear Bias and Methods of Forming Thereof

      
Application Number 18890207
Status Pending
Filing Date 2024-09-19
First Publication Date 2025-01-09
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Mao, Ming
  • Wang, Yung-Hung
  • Hu, Chih-Ching
  • Chien, Chen-Jung
  • Corona, Carlos
  • Yuan, Hongping
  • Jiang, Ming
  • Baião De Albuquerque, Goncalo Marcos

Abstract

The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.

IPC Classes  ?

  • G11B 5/11 - Shielding of head against electric or magnetic fields
  • G11B 5/265 - Structure or manufacture of a head with more than one gap for erasing, recording or reproducing on the same track

13.

NUCLEIC ACID SEQUENCING BY SYNTHESIS USING MAGNETIC SENSOR ARRAYS

      
Application Number 18888896
Status Pending
Filing Date 2024-09-18
First Publication Date 2025-01-09
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Astier, Yann
  • Braganca, Patrick
  • Topolancik, Juraj

Abstract

Methods of detecting molecules using an apparatus comprising a plurality of magnetic sensors are disclosed. A method may include binding a first molecule to a proximal wall of a fluid chamber of the apparatus, and adding, to the fluid chamber, a magnetically-labeled molecule comprising a cleavable magnetic label, wherein the magnetically-labeled molecule is configured to bind to or be incorporated by the first molecule. The method may use at least one address line and at least one selector element of the apparatus to detect a characteristic of at least a portion of the plurality of magnetic sensors, wherein the characteristic indicates whether the magnetically-labeled molecule has bound to or been incorporated by the first molecule.

IPC Classes  ?

  • B01L 3/00 - Containers or dishes for laboratory use, e.g. laboratory glasswareDroppers
  • C12Q 1/6869 - Methods for sequencing
  • G01N 27/08 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a liquid which is flowing continuously
  • G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
  • G01N 33/58 - Chemical analysis of biological material, e.g. blood, urineTesting involving biospecific ligand binding methodsImmunological testing involving labelled substances

14.

STORAGE POWER REDUCTION IN BATTERY-OPERATED DEVICES

      
Application Number US2024012247
Publication Number 2025/005999
Status In Force
Filing Date 2024-01-19
Publication Date 2025-01-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sharma, Amit
  • Agarwal, Dinesh Kumar
  • Venugopal, Abhinandan

Abstract

Techniques are provided for optimizing the power consumption of a data storage device included in a battery-operated device. The battery-operated device (e.g., portable devices like wearable devices, smartwatches, and mobile phones) can access certain data stored on the data storage device more frequently when the device operates on battery power as compared to when the device does not operate on battery power. Techniques are provided for identifying and classifying data into different classifications, for example, power sensitive data and non-power sensitive data. Then the device can optimize the battery power consumption of the data storage device by storing or relocating data stored at the data storage device based on the classification of the data.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication

15.

PHASE-COHERENT IN-LINE VCSEL ARRAY WITH SLIDER TRAILING MOUNT FOR HAMR

      
Application Number US2024012257
Publication Number 2025/006000
Status In Force
Filing Date 2024-01-19
Publication Date 2025-01-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Stipe, Barry C.

Abstract

The present disclosure relates to pretreating a magnetic recording head assembly for magnetic media drive. The magnetic recording head assembly comprises a slider having a media facing surface (MFS), a top surface disposed opposite the MFS, a trailing edge surface disposed adjacent to the top surface, and an optical grating disposed on the trailing edge surface. A vertical cavity surface emitting laser (VCSEL) device is mounted to the trailing edge surface of the slider. The VCSEL device is aligned with the optical grating. A magnetic recording head comprising a waveguide and a near field transducer (NFT) coupled to the waveguide is disposed on the trailing edge surface of the slider. The VCSEL device is capable of emitting a plurality of lasers that are phase coherent on to the optical grating. The optical grating is capable of directing the emitted lasers about 90 degrees to the waveguide.

IPC Classes  ?

  • G11B 13/08 - Recording simultaneously or selectively by methods or means covered by different main groupsRecord carriers thereforReproducing simultaneously or selectively therefrom using near-field interactions or transducing means and at least one other method or means for recording or reproducing
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor

16.

NEAR-FIELD TRANSDUCER FOR HEAT ASSISTED MAGNETIC RECORDING COMPRISING OF THERMALLY STABLE MATERIAL LAYER

      
Application Number US2024012457
Publication Number 2025/006002
Status In Force
Filing Date 2024-01-22
Publication Date 2025-01-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Matsumoto, Takuya
  • Balamane, Mr. Hamid

Abstract

The present disclosure generally relates to a magnetic recording head for a magnetic media drive. The magnetic recording head comprises a main pole, a waveguide disposed adjacent to the main pole, a near field transducer (NFT) coupled between the main pole and the waveguide at a media facing surface (MFS), a thermal shunt disposed on the NFT, the thermal shunt being recessed from the MFS, and a stable material disposed on the NFT at the MFS. In some embodiments, the stable material is wedge-shaped or triangular-shaped. In another embodiment, the stable material comprises a first portion and a second portion, where the first and second portions may each by linear, or where the first portion is triangular-shaped and the second portion is square-shaped. The stable material may be in contact with the thermal shunt, or spaced from the thermal shunt.

IPC Classes  ?

  • G11B 13/08 - Recording simultaneously or selectively by methods or means covered by different main groupsRecord carriers thereforReproducing simultaneously or selectively therefrom using near-field interactions or transducing means and at least one other method or means for recording or reproducing
  • G11B 5/73 - Base layers
  • G11B 5/31 - Structure or manufacture of heads, e.g. inductive using thin film
  • G11B 5/00 - Recording by magnetisation or demagnetisation of a record carrierReproducing by magnetic meansRecord carriers therefor

17.

MAGNETIC CONTROL OF MOLECULE TRANSLOCATION SPEED THROUGH A NANOPORE

      
Application Number US2024012179
Publication Number 2024/263212
Status In Force
Filing Date 2024-01-19
Publication Date 2024-12-26
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Kinney, Justin P.
  • Bedau, Daniel

Abstract

A system for controlling a translocation speed of a molecule through a nanopore may include a fluid chamber containing a solution with a magnetic susceptibility that is different from the magnetic susceptibility of the molecule, a nanopore situated in the fluid chamber, and at least one magnetic component configured to create a magnetic field gradient within the solution to control the translocation speed of a molecule through the nanopore. A system for controlling a translocation speed of a molecule through a nanopore may include a nanopore at least one magnetic component situated to create a magnetic field that causes the molecule to experience a rotational torque as it passes through the nanopore.

IPC Classes  ?

  • G01N 33/487 - Physical analysis of biological material of liquid biological material

18.

SPIN ORBITAL SQUARED (SO-SO) LOGIC

      
Application Number US2024033621
Publication Number 2024/258973
Status In Force
Filing Date 2024-06-12
Publication Date 2024-12-19
Owner
  • WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
  • TOKYO INSTITUTE OF TECHNOLOGY (Japan)
Inventor
  • Le, Quang
  • Liu, Xiaoyong
  • York, Brian R.
  • Hwang, Cherngye
  • Takano, Hisashi
  • Pham, Nam Hai

Abstract

The present disclosure generally relate to an integrated circuit utilizing spin orbital-spin orbital (SO-SO) logic. The integrated circuit comprises a plurality of SO-SO logic cells, where each SO-SO logic cell comprises a first spin orbit torque (SOT1 ) layer, a second spin orbit torque (SOT2) layer, and a ferromagnetic layer disposed between the SOT1 and SOT2 layer. Each SO-SO logic cell is configured for: a first current path that is in plane to a plane of the SOT1 layer, and a second current path that is perpendicular to a plane of the SOT2 layer, the second current path being configured to extend into the ferromagnetic layer. The integrated circuit further comprises a common voltage source connected to each SOT device, and one or more interconnects disposed between adjacent SOT devices of the plurality of SOT devices, the one or more interconnects connecting the adjacent SOT devices together.

IPC Classes  ?

  • H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
  • H10N 52/00 - Hall-effect devices
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect

19.

HIGHLY TEXTURED BUFFER LAYER TO GROW YBIPT (110) FOR SPINTRONIC APPLICATIONS

      
Application Number US2024033620
Publication Number 2024/258972
Status In Force
Filing Date 2024-06-12
Publication Date 2024-12-19
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Le, Quang
  • York, Brian R.
  • Banh, Sharon Swee Ling
  • Osman, Hassan
  • Takano, Hisashi

Abstract

3232233333 (100), YPt (110), NiFeGeN, NiAIN, NiAl, NiFeGe, NiAIGe, or HfN, and a ferromagnetic layer.

IPC Classes  ?

  • H10N 50/00 - Galvanomagnetic devices
  • H10N 50/20 - Spin-polarised current-controlled devices
  • H01F 10/32 - Spin-exchange-coupled multilayers, e.g. nanostructured superlattices

20.

ASSIST CORES FOR SPOT SIZE CONVERTER FOR HEAT ASSISTED MAGNETIC RECORDING

      
Application Number US2024011519
Publication Number 2024/253714
Status In Force
Filing Date 2024-01-13
Publication Date 2024-12-12
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Shi, Norman Nan
  • Matsumoto, Takuya
  • Stipe, Barry C.

Abstract

Spot size converter (SSC) in a HAMR magnetic recording head assembly have a plurality of split assist core structures. Each split assist core structure includes multiple assist cores and a main waveguide. Each split core may also include one or more side waveguides such that the main waveguide is sandwiched between the side waveguides and top and bottom assist cores. Adjacent split assist core structures, may share assist cores. The split assist core structures reduce light source power utilized to write data to magnetic media.

IPC Classes  ?

  • G11B 13/04 - Recording simultaneously or selectively by methods or means covered by different main groupsRecord carriers thereforReproducing simultaneously or selectively therefrom magnetically and optically
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/31 - Structure or manufacture of heads, e.g. inductive using thin film

21.

FILM AND METHOD FOR BISBX (012) TEXTURE FOR SOT DEVICES

      
Application Number US2024011521
Publication Number 2024/253715
Status In Force
Filing Date 2024-01-13
Publication Date 2024-12-12
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Liu, Xiaoyong
  • Gribelyuk, Michael A.
  • Le, Son T.
  • Takano, Mr. Hisashi

Abstract

The present disclosure generally relates to spin-orbit torque (SOT) device comprising a bismuth antimony (BiSb) layer. The SOT device comprises a seed layer and a BiSb layer having a (012) orientation. The seed layer comprises at least one of an amorphous/nanocrystalline material with a nearest neighbor x-ray diffraction peak with a d-spacing in the range of about 2.02 Å to about 2.20 Å; a polycrystalline material having a (111) orientation and an a-axis of about 3.53 Å to about 3.81 Å; and a polycrystalline material having a cubic (100) or tetragonal (001) orientation and an a-axis of about 4.1 Å to about 4.7 Å. When the seed layer comprises an amorphous material or a polycrystalline material having a (111), the BiSb layer is doped, and the seed layer has a lower a/c ratio than when the seed layer comprises polycrystalline material having a cubic (100) or tetragonal (001) orientation.

IPC Classes  ?

  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/85 - Materials of the active region
  • H10N 50/01 - Manufacture or treatment
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
  • G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

22.

DISAGGREGATED MEMORY MANAGEMENT

      
Application Number US2024010727
Publication Number 2024/242724
Status In Force
Filing Date 2024-01-08
Publication Date 2024-11-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Radi, Marjan
  • Vucinic, Dejan

Abstract

A server includes at least one local memory and communicates with one or more network devices that provide an external shared memory. A kernel space of the server is used to monitor memory usage by different applications executed by the server. A memory kernel module adjusts usage of the at least one local memory and the external shared memory by the different applications based at least in part on the monitored memory usage. In another aspect, a memory access profiling server receives memory information and application usage information added to packets sent between servers and one or more memory devices. The memory access profiling server analyzes the memory information and application usage information to determine memory placement information that is sent to at least one server to adjust usage of the external shared memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

23.

SUB-BLOCK MODE (SBM) PRE-CHARGE OPERATION SEQUENCES

      
Application Number 18356712
Status Pending
Filing Date 2023-07-21
First Publication Date 2024-11-21
Owner WesternDigital Technologies, Inc. (USA)
Inventor
  • S., Gopu
  • Panakkal, Binoy Jose

Abstract

Embodiments of the disclosed technology relate to the operation of memory devices, and more particularly to sub-block mode (SBM) pre-charge operation sequences. One example embodiment provides a novel logic design of the control circuitry of a memory device using comments/instructions for the control circuitry. By virtue of the features of the disclosed technology, the control circuitry can effect pre-charging of an inner or middle vertical sub-block of a NAND string in a memory array. In some examples the NAND string has at least three vertical sub-blocks of non-volatile memory cells.

IPC Classes  ?

  • G11C 16/08 - Address circuitsDecodersWord-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/24 - Bit-line control circuits

24.

THREE-DIMENSIONAL MEMORY DEVICE WITH LAYER CONTACT VIA STRUCTURES LOCATED IN A MEMORY ARRAY REGION AND METHODS OF FORMING THE SAME

      
Application Number 18233759
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-11-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Iwai, Takaaki
  • Totoki, Yuji
  • Izumi, Keisuke

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory openings vertically extending through the alternating stack, memory-opening-free areas located in the array of the memory openings in a plan view, an array of memory opening fill structures located in the array of memory openings, and layer contact assemblies located within the memory-opening-free areas in the plan view. Each of the memory opening fill structures includes a respective vertical semiconductor channel and respective memory elements located at levels of the electrically conductive layers. Each of the layer contact assemblies includes a respective layer contact via structure contacting a respective one of the electrically conductive layers, and a respective insulating spacer that laterally surrounds the respective layer contact via structure.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

25.

SHOCK ABSORBER ASSEMBLY FOR A PRINTED CIRCUIT BOARD

      
Application Number 18357759
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-11-14
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Kim, Myungjin
  • Chan, Fu Xing
  • Lau, Chun Sean
  • Fong, Lihwa

Abstract

A shock absorber for a printed circuit board (PCB) includes a first portion and a second portion. The first portion is positioned on a first side of the PCB at or near a connector that extends from the PCB. The second portion is positioned on a second side of the PCB, opposite the first portion. The first and second portions prevent the PCB from moving when the PCB is coupled to a host device. As the PCB is subjected to various movements, strains and stresses, the shock absorber prevents the PCB from cracking or breaking, especially at or near the connector, which is susceptible to cracking and breaking.

IPC Classes  ?

  • H05K 1/02 - Printed circuits Details
  • H05K 1/18 - Printed circuits structurally associated with non-printed electric components

26.

DATA STORAGE DEVICE AND METHOD FOR USING A DYNAMIC FLOATING FLASH REGION TO SECURE A FIRMWARE UPDATE

      
Application Number US2024010596
Publication Number 2024/232954
Status In Force
Filing Date 2024-01-06
Publication Date 2024-11-14
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Jayachandran, Anusuya
  • Veluswamy, Senthil Kumar

Abstract

A data storage device and method are provided for using a dynamic floating flash region to secure a firmware update. In one embodiment, a data storage device is provided comprising a first non-volatile memory, a second non-volatile memory, and a controller. The controller is configured to communicate with the first and second non-volatile memories and further configured to: determine addresses in the second non-volatile memory to store portions of a firmware update, wherein the addresses are determined on-the-fly as opposed to being predetermined; and store the portion of the firmware update in the addresses in the second non-volatile memory. Other embodiments are provided.

IPC Classes  ?

  • G06F 8/65 - Updates
  • G06F 8/71 - Version control Configuration management
  • G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
  • G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
  • G06F 21/62 - Protecting access to data via a platform, e.g. using keys or access control rules
  • G06F 13/42 - Bus transfer protocol, e.g. handshakeSynchronisation
  • G06F 12/02 - Addressing or allocationRelocation

27.

STORAGE DEVICE CARRIER AND LATCHING MECHANISM

      
Application Number 18225652
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-11-07
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Patterson, Scott R.
  • Altermatt, Andrew
  • Wilke, Jeffrey D.

Abstract

A device carrier mechanism configured for attachment to an electronic device such as a hard disk drive includes a pair of rotatable handles interlocked at a common first pivot at a proximal end of each handle and a respective second pivot at a distal end, a pair of pin mechanisms each coupled at the second pivot of a respective handle and having a protruding latch pin, and a frame with which each pin mechanism is translatably coupled. Such a linkage system operates as an over-center mechanism, in a device handling state responsive to an upward handling force and with the latch pins in a retracted position within the frame, a neutral state with the latch pins in an extended position extending external to the frame, and a locked over-center state with the latch pins clamped in the extended position for locking into a data storage system.

IPC Classes  ?

  • H05K 7/14 - Mounting supporting structure in casing or on frame or rack
  • G11B 33/02 - CabinetsCasesStandsDisposition of apparatus therein or thereon

28.

USE OF COMMON HEAD SLIDER FOR DIFFERENT RPM HARD DISK DRIVES

      
Application Number 18226217
Status Pending
Filing Date 2023-07-25
First Publication Date 2024-11-07
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Liu, Yanning
  • Sun, Biao

Abstract

A method of manufacturing hard disk drives (HDDs) includes assembling a first HDD including a first slider having a first air bearing surface (ABS) configuration, configuring the first HDD to rotate its disk media at a first revolutions-per-minute (RPM), and sealing the first HDD with a first internal pressure level. Continuing, the method includes assembling a second HDD including a second head slider having the same first ABS configuration, configuring the second HDD to rotate its disk media at a second RPM that is lower than the first RPM, and sealing the second HDD with a second internal pressure level that is higher than the first pressure level. Thus, in the context of using a common slider among different RPM drives, a higher internal pressure for the lower RPM drive can compensate for loss in fly height that might otherwise occur due to the lower operational RPM.

IPC Classes  ?

  • G11B 5/60 - Fluid-dynamic spacing of heads from record carriers
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

29.

MULTIPLE SECURITY RANGE COMMANDS

      
Application Number 18357743
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-11-07
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

Improved automation can be achieved using command-parts. Rather than using a command to determine which key to use, command partitioning will generate a task-ID based on a key index table to determine what key to use. Based on the task-ID, an encryption engine (XTS) will know which key to use. The command is split into partitions with the same attributes. The amount of task-IDs created will equal the amount of partitions. Automation will be based on the task-IDs to create a completion for a host. The controller will then return to the key index table to count the completed commands and send the completion to the host.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

30.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PERIPHERAL CIRCUIT WITH FIN AND PLANAR FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THEREOF

      
Application Number 18361550
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Mayuzumi, Satoru
  • Narayanan, Sudarshan
  • Dunga, Mohan

Abstract

A semiconductor structure includes a logic die containing a word line switching circuit containing a fin field effect transistor having at least one semiconductor fin, and a planar field effect transistor, and a memory die containing a three-dimensional memory device bonded to the logic die.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region

31.

CROSS-POINT MAGNETORESISTIVE MEMORY ARRAY CONTAINING CARBON-BASED LAYER AND METHOD OF MAKING THE SAME

      
Application Number 18363542
Status Pending
Filing Date 2023-08-01
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Lille, Jeffrey
  • Katine, Jordan
  • Santos, Tiffany

Abstract

A device structure includes first electrically conductive lines that are laterally spaced apart from each other, second electrically conductive lines that are vertically spaced apart from the first electrically conductive lines and are laterally spaced apart from each other, a two-dimensional array of magnetoresistive random access memory (MRAM) pillars located between the first electrically conductive lines and the second electrically conductive lines, and each of the MRAM pillars includes a respective reference layer, a respective nonmagnetic tunnel barrier layer, and a respective free layer, and a two-dimensional array of carbon-based layers contacting surfaces of the first electrically conductive lines and surfaces of the two-dimensional array of MRAM pillars.

IPC Classes  ?

  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

32.

THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

      
Application Number 18455988
Status Pending
Filing Date 2023-08-25
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Dunga, Mohan
  • Matsuno, Koichi

Abstract

A memory device includes an alternating stack of insulating layers and electrically conductive layers containing stepped surfaces in a contact region, a first stepped dielectric material portion overlying the stepped surfaces of the alternating stack, a memory opening vertically extending at least through each layer within the alternating stack, a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel, and a bundled contact via structure vertically extending through the first stepped dielectric material portion and through a plurality of bottommost electrically conductive layers of the electrically conductive layers, and laterally contacting each of the plurality of the bottommost electrically conductive layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

33.

STORAGE DEVICE CARRIER AND LATCHING MECHANISM

      
Application Number US2023084605
Publication Number 2024/228751
Status In Force
Filing Date 2023-12-18
Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Patterson, Scott R.
  • Altermatt, Andrew
  • Wilke, Jeffrey D.

Abstract

A device carrier mechanism configured for attachment to an electronic device such as a hard disk drive includes a pair of rotatable handles interlocked at a common first pivot at a proximal end of each handle and a respective second pivot at a distal end, a pair of pin mechanisms each coupled at the second pivot of a respective handle and having a protruding latch pin, and a frame with which each pin mechanism is translatably coupled. Such a linkage system operates as an over-center mechanism, in a device handling state responsive to an upward handling force and with the latch pins in a retracted position within the frame, a neutral state with the latch pins in an extended position extending external to the frame, and a locked over-center state with the latch pins clamped in the extended position for locking into a data storage system.

IPC Classes  ?

  • G11B 23/03 - Containers for flat record carriers
  • G11B 23/04 - MagazinesCassettes
  • G11B 33/04 - CabinetsCasesStandsDisposition of apparatus therein or thereon modified to store record carriers

34.

ASYMMETRIC VREADK TO REDUCE NEIGHBORING WORD LINE INTERFERENCE IN A MEMORY DEVICE

      
Application Number 18228795
Status Pending
Filing Date 2023-08-01
First Publication Date 2024-11-07
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Zhao, Dengtao
  • Yang, Xiang
  • Zhang, Peng

Abstract

The memory device includes a memory block with a plurality of memory cells that are arranged in a plurality of word lines. The plurality of word lines include a selected word line, a pair of neighboring word lines that are immediately adjacent the selected word line, and a plurality of non-neighboring word lines that are not immediately adjacent the selected word line. Circuitry can perform a sensing operation on at least one memory cell in the selected word line. During the sensing operation, the circuitry is configured to apply a reference voltage to the selected word line, apply different first and second pass voltages to the neighboring word lines, and apply a third pass voltage that is different than the first and second pass voltages to the plurality of non-neighboring word lines. The circuitry is further configured to sense a threshold voltage of the at least one memory cell.

IPC Classes  ?

  • G11C 16/08 - Address circuitsDecodersWord-line control circuits
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C 16/26 - Sensing or reading circuitsData output circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

35.

RECLAIM PACKAGE CACHE FOR THERMAL THROTTLING

      
Application Number 18237096
Status Pending
Filing Date 2023-08-23
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Dua, Udita
  • Bordia, Kalpit

Abstract

A storage device is communicatively coupled to a host that stores data on a primary memory package on the storage device. A controller on the storage device may monitor the temperature of components on the storage device and determine when the temperature exceeds a thermal temperature limit. When the temperature exceeds a thermal temperature limit, the controller may suspend certain operations on the primary memory package and write host data to the secondary memory package on the storage device. The controller may continue to monitor the temperature on the storage device, determine when the temperature on the storage device returns to an acceptable level, transfer data from the secondary memory package to the primary memory package, and resume writing host data to primary memory package.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

36.

METHOD FOR OPTIMIZING LOGICAL-TO-PHYSICAL TABLE UPDATES FOR FIXED GRANULARITY LOGICAL-TO-PHYSICAL TABLES

      
Application Number 18237301
Status Pending
Filing Date 2023-08-23
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Bordia, Kalpit

Abstract

Performance on a storage device may be improved when executing a write command with sequential host data. The storage device optimizes logical-to-physical table updates for fixed granularity logical-to-physical tables that are populated when writing the sequential host data. A host interface module on the storage device may receive, from a host, a command to store the host data on a memory device and classify the host data as sequential host data or random host data. A flash translation layer on the storage device predetermines open contiguous blocks on the memory device where the sequential host data is to be written and provides a beginning address of the open contiguous blocks to the host interface module. The host interface module populates an address translation table with logical-to-physical mappings starting at the beginning address with an appropriate offset. Each entry in the address translation table corresponds to a fixed granularity.

IPC Classes  ?

37.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING TRENCH SUPPORT BRIDGE STRUCTURES AND METHODS FOR MANUFACTURING THE SAME

      
Application Number 18357781
Status Pending
Filing Date 2023-07-24
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Matsuno, Koichi
  • Alsmeier, Johann

Abstract

A memory device includes layer stacks, each including a respective alternating stack of respective insulating layers and respective electrically conductive layers and a respective contact-level dielectric layer, memory openings vertically extending through a respective one of the alternating stacks. memory opening fill structures located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and dielectric bridges structures located within access trenches that laterally separate the layer stacks. Each of the dielectric bridge structures includes a respective pair of contoured sidewalls. Each contoured sidewall of the dielectric bridge structures includes at least two vertically-straight and horizontally-convex surface segments that are adjoined by a vertically-extending edge. Access trench fill structures are located in the access trenches and each access trench fill structure embed a respective subset of the dielectric bridge structures.

IPC Classes  ?

  • H01L 23/00 - Details of semiconductor or other solid state devices
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

38.

THREE-DIMENSIONAL MEMORY DEVICE AND METHOD OF MAKING THEREOF USING ION IMPLANTED ETCH STOP LAYER ON A SACRIFICIAL FILL MATERIAL

      
Application Number 18361594
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Zhou, Bing
  • Kanakamedala, Senaka
  • Makala, Raghuveer S.

Abstract

A method includes forming a first alternating stack of first insulating layers and first sacrificial material layers over a substrate, forming a first in-process inter-tier dielectric layer over the first alternating stack, forming a first memory opening through the first in-process inter-tier dielectric layer and the first alternating stack, forming a sacrificial memory opening fill structure in the first memory opening, doping an upper portion of the sacrificial memory opening fill structure with atoms of at least one dopant species, forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack, forming a second memory opening through the second alternating stack by performing an anisotropic etch process, and removing the sacrificial memory opening fill structure.

IPC Classes  ?

  • H01L 23/528 - Layout of the interconnection structure
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

39.

THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME

      
Application Number 18361629
Status Pending
Filing Date 2023-07-28
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Matsuno, Koichi
  • Alsmeier, Johann

Abstract

A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first dielectric material portion overlying first stepped surfaces of the first alternating stack, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a first contact via structure vertically extending through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.

IPC Classes  ?

  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout

40.

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING PERIPHERAL CIRCUIT WITH FIN FIELD EFFECT TRANSISTORS AND METHOD OF MAKING THE SAME

      
Application Number 18396150
Status Pending
Filing Date 2023-12-26
First Publication Date 2024-11-07
Owner WESTERN DIGITAL TECHNOLOGIES, INC., (USA)
Inventor
  • Kagawa, Ryo
  • Kodate, Hokuto
  • Yoshizawa, Kazutaka
  • Karumuri, Sriharsha
  • Abe, Tomohisa
  • Mayuzumi, Satoru

Abstract

A semiconductor structure includes a memory die including a three-dimensional memory device, and a logic die bonded to the memory die. The logic die includes a word line switching circuit containing a fin field effect transistor including a semiconductor fin and a first gate dielectric having a first gate dielectric thickness, and further includes a first additional field effect transistor including a second gate dielectric having a second gate dielectric thickness that is different from the first gate dielectric thickness.

IPC Classes  ?

  • H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 29/66 - Types of semiconductor device
  • H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
  • H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
  • H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
  • H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
  • H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
  • H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
  • H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

41.

DETECTION OF DATA STORAGE DEVICE REMOVAL

      
Application Number US2023084700
Publication Number 2024/220115
Status In Force
Filing Date 2023-12-18
Publication Date 2024-10-24
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hodes, Avichay
  • Inbar, Karin
  • Bazarsky, Alexander

Abstract

Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.

IPC Classes  ?

  • G11B 33/12 - Disposition of constructional parts in the apparatus, e.g. of power supply, of modules
  • G11B 33/10 - Indicating arrangementsWarning arrangements
  • G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor
  • G11B 7/004 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor

42.

SYSTEM AND METHOD FOR FLEXIBLE EMERGENCY POWER FAIL MANAGEMENT FOR MULTIPLE PERSISTENT MEMORY REGIONS

      
Application Number US2024012470
Publication Number 2024/205695
Status In Force
Filing Date 2024-01-22
Publication Date 2024-10-03
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Navon, Ariel
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel

Abstract

A system and method are disclosed for flexible emergency power fail management for multiple persistent memory regions. In one embodiment, a method is provided that is performed in a host in communication with a plurality of data storage devices, each data storage device having a persistent memory region, wherein the host comprises a capacitor shared by the plurality of data storage devices. The method comprises determining an allocation of power from the capacitor to each of the plurality of data storage devices; and dynamically changing the allocation of power from the capacitor to at least one data storage device of the plurality of data storage devices. Other embodiments are disclosed.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 1/30 - Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations

43.

CAPACITOR HEALTH CHECK FOR DATA STORAGE DEVICES

      
Application Number US2024010747
Publication Number 2024/196455
Status In Force
Filing Date 2024-01-08
Publication Date 2024-09-26
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Trichy, Narasimhan
  • Prosory, Andrew

Abstract

A data storage device includes a non-volatile memory device, a capacitor bank, and a power regulator electrically coupled to the capacitor bank and configured to provide power to the non-volatile memory device. The data storage device further includes a controller configured to discharge the capacitor bank from a first voltage to a second voltage at a first constant current and determine a first discharge time. controller is further configured to discharge the capacitor bank from the first voltage to the second voltage at a second constant current and determine a second discharge time. A voltage holdup time of the capacitor bank is then determined based on at least the first discharge time and the second discharge time.

IPC Classes  ?

  • G01R 31/64 - Testing of capacitors
  • G01R 27/02 - Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
  • G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
  • G01R 19/12 - Measuring rate of change
  • G01R 31/52 - Testing for short-circuits, leakage current or ground faults

44.

LOW POWER OPTIMIZATION BASED UPON HOST EXIT LATENCY

      
Application Number US2024011408
Publication Number 2024/196458
Status In Force
Filing Date 2024-01-12
Publication Date 2024-09-26
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Elmaleh, Nissim
  • Segev, Amir
  • Benisty, Shay

Abstract

There is a tradeoff between the amount of power consumption decreased and the latency needed to return a data storage device back to an operational power mode. When the data storage device receives a wake up indication from a host device, a controller of the data storage device initiates a counter in order to determine a host exit latency. Based on the host exit latency, the controller determines a group of low power state entrance actions from a plurality of groups to perform during a next entrance into a firmware active idle state based on an associated completion wake up time and the host exit latency. The controller selects the group whose completion wake up time is closest to the host exit latency and less than or equal to the host exit latency. The controller performs the selected groups low power state entrance actions during a next entrance into the firmware active idle state.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

45.

PROTOCOL FOR SOLID STATE DRIVE WITH HIGH QUALITY OF SERVICE

      
Application Number US2024011425
Publication Number 2024/191501
Status In Force
Filing Date 2024-01-12
Publication Date 2024-09-19
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Yang, Niles

Abstract

A storage device is communicatively coupled to a host that defines a quality of service level for responses transmitted from the storage device to the host. The storage device includes a memory device to store data. The storage device also includes a controller to perform background operations to manage resources on the memory device while performing foreground operations according to the quality of service level set by the host. The controller generates a free block file including information on free blocks in the memory device and transmits the free block file to the host. The host uses the free block file to determine when the memory device is at or near a critical level of block availability and transmits an indication from to the controller. The controller adjusts the priority of the background operations in response to receipt of the indication to maintain the quality of service level.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

46.

NON-VOLATILE MEMORY WITH INTELLIGENT ERASE TESTING TO AVOID NEIGHBOR PLANE DISTURB

      
Application Number US2023086544
Publication Number 2024/191493
Status In Force
Filing Date 2023-12-29
Publication Date 2024-09-19
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Li, Liang
  • Yi, Dandan
  • Lee, Dana

Abstract

A non-volatile memory system is configured to perform a multiplane erase process that concurrently erases groups of memory cells in multiple planes. Based on that multiplane erase process, the memory system determines that a first group of memory cells in a first plane of the multiple planes is slow to erase. As a result, the system will perform one or more multiplane erase processes for the groups of memory cells in multiple planes without erasing the first group of memory cells in the first plane as part of the multiplane erase process(es).

IPC Classes  ?

  • G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

47.

Electronic device

      
Application Number 29794408
Grant Number D1042445
Status In Force
Filing Date 2021-06-11
First Publication Date 2024-09-17
Grant Date 2024-09-17
Owner Westem Digital Technologies, Inc. (USA)
Inventor
  • Peng, Steven Tzu-Yen
  • Vanderpol, Gregory A.
  • Sterzick, Mark F.

48.

DATA STORAGE DEVICE AND METHOD FOR HOST-ASSISTED EFFICIENT HANDLING OF MULTIPLE VERSIONS OF DATA

      
Application Number US2023084858
Publication Number 2024/186372
Status In Force
Filing Date 2023-12-19
Publication Date 2024-09-12
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Agarwal, Dinesh Kumar
  • Sharma, Amit

Abstract

A data storage device and method for host-assisted efficient handling of multiple versions of data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive, from a host, identification of different versions of data that are to deleted together; store the different versions of the data in areas of the memory that are erasable in parallel; receive, from the host, a command to erase the different versions of the data; and erase the different versions of the data in parallel. Other embodiments are provided.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

49.

DATA STORAGE DEVICE AND METHOD FOR ENHANCED RECOVERY THROUGH A HARDWARE RESET OF ONE OF ITS DISCRETE COMPONENTS

      
Application Number US2023084877
Publication Number 2024/186373
Status In Force
Filing Date 2023-12-19
Publication Date 2024-09-12
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Inbar, Karin
  • Hodes, Avichay
  • Bazarsky, Alexander

Abstract

A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

50.

KEY-PER-IO MULTIPLE TENANT ISOLATION

      
Application Number US2023083666
Publication Number 2024/163065
Status In Force
Filing Date 2023-12-12
Publication Date 2024-08-08
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay

Abstract

The present disclosure generally relates improved key-per IO (KIPO) processing for multiple tenants. Rather than when a tenant requests a key change to stop tenants from working, indirect-double-indexing can be used to prevent bandwidth loss in tenants during adaptions for other tenants. When a tenant requests to manipulate the key-index table, the system will keep working. The current key index list will be duplicated. While the duplicated key-index list is manipulated according to the request, all tenants may still work on their current key-index tables until the request is complete. Once the request is complete, the tenant with the request will switch to the new table, while the old table is updated. Once the old table is updated, the tenant will switch to the updated table for continued work. No tenant, including the tenant that makes the request, continues working as the request is completed.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

51.

DATA STORAGE DEVICE AND METHOD FOR HOST-ASSISTED DEFERRED DEFRAGMENTATION AND SYSTEM HANDLING

      
Application Number US2023083673
Publication Number 2024/163066
Status In Force
Filing Date 2023-12-12
Publication Date 2024-08-08
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Muthiah, Ramanathan
  • Ramamurthy, Ramkumar
  • Krishna, Bhavya

Abstract

A data storage device and method for host-assisted deferred defragmentation and system handling are provided. In one embodiment, the data storage device comprises a memory and a controller. The controller is configured to receive, from a host, a plurality of write commands and a grouping identifier associated with the plurality of write commands, wherein the plurality of write commands comprise a plurality of non-sequential logical block addresses and a plurality of sequential segments of a file; and in response to the grouping identifier being associated with the plurality of write commands, execute the plurality of write commands by storing the plurality of sequential segments of the file sequentially in the memory even though the logical block addresses associated with the segments of the file are non-sequential. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/02 - Addressing or allocationRelocation

52.

MACHINE LEARNING DEFECT MANAGEMENT IN STORAGE DEVICES

      
Application Number 18449278
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-08-01
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Giri, Saket
  • Gupta, Anand Lallan
  • Lloyd, Jonathan
  • Chattopadhyay, Amit

Abstract

Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. Machine learning modeling is used to reconstruct the data for the untested cylinders. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges. In a test mode, some portion of the cylinders is chosen for testing. Each wedge in the chosen cylinders is tested and labeled defective or non-defective. The test data for each defective wedge is run through a machine learning defect management logic, and inferences are made for the defective/non-defective status of the untested wedges.

IPC Classes  ?

  • G11B 19/04 - Arrangements for preventing, inhibiting, or warning against, double recording on the same blank, or against other recording or reproducing malfunctions

53.

MACHINE LEARNING DEFECT MANAGEMENT IN STORAGE DEVICES

      
Application Number 18449480
Status Pending
Filing Date 2023-08-14
First Publication Date 2024-08-01
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Giri, Saket
  • Gupta, Anand Lallan
  • Lloyd, Jonathan
  • Chattopadhyay, Amit

Abstract

Methods are provided for managing defects in Hard Disk Drive (HDD) storage devices. In particular, only a portion of the cylinders of an HDD is tested. A bag of machine learning models is used to reconstruct the data for the untested cylinders. A defect file for the HDD is generated, a classifier model may be applied to the defect file, and one or more neural network models may be applied. If the defects are unsuitable for use by the models, then a scan of the entire HDD is run instead. An HDD comprises a rotating disk and a read/write head actuated above the disk surface. The disk may be formatted into concentric data tracks, with each track being divided into sectors. The tracks may be organized into zones (groups of tracks called cylinders), and the axially parallel sectors in each cylinder may be organized into wedges.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

54.

NOTIFICATIONS FOR AVOIDING THERMAL SHUTDOWN

      
Application Number US2023079022
Publication Number 2024/151337
Status In Force
Filing Date 2023-11-07
Publication Date 2024-07-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Jain, Nitin
  • Peddayyavandla, Srikanth

Abstract

The present disclosure generally relates to improved wait time notifications from SSDs to host systems. Rather than assuming on when to restart an SSD after an asynchronous event notification (AEN) is sent, issuing a cool-off wait time. When an SSD is overheating, an AEN is sent from the SSD. An AEN may either be a warning event or a critical event. Once the AEN is received, a host may issue a banner with a cool-off wait time. The cool-off wait time is a predetermined time that will begin if the SSD is not detected by host systems. A non-detectable SSD means that the SSD is in a thermal shut down mode, which is initiated by a PMIC. In the thermal shut down mode, the cool-off wait timer will begin at host side. After the time has elapsed the SSD can then be restarted either manually by user or automatically by host.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

55.

METHOD FOR HANDLING EXTREME TEMPERATURES IN STORAGE DEVICES

      
Application Number US2023079335
Publication Number 2024/151339
Status In Force
Filing Date 2023-11-10
Publication Date 2024-07-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Jain, Nitin
  • Peddayyavandla, Srikanth

Abstract

An AON module on a storage device periodically obtains the temperatures of the storage device and memory device. A controller uses the temperatures obtained by the AON module to determine a calculated temperature. The controller determines when the calculated temperature is above a thermal threshold and causes the storage device to enter the thermal sleep state where normal operations on the storage device are suspended. In the thermal sleep state, power to the AON module is maintained and the power to other components is modified. The AON module starts a cool-off timer and after a cool-off time expires, the AON module causes power to at least one component on the storage device to be turned on to determine whether the temperature of the storage device is below a first thermal throttling threshold and to cause the storage device to resume normal operations.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

56.

DATA STORAGE DEVICE AND METHOD FOR RACE-BASED DATA ACCESS IN A MULTIPLE HOST MEMORY BUFFER SYSTEM

      
Application Number US2023078986
Publication Number 2024/147841
Status In Force
Filing Date 2023-11-07
Publication Date 2024-07-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Navon, Ariel

Abstract

A data storage device and method for race-based data access in a multiple host memory buffer system are provided. In one embodiment, the data storage device stores data in a plurality of host memory buffers in the host instead of in just the host memory buffer usually associated with the data. To read the data, the data storage device sends read commands to all of the host memory buffers. That way, even if some of the host memory buffers are busy, the data can be returned from another one of the host memory buffers. In future reads in similar workloads, a read command can be sent to the host memory buffer that returned the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

57.

FLUORINATED MEDIA LUBRICANTS WITH REDUCED HYDROCARBON FRACTION FOR DATA STORAGE DEVICES

      
Application Number US2023079388
Publication Number 2024/147848
Status In Force
Filing Date 2023-11-10
Publication Date 2024-07-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • He, Xingliang
  • Wen, Jianming
  • Lee, Charles Cheng-Hsing

Abstract

1f1f222n2f222222s2222222s222232s22222r2s2222s211 is a fluorinated hydrocarbon having a functional group terminating in –OH.

IPC Classes  ?

  • G11B 5/725 - Protective coatings, e.g. anti-static containing a lubricant
  • G11B 5/71 - Record carriers characterised by the selection of the material comprising one or more layers of magnetisable particles homogeneously mixed with a bonding agent on a base layer characterised by the lubricant
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 5/73 - Base layers

58.

DATA STORAGE DEVICE AND METHOD FOR DYNAMIC CONTROLLER MEMORY BUFFER ALLOCATION

      
Application Number US2023079018
Publication Number 2024/147843
Status In Force
Filing Date 2023-11-07
Publication Date 2024-07-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hahn, Judah Gamliel
  • Bazarsky, Alexander
  • Yonin, Micha

Abstract

A data storage device and method for dynamic controller memory buffer allocation are disclosed. In one embodiment, a data storage device is provided comprising a memory and a controller with a controller memory buffer. The controller is configured to communicate with the non-volatile memory and is further configured to configure a size of the controller memory buffer; receive a request from the host to modify the size of the controller memory buffer during operation of the data storage device; and determine whether to grant the request to modify the size of the controller memory buffer. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

59.

ZNS PROTECTION WITH SMALL SLC CACHE USING ZONE GROUPS

      
Application Number US2023079293
Publication Number 2024/147846
Status In Force
Filing Date 2023-11-09
Publication Date 2024-07-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Inbar, Karin
  • Gold, Stephen
  • Parker, Liam

Abstract

The present disclosure generally relates to achieving an acceptable uncorrectable bit error rate (UBER) using a dual temporary data protecting approach and a small SLC cache by adding a temporary XOR protection to zone-groups rather than storing another copy of the zone within the drive. The parity data can be stored with the user data (e.g., as part of the zone-group, effectively increasing zone-group size by 1) or in a separate location, e.g., in an SLC block or another separate MLC block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

60.

STORAGE DEVICES HAVING MULTI-CHANNEL CAPACITIVE SENSORS FOR DETECTING GESTURE BASED COMMANDS

      
Application Number US2023077255
Publication Number 2024/144909
Status In Force
Filing Date 2023-10-19
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Godwin, Sudhan Immanuel
  • Narayanappa, Anil Kumar Kolar

Abstract

Systems and methods are disclosed for providing multi-channel capacitive sensors for detecting user gestures. In certain embodiments, a data storage device includes a non-volatile memory; a plurality of metal pieces configured to form one or more heat sinks of the data storage device and to form a plurality of capacitive pads of a capacitive sensor configured to detect a user gesture; and a controller configured to: detect a gesture of a user in proximity of the plurality of capacitive pads using the capacitive sensor; and perform a command associated with the data storage device based on the detected gesture.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
  • G06F 3/01 - Input arrangements or combined input and output arrangements for interaction between user and computer

61.

NON-VOLATILE MEMORY THAT DYNAMICALLY REDUCES THE NUMBER OF BITS OF DATA STORED PER MEMORY CELL

      
Application Number US2023077258
Publication Number 2024/144910
Status In Force
Filing Date 2023-10-19
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Li, Liang
  • Yuan, Jiahui
  • Tu, Loc

Abstract

A non-volatile memory system reduces the number of bits of data per non-volatile memory cell for a block (or other grouping of non-volatile memory cells) in response to a failed memory operation, the block being subjected to more than a minimum number of programming cycles or other events. The reducing of the number of bits of data stored in the memory cells allows the useful life of the block to be extended.

IPC Classes  ?

  • G11C 16/26 - Sensing or reading circuitsData output circuits
  • G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
  • G11C 16/32 - Timing circuits

62.

SMART CARD WITH BUS INTERFACE RECEPTACLE PRINTED AS PART OF PCB

      
Application Number US2023077262
Publication Number 2024/144911
Status In Force
Filing Date 2023-10-19
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Klapman, Matthew Harris

Abstract

This disclosure a smart card device that provides a bus interface, such as a USB-C bus interface, printed on a portion of a PCB that forms a base layer of the smart card device. The smart card device can provide the bus interface without having to mount a traditional socket. By leveraging the portion of the PCB to provide a printed bus interface and excluding the traditional socket, the bus interface can be easily manufactured using well-known PCB manufacturing techniques while significantly reducing manufacturing costs. Furthermore, the smart card device can have a thickness that conforms to known card form factor standards, enabling the smart device to fit within a standard wallet. To enhance durability of the portion of the PCB from wear-and-tear, a metal core can be added to the PCB as an additional layer. The portion may also be reinforced with edge plating.

IPC Classes  ?

  • G06K 19/077 - Constructional details, e.g. mounting of circuits in the carrier

63.

OPTIMIZED SSD FOR GAME LOADING AND RENDERING

      
Application Number US2023077264
Publication Number 2024/144912
Status In Force
Filing Date 2023-10-19
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Doni Gurudath, Bhanushankar
  • Gopalakrishnan, Raghavendra

Abstract

Aspects are provided for optimizing game loading and rendering using an RMB dedicated for predicted host data that is accessible to a host and to a controller of a storage device. The controller obtains a bitmap indicating a status of a buffer in the RMB, receives from the host a read command indicating a logical address, predicts and reads from an NVM host data associated with a predicted logical address that is subsequent to the logical address, and loads the host data in the buffer in the RMB if the buffer is free. Subsequent read commands indicating the predicted logical address may lack PRP addresses in response to the host data being loaded in the RMB, while completion queue elements in response to such commands may include PRP addresses in the RMB where the host data is stored. Thus, command creation and completion overhead may be reduced using the RMB.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

64.

IN-SITU INSTALL OF CROSS-FLUX MAGNET IN VOICE COIL MOTOR ACTUATOR

      
Application Number US2023077458
Publication Number 2024/144915
Status In Force
Filing Date 2023-10-20
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Kaplan, Brandon

Abstract

A process of assembling a voice coil motor (VCM), such as for a hard disk drive, includes creating an opening in a yoke, attaching a primary magnet to an inside surface of the yoke, installing through the opening in the yoke a cross-flux magnet into a channel of the primary magnet, and installing a plug into the opening in the yoke. Thus, part count is minimized and the manufacturing process is readily incorporated into existing VCM manufacturing processes.

IPC Classes  ?

  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers
  • G11B 21/02 - Driving or moving of heads

65.

TSV SEMICONDUCTOR DEVICE INCLUDING INDUCTIVE COMPENSATION LOOPS

      
Application Number US2023077469
Publication Number 2024/144917
Status In Force
Filing Date 2023-10-20
Publication Date 2024-07-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Contreras, John T.
  • Mobin, Md. Sayed
  • Vodrahalli, Nagesh
  • Varadharajan, Narayanan Terizhandur

Abstract

A semiconductor device includes semiconductor dies formed with through silicon vias (TSVs). The TSVs are coupled to contact pads in a surface of the semiconductor die by coils forming inductance loops at a number of contact pads. These inductance loops serve to distribute the capacitance at each bond pad along transmission lines, which distribution of the capacitance allows for a marked increase in read/write bandwidth for the semiconductor die.

IPC Classes  ?

  • H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
  • H01L 23/528 - Layout of the interconnection structure
  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01F 17/00 - Fixed inductances of the signal type

66.

ERROR CORRECTION METHODS FOR COMPUTATIONAL SSD SUPPORTING RAPID FILE SEMANTIC SEARCH

      
Application Number US2023077105
Publication Number 2024/137024
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-27
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sun, Chao
  • Liu, Muqing
  • Li, Yan
  • Vucinic, Dejan

Abstract

Devices and methods to implement semantic searching on SSD through a computational SSD system that distributes computing to each NAND flash die of the SSD while the SSD controller handles the results aggregation with new on-die computation logic circuits to provide on device file semantic search are disclosed herein. The computational SSD system can read file feature vectors from multiple dies to the SSD controller, and if needed, these feature vectors may be buffered in DRAM and controller handles distance computing. Local, on-die AI/ML processing units may perform, for example, computation and comparison operations and pass the processing scores and results to the SSD controller. The SSD controller aggregates results from all dies and returns the result to the host. The feature vector store size, circuitry and number of on-die AI/ML processing units may be configured as needed to adapt to different tasks, system constraints, and/or feature vector sizes.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • G06F 16/11 - File system administration, e.g. details of archiving or snapshots
  • G06F 16/172 - Caching, prefetching or hoarding of files
  • G06N 20/00 - Machine learning

67.

WRITE COMPLETION PACING FOR UNBALANCED COMMAND LENGTH

      
Application Number US2023077114
Publication Number 2024/137027
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-27
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Richter, Elkana
  • Benisty, Shay
  • Segev, Amir

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. When a command is received by the controller from a host device, the controller determines whether the command size is greater than a threshold size. If the command is not greater than the threshold size, the command is sent to a first queue, otherwise, the command is sent to a second queue. Commands are executed from the first queue until a command size tracker value, which increases by a size representative of each command executed from the first queue, equals or exceeds a threshold value. When the command size tracker value equals or exceeds the threshold value, a command from the second queue is executed and the command size tracker value decreases by a size representative of the command from the second queue. Completion messages are sent at specific intervals based on the executing.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt

68.

SYSTEMS AND METHODS FOR IMPROVING FIND LAST GOOD PAGE PROCESSING IN MEMORY DEVICES

      
Application Number US2023077119
Publication Number 2024/129240
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-20
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Gueta, Asaf
  • Star, Arie
  • Fainzilber, Omer
  • Sharon, Eran

Abstract

A storage device includes a memory die and a controller. The controller identifies a dirty block that was subject to an interrupted I/O operation and performs a coarse inspection of the dirty block. Each iteration of the coarse inspection includes: requesting first bytes of a current page of the dirty block; receiving contents of the first bytes from the at least one memory die; and evaluating a state of the current page based on the contents of the first bytes. The controller also determines an initial last good page based on the coarse inspection and performs a fine inspection of at least one page based on a second number of bytes greater than the first number of bytes. The fine inspection validates the initial last good page and identifies the initial last good page as an actual last good page of the dirty block.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

69.

SEGREGATING LARGE DATA BLOCKS FOR DATA STORAGE SYSTEM

      
Application Number US2023077225
Publication Number 2024/129243
Status In Force
Filing Date 2023-10-18
Publication Date 2024-06-20
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Yang, Niles
  • Linnen, Daniel J.
  • Hahn, Judah Gamliel

Abstract

Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

70.

RAISEABLE PROFILE-BASED ACCESS FOR MEDIA CONTENT

      
Application Number US2023077029
Publication Number 2024/129237
Status In Force
Filing Date 2023-10-16
Publication Date 2024-06-20
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Shukla, Arun Kumar
  • Muthiah, Ramanathan

Abstract

A media playback device is configured to control access to a plurality of files. The media playback device includes memory configured to store a plurality of files, the plurality of files including at least a first set of files and a second set of files, the second set of files having a higher security level the first set of files. The media playback device also includes control circuitry that can be configured to receive a first login from a user, determine that the first login is associated with a user profile associated with the first set of files and the second set of files, provide access to the first set of files in response to validating the first login while keeping the second set of files locked, receive a second login, and provide access to the second set of files in response to validating the second login.

IPC Classes  ?

  • G06F 21/32 - User authentication using biometric data, e.g. fingerprints, iris scans or voiceprints
  • G06F 21/60 - Protecting data
  • G06F 21/64 - Protecting data integrity, e.g. using checksums, certificates or signatures
  • G06F 21/46 - Structures or tools for the administration of authentication by designing passwords or checking the strength of passwords
  • G06V 40/12 - Fingerprints or palmprints
  • G06V 40/16 - Human faces, e.g. facial parts, sketches or expressions

71.

SEMICONDUCTOR DEVICE PACKAGE WITH COUPLED SUBSTRATES

      
Application Number US2023077116
Publication Number 2024/129238
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-20
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Amberkar, Guru Prasada Rao
  • A, Mahesh
  • Anjaneyulu, Kuruba

Abstract

A semiconductor device package includes a first substrate and receiving ports electrically connected to the first substrate. First semiconductor dies are electrically connected to and mounted directly on the first substrate. A second substrate is electrically connected to the first substrate via a corresponding receiving port and is oriented generally perpendicular to the first substrate. Second semiconductor dies are electrically connected to and mounted directly on the second substrate. A housing substantially encloses each of the above mentioned components. The receiving ports allow for additional substrates carrying semiconductor memory dies to be connected to the first substrate thereby increasing the total storage capacity of the semiconductor device package while conforming to a predefined form factor.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/04 - ContainersSeals characterised by the shape
  • H01L 23/42 - Fillings or auxiliary members in containers selected or arranged to facilitate heating or cooling
  • H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
  • H01L 23/498 - Leads on insulating substrates
  • H01L 23/367 - Cooling facilitated by shape of device
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

72.

MEMORY DEVICE AND METHOD OF ASSEMBLING SAME

      
Application Number US2023077118
Publication Number 2024/129239
Status In Force
Filing Date 2023-10-17
Publication Date 2024-06-20
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Wong, Chee Seng
  • Chin, Yoong Tatt
  • Teng, Wei Chiat

Abstract

Technology for a memory device having memory dies flip-chip bonded to one or more interposers that are mounted to a system board is disclosed. The memory device may be an SSD and the system board may be an M.2 board. A memory controller die may be bonded to one of the interposer boards. In one aspect, the memory controller die is flip-chip bonded to the interposer board. In one aspect, a heat sink is attached to a top surface of the flip-chip bonded controller die and to top surfaces of a group of the memory dies. Neither the memory dies nor the interposers are covered with a mold compound. Performance of the memory device is improved by, for example, lower inductance and improved heat dissipation.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H01L 23/498 - Leads on insulating substrates
  • H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
  • H01L 23/367 - Cooling facilitated by shape of device
  • H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

73.

DATA STORAGE DEVICE AND METHOD FOR SWAP DEFRAGMENTATION

      
Application Number US2023076019
Publication Number 2024/118256
Status In Force
Filing Date 2023-10-04
Publication Date 2024-06-06
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Linnen, Daniel J.
  • Muthiah, Ramanathan
  • Hahn, Judah Gamliel

Abstract

A data storage device stores files in its memory. The files may be logically fragmented in that various parts of a given file may be located in non-continuous logical addresses, which can be disadvantageous. The host can send a request to the data storage device to reduce such logical fragmentation. For example, the host can send a swap command to the data storage device, in response to which the data storage device swaps the logical addresses of data fragments of two different files. This results in the logical address of one or both of the data fragments being continuous with the logical address of another data fragment of the same file. This logical address swap can take place without physically moving the data in the memory.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

74.

DATA STORAGE DEVICE WITH MAPPING AND MITIGATION OF LASER MODE HOP EFFECTS IN HEAT-ASSISTED MAGNETIC RECORDING (HAMR)

      
Application Number US2023076022
Publication Number 2024/118257
Status In Force
Filing Date 2023-10-04
Publication Date 2024-06-06
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Knigge, Bernhard E.
  • Haralson, Phillip S.
  • Ito, Naoto
  • Burton, Derrick

Abstract

Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks; and one or more processing devices. The one or more processing devices are configured to generate a map of laser mode hop effects across the corresponding disk surface, for the selected head. The one or more processing devices are further configured to apply a laser mode hop mitigation in operating the selected head, based on the map of laser mode hop effects.

IPC Classes  ?

  • G11B 7/1263 - Power control during transducing, e.g. by monitoring
  • G11B 5/588 - Disposition or mounting of heads relative to record carriers with provision for moving the head for the purpose of maintaining alignment of the head relative to the record carrier during transducing operation, e.g. to compensate for surface irregularities of the latter or for track following for track following on tapes by controlling the position of the rotating heads
  • G11B 5/73 - Base layers
  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 7/127 - LasersMultiple laser arrays

75.

QoS OPTIMIZATION BY USING DATA TRACKING MODULE

      
Application Number US2023076016
Publication Number 2024/112457
Status In Force
Filing Date 2023-10-04
Publication Date 2024-05-30
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Ionin, Michael
  • Bazarsky, Alexander
  • Hahn, Judah Gamliel

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. When data received by the controller, from a host device or from a non-volatile memory of the data storage device, the controller maintains table tracking the location of the data. The table may include a current location of the data in a volatile memory of the controller or the data storage device as well as the current location of the data a latch of the non-volatile memory. The table may further associate the location with a logical block address, such that when the host device requests the data not yet programmed to the non-volatile memory or data that is part of a data relocation operation, the controller may utilize the table to locate the relevant data and provide the data to the host device.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

76.

HEAT-ASSISTED MAGNETIC RECORDING (HAMR) HEAD WITH MAIN POLE HAVING NARROW POLE TIP WITH PLASMONIC LAYER

      
Application Number US2023025561
Publication Number 2024/107243
Status In Force
Filing Date 2023-06-16
Publication Date 2024-05-23
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Matsumoto, Takuya

Abstract

A heat-assisted magnetic recording (HAMR) head has a slider with a gas-bearing-surface (GBS). The slider supports a near-field transducer (NFT) with an output tip at the GBS and a main magnetic pole with a pole tip at the GBS. The pole tip has a narrow cross-track width that can be substantially the same as the cross-track width of the NFT output tip. A plasmonic layer is located between the main pole and the NFT and has a tip at the GBS between the main pole tip and the NFT output tip. The plasmonic layer may also be located on the cross-track sides of the main pole and the main pole tip.

IPC Classes  ?

  • G11B 5/73 - Base layers
  • G11B 5/48 - Disposition or mounting of heads relative to record carriers

77.

PREHEATING LASER DIODES WITH REVERSE BIAS FOR HAMR DISK DRIVES

      
Application Number US2023076012
Publication Number 2024/107498
Status In Force
Filing Date 2023-10-04
Publication Date 2024-05-23
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Schreck, Erhard
  • Rajauria, Sukumar
  • Smith, Robert
  • Poss, Joey M.

Abstract

A data storage device may include one or more disks, an actuator arm assembly comprising one or more disk heads, at least one laser diode positioned inside a corresponding laser diode cavity, a preamplifier, and one or more processing devices. The one or more processing devices are configured to: generate a reverse bias; apply, using the preamplifier, the reverse bias to the at least one laser diode to preheat a corresponding laser diode cavity to a target temperature prior to a write operation; control transition of the preamplifier from applying the reverse bias to applying a forward bias to the at least one laser diode; and activate the at least one laser diode to begin the write operation.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

78.

HIBERNATE EXIT TIME FOR UFS DEVICES

      
Application Number US2023075884
Publication Number 2024/102532
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-16
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Ganon, Doron
  • Lerner, Eitan

Abstract

Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

79.

ZONE-BASED GARBAGE COLLECTION IN ZNS SSDS

      
Application Number US2023075885
Publication Number 2024/102533
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-16
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Deora, Aakar
  • Kochar, Navin
  • Raja Murthy, Sampath Kumar
  • Kashyap, Gursimran

Abstract

Aspects of a storage device are provided including zone-based GC in a ZNS. The storage device includes a NVM and a controller. The NVM includes first blocks, second blocks, and third blocks. The controller creates a first superblock including the first blocks, a second superblock including the second blocks, and a third superblock including the third blocks. The controller allocates a first sub-drive including the first superblock for storing data overwrites and a second sub-drive including the second and third superblocks for storing sequential data in the NVM. During GC for superblocks respectively including data for a specific zone, the controller relocates written data for this zone from the first and third superblocks to the second superblock while refraining from relocating data associated with other zones from the first superblock to the second superblock. As a result, storage device cost, overprovisioning, and WAF may be reduced.

IPC Classes  ?

  • G06F 12/02 - Addressing or allocationRelocation
  • G06F 3/06 - Digital input from, or digital output to, record carriers

80.

FAST EXECUTION OF BARRIER COMMAND

      
Application Number US2023075881
Publication Number 2024/097492
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Segev, Amir
  • Benisty, Shay
  • Sela, Rotem

Abstract

The present disclosure generally relates to read and write operations utilizing barrier commands. Using barrier commands and a snapshot of doorbell states of submission queues (SQs), the necessary write commands to perform a read may be identified and executed to reduce any wait time of the host. As such, host delays during reads and writes are reduced. In absence of a barrier command, the host needs to wait for writes to complete before performing a read. When a barrier command is used, the host needs to wait for the barrier command to complete before performing a read. The controller will execute the post barrier reads only after completing the pre-barrier writes. As will be discussed herein, the controller completes the barrier command as soon as a doorbell snapshot is taken even though the pre-barrier writes may not yet be completed.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

81.

WRITE BUFFER LINKING FOR EASY CACHE READS

      
Application Number US2023075882
Publication Number 2024/097493
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Benisty, Shay
  • Hahn, Judah Gamliel

Abstract

The present disclosure generally relates to improved optimization of a cache lookup operation by structuring the write cache buffers differently using a link-list. Rather than executing a read command first and then executing a write command only after the read command is executed, this disclosure suggests reordering the command executions. A device waits before executing the read command giving the opportunity to obtain the overlap write command. The device then reorders the command execution and executes first the write command and then executes the read command by accessing the write cache instead of the NAND. When two write commands need to be executed consecutively, the link-list operation is used. The controller finds the relevant buffer in the cache that is needed and overwrites the buffer with the new data. The new data is then written to the cache without accessing the cache multiple times.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers
  • G06F 12/0802 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

82.

STORAGE SYSTEM AND METHOD FOR CIRCUIT-BOUNDED-ARRAY-BASED TIME AND TEMPERATURE TAG MANAGEMENT AND INFERENCE OF READ THRESHOLDS

      
Application Number US2023075883
Publication Number 2024/097494
Status In Force
Filing Date 2023-10-03
Publication Date 2024-05-10
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bazarsky, Alexander
  • Navon, Ariel
  • Sharon, Eran
  • Avraham, David
  • Yanuka, Nika
  • Alrod, Idan

Abstract

A storage system has an inference engine that can infer a read threshold based on a plurality of parameters of the memory. The read threshold can be used in reading a wordline in the memory during a regular read operation or as part of an error handling process. Using a machine-learning-based approach to infer a read threshold can provide significant improvement in read threshold accuracy, which can reduce bit error rate and improve latency, throughput, power consumption, and quality of service. In another embodiment, a circuit-bounded array is used to manage updates to time and temperature tag information and to infer read thresholds.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

83.

HOST INDEPENDENT FORMATTING OF STORAGE DEVICES

      
Application Number US2023075297
Publication Number 2024/091761
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Puthamparambil Jayaraj, Prajual

Abstract

A data storage device is enabled to independently self-format, without requiring a connected host device during the active formatting process. The storage device includes a data interface configured to receive power from the host device or a wall charger, non-volatile storage media, and control circuitry. The control circuitry is configured to receive first power from the host device, receive instructions from the host device to perform a format operation, save the instructions to perform the format operation, and cease receiving the first power from the host device. The control circuitry is further configured to receive second power from the wall charger and, in response to retrieving the saved instructions, initiate the format operation on the non-volatile storage media.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

84.

USING CONTROL BUS COMMUNICATION TO ACCELERATE LINK NEGOTIATION

      
Application Number US2023075298
Publication Number 2024/091762
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Moshe, Eran
  • Shmaya, Shuli
  • Edwards, Barrett

Abstract

Systems and methods for devices connected by a control bus to share configuration data for accelerating physical link negotiation for a peripheral interface are described. Computer devices, such as data storage devices, may include a peripheral interface configured to connect to a host system and a control bus interface to connect to a control bus. Other devices on the same control bus may establish peer communication through the control bus interface to share configuration data, such as coefficients for physical link negotiation of the peripheral interface. To accelerate reestablishing communication through the peripheral interface, the device may receive previously stored configuration data from another device over the control bus.

IPC Classes  ?

  • G06F 13/16 - Handling requests for interconnection or transfer for access to memory bus

85.

NAND DIE WITH WIRE-BOND INDUCTIVE COMPENSATION FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES

      
Application Number US2023075300
Publication Number 2024/091763
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Contreras, John
  • Vodrahalli, Nagesh
  • Mobin, Md. Sayed

Abstract

A storage device includes a substrate of a memory package that includes a first pin pad, a controller mounted on the substrate and electrically connected to the first pin pad, the controller being configured to manage data communications on a data channel, and a first memory die. The first memory die includes a front pin pad electrically connected to the first pin pad of the substrate by way of a first bond wire, a rear pin pad, a conductor segment electrically connecting the front pin pad and the rear pin pad of the first memory die, and a plurality of memory cells configured to provide non-volatile storage accessible by way of the data channel.

IPC Classes  ?

  • H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
  • H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
  • H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
  • H01L 23/00 - Details of semiconductor or other solid state devices

86.

DATA STORAGE DEVICE AND METHOD FOR REDUCING FLUSH LATENCY

      
Application Number US2023075301
Publication Number 2024/091764
Status In Force
Filing Date 2023-09-28
Publication Date 2024-05-02
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Sela, Rotem
  • Soffer, Meytal
  • Druck, Asher

Abstract

A data storage device has a cache and a non-volatile memory. Instead of flushing the entire cache to the non-volatile memory in response to a command from a host, the data storage device flushes only the cached data that is associated with an identifier provided by the host. This allows the cached data associated with the identifier to be flushed more quickly. The data storage device can also prioritize queued commands that are associated with the identifier.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

87.

ADVANCED ULTRA LOW POWER ERROR CORRECTING CODE ENCODERS AND DECODERS

      
Application Number US2023075174
Publication Number 2024/086433
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-25
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Pele, Ofir
  • Achtenberg, Stella
  • Zamir, Ran
  • Fainzilber, Omer

Abstract

Advanced ultra-low power error correcting codes are generated using soft quantization and lattice interpolation based on clock and Syndrome Weight. Reinforcement learning may be used to generate threshold values for flipping bits for low density parity check Ultra-Low Power error correction codes. The threshold values can be generated offline and downloaded to a storage device or generated while the storage device is in use.

IPC Classes  ?

  • G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
  • H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes

88.

SENSITIVITY AMPLIFICATION TECHNIQUES FOR MAGNETOCHEMICAL SENSORS

      
Application Number US2023075171
Publication Number 2024/081506
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-18
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Bedau, Daniel
  • Elias, Alexander

Abstract

A device may include a fluid region. A device may also include a magnetochemical sensor for detecting magnetic particles in the fluid region, wherein the magnetochemical sensor comprises: a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer situated between and coupled to the first ferromagnetic layer and the second ferromagnetic layer. A device may further include a current-carrying structure for drawing the magnetic particles in the fluid region toward the magnetochemical sensor, wherein: the current-carrying structure consists of a single, undivided structure, and the current-carrying structure is configured to carry a current in at least one direction that is substantially parallel to an in-plane axis or a longitudinal axis of the magnetochemical sensor. The magnetochemical sensor may be one of a plurality of magnetochemical sensors in a sensor array.

IPC Classes  ?

  • G01N 27/74 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating magnetic variables of fluids
  • G01R 33/12 - Measuring magnetic properties of articles or specimens of solids or fluids

89.

READ COLLISION AVOIDANCE IN SEQUENTIAL MIXED WORKLOADS

      
Application Number US2023075170
Publication Number 2024/076853
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Hutchison, Neil
  • Liu, Haining
  • Lo, Jerry
  • Gorobets, Sergey Anatolievich

Abstract

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

90.

AROMATIC AND AROMATIC-LIKE CONTAINING MEDIA LUBRICANTS FOR DATA STORAGE DEVICES

      
Application Number US2023075880
Publication Number 2024/077021
Status In Force
Filing Date 2023-10-03
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • He, Xingliang
  • Wen, Jianming
  • Lee, Charles Cheng-Hsing

Abstract

mfpqff 222n2mfpqq.

IPC Classes  ?

  • C10M 105/54 - Lubricating compositions characterised by the base-material being a non-macromolecular organic compound containing halogen containing carbon, hydrogen, halogen and oxygen
  • G11B 5/725 - Protective coatings, e.g. anti-static containing a lubricant
  • C10N 40/18 - Electric or magnetic purposes in connection with recordings on magnetic tape or disc

91.

HOLD-UP CAPACITOR FAILURE HANDLING IN DATA STORAGE DEVICES

      
Application Number US2023075149
Publication Number 2024/076850
Status In Force
Filing Date 2023-09-26
Publication Date 2024-04-11
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Chodem, Nagi Reddy
  • Gorobets, Sergey Anatolievich
  • Vazaios, Evangelos

Abstract

A data storage device includes a plurality of hold-up capacitors configured to provide back-up power for a non-volatile memory, a controller, and a write cache. The controller is configured to detect one or more failed hold-up capacitors of the plurality of hold-up capacitors; and in response to detecting the one or more failed hold-up capacitors: perform one or more quiesce operations and determine a count of the one or more failed hold-up capacitors. Based on the count of the one or more failed hold-up capacitors, the controller is configured to reallocate the write buffers of the write cache for use in one or more subsequent write operations.

IPC Classes  ?

  • G11C 16/30 - Power supply circuits
  • G11C 5/14 - Power supply arrangements
  • G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters

92.

FINDING AND RELEASING TRAPPED MEMORY IN ULAYER

      
Application Number US2023025432
Publication Number 2024/072499
Status In Force
Filing Date 2023-06-15
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Frid, Marina
  • Genshaft, Igor

Abstract

The present disclosure generally relates to improving memory management. When valid mSets are relocated via mBlock compaction, the uLayer will have some updates for the mSet and consolidation of the mSet will write the mSet to mBlock once more. The disclosure herein reduces the impact of the problem that the same more frequently updated mSets uRegions are consolidated many times and written to flash where the less updated mSets uRegions become trapped uRegions in the uLayer reducing the uLayer capacity and efficacy. The disclosure provides guidance on how to synchronize the uLayer consolidations efficiently and preventing trapping of unused uRegions in the uLayer that reduces the uLayer capacity and efficiency. The synchronizing is between the uLayer consolidation to the mLayer and the mBlock compaction process such that the smaller uLayer efficacy will not be reduced due to trapped uRegions that are less frequently updated.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

93.

COBALT-BORON (CoB) LAYER FOR MAGNETIC RECORDING DEVICES, MEMORY DEVICES, AND STORAGE DEVICES

      
Application Number US2023025639
Publication Number 2024/072505
Status In Force
Filing Date 2023-06-17
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Okamura, Susumu
  • Le, Quang
  • York, Brian R.
  • Hwang, Cherngye
  • Simmons, Randy G.
  • Ho, Kuok San
  • Takano, Hisashi

Abstract

Embodiments of the present disclosure relate to a cobalt-boron (CoB) layer for magnetic recording devices, memory devices, and storage devices. In one or more embodiments, the CoB layer is part of a spin-orbit torque (SOT) device. In one or more embodiments, the SOT device is part of an SOT based sensor, an SOT based writer, a memory device (such as a magnetoresistive random-access memory (MRAM) device), and/or a storage device (such as a hard disk drive (HDD) or a tape drive). In one embodiment, an SOT device includes a seed layer, and a cap layer spaced from the seed layer. The SOT device includes a spin-orbit torque (SOT) layer, and a nano layer (NL) between the seed layer and the cap layer. The SOT device includes a cobalt-boron (CoB) layer between the seed layer and the cap layer, and the CoB layer is ferromagnetic.

IPC Classes  ?

  • H10N 50/10 - Magnetoresistive devices
  • H10N 50/85 - Materials of the active region
  • H10N 50/01 - Manufacture or treatment
  • H10B 61/00 - Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

94.

GLASS SHEET FOR FABRICATING MAGNETIC RECORDING MEDIA AND METHOD OF FABRICATING MAGNETIC RECORDING MEDIA

      
Application Number US2023025392
Publication Number 2024/072498
Status In Force
Filing Date 2023-06-15
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Suzuki, Shoji
  • Shieh, Mary Grace

Abstract

A glass sheet configured to be cut into glass substrates for magnetic recording disks is described. The glass sheet includes a first surface. For surface features of the first surface with a feature wavelength of 60 to 500 micrometers (μm), a root mean square of a surface topography of the surface features determined using a surface analysis on the first surface with incident and reflected light is given as a microwaviness. A maximum value of the microwaviness of any arbitrary region of the first surface may be between 1.2 nanometers (nm) and 2.8 nm, inclusive of 1.2 nm and 2.8 nm. After the surface analysis, the glass sheet may be cut into the glass substrates in response to determining that the maximum value of the microwaviness is in the noted range. Further, a method of fabricating glass substrates from a glass sheet is described.

IPC Classes  ?

  • G11B 5/73 - Base layers
  • G11B 5/84 - Processes or apparatus specially adapted for manufacturing record carriers

95.

HMB MULTI-SEGMENT OPTIMAL SELECTION

      
Application Number US2023025514
Publication Number 2024/072500
Status In Force
Filing Date 2023-06-16
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

The present disclosure generally relates to improved host memory buffer (HMB) segment selection at the initialization phase. Rather than selecting an HMB segment strictly on one parameter, the selection process will consider multiple factors of the HMB segments. Instead of just selecting a HMB segments based on the size of the HMB segment, the data storage device will perform some basic performance measurements on the provided HMB segments before selecting HMB segments. The selection will be based also on the performance results from the various experiments. The experiments are performed in the initialization phase so the performance of the solid state drive (SSD) will not be impacted. The basic experiments include read, write, and mixed operations toward the HMB segments while measuring the performance and QoS.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

96.

CONTROL TABLE SET MANAGEMENT IN STORAGE DEVICES

      
Application Number US2023025524
Publication Number 2024/072501
Status In Force
Filing Date 2023-06-16
Publication Date 2024-04-04
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor
  • Thacker, Nikita
  • Suresh, Ruthvick

Abstract

Various devices, such as storage devices or systems are configured to efficiently process and update logical maps within control table sets. Control table sets are often groupings of logical map corresponding to the logical locations of data requested by a host-computing device and the physical locations of the data within the memory array. As data is written and erased, these maps must be updated within the control table set. Received changes to these maps are typically stored and updated in two locations: a cache memory and a control table update list. By tracking and marking various control table sets as dirty or having undergone multiple changes, additional received updates can be stored and updated in only the cache memory, bypassing the second control table change list. By only utilizing one method of updating control table sets, processing overhead is reduced and various read or write activities are more efficiently done.

IPC Classes  ?

  • G06F 3/06 - Digital input from, or digital output to, record carriers

97.

DYNAMIC TD-PPM STATE AND DIE MAPPING IN MULTI-NAND CHANNELS

      
Application Number US2023025165
Publication Number 2024/063820
Status In Force
Filing Date 2023-06-13
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller and the memory device communicate using a plurality of flash channels, where each channel is mapped to one or more dies of the memory device. Each of the one or more dies of the memory device are associated with one or more strobes of a strobe cycle of a respective flash channel, where a die is provided power during a respective strobe. The controller is configured to, using a time division peak power management (TD-PPM) operation, change an association of a strobe from a first channel to a strobe of a second channel, which may adjust an amount of power provided to each of the channels and improve performance and latency of the data storage device.

IPC Classes  ?

  • G06F 1/3234 - Power saving characterised by the action undertaken
  • G06F 1/3225 - Monitoring of peripheral devices of memory devices
  • G06F 1/3228 - Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands

98.

CENTER STRUCTURE HAVING ATTACHMENT SUPPORT FOR AN ACTUATOR IN A MULTI-ACTUATOR HARD DISK DRIVE

      
Application Number 18226584
Status Pending
Filing Date 2023-07-26
First Publication Date 2024-03-28
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Park, Jung-Seo
  • Hitchner, Thomas J.
  • Mcnab, Robert
  • Sakhalkar, Siddhesh Vivek

Abstract

A multi-actuator hard disk drive includes a lower actuator with a corresponding voice coil motor assembly (VCMA), a coaxial upper actuator with a corresponding VCMA, and a central support plate positioned between the upper and lower VCMAs and to which the upper VCMA is fastened. Use of a central support plate enables some control over the direct and coupled plant transfer functions, while effectively providing a base support structure for the upper VCMA and enabling use of conventionally-sized fasteners.

IPC Classes  ?

  • G11B 5/55 - Track change, selection, or acquisition by displacement of the head
  • G11B 33/02 - CabinetsCasesStandsDisposition of apparatus therein or thereon

99.

DC AND SYNCHRONIZED ENERGY ASSISTED PERPENDICULAR MAGNETIC RECORDING (EPMR) DRIVER CIRCUIT FOR HARD DISK DRIVE (HDD)

      
Application Number 18467045
Status Pending
Filing Date 2023-09-14
First Publication Date 2024-03-28
Owner Western Digital Technologies, Inc. (USA)
Inventor
  • Poss, Joey M.
  • Ding, Yunfei
  • Contreras, John T.

Abstract

Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.

IPC Classes  ?

  • G11B 5/02 - Recording, reproducing or erasing methodsRead, write or erase circuits therefor

100.

DYNAMIC AND SHARED CMB AND HMB ALLOCATION

      
Application Number US2023025256
Publication Number 2024/063821
Status In Force
Filing Date 2023-06-14
Publication Date 2024-03-28
Owner WESTERN DIGITAL TECHNOLOGIES, INC. (USA)
Inventor Benisty, Shay

Abstract

A data storage device includes a controller. The controller includes a controller memory buffer (CMB). The controller is configured to associate both the CMB and a host memory buffer (HMB) of a host device as a single buffer pool with a plurality of CMB buffers and a plurality of HMB buffers. The controller is further configured to allocate either a CMB buffer or a HMB buffer based on a tradeoff between latency and performance between using the CMB or using the HMB to store data. By leveraging the benefits of both the CMB and the HMB to store data, the overall performance of the data storage device may be improved.

IPC Classes  ?

  • G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
  • G06F 9/30 - Arrangements for executing machine instructions, e.g. instruction decode
  • G06F 9/48 - Program initiatingProgram switching, e.g. by interrupt
  • G06F 12/10 - Address translation
  • G06F 3/06 - Digital input from, or digital output to, record carriers
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