A method includes: receiving first structured data extracted from a first logfile generated by a first run of an electronic design automation process and second structured data extracted from a second logfile generated by a second run of the electronic design automation process; determining, by a processing device, based on the first structured data and the second structured data, that a first section of the first logfile and a second section of the second logfile correspond to outputs of a same stage of the electronic design automation process; extracting first metrics from the first section of the first logfile and second metrics from the second section of the second logfile; and generating a user interface to display the first metrics from the first section of the first logfile adjacent to the second metrics from the second section of the second logfile.
G06F 40/154 - Transformation en arborescence pour documents en configuration arborescente ou balisés, p. ex. langages XSLT, XSL-FO ou feuilles de style
G06F 16/2457 - Traitement des requêtes avec adaptation aux besoins de l’utilisateur
G06F 40/137 - Traitement hiérarchique, p. ex. données générales
Digital ring oscillators (DROs) are distributed throughout an integrated circuit die to achieve localized temperature sensing with a small form factor. A DRO can include cross-coupled inverters, header and footer transistors, and delay elements. Leakage current through the DRO causes a state of an internal node to toggle at a frequency that is a function of temperature of the DRO, which can depend on temperature of a nearby circuit (e.g., a processor). The integrated circuit die may include a controller that is coupled to the DROs. The controller can receive oscillatory digital signals produced by the DROs and control operation of the integrated circuit die based on temperatures indicated by the frequencies of the oscillatory digital signals.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
3.
Pay-per-use metering service for electronic design automation workloads in the cloud
A check-out request for a license may be received from an application, e.g., an electronic design automation (EDA) application, and may be routed to a license server. The license may be granted to the application, where granting the license to the application may include establishing a connection between the license server and the application. A check-in request may be received for the license from the application. The license may be revoked, which may include terminating the connection between the license server and the application. A usage amount may be determined based on information about the check-out request and information about the check-in request.
A delay circuit. In some embodiments, a non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to generate a digital representation of a circuit including: a first inverter, having an input, an output, and two power supply connections; a first current source, electrically coupled in series between a power supply conductor and a power supply connection of the two power supply connections of the first inverter; and a ramp generator circuit, electrically coupled to the input of the first inverter.
H03K 5/13 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés
G11C 11/16 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments magnétiques utilisant des éléments dans lesquels l'effet d'emmagasinage est basé sur l'effet de spin
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
5.
UNDER TEST (DUT) PROCESSING FOR LOGIC OPTIMIZATION
An example is a non-transitory computer-readable storage medium including stored instructions. The instruction, which when executed by one or more processors, cause the one or more processors to: obtain a representation of a design under test (DUT) and split the representation of the DUT into multiple partitions. The representation of the DUT includes optimizable leaf instances and timing paths between respective timing startpoints and timing endpoints. Splitting the representation of the DUT into multiple partitions is based on respective slacks of the timing endpoints. Each partition of the multiple partitions includes one or more timing endpoints of the timing endpoints and a transitive fan-in including one or more optimizable leaf instances along one or more timing paths of the timing paths that terminate at the respective one or more timing endpoints.
An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.
An integrated circuit device includes scan chains and path margin monitor units (PMUs) on a single die. The scan chains test signal paths in the integrated circuit device. The PMUs include path monitor circuitry and self-test circuitry. The path monitor circuitry monitor delays of signals propagating along the signal paths. The self-test circuitry test the path monitor circuitry and report the test results via a communications path other than the scan chains.
A configuration may identify an IC chip component the IC chip component comprising one of a logic block, a memory block, and a power grid. A configuration may train a machine learning model based on one or more features and one or more labels corresponding to the identified IC chip component. A configuration may generate an artificial intelligence model having characteristics comprising the trained machine learning model, the one or more features, and the one or more labels. A configuration may generate a prediction for the one or more labels based on past, present and projected one or more features. A configuration may monitor future label prediction versus a failure threshold. A configuration may generate a notification in response to the failure threshold being reached.
A system and method for automated topology recognition and functional annotation of a mixed-signal circuit is disclosed. The method includes extracting structural information available from the mixed-signal circuit. The method includes identifying functionality of a sub-circuit of the mixed-signal circuit based on the extracted structural information by comparing the sub-circuit with a library cell. The method includes annotating the extracted structural information with the identified functionality corresponding to the sub-circuit. The method includes automatically generating a plurality of configurations corresponding to the annotated structural information.
G06F 30/18 - Conception de réseaux, p. ex. conception basée sur les aspects topologiques ou d’interconnexion des systèmes d’approvisionnement en eau, électricité ou gaz, de tuyauterie, de chauffage, ventilation et climatisation [CVC], ou de systèmes de câblage
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
10.
Partitioning a circuit for distributed balanced independent simulation jobs with upper-bounded memory
Disclosed herein are system, method, and computer program product embodiments for partitioning large circuits into balanced portions for independent simulation. Embodiments include generating a reduced graph by removing a plurality of startpoint vertices from a graph corresponding to a circuit. A plurality of small weakly connected components (SWCCs) and a plurality of large weakly connected components (LWCCs) corresponding to the reduced graph are computed. A first plurality of balanced subgraphs based on the plurality of SWCCs, and a second plurality of balanced subgraphs based on the plurality of LWCCs, where each balanced subgraph of the first and second plurality of balanced subgraphs can be simulated using a simulator with a processing capacity less than or equal to a memory limit are generated. The first and the second plurality of balanced subgraphs are simulated.
G06F 30/31 - Saisie informatique, p. ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
11.
DESIGN OF CURVED MASK LAYERS BASED ON LEVELSET FUNCTIONS
In some aspects, a lithographic mask having multiple features including a curved main feature is designed. A mask layer that represents a vector representation of the lithographic mask is first accessed. A correction field between a simulation field and a target field is then computed. The simulation field is a field representation of a simulated result of a lithography process using the lithographic mask, and the target field is a field representation of a target result of the lithography process. The main feature of a mask field is modified based on the correction field, where the mask field is a field representation of the main feature of the lithographic mask. Finally, the main feature of the mask layer is updated based on the modification to the mask field. This process can be repeated for multiple iterations, and, after the last iteration, a final version of the mask layer is output.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.
G06F 12/0853 - Mémoire cache avec matrices multiples d’étiquettes ou de données
G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
13.
CIRCUIT VARIATION ANALYSIS USING INFORMATION SHARING ACROSS DIFFERENT SCENARIOS
Simulations of a circuit are performed for many different scenarios. These simulations are subject to statistical variations and the simulations produce preliminary analyses of the circuit for the different scenarios. A full characterization of the circuit is estimated for a scenario of interest, by migrating a full characterization for a reference scenario from the reference scenario to the scenario of interest. The full characterization for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
14.
CIRCUIT VARIATION ANALYSIS USING INFORMATION SHARING ACROSS DIFFERENT SCENARIOS
Simulations of a circuit (110) are performed for many different scenarios (120). These simulations are subject to statistical variations and the simulations produce preliminary analyses (130) of the circuit for the different scenarios. A full characterisation of the circuit is estimated for a scenario of interest, by migrating a full characterisation for a reference scenario from the reference scenario to the scenario of interest (166). The full characterisation for the reference scenario was produced by additional simulations of the circuit under the reference scenario. The reference scenario may be identified by grouping the different scenarios into clusters (140).
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A request to provide an application with direct memory access to data stored at an external memory address of an external memory is received. Responsive to determining that the external memory address is not registered in a cache, the data is copied from the external memory address to a first internal memory address within the internal memory. A first cache line, within the cache, associated with the external memory address is updated to include a reference to the first internal memory address. The data is provided from the internal memory to the application.
The present disclosure describes systems and methods for forming scan chains. The system includes a memory and a processor communicatively coupled to the memory. The processor receives a circuit design that includes a plurality of scan cells. The plurality of scan cells includes a first scan cell and a first set of scan cells coupled logically to the first scan cell. The processor forms the plurality of scan cells into a first scan chain such that the first set of scan cells are placed outside an extended neighborhood of the first scan cell. The extended neighborhood of the first scan cell includes (i) scan cells that are downstream of the first scan cell in the first scan chain and (ii) a scan cell that is adjacent to and upstream of the first scan cell in the first scan chain.
A bitcell of a one-time programmable memory includes: a write-once programmable circuit element and a node connected in series between a word line and a power rail; a select read device connected between the node and a bitline, the select read device having a gate electrode connected to a first signal line extending parallel to the word line; and a select write device connected between the word line and the power rail and in series with the write-once programmable circuit element and the node, the select write device having a gate electrode connected to a second signal line extending parallel to the bitline.
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
18.
STATISTICAL TIMING CHARACTERIZATION OF SUPERCONDUCTING ELECTRONIC CIRCUIT DESIGNS
The present disclosure describes systems and methods for generating timing libraries. The apparatus includes a memory and a processor. The processor determines a condition that indicates whether a superconducting electronic circuit design passes or fails logic verification and determines an edge-of-failure value for a timing parameter for the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a first process variation to produce a first timing value for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the edge-of-failure value for the timing parameter and a second process variation to produce a second timing value for the superconducting electronic circuit design. The processor generates a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.
G06F 30/3315 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
Certain aspects of the present disclosure are directed towards a multi-port memory cell. The multi-port memory cell may include: an inverter circuit cell; a hold circuit cell having an output coupled to an input of the inverter circuit cell and an input coupled to an output of the inverter circuit cell; and multiple unit circuit cells having respective tristate drivers, wherein a first plurality of the multiple unit circuit cells are configured as read circuit cells having inputs coupled to an output of the inverter circuit cell and a second plurality of the multiple unit circuit cells are configured as write circuit cells having outputs coupled to an input of the inverter circuit cell.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
Systems and methods for address mapping for a memory system are described. A system address that includes a first set of bits may be received. The first set of bits may be partitioned into at least a second set of bits and a third set of bits. A fourth set of bits may be determined based on the second set of bits. A memory address may be determined by using the third set of bits and the fourth set of bits.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
21.
Finding equivalent classes of hard defects in stacked MOSFET arrays
This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
22.
LOW OVERHEAD OPERATING SYSTEM FOR SIMULATION OF EMBEDDED SYSTEM
A method includes: receiving a software system under test including a software application; determining one or more operating system application programming interfaces invoked by the software system under test; compiling, by a processing device, a simulated operating system including a reduced interface layer providing services associated with the one or more operating system application programming interfaces that are invoked by the software system under test, the services including a virtual timer; and outputting the simulated operating system configured to execute the software system under test.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
23.
CUSTOM LAYOUT RECOMMENDATION USING MACHINE LEARNING
A processing device acquires an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device executes a machine learning model (304) to compute a probability distribution function over a library of historical device placements that estimates a suitability of each historical device placement in the library of historical device placements for placing and routing the set of devices specified in the input. The processing device presents (306) graphical representations for a defined number of historical device placements from the library of historical device placements that are estimated to be suited for placing and routing the set of devices based on the probability distribution function.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/31 - Saisie informatique, p. ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/36 - Conception de circuits au niveau analogique
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
A method for determining a sparse memory size during emulation, the method including: determining, by a profiler memory coupled to a user memory, that one or more pages of the user memory are used by a first test sequence of a testbench during the emulation; identifying, by the profiler memory, a first set of indexes of the one or more pages of the user memory used by the first test sequence; determining a number of unique pages of the user memory that are used by the first test sequence for the emulation based on the first set of indexes; determining, by a processor, the sparse memory size for the user memory based on the number of unique pages of the user memory that are used by the testbench for the emulation and a page size of the user memory.
A processing device may acquire an input (302), where the input specifies a set of devices to be placed and routed for a circuit design. In response to the input, the processing device may execute a machine learning model (304) to compute a probability distribution function over a library of historical device placements that estimates a suitability of each historical device placement in the library of historical device placements for placing and routing the set of devices specified in the input. The processing device may present (306) graphical representations for a defined number of historical device placements from the library of historical device placements that are estimated to be suited for placing and routing the set of devices based on the probability distribution function.
A method of transferring data from a first circuit block to a second circuit block, includes, in part, sampling the data using a first clock signal during a first cycle, compressing the sampled data at the first circuit block and using a compression ratio. In response to a determination that the compression ratio is equal to or less than a threshold value, selecting the compressed data for transmission to the second circuit block, and selecting a second clock signal for sampling the data during a second cycle. The phase of the second clock signal relative to a phase of the first clock signal is determined in accordance with the compression ratio.
H04B 1/66 - Détails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission pour réduire la largeur de bande des signauxDétails des systèmes de transmission, non couverts par l'un des groupes Détails des systèmes de transmission non caractérisés par le milieu utilisé pour la transmission pour améliorer l'efficacité de la transmission
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
A method includes: receiving a simulation vector associated with a circuit design, wherein the simulation vector is associated with a simulation vector type; identifying, by a processor, a plurality of glitch transitions from among one or more transitions associated with a pin of a cell of the circuit design during a clock period of the simulation vector, and determining a glitch power consumption of the cell during the clock period based on the plurality of glitch transitions.
G06F 30/3315 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.
An integrated circuit includes delay monitors that monitor the delays of data signals from the digital circuitry by generating pulses having widths determined by the delays. In some embodiments, the delay monitor is implemented as a digital circuit that includes a pulse generator and an event generator. The delay monitor receives a data signal and a clock signal used to clock the data signal. The pulse generator generates pulses from the received data and clock signals, where the widths of the pulses are determined by a delay of the data signal relative to the clock signal. The event generator generates events that are distributed in time relative to the clock signal. As a result, the delay is estimable based on an overlap between the events and the pulses.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
H03K 5/15 - Dispositions dans lesquelles des impulsions sont délivrées à plusieurs sorties à des instants différents, c.-à-d. distributeurs d'impulsions
30.
OPTICAL AND MANUFACTURING AWARE DESIGN FLOW FOR METASURFACES
A method includes receiving a metasurface design including a plurality of meta-atoms arranged to modify phases of incident waves, the plurality of meta-atoms being from a library of different nominal meta-atoms; generating, by a processing device, a library of manufacturing-aware meta-atoms based on the library of different nominal meta-atoms; and generating instructions for fabricating a manufacturing-aware metasurface having layout computed using a cost function based on the metasurface design and the library of manufacturing-aware meta-atoms.
Various embodiments of a method and apparatus for determining parametric timing yield and bottlenecks are disclosed which take into account correlation between electrical circuit paths through common timing arcs of an integrated circuit chip under design. Monte Carlo samples of timing arc delays are generated and used in computing timing yield and identify yield bottlenecks.
Certain aspects of the present disclosure include a method for memory processing. The method generally includes determining, via one or more processors and for each of different quantities of columns per section of a memory, a read signal indicating a change in a bitline signal during a read window based on at least one calculated slope of the bitline signal during the read window, where the read signal being determined for each of the different quantities of the columns per section of the memory yields a plurality of read signals; determining a difference between at least two of the plurality of read signals, identifying breakpoints within the memory based on the difference between the at least two of the plurality of read signals. The method also includes generating a representation of the memory based on the breakpoints.
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
33.
IMPROVING COVERAGE IN FUNCTIONAL VERIFICATION BY COORDINATED RANDOMIZATION OF VARIABLES ACROSS MULTIPLE CLASSES
A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined.
G06F 7/58 - Générateurs de nombres aléatoires ou pseudo-aléatoires
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
A method includes receiving a metasurface design including a plurality of meta-atoms arranged to modify phases of incident waves, the plurality of meta-atoms being from a library of different nominal meta-atoms; generating, by a processing device, a library of manufacturing-aware meta-atoms based on the library of different nominal meta-atoms; and generating instructions for fabricating a manufacturing-aware metasurface having layout computed using a cost function based on the metasurface design and the library of manufacturing-aware meta-atoms.
G02B 1/00 - Éléments optiques caractérisés par la substance dont ils sont faitsRevêtements optiques pour éléments optiques
G02B 27/00 - Systèmes ou appareils optiques non prévus dans aucun des groupes ,
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
35.
Method and system for transmission power control in bluetooth low energy controllers
A method for dynamically adjusting transmit power of a first device that is in communication with a second device using a wireless communications protocol includes, in part, determining, by the second device, a received signal strength indication (RSSI) associated with a signal received from the first device; determining, by the second device, a first amount of power adjustment for the first device in accordance with the determined RSSI; transmitting the first amount of power adjustment from the second device to the first device; determining, by the first device, a second amount of power adjustment for the first device in accordance with the RSSI and the first amount of power adjustment; and changing a transmit power of the first device in accordance with the second amount of power adjustment.
H04W 52/24 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques utilisant le rapport signal sur parasite [SIR Signal to Interference Ratio] ou d'autres paramètres de trajet sans fil
H04W 52/36 - Commande de puissance d'émission [TPC Transmission power control] utilisant les limitations de la quantité totale de puissance d'émission disponible avec une plage ou un ensemble discrets de valeurs, p. ex. incrément, variation graduelle ou décalages
36.
Data-driven clock port and clock signal recognition
Operations to recognize clock ports within a simulation circuit component and/or recognize a clock signal within simulation waveforms are described. One or more of the operations include generating a plurality of output values at an output port of a circuit simulation component by applying, during a simulation, a plurality of input values to a first input port of the circuit simulation component. The operations also include calculating a correlation vector based on bit sequences in the input values and bit sequences in the output values. The first input port is determined to be a clock port by applying a machine learning model to the correlation vector. One or more of the operations include determining a waveform file comprising signals from a simulation, determining a subset of the signals are bit-level signals, calculating toggle metrics for the subset of the signals, identifying a signal from the subset with a toggle metric satisfying a toggle threshold, calculating, by a processor, multiple duty cycles for the signal, and determining the signal is a clock signal based on the multiple duty cycles.
G06F 30/3308 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle par simulation
G06F 30/20 - Optimisation, vérification ou simulation de l’objet conçu
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
37.
Output driver level-shifting latch circuit for dual-rail memory
A system and method are provided for driving a dual-rail memory circuit that operates with sensing of a memory bit cell, inversion of the sense signal and level shifting in four stage delays. The system includes inversion circuitry configured to (i) receive power from a first power rail (VDDA) of the dual-rail memory, (ii) receive an output of a sense amplifier that senses a state of a bit cell of the dual-rail memory, and (iii) provide two outputs (QB, QT) limited to the first power rail VDDA. The system further includes level-shifting circuitry configured to (i) receive the two outputs of the inversion circuitry (QB, QT). (ii) receive power from a second power rail of the dual-rail memory (VDDP) and (iii) drive an output (Q) in dependence on the two outputs of the inversion circuitry (QB, QT) and limited to the second power rail VDDP which is less than the first power rail VDDA.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 7/06 - Amplificateurs de lectureCircuits associés
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits
An example described herein is a circuit including a dynamic complementary metal-oxide-semiconductor (CMOS) inverter level translator circuit and a capacitor. The dynamic CMOS inverter level translator circuit is electrically connected to a first power domain and has a first input node configured to receive a first trigger signal generated in the first power domain. The dynamic CMOS inverter level translator circuit has a second input node configured to receive a second trigger signal generated in a second power domain different from the first power domain. The capacitor is electrically coupled to an output node of the dynamic CMOS inverter level translator circuit. The capacitor selectively charges to the first power domain through the dynamic CMOS inverter level translator circuit based on the first trigger signal. The capacitor selectively discharges to provide a negative coupling voltage to a write assist supply node.
A description of stimuli used for functional verification of a circuit design is received. The description includes classes of variables and the variable include random variables. A coverage model for the functional verification of the circuit design is also received. The coverage model includes coverage targets that are functions of the variables. A processing device generates stimuli for multiple iterations of the functional verification, as follows. Context values, which include values of the random variables for the stimuli, are maintained. The values of the random variables in an individual class are randomized, and the randomization of the random variables in the individual class is biased to hit the coverage targets given the context values for the random variables outside the individual class. Whether the coverage targets are hit by the generated stimuli is determined.
Embodiments relate to a system for translating design specifications of an electronic circuit. In one embodiment, the design specification is parsed to identify one or more sentences. From the one or more identified sentences, the system extracts semantic concepts. Additionally, for each sentence of the one or more identified sentences, the system determines whether the sentence is translatable. If a target sentence is translatable, the system generates a parse tree for the target sentence, and generates a probabilistic shift-reduce schedule for the generated parse tree. Using the generated probabilistic shift-reduce schedule and optionally the generated parse tree, the system generates code for verifying the condition specified in the target sentence. In some embodiments, to generate the code, the system parses the target sentence using the generated probabilistic shift-reduce schedule.
On-chip testing of a superconductive integrated circuit device includes receiving a superconductive circuit design having superconductive logic elements. Further, a first testability characteristic for first test circuitry at a first node within the superconductive circuit design is determined. The first testability characteristic corresponds to one or more of a test generation control level and a test observability control level. An updated superconductive circuit design from the superconductive circuit design is generated based on the first testability characteristic for the first test circuitry. The superconductive circuit design includes the first test circuitry at the first node.
An output driver includes a pullup driver, a pulldown driver and a resistive element. The pullup driver includes a first PMOS transistor having a source coupled to a first supply voltage and a gate receiving a first data representative of a transmitted data, and a second PMOS transistor having a source coupled to a drain of the first PMOS transistor and a gate receiving a first analog signal. The pulldown driver includes a first NMOS transistor having a source coupled to a second supply voltage and a gate receiving a second data representative of the transmitted data, and a second NMOS transistor having a source coupled to a drain of the first NMOS transistor, a drain coupled to a drain of the second PMOS transistor, and a gate receiving a second analog signal. The resistive element is coupled between the drain terminal of the second NMOS transistor and a pad.
G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
A system and method for temporal control of fault functional verification. In some embodiments, a method includes: determining, in a nominal functional verification of a circuit, that an output of a first component has a first value at a first point in time, the output of the first component being connected to an input of a second component by a wire; determining, in a fault functional verification of the circuit, that the output of the first component has a second value, different from the first value, at the first point in time; determining, based on runtime input, that the wire passes through a barrier; and setting, in the fault functional verification, the value of the input of the second component, at the first point in time, to the first value.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
A circuit includes: a first latch; a second latch coupled to the first latch; and a third latch coupled to the second latch at an input terminal of the second latch, wherein the third latch includes: a first inverter and a second inverter, the first inverter being coupled between the input terminal of the second latch and an input terminal of the second inverter and the second inverter being coupled between an output terminal of the first inverter and an input terminal of the first inverter; a first switch connecting the first inverter to a first voltage source; a second switch connecting the first inverter to ground voltage; a third switch connecting the second inverter to the first voltage source; a fourth switch connecting the second inverter to the ground voltage; and a fifth switch connecting the second latch and the first inverter.
A method for timing path analysis using flow graphs. The method includes receiving timing data associated with an integrated circuit (IC) design. The timing data includes a plurality of timing paths. The method also includes generating a graphical representation of the plurality of timing paths. A timing path is represented as a flow ribbon across one or more components of the IC design. A display attribute of the flow ribbon is indicative of a metric of the timing path. The graphical representation is provided in a graphical user interface (GUI) to a user.
09 - Appareils et instruments scientifiques et électriques
41 - Éducation, divertissements, activités sportives et culturelles
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Downloadable computer software for design and development of computer systems and software applications; Downloadable computer software for analysis and production of programming code in the field of software development; Downloadable computer software development tools; Downloadable computer software for visualization of software and design of computer systems; Downloadable computer software for testing software systems for security; Downloadable software to detect defects in security system software and reliability; Downloadable software for use in identifying, verifying, analyzing, testing and improving security weaknesses within software code; Downloadable software for use in identifying, verifying, analyzing, testing, and improving known vulnerabilities in open source dependencies within software code; Downloadable software for use in identifying, verifying, analyzing, testing, and improving insecure software code configurations; Downloadable software for use in identifying, verifying, analyzing, testing, and improving data leakage risks in computer systems; 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A line driver circuit include a multitude of PMOS and NMOS transistors. A first PMOS transistor receives an output voltage of a first level converter. A second PMOS transistor receives a first reference voltage. A third and fourth PMOS transistors receive an output voltage of a second voltage level converter. The source terminal of the first PMOS transistor receives the supply voltage. The drain terminal of the fourth PMOS transistor is coupled to an output terminal of the line driver circuit. A first NMOS transistor receives an input signal. A second NMOS transistor receives a second reference voltage. A third and fourth NMOS transistors receive an output voltage of a third level converter. The first NMOS transistor receives a ground potential. The drain terminal of the fourth NMOS transistor is coupled to the output terminal of the line driver. The first, second and third voltage converters receive the input signal.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
In an example, a control binary sequence (CBS) determined during simulating a design under test (DUT) is obtained. Simulating included using a constraint random stimulus generator (CRSG) biased by a coverage biaser. The CBS includes first enabled bits that correspond to respective constraint problems solved by the CRSG and biased by the coverage biaser and from which a designated message was triggered during the simulating. A reduced CBS that has second enabled bits that are a subset of the first enabled bits is constructed. A simulation result generated by re-simulating the DUT is obtained. Re-simulating includes selectively, for each constraint problem, restoring solving steps of the CRSG that were performed during the simulating when a corresponding bit of the reduced CBS is an enabled bit. The reduced CBS is assigned as a triggering CBS that triggered the designated message when the simulation result includes the designated message.
Systems and methods to receive a computing job from an Electronic Design Automation (EDA) software application, and dynamically determine at least one precedence or successor job constraint for the received computing job, are described herein. Further, an edge inference algorithm is used to determine edges of a Dynamic Acyclic Graph (DAG) representing the EDA software application computing jobs, along with jobs that are dependent on the received computing job. In this way, job dependencies are discovered and scheduled dynamically, reducing turnaround time, and increasing efficiency of computing resources.
The present disclosure is related to systems and methods for application of machine learning techniques to functional safety analyses of IP cores used in chip designs, to facilitate efficiency, accuracy and completeness of the chip designs. In embodiments of the present disclosure, a functional safety system receives input data for a chip design, and profiles the input data to identify a plurality of IP cores present in the design. The functional safety system determines a match of at least one identified IP core with an IP core present in a functional safety related data structure. The functional safety system then conducts one or more safety analyses on the identified IP core and generates a safety report accordingly.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
An adaptive hardware trace circuit is presented. The adaptive hardware trace circuit may include one or more trace circuits, a trace port funnel circuit, a trace FIFO buffer, and an adaptation logic circuit. Each trace circuit may be coupled to a processor core and configured to monitor and encode trace data generated by a processor core. The trace buffer may be configured to store the trace data generated by the processor cores. The adaptation circuit may be configured to receive, from a user, one or more buffer capacity thresholds and a priority level assigned to each trace. The adaptation circuit may map ranges of trace buffer capacities to corresponding sets of actions. The adaptation circuit may detect a buffer capacity to determine a set of one or more actions associated with the buffer capacity and execute the set of one or more actions.
Aspects of the present disclosure relate to waveform calculation using a hybrid evaluation and simulation approach. Using one or more processors, one or more first portions of a design that are capable of being evaluated using waveform propagation are identified. The identified one or more first portions of the design are evaluated using waveform propagation. One or more second portions of the design that are not capable of being evaluated using waveform propagation are identified. Operation of the one or more second portions of the design is simulated.
System level functional and performance verification across protocols/platforms using a system analyzer that includes a protocol adaptor engine that includes multiple protocol adaptors that convert transactions of a circuit design from respective protocols of the circuit design to a unified protocol, to provide respective unified protocol transactions, and a core engine that includes multiple subsystem monitors configured to monitor respective user-defined subsystems of the circuit design, including to correlate upstream unified protocol transactions of the respective subsystems with downstream unified protocol transactions of the respective subsystems, perform integrity checks on the correlated unified protocol transactions, and report correlation and integrity checking results to an application manager. The application manager may permit user-configuration of the protocol adaptor engine, correlation policies, and/or integrity checking features.
A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.
A method of detecting an error includes, in part, defining a bit pattern using a first multitude of bits, a second multitude of bits, the bits of an error correction code (ECC), and at least one user selected bit. The method further includes, in part, receiving a first value represented by the first multitude of bits and the at least one user selected bit; receiving a second value represented by the second multitude of bits; receiving a third value represented by the ECC bits. The method further includes, in part, generating a syndrome value from the first, second and third values; and using a subset of the syndrome value bits to detect the error in the first, second or third values. The third value is determined in accordance with the first and second values.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
G11C 29/42 - Dispositifs de vérification de réponse utilisant des codes correcteurs d'erreurs [ECC] ou un contrôle de parité
G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
H03M 13/45 - Décodage discret, c.-à-d. utilisant l'information de fiabilité des symboles
56.
Mask synthesis using tensor-based computing platforms
A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further includes modifying the layout of the lithographic mask based on differences between the estimated printed pattern and a target printed pattern. All of the forward models are implemented on the tensor-based computing platform.
G06N 3/00 - Agencements informatiques fondés sur des modèles biologiques
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 1/70 - Adaptation du tracé ou de la conception de base du masque aux exigences du procédé lithographique, p. ex. correction par deuxième itération d'un motif de masque pour l'imagerie
A method of testing a connectivity controller includes, in part, setting a configuration register disposed in the connectivity controller to a first value; causing a first data stored in a first section of a memory associated with the connectivity controller to be forwarded and pass through at least a first component of the connectivity controller and a second component of the connectivity controller, in sequence, in response to the first value; returning data received by the second component, via the first component, for storage in a second section of the memory; comparing, by a processor, the first data to the data returned and stored in the second section of the memory; and verifying the test if the first data matches the returned data.
G06F 13/10 - Commande par programme pour dispositifs périphériques
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
58.
TRACKING TAINT PROPAGATION IN INTEGRATED CIRCUIT DESIGN
Operation of an integrated circuit is simulated. The simulation includes tracking propagation of taint from source data (such as sensitive information or faults) by using taint indicators. The source data is marked as “tainted” by setting a value of a corresponding taint indicator to a taint value. Propagation of the source data along signal paths in the integrated circuit is simulated. The signal paths contain elements through which the source data is propagated. Propagation of the taint from the source data is simulated by calculating values of taint indicators corresponding to signals along the signal paths. These taint indicators indicate whether the taint of the source data has propagated to the corresponding signals. The values of these taint indicators are calculated based on the elements in the signal paths and on the input signals and/or output signals for these elements.
G06F 11/36 - Prévention d'erreurs par analyse, par débogage ou par test de logiciel
G06F 11/277 - Matériel de test, c.-à-d. circuits de traitement de signaux de sortie avec une comparaison entre la réponse effective et la réponse connue en l'absence d'erreur
59.
AUTOMATIC GENERATION OF MULTI-CYCLE PATH DESIGN CONSTRAINT FOR FORWARD ANNOTATION IN INTEGRATED CIRCUIT DESIGN
A method includes: receiving an integrated circuit design; obtaining a timing path between a first sequential circuit element at a launch end of the timing path and a second sequential circuit element at a capture end of the timing path of the integrated circuit design; determining, by a processing device, a common clock that drives a first clock clocking the first sequential circuit element and a second clock clocking the second sequential circuit element based on a clock graph of relationships between a plurality of clocks of the integrated circuit design; and setting a timing constraint for the timing path of the integrated circuit design based on a period of the common clock.
A method of performing an optimization within a circuit layout design is provided. The method includes determining, from multiple nets of the circuit layout design, a target net that has one or more performance characteristics that are outside a range of constraints, determining, from the multiple nets, a non-critical net that has the one or more performance characteristics that are within the range of the constraints, and adjusting, by a processor, one or more of a shape and a location of one or more of the non-critical net and the target net, such that the one or more performance characteristics of the non-critical net is changed and remains within the range of the constraints.
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.
G01R 31/30 - Tests marginaux, p. ex. en faisant varier la tension d'alimentation
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
62.
Power-efficient enable signal for fanin-based sequential clock gating on enabled flip flops
A circuit includes, in part, first and second sequential elements and a clock gating circuit. The first sequential element has an enable terminal receiving a first enabling signal, a clock terminal receiving a first clock signal, a data input terminal and a data output terminal. The second sequential element has a clock terminal, and a data input terminal coupled to the data output terminal of the first sequential element. The clock gating circuit is coupled to the first and second sequential elements and includes, in part, a third sequential element configured to store data in response to the first enabling signal and a second enabling signal. The clock gating circuit is further configured to supply a second clock signal to the clock terminal of the second sequential element in response to an assertion of the second enabling signal and the data stored in the third sequential element.
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
Certain aspects are directed to apparatus and methods for performing a blinded operation. The method generally includes: obtaining a first operand and a second operand for a multiplication operation; performing, via one or more processors, one or more shift operations or a bit-flip operation on the first operand to generate a first blinded operand; and performing the multiplication operation based on the first blinded operand and the second operand to generate a blinded multiplication result.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
A method of forming a complementary field effect transistor (CFET) is provided. The method includes adding a blocking material to a vertical channel of the CFET having an epitaxial growth, the blocking material being located below and in contact with a lower portion of the growth, adding an insulating material to an open area within the vertical channel to surround a portion of the epitaxial growth, performing an etch to (i) remove a portion of the insulating material, (ii) expose a contact surface of the epitaxial growth and (iii) provide a vertical opening within the vertical channel, the etch leaving a portion of the blocking material, and filling in the vertical opening with a conductive material, the conductive material reaching the exposed contact surface of the epitaxial growth, the blocking material remaining below the conductive material to prevent contact between the conductive material and a silicon substrate below the growth.
A method includes: receiving an integrated circuit design including a plurality of circuit modules; partitioning the integrated circuit design into a plurality of partitions in accordance with the plurality of circuit modules; assigning the plurality of partitions of the integrated circuit design to corresponding portions of an emulation system; inserting, by a processor, a plurality of emulation communication circuit structures into the plurality of circuit modules of the integrated circuit design, the corresponding portions of the emulation system being configured to communicate via one or more emulation interconnects connected to the emulation communication circuit structures, the emulation communication circuit structures being represented at a representation level selected from a group comprising: a packet level; a transaction level; and a protocol level; and emulating operation of the integrated circuit design using the emulation system.
A communication system includes a receiver device having a continuous time linear equalizer circuitry. The continuous time linear equalizer circuitry includes first gain circuitry, second gain circuitry, second gain circuitry a first capacitor, a first resistive element, a first inductor, and a second resistive element. The first gain circuitry and the second gain circuitry receive an input signal. The first capacitor is connected between an output of the first gain circuitry and an output of the second gain circuitry. The first resistive element is connected between the output of the first gain circuitry and the output of the second gain circuitry. The first inductor is connected to the output of the first gain circuitry, the first capacitor, and the first resistive element. The second resistive element is connected in parallel with the first inductor.
A relationship between at least a first metric of an integrated circuit (IC) design and a power supply voltage of the IC design may be determined based on a set of IC designs that have different power supply voltages. Next, the power supply voltage and at least the first metric of the IC design may be modified by interpolating values of the first metric based on the relationship between the first metric and the power supply voltage of the IC design.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
68.
At-speed synchronous write-through operation for testing two-port memory
A method is provided for testing two port memory. The method includes receiving a synchronous write through (SWT) mode signal that indicates one of a functional mode of operation and a testing mode of operation of the memory, wherein the testing mode triggers bypassing of one or more read operations from bit cells of the memory identified by read address signals, and switching between the functional and testing modes of operation in dependence on the SWT mode signal. When the memory is in the testing mode of operation the circuit, receiving test data obtained from read address signals to represent a test state for the bit cells of the memory.
Simulating a system involves running a simulation model on a virtual processor that interfaces to a simulator, the virtual processor being associated with a unique memory space in the memory space used by the simulator. The virtual processor technique gives the developer a simple technique for ensuring the model and simulator interactions are managed effectively, i.e. that no unintentional corruptions of each other's memory space are possible. It also facilitates making multiple instantiations of a C, C++ or other general purpose programming language model. The resulting environment also resolves one of the limitations on the use of third party models within the SystemC environment.
A communication receiver can determine an angle of arrival (AoA) of a communication signal. The communication receiver includes multiple receiving antennas and processing circuitry. The processing circuitry determines multiple phase shifts over multiple instances in time from first samples of a communication signal as observed by a reference receiving antenna selected from among the multiple receiving antennas, samples the communication signal as observed by the selected receiving antennas from among the multiple receiving antennas over the multiple instances in time to provide second samples of the communication signal, removes the multiple phase shifts from corresponding samples from among the second samples of the communication signal to provide phase corrected second samples of the communication signal, and determines the AoA of the communication signal from the phase corrected second samples of the communication signal.
H04B 7/08 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station de réception
G01S 5/06 - Position de source déterminée par coordination d'un ensemble de lignes de position définies par des mesures de différence de parcours
H03H 11/20 - Déphaseurs à deux accès produisant un déphasage réglable
H04B 5/00 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive
H04B 5/77 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive spécialement adaptés à des fins spécifiques pour l'interrogation
H04B 7/165 - Stations terrestres employant la modulation angulaire
H04W 4/80 - Services utilisant la communication de courte portée, p. ex. la communication en champ proche, l'identification par radiofréquence ou la communication à faible consommation d’énergie
09 - Appareils et instruments scientifiques et électriques
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Downloadable computer software for electronic design
automation; downloadable computer software for electronic
design automation using artificial intelligence;
downloadable computer software for electronic design
automation in the field of designing of computer logic;
downloadable computer software for use in electronic system
design and integrated circuit design; downloadable computer
software for use with system emulators; downloadable
computer software for simulating electronic circuits;
downloadable software for use with application-specific
integrated circuit (ASIC) and system-on-a-chip (SOC)
emulators; downloadable computer software for viewing,
modeling, testing, and editing components and layouts of
integrated circuits and semiconductors; downloadable
computer software for integrated circuit design,
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verification; downloadable computer software for performance
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through artificial intelligence; downloadable computer
software for fast Path Based Analysis (PBA) through
artificial intelligence; downloadable computer software for
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artificial intelligence applications; downloadable software
in the nature of an interview-driven application that
evaluates a cloud application's design and security
controls; downloadable computer software for design and
development of computer systems and software applications;
downloadable computer software for analysis and production
of programming code in the field of software development;
downloadable computer software for visualization of software
and design of computer systems; downloadable computer
software utilized by software developers to search internal
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making internal code assets searchable at a code-level for
developer knowledge and understanding; downloadable computer
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electrical capacitance of electrical circuits; downloadable
computer software for generating models of integrated
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design, analysis, optimization, and generation of models for
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software for design and fabrication of printed circuit
boards; downloadable computer software for analysis of
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software for designing electronic systems wiring and
assembly; downloadable computer software for use in yield
management in the field of semiconductor, solar, photonic,
and electronic display manufacturing; downloadable computer
software for use in analyzing and designing photomasks for
use in semiconductor, photonic, and electronic display
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analyzing and designing semiconductor, solar, photonic, and
electronic display manufacturing processes and devices;
downloadable computer software for use in analyzing
two-dimensional images in medical and industrial fields;
downloadable computer software for computer-aided, visual
and photometric development of products in the automotive
field; downloadable computer software for design,
simulation, and analysis for development of photonic
integrated circuits and photonic devices; downloadable
software for the design of security controls for a cloud
migration or assessing the effectiveness of controls in an
existing application; downloadable software for automatic
detection of security threats and vulnerabilities in
computer software; downloadable computer software for
testing software systems for security; downloadable software
to detect defects in security system software and
reliability; downloadable computer software for identifying,
analyzing, and improving software and application security;
downloadable computer software for software composition
analysis, auditing open source software compliance, and
detecting vulnerabilities in third party code; downloadable
computer software to assist software developers to manage
the software development process and for auditing of
computer software and computer programs and for managing
compliance and open source software use and development;
downloadable computer software for use in scanning,
reviewing, evaluating and reporting on the composition and
components of other computer for identifying, tracking and
managing of software assets and use of third party software,
or to ensure compliance with industry, legal or governmental
regulations by businesses and institutions; downloadable
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components to databases of known software sources in order
to evaluate and categorize such components and identify the
source of such components; downloadable computer software
for conducting computer software audits and reporting the
results of such audits; downloadable computer software for
automating open source security and license compliance
during application development; computer application
software for the design and deployment of machine
learning-based applications; downloadable artificial
intelligence-enabled computer software applications for
design space optimization and assistance with debugging;
software for processing digital audio; downloadable
computer-aided design (CAD) software for designing and
testing integrated circuits; downloadable computer software
for computer-aided design, simulation, verification,
analysis, testing, and developing of the silicon
manufacturing processes of electronic circuits, integrated
circuit, and other semiconductor devices; downloadable
computer-aided design (CAD) software for designing,
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downloadable computer software, computer code, databases,
and data files used in, and for use in, the design and
development of semiconductors, electronic circuits, and
integrated circuits; downloadable computer software
development tools; downloadable computer software
development tools used to test, evaluate, and improve
information and network security; downloadable software
development kits (SDKs); electronic design automation (EDA)
software tools for designing, developing, verifying,
testing, and debugging electronic systems, electronic
circuits, systems on chips (SOCs), integrated circuits,
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optimization, namely, designing, verifying, simulating,
testing, and debugging semiconductor manufacturing
processes; downloadable computer hardware and software for
system-on-a-chip (SOC) debugging; downloadable computer
hardware and software for computer system and application
development; downloadable computer hardware and software for
hardware and software co-verification and system-level
validation; computer hardware; computer hardware for
electronic design automation; computer hardware for
verification of integrated circuit design; computer
hardware, namely, emulators; computer hardware, namely,
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(ASIC) and system-on-a-chip (SOC) emulators; computer
hardware, namely, integrated circuits, microprocessors, and
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intellectual property (SIP) architecture for security
purposes; computer hardware, namely, computer motherboards,
daughterboards, memory boards, input/output boards, adaptor
boards, interconnect boards, and power supplies, for use in
integrated circuit design; connectors for computer
motherboards and daughterboards; computer programs for
artificial intelligence; downloadable electronic instruction
manuals in the fields of software, electronic systems, and
integrated circuit design; electronic downloadable
publications in the nature of newsletters, datasheets,
technical papers, educational materials, and white papers in
the fields of computer software, electronic design
automation, software verification, software security, cyber
security, software risk management, integrated circuit
design, software design, software productivity, and chip
power management; data processors; microprocessors; vision
processors; vision processing units (VCUs); semiconductor
intellectual property (SIP) architecture (Term considered
too vague by the International Bureau pursuant to Rule 13
(2) (b) of the Regulations); semiconductor intellectual
property (SIP) architecture for security purposes (Term
considered too vague by the International Bureau pursuant to
Rule 13 (2) (b) of the Regulations); semiconductor
intellectual property (SIP) cores; semiconductor
intellectual property (SIP) cores for video and audio
encoding, decoding, and transcoding; cloud computing
software for electronic design automation. Educational services, namely, providing and disseminating
educational and training materials in the fields of computer
software, electronics design and computer security;
educational services, namely, conducting classes, seminars,
webinars, workshops, and classes in the fields of computer
software, software design and development, software
security, software development security, silicon chip design
and verification, semiconductor intellectual property (SIP),
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management and software licensing and compliance; academic
enrichment programs in the field of computer software,
electronic design automation software, and static analysis
software; providing a website featuring blogs and
non-downloadable publications in the fields of software
integrity, cloud integrity, chip design and verification,
intellectual property, and software security and quality
(Term considered too vague by the International Bureau
pursuant to Rule 13 (2) (b) of the Regulations); providing
online publications in the nature of instruction manuals for
development systems, software libraries, designs, design
specifications and protection systems in the field of
electronic system and integrated circuit design (Term
considered too vague by the International Bureau pursuant to
Rule 13 (2) (b) of the Regulations). Consultation services in the field of design, development,
and testing of computer software; consulting services in the
field of cloud computing; consultancy in the field of cloud
application design and development and cloud computing
infrastructure design and development; consultation services
in the field of cloud migration and implementing cloud
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weaknesses in the cloud infrastructures; cloud computing
security consultancy; data security consultancy; computer
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information security vulnerability; consulting services,
namely, providing problem resolution to design level
engineers; consulting services, namely, identifying,
analyzing, and reducing the risks of software failure;
information technology consultation in the field of
microelectronics; technological consultation and advisory
services in the field of microelectronics as it relates to
verification technology; computer software consulting
services to assist the management of intellectual property
risks of the software development process; computer software
consulting services to assist the management of licensing
and compliance risks of the software development and
management process and managing risks associated with the
development, ownership and licensing of software; computer
consulting services in the field of application development,
code review, computer security, and software architecture
analysis; computer software consultation services in
connection with conducting software audits and implementing
best practices in the identification, tracking, and
management of software assets and the use of third party
software; computer services, namely, providing computer
software and application programming consulting services;
technical consulting services in the fields of datacenter
architecture, public and private cloud computing solutions,
and evaluation and implementation of internet technology and
services; consulting and technical support services, namely,
providing technical advice relating to software security
testing, security control, and analysis; technical support
services, namely, troubleshooting in the nature of
diagnosing computer software and hardware problems;
technical support services, namely, 24/7 reporting and
monitoring of open source vulnerabilities in software
application development; providing quality assurance
services in the field of computer software; testing of
computer software; design and development of computer
hardware and software; development and implementation of
software, hardware and technology solutions for artificial
intelligence; development and implementation of software,
hardware and technology solutions for the purpose of testing
and productization of electronic components and electronic
systems for automobiles; development and implementation of
software, hardware and technology solutions for the design
and deployment of machine learning-based applications;
development, design, and maintenance of computer software
for computer-aided, visual, and photometric development of
products in the automotive field and in industry; design for
others of computer hardware, computer software, and computer
programs all in the field of the development and
verification of microelectronics; integrated circuit,
semiconductor, and electronic circuit design services,
namely, electronic design automation services; providing
temporary use of on-line non-downloadable artificial
intelligence software for smart parameter setup; providing
temporary use of on-line non-downloadable software for
silicon lifecycle management (SLM); providing temporary use
of on-line non-downloadable software for electronic design
automation; providing temporary use of on-line
non-downloadable software for identifying, analyzing, and
improving software and application security; providing
temporary use of on-line non-downloadable software for the
purpose of analyzing computer code and reporting the
contents of computer code; software-as-a-service (SaaS)
services featuring software for electronic design
automation; software-as-a-service (SaaS) services featuring
software for electronic design automation using artificial
intelligence; software-as-a-service (SaaS) services
featuring software for integrated circuit design and
verification; software-as-a-service (SaaS) services
featuring software for integrated circuit design and
verification using artificial intelligence;
software-as-a-service (SaaS) services featuring computer
software for development, design, and visualization of
computer systems and software applications;
software-as-a-service (SaaS) services featuring an
artificial neural network software for lithography
correction; software-as-a-service (SaaS) services featuring
artificial intelligence-enabled software applications for
design space optimization and assistance with debugging;
software-as-a-service (SaaS) services featuring software for
monitoring, analysis, and optimization of semiconductor
devices throughout their lifecycle; software-as-a-service
(SaaS) services featuring software for testing software,
identifying threats to security, eliminating software
security vulnerabilities, and benchmarking software
security; software-as-a-service (SaaS) services featuring
software for automatic detection of security threats and
vulnerabilities in computer software; software-as-a-service
(SaaS) services featuring software development tools used to
test, evaluate, and improve information and network
security; software-as-a-service (SaaS) services featuring
software for analysis and production of programming code in
the field of software development; software-as-a-service
(SaaS) services featuring software for testing software and
benchmarking software reliability; software-as-a-service
(SaaS) services featuring software for application security
orchestration and correlation, as well as remediation
prioritization and cybersecurity risk management;
software-as-a-service (SaaS) cloud computing technology;
cloud computing featuring software for use in integrated
circuit design and verification; cloud computing security
threat analysis for protecting data; cloud computing
services featuring software for use in security analysis and
testing, source code review, application testing; providing
virtual computer environments through cloud computing;
providing an Internet website portal featuring computer
software for design and development of computer systems and
software applications (Term considered too vague by the
International Bureau pursuant to Rule 13 (2) (b) of the
Regulations); providing a website that features information
on computer technology and programming directed to open
source programmers and developers (Term considered too vague
by the International Bureau pursuant to Rule 13 (2) (b) of
the Regulations); providing an Internet website portal
featuring computer application development environments and
tools, namely, testing and evaluation of software, software
containing open source code, and software applications for
interoperability and compliance with industry standards and
established policies and standards (Term considered too
vague by the International Bureau pursuant to Rule 13 (2)
(b) of the Regulations); hosting and maintenance of online
searchable computer databases of open source code;
infrastructure-as-a-service (IaaS) cloud computing
technology; infrastructure-as-a-service (IaaS) services
featuring electronic design automation;
infrastructure-as-code (IaC) services, namely, providing a
security control matrix that maps the solutions outlined in
cloud security blueprints in accordance with regulatory
standards for the implementation of computing services;
services in the field of simulation of physical properties
of materials and electronic equipment, namely development of
computer simulation software that take into account the
atomic scale data of the materials and equipment; computer
simulation based on computer programs to develop and
optimize semiconductor processing technologies and devices;
computer services, namely, providing an online portal for
tracking and analyzing computer software development (Term
considered too vague by the International Bureau pursuant to
Rule 13 (2) (b) of the Regulations); computer services,
namely, a website featuring technology that provides access
to graphic user interfaces for developers of open source
projects (Term considered too vague by the International
Bureau pursuant to Rule 13 (2) (b) of the Regulations);
computer services, namely, conducting software audits,
namely, using the company's proprietary software to scan the
software of others in order to detect and report on the
software content found within, and evaluating and reporting
the results of such audits; computer services, namely,
hosting and maintaining a website to analyze computer code
and report on the contents of computer code; computer
systems analysis, namely, reviewing, evaluating and
reporting on the composition and components of computer
software on the computer systems of others in order to
assist businesses and government organizations in
identifying, tracking and managing their software assets and
use of third party software, or to ensure compliance with
industry, legal or governmental regulations; computer
systems analysis, namely, using proprietary software to
compare individual software components on the computer
systems of others to databases of known software sources in
order to evaluate and categorize such components and
identify the source of such components; consultation in the
field of testing computer systems for security purposes. Monitoring of computer software and systems for security
purposes; consultation in the field of monitoring computer
systems for security purposes.
72.
REDUCED CIRCUIT AREA MEMORY DEVICE WITH A HALF-WORD MEMORY ARCHITECTURE
A memory device includes a memory device and control circuitry. The memory array includes bitcells and bitlines connected to the bitcells. The bitcells are grouped into bitcell groups. The control circuitry is connected to the bitcell groups via the bitlines. The control circuitry adjusts connections with the bitcell groups to include a first bitcell group of the bitcell groups in memory operations and exclude a second bitcell group of the bitcell groups from the memory operations based on a half-word control signal being enabled.
The present disclosure describes a system and method for generating and/or adjusting a superconducting electronic circuit design. According to an embodiment, the system includes a memory and a processor communicatively coupled to the memory. The processor determines a slope in a voltage pulse at a transmitter for a passive transmission line of a superconducting electronic circuit design and determines a model for the passive transmission line based on the slope. The processor also simulates the superconducting electronic circuit design using the model and makes an adjustment to the transmitter based on simulating the superconducting electronic circuit design.
A method and system are provided for synchronizing signals, using a synchronizer circuit, between a source circuit and a destination circuit that utilizes detection of when the destination circuit clock is turned off. In the method performed by the synchronizer circuit, a stop signal is received from the destination circuit that is generated upon determination that the destination clock in the destination circuit is turned off. A data signal from the source circuit is, upon receipt of the stop signal, prevented by the synchronizer circuit from being transmitted from the source circuit to the destination circuit. Then once a start signal is received in response to the destination circuit clock signal turning back on, the data signal is once again transmitted from the source circuit to the destination circuit by the synchronizer.
Certain aspects are directed to apparatus and methods for logic synthesis. One example method generally includes: receiving a logic design including a representation of a plurality of registers and ports; detecting one or more constant, equal, or opposite registers or ports of the plurality of registers and ports by analyzing logic across a hierarchy boundary identified for the logic synthesis; and generating a netlist by modifying the logic based on the detection.
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
76.
STATISTICAL SHAPE AND APPEARANCE MODELING FOR VOLUMETRIC GEOMETRY AND INTENSITY DATA
An image-based approach for statistical shape and appearance modeling includes re-orienting (rotating/translating) training masks to align the training masks with a reference mask to provide corresponding re-orientation parameters, where the training masks represent 3-dimensional shapes of a population of objects and the reference mask represents a 3-dimensional shape of a reference object, deforming the re-oriented training masks based on the reference mask to provide displacement fields indicative of differences between a 3-dimensional shape of the reference mask and 3-dimensional shapes of the re-oriented training masks, re-orienting training backgrounds based on the re-orientation parameters, where the training backgrounds represent volumetric intensity data of the 3-dimensional images of the objects, deforming the re-oriented training backgrounds based on the displacement fields, combining the deformed training backgrounds and the displacement fields, and reducing a dimensionality of the combined deformed training backgrounds and displacement fields to provide a statistical shape and appearance model.
An example is a method. A control flow graph is populated with instances of model objects. Each instance of the instances of the model objects represents a respective stage of a processor architecture design. The instances of the model objects are interconnected in the control flow graph. The interconnected instances of the model objects are an architecture model representing the processor architecture design. The architecture model including the interconnected instances of the model objects is output by one or more processors.
An example is a method. A control flow graph is populated with instances of model objects. Each instance of the instances of the model objects represents a respective stage of a processor architecture design. The instances of the model objects are interconnected in the control flow graph. The interconnected instances of the model objects are an architecture model representing the processor architecture design. The architecture model including the interconnected instances of the model objects is output by one or more processors.
A second virtual address may be received, where the second virtual address is different from a first virtual address. A second hash value may be computed based on the second virtual address. A first comparison result may be determined by comparing the second hash value with a first hash value, where the first hash value is computed based on the first virtual address. The first comparison result may be used to select a selected structure from either a first structure or a second structure. The selected structure may be used to determine predicted aliasing bits which are used to determine an index corresponding to the second virtual address.
G06F 12/08 - Adressage ou affectationRéadressage dans des systèmes de mémoires hiérarchiques, p. ex. des systèmes de mémoire virtuelle
G06F 12/0864 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens pseudo-associatifs, p. ex. associatifs d’ensemble ou de hachage
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
80.
Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis
A graph-based timing analysis (GBA) is applied to a circuit design that includes a routed gate-level netlist to produce timing estimates of the circuit design. A machine learning (ML) model is applied to modify these GBA timing estimates of the circuit design to make them more accurate. For example, the ML model may be trained using timing estimates from path-based timing analysis as the ground truth, and using features of the circuit design from the GBA as input to the ML model.
Methods and systems are described herein relate to automatic channel identification of high-bandwidth memory channels and subchannel generation. An HBM channel identification system may perform a sequence of operations to identify HBM channels within a netlist of an interposer: channel dimension prediction, channel bounding box prediction, channel orientation derivation, subchannel partition, and subchannel routing region creation. In one example, an HBM channel identification method includes identifying candidate nets within a netlist. A bounding box that includes one or more nets of the candidate nets is determined. Once the bounding box is determined, the orientation of the box is determined and used to determine a pattern of bumps within the bounding box. Finally, a subchannel is generated based on the pattern of bumps.
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
G06F 30/392 - Conception de plans ou d’agencements, p. ex. partitionnement ou positionnement
G06F 30/398 - Vérification ou optimisation de la conception, p. ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
The present disclosure describes circuits (e.g., clock synthesizers) and methods for producing alternating signals. A clock synthesizer includes an oscillator, a voltage control circuit, and a frequency control circuit. The oscillator produces an output signal with a frequency. The voltage control circuit produces a control voltage for the oscillator based on the frequency of the output signal. The frequency control circuit produces a control signal for the oscillator based on (i) an input voltage to the frequency control circuit and (ii) the control voltage. The control signal causes the oscillator to adjust the frequency of the output signal such that the voltage control circuit adjusts the control voltage to be closer to the input voltage.
H03K 5/135 - Dispositions ayant une sortie unique et transformant les signaux d'entrée en impulsions délivrées à des intervalles de temps désirés par l'utilisation de signaux de référence de temps, p. ex. des signaux d'horloge
H03K 5/00 - Transformation d'impulsions non couvertes par l'un des autres groupes principaux de la présente sous-classe
H03K 5/26 - Circuits présentant plusieurs entrées et une sortie pour comparer des impulsions ou des trains d'impulsions entre eux en ce qui concerne certaines caractéristiques du signal d'entrée, p. ex. la pente, l'intégrale la caractéristique étant la durée, l'intervalle, la position, la fréquence ou la séquence
83.
Multiple clock and clock cycle selection for x-tolerant logic built in self test (XLBIST)
A system and method are provided for testing logic using a logic built in self-test (LBIST) system, and in particular where the LBIST system tolerates unknown inputs (Xs) to the logic cells forming an XLBIST system. The system allows for providing multiple test system clocks from the LBIST system to the logic during a system clock capture cycle of a system clock during testing of the logic, wherein the system clock is separate from the multiple test system clocks of the LBIST system. Further, timing of an application of clock cycles of the multiple test system clocks of the LBIST system is controlled and provided to the logic during the system clock capture cycle.
The present disclosure describes a system and method for generating references for software crashes. The method includes applying a first machine learning model to a test case for a software application to adjust the test case to produce an adjusted test case and executing the adjusted test case on the software application to produce a software crash. The method also includes applying a second machine learning model to the software crash to generate a reference crash signature for the software crash and logging, using the second machine learning model, a reference crash configuration for the software crash.
A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
Emulating a circuit design includes receiving a circuit design. The circuit design is mapped onto integrated circuit (IC) devices. Further, the circuit design that is mapped onto the IC devices is instrumented by inserting a first change detection circuit and a first synchronization circuit. The first synchronization circuit is connected to the first change detection circuit and stops emulation on one of the IC devices based on an output of the first change detection circuit and completion of a first one or more emulation cycles. Further, the IC devices are provided for emulation.
A plurality of design iterations are executed for a flow to design a circuit. The design flow includes a sequence of at least two stages. Each stage produces an output design of the circuit from an input design of the circuit, in accordance with parameters for that stage. The design iterations select parameter values for slices of one or more stages of the design flow. In the design iterations for at least one of the slices, parameter values for a non-final stage of the design flow are selected based on a final quality of result (QoR) of the design flow. The design iterations for this slice are adapted based on final QoRs produced by the design iterations.
Embodiments relate to reading signals from a stimulus file produced by an emulator into a data store. A method includes executing, by a set of one or more worker processes, reading tasks. Each reading task is executable independent of other reading tasks. Each reading task includes reading a time slice of a signal from a stimulus file produced by a hardware emulator, and pushing a partial waveform corresponding to the time slice to a data store. The partial waveform includes a head and a tail that each has a smaller data size than an entirety of the partial waveform. The method further includes executing stitching tasks. The stitching tasks include pulling the heads and tails of the partial waveform from the data store, modifying the heads and tails to indicate a temporal order of the partial waveforms, and pushing the modified heads and tails back to the data store.
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
89.
IDENTIFYING RTL CODE THAT CAN BE A SOURCE OF VERIFICATION COMPLEXITY FOR DOWNSTREAM EQUIVALENCE CHECKERS AND GENERATING RECOMMENDATIONS TO IMPROVE RUNTIME OF EQUIVALENCE CHECKERS
Aspects of the present disclosure relate to improving runtime performance of equivalence checkers by a shift left process that uses an RTL lint tool to identify RTL code that can be a source of verification complexity for the downstream equivalence checker. The RTL code is further compared to a corresponding circuit model to determine a potential gate-level location of the potentially problematic RTL code. A weight can be calculated to represent a level of verification complexity that may be generated by the particular portion of the RTL code. Further, one or more recommendations can be generated by the RTL lint tool to prevent some of the verification complexity for the downstream equivalence checker.
G06F 30/33 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
09 - Appareils et instruments scientifiques et électriques
41 - Éducation, divertissements, activités sportives et culturelles
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
Downloadable computer software for electronic design
automation; downloadable computer software for electronic
design automation using artificial intelligence;
downloadable computer software for electronic design
automation in the field of designing of computer logic;
downloadable computer software for use in electronic system
design and integrated circuit design; downloadable computer
software for simulating electronic circuits; downloadable
software for use with application-specific integrated
circuits (ASICs); downloadable computer software for
viewing, modeling, testing, and editing components and
layouts of integrated circuits and semiconductors;
downloadable computer software for integrated circuit
design, manufacturing, manufacturing simulation, and
verification; downloadable computer software for use in
analyzing, designing, manufacturing, and testing of
integrated circuits; downloadable computer software to
assemble, analyze, optimize, de-bug, and improve the
efficiency of design for complex electrical circuits,
namely, system-on-a-chip (SoC) designs; downloadable
computer software for design, development, and verification
of processors, accelerators, and systems-on-chips (SOCs) for
artificial intelligence applications; downloadable computer
software for design and development of computer systems and
software applications; downloadable computer software for
analysis and production of programming code in the field of
software development; downloadable computer software for
visualization of software and design of computer systems;
downloadable computer software utilized by software
developers to search internal software code resources;
downloadable computer software for making internal code
assets searchable at a code-level for developer knowledge
and understanding; downloadable computer software for
integrating microprocessors with embedded systems
applications; downloadable computer software for performing
static timing analysis for integrated circuit design;
downloadable computer software for analyzing electrical
capacitance of electrical circuits; downloadable computer
software for generating models of integrated circuit
libraries; downloadable computer software for design,
analysis, optimization, and generation of models for
electronic circuit fabrication; downloadable computer
software for design and fabrication of printed circuit
boards; downloadable computer software for analysis of
printed circuit boards performance; downloadable computer
software for designing electronic systems wiring and
assembly; computer application software for the design and
deployment of machine learning-based applications;
downloadable artificial intelligence-enabled computer
software applications for design space optimization and
assistance with debugging; software for processing digital
audio; downloadable computer-aided design (CAD) software for
designing and testing integrated circuits; downloadable
computer software for computer-aided design, simulation,
verification, analysis, testing, and developing of the
silicon manufacturing processes of electronic circuits,
integrated circuit, and other semiconductor devices;
downloadable computer software, computer code, databases,
and data files used in, and for use in, the design and
development of semiconductors, electronic circuits, and
integrated circuits; downloadable computer software
development tools; electronic design automation (EDA)
software tools for designing, developing, verifying,
testing, and debugging electronic systems, electronic
circuits, systems on chips (SOCs), integrated circuits,
semiconductors, silicon chips, and microchips; downloadable
electronic design automation (EDA) software tools for
semiconductor device manufacturing process development and
optimization, namely, designing, verifying, simulating,
testing, and debugging semiconductor manufacturing
processes; downloadable computer hardware and software for
system-on-a-chip (SOC) debugging; downloadable computer
hardware and software for computer system and application
development; downloadable computer hardware and software for
hardware and software co-verification and system-level
validation; computer programs for artificial intelligence;
downloadable electronic instruction manuals in the fields of
software, electronic systems, and integrated circuit design;
electronic downloadable publications in the nature of
newsletters, datasheets, technical papers, educational
materials, and white papers in the fields of computer
software, electronic design automation, software
verification, software security, cyber security, software
risk management, integrated circuit design, software design,
software productivity, and chip power management; data
processors; microprocessors; vision processors; vision
processing units (VCUs). Educational services, namely, providing and disseminating
educational and training materials in the fields of computer
software, electronics design and computer security;
educational services, namely, conducting classes, seminars,
webinars, workshops, and classes in the fields of computer
software, software design and development, software
security, software development security, silicon chip design
and verification, semiconductor intellectual property (SIP),
and power management; academic enrichment programs in the
field of computer software, electronic design automation
software, and static analysis software; providing blogs and
non-downloadable publications in the fields of chip design
and verification and intellectual property via a website;
providing online publications in the nature of instruction
manuals for development systems, software libraries,
designs, design specifications and protection systems in the
field of electronic system and integrated circuit design. Consultation services in the field of design, development,
and testing of computer software; consulting services,
namely, providing problem resolution to design level
engineers; consulting services, namely, identifying,
analyzing, and reducing the risks of software failure;
information technology consultation in the field of
microelectronics; technological consultation and advisory
services in the field of microelectronics as it relates to
verification technology; computer software consulting
services to assist the management of intellectual property
risks of the software development process; computer software
consulting services to assist the management of licensing
and compliance risks of the software development and
management process and managing risks associated with the
development, ownership and licensing of software;
development and implementation of software, hardware and
technology solutions for artificial intelligence;
development and implementation of software, hardware and
technology solutions for the purpose of testing and
productization of electronic components and electronic
systems for automobiles; development and implementation of
software, hardware and technology solutions for the design
and deployment of machine learning-based applications;
development, design, and maintenance of computer software
for computer-aided, visual, and photometric development of
products in the automotive field and in industry; design for
others of computer hardware, computer software, and computer
programs all in the field of the development and
verification of microelectronics; integrated circuit,
semiconductor, and electronic circuit design services,
namely, electronic design automation services; providing
temporary use of on-line non-downloadable software for
electronic design automation; software-as-a-service (SaaS)
services featuring software for electronic design
automation; software-as-a-service (SaaS) services featuring
software for electronic design automation using artificial
intelligence; software-as-a-service (SaaS) services
featuring software for integrated circuit design and
verification; software-as-a-service (SaaS) services
featuring software for integrated circuit design and
verification using artificial intelligence;
software-as-a-service (SaaS) services featuring computer
software for development, design, and visualization of
computer systems and software applications;
software-as-a-service (SaaS) services featuring an
artificial neural network software for lithography
correction; software-as-a-service (SaaS) services featuring
artificial intelligence-enabled software applications for
design space optimization and assistance with debugging;
software-as-a-service (SaaS) services featuring software for
monitoring, analysis, and optimization of semiconductor
devices throughout their lifecycle; software-as-a-service
(SaaS) cloud computing technology; cloud computing software
for electronic design automation; cloud computing featuring
software for use in integrated circuit design and
verification; providing virtual computer environments
through cloud computing; providing an Internet website
portal featuring computer software for design and
development of computer systems and software applications;
computer programming and computer program design, namely,
computer simulation based on computer programs to develop
and optimize semiconductor processing technologies and
devices.
91.
Semantic analysis of source code using stubs for external references
A system receives source code for analysis. The system identifies external references to reference code in source code. The reference code is not included in the source code received for analysis. The system generates code stubs corresponding to the external references. Each code stub describes a semantic context for the corresponding external reference. The system provides the set of source code and the one or more code stubs for analysis of the code, for example, using a code analysis tool.
A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.
G06F 30/3315 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant une analyse temporelle statique [STA]
G06F 119/06 - Analyse de puissance ou optimisation de puissance
G06F 119/12 - Analyse temporelle ou optimisation temporelle
Methods for diagnosing faults in memory periphery circuitry, computer readable media, and a test device for the same are provided. In one example, method is provided that includes receiving, at a test device, a first test syndrome from a memory device, the first test syndrome corresponds to a first test process executed by the memory device, wherein the memory device comprises a memory array and peripheral circuitry, and wherein the first test process is associated with a first circuit element of the peripheral circuitry; determining, by a processing device of the test device, a first fault associated with the first circuit element based on the first test syndrome; and diagnosing, by the processing device, the first fault to determine positional information of the first fault, the positional information is associated with the first circuit element.
G11C 29/10 - Algorithmes de test, p. ex. algorithmes par balayage de mémoire [MScan]Configurations de test, p. ex. configurations en damier
G11C 7/06 - Amplificateurs de lectureCircuits associés
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
94.
Using multiple error correction code decoders to store extra data in a memory system
Disclosed is a configuration to store metadata using an error correction code (ECC). The configuration receives at an ECC encoder of a memory controller, write data and an N-bit metadata, N comprising an integer greater than 0. The configuration generates a meta symbol using the N-bit metadata and creates an enhanced write data, the enhanced write data comprising the write data and the meta symbol generated by the N-bit metadata. The configuration encodes the enhanced write data and meta symbol to generate a parity. It deletes the meta symbol to generate an output, the output comprising an enhanced codeword and writes the enhanced codeword to a memory.
H03M 13/03 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source
H03M 13/37 - Méthodes ou techniques de décodage non spécifiques à un type particulier de codage prévu dans les groupes
95.
Accelerating static program analysis with summary reuse
A system performs static program analysis with artifact reuse. The system identifies artifacts associated with the software program being analyzed. The system processes the identified artifacts for performing static program analysis and transmits either the artifacts or identifiers for the artifacts to a second processing device for performing program analysis. The second processing device receives the artifacts and uses the received identifiers to retrieve the artifacts from a networked storage system. The second device also retrieves stored summaries of previous program analysis from the networked storage system. The program analysis uses the retrieved artifacts to generate work units for static program analysis. The analysis is performed only for those work units that are determined to remain unchanged from previous static program analysis cycles.
Disclosed are techniques for simulation of a circuit design using a set of primary signals captured by a hardware emulation system. In preparation for simulation, the circuit design is divided into partitions that are substantially uniform in size. Sequential dependencies are then identified based on signals that cross partitions. The set of primary signals includes signals that, when provided as input to the simulation, break the sequential dependencies such that each partition can be simulated independently. Techniques for determining which signals to include in the set of primary signals are also disclosed. The hardware emulation system is configured to capture values of the primary signals as part of emulating the circuit design. Afterwards, the simulation is performed using the captured values. During the simulation, non-primary signals are reconstructed using values obtained from simulating each partition independently.
Phase detector circuitry includes first mixer circuitry configured to receive a first clock signal and a second clock signal. The first mixer circuitry includes a first plurality of transistors. The first plurality of transistors includes first transistors, second transistors, and an output transistor. The first transistors receive the first clock signal, and the second transistors receive the second clock signal. The first output transistor outputs a first output signal. The first output signal corresponds to a first phase difference between the first clock signal and the second clock signal.
A voltage driver for supplying a supply voltage includes multiple PMOS transistors, multiple NMOS transistors, a pad, impedance divider circuits, NMOS clampers, and PMOS clampers. A maximum of the supply voltage is N times a maximum of the drain-source voltage of each transistor. The pad is configured to receive a voltage signal for dynamically controlling gates of a subset of the NMOS transistors and a subset of the PMOS transistors. The impedance divider circuits are configured to generate limited voltage signals, each of which is a fraction of voltage between the pad and supply voltage or between the pad and ground. The NMOS clampers and PMOS clampers configured to receive reference voltages and limited voltage signals to generate output, which is in turn input into gate terminals of the subset of NMOS or PMOS transistors.
H03K 5/08 - Mise en forme d'impulsions par limitation, par application d'un seuil, par découpage, c.-à-d. par application combinée d'une limitation et d'un seuil
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
In an example, a target design of a metalens is obtained. The target design includes target design meta-atoms. A mask design is generated, by one or more processors, based on area deviations of to-be-fabricated meta-atoms of the metalens relative to the target design meta-atoms. The mask design may be generated using a rule-based correction, such as using a look-up table (LUT), in some examples, and may be generated using a model-based correction in some examples.
G03F 1/36 - Masques à correction d'effets de proximitéLeur préparation, p. ex. procédés de conception à correction d'effets de proximité [OPC optical proximity correction]
G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
100.
One time programmable bitcell with select device in isolated well
A semiconductor memory includes, in part, M×N select transistors disposed along M rows and N columns, where M and N are integers greater than or equal to 2. The memory further includes, in part, a first set of M wells each configured to be biased independently of the remaining M−1 wells. Each well has formed therein N of the select transistors each having a source/drain terminal coupled to the same bitline corresponding to a different one of M bitlines of the memory. The memory further includes, in part, M×N anti-fuses. Each anti-fuse is associated and forms a bitcell with a corresponding one of the M×N select transistors.
G11C 17/16 - Mémoires mortes programmables une seule foisMémoires semi-permanentes, p. ex. cartes d'information pouvant être replacées à la main dans lesquelles le contenu est déterminé en établissant, en rompant ou en modifiant sélectivement les liaisons de connexion par une modification définitive de l'état des éléments de couplage, p. ex. mémoires PROM utilisant des liaisons électriquement fusibles
G11C 17/18 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H10B 20/20 - Dispositifs ROM programmable électriquement [PROM] comprenant des composants à effet de champ
