A method includes determining a plurality of threshold margins corresponding to a plurality of functional paths in an electronic circuit. The method further includes storing the plurality of threshold margins corresponding to the plurality of functional paths in a memory. The method further includes receiving a first trigger from a processing device. The method further includes responsive to receiving the first trigger, monitoring at least one of the plurality of threshold margins corresponding to at least one of the plurality of functional paths in view of a previously determined threshold margin stored in the memory and corresponding to the at least one of the plurality functional paths.
A method of simulating a mixed-signal circuit design, includes, dividing a first circuit disposed in a first level of hierarchy of the circuit design into a multitude of subcircuits. At least a first subcircuit processes an electrical signal, and at a least a second subcircuit processes an optical signal; adding one or more input/output terminals to the first subcircuit to transform the subcircuit into a first subblock; adding one or more input/output terminals to the second subcircuit to transform the second subcircuit into a second subblock; replacing an instance of the first circuit design in a second level of hierarchy of the mixed-signal design with the first and second subblocks; simulating the first subblock in each of the first and second levels of the hierarchy using an electrical circuit simulator; and simulating the second subblock in each of the first and second levels of the hierarchy using an optical simulator.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/38 - Circuit design at the mixed level of analogue and digital signals
3.
Pattern-based hierarchy exploration for compressing an integrated circuit design layout
An integrated circuit (IC) design layout may be partitioned into a set of content areas. A content area in the set of content areas may be divided into a set of zones based on an image-based representation of the content area. A repetition unit may be identified in a zone in the set of zones, where the repetition unit is a portion of the zone, and where the zone includes multiple instances of the repetition unit. A skeleton layout may be generated corresponding to the IC design layout, where the skeleton layout specifies locations of the multiple instances of the repetition unit in the IC design layout.
G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
A testbench for a design under test (DUT) includes components used to verify functionality of the DUT through simulation of the DUT. The components are grouped into component groups, and the components within an individual component group are executed on a same thread of the simulation. The component groups are also executed on a single thread, which includes logging accesses to memory by different component groups. Based on the logged memory accesses, a processing device identifies whether any component groups create a thread data race. An action is taken in response to identifying thread data races.
A method and system are provided for placing cells in a circuit design layout. The method includes placing the cells at candidate locations in the circuit design layout in accordance with design rules, and determining, for each location, a probability of design rule success for the placement of each cell of the cells based on one or more of the available candidate locations.
The processing logic (e.g., a web crawler program) receives a server output from a server hosting a web page and downloads content from the server output. The server output can include embedded resources, including source code files. The processing logic parses the source code and generates a plurality of elements into a data structure as elements. The data structure is made up of multiple elements, each element representing a language construct extracted from the source code. The processing logic can evaluate the elements of the data structure to identify and retrieve request components pertinent. Using the one or more request components retrieved from the data structure, the processing logic can generate server requests. The web crawler will send each server request to the server to receive a subsequent server output and continue the crawl.
Systems and methods for load compensation are presented to support a wide range of capacitive loads on a pad coupled to an I/O transmitter. The I/O transmitter includes I/O architecture coupled to a pad and a calibration circuit coupled to the I/O architecture. The calibration circuit includes sensing circuitry, pulse generation circuitry coupled to the sensing circuitry and control bit generation circuitry coupled to the pulse generation circuitry. The control bit generation circuitry generates control bits proportional to load variations detected at the pad and feeds the control bits to the I/O architecture to modulate rise and fall times of pulsed signals at the pad.
H03K 5/24 - Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
8.
Identifying circuit elements and/or ports for threat analysis and risk assessment
A first set of ports and/or circuit elements in a circuit design may be received, where the first set of ports and/or circuit elements is expected to cause damage if the first set of ports and/or circuit elements is compromised. A second set of ports and/or circuit elements in the circuit design may be determined by performing forward path tracing from the first set of ports and/or circuit elements, backward path tracing from the first set of ports and/or circuit elements, or both forward and backward path tracing from the first set of ports and/or circuit elements. A report may be generated based on the second set of ports and/or circuit elements in the circuit design, where the report is used for performing threat analysis and risk assessment for the circuit design.
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
9.
Signoff-safe multi-corner reduction for static timing analysis
A first set of timing paths may be selected in an integrated circuit (IC) design. A first set of timing slack values may be calculated for the first set of timing paths across a first set of corners. A dominant corner may be selected in the first set of corners based on the first set of timing slack values. A second set of timing slack values for the dominant corner may be determined for a second set of timing paths in the IC design. A third set of timing slack values may be estimated for the second set of timing paths for non-dominant corners. The third set of timing slack values may be used to select a second set of corners for a timing path in the second set of timing paths, and circuit objects in the timing path may be marked with the second set of corners.
A time division multiplexing (TDM) device includes a first first-in-first-out (FIFO) circuit configured to receive a user clock signal and a user data signal from a plurality of inputs, a transmitter circuit operatively coupled to the first FIFO circuit in a fast clock domain, the transmitter circuit including one or more multiplexing state machines, the one or more multiplexing state machines configured to receive a plurality of input signals from the plurality of inputs, multiplexing the input signals to form a multiplexed signal, and transmitting the multiplexed signal using a fast clock, a receiver circuit including one or more demultiplexing state machines, the one or more demultiplexing state machines configured to receive the multiplexed signal, and a second FIFO circuit configured to output the user data signal to the plurality of outputs.
A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops disposed in the logic circuit design to a dual-enable flip-flop configured to operate in response to positive edges of a second clock signal thereby to generate a transformed logic circuit design. The state of the logic circuit design after 2k cycles of the first clock is the same as a state of the transformed logic circuit design after k cycles of the second clock.
An initial polarity associated with an element of an integrated circuit design is determined. Responsive to a determination that an optimization process associated with the integrated circuit design is completed, a current polarity associated with the element is determined. A determination is made that a signal is to be applied at the element based on activity data associated with the integrated circuit design. The signal is associated with a first activity. Responsive to a determination that the current polarity associated with the element does not correspond to the initial polarity associated with the element, the single applied to the element is inverted. The inverted signal is associated with a second activity that is inverted from the first activity.
09 - Scientific and electric apparatus and instruments
35 - Advertising and business services
42 - Scientific, technological and industrial services, research and design
45 - Legal and security services; personal services for individuals.
Goods & Services
Downloadable computer software for simulating chemical and physical interactions between cosmetic, medical, pharmaceutical, food, and beverage products and their packaging as well as generating and validating results for regulatory compliance or certification purposes; downloadable computer software for technical data analysis Business data analysis in the field of cosmetic, medical, pharmaceutical, food, and beverage products; analyzing and compiling business data Providing temporary use of non-downloadable computer software for simulating chemical and physical interactions between cosmetic, medical, pharmaceutical, food, and beverage products and their packaging as well as generating and validating results for regulatory compliance or certification purposes; providing temporary use of non-downloadable computer software for technical data analysis; software-as-a-service (SaaS) services for technical data analysis; software-as-a-service (SaaS) services for simulating chemical and physical interactions between cosmetic, medical, pharmaceutical, food, and beverage products and their packaging as well as generating and validating results for regulatory compliance or certification purposes; testing, analysis, and evaluation of the goods and services of others to determine conformity with certification standards; technical analysis of chemical and physical interactions between cosmetic, medical, pharmaceutical, food, and beverage products and their packaging for scientific and certification purposes Testing, analysis, and evaluation of the goods and services of others to determine regulatory compliance; data analysis of chemical and physical interactions between cosmetic, medical, pharmaceutical, food, and beverage products and their packaging for regulatory purposes
14.
DISTRIBUTED TEST PATTERN GENERATION AND SYNCHRONIZATION
A method for performing an asynchronous automatic test-pattern generation (ATPG) by an ATPG machine includes, in part, generating a set of test patterns; detecting one or more faults associated with the set of test patterns; and receiving, from an ATPG manager, information relating to undetected faults. The method further includes, in part, updating the fault state of the ATPG machine in response to a degree of staleness of a fault state of the ATPG machine determined based at least on the information relating to the undetected faults from the ATPG manager.
A system and method for synthesizing and verifying a circuit design includes receiving a circuit design. An equivalency metric is determined across a first hierarchy and a second hierarchy from hierarchies of the circuit design. The equivalency metric is based on one or more of a combinational element equivalency and a sequential element equivalency across the first hierarchy and the second hierarchy. An updated circuit design is generated by ungrouping the first hierarchy of the hierarchies into the second hierarchy of the hierarchies based on the equivalency metric.
Machine-leaming-aided logic synthesis using do-not-care-based backpropagation, including constructing a neural network (NN) model based on a functional specification of a circuit design, training the NN model to perform a function of the circuit design, where nodes of the neural network perform a first Boolean function (e.g., AND), and where the training comprises do-not-care-based backpropagating, which may include explicitly computing target functions at fanins of the nodes. The NN may be converted to a two-input graph having nodes that represent a second Boolean function (e.g., AND). The function of the circuit design may include a multiplier function, and the graph may include an AND-inverter graph (AIG). A Boolean patch may be constructed to correct an error in the graph.
A circuit including: a memory cell connected to a first power supply configured to supply a first power supply voltage; a first bleeder transistor coupled between a first node of the memory cell and ground; and a second circuit coupled to a gate electrode of the first bleeder transistor and configured to supply a bleeder signal to control the first bleeder transistor in response to a drop in the first power supply voltage, wherein the first bleeder transistor is configured to discharge the memory cell in response to receiving the bleeder signal.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
H10B 10/00 - Static random access memory [SRAM] devices
18.
Pointer information encoded in weighted increment signals
An example non-transitory computer readable medium includes stored instructions which, when executed by a processor, cause the processor to convert an input clockwide pulse received from an upstream circuit running in a first clock domain into an output clockwide pulse that is synchronized to a second clock domain. The instructions further cause the processor to advance a count in response to the output clockwide pulse that is synchronized to the second clock domain.
Design metrics from the physical design of an integrated circuit are made available to the front end designer. Physical design metrics are computed for sub-circuits from the physical design of an integrated circuit. Examples of physical design metrics include metrics for timing, congestion, power consumption and other metrics that depend on physical aspects of the circuit. Correspondence between the sub-circuits and register transfer level (RTL) source elements from RTL source code for the integrated circuit are determined. Examples of RTL source elements include individual lines of RTL source code, modules in the RTL source code, and user-defined constructs in the RTL source code. For different RTL source elements, the physical design metrics for the corresponding sub-circuits are aggregated. These aggregated physical design metrics, including the associations to the corresponding RTL source elements, are made available to users, for example front end designers.
In one example, a method includes converting source code for a register transfer level design into a directed graph, acquiring a first violation generated by analyzing the source code, identifying a violation statement subgraph associated with the first violation in the directed graph, extracting a reduced subgraph representing the first violation from the directed graph, wherein the violation statement subgraph comprises a starting point for the reduced subgraph, converting the reduced subgraph to a first vector, calculating a graph similarity between the first vector and a second vector representing a second violation for the source code for which an existing waiver has been generated, determining, by a processing device, that the graph similarity satisfies a threshold similarity, and generating, in response to the determining, a waiver for the first violation.
The present disclosure describes a computer system for generating test code. According to an embodiment, the computer system includes one or more memories and one or more processors communicatively coupled to the one or more memories. The one or more processors, individually or collectively, parse software code to determine a function in the software code, generate a prompt based on the function, generate, using a machine learning model and based on the prompt, test code for testing the function, and execute the test code to generate a crash.
Built-in self-test (BIST) may be run on a set of circuits in proximity to a circuit under test (CUT) in an integrated circuit (IC) chip to generate noise and voltage drop conditions in the CUT. BIST may be run on the CUT while BIST is running on the set of circuits. A result of running the BIST on the CUT may be determined. The result may be associated with the noise and voltage drop conditions.
At least one processor may obtain a plurality of test pattern data sets for a plurality of cores of an integrated circuit to be applied via a shared testing input bus. The at least one processor may next generate a test data sequence including an interleaving of respective task procedures of the plurality of test pattern data sets, where the generating of the test data sequence includes generating sleep instructions for respective cores of the plurality of cores in accordance with the interleaving. The at least one processor may then apply the test data sequence via the shared testing input bus.
In some aspects, timing metrics for timing paths of a circuit design are accessed. These timing metrics were evaluated at a first temperature. The circuit design includes multiple components. Location-dependent temperature information for the components and a thermal derate schedule are also accessed. The thermal derate schedule specifies adjustments to timing metrics as a function of temperature. A processing device adjusts the timing metrics based on the thermal derate schedule and based on differences between the first temperature and the location-dependent temperature information for the respective components of the circuit design.
The present disclosure describes a computer system for generating test code. According to an embodiment, the computer system includes one or more memories and one or more processors communicatively coupled to the one or more memories. The one or more processors, individually or collectively, parse software code to determine a function in the software code, generate a prompt based on the function, generate, using a machine learning model and based on the prompt, test code for testing the function, and execute the test code to generate a crash.
An example is a method. A first logical value is written to a latch node of a latch circuit of a half static random access memory (SRAM) cell. A second logical value is read from the latch node. The latch circuit is non-inverter-based. The latch circuit includes a p-type transistor and an n-type transistor. A drain node of the p-type transistor is electrically connected to a gate node of the n-type transistor, and a drain node of the n-type transistor is electrically connected to a gate node of the p-type transistor. According to some examples, the half SRAM cell may be implemented as a storage node, for a physical unclonable function (PUF), and/or for data padding.
Shadow application programming interface (API) endpoints are detected within a software application by obtaining API documentation and an implemented API endpoint for the software application. The implemented API endpoint is obtained during an implementation of the software application. API endpoint is generated comparison data from the API documentation. Further, an indication of whether the implemented API endpoint is a shadow API endpoint is determined based on a comparison of the API endpoint comparison data with the implemented API endpoint. The indication is output.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
A system and method for performing digital calibration of non-linearity in a circuit is presented. The circuit includes a phase detector, a statistics gathering device, and a feedback device. The phase detector provides information regarding a relationship between a clock from the programmable clock phase circuit and a reference signal. The statistics gathering device is coupled to the phase detector. The statistics gathering device receives an output of the phase detector to measure linearity of the programmable clock phase circuit. The feedback device is coupled to the statistics gathering device. The feedback device controls a delay and adjusts a phase of the clock based on measured values received from the statistics gathering device.
H04L 7/033 - Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal- generating means, e.g. using a phase-locked loop
29.
GRAPH-BASED VISUALIZATION OF WAYPOINT FOR DETECTING DESIGN ERROR IN INTEGRATED CIRCUIT DESIGN
A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.
A non-transitory computer readable medium includes stored instructions, which when executed by a processor, cause the processor to acquire a plurality of graphs that model results of a plurality of bug hunting searches for a register transfer level design, wherein the plurality of bug hunting searches determines a design error in the register transfer level design, construct a composite graph using the plurality of graphs, wherein the composite graph models a plurality of causal relationships between a plurality of detected bugs and a plurality of helper properties covered by the plurality of bug hunting searches, and execute an additional bug hunting search whose parameters are configured based on the composite graph.
Some aspects utilize an iterative process to synthesis a logic network within an ASIC using lookup table (LUT) optimization techniques. The logic network may be represented by an And-Inverter graph (AIG), as described in more detail below. On each iteration, the current AIG representation of the logic network is mapped to a network of k-LUTs. A k-LUT is a lookup table that can represent any function of k variables. This network may then be improved using LUT optimization techniques. The improved network of k-LUTs is decomposed into a trial AIG representation, which may be further improved for example by applying Boolean-based optimization techniques. The current AIG representation may then be updated in accordance with the quality of the trial AIG representation produced by the current iteration. The final AIG representation from the iterations is synthesized to a netlist of standard cells.
Logic verification of superconducting electronic circuits is implemented as follows. The superconducting electronic circuit is supposed to implement a desired logic function. A description of the circuit includes a plurality of nodes of the circuit, including one or more input nodes and one or more output nodes. Operation of the superconducting electronic circuit is simulated, including probing signal values at the nodes. These signal values are converted to state transitions of the quantum phase at the nodes (phase state transitions). The phase state transitions are related to the logic values represented by the circuit. The phase state transitions are compared with the desired phase state transitions for the desired logic function. Based on this comparison, it is determined whether the superconducting electronic circuit implements the desired logic function.
A method includes receiving, by a processing device, receiving a data file, dividing the data file into a plurality of partitions based on a defined criteria, compiling the plurality of partitions associated with the data file to form a plurality of compiled partitions, generating a status identifier for each of the plurality of partitions, wherein the status identifier reflects a current version of a corresponding partition. The method further includes combining the plurality of compiled partitions to form a first executable file, and storing the plurality of compiled partitions and a corresponding status identifier for each of the plurality of compiled partitions in a first storage area of a first storage medium. The method also includes receiving a request for the data file, identifying that one or more partitions of the plurality of partitions is reusable, and sending the one or more partitions identified as being reusable.
A method or system for processing a specification document associated with a circuit design to identify design requirements. The method includes receiving a specification document associated with a circuit design, and processing the specification document to identify at least one of a text component, a table component, or a finite state machine (FSM). After that, the text component is parsed by a first parser to identify a first set of design requirements. The table component is parsed by a second parser to identify a second set of design requirements. The FSM component is parsed by a third parser to identify a third set of design requirements. The identified first, second, and/or third set of design requirements are then provided for display to a user for review.
Techniques for non-retention mode leakage reduction without impacting cell content in a retention mode. A plurality of power gate circuits provide power to respective regions of memory cells. The power gate circuits may be placed physically proximate to the respective regions of the memory cells, and the control circuitry may be placed in a central location of the circuit. The power gate circuits include respective first and second series-connected transistors. Threshold voltages of the first transistors may be less than threshold voltages of the respective second transistors. The first transistors may be controlled independent of the respective second transistors. A third transistor may diode-connect the first transistors, or a subset thereof, in a retention mode. The power gate circuits may include multiple individually controllable first transistors in parallel with one another.
G11C 11/40 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors
G11C 11/4072 - Circuits for initialization, powering up or down, clearing memory or presetting
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
A circuit. In some embodiments, the circuit includes: a first pair of transistors, configured as a cross-coupled pair of transistors; a second pair of transistors, configured as another cross-coupled pair of transistors; and a first series combination of one or more voltage clamping transistors. A first transistor of the first pair of transistors may have a current-carrying terminal electrically coupled to a first end terminal of the first series combination of one or more voltage clamping transistors, and a first transistor of the second pair of transistors may have a first current-carrying terminal electrically coupled to a second end terminal of the first series combination of one or more voltage clamping transistors.
H03K 3/011 - Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A circuit includes a control circuit branch and a discharge circuit branch. The control circuit branch is electrically coupled between a control input node and a negative node. The control circuit branch includes a p-type transistor (MP), a diode, and a first n-type transistor (MN1). A source node of MP is electrically coupled to the control input node. The diode has an anode and a cathode. The anode is electrically coupled to a drain node of MP. A drain node of MN1 is electrically coupled to the cathode. A source node of MN1 is electrically coupled to the negative node. The discharge circuit branch is electrically coupled between the negative node and a discharge node. The discharge circuit branch includes a second n-type transistor (MN2). A drain node of MN2 is electrically coupled to the negative node. A gate node of MN2 is electrically coupled to the cathode.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
38.
Connectivity controller with enhanced throughput in an embedded system
A computing system includes, in part, a host controller and a device controller. The host controller is configured to comply with a connectivity standard and includes, in part, a host protocol layer, a host link layer, and a host register. The device controller is configured to communicate with the host controller in conformity with the connectivity standard. The device controller includes, in part, a device protocol layer, a device link layer, and a device register. In response to the device register being set, the device link layer is inhibited from performing an integrity check on a packet received from the host link layer and using a first cyclic redundancy check (CRC) value of the first packet. The CRC value is computed by and disposed in the first packet by the host link layer.
A method includes generating a plurality of intermediate designs for a chip by executing a first sub-step based on a first plurality of inputs, adding at least one intermediate design of the plurality of intermediate designs to a second plurality of inputs, generating a plurality of final designs by executing a second sub-step of the step of the design flow based on the second plurality of inputs, and selecting using a machine learning model a final design from the plurality of final designs. The first sub-step is a sub-step of a step of a design flow and the first plurality of inputs corresponds to input parameters associated with the first sub-step.
G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
42 - Scientific, technological and industrial services, research and design
Goods & Services
Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for security testing and vulnerability management; Software as a service (SAAS) services featuring artificial intelligence-enabled software applications for security testing and vulnerability management in connection with Model Context Protocol (MCP) integrations; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for use in identifying, verifying, analyzing, testing, and improving software application vulnerabilities; Providing online non-downloadable agentic software for use in identifying, verifying, analyzing, testing, and improving software application vulnerabilities; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for identifying computer software defects, ensuring compliance, and analyzing software applications and computer code; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for security testing of web-based software applications; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for analyzing software composition for the purpose of managing risk from use of open source and third-party software code in software applications and containers; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for the purpose of application security management to scale testing, remediation, and risk management; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for the purpose of discovering and remediating security weaknesses; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for detection of security threats and vulnerabilities in computer code; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for conducting computer software audits and reporting the results of such audits; Consultation services in the field of design, development, and testing of computer code; Computer software consulting services in the field of application development, code review, and computer security; Computer security consultation in the field of monitoring, analyzing, scanning and testing computer code using artificial intelligence
42 - Scientific, technological and industrial services, research and design
Goods & Services
Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for security testing and vulnerability management; Software as a service (SAAS) services featuring artificial intelligence-enabled software applications for security testing and vulnerability management in connection with Model Context Protocol (MCP) integrations; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for use in identifying, verifying, analyzing, testing, and improving software application vulnerabilities; Providing online non-downloadable agentic software for use in identifying, verifying, analyzing, testing, and improving software application vulnerabilities; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for identifying computer software defects, ensuring compliance, and analyzing software applications and computer code; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for security testing of web-based software applications; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for analyzing software composition for the purpose of managing risk from use of open source and third-party software code in software applications and containers; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for the purpose of application security management to scale testing, remediation, and risk management; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for the purpose of discovering and remediating security weaknesses; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for detection of security threats and vulnerabilities in computer code; Software as a service (SaaS) services featuring artificial intelligence-enabled software applications for conducting computer software audits and reporting the results of such audits; Consultation services in the field of design, development, and testing of computer code; Computer software consulting services in the field of application development, code review, and computer security; Computer security consultation in the field of monitoring, analyzing, scanning and testing computer code using artificial intelligence
42.
Resonance mitigation for a system-on-chip memory subsystem
A processing device identifies a repeated memory access pattern in a memory access stream of a memory subsystem, the repeated memory access pattern having a memory access pattern frequency, and determines an accumulated value associated with the repeated memory access pattern. The processing device further determines whether the accumulated value satisfies a threshold criterion associated with the memory access pattern frequency, and responsive to determining that the accumulated value satisfies the threshold criterion, causes a delay period to be introduced to the memory access stream to break the repeated memory access pattern.
A circuit design may be partitioned into a set of regions. Regions in the set of regions that are substantially identical to one another may be identified and overlaps between the set of regions may be determined. A scanning plan may be created based on the set of regions, the regions in the set of regions that are substantially identical to one another, and the overlaps between the set of regions. The scanning plan may be provided to an OWI system which inspects a set of dies fabricated based on the circuit design. A scan result may be received from the OWI system based on inspecting a die in the set of dies. A defect location in the die may be identified based on the scan result and the scanning plan.
A system includes a MAC layer and a PCS in communication with the MAC layer via a transmit data path. The transmit data path includes a data request signal transmitted from the PCS to the MAC layer and a data valid signal transmitted from the MAC layer to the PCS. A SYNC pipeline of the PCS generates a copy of the data valid signal that has a same timing as the data valid signal. When the data valid signal from the MAC layer to the PCS matches the copy of the data valid signal generated by the PCS, the PCS is in synchronization with the MAC layer. When the data valid signal from the MAC layer to the PCS does not match the copy of the data valid signal, the PCS ignores input data from the MAC layer and generates an idle symbol to a link partner.
H04L 1/00 - Arrangements for detecting or preventing errors in the information received
H04L 1/16 - Arrangements for detecting or preventing errors in the information received by using return channel in which the return channel carries supervisory signals, e.g. repetition request signals
H04L 43/0817 - Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking functioning
A circuit includes a first PMOS having a source coupled to a supply voltage and a gate coupled to a first bitline of a first memory cell; a second PMOS having a source coupled to the supply voltage and a gate coupled to a second bitline of a second memory cell; a first NMOS having a drain coupled to drains of the first and second PMOS transistors and a gate coupled to the first bitline; a second NMOS having a drain coupled to a source of the first NMOS and a gate coupled to the second bitline; a third PMOS precharging the first bitline to the supply voltage in response to a first precharge signal; and a fourth PMOS precharging the second bitline to the supply voltage in response to a second precharge signal. In response to the first and second precharge signals, the ground terminal is caused to float.
An integrated circuit (IC) design may be received by a first process. First reset domain crossing (RDC) analysis may be performed by the first process on the IC design to generate first RDC analysis results. A set of processes may be spawned by the first process, where a second process in the set of processes may read the first RDC analysis results, obtain information for an RDC scenario from the first process, perform second RDC analysis on the IC design based on the information for the RDC scenario to obtain second RDC analysis results, and send the second RDC analysis results to the first process. The second RDC analysis results received from the set of processes may be merged by the first process to obtain merged RDC analysis results.
Systems and methods for fault simulation are presented to reduce computation processing. A system includes a memory and a processor, operatively coupled to the memory, to perform fault simulation by injecting a plurality of faults into an IC model, initiating a concurrent fault simulation for all of the plurality of faults injected into the IC model, identifying at least one fault of the plurality of faults that is unable to be implemented by the concurrent fault simulation, and initiating a single fault simulation to process the at least one fault unable to be implemented by the concurrent fault simulation without interrupting the concurrent fault simulation from processing other faults of the plurality of faults. The at least one fault from the concurrent fault simulation is immediately discarded and the fault results from the concurrent fault simulation and the single fault simulation are combined upon completion of both simulations.
A computer-implemented method for validation of a low-power design for an electronic circuit. The method includes accessing, by a processing device, the low-power design of the electronic circuit including one or more low-power elements. The method further includes selecting, from the design of the electronic circuit, a domain and a power activity, and enabling an assertion component configured to control the one or more low-power elements in the domain, the low-power elements performing the power activity.
Analysis may be performed on hardware description language (HDL) code to identify a violation, where the HDL code may describe an IC design, and where the violation may specify a line in the HDL code. The HDL code may be parsed to obtain a digital representation of the IC design. Connectivity information and semantic information of objects in the digital representation may be determined. A first object in the digital representation may be determined which corresponds to the line in the HDL code. The connectivity information and the semantic information may be used to identify a set of objects in the digital representation which are related to the first object. A set of lines in the HDL code may be selected which correspond to the set of objects in the digital representation.
Analysis may be performed on hardware description language (HDL) code to identify a violation, where the HDL code may describe an IC design, and where the violation may specify a line in the HDL code. The HDL code may be parsed to obtain a digital representation of the IC design. Connectivity information and semantic information of objects in the digital representation may be determined. A first object in the digital representation may be determined which corresponds to the line in the HDL code. The connectivity information and the semantic information may be used to identify a set of objects in the digital representation which are related to the first object. A set of lines in the HDL code may be selected which correspond to the set of objects in the digital representation.
Preemptive stoppage of design clocks for processing blocking direct programming interface (DPI) calls is described. A blocking DPI call is received at a first field programable gate array (FPGA) of a plurality of FPGAs of an emulation system. The DPI call is received at a system clock cycle, K, of a system clock of the emulation system. Prior to the first FPGA calling the blocking DPI call, an amount of delay, N, associated with the blocking task is determined. The emulation system performs operations to communicate a stop clock instruction to each of a set of FPGAs of the plurality of FPGAs such that design clocks of each of the set of FPGAs are stopped in unison at a system clock cycle of K+N. The emulation system calls the blocking task at a system clock cycle of K+N+1.
An integrated circuit includes a configurable delay chain, which contains a chain of binary delay blocks. Each binary delay block includes the following. Inputs receive an input signal, a select signal and a test control signal. A delay branch transmits the input signal with a delay, and a bypass branch transmits the input signal without the delay. Selector circuitry is connected to the delay branch and to the bypass branch. The selector circuitry selects either the delay branch or the bypass branch according to the select signal. According to the test control signal, test circuitry produces a test signal to test the selector circuitry.
H03K 5/133 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices
G01R 31/3185 - Reconfiguring for testing, e.g. LSSD, partitioning
H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
H03K 19/20 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
A circuit may include a first circuit, a second circuit, and a third circuit. The first circuit may generate a first set of channel state vectors corresponding to a communication channel, where each channel state vector in the first set of channel state vectors includes a set of channel state indices, and where each channel state index corresponds to a sequence of decoded symbols received over the communication channel. The second circuit may combine a first channel state vector and a second channel state vector in the first set of channel state vectors to obtain a combined channel state vector. The third circuit may select a first channel state index in the combined channel state vector based on a second channel state index.
A layout is used in a computational lithography process. For example, the layout may be the layout of the lithographic mask or the layout of the desired resist shape. The layout is made up of multiple disjoint shapes. At least some of the disjoint shapes are represented by parametric curve representations, rather than polygons or other rectilinear representations. The parametric curve representations of the shapes are then used in the computational lithography process.
G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
Methods and apparatus for obtaining timing adjustment values for clock points in a clock network are disclosed. In some embodiments, engineering change order (ECO) may be performed in a time- and resource-efficient manner by selecting candidate clock points from a plurality of clock points in the clock network, and performing enumerative and iterative tests on the selected candidate clock points to determine a combination of timing delay adjustment values that most reduces negative slack. The determined timing delay adjustment values may be implemented by an ECO system to effect changes to the clock network and reduce timing violations therein.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
09 - Scientific and electric apparatus and instruments
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57.
Dual-error correcting code (ECC) for metadata in memory system
Error correcting first uncorrected data according to a first error correcting code produces first corrected data and an indicator of whether a device failure is detected. Responsive to the indicator indicating that a device failure is detected, error correcting second uncorrected data according to (1) a second error correcting code and (2) an erasure decoding mode, and using an identification of a failing device produced by the error correcting of the first uncorrected data.
G06F 11/08 - Error detection or correction by redundancy in data representation, e.g. by using checking codes
H03M 13/15 - Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
58.
Maximizing detectable defect coverage of analog circuits in integrated circuit design
A system and method are provided for detectability analysis to identify defective analog components of a circuit. The method includes applying detectability analysis stimuli to the circuit for the purpose of identifying all detectable defects within a defect universe of the circuit, the defect universe including all actual, and potentially undetectable, defects in the circuit, and the applying resulting in an identification of first defects, which is a subset of all of the actual defects within the defect universe. The method further includes applying a user defect analysis to the circuit to identify second defects, which is a subset of all of the actual defects within the defect universe, determining defects, from the first defects, that are not included in the second defects to be not-covered (NC) defects, grouping the NC defects into clusters, and providing the grouped NC defects as a result of the defect detectability analysis.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
59.
Interposer routing for universal chiplet interconnect express™ channels by partitioning into subchannels
A description of an interconnect channel within an interposer (such as a Universal Chiplet Interconnect Express™ (UCIe) channel) includes first bump locations for a first interface to the interconnect channel on a first die, second bump locations for a second interface to the interconnect channel on a second die, and nets connecting corresponding first and second bump locations for the two interfaces on the two dies. A processing device partitions the interconnect channel into subchannels. The subchannels include corresponding clusters of first and second bump locations connected by nets. The bounding boxes for the subchannels are non-overlapping. For each subchannel, the nets within the subchannel are routed.
A computer-implemented method for performing static noise analysis in an electronic design of an integrated circuit includes accessing, by a processing device, the electronic design including a plurality of voltage domains, wherein each voltage domain includes one or more functional elements and one or more domain voltages. The method further includes performing a timing analysis of the electronic design and determining respective signal arrival timing windows for the one or more functional elements in the electronic design. The method further includes generating a noise waveform at a first functional element based on the signal arrival timing windows and slews of aggressor nets of a first functional element in a first voltage domain of the plurality of voltage domains. The method further includes determining a number of noise waveforms reaching a second functional element in a second voltage domain based on the plurality of voltage domains and the one or more domain voltages in the plurality of voltage domains, and propagating at least one noise waveform of the number of noise waveforms to the second functional element.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A device includes a processing device, a set of local resources coupled to the processing device, a plurality of parent interfaces, and a plurality of child interfaces. Each parent interface and each child interface is configured to couple the processing device to a respective node residing outside of the device when selected. The processing device is to select one parent interface, such that a selection of the one parent interface causes the respective node coupled to the one parent interface to operate as a parent of the processing device. The processing device is to further select one child interface, such that a selection of the one child interface causes the processing device to operate as a parent of the respective node coupled to the one child interface.
A method and circuit are provided for maintaining an operating voltage on a selected column with a plurality of bitcells in a memory when writing to the selected column. The method includes during an active write operation to the selected column, implementing an NMOS transistor NC to allow a bitcell-supply self-discharge (BSSD) to occur on the selected column, wherein the BSSD occurs by connecting a first drain voltage to an operating voltage connection of the selected column via the NMOS transistor NC to allow discharge of the operating voltage connection while limiting over-discharge of the selected column. The method further includes a PMOS select transistor PS to connect a second drain voltage to the operating voltage connection of the unselected column.
A method includes: executing, on a host computer including a host processor and host memory, a hypervisor managing a virtual machine including a virtual processor and virtual machine memory, the virtual machine executing a guest program stored in the virtual machine memory, the guest program including machine instructions; disabling, by the hypervisor, execute permissions on a first page of the virtual machine memory; and handling, by the hypervisor, a first abort triggered when the virtual processor executes an instruction in the first page of the virtual machine memory having an execute permission disabled including: replacing, by the hypervisor, one or more instructions in the first page of the virtual machine memory; disabling read and write permissions and enabling an execute permission in a first entry of a page table corresponding to the first page of the virtual machine memory; and resuming execution of the guest program on the virtual processor.
th time-to-digital convert unit. The data terminal of the flip-flop of each time-to-digital converter unit is responsive to the first pulse, and the clock terminal of the flip-flop of each time-to-digital converter unit is responsive to the first signal.
In an example, a pre-solution state and other attributes of each constraint problem (CP) in a first series of constraint problems (CPs) solved by a constraint solver are recorded during a first simulation run with a first testbench. The recorded attributes are mapped to at least one key value set of a plurality of key value sets. Each key value set uses a different level of generalization to represent the recorded attributes. A matching CP from the first series is determined for each CP in a second series of CPs to be solved during a second simulation run with a second testbench. The matching CP is mapped to a key value set that uses a lower level of generalization to represent the matching CP's recorded attributes relative to other key value sets. A pre-solution state of each CP in the second series is set to that of the matching CP.
A method includes: executing, on a host computer including a host processor and host memory, a hypervisor managing a virtual machine including a virtual processor and virtual machine memory, the virtual machine executing a guest program stored in the virtual machine memory, the guest program including machine instructions; disabling, by the hypervisor, execute permissions on a first page of the virtual machine memory; and handling, by the hypervisor, a first abort triggered when the virtual processor executes an instruction in the first page of the virtual machine memory having an execute permission disabled including: replacing, by the hypervisor, one or more instructions in the first page of the virtual machine memory; disabling read and write permissions and enabling an execute permission in a first entry of a page table corresponding to the first page of the virtual machine memory; and resuming execution of the guest program on the virtual processor.
A computer-implemented method of predicting a branch direction of a fetch block in a processor, includes in part, determining a multitude of first counts each associated with a different one of a multitude of branch offsets of a branch direction predictor data associated with the fetch block. Each of the multitude of first counts represents the number of times that the associated branch offset was taken during a multitude of fetch cycles. The computer-implemented method further includes, in part, determining a second count associated with the fetch block. The second count represents the number of times that none of the multitude of branch offsets were taken during the multitude of fetch cycles. The computer-implemented method further includes, in part, computing a confidence level based on the multitude of first counts and the second count, and determining the branch direction of the fetch block in accordance with the computed confidence level.
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70.
Local Oxidation for Three-Dimensional Dynamic Random Access Memory Transistor
A method may include operations associated with providing a stack of layers, the layers separated by a dielectric between the layers, each layer comprising a plurality of unit cells separated by the dielectric between the plurality of unit cells, each unit cell including a silicon channel, a gate oxide surrounding the silicon channel in at least two dimensions, and a gate metal surrounding the gate oxide in the at least two dimensions, the operations including recess etching to remove a portion of the gate metal in each unit cell and applying an oxide growth process to the gate oxide in each unit cell.
A computer-implemented method of predicting a branch direction of a fetch block in a processor, includes in part, determining a multitude of first counts each associated with a different one of a multitude of branch offsets of a branch direction predictor data associated with the fetch block. Each of the multitude of first counts represents the number of times that the associated branch offset was taken during a multitude of fetch cycles. The computer-implemented method further includes, in part, determining a second count associated with the fetch block. The second count represents the number of times that none of the multitude of branch offsets were taken during the multitude of fetch cycles. The computer-implemented method further includes, in part, computing a confidence level based on the multitude of first counts and the second count, and determining the branch direction of the fetch block in accordance with the computed confidence level.
A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.
A memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device in the feedback loop between an output of the second inverter and an input of the first inverter. An additional memory device may include first and second inverters cross-coupled in a feedback loop, a first access transistor for a first node of the feedback loop, a second access transistor for a second node of the feedback loop, where the first node and the second node are to store complementary binary data bit values, and a bidirectional threshold switching device between the first access transistor and the first node.
G11C 11/412 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
G11C 7/02 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
G11C 8/16 - Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
Cells in a superconducting electronics (SCE) netlist may be levelized. The SCE may use multiple clock phases, and each level in the levelized SCE netlist may be associated with a clock phase. Buffers may be inserted in the SCE netlist so that output ports of the SCE netlist are associated with the same clock phase. A floorplan may be created for the SCE netlist. A placed SCE netlist may be generated based on the floorplan, where cells in each row of the placed SCE netlist may be clocked using the same clock phase.
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of software and design of computer systems; software as a
service (SaaS) services featuring software for security
testing and vulnerability management; software-as-a-service
(SaaS) services featuring software for testing software and
benchmarking software reliability; software as a service
(SaaS) services featuring software for identifying,
verifying, testing and repairing defects in software code;
software as a service (SaaS) services featuring software for
identifying vulnerabilities in software supply chain;
software as a service (SaaS) services featuring software in
the field of security testing of web-based software
applications; software as a service (SaaS) services
featuring software in the field of security testing of
computer application software for mobile phones; software as
a service (SaaS) services featuring software for automated
dynamic application security testing; software as a service
(SaaS) services featuring software for analyzing software
composition for the purpose of managing risk from use of
open source and third-party software code in software
applications and containers; software as a service (SaaS)
services featuring software for the purpose of application
security management to scale testing, remediation, and risk
management; software as a service (SaaS) services featuring
software for the purpose of discovering and remediating
security weaknesses; software as a service (SaaS) services
featuring software for automatic detection of security
threats and vulnerabilities in computer software; software
as a service (SaaS) services featuring software for use in
scanning, reviewing, evaluating and reporting on the
composition and components of other computers for
identifying, tracking and managing of software assets and
use of third party software, or to ensure compliance with
industry, legal or governmental regulations by businesses
and institutions; software as a service (SaaS) services
featuring software for use in comparing individual software
components to databases of known software sources in order
to evaluate and categorize such components and identify the
source of such components; software as a service (SaaS)
services featuring software for conducting computer software
audits and reporting the results of such audits; platform as
a service (PaaS) services featuring computer software
platforms for use in testing computer software applications
or systems and identifying security vulnerabilities by
emulating conditions that cause exceptions or crashes in
software functionality; hosting and maintenance of online
searchable computer databases, namely, providing an on-line
searchable database in the field of open source code (term
considered too vague by the International Bureau pursuant to
Rule 13 (2) (b) of the Regulations); providing a website
that features information on computer technology, computer
programming and software security directed to open source
programmers and developers (term considered too vague by the
International Bureau pursuant to Rule 13 (2) (b) of the
Regulations); providing an Internet website portal in the
field of computer application development environments and
tools, namely, testing and evaluation of software, software
containing open source code, and software applications for
interoperability and compliance with industry standards and
established policies and standards (term considered too
vague by the International Bureau pursuant to Rule 13 (2)
(b) of the Regulations); computer services, namely,
providing a website featuring technology that enables access
to graphic user interfaces for developers of open source
projects (term considered too vague by the International
Bureau pursuant to Rule 13 (2) (b) of the Regulations);
consultation services in the field of design, development,
and testing of computer software; consultation services in
the field of software security risk assessment, namely,
identification of security weaknesses in software design for
purposes of understanding secure design practices,
developing and planning software security strategy,
mitigating security flaws, meeting organizational compliance
mandates, and addressing business risks; consultation
services in the field of software security risk assessment,
namely, scanning, penetration, and network testing to assess
security vulnerabilities; software consultation services
relating to identifying, analyzing and reducing the risks of
software failure; computer software consulting services in
the field of application development, code review, computer
security, software architecture analysis; computer software
consulting services to assist the management of licensing
and compliance risks of the software development and
management process and managing risks associated with the
development, ownership and licensing of software; computer
systems analysis, namely, reviewing, evaluating and
reporting on the composition and components of computer
software on the computer systems of others in order to
assist businesses and government organizations in
identifying, tracking and managing their software assets and
use of third party software, or to ensure compliance with
industry, legal or governmental regulations; computer
software auditing services in the nature of assessing open
source, legal, compliance, security, and quality risks;
computer services, namely, conducting software audits using
proprietary software to scan the software of others in order
to detect and report on the software content found within,
and evaluating and reporting the results of such audits in
the nature of computer systems analysis; computer software
consultation services in connection with conducting software
audits and implementing best practices in the
identification, tracking and management of software assets
and the use of third party software; computer services,
namely, providing computer software and application
programming consulting services; computer services, namely,
providing an Internet website portal in the fields of
technology and software development for tracking and
analyzing computer software development (term considered too
vague by the International Bureau pursuant to Rule 13 (2)
(b) of the Regulations); computer security consultation in
the field of monitoring and testing computer systems;
consulting and technical support services, namely, providing
technical advice related to software testing, control and
analysis; technical support services, namely, reporting and
monitoring of open source vulnerabilities in software
application development; technical support services, namely,
troubleshooting in the nature of diagnosing computer
software and hardware problems.
76.
Performing timing constraint equivalence checking on circuit designs
A first set of timing relationships may be determined in a first circuit design based on a first set of timing constraints specified for the first circuit design. A second set of timing relationships may be determined in a second circuit design based on a second set of timing constraints specified for the second circuit design. The first set of timing relationships may be compared with the second set of timing relationships to obtain a comparison result. Equivalency between the first set of timing constraints and the second set of timing constraints may be determined based on the comparison result.
G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Techniques for determining a density of through-silicon vias (TSVs) in a three-dimensional (3D) stacked die are disclosed. In some embodiments, such techniques may include obtaining first power consumption information associated with a first die of the 3D stacked die; obtaining second power consumption information associated with a second die of the 3D stacked die; identifying, on the first die, an area associated with the second die, the identified area overlapping an area associated with the first die; and determining a density of TSVs for the identified area based at least on the first power consumption information and the second power consumption information.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A Gray code counter is enabled to increment by greater than one and still obey a rule of only one bit of change. The Gray code counter has applicability, for example, with use with an arbiter to control a multi-input asynchronous FIFO usable to synchronize data transfers between asynchronous source and destination clock domains.
G06F 1/12 - Synchronisation of different clock signals
G06F 5/10 - Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
79.
In-situ function parameter search space filtering for machine learning in electronic design automation
A set of parameter values may be generated by a machine learning (ML) model, where the set of parameter values may be used by a black-box function to generate a set of outputs based on a set of inputs. It may be determined whether the set of parameter values is expected to cause the set of outputs generated by the black-box function to violate one or more desired goals. If so, a first response may be provided to the ML model that discourages the ML model from generating sets of parameter values that are similar to the set of parameter values. Otherwise, the set of parameter values may be provided to the black-box function, a second response may be determined based on the set of outputs generated by the black-box function, and the second response may be provided to the ML model.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
A memory cell with dynamic disturb reduction includes first and second inverters in a cross-coupled arrangement, a write circuit to write to the memory cell, a read circuit to read the memory cell, and an interrupt circuit to disable at least a portion of the first inverter when the read circuit reads the memory cell.
A method or system for clock gating verification of a circuit design. The system identifies a set of sequential components of the circuit design, and a set of nets of the circuit design. Each net is configured to provide a signal to a clock pin of a sequential component. The system then identifies a subset of nets that are associated with toggle signals, each of which transitions between two different signal values. For each of the subset of nets, the system determines one or more toggle cover properties. The system also determines a depth of at least one net in the subset of nets, and performs sign off for the clock gating verification based on the toggle cover properties and the depth of the at least one net.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
A method of performing static verification of a circuit design that includes a number of circuit blocks, includes, in part, receiving a first model of a first block generated using a first version of a verification tool and having associated therewith data representative of a version number of each of a multitude of verification tests performed by the first version of the tool as well as associated first setup information. In response to the determination that, for each of the of tests performed, the version number of the test to be run on the circuit design is incompatible with the version number of the test performed by the first version of the tool, portions of the first model that were tested with the version number(s) of the test(s) determined to be incompatible with the version number(s) of the test(s) to be run on the circuit design are regenerated.
A method includes: receiving an integrated circuit design; classifying, by the processing device, a signal path of a sub-circuit of the integrated circuit design based on a connection between an input port of the signal path and a component of the sub-circuit to generate a classification of the signal path; computing, by the processing device, a security vulnerability result of the sub-circuit of the integrated circuit design based on the classification of the signal path and based on a trust level of a zone in a fan-in cone to an input port of the signal path; and generating a security vulnerability report based on the security vulnerability result of the sub-circuit of the integrated circuit design.
G06F 21/00 - Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
G06F 21/71 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
84.
Solving multiple array problems interacting with each other in constraint solving for functional verification of logic designs
In some aspects, a logic design undergoes functional verification, which includes generating a test stimulus to apply to the logic design. The test stimulus includes test values for variables representing signals in the logic design. Generating the test stimulus involves a first problem of solving for the test values of the variables subject to constraints on the test values. It is solved as follows. A specification of the logic design is accessed. An array implication graph is generated from the specification. The array implication graph represents the problem as a set of two or more single-array constraint problems. Each single-array constraint problem solves for the test values of a single array of the variables subject to the constraints within that single array. The array implication graph also represents dependencies between different single-array constraint problems. The problem is solved based on the dependencies represented in the array implication graph.
An integrated circuit comprising a substrate. At least two component bearing structures are fabricated within a layer above the substrate. In addition, at least one vertical space is present separating adjacent component bearing structures. At least one upsized buried power rail is formed within a corresponding cavity contiguously formed adjacent to a corresponding one of vertical spaces. The upsized buried power rail has a width that is greater than the width of the vertical space.
H01L 23/528 - Layout of the interconnection structure
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
A computer-implemented method for modeling mandrel tolerance in a design of semiconductor device. The method includes receiving a multiple patterning (MPT) process design kit (PDK) for the semiconductor device. The PDK includes design parameters of a plurality of transistors that form at least part of the semiconductor device and a plurality of fins associated with each of the plurality of transistors. The method includes generating a fin index identifying each of the plurality of fins and grouping the fin indexes of the plurality of fins into two or more groups based on a type of fin. The method further includes identifying a mandrel mismatch in response to determining that a first fin index associated with a first transistor belongs to a group that is different from a second fin index associated with a second transistor. The method also includes determining a device parameter based on the mandrel mismatch identified.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/31 - Design entry, e.g. editors specifically adapted for circuit design
G06F 119/06 - Power analysis or power optimisation
87.
Automatic design parameter optimization for electronic circuit designs with operating environment coverage
A system performs optimization of parameters of a circuit design. The system accesses a model configured to receive design variables of the circuit design and predict a measure of quality of the circuit design. For multiple coverage levels, the system generates samples representing a values of design parameters. For each sample, the system predicts the quality of the sample using the model. The system selects a subset of samples having a predicted quality that exceeds a target. The system performs simulations of the selected subset of samples. The system maintains a moving target and drops samples encountering worse results before all simulations finish. The system performs incremental training of the model based on results of the simulations of the selected subset of samples. The system also decides whether to enter the next coverage level based on the simulation results and the moving target.
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
G06F 119/02 - Reliability analysis or reliability optimisationFailure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
88.
Stacked nanosheet device for process and performance optimization
A method of forming a multitude of GAAFETs on a silicon substrate includes forming alternating layers of Si nanosheets and SiGe alloys above the silicon substrate, depositing a layer of oxide buffer above the top layer of SiGe alloy, depositing a mask layer above the oxide buffer layer, patterning the mask and the oxide, and performing a RIE of the silicon nanosheet and SiGe alloy layers so as to form tapered pillars of silicon nanosheet and SiGe alloy layers. In each tapered pillar, a width of the first layer of silicon nanosheet that is closer to the substrate is greater than a width of the etched second layer of silicon nanosheet that is formed above the first layer of silicon nanosheet. The first, and second tapered silicon nanosheet layers in each pillar form channels of first and second GAAFETs.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
An example is a non-transitory computer-readable storage medium including stored instructions. The instructions, which when executed by one or more processors, cause the one or more processors to: obtain an assignment of an assigned bucket; generate stimulus values targeting one or more uncovered bins of the assigned bucket; simulate operation of a circuit design using the stimulus values; determine whether the assigned bucket has been covered by the simulated operation of the circuit design; and expand a size of the assigned bucket following a determination that the assigned bucket has been covered. The assigned bucket, as assigned, has a subset of bins of a functional coverage space.
An example is a circuit. The circuit includes a memory array, a mimic column, a mimic resistor, and a calibration circuit. The mimic column is along a periphery of the memory array. The mimic resistor is in a path through the mimic column. The calibration circuit is configured to calibrate a voltage for writing a memory cell in the memory array. The calibration circuit is electrically connected to the mimic resistor. A voltage may be calibrated, such as by the calibration circuit, using the mimic column. A value may be written to a memory cell of the memory array using the calibrated voltage.
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
91.
Placing hard macros using machine learning predictions trained on different circuit designs
In one aspect, QoR metrics for different candidate macro placements are estimated using machine learning models. A set of candidate macro placements of hard macros within a circuit design is assessed by estimating a quality metric for each candidate macro placement, as follows. Model-specific estimates of the quality metric are predicted by applying different machine learning models to the candidate macro placements. The different machine learning models are trained using sets of completed macro placements for other circuit designs. The model-specific estimates of the quality metric are combined based on an applicability of (a) the set of macro placements used to train that model to (b) the set of candidate macro placements being evaluated.
A processing device identifies a first clock tree topology for a circuit design, the first clock tree topology having a threshold feedthrough count and a first timing solution. The processing device further identifies one or more additional clock tree topologies for the circuit design, each of the one or more additional clock tree topologies having a different respective feedthrough count that is less than the threshold feedthrough count, and each of the one or more additional clock tree topologies comprising a respective timing solution. In addition, the processing device receives a selection of at least one of the first clock tree topology or the one or more additional clock tree topologies, and generates the circuit design according to the selection.
A logic circuit includes: a first cascode circuit including: a first transistor, a second transistor, and a third transistor connected in series, the third transistor connected to an output of the first cascode circuit; and a first diode connected in parallel with the third transistor; and a second cascode circuit connected in series with the first cascode circuit, the second cascode circuit including: a fourth transistor, a fifth transistor, and a sixth transistor connected in series, the sixth transistor connected to an output of the second cascode circuit; and a second diode connected in parallel with the sixth transistor; and wherein the output of the first cascode circuit is connected to the output of the second cascode circuit and connects the first cascode circuit in series with the second cascode circuit.
H03K 19/0944 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET
A memory protection unit (MPU) configuration request may be received, where the MPU configuration request may include a memory protection rule. A first entry in a first MPU circuit may be determined which matches the memory protection rule. A compliance result may be determined based on checking if the memory protection rule complies with the first entry. The memory protection rule may be written in a second MPU circuit based on the compliance result.
A set of global parameters may be modeled using a set of equivalent parameters, where the set of global parameters represents global process variation in a circuit. A global distribution for a metric in the circuit may be determined by performing Monte-Carlo (MC) analysis using the set of equivalent parameters. Combined local and global variations for the metric may be calculated based on the global distribution for the metric and a local distribution for the metric.
G06F 30/367 - Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
G06F 30/20 - Design optimisation, verification or simulation
G06F 30/3308 - Design verification, e.g. functional simulation or model checking using simulation
G06F 30/3323 - Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
Embodiments relate to a system and method of generating a duty-cycle matched differential clock divider circuit. The duty-cycle matched differential clock divider circuit may include a primary latch, differential latch, and a first inverter. The primary latch may be coupled to receive a feedback signal and complementary input clock signals. The primary latch may be configured to produce a first output signal. The differential latch may be coupled to receive the first output signal produced by the primary latch and the complementary input clock signals. The differential latch may be configured to produce a second output signal and a third output signal. The first inverter may be coupled to receive the second output signal produced by the differential latch, and may be configured to produce the feedback signal applied to an input of the primary latch.
A level-shiftless transmitter includes a transmitter driver circuit. The transmitter driver circuit includes a first PMOS device, a second PMOS device, a first NMOS device, a second NMOS device, and a sub-circuit. The sources of the first and second PMOS devices are electrically coupled with each other. The gates of the first PMOS and the first NMOS devices are electrically coupled with each other. The gates of the second PMOS and the second NMOS devices are electrically coupled with each other. The sub-circuit is electrically coupled with a voltage domain to provide a voltage lower than the voltage domain to the sources of the first and second PMOS devices.
H03M 9/00 - Parallel/series conversion or vice versa
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H03K 17/76 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
H03K 19/0185 - Coupling arrangementsInterface arrangements using field-effect transistors only
98.
PROTECTING INTELLECTUAL PROPERTY USING DIGITAL SIGNATURES
Methods of protecting intellectual property using digital signatures include generating reference digital signatures of first content, generating a digital signature of second content, comparing the digital signature of the second content to the reference digital signatures to identify matching reference digital signatures, and selectively performing an action based on the matching reference digital signatures and a policy. The first content may include proprietary information of an organization and/or posts of a machine-learning (ML) model. The second content may include source code intercepted from a transmission directed to an external site, such as a ML model, and/or source code saved to a source code repository. Actions may include, without limitation, initiating an audit of the second content, sending a notification to a user interface indicating that the second content likely contains a portion of the first content, releasing the transmission, and/or terminating the transmission.
A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.
A fail tolerant sensor circuit for adjusting an input signal received at an input pad to be provided to an integrated circuit (IC). The circuit includes a sensor input transistor including a first terminal coupled to the input pad, a second terminal coupled to a receiver circuit, and a gate. The circuit further includes a feedback loop that includes a first voltage clamp circuit having an input coupled to the second terminal of the senor input transistor and providing an output, and a first level shifter including an input coupled to the output of the first voltage clamp circuit and providing the feedback output coupled to the gate of the sensor input transistor.
