Produits et services

Televisions; video monitors; television monitors; wearable video display monitors; LCD monitors; LED monitors; digital signage monitors; touchscreen monitors; electronic driver-interface displays for automobiles; video displays for navigation apparatus for vehicles; light emitting diode (LED) displays; OLED (organic light emitting diode) display panels; flat panel display screens.

Produits et services

Washing machines for household purposes. Electric laundry dryers.

Abrégé

An image sensor including a semiconductor substrate having a first surface and a second surface; and a pixel isolation film extending from the first surface of the semiconductor substrate into the semiconductor substrate and defining active pixels in the semiconductor substrate, wherein the pixel isolation film includes a buried conductive layer including polysilicon containing a fining element at a first concentration; and an insulating liner between the buried conductive layer and the semiconductor substrate, and wherein the fining element includes oxygen, carbon, or fluorine.

Classes IPC  ?

• H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes

Abrégé

An electronic apparatus includes: a housing including a coupling region; and a printed circuit board (PCB) including: an overlap region that overlaps the coupling region; a non-overlap region that does not overlap the coupling region; a plurality of metal layers including a plurality of lines; and a void portion in which a portion of at least one metal layer, among the plurality of metal layers, is not formed so that the at least one metal layer is discontinuous or terminated in the void portion, the at least one metal layer including a metal layer that is closest to the coupling region among the plurality of metal layers.

Classes IPC  ?

• H01Q 1/24 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets avec appareil récepteur
• H01Q 1/48 - Moyens de mise à la terreÉcrans de terreContrepoids
• H04M 1/02 - Caractéristiques de structure des appareils téléphoniques
• H05K 1/02 - Circuits imprimés Détails
• H05K 7/14 - Montage de la structure de support dans l'enveloppe, sur cadre ou sur bâti

Abrégé

An electronic device may include a flexible display, a first housing, a second housing movably coupled to the first housing, and a support member which supports at least a portion of the flexible display and moves according to movement of the second housing. The support member may include support bars which support the rear surface of the flexible display, first guide protrusions protruding from opposite ends of each of the multiple support bars, and second guide protrusions extending from the first guide protrusions. The electronic device may include a guide rail disposed in the first housing. The guide rail may include a guide slit. The guide slit may include a linear section, a curved section extending from the linear section, a first guide slit extending from the linear section to the curved section, and a second guide slit provided in the curved section.

Classes IPC  ?

• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails

Abrégé

A display apparatus includes: a display module including a substrate on which a plurality of light emitting diodes (LEDs) are mounted; a cabinet provided to support the display module; and a circuit case attached to the cabinet. The display module is provided to be detachable from and mountable on a front side of the cabinet, and the display module is provided to be detachable from and mountable on a rear side of the cabinet.

Classes IPC  ?

• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails
• H01L 25/075 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H05K 5/30 - Dispositions côte à côte ou empilées

Abrégé

A method of providing search results based on a user's search context is provided. The method includes determining a user's search context based on a user input and context information for a search, determining a tolerance limit representing a degree to which a user is tolerable from the determined user's search context, obtaining a search condition for the search, based on the determined tolerance limit, and providing search results according to the obtained search condition.

Classes IPC  ?

• G06F 16/335 - Filtrage basé sur des données supplémentaires, p. ex. sur des profils d’utilisateurs ou de groupes
• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
• G06F 16/35 - PartitionnementClassement

Abrégé

An electronic device is provided. The electronic device includes a housing, a flexible display configured to slide into or out of the housing, an actuator configured to pull in at least aa portion of the flexible display into the housing or pull out at least a portion of the flexible display from the housing, a memory, and a processor. The processor is configured to display a visual object for guiding to change a state of a display region to a reference state, based on identifying that the state of the display region is distinguished from the reference state.

Classes IPC  ?

• G06F 1/16 - Détails ou dispositions de structure
• G06F 3/0481 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] fondées sur des propriétés spécifiques de l’objet d’interaction affiché ou sur un environnement basé sur les métaphores, p. ex. interaction avec des éléments du bureau telles les fenêtres ou les icônes, ou avec l’aide d’un curseur changeant de comportement ou d’aspect
• G06F 3/0484 - Techniques d’interaction fondées sur les interfaces utilisateur graphiques [GUI] pour la commande de fonctions ou d’opérations spécifiques, p. ex. sélection ou transformation d’un objet, d’une image ou d’un élément de texte affiché, détermination d’une valeur de paramètre ou sélection d’une plage de valeurs
• G06F 9/451 - Dispositions d’exécution pour interfaces utilisateur

Abrégé

Provided is an electronic device including a first housing having a ring shape, a second housing having a ring shape, the first housing and the second housing being connected and rotatable relative to each other, a plurality of magnet members, at least some of the plurality of magnet members being at different intervals in the second housing, a sensor in the first housing and configured to detect a magnetic force generated from the plurality of magnet members, a memory configured to store instructions, and at least one processor configured to execute the instructions to control the sensor to detect a change in the magnetic force that is generated from the plurality of magnet members based on the second housing rotating relative to the first housing, and detect a rotation attribute of the second housing relative to the first housing based on an attribute of the detected change in the magnetic force.

Classes IPC  ?

• G01D 5/14 - Moyens mécaniques pour le transfert de la grandeur de sortie d'un organe sensibleMoyens pour convertir la grandeur de sortie d'un organe sensible en une autre variable, lorsque la forme ou la nature de l'organe sensible n'imposent pas un moyen de conversion déterminéTransducteurs non spécialement adaptés à une variable particulière utilisant des moyens électriques ou magnétiques influençant la valeur d'un courant ou d'une tension
• G06F 3/0362 - Dispositifs de pointage déplacés ou positionnés par l'utilisateurLeurs accessoires avec détection des translations ou des rotations unidimensionnelles [1D] d’une partie agissante du dispositif de pointage, p. ex. molettes de défilement, curseurs, boutons, rouleaux ou bandes

Abrégé

A detergent feeding device including a case including a receiving portion and an outlet, a siphon tube, to protrude from the bottom surface of the receiving portion, including a first flow path, a siphon cap, to cover an outer side of the siphon tube, including an agitating blade configured to be rotated by water supplied to the receiving portion, the siphon cap to form a second flow path to guide the water supplied to the receiving portion toward the outlet of the case through the first flow path of the siphon tube, and a plurality of support ribs, to extend from an inner surface of the siphon cap toward the siphon tube, configured to be supported by the siphon tube, wherein a cross-section of a corner at which the plurality of support ribs and the inner surface of the siphon cap meet has a curved shape.

Classes IPC  ?

• D06F 39/02 - Dispositifs pour l'addition de savon ou autres agents de lavage

Abrégé

An electronic device includes memory storing instructions; and at least one processor; wherein the instructions, when executed by the at least one processor, cause the electronic device to identify a first audio signal including a first plurality of audio sources; identify a first audio source, corresponding to at least one first type, from the first audio signal; based on at least one configuration value corresponding to each of the at least one first type, perform signal processing on the first audio source; generate a second audio signal based on at least a portion of a remaining signal of the first audio signal excluding the first audio source, and the signal-processed first audio source; and output the second audio signal.

Classes IPC  ?

• G10L 25/51 - Techniques d'analyse de la parole ou de la voix qui ne se limitent pas à un seul des groupes spécialement adaptées pour un usage particulier pour comparaison ou différentiation
• G06F 9/451 - Dispositions d’exécution pour interfaces utilisateur

Abrégé

Provided is a semiconductor device that includes a first active pattern and a second active pattern on a substrate, the first active pattern spaced apart from the second active pattern in a first direction, and extending in a second direction, the second direction being different from the first direction, a lower channel pattern and a lower source/drain pattern on the first active pattern and alternately arranged in the second direction, an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern, a gate pattern on first active pattern, the lower channel pattern, and the upper channel pattern, and a first active contact connected to the lower source/drain pattern, and a second active contact connected to the upper source/drain pattern.

Classes IPC  ?

• H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
• H10D 30/00 - Transistors à effet de champ [FET]
• H10D 30/01 - Fabrication ou traitement
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
• H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
• H10D 84/01 - Fabrication ou traitement

Abrégé

A method for managing data channel communication by a user equipment (UE) is provided. The method includes determining transmit a root application request, transmitting the root application request comprising a first application type information element (IE) associated with the root application, based on determining to transmit the root application request, and receiving a root application response based on the first application type IE associated with the root application, in response to the root application request, wherein the root application response comprise at least one of a list of data channel applications, a root application version IE and a root application validity IE.

Classes IPC  ?

• H04W 8/20 - Transfert de données utilisateur ou abonné
• H04W 8/18 - Traitement de données utilisateur ou abonné, p. ex. services faisant l'objet d'un abonnement, préférences utilisateur ou profils utilisateurTransfert de données utilisateur ou abonné
• H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications

Abrégé

A semiconductor device includes a first source/drain, a second source/drain, a first nanosheet, a second nanosheet, and interconnect, which is configured to electrically connect the first source/drain to the second source/drain, and contacts the first and second nanosheets. The interconnect includes an enclosure, a first side via region extending inside the enclosure and electrically connected to the first source/drain, a second side via region extending inside the enclosure and electrically connected to the second source/drain, and a side metal region, which extends inside the enclosure and is electrically connected to the first side via region and the second side via region.

Classes IPC  ?

• H10D 84/90 - Circuits intégrés à tranches maîtresses

Abrégé

A method of an electronic device including obtaining a low-resolution input image by down-sampling a high-resolution input image; obtaining a low-resolution output image by performing image quality processing on the low-resolution input image; obtaining a low-resolution model from a conversion relationship between the low-resolution input image prior to the image quality processing being performed and the low-resolution output image subsequent to the image quality processing being performed; performing up-sampling of the low-resolution model; obtaining a high-resolution model by modifying the up-sampled low-resolution model, based on a difference between the high-resolution input image and the low-resolution input image; and obtaining a high-resolution output image from the high-resolution input image, by applying the high-resolution model to the high-resolution input image.

Classes IPC  ?

• G06T 5/20 - Amélioration ou restauration d'image utilisant des opérateurs locaux
• G06T 3/4007 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur l’interpolation, p. ex. interpolation bilinéaire
• G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
• G06T 5/70 - DébruitageLissage

Abrégé

An apparatus of a base station is provided. The apparatus includes memory for storing instructions, at least one transceiver, and at least one processor communicatively coupled to the at least one transceiver and the memory, wherein the instructions, when executed by the at least one processor individually or collectively, cause the apparatus to: obtain signals received from a terminal through a plurality of antennas, obtain a first angle of arrival (AoAs) for a first direction of the plurality of antennas based on the signals, and transmit, to a location management server through the at least one transceiver, a measurement message including the first AoA and at least one first candidate AoA associated with the first AoAs, wherein the at least one first candidate AoA is identified based on the first AoA and a first interval between antennas disposed along the first direction.

Classes IPC  ?

• H04W 16/28 - Structures des cellules utilisant l'orientation du faisceau
• H04W 24/10 - Planification des comptes-rendus de mesures

Abrégé

A display apparatus according to an embodiment may include: a display, a second standard port connected to a first standard port of an external device; communication circuitry configured to receive a first standard image and variable refresh rate information through the second standard port; a controller configured to convert the first standard image into a second standard image based on the variable refresh rate information, and control the display to display the converted second standard image.

Classes IPC  ?

• H04N 21/4363 - Adaptation du flux vidéo à un réseau local spécifique, p. ex. un réseau Bluetooth®
• G06F 3/14 - Sortie numérique vers un dispositif de visualisation
• H04N 21/4402 - Traitement de flux élémentaires vidéo, p. ex. raccordement d'un clip vidéo récupéré d'un stockage local avec un flux vidéo en entrée ou rendu de scènes selon des graphes de scène du flux vidéo codé impliquant des opérations de reformatage de signaux vidéo pour la redistribution domestique, le stockage ou l'affichage en temps réel

Abrégé

Provided is a mounting substrate for a semiconductor package, including a substrate having an upper surface and a lower surface opposite to each other, the substrate including a plurality of insulation layers and wirings in the plurality of insulation layers, first substrate pads and second substrate pads on the upper surface in a chip mounting region of the mounting surface, heat absorbing pads on the upper surface in a peripheral region of the mounting surface adjacent to the chip mounting region, and connection lines in the substrate, the connection lines being configured to thermally couple the heat absorbing pads and the second substrate pads to each other.

Classes IPC  ?

• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide

Abrégé

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Embodiments herein provide a method for PLMN search and selection after removal of a candidate PLMN in a wireless network by a UE. The method includes identifying that the UE is in a limited service state. Further, the method includes identifying that an entry of at least one candidate public land mobile network (PLMN) from a list of PLMNs not allowed to operate at a current location of the UE is removed. Further, the method includes triggering a PLMN selection in case that the entry is removed from the list of PLMNs and the UE is in the limited service state.

Classes IPC  ?

• H04W 48/18 - Sélection d'un réseau ou d'un service de télécommunications
• H04W 4/90 - Services pour gérer les situations d’urgence ou dangereuses, p. ex. systèmes d’alerte aux séismes et aux tsunamis
• H04W 8/18 - Traitement de données utilisateur ou abonné, p. ex. services faisant l'objet d'un abonnement, préférences utilisateur ou profils utilisateurTransfert de données utilisateur ou abonné
• H04W 48/04 - Restriction d'accès effectuée dans des conditions spécifiques sur la base des données de localisation ou de mobilité de l'utilisateur ou du terminal, p. ex. du sens ou de la vitesse de déplacement
• H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
• H04W 84/04 - Réseaux à grande échelleRéseaux fortement hiérarchisés
• H04W 84/06 - Réseaux aériens ou satellitaires

Abrégé

An electronic device according to an embodiment disclosed in the present disclosure may include a housing including a first housing part and a second housing part, a flexible display, an actuator configured to move the second housing part relative to the first housing part, a first antenna that performs wireless communication using a first part of a side frame of the first housing part, a second antenna that performs wireless communication using a second part of the side frame of the first housing part, a sensor module that detects movement of the first housing part or the second housing part, a communication circuit that transmits/receives a wireless signal through the first antenna or the second antenna, and a processor that changes a tune code of a tuner included in each of the first antenna and the second antenna based on an extension distance of the display. Another embodiment recognized from the description can be implemented.

Classes IPC  ?

• H04B 1/40 - Circuits

Abrégé

A method for supplying power and an electronic device for performing the method are disclosed provided. The electronic device includes memory, including storing instructions, and at least one processor, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to receive, from an external power supply device, power information corresponding to a plurality of power supply modes, based on the power information, set, among the plurality of power supply modes, an interface to supply power in a first power mode in which a magnitude of power capable of being supplied is a maximum, determine power consumed by the electronic device, and in the first power mode, set the interface to supply power in a second power mode in which a magnitude of power capable of being supplied is smaller than that of the first power mode.

Classes IPC  ?

• H02M 1/00 - Détails d'appareils pour transformation

Abrégé

A device includes a photonic integrated circuit, an optical demultiplexer, and an electronic integrated circuit. The electronic integrated circuit is mounted on the photonic integrated circuit and includes at least one photodetector optically coupled to the optical demultiplexer. The optical demultiplexer separates an incoming optical signal into a first separated optical signal and a second separated optical signal. The at least one photodetector has a first photodetector and a second photodetector. The first photodetector receives the first separated optical signal, and the second photodetector receives the second separated optical signal.

Classes IPC  ?

• G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
• G02B 6/42 - Couplage de guides de lumière avec des éléments opto-électroniques

Abrégé

An electronic device includes a camera, a communication interface, a display, memory storing instructions, and at least one processor. The instructions, when executed by the at least one processor, individually or collectively, may cause the electronic device to: obtain, through the camera, images including motion information of a user; transmit, through the communication interface, the images to an external electronic device; based on the group mission being achieved, obtain, through the communication interface, content related to a performance from the external electronic device; and display the content through the display.

Classes IPC  ?

• G06T 11/60 - Édition de figures et de texteCombinaison de figures ou de texte
• G06F 3/01 - Dispositions d'entrée ou dispositions d'entrée et de sortie combinées pour l'interaction entre l'utilisateur et le calculateur
• G06T 7/20 - Analyse du mouvement

Abrégé

An electronic device and a controlling method thereof are provided. The electronic device includes memory, comprising one or more storage media, storing instructions and configured to store information on a neural network model and information on a plurality of resources for performing distributed learning on the neural network model, and a processor communicatively coupled to the memory and configured to perform a parallelism process including pipeline parallelism, data parallelism, and tensor parallelism based on the information on the neural network model and the information on the plurality of resources, wherein the instructions, when executed by the processor, cause the electronic device to acquire a first computation amount when performing the distributed learning from a time when a change in the plurality of resources is detected to a next checkpoint using the plurality of resources before the change, if the change is detected while performing the distributed learning according to a result of performing the parallelism process, perform the parallelism process again based on the information on the plurality of changed resources, acquire a second computation amount when performing the distributed learning from the time when the change is detected to the next checkpoint using the plurality of changed resources, as the result of the parallelism performed again, and perform the distributed learning by a method corresponding to a smaller computation amount of the first computation amount and the second computation amount.

Classes IPC  ?

• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
• G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire

Abrégé

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates. The present disclosure provides an operation method for supporting an energy saving mode of a base station in a wireless communication system, comprising the steps of: receiving, from a base station, a radio resource control (RRC) message including configuration information regarding energy saving of the base station; and performing communication with the base station on the basis of periodic activation or deactivation of the energy saving mode of the base station, which is identified on the basis of the configuration information, and activation or deactivation of the energy saving mode, which is determined on the basis of reception of a mode change indicator received from the base station.

Classes IPC  ?

• H04W 52/02 - Dispositions d'économie de puissance
• H04W 72/11 - Planification semi-persistante
• H04W 72/231 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal les données de commande provenant des couches au-dessus de la couche physique, p. ex. signalisation RRC ou MAC-CE

Abrégé

A method and a device of multimedia playback for a virtual system are provided. The method of multimedia playback for a virtual system includes establishing a secure communication channel between the virtual system and a host system, acquiring a license file for acquiring encrypted multimedia data in a case that an application in the virtual system requesting access to the host system passes authentication of the host system, acquiring the encrypted multimedia data based on the license file, transmitting the encrypted multimedia data to the host system for decryption based on the secure communication channel, and acquiring decrypted multimedia data obtained by decryption by the host system, and playing back the decrypted multimedia data.

Classes IPC  ?

• H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système

Abrégé

An electronic device according to an embodiment may include a display including a first area and a second area, a pair of housings including a first housing supporting the first area and a second housing supporting the second area, a hinge connecting the first housing and the second housing to be foldable about a folding axis, a hinge housing in which at least a portion of the hinge assembly is accommodated, and a sweeper arranged in each of the first housing and the second housing in a direction parallel to the folding axis, so that the first area and the second area contact the hinge housing based on the folded state of facing each other. The sweeper may not contact the hinge assembly.

Classes IPC  ?

• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails
• F16C 11/04 - Articulations

Abrégé

A repeater includes a first antenna configured to transmit and receive RF signals from a BS, a second antenna configured to transmit and receive RF signals from a UE, a processor configured to control an operating mode of the repeater, and a transceiver operatively coupled to the processor. The transceiver includes an amplifier stage and a DPDT switch. The DPDT switch is configured to, when the repeater is operating in a downlink operating mode, electrically couple the first antenna to an input signal path of the amplifier stage, and electrically couple the second antenna to an output signal path of the amplifier stage. The DPDT switch is further configured to, when the repeater is operating in an uplink operating mode, electrically couple the second antenna to the input signal path of the amplifier stage, and electrically couple the first antenna to the output signal path of the amplifier stage.

Classes IPC  ?

• H04B 7/155 - Stations terrestres

Abrégé

An integrated circuit device may include: a substrate; and a bipolar junction transistor in the substrate, wherein the bipolar junction transistor includes: a first well region of a second conductivity type in the substrate and having a first doping concentration; a second well region adjacent to one side of the first well region in the substrate, of the second conductivity type, and having a second doping concentration that is different from the first doping concentration; a third well region adjacent to another side of the first well region in the substrate and of a first conductivity type; a base on the first well region and having the second conductivity type; an emitter on the second well region and of the first conductivity type; and a collector on the third well region and of the first conductivity type.

Classes IPC  ?

• H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
• H10D 10/60 - Transistors BJT latéraux
• H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
• H10D 62/60 - Distribution ou concentrations d’impuretés

Abrégé

A storage device including: a non-volatile memory comprising a plurality of memory cells, wherein the plurality of memory cells comprises a target memory cell; and a storage controller: wherein the storage controller is configured to: read the target memory cell at a plurality of target read times to obtain a plurality of target voltages, select a threshold model corresponding to the target memory cell from among a plurality of threshold models, and generate data corresponding to the target memory cell by providing the plurality of target voltages to the threshold model.

Classes IPC  ?

• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• G11C 16/32 - Circuits de synchronisation

Abrégé

Apparatuses and methods for channel state information (CSI) codebook. A method for operating a user equipment (UE) includes receiving a configuration about a CSI report. The configuration includes information about N>1 groups of CSI reference signal (CSI-RS) ports and a codebook. The codebook includes a spatial-domain (SD) basis component, a frequency-domain (FD) basis component, and a coefficient component. The SD basis component includes Lr basis vectors for each group r=1, . . . , N. The FD basis component includes Mv basis vectors. The coefficient component includes coefficients associated with (SD, FD) basis vector pairs. The method further includes, based on the configuration, measuring the N groups of CSI-RS ports and determining the SD basis component, the FD basis component, and the coefficient component such that K1 coefficients are non-zero and remaining coefficients are zero, where Apparatuses and methods for channel state information (CSI) codebook. A method for operating a user equipment (UE) includes receiving a configuration about a CSI report. The configuration includes information about N>1 groups of CSI reference signal (CSI-RS) ports and a codebook. The codebook includes a spatial-domain (SD) basis component, a frequency-domain (FD) basis component, and a coefficient component. The SD basis component includes Lr basis vectors for each group r=1, . . . , N. The FD basis component includes Mv basis vectors. The coefficient component includes coefficients associated with (SD, FD) basis vector pairs. The method further includes, based on the configuration, measuring the N groups of CSI-RS ports and determining the SD basis component, the FD basis component, and the coefficient component such that K1 coefficients are non-zero and remaining coefficients are zero, where K 1 ≤ ∑ r = 1 N ⁢ ( 2 ⁢ L r ⁢ M v ) . Apparatuses and methods for channel state information (CSI) codebook. A method for operating a user equipment (UE) includes receiving a configuration about a CSI report. The configuration includes information about N>1 groups of CSI reference signal (CSI-RS) ports and a codebook. The codebook includes a spatial-domain (SD) basis component, a frequency-domain (FD) basis component, and a coefficient component. The SD basis component includes Lr basis vectors for each group r=1, . . . , N. The FD basis component includes Mv basis vectors. The coefficient component includes coefficients associated with (SD, FD) basis vector pairs. The method further includes, based on the configuration, measuring the N groups of CSI-RS ports and determining the SD basis component, the FD basis component, and the coefficient component such that K1 coefficients are non-zero and remaining coefficients are zero, where K 1 ≤ ∑ r = 1 N ⁢ ( 2 ⁢ L r ⁢ M v ) . The method further includes transmitting the CSI report including an indicator indicating locations of non-zero coefficients.

Classes IPC  ?

• H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission

Abrégé

A semiconductor device may include a substrate including a cell array area and a peripheral area, a plurality of bit lines in the cell array area, a plurality of insulating capping structures covering the plurality of bit lines, a plurality of bit line spacers surrounding the plurality of bit lines, a cell pad structure between a pair of adjacent bit lines among the plurality of bit lines, a landing pad on the cell pad structure and including a conductive barrier film and a landing pad conductive layer, and an insulating pattern covering at least a portion of the landing pad. The insulating pattern may be in contact with the conductive barrier film.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux

Abrégé

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates. A method performed in a wireless communication system by a terminal disclosed herein comprises the steps of: acquiring, from a base station, random access configuration parameters for a combination of a plurality of functions; using the acquired random access configuration parameters to perform a random access procedure; and transmitting a random access report about the performed random access procedure to the base station, wherein the random access report includes random access configuration information on at least one function, used when the random access procedure was performed, among the plurality of functions.

Classes IPC  ?

• H04W 74/0833 - Procédures d’accès aléatoire, p. ex. avec accès en 4 étapes

Abrégé

A method performed by an electronic device for managing a personal knowledge graph is provided. The method includes detecting, by the electronic device, an instance including an incomplete node having missing knowledge property information in a personal knowledge graph, identifying, by the electronic device, candidate knowledge property information corresponding to the missing knowledge property information of the incomplete node, and performing, by the electronic device, a task of completing the incomplete node based on the identified candidate knowledge property information.

Classes IPC  ?

• G06N 5/022 - Ingénierie de la connaissanceAcquisition de la connaissance

Abrégé

An electronic device may comprise: a memory, and at least one processor, comprising processing circuitry. At least one processor, individually and/or collectively, may be configured to cause the electronic device to: transmit, to a shared application, first user input data input through a first application corresponding to a first vendor and second user input data input through a second application corresponding to a second vendor, stored in the memory, train a first artificial intelligence model of the shared application based on the first user input data and the second user input data, estimate results of a third user input data input through the first application or the second application, through the first artificial intelligence model, based on training the artificial intelligence model, and determine a priority for the estimated results and transmit information about the determined priority and the estimated results to the first application or the second application.

Classes IPC  ?

• G06N 20/00 - Apprentissage automatique

Abrégé

A storage device, including a volatile memory; a non-volatile memory; and a storage controller: wherein, based on detecting a power loss corresponding to the storage device, the storage controller is configured to: obtain a word stored in the volatile memory; write the word to a first word line; compare a number of unprogrammed cells to a first threshold number and a second threshold number, wherein the unprogrammed cells correspond to remainder data; based on determining that the number of unprogrammed cells is less than or equal to the first threshold number and greater than the second threshold number, determine whether to continue writing the word to the first word line by providing information about the first word line to a machine learning model; and based on determining not to continue writing the word to the first word line, write the remainder data to a second word line.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/408 - Circuits d'adressage
• G11C 11/4093 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. mémoires tampon de données
• G11C 11/54 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments simulateurs de cellules biologiques, p. ex. neurone

Abrégé

A semiconductor memory device may be provided. The semiconductor memory device may include a bit line, a channel pattern on the bit line, the channel pattern including a horizontal channel portion, which is provided on the bit line, and a vertical channel portion, which is vertically extended from the horizontal channel portion, a word line provided on the channel pattern to cross the bit line, the word line including a horizontal portion, which is provided on the horizontal channel portion, and a vertical portion, which is vertically extended from the horizontal portion to face the vertical channel portion, and a gate insulating pattern provided between the channel pattern and the word line.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10D 30/63 - Transistors IGFET verticaux
• H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal

Abrégé

An electronic device may comprise: a communication module comprising communication circuitry and at least one processor, comprising processing circuitry, wherein at least one processor, individually and/or collectively, is configured to: obtain a character string; divide the obtained character string by a designated character string unit to obtain first character string blocks; obtain second character string blocks by inserting connection information between the first character string blocks into each of the first character string blocks; apply a local differential privacy algorithm for each of the second character string blocks; and transmit, to the outside via the communication module, character string data including the second character string blocks to which the local differential privacy algorithm has been applied.

Classes IPC  ?

• G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès

Abrégé

An electronic device is provided. The electronic device according to one embodiment comprises: a frame including a first surface, and a partition wall protruding from the first surface; a battery disposed on the first surface and adjacent to the partition wall; a flexible printed circuit board which includes a bending portion bent in the partition wall, and which is connected to the battery; and a support member movably coupled to the partition wall, wherein the supporting member which is moved to contact the bending portion includes the supporting member applying a force to the bending portion in a direction toward the first surface to define a first position of the supporting member, and wherein the supporting member which is moved to be spaced apart from the bending portion includes removal of the force from the bending portion to define a second position of the supporting member.

Classes IPC  ?

• H05K 1/02 - Circuits imprimés Détails
• G06F 1/16 - Détails ou dispositions de structure
• H05K 1/18 - Circuits imprimés associés structurellement à des composants électriques non imprimés

Abrégé

An electroluminescent device, a manufacturing method, and a display device. An electroluminescent device of an embodiment includes a first electrode and a second electrode spaced apart from each other, and a light emitting layer disposed between the first electrode and the second electrode and including a semiconductor nanoparticle, where the semiconductor nanoparticle is configured to emit blue light, an peak emission wavelength of the blue light is greater than or equal to about 440 nanometers and less than or equal to about 480 nanometers, the semiconductor nanoparticle includes zinc, tellurium, selenium, and sulfur, the semiconductor nanoparticle further includes a metal dopant, and the metal dopant includes aluminum, gallium, zirconium, hafnium, magnesium, or a combination thereof.

Classes IPC  ?

• H10K 50/115 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des nanostructures inorganiques actives, p. ex. des points quantiques luminescents
• H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
• H10K 71/13 - Dépôt d'une matière active organique en utilisant un dépôt liquide, p. ex. revêtement par centrifugation en utilisant des techniques d'impression, p. ex. l’impression par jet d'encre ou la sérigraphie

Abrégé

An electronic apparatus may include at least one processor configured to control the electronic apparatus, wherein the at least one processor is configured to execute at least one instruction to: control a speaker to play content at a first volume; receive a first control instruction from the external device through a communication interface, the first control instruction being for decreasing an audio volume of the content while the external device outputs guidance audio for guiding a user input; control the speaker to decrease the audio volume of the content based on the first control instruction; receive a second control instruction from the external device through the communication interface, the second control instruction being for restoring the audio volume of the content to the first volume; and control the speaker to restore the audio volume of the content to the first volume based on the second control instruction.

Classes IPC  ?

• G06F 3/16 - Entrée acoustiqueSortie acoustique
• H04N 21/422 - Périphériques d'entrée uniquement, p. ex. système de positionnement global [GPS]
• H04N 21/485 - Interface pour utilisateurs finaux pour la configuration du client

Abrégé

An electronic device outputting a sound according to embodiments of the disclosure may comprise memory storing at least one instruction, a processor executing the at least one instruction, at least one speaker, and an audio processing module processing the input audio signal and outputting the processed input audio signal to the at least one speaker. The audio processing module may include a digital amplifier amplifying a digital audio signal, a digital-to-analog converter (DAC) converting the digital audio signal into an analog audio signal, an analog amplifier amplifying the analog audio signal, a boost amplifier boosting the analog audio signal to a reference high voltage or more, and at least one noise gate removing noise included in the analog audio signal. The digital amplifier may apply a positive (+) digital gain to the digital audio signal. The analog amplifier may apply a negative (−) analog gain to the analog audio signal.

Classes IPC  ?

• H03F 3/181 - Amplificateurs à basse fréquence, p. ex. préamplificateurs à fréquence musicale
• H03G 3/30 - Commande automatique dans des amplificateurs comportant des dispositifs semi-conducteurs
• H03G 5/00 - Commande de tonalité ou commande de largeur de bande dans les amplificateurs
• H03M 1/72 - Conversion séquentielle dans des étages disposés en série
• H04R 3/12 - Circuits pour transducteurs pour distribuer des signaux à plusieurs haut-parleurs
• H04R 9/06 - Haut-parleurs
• H04R 17/00 - Transducteurs piézo-électriquesTransducteurs électrostrictifs

Abrégé

A method performed by a reception device in a wireless communication system is provided. The method includes generating one or more first sets by selecting three symbols in one slot, the three symbols corresponding to a first symbol, a second symbol and a third symbol, respectively, in an ascending order, for each of the one or more first sets, calculating an estimation range of a frequency offset, based on a first distance corresponding to a time interval between the first symbol and the second symbol and a second distance corresponding to a time interval between the second symbol and the third symbol, identifying, from among the one or more first sets, one or more second sets in which the calculated estimation range of the frequency offset is greatest, and transmitting a signal by arranging a reference signal (RS) symbols for one of the one or more second sets.

Classes IPC  ?

• H04L 5/00 - Dispositions destinées à permettre l'usage multiple de la voie de transmission

Abrégé

A system and a method for reusing carbon dioxide are provided. The method includes: producing reused carbon dioxide by purifying exhaust gas discharged from a semiconductor manufacturing apparatus; storing the produced reused carbon dioxide in a recovery tank; supplying the reused carbon dioxide from the recovery tank to a first supply tank; supplying the reused carbon dioxide from the first supply tank to a second supply tank; supplying the reused carbon dioxide from the second supply tank to the semiconductor manufacturing apparatus; determining whether a purity of the reused carbon dioxide flowing from the recovery tank to the first supply tank meets a predefined reference; and blocking flow of the reused carbon dioxide from the recovery tank to the first supply tank, based on determining that the purity of the reused carbon dioxide flowing from the recovery tank to the first supply tank does not meet the predefined reference.

Classes IPC  ?

• F25J 3/02 - Procédés ou appareils pour séparer les constituants des mélanges gazeux impliquant l'emploi d'une liquéfaction ou d'une solidification par rectification, c.-à-d. par échange continuel de chaleur et de matière entre un courant de vapeur et un courant de liquide
• C01B 32/50 - Anhydride carbonique
• G01N 1/22 - Dispositifs pour prélever des échantillons à l'état gazeux
• G01N 33/00 - Recherche ou analyse des matériaux par des méthodes spécifiques non couvertes par les groupes

Abrégé

A method includes obtaining, using multiple imaging sensors of an electronic device, a left image frame and a right image frame forming a stereo pair of image frames. The method also includes identifying, using at least one processing device of the electronic device, extrinsic parameters associated with relative positions and orientations of the imaging sensors. The method further includes performing, using the at least one processing device, an online stereo rectification of the stereo pair of image frames based on the extrinsic parameters such that epipolar lines of the left and right image frames are horizontally aligned to generate a rectified stereo pair of image frames. In addition, the method includes rendering, using the at least one processing device, one or more images for display based on the rectified stereo pair of image frames.

Classes IPC  ?

• H04N 13/111 - Transformation de signaux d’images correspondant à des points de vue virtuels, p. ex. interpolation spatiale de l’image
• G06T 7/33 - Détermination des paramètres de transformation pour l'alignement des images, c.-à-d. recalage des images utilisant des procédés basés sur les caractéristiques
• G06T 7/80 - Analyse des images capturées pour déterminer les paramètres de caméra intrinsèques ou extrinsèques, c.-à-d. étalonnage de caméra
• H04N 13/00 - Systèmes vidéo stéréoscopiquesSystèmes vidéo multi-vuesLeurs détails
• H04N 13/156 - Mélange de signaux d’images
• H04N 13/366 - Suivi des spectateurs

Abrégé

Provided are an electronic device and a method of operating the electronic device. The electronic device includes a communication interface, a memory storing at least one instruction, and a processor connected to the memory and the communication interface. The processor receives a signal including error information broadcast by another electronic device through the communication interface, the error information including information related to a communication connection loss occurring between the other electronic device and a server, identifies whether to transmit the error information to the server based on the received signal, and controls the communication interface to transmit the error information to the server based on identifying that the error information is to be transmitted to the server.

Classes IPC  ?

• H04L 41/06 - Gestion des fautes, des événements, des alarmes ou des notifications

Abrégé

A semiconductor device may include a first active pattern on a substrate, a pair of first source/drain patterns on the first active pattern and a first channel pattern between the first source/drain patterns, the first channel pattern including first semiconductor patterns, which are spaced apart from each other in a stacked formation, a gate electrode on the first channel pattern, a first gate cutting pattern adjacent to the first channel pattern that penetrates the gate electrode, and a first spacer pattern between the first gate cutting pattern and the first channel pattern. The first spacer pattern may include a first remaining pattern adjacent to an outermost side surface of at least one of the first semiconductor patterns and a second remaining pattern on the first remaining pattern. The second remaining pattern may be spaced apart from the first gate cutting pattern.

Classes IPC  ?

• H10D 84/90 - Circuits intégrés à tranches maîtresses
• H10D 89/10 - Schémas de dispositifs intégrés

Abrégé

A 5th Generation (5G) or pre-5G communication system for supporting a data transfer rate higher than that of a post-4th Generation (4G) communication system such as Long Term Evolution (LTE) is provided. The radio unit (RU) device includes a first printed circuit board (PCB) on which a plurality of antenna elements are disposed, a second PCB on which a radio frequency integrated circuit (RFIC) is disposed, and a third PCB configured to electrically connect each of the plurality of antenna elements and the RFIC between the first PCB and the second PCB, a first surface of the third PCB is coupled to a first surface of the first PCB through a grid array, and positions of feeding ports on the first surface of the third PCB correspond to positions in which ports of the plurality of antenna elements are disposed on a second surface opposite the first surface of the first PCB.

Classes IPC  ?

• H01Q 1/24 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets avec appareil récepteur
• H01Q 1/22 - SupportsMoyens de montage par association structurale avec d'autres équipements ou objets

Abrégé

In some embodiments, a semiconductor memory device includes a peripheral circuit structure, and a first and a second cell array structure. The peripheral circuit structure includes a circuit board, a peripheral circuit on the circuit board, a first insulating layer, and a plurality of first bonding pads on the first insulating layer. The first cell array structure includes a first memory cell array, a first conductive plate structure, a second insulating layer, and pluralities of second and third bonding pads on the second insulating layer. The second cell array structure includes a second memory cell array, a second conductive plate structure, a third insulating layer, and a plurality of fourth bonding pads on the third insulating layer. The first cell array structure and the second cell array structure are sequentially stacked in a vertical direction on the peripheral circuit structure.

Classes IPC  ?

• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/16 - Circuits pour effacer électriquement, p. ex. circuits de commutation de la tension d'effacement pour effacer des blocs, p. ex. des réseaux, des mots, des groupes
• G11C 16/34 - Détermination de l'état de programmation, p. ex. de la tension de seuil, de la surprogrammation ou de la sousprogrammation, de la rétention
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou

Abrégé

Embodiments herein provide a method and an electronic device of multi-stage enhancement for obtaining a fine-tuned image. The method includes receiving, by an electronic device 201, an input image. The input image includes a noise element and an image feature to be enhanced. Further, the method includes decoding the input image to obtain a low-resolution image. Thereafter, the method generates a denoised image by removing the at least one noise element from the low-resolution image based on a noise reduction model.

Classes IPC  ?

• G06T 5/70 - DébruitageLissage
• G06T 3/4053 - Changement d'échelle d’images complètes ou de parties d’image, p. ex. agrandissement ou rétrécissement basé sur la super-résolution, c.-à-d. où la résolution de l’image obtenue est plus élevée que la résolution du capteur
• G06T 5/50 - Amélioration ou restauration d'image utilisant plusieurs images, p. ex. moyenne ou soustraction

Abrégé

A method of semi-persistently scheduled (SPS) release, comprising: receiving, by a user equipment (UE), one or more occasions of SPS physical downlink shared channels (PDSCHs) over multiple slots for a transport block (TB) according to an SPS configuration; receiving, by the UE, a physical downlink control channel (PDCCH) including a downlink control information (DCI) format such that an end of a last symbol of the PDCCH is received before or at a same time as an end of a last symbol of a first occasion of a received SPS PDSCH; and releasing, by the UE, the SPS configuration in response to receiving the PDCCH.

Classes IPC  ?

• H04W 72/1273 - Jumelage du trafic à la planification, p. ex. affectation planifiée ou multiplexage de flux de flux de données en liaison descendante
• H04W 72/21 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens ascendant de la liaison sans fil, c.-à-d. en direction du réseau
• H04W 72/23 - Canaux de commande ou signalisation pour la gestion des ressources dans le sens descendant de la liaison sans fil, c.-à-d. en direction du terminal

Abrégé

Provided are a switching device and a memory device including the switching device. The switching device includes first and second electrodes, and a switching material layer provided between the first and second electrodes and including a chalcogenide. The switching material layer includes a core portion and a shell portion covering a side surface of the core portion. The switching layer includes a material having an electrical resistance greater than an electrical resistance of the core portion, for example in at least one of the core portion or the shell portion.

Classes IPC  ?

• H10B 63/00 - Dispositifs de mémoire par changement de résistance, p. ex. dispositifs RAM résistifs [ReRAM]
• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou
• H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation

Abrégé

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method disclosed herein includes using a hierarchical signalling to provide one or more MBS services to a User Equipment (UE), wherein an MBS System Information Block (SIB) is used to signal MBS control channel (MCCH) information, and a MCCH message is used to signal the MBS traffic channel (MTCH) information.

Classes IPC  ?

• H04W 4/06 - Répartition sélective de services de diffusion, p. ex. service de diffusion/multidiffusion multimédiaServices à des groupes d’utilisateursServices d’appel sélectif unidirectionnel
• H04W 72/30 - Gestion des ressources des services de diffusion
• H04W 76/27 - Transitions entre états de commande de ressources radio [RRC]
• H04W 76/28 - Transmission discontinue [DTX]Réception discontinue [DRX]

Abrégé

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.

Classes IPC  ?

• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

A semiconductor device includes a cell structure, and a peripheral circuit structure disposed on the cell structure. The cell structure includes a first substrate having a cell array region, data storage patterns spaced apart from each other on the cell array region, word lines on the data storage patterns, and spaced apart from each other, and bit lines crossing the word lines on the word lines. The peripheral circuit structure includes a first region overlapping the cell array region and a second region spaced apart from the first region, first and second transistors, on the first region, disposed on one surface of the second substrate, and a first penetration electrode disposed between the first and second transistors, and vertically extending through the second substrate on the first region to be electrically connected to the bit lines. The first transistors and the second transistors have different conductivity type channel regions.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

An error correction code circuit, an operating method thereof, and a storage device are disclosed. The error correction code circuit includes a forward error correction (FEC) decoder configured to correct an error of a codeword based on a first generator polynomial with respect to a first primitive polynomial having a calculation complexity among primitive polynomials having a leading term m on a Galois field GF(2m), and a cyclic redundancy check (CRC) decoder configured to detect an error of an error-corrected CRC codeword based on a second generator polynomial with respect to a second primitive polynomial different from the first primitive polynomial. The respective values of the coefficients of the second generator polynomial are symmetrical to each other based on the intermediate-order term.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

A method and device for adaptive user equipment (UE) beam refinement procedure triggering and traffic-based beam management procedure training. A method comprises determining, via a base station (BS), that one or more trigger conditions have occurred. The method includes determining to trigger a UE beam refinement procedure based on determining that the trigger conditions have occurred, and transmitting a reference signal with repetitions for UE beam selection for the UE beam refinement procedure.

Classes IPC  ?

• H04B 7/06 - Systèmes de diversitéSystèmes à plusieurs antennes, c.-à-d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission

Abrégé

An integrated circuit device includes a gate line extending in a first direction, which is generally normal to a surface of an underlying substrate, and a dielectric layer at least partially surrounding a sidewall of the gate line. A metal layer is provided, which at least partially surrounds the sidewall of the gate line, and a fixed charge layer is provided, which at least partially surrounds the sidewall of the gate line. A gate dielectric layer is provided, which at least partially surrounds the sidewall of the gate line, and a ring-shaped channel layer is provided on the gate dielectric layer.

Classes IPC  ?

• H10B 51/30 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H10B 51/20 - Dispositifs de RAM ferro-électrique [FeRAM] comprenant des transistors ferro-électriques de mémoire caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur

Abrégé

A method of manufacturing a semiconductor device includes forming a mask layer structure on a substrate including a first region and a second region, the mask layer structure covering the first region and the second region of the substrate, forming a first photoresist pattern covering at least part of the second region and exposing the first region of the mask layer structure, forming a second photoresist pattern on the mask layer structure and the first photoresist pattern, and etching the mask layer structure by using the first photoresist pattern and the second photoresist pattern.

Classes IPC  ?

• H01L 21/033 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou comportant des couches inorganiques
• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, comprising: a gate electrode and a back-gate electrode on a substrate, wherein the gate electrode and the back-gate electrode are spaced apart from each other in a first direction and extend in a second direction; a semiconductor pattern between the gate electrode and the back-gate electrode in the first direction, wherein the semiconductor pattern extends in a third direction; an upper gate capping pattern on the gate electrode; and an upper back-gate capping pattern on the back-gate electrode, wherein the semiconductor pattern extends between the upper gate capping pattern and the upper back-gate capping pattern, and wherein the upper gate capping pattern comprises a first insulating material having a first dielectric constant that is greater than a second dielectric constant of a second insulating material in the upper back-gate capping pattern.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device includes a first active pattern and a second active pattern spaced apart from each other in a first direction, a first semiconductor pattern and a second semiconductor pattern overlapping the first active pattern, a third semiconductor pattern and a fourth semiconductor pattern overlapping the second active pattern, a lower isolation insulating layer between the first and second active patterns, source/drain patterns on the first and second active patterns and a gate electrode extending in the first direction. The first and third semiconductor patterns are arranged in the first direction as are the second and fourth semiconductor patterns. A width of the first semiconductor pattern in the first direction is greater than a width of the second semiconductor pattern in the first direction. A width of the third semiconductor pattern in the first direction is greater than a width of the fourth semiconductor pattern in the first direction.

Classes IPC  ?

• H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
• H10D 84/01 - Fabrication ou traitement

Abrégé

A display device including a display including a plurality of light emitting devices (LEDs) arranged in a plurality of lines; a scan integrated circuit (IC) configured to scan the plurality of lines in which the plurality of LEDs are arranged; and a controller is configured to apply, to the scan IC, a control signal including a plurality of clock intervals having different frequencies, wherein, based on the control signal received from the controller, the scan IC non-sequentially scans the plurality of lines.

Classes IPC  ?

• G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]

Abrégé

A memory device including: a memory cell array including a first memory block; a control logic circuit configured to receive an erase command from an external controller and to control an erase operation on the first memory block in response to the erase command; an erase to program interval (EPI) timer configured to begin measuring a first EPI time of the first memory block in response to the erase command; and a memory circuit configured to store an EPI table that stores the first EPI time, wherein, when the first EPI time exceeds a reference time, the control logic circuit is further configured to provide EPI information to the external controller.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

An integrated circuit (IC) includes a plurality of first tap cells arranged in a first column, and a plurality of second tap cells arranged in a second column and disposed in a row different from a row in which the plurality of first tap cells are disposed. The second column is adjacent to the first column in a first direction and spaced apart from the first column by a first distance. The IC includes a plurality of third tap cells arranged in a third column and disposed in a row different from the row in which the plurality of first tap cells are disposed and different from the row in which the plurality of second tap cells are disposed. The third column is adjacent to the first column in the first direction and spaced apart from the first column by a second distance that is different from the first distance.

Classes IPC  ?

• H10D 89/10 - Schémas de dispositifs intégrés
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

A display module includes a display panel, a support plate, including a bendable region including a lattice pattern, a first region spaced from the bendable region in a first direction, and a second region between the first region and the bendable region, and an adhesive layer between the display panel and the support plate, the adhesive layer including an adhesive area and a non-adhesive area, the adhesive layer includes a first portion on the first region of the support plate, the first portion including the adhesive area; and a second portion on the second region of the support plate, the second portion including the adhesive area and the non-adhesive area, a ratio of the adhesive area of the second portion increasing along the first direction.

Classes IPC  ?

• H05K 5/02 - Enveloppes, coffrets ou tiroirs pour appareils électriques Détails

Abrégé

A semiconductor device includes a receiver and a controller. The receiver is configured to sample a data signal and a track signal received through data lanes in response to rising edges of first and second internal clock signal pairs. The controller is configured to detect a skew status between the track signal and the first and second internal clock signal pairs, based on the number of times a specific logic level of the track signal is sampled in synchronization with each of the first and second internal clock signal pairs, and provide the receiver with a clock shift signal for calibrating a clock skew, based on the skew status.

Classes IPC  ?

• H03L 7/081 - Détails de la boucle verrouillée en phase avec un déphaseur commandé additionnel
• H03K 3/037 - Circuits bistables
• H03L 7/091 - Détails de la boucle verrouillée en phase concernant principalement l'agencement de détection de phase ou de fréquence, y compris le filtrage ou l'amplification de son signal de sortie le détecteur de phase ou de fréquence utilisant un dispositif d'échantillonnage

Abrégé

Disclosed is an electronic device that includes a memory device operating in a current frequency set point (FSP) operation mode among FSP operation modes and a system-on-chip (SoC) controlling the memory device. The memory device includes FSP mode register sets storing FSP data sets respectively corresponding to the FSP operation modes, and a temperature monitoring circuit monitoring a temperature range of the memory device. The SoC controls the current FSP operation mode based on a current operation frequency of the memory device and a current temperature range of the memory device. The FSP operation modes include a first FSP operation mode for an operation of the memory device at a first operation frequency and a first temperature range, and a second FSP operation mode for an operation of the memory device at the first operation frequency and a second temperature range higher than the first temperature range.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A verification system for verifying a cell area of a flash memory model includes memory including a memory area, wherein, in order to verify the cell area, the cell area is modeled as the memory area, and an integrated circuit configured to perform a verification operation on the memory based on a verification signal for the flash memory model, wherein the integrated circuit includes a memory control logic configured to map the cell area of the flash memory model to the memory area of the memory based on the verification signal and to perform a memory operation corresponding to the verification signal to read verification data associated with the verification operation from the memory.

Classes IPC  ?

• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET

Abrégé

A semiconductor package includes a semiconductor chip including a plurality of through vias, a plurality of stacked structures located on a top surface of the semiconductor chip and including a plurality of core chips stacked in a vertical direction, the plurality of stacked structures spaced apart from one another in a horizontal direction, a stiffener located on the plurality of stacked structures, a first adhesive layer located on a bottom surface of the stiffener and including a top surface having the same area as a bottom surface of the stiffener, and a molding layer located on a top surface of the semiconductor chip and surrounding the plurality of stacked structures, the stiffener, and the first adhesive layer. A thermal expansion coefficient of the stiffener is the same as that of the semiconductor chip, and an uppermost surface of the molding layer is coplanar with a top surface of the stiffener.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 25/03 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses

Abrégé

A semiconductor device includes a peripheral circuit pattern on a substrate including first and second regions, a bit line structure on the peripheral circuit pattern electrically connected to the peripheral circuit pattern on the first region of the substrate, a channel on and electrically connected to the bit line structure, a word line at a side of the channel, a capacitor on and electrically connected to the channel, a plate electrode on an upper surface and a sidewall of the capacitor, an etch stop pattern on the second region of the substrate, and a first through via on and electrically connected to the peripheral circuit pattern on the second region of the substrate. A lower surface of the etch stop pattern is coplanar with a lower surface of the channel, and the first through via extends through the etch stop pattern in a vertical direction, and contacts the plate electrode.

Classes IPC  ?

• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor memory device includes a stacked structure comprising gate electrodes and interlayer insulating layers that are alternately stacked; a source structure on the stacked structure; and channel structures extending in the stacked. Each of the channel structures includes a core insulator that extends in the stacked structure in the vertical direction, wherein the core insulator protrudes into the source structure; a channel layer extending around the core insulator; and a gate dielectric layer extending around at least a portion of the channel layer, wherein a portion of the gate dielectric layer extends in a horizontal direction on the stacked structure. The source structure includes a first source part that is in contact with the channel structures and second source parts spaced apart from the channel structures by the first source part, wherein the first source part has a different crystal structure from the second source parts.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

An electronic apparatus including at least one processor configured to identify an audio apparatus connectable to the electronic apparatus through a communication interface, acquire, from the audio apparatus through the communication interface, channel configuration information related to a plurality of speakers included in the audio apparatus, a position response signal representing a position of the audio apparatus, and tilt angle information representing a degree to which the audio apparatus is tilted in space, identify an arrangement position of the audio apparatus based on the position response signal, identify an arrangement angle of the audio apparatus based on the tilt angle information, acquire audio data for outputting different audio signals to each of the plurality of speakers of the audio apparatus based on audio content stored by the electronic apparatus, the channel configuration information, the arrangement position, and the arrangement angle, and transmit the audio data to the audio apparatus.

Classes IPC  ?

• H04S 7/00 - Dispositions pour l'indicationDispositions pour la commande, p. ex. pour la commande de l'équilibrage
• G06F 3/16 - Entrée acoustiqueSortie acoustique
• H04R 3/12 - Circuits pour transducteurs pour distribuer des signaux à plusieurs haut-parleurs
• H04R 5/02 - Dispositions spatiales ou structurelles de haut-parleurs
• H04R 5/04 - Circuits
• H04S 3/00 - Systèmes utilisant plus de deux canaux, p. ex. systèmes quadriphoniques

Abrégé

A method of manufacturing a semiconductor device includes forming a lower insulating layer on a substrate, forming line patterns extending in a first direction, forming a mask structure on the line patterns, forming a photoresist pattern including a first opening on the mask structure, etching the mask structure using the photoresist pattern, etching the line patterns using the etched mask, etching the lower insulating layer using the etched line patterns to form lower patterns, and etching the substrate using the lower patterns. The line patterns include a first line pattern overlapping the first opening, and a second line pattern and a third line pattern adjacent to the first line pattern. The first opening includes a first inner wall, a second inner wall facing the first inner wall, and a third inner wall between the first and second inner walls.

Classes IPC  ?

• H01L 21/308 - Traitement chimique ou électrique, p. ex. gravure électrolytique en utilisant des masques
• H01L 21/311 - Gravure des couches isolantes

Abrégé

A method of fabricating a semiconductor device includes forming capping patterns that are spaced apart in a first direction on a second side of a semiconductor structure, and forming channel structures that are spaced apart in the first direction on a first side of the semiconductor structure. A bottom portion of a gate structure extends between first and second channel structures among the channel structures. The first and second channel structures vertically overlap first and second capping patterns among the capping patterns, respectively. The method further includes forming a backside gate contact structure that contacts the bottom portion of the gate structure and is aligned based on the first and second capping patterns.

Classes IPC  ?

• H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

A semiconductor device includes: a substrate including a first active pattern and a second active pattern that are spaced apart from each other in a first direction; first doped regions disposed on the first active pattern and spaced apart from each other in a second direction that intersects the first direction; lower doped regions interposed between the first doped regions and spaced apart from each other in the second direction; and an erase gate disposed on the first active pattern and the lower doped regions, wherein the first doped regions and the lower doped regions have a same conductivity type as each other, and wherein the first doped regions include a material that is different from a material of the lower doped regions.

Classes IPC  ?

• H10D 30/68 - Transistors IGFET à grille flottante
• H10D 30/01 - Fabrication ou traitement

Abrégé

A frequency control method for a neural processing unit according to at least one embodiment includes receiving information about a neural network model to be executed on a neural processing unit (NPU), extracting static feature data determined within offline time of the neural network model and dynamic feature data determined within runtime of the neural network model from information about the NPU and information about the neural network model, generating a prediction model for predicting operating frequency of the NPU for executing the neural network model based on the static feature data and the dynamic feature data, and controlling the operating frequency of the NPU based on the prediction model.

Classes IPC  ?

• G06F 11/34 - Enregistrement ou évaluation statistique de l'activité du calculateur, p. ex. des interruptions ou des opérations d'entrée–sortie
• G06N 3/045 - Combinaisons de réseaux
• G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques

Abrégé

A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Classes IPC  ?

• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H01L 21/285 - Dépôt de matériaux conducteurs ou isolants pour les électrodes à partir d'un gaz ou d'une vapeur, p. ex. condensation
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 41/35 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région noyau de mémoire avec un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/40 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique
• H10B 41/41 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région de circuit périphérique de régions de mémoire comprenant un transistor de sélection de cellules, p. ex. NON-ET
• H10B 41/50 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par la région limite entre la région noyau et la région de circuit périphérique
• H10B 43/10 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la configuration vue du dessus
• H10B 43/30 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire
• H10B 43/35 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région noyau de mémoire avec transistors de sélection de cellules, p. ex. NON-ET
• H10B 43/40 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région de circuit périphérique
• H10B 43/50 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par la région limite entre la région noyau et la région de circuit périphérique
• H10B 69/00 - Dispositifs de mémoire morte reprogrammable [EPROM] non couverts par les groupes , p. ex. dispositifs de mémoire morte reprogrammable aux ultraviolets [UVEPROM]
• H10D 1/00 - Résistances, Condensateurs, Inducteurs
• H10D 30/01 - Fabrication ou traitement
• H10D 64/01 - Fabrication ou traitement

Abrégé

A semiconductor package includes: a package substrate and a plurality of semiconductor chips stacked on the package substrate in a vertical direction, wherein each of the plurality of semiconductor chips includes a semiconductor substrate including a first surface, a lower semiconductor device on the first surface, a second surface opposite to the first surface, and an upper semiconductor device on the second surface, a lower wiring structure disposed on the first surface, and an upper wiring structure disposed on the second surface.

Classes IPC  ?

• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe

Abrégé

A method of manufacturing a power semiconductor device includes forming a drift layer, a well region, and a source region to form a substrate structure, forming mask layers on upper and lower surfaces of the substrate structure, performing a first annealing process on the substrate structure, forming a preliminary gate insulating layer on the upper surface of the substrate structure, performing a second annealing process on the substrate structure, forming a preliminary gate electrode layer on the preliminary gate insulating layer, forming a gate insulating layer and a gate electrode layer, forming a dielectric layer on the gate electrode layer, forming a source electrode coupled with the source region, forming a drain electrode on the lower surface of the substrate, and performing a high-pressure annealing process using deuterium subsequent to at least one of the performing the second annealing process or the forming of the dielectric layer.

Classes IPC  ?

• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
• H01L 21/324 - Traitement thermique pour modifier les propriétés des corps semi-conducteurs, p. ex. recuit, frittage
• H01L 29/16 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée
• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter

Abrégé

An organometallic compound represented by Formula 1: An organometallic compound represented by Formula 1: wherein, in Formula 1, M1 is a transition metal, L1 is a ligand represented by Formula 1A, L2 is a ligand represented by Formula 1B, and n1 and n2 are each independently 1 or 2, An organometallic compound represented by Formula 1: wherein, in Formula 1, M1 is a transition metal, L1 is a ligand represented by Formula 1A, L2 is a ligand represented by Formula 1B, and n1 and n2 are each independently 1 or 2, wherein Formulae 1A and 1B are as described in the present specification.

Classes IPC  ?

• H10K 85/30 - Composés de coordination
• C07F 19/00 - Composés métalliques couverts par plus d'un des groupes principaux
• C09K 11/06 - Substances luminescentes, p. ex. électroluminescentes, chimiluminescentes contenant des substances organiques luminescentes
• H10K 50/12 - OLED ou diodes électroluminescentes polymères [PLED] caractérisées par les couches électroluminescentes [EL] comprenant des dopants
• H10K 85/40 - Composés organosiliciés, p. ex. pentacène TIPS

Abrégé

A heat treatment apparatus includes a stage having a surface configured to support a substrate, wherein an exposed resist film is formed on the substrate; and a heater spaced apart from the stage in a direction perpendicular to the surface of the stage, wherein the heater is configured such that a relative movement occurs between the stage and the heater that is parallel to the surface of the stage, and the heater is configured to apply heat energy to the substrate in a position at which the heater overlaps with the stage in the direction perpendicular to the surface of the stage during the relative movement between the stage and the heater.

Classes IPC  ?

• G03F 7/20 - ExpositionAppareillages à cet effet
• G03F 7/00 - Production par voie photomécanique, p. ex. photolithographique, de surfaces texturées, p. ex. surfaces impriméesMatériaux à cet effet, p. ex. comportant des photoréservesAppareillages spécialement adaptés à cet effet
• H05B 3/00 - Chauffage par résistance ohmique

Abrégé

A semiconductor package includes a first semiconductor chip having a chip region and a dummy region surrounding the chip region in a plan view, a second semiconductor chip on an upper surface of the chip region of the first semiconductor chip, and a molding layer configured to cover the second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip has a recessed portion in an outer wall of the first semiconductor chip and an upper surface of the dummy region of the first semiconductor chip, and surface roughness of an inner surface of the recessed portion of the first semiconductor chip is greater than surface roughness of an outer wall of the molding layer.

Classes IPC  ?

• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe

Abrégé

The present disclosure aims to provide a photoelectric conversion device capable of suppressing an increase in power consumption of a SPAD pixel. For example, a photoelectric conversion device may include an avalanche photodiode including an anode and a cathode in each pixel of a pixel array. The device may include a recharger configured to recharge the anode or the cathode once per unit exposure time, a gating circuit configured to generate a pulse signal based on an output of the avalanche photodiode at a plurality of different timings within the unit exposure time, and a counter configured to count the pulse signal from the gating circuit.

Classes IPC  ?

• H04N 25/773 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des convertisseurs A/N, V/T, V/F, I/T ou I/F comprenant des circuits de comptage de photons, p. ex. des diodes de détection de photons uniques [SPD] ou des diodes à avalanche de photons uniques [SPAD]
• H04N 25/706 - Pixels pour la mesure de l'exposition ou de la lumière ambiante
• H04N 25/771 - Circuits de pixels, p. ex. mémoires, convertisseurs A/N, amplificateurs de pixels, circuits communs ou composants communs comprenant des moyens de stockage autres que la diffusion flottante

Abrégé

An image sensor includes a plurality of pixels. Each pixel of the plurality of pixels includes at least two photoelectric elements, at least two floating diffusion regions, a lateral overflow integration capacitor coupled with a floating diffusion region and configured to accumulate charges overflowed from a photoelectric element, a reset transistor coupling a floating diffusion region with a power supply voltage, a driving transistor having a gate coupled with a floating diffusion region and configured to operate based on a voltage of the floating diffusion region, a select transistor having a first terminal coupled with the driving transistor and a second terminal coupled with a column line, a deep trench isolation structure disposed between the at least two photoelectric elements, and a doped region doped with N type dopant disposed between a photoelectric element and a floating diffusion region.

Classes IPC  ?

• H10F 39/18 - Capteurs d’images à semi-conducteurs d’oxyde de métal complémentaire [CMOS]Capteurs d’images à matrice de photodiodes
• H10F 39/00 - Dispositifs intégrés, ou ensembles de plusieurs dispositifs, comprenant au moins un élément couvert par le groupe , p. ex. détecteurs de rayonnement comportant une matrice de photodiodes

Abrégé

An atomic layer deposition apparatus includes: a substrate mounting plate configured to have a substrate mounted thereon; a housing including an internal space in which the substrate mounting plate is accommodated; a reactant supplier including a plurality of regions respectively corresponding to a plurality of zones of the substrate; and a product measurer configured to measure a thickness of a product deposited on each of the plurality of zones, wherein the housing further includes a plurality of supply holes respectively corresponding to the plurality of regions and configured to allow a reactant to pass into the internal space from the reactant supplier, and the reactant supplier is configured to supply the reactant to the plurality of zones through the plurality of regions and the plurality of supply holes.

Classes IPC  ?

• C23C 16/455 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour introduire des gaz dans la chambre de réaction ou pour modifier les écoulements de gaz dans la chambre de réaction
• C23C 16/458 - Revêtement chimique par décomposition de composés gazeux, ne laissant pas de produits de réaction du matériau de la surface dans le revêtement, c.-à-d. procédés de dépôt chimique en phase vapeur [CVD] caractérisé par le procédé de revêtement caractérisé par le procédé utilisé pour supporter les substrats dans la chambre de réaction
• C23C 16/52 - Commande ou régulation du processus de dépôt

Abrégé

A semiconductor device includes: a lower stack including a plurality of lower gate lines and a plurality of lower nanosheets that are alternately stacked on a substrate; an upper stack including a plurality of upper gate lines and a plurality of upper nanosheets that are alternately stacked on the lower stack; a lower source/drain region disposed on a side surface of the lower stack; and an upper source/drain region disposed on the lower source/drain region and adjacent to a side surface of the upper stack, wherein the upper source/drain region includes a side impurity layer and an upper center impurity layer, wherein the side impurity layer extends in a vertical direction along the side surface of the upper stack, and the upper center impurity layer is disposed on an inner side of the side impurity layer, and a first surface of the upper center impurity layer has a curved shape.

Classes IPC  ?

• H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
• H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
• H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
• H01L 29/786 - Transistors à couche mince

Abrégé

An integrated circuit device includes a substrate and a bit line extending in a first direction thereon. A plurality of semiconductor patterns are provided, which extend on the bit line, along with a back-gate electrode, which extends between the plurality of semiconductor patterns and in a second direction different from the first direction. A back-gate separation pattern is provided, which extends on a bottom surface of the back-gate electrode and between the plurality of semiconductor patterns. The back-gate separation pattern may include an insulating material, which has a dielectric constant lower than a dielectric constant of SiON and has an impurity therein selected from a group consisting of nitrogen (N) and fluorine (F).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor chip for a bonding semiconductor device includes a substrate, a wiring portion on the substrate, and a bonding portion on the wiring portion. The bonding portion includes an insulation layer, a bonding structure, and an extension pattern. The bonding structure includes a pad structure passing through the insulation layer and a dummy structure passing through a partial portion of the insulation layer. The extension pattern is at a lower portion of the dummy structure that is adjacent to the wiring portion and includes an extension portion extending in one direction in a plan view.

Classes IPC  ?

• H01L 23/528 - Configuration de la structure d'interconnexion
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
• H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
• H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré

Abrégé

A display device includes a display panel, display pixels arranged in a display area of the display panel, light sensing pixels in the display area together with the display pixels, infrared light emitting pixels in the display area together with the display pixels, a display scan driver to drive the display pixels and the light sensing pixels to emit light, a light sensing scan driver to drive the light sensing pixels to detect light, and a main driving circuit to detect pulse wave signals of a user using light sensing signals received through the light sensing pixels and to measure biometric information, wherein the main driving circuit is to separate and generate blood vessel image data from image data and to receive the light sensing signals of a light receiving area by distinguishing the light receiving area according to the blood vessel image data in the display area.

Classes IPC  ?

• G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage

Abrégé

Provided is a method for dry-etching a silicon oxide layer, the method includes selectively etching a first layer including the silicon oxide layer by allowing etching gas including hydrogen fluoride, an amine compound, and inert gas to react with a stack structure including the first layer and a second layer, which includes a material different from the silicon oxide layer and is stacked on the first layer, in which the first layer includes the silicon oxide layer, the selectively-etching includes allowing the etching gas to self-limiting react with the exposed region at the first layer and removing the region subject to the self-limiting reaction.

Classes IPC  ?

• H01L 21/311 - Gravure des couches isolantes

Abrégé

A deposition mask is provided. The deposition mask includes a substrate including a plurality of cell regions, a mask lip region partitioning the plurality of cell regions, and an outer frame region outside the plurality of cell regions, a mask membrane including a first inorganic film on the substrate corresponding to the plurality of cell regions, and a warpage compensation pattern including a second inorganic film on the substrate corresponding to the outer frame region. A material of the first inorganic film is a material that exerts stress on the substrate in a first reference direction. A material of the second inorganic film is a material that exerts stress on the substrate in the first reference direction.

Classes IPC  ?

• C23C 16/04 - Revêtement de parties déterminées de la surface, p. ex. au moyen de masques

Abrégé

A display device comprises a display panel including a folding area and a non-folding area, and a cover window on the display panel and including a folding portion and a non-folding portion. The cover window comprises a glass layer, a coating layer on the glass layer, an adhesive layer on the coating layer, and a protective layer on the adhesive layer. The thickness of the coating layer is 30 μm to 90 μm. Edges of the protective layer, the adhesive layer, and the coating layer are aligned. The folding portion includes an inner surface that is compressed when folded and an outer surface that is stretched when folded. The folding portion overlaps the folding area, and the non-folding portion overlaps the non-folding area.

Classes IPC  ?

• H10K 59/80 - Détails de structure
• H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
• H10K 102/00 - Détails de structure relatifs aux dispositifs organiques couverts par la présente sous-classe

Abrégé

Each of a plurality of stages of a driving circuit includes a first transistor connected to an input terminal, to which a start signal is input, and a first node and including a gate connected to a first clock terminal, to which a first clock signal is input, and a second transistor connected to a first output terminal and a second clock terminal, to which a second clock signal is input, and including a gate connected to the first node. The second clock signal swings between a first voltage and a second voltage lower than the first voltage, and the first clock signal swings between the first voltage and a third voltage lower than the second voltage.

Classes IPC  ?

• G09G 3/3266 - Détails des circuits de commande pour les électrodes de balayage

Abrégé

A display device may include a substrate including a display area and a peripheral area disposed outside a display area, a light-emitting element disposed on the display area of the substrate, a static electricity prevention layer configured to cover a side surface of the substrate, and a static electricity test wire disposed on the peripheral area, where the static electricity test wire may include a plurality of first test wires spaced apart from each other and connected to the static electricity prevention layer, respectively, and a second test wire electrically connected to the plurality of first test wires.

Classes IPC  ?

• H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
• H10K 59/124 - Couches isolantes formées entre les éléments TFT et les éléments OLED

Abrégé

A method for manufacturing a window includes providing a glass substrate including a first non-folding region, a second non-folding region, and a folding region interposed between the first non-folding region and the second non-folding region, forming a photoresist layer on the glass substrate, forming an opening pattern in the photoresist layer, wherein the opening pattern overlaps with the folding region and exposes the glass substrate, etching the glass substrate by supplying a first etchant to the glass substrate exposed through the opening pattern, removing the photoresist layer having the opening pattern, and polishing at least a portion of the glass substrate by supplying a second etchant to a top surface of the glass substrate.

Classes IPC  ?

• C03C 15/02 - Traitement de surface du verre, autre que sous forme de fibres ou de filaments, par attaque chimique pour l'obtention d'une surface unie
• H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
• H10K 59/80 - Détails de structure
• H10K 71/00 - Fabrication ou traitement spécialement adaptés aux dispositifs organiques couverts par la présente sous-classe

Abrégé

The present disclosure relates to a display device, and more particularly, to a display device capable of reducing or minimizing loss of image data information in merged pixels. A display device includes: a light-emitting element; a first switching transistor connected to a scan line and a first data line; a driving transistor connected to the first switching transistor, a driving voltage line, and the light-emitting element; a capacitor, one electrode of the capacitor being connected to a source electrode of the driving transistor; a second switching transistor connected to the scan line and a second data line; and a voltage divider connected to an other electrode of the capacitor, the first switching transistor, and the second switching transistor.

Classes IPC  ?

• H10K 59/121 - Affichages à OLED à matrice active [AMOLED] caractérisés par la géométrie ou la disposition des éléments de pixel
• G02B 27/01 - Dispositifs d'affichage "tête haute"
• H10H 29/32 - Affichages LED à matrice active caractérisés par la géométrie ou l’agencement des éléments à l’intérieur d’un sous-pixel, p. ex. l’agencement du transistor à l’intérieur de son sous-pixel RGB
• H10H 29/49 - Interconnexions, p. ex. lignes de câblage ou bornes
• H10K 59/131 - Interconnexions, p. ex. lignes de câblage ou bornes
• H10K 102/00 - Détails de structure relatifs aux dispositifs organiques couverts par la présente sous-classe

Abrégé

A display device includes a display panel, and a panel driver which drives the display panel. The panel driver receives a multi-frequency driving (“MFD”) enable command from a host processor. In a first frame period, the panel driver receives a boundary setting command indicating a boundary between a first panel region and a second panel region of the display panel from the host processor. In a second frame period after the first frame period, the panel driver receives input image data for the first panel region from the host processor, does not receive the input image data for the second panel region from the host processor, drives the first panel region based on the input image data for the first panel region, and does not drive the second panel region.

Classes IPC  ?

• G09G 3/20 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice

Abrégé

An operation plan derivation method includes outputting a plurality of initial operation plans by sampling a plurality of operation plans using a first algorithm. Each of the plurality of initial operation plans has an operation factor and a judgment factor corresponding to the operation factor. A simulation is performed on the plurality of initial operation plans. An optimal operation plan is output. The performing of the simulation includes evaluating a potential of an unobserved operation plan among the plurality of operation plans using a second algorithm. A plurality of areas is defined that includes the plurality of initial operation plans based on the evaluated potential. A weight is assigned according to the evaluated potential to each of the plurality of areas using a third algorithm. The plurality of operation plans is additionally sampled depending on the assigned weight using the first algorithm.

Classes IPC  ?

• G06Q 10/0631 - Planification, affectation, distribution ou ordonnancement de ressources d’entreprises ou d’organisations

Abrégé

A display device includes a bank layer disposed on an emission area of a substrate and comprising at least one metal layer; a pixel defining layer disposed on the bank layer and defining an opening; and a light-emitting element disposed on the pixel defining layer and comprising a light-emitting layer, a cathode electrode, and an auxiliary electrode. The bank layer includes a first side surface facing a non-emission area of the substrate; and a tip portion protruding further toward the non-emission area than the first side surface. A portion of the tip portion of the bank layer facing the non-emission area is inclined in a direction intersecting the substrate.

Classes IPC  ?

• H10K 59/122 - Structures ou couches définissant le pixel, p. ex. bords
• H10K 59/12 - Affichages à OLED à matrice active [AMOLED]
• H10K 59/80 - Détails de structure
• H10K 102/10 - Électrodes transparentes, p. ex. utilisant du graphène

Abrégé

A power supply includes: a converter configured to output a power supply voltage based on an output control signal; a first capacitor configured to discharge a first clamp voltage to a first resistor in a first mode and be to charged with the first clamp voltage in a second mode; and a second capacitor configured to be charged with a second clamp voltage in the first mode and to discharge the second clamp voltage to the first resistor in the second mode.

Classes IPC  ?

• G09G 3/3233 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED] organiques, p. ex. utilisant des diodes électroluminescentes organiques [OLED] utilisant une matrice active avec un circuit de pixel pour commander le courant à travers l'élément électroluminescent
• G09G 3/32 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice utilisant des sources lumineuses commandées utilisant des panneaux électroluminescents semi-conducteurs, p. ex. utilisant des diodes électroluminescentes [LED]