A display apparatus includes a substrate, a thin-film transistor, an insulating material stack, and a first dam structure. The substrate includes a display area and a peripheral area located outside the display area. The thin-film transistor layer overlaps the substrate. The insulating material stack overlaps the peripheral area. The first dam structure overlaps the substrate, is located closer to the display area than the insulating material stack, partially covers the insulating material stack, and reaches farther than the insulating material stack with reference to the substrate.
An electronic device includes a display layer and a sensor layer, the display layer including a common electrode, the sensor layer including first electrodes, second electrodes, third electrodes, and a loop trace line comprising a first line portion electrically connected to the third electrodes and extending along the first direction, a second line portion extending from an end of the first line portion in the second direction, and a third line portion extending an opposite end of the first line portion in the second direction, the second line portion and the third line portion being spaced from the common electrode in plan view.
A display panel includes a substrate including a first display area and a second display area, the second display area including a transmission area, a plurality of first pixel circuits and a plurality of first light-emitting diodes arranged in the first display area, a plurality of second pixel circuits arranged in the second display area and each including a first transistor and a second transistor, the first transistor including an oxide semiconductor, and the second transistor including a silicon semiconductor, a plurality of second light-emitting diodes arranged in the second display area and respectively connected to the plurality of second pixel circuits, and a bottom metal layer arranged in the second display area and between the substrate and the second transistor, wherein the bottom metal layer overlaps the second transistor of each of the plurality of second pixel circuits and extends across the second display area in a first direction.
A display module including: a display panel including pixels arranged in a display area, first signal pads arranged in a non-display area and electrically connected to the pixels through signal lines, and second signal pads arranged in the non-display area and spaced farther from the display area than the first signal pads; first insulating patterns arranged at edges of the first signal pads; second insulating patterns arranged at edges of the second signal pads; and an insulating film disposed on the non-display area, wherein the insulating film is spaced apart from the first signal pads and the first insulating patterns, overlaps the edges of the second signal pads, and covers the second insulating patterns.
H10H 20/857 - Interconnections, e.g. lead-frames, bond wires or solder balls
G06F 3/044 - Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
A mask assembly manufacturing apparatus for manufacturing a mask assembly, including a frame through which an opening is defined and a support bar disposed above the frame, includes a stage on which the frame is placed, an alignment unit disposed above the stage and including magnetic units, and a fixing unit disposed between the stage and the alignment unit and including a first sub-fixing unit which fixes one end of the support bar and a second sub-fixing unit which fixes another end of the support bar and spaced apart from the first sub-fixing unit in a first direction. The magnetic units includes first magnetic units disposed above the support bar and second magnetic units disposed above the support bar, spaced apart from the first magnetic units in a second direction perpendicular to the first direction, and having a polarity opposite to a polarity of the first magnetic units.
A display panel includes a substrate, a display layer disposed on the substrate, an encapsulation layer disposed on the display layer, a metal layer disposed on the encapsulation layer and including a tip portion that protrudes in one direction, and a light absorption layer disposed on the metal layer.
A stage circuit includes a controller connected to first and second power input terminals, to first and second carry input terminals, and to an initialization terminal, and configured to control a voltage of a connection control line, a driver configured to control voltages of first and second nodes, first outputs configured to supply scan clock signals as an enable scan signal to first output terminals based on voltages of first local nodes, second outputs configured to supply initialization clock signals as an enable initialization signal to second output terminals based on voltages of second local nodes, first connectors configured to control electrical connections between the first node and the first local nodes based on a voltage of the connection control line, and second connectors configured to control electrical connections between the first node and the second local nodes based on the voltage of the connection control line.
G09G 3/3266 - Details of drivers for scan electrodes
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
8.
DISPLAY DRIVER, DISPLAY DEVICE INCLUDING THE DISPLAY DRIVER, AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICE
A display driver includes an encoder, a first compensation volatile memory, a nonvolatile memory, and a second compensation volatile memory. The display driver further includes a verification value calculator and a data contamination verificator. The verification value calculator calculates a line count value and a checksum value for encoding compensation data generated based on compensation data. The data contamination verificator calculates a verification checksum value for the encoding compensation data using the line count value, and compares the verification checksum value with the checksum value to verify a data contamination of the encoding compensation data.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
A display device includes a protective layer. A display panel is disposed on an upper surface of the protective layer. The display panel includes a display area configured to display an image and a non-display area at least partially surrounding the display area. A cover panel is disposed on a back surface of the protective layer. The cover panel includes an opening that exposes the protective layer. A fingerprint sensor is disposed within the opening of the cover panel. The fingerprint sensor is configured to sense a fingerprint. A first fixing member is disposed on one surface of the fingerprint sensor. A second fixing member at least partially overlaps at least one side of the first fixing member, the second fixing member fixing the fingerprint sensor. The first fixing member and the second fixing member each include at least one different material from each other.
A display apparatus includes an auxiliary wiring on a substrate, an insulating layer disposed on the auxiliary wiring and that includes a first opening that overlaps the auxiliary wiring and has a greater width than a width of the auxiliary wiring, a first electrode disposed on the insulating layer, a bank layer that includes an emission opening that overlaps the first electrode, an intermediate layer that overlaps the first electrode through the emission opening and that includes an emission layer, and a second electrode disposed on the intermediate layer, wherein the auxiliary wiring includes a plurality of sub-layers, and the second electrode contacts a side surface of any one of the plurality of sub-layers through the first opening of the insulating layer.
A display device which includes a substrate including a display area where emission areas are arranged; a circuit layer on the substrate; and an element layer on the circuit layer. The circuit layer includes a light blocking conductive layer on the substrate; a buffer layer covering the light blocking conductive layer; a first semiconductor layer on the buffer layer; a first interlayer insulating layer on the first semiconductor layer; and a second semiconductor layer on the first interlayer insulating layer and including an oxide semiconductor material.
H10K 59/131 - Interconnections, e.g. wiring lines or terminals
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10K 59/121 - Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
H10K 59/126 - Shielding, e.g. light-blocking means over the TFTs
12.
DISPLAY DEVICE, DRIVING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE SAME
Provided is a display device which may include an i-th pixel which receives a data voltage and a reference voltage in response to an i-th scan signal during a display period, and an (i+1)-th pixel which receives the data voltage and the reference voltage in response to an (i+1)-th scan signal during the display period. The i-th scan signal may be applied to the i-th pixel during first to third periods of a blank period, the (i+1)-th scan signal may be applied to the (i+1)-th pixel during the first period, the i-th pixel may receive a data voltage for sensing and the reference voltage during the first period, and a level of the reference voltage may be changed by the (i+1)-th pixel.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G09G 3/00 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
G09G 3/3233 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
A display device in which a noise of a driving voltage and a voltage drop may be reduced, and an electronic device are provided. The display device includes: a display panel including a display area and a non-display area; a data driver, which is in the non-display area and is adjacent to a first edge of the display area; and a first decoupling circuit, which is in the non-display area, is adjacent to a second edge of the display area, and is connected to a sub-pixel of the display area through a driving voltage line, the second edge being opposite to the first edge.
G09G 3/3291 - Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
G09G 3/3266 - Details of drivers for scan electrodes
Provided is a display panel including a driving element layer having a pixel driver, a light-emitting element disposed on the driving element layer and having a first electrode, an intermediate layer disposed on the first electrode and having at least a light-emitting layer, and a second electrode disposed on the intermediate layer, a pixel-defining layer disposed on the driving element layer and having an opening exposing at least a portion of the first electrode, a connection electrode disposed on the pixel-defining layer and electrically connected to the pixel driver and the second electrode, and a separator disposed on the pixel-defining layer. In a contact region adjacent to the separator, a lower surface of the second electrode is in contact with an upper surface of the connection electrode.
G09G 3/3225 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
H10K 59/122 - Pixel-defining structures or layers, e.g. banks
H10K 59/88 - Dummy elements, i.e. elements having non-functional features
A display device includes a pixel electrode layer on a substrate and including a pixel electrode, an insulating layer on the pixel electrode layer and covering a portion of the pixel electrode, a light emitting element on the insulating layer and including a first contact electrode located at a first side surface, and a first connection electrode on the insulating layer and the first side surface of the light emitting element and connecting the pixel electrode and the first contact electrode. The insulating layer is located at least below bottom surface vertex portions of the light emitting element and supports the light emitting element. The insulating layer includes a first opening having a width smaller than a width of the first contact electrode and below a portion of the first contact electrode, and a portion of the first connection electrode is located inside the first opening.
A display device includes: a display panel including a first pixel circuit portion to drive a first light emitting diode to emit a first color; a second pixel circuit portion to drive a second light emitting diode to emit the first color; a third pixel circuit portion to drive a third light emitting diode to emit a second color; a fourth pixel circuit portion to drive a fourth light emitting diode to emit a third color; a fifth pixel circuit portion to drive a fifth light emitting diode to emit the first color; a sixth pixel circuit portion to drive a sixth light emitting diode to emit the first color; a seventh pixel circuit portion to drive a seventh light emitting diode to emit the second color; and an eighth pixel circuit portion to drive an eighth light emitting diode to emit the third color.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
17.
ELECTRONIC DEVICE, METHOD, AND COMPUTER-READABLE STORAGE MEDIUM FOR CONTROLLING ACTUATOR
An electronic device includes: a plurality of housings; a microphone; an actuator; at least one processor including processing circuitry; and memory including one or more storage media storing instructions, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to: identify, based on a position relationship of the plurality of housings, a state of the electronic device, based on the state of the electronic device being a first state, drive the actuator in a first frequency range identified through the microphone, and based on the state of the electronic device being a second state, drive the actuator in a second frequency range identified through the microphone, the second frequency range being different from the first frequency range
A memory device includes a memory cell array that includes a plurality of memory cells, an input/output circuit configured to transmit data received from an external source through a data pad to the memory cell array or transmit data read from the memory cell array to the external source, and an impedance calibration circuit configured to generate an impedance calibration code that is applied to the input/output circuit, the impedance calibration circuit is further configured to: divide a total impedance calibration section into a plurality of sub-impedance calibration sections, and perform at least one sub-impedance calibration in each of the plurality of sub-impedance calibration sections, the at least one sub-impedance calibration corresponding to at least one of a plurality of impedance modes.
A method for manufacturing a thermoelectric element, the method including preparing a Bi—Te based alloy material that includes Se in a range of 0.1 to 0.5 mol. % based on total moles of the Bi—Te based alloy material; primarily crushing the Bi—Te based alloy material between a pair of crushing plates having a gap between the crushing plates set to 1 mm to 5 mm, so as to form primarily crushed alloy pieces having a first length; and secondarily crushing the primarily crushed alloy pieces between a pair of disks having a gap between the disks set to 0.1 mm to 10 mm, so as to form an alloy powder including plate-shaped alloy powder having a second length smaller than the first length.
F25B 21/02 - Machines, plants or systems, using electric or magnetic effects using Peltier effectMachines, plants or systems, using electric or magnetic effects using Nernst-Ettinghausen effect
B22F 3/20 - Manufacture of workpieces or articles from metallic powder characterised by the manner of compacting or sinteringApparatus specially adapted therefor by extruding
A semiconductor package includes a first semiconductor chip, and at least one second semiconductor chip on the first semiconductor chip, the at least one second semiconductor chip including a substrate, an integrated device layer on the substrate, a multi-wiring layer on the integrated device layer having at least two layers of wires, and a pad metal layer on the multi-wiring layer, electrically connected to the wires, having test pads, pad metal layers including the pad metal layer arranged in a first direction parallel to a top surface of the semiconductor substrate or a second direction perpendicular to the first direction, and a test pad includes a central portion of the pad metal layer, the test pad is exposed by a protective layer that overlaps the pad metal layer, in a third direction perpendicular to the top surface of the semiconductor substrate, the wires disposed without overlapping the test pads.
Apparatuses and methods for system information block 1 (SIB1) repetition. A method performed by a user equipment includes receiving a synchronization signals and physical broadcast channel (SS/PBCH) block in a cell and identifying, based on a physical broadcast channel (PBCH) in the SS/PBCH block, an indication associated with a repetition of a physical downlink control channel (PDCCH). The method further includes determining, based on the indication, that a PDCCH carrying a downlink control information (DCI) format is to be monitored in a first slot (n0) and a second slot (n0+1), determining that the DCI format carried in a first PDCCH in the first slot and a second PDCCH in the second slot is the same, and receiving the first PDCCH and the second PDCCH.
H04W 72/232 - Control channels or signalling for resource management in the downlink direction of a wireless link, i.e. towards a terminal the control data signalling from the physical layer, e.g. DCI signalling
An electronic device comprises: a communication interface; a projection unit; a memory storing information about a projection range ratio for each aspect ratio of content provided to an external display device; and at least one processor, comprising processing circuitry, that, when image information and aspect ratio information corresponding to the content displayed on the external display device are received via the communication interface, identify a projection area on the basis of the received aspect ratio information corresponding to the content and information stored in the memory, identify a projection image to be output to the projection area on the basis of the aspect ratio information corresponding to the content, the image information, and the information stored in the memory, and control the projection unit so that the identified projection image is output to the identified projection area.
A wearable device includes, a housing, a display disposed on at least a portion of the front surface of the wearable device, a first conductive member included in the housing or disposed in the housing, a second conductive member disposed in the housing to be adjacent to the first conductive member, a non-conductive member that is disposed along one side of an area in which the display is visible through the front surface of the wearable device and supported by the first conductive member and the second conductive member, and a wireless communication circuit, wherein the wireless communication circuit may feed power to the first conductive member and/or the second conductive member and transmit and/or receive radio frequency (RF) signals in a first frequency band based on an electrical path formed in the first conductive member and the second conductive member.
H04B 1/00 - Details of transmission systems, not covered by a single one of groups Details of transmission systems not characterised by the medium used for transmission
H01Q 1/27 - Adaptation for use in or on movable bodies
A semiconductor device is provided. The semiconductor device includes a substrate, a first base fin protruding from the substrate and extending in a first direction, and a first fin type pattern protruding from the first base fin and extending in the first direction. The first base fin includes a first sidewall and a second sidewall, the first and second sidewalls extending in the first direction, the first sidewall opposite to the second sidewall, the first sidewall of the first base fin at least partially defines a first deep trench, the second sidewall of the first base fin at least partially defines a second deep trench, and a depth of the first deep trench is greater than a depth of the second deep trench.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
An electronic device is provided that includes a display and a processor that executes a first application based on a first language, displays a first execution screen corresponding to the first application, wherein a content, which changes over time, is displayed in a first area of the first execution screen, executes a second application in response to receiving a first user input, translates a text included in the first execution screen from the first language to a second language using the second application and displays the translation, in a state in which the second application is executed and in response to the content in the first area being changed, extracts the text included in the changed content, translates the extracted text from the first language to the second language using the second application, and displays a second execution screen corresponding to the first execution screen based on the second language.
Provided are systems, methods, and apparatuses for increasing the sense margin of memory sensing amplifiers in memory systems. In one or more examples, the disclosed systems, methods, and apparatuses include configuring a bitline selector to selectively couple a local bitline to a global bitline during a charge-sharing mode, the bitline selector including at least one transistor having a source terminal coupled to the local bitline and a drain terminal connected to a conductive connector that is connected to the global bitline; and forming an insulator between the bitline selector and underlying memory cells, the insulator to increase an inter-tier dielectric between the bitline selector and the underlying memory cells and between a capacitor area associated with the memory cells.
G11C 11/4094 - Bit-line management or control circuits
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
27.
SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME
There is provided a semiconductor package including a substrate, a first semiconductor die on the substrate, a second semiconductor die on the first semiconductor die, the second semiconductor die arranged with an offset in a first horizontal direction with respect to the first semiconductor die, a third semiconductor die on the second semiconductor die, the third semiconductor die arranged with an offset in a second horizontal direction opposite to the first horizontal direction with respect to the first semiconductor die, a fourth semiconductor die on the third semiconductor die, the fourth semiconductor die arranged with an offset in the first horizontal direction with respect to the second semiconductor die, and a plurality of bonding wires that electrically connects each of the first semiconductor die, the second semiconductor die, the third semiconductor die, and the fourth semiconductor die to the substrate.
Provided is a communication device including an antenna tuner configured to adjust impedance based on a first tune code; and a processor configured to: obtain a first reflection coefficient of the antenna tuner based on a forward signal transmitted to an antenna through the antenna tuner and a reverse signal received through the antenna tuner, the reverse signal including at least a portion of a reflected signal of the forward signal; obtain a second reflection coefficient of the antenna based on the first reflection coefficient and a first scattering parameter (S-parameter) set corresponding to the first tune code; and generate a second tune code based on the second reflection coefficient.
An electronic device is provided. The electronic device includes a housing including a first surface, a second surface opposite to the first surface, and a side member surrounding at least a portion of an inner space between the first surface and the second surface, cover glass disposed on the first surface of the housing, a connection member connected to the inside of the side member and supporting at least a portion of the cover glass, and a support member connected to the connection member and supporting an edge of the cover glass, wherein the surfaces of the cover glass and the support member may protrude in the direction faced by the first surface, compared to the surface of the side member.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Embodiments herein disclose methods and systems for performing lower layer triggered mobility in NR. Embodiments herein disclose methods and systems for enabling the gNB to communicate the reference configuration to a UE, wherein the received reference configuration can be used for the LTM to the UE. Embodiments herein disclose methods and systems for enabling the gNB to communicate to the UE to apply full configuration for LTM during LTM. Embodiments herein disclose actions to be performed by the UE for full configuration for LTM. Embodiments herein disclose actions to be performed by the UE for addition/modification/release of LTM reference configuration. Embodiments herein disclose methods and systems for performing internode communication between gNB and DU for LTM.
Disclosed is a storage device which includes a plurality of nonvolatile memory devices, and a storage controller that selects one of the plurality of nonvolatile memory devices by controlling a plurality of chip enable signals to be transferred to the plurality of nonvolatile memory devices. The storage controller uses one of the plurality of chip enable signals as a reduced chip enable signal and remaining chip enable signals as chip enable address signals. The storage controller selects one of the plurality of nonvolatile memory devices by activating the reduced chip enable signal and controlling the chip enable address signals. The storage controller generates each of the chip enable address signals by using one of at least three voltage levels.
Samsung Electronics Company, Ltd. (Republic of Korea)
Inventor
Paul, Amrit
Abstract
In one embodiment, a method includes accessing an image depicting a scene from a first sensor, constructing a semantic segmentation of the image including image segments for the scene based on the image, generating neural radiance fields based on the image segments, learning a graph neural network based on the neural radiance fields, constructing graph motifs based on sub-graphs associated with the graph neural network, wherein each graph motif functions as a graph-rule learner, generating a pre-trained digital twin based on the image segments and the graph-rule learners, generating semantic graph radiance fields based on sensor data from second sensors, the pre-trained digital twin, and the graph neural network, and generating a domain-specific digital twin based on the semantic graph radiance fields.
A method and a device are provided in which a request for positioning assistance is received from a UE in a dedicated field of sidelink (SL) control information (SCI). A request for assistance in selecting resources for SL-positioning reference signal (PRS) transmission is transmitted to the UE. A set of one or more preferred or non-preferred resources for SL-PRS transmission is received from the UE. Resources for the SL-PRS transmission are selected based on at least the set of one or more preferred or non-preferred resources.
An error correction code (ECC) engine includes an ECC decoder configured to correct Q symbol errors in a codeword read from a memory cell array, Q being a maximum natural number equal to or less than P/2, P being a natural number equal to or greater than four; the ECC decoder being configured to: generate a syndrome including first through P-th syndrome symbols based on the read codeword by using a parity check matrix; and perform a first ECC decoding to correct a single symbol error in the read codeword based on the first syndrome symbol and a selected syndrome symbol corresponding to one of the second through P-th syndrome symbols and by using a ratio of the selected syndrome symbol to the first syndrome symbol.
The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). Embodiments herein provide a method and device for handling security for concatenated packets in telecommunication network. The method includes receiving by a transmitter device (130) a plurality of SDU packets (502-508) from a higher layer to a Layer (L2) of the transmitter device (130). The same SN assigned to each SDU packets of the plurality of SDU packets (502-508) to form a single PDU packet (520c) and generating a first label unique security signature (510-516) based on the assigned SN number. Further, encrypting, each SDU packet of the plurality of SDU packets (502-508) with the first label unique security signature (510-516), except for the L2 packet header (518). The receiver device deciphers the received each SDU packets of the plurality of SDU packets (502-508) irrespective of missing segments or received in out of order.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
H04L 69/321 - Interlayer communication protocols or service data unit [SDU] definitionsInterfaces between layers
H04L 69/324 - Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
H04W 12/033 - Protecting confidentiality, e.g. by encryption of the user plane, e.g. user’s traffic
A grinding apparatus includes a grinding unit configured to grind a molding resin layer of a workpiece, a measurement unit configured to measure a thickness of the molding resin layer, and a controller. The controller is configured to control the measurement unit to measure the thickness of the molding resin layer, obtain thickness information of the molding resin layer from the measurement unit, determine at least one grinding condition based on the thickness information of the molding resin layer, and control the grinding unit to perform a grinding process on the workpiece, the grinding process corresponding to the at least one grinding condition. The workpiece includes a substrate and the molding resin layer on the substrate, and the molding resin layer is colored or opaque.
A method includes receiving, from an energy information function (EIF), group energy target information for one or more application energy groups, wherein each of the one or more application energy groups includes a plurality of applications executed by a UE, and determining, based at least in part on the group energy target information and configuration information associated with the plurality of applications, a per-application energy target for the plurality of applications, and enforcing the per-application energy target by configuring the plurality of applications to control their energy consumption not to exceed the per-application energy target. The method also includes obtaining application energy index reports from the plurality of applications, deriving, based on the application energy index reports, application group energy index information for the one or more application energy groups, and reporting the application group energy index information for the one or more application energy groups to the EIF.
A semiconductor memory device includes a first conductive line, a first bitline spaced apart from the first conductive line in a first direction, a second bitline spaced apart from the first conductive line in the first direction, a first wordline disposed between the first conductive line and each of the first bitline and the second bitline, a first channel pattern including a horizontal portion and disposed between the first wordline and the first conductive line and a first vertical portion, the horizontal portion of the first channel pattern being connected to the first conductive line, and the first vertical portion of the first channel pattern being connected to the first bitline, and a second channel pattern disposed between the first channel pattern and the first wordline and connected to the second bitline.
A battery protection member and an electronic device including the same are provided. The electronic device includes a battery and a battery protection member, wherein the battery protection member includes a plurality of porous membrane layers including pores and stacked one on another, a non-Newtonian fluid immersed in the porous membrane layers, and a pouch surrounding an exterior of the plurality of porous membrane layers.
H01M 50/242 - MountingsSecondary casings or framesRacks, modules or packsSuspension devicesShock absorbersTransport or carrying devicesHolders characterised by physical properties of casings or racks, e.g. dimensions adapted for protecting batteries against vibrations, collision impact or swelling
H01M 10/04 - Construction or manufacture in general
H01M 10/653 - Means for temperature control structurally associated with the cells characterised by electrically insulating or thermally conductive materials
H01M 10/6551 - Surfaces specially adapted for heat dissipation or radiation, e.g. fins or coatings
H01M 50/184 - Sealing members characterised by their shape or structure
H01M 50/46 - Separators, membranes or diaphragms characterised by their combination with electrodes
An electronic device may include a housing, a flexible display, a support plate or a cover member. The housing can include a first housing or a second housing. The second housing can be disposed to be rotatable with respect to the first housing. The flexible display can be disposed on the housing. The support plate can be disposed between the housing and the flexible display. The support plate can be formed to support the flexible display. The cover member can cover at least a portion of the edge of the flexible display. The cover member can be coupled to the support plate.
A method for manufacturing a semiconductor device includes forming a stacked structure by alternately stacking a plurality of sacrificial layers and a plurality of channel layers on a substrate, forming an active region by partially removing the stacked structure and the substrate, forming a sacrificial gate structure to traverse the active region on the substrate and gate spacer layers on sidewalls of the sacrificial gate structure, forming a recess region by partially removing the stacked structure exposed from the sacrificial gate structure, forming a source/drain region in the recess region, forming an interlayer insulating layer covering the source/drain region, removing the sacrificial gate structure, removing the plurality of sacrificial layers, and forming a gate structure including a gate electrode layer in regions in which the sacrificial gate structure and the plurality of sacrificial layers are removed.
A semiconductor device includes a cell array substrate and a peripheral circuit substrate on the cell array substrate. The cell array substrate includes a memory cell region and a pad region, active patterns extending in a first horizontal direction on the memory cell region and spaced apart from each other in a vertical direction, bit lines contacting the active patterns and extending in the vertical direction, gate electrodes extending in a second horizontal direction, conductive connection lines electrically connected to the bit lines, and pad portions connected to the gate electrodes and on the pad region. The memory cell region includes a first sub-cell region, a second sub-cell region and a third sub-cell region sequentially arranged in the first horizontal direction. The bit lines include a first bit line, a second bit line, a third bit line, and a fourth bit line.
An electronic device may identify, based on a content image input thereto, one or more objects through each of a first artificial intelligence (AI) model and a second AI model, and when the identified objects do not correspond to each other, transmit, to a server, the content image and information corresponding to the identified one or more objects.
A storage device includes a memory device that stores a vector database including a plurality of vector data and index information, and a storage controller that controls the memory device. The storage controller receives a query request including a start node identifier from a host device, performs beam search on the start node identifier based on the index information in response to the received query request, and transmits a response including at least one neighbor node identifier corresponding to the start node identifier to the host device.
Seoul National University R&DB Foundation (Republic of Korea)
Inventor
Lee, Noho
Hwang, Yunjeong
Choi, Juhyung
Kim, Jaeeun
Cho, Kanghee
Kwon, Hyukjae
Kim, Dayeon
Park, Sejin
Abstract
A carbon oxide reduction electrode (CORE), a carbon oxide electrolyzer cell including the CORE, and a method of preparing a CORE. The CORE includes a gas diffusion layer (GDL) including a microporous substrate (MPS) that includes conductive fibers, and a microporous catalyst layer (MPCL) on the GDL, wherein the MPCL includes conductive particles and catalyst particles and has a thickness of 10 micrometers or more.
C25B 11/075 - Electrodes formed of electrocatalysts on a substrate or carrier characterised by the electrocatalysts material consisting of a single catalytic element or catalytic compound
C25B 11/052 - Electrodes comprising one or more electrocatalytic coatings on a substrate
C25B 11/056 - Electrodes formed of electrocatalysts on a substrate or carrier characterised by the substrate or carrier material consisting of textile or non-woven fabric
A method for manufacturing a semiconductor device includes: forming, on an upper surface of a lower structure, a dielectric layer, a first hard mask on the dielectric layer, and a first patterning layer on the first hard mask; forming a non-mandrel region and a mandrel pattern; forming a pattern block layer on the preliminary spacer layer; forming a spacer layer by etching the preliminary spacer layer; forming a second hard mask covering the spacer layer, the pattern block layer, the non-mandrel region and the mandrel pattern; forming a second patterning layer on the second hard mask; removing the second patterning layer and the second hard mask; patterning the first hard mask; patterning the dielectric layer by etching the dielectric layer; and forming a plurality of first patterns in a plurality of first trenches and a plurality of second patterns in a plurality of second trenches.
An electronic device is provided. The electronic device includes a touch-sensitive display, at least one processor, and memory configured to store a first application, a second application, and instructions. The instructions, when executed by the at least one processor individually or collectively, cause the electronic device to receive, via the touch-sensitive display, a first user input requesting to share first content provided by the first application, display, via the touch-sensitive display, a user interface (UI) supporting interaction with a user in connection with regeneration of the first content, receive a second user input via the touch-sensitive display through the UI, obtain second content generated by processing the first content, based on the second user input, and configure the second content to be usable by the second application.
G06F 3/0484 - Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
G06F 3/0482 - Interaction with lists of selectable items, e.g. menus
G06F 3/04886 - Interaction techniques based on graphical user interfaces [GUI] using specific features provided by the input device, e.g. functions controlled by the rotation of a mouse with dual sensing arrangements, or of the nature of the input device, e.g. tap gestures based on pressure sensed by a digitiser using a touch-screen or digitiser, e.g. input of commands through traced gestures by partitioning the display area of the touch-screen or the surface of the digitising tablet into independently controllable areas, e.g. virtual keyboards or menus
48.
METHOD AND APPARATUS FOR PLMN SELECTION IN WIRELESS COMMUNICATION SYSTEM
Embodiments herein disclose a method for handling a PLMN selection in a wireless network by a UE. The method includes receiving, by a user equipment (UE), slice-based PLMN selection information from a network entity of a home public land mobile network (HPLMN), and selecting, by the UE, a visited public land mobile network (VPLMN) among a plurality of PLMNs based on a priority order defined in the slice-based PLMN selection information.
A communication device includes a first tuning network including a first antenna and a first antenna tuner configured to adjust an impedance according to a received tune code, a first processor configured to identify a first reflection coefficient based on a first forward signal and a first reverse signal, the first forward signal being transmitted to the first antenna through the first antenna tuner, the first reverse signal being received through the first antenna tuner as at least a portion of the first forward signal is reflected, and a second processor configured to execute a machine learning model trained based on a plurality of training reflection coefficients and a plurality of training events, the first processor being configured to provide the first reflection coefficient to the second processor, and identify a first event corresponding to the first reflection coefficient based on an output of the machine learning model provided.
H04B 17/11 - MonitoringTesting of transmitters for calibration
H01Q 5/335 - Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors at the feed, e.g. for impedance matching
H04B 17/21 - MonitoringTesting of receivers for calibrationMonitoringTesting of receivers for correcting measurements
An image sensor includes a substrate having a first surface on which light is incident and a second surface opposite to the first surface; a pixel isolation structure surrounding a pixel region in the substrate; a photoelectric conversion region in the pixel region; a first device isolation layer disposed in a first shallow trench recessed from the second surface to a first depth in a vertical direction, and spaced apart from the pixel isolation structure by a first distance; and a second device isolation layer disposed in a second shallow trench recessed from the second surface to a second depth in the vertical direction, and spaced apart from the pixel isolation structure by a second distance. The first depth of the first shallow trench is different from the second depth of the second shallow trench.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
Provided is a semiconductor package including a substrate having a first surface, a second surface, and a side surface between the first surface and the second surface, the substrate including an insulating layer and a conductive layer in the insulating layer, a plurality of semiconductor chips on the first surface of the substrate and electrically connected to each other through the conductive layer, a mold on the first surface of the substrate, the side surface of the substrate, and at least a portion of each semiconductor chip of the plurality of semiconductor chips, and a connection bump on the second surface of the substrate and electrically connected to the conductive layer, wherein the conductive layer includes a first metal, and wherein an elastic modulus of the conductive layer is smaller than a first elastic modulus of the first metal.
RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY (Republic of Korea)
Inventor
Kwon, Youngchun
Kang, Seokho
Jung, Yongsik
Abstract
A method of predicting yield may include receiving input data including a product and reaction factors, obtaining reaction factor embedding vectors via an encoder based on the reactor factors, obtaining a product embedding vector via the encoder based on the product, obtaining a reaction embedding vector corresponding to an entire reaction via a projection layer based on the reaction factor embedding vectors and the product embedding vector, predicting a contribution of each of the reaction factors based on the reaction embedding vector and the reaction factor embedding vectors, and predicting yield of the entire reaction based on the contribution of each of the reaction factors.
The present disclosure relates to a method and a device, and the method performed by a terminal in a wireless communication system comprises the steps of receiving assistance data from a position server by using a positioning protocol defined between the terminal and the position server; receiving a downlink (DL) positioning reference signal (PRS) from a base station via a repeater; receiving a request for a position of the terminal from the position server; acquiring a measurement value related to the position of the terminal on the basis of the DL PRS; and transmitting the measurement value or position information of the terminal to the position server, wherein the position information is based on the assistance data and the measurement value, and the assistance data includes configuration information of the DL PRS, repeater timing error group (TEG) information for a delay occurring inside a repeater, base station TEG information for a delay occurring inside the base station, and propagation delay information on a delay occurring between the base station and the repeater.
An antenna module includes an antenna substrate formed of a dielectric, the antenna substrate including a first area where a plurality of antenna elements is disposed, a printed circuit board (PCB) including a first surface where a filter is disposed, and a connector disposed on a second area of the antenna substrate, the second area being different from the first area, the connector penetrating the second area of the antenna substrate between the PCB and the antenna substrate, wherein the connector includes a conductive portion connecting the plurality of antenna elements and the PCB, the conductive portion being configured to provide a signal to the plurality of antenna elements, and an elastic portion surrounding the conductive portion, and wherein the conductive portion is contacted to a second surface of the PCB, the second surface being opposite to the first surface.
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including a channel region and a source/drain region contacting the channel region, a power rail that is configured be electrically connected to a power source and is spaced apart from the source/drain region in a first direction, and a power contact that is between the source/drain region and the power rail and contacts both the source/drain region and the power rail. The channel region may overlap the power contact in the first direction.
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
The present disclosure relates to an electronic device. The electronic device according to an embodiment of the present disclosure may comprise: a first housing; a second housing; a hinge structure configured such that the first housing and the second housing are connected, and such that the first housing and the second housing are rotated; a flexible display disposed on the first housing and the second housing; a speaker disposed on the first housing; a first sound output path configured to be opened if the first housing and the second housing reach an unfolded state, the first sound output path comprising a first speaker hole configured to be covered at least partially if the first housing and the second housing reach a folded state; and a second sound output path configured to be opened if the first housing and the second housing reach a folded state, the second sound output path comprising a second speaker hole configured to be covered at least partially if the first housing and the second housing reach the unfolded state. The second speaker hole may be disposed in the first housing.
A method for operating a first electronic device supporting ultra-wideband (UWB) communication according to an embodiment of the present disclosure may comprise the steps of: receiving a Bluetooth low energy (BLE) advertisement message including an identifier of the first electronic device from a second electronic device; on the basis of the BLE advertisement message, identifying that there is service information displayed on the second electronic device and provided from a third electronic device to the first electronic device; and transmitting a service request message for the service information to the second electronic device.
H04W 4/80 - Services using short range communication, e.g. near-field communication [NFC], radio-frequency identification [RFID] or low energy communication
58.
SYSTEMS AND METHODS FOR A CACHE-COHERENT INTERCONNECT PROTOCOL STORAGE DEVICE
A device is disclosed. An interface may connect the device to a processor. The interface may support a first protocol. A first storage and a second storage may the data. The second storage may support a second protocol different from the first protocol. A controller may be connected to the interface and the first storage. A bridge may be connected to the interface, the first storage, and the second storage. The bridge may include a filter configured to coordinate a data transfer between the first storage and the second storage.
An electronic device may assist an audio sink device. The electronic device may include: a memory that stores instructions; a display; communication circuitry for BLE; and a processor. The instructions, when executed by the processor, may cause the electronic device to: perform a first scan for an extended advertisement around the electronic device using the communication circuitry; receive an advertised packet via the extended advertisement of an external electronic device; display, on the display, a device list including a visual object representing the external electronic device as a candidate audio source device; and synchronize with a periodic advertisement of the external electronic device according to a second scan for the periodic advertisement caused around the electronic device.
H04N 21/43 - Processing of content or additional data, e.g. demultiplexing additional data from a digital video streamElementary client operations, e.g. monitoring of home network or synchronizing decoder's clockClient middleware
An image sensor includes a plurality of pixels, where each of the plurality of pixels includes a plurality of photodiodes, a plurality of transfer transistors, a floating diffusion region sharing the plurality of photodiodes and the plurality of transfer transistors, a dual conversion gain transistor connected to the floating diffusion region, and a capacitor connected to one end of the dual conversion gain transistor, where the capacitor includes a first insulator, the dual conversion gain transistor includes a second insulator, and in a first direction, a first thickness of the first insulator of the capacitor is different from a second thickness of the second insulator of the dual conversion gain transistor.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
Secure provisioning of wireless channels includes discovery and provisioning, discovery comprising: first device: receiving first presence signal; second device: receiving second presence signal; generating asymmetric public-private key pair; scanning channels by transmitting request to be provisioned signal including generated public key to receive ready to provision signal; if ready to provision signal was received over exactly one of scanned channels, identifying that channel as the channel; first device: receiving request to be provisioned signal at least once; if request to be provisioned signal was received with exactly one public key, proceeding to provisioning; provisioning comprising: one of second device or first device: allocating secure link with other of second device or first device based on public key; other of second device or first device: allocating secure link from one of second device or first device based on public key; and provisioning one of second device or first device.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
62.
SEMICONDUCTOR PACKAGE INCLUDING INTERPOSORS AND ELECTRONIC SYSTEM
A semiconductor package including a package substrate, an interposer structure on the package substrate, a first semiconductor chip structure on the interposer structure; and a stack chip structure on the interposer structure, the interposer structure includes a first interposer on the package substrate and including first signal paths, and a second interposer on the package substrate, spaced apart from the first interposer, and including second signal paths, the stack chip structure includes a lower chip, and second semiconductor chips vertically stacked on the lower chip, the stack chip structure is electrically connected to the first semiconductor chip structure through the first signal paths and electrically connected to the first semiconductor chip structure through the second signal paths, and a number of the first signal paths is different from a number of the second signal paths.
A semiconductor chip and a method of manufacturing a semiconductor chip are provided. The semiconductor chip may include a chip substrate, a pattern on an upper surface of the chip substrate, a scribe lane on the upper surface of the chip substrate and surrounding the pattern, and a chip redistribution layer in the pattern, the chip redistribution layer extending from the pattern into the scribe lane, passing through the scribe lane, and exposed to an outside of the scribe lane. According to an example embodiment of the present disclosure, because the chip redistribution layer is exposed to the outside of the scribe lane and an outer side surface of the scribe lane is coplanar with a side surface of the chip substrate, electrical connection between the semiconductor chip and an external device can be implemented at a side surface of the semiconductor chip.
A data storage structure may include a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer. The dielectric layer may include a metal compound having a crystalline phase and including a first metal. The dielectric layer also may include a phase control material located in an interfacial region of the dielectric layer, adjacent to the upper electrode. The phase control material may include at least one of a second metal and a metal nitride. The second metal may be configured to induce a phase change in the metal compound of the dielectric layer. The metal nitride may include the second metal.
A method and apparatus are disclosed. The method comprises storing data representing a large language model (LLM) in a storage medium; receiving a quality of service (QoS) requirement specified by a user, wherein the QoS requirement includes a value representing at least one of a desired accuracy and a desired compression ratio; selecting a compression algorithm based on the QoS requirement, wherein the compression algorithm is chosen to balance the at least one of the desired accuracy and the desired compression ratio; and compressing the data representing the LLM using the selected compression algorithm.
SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Republic of Korea)
Inventor
Jeong, Jungi
Oh, Jungsuek
Bang, Seungwoo
Kim, Jaehoon
Oh, Junhwa
Abstract
The disclosure relates to a 5th generation (5G) or 6th generation (6G) communication system for supporting a higher data transmission rate. A patch antenna includes a first radiator, a second radiator disposed to face the first radiator at a predetermined distance in an −X-axis direction with respect to a Y-axis, a first transmission line electrically connecting the first radiator and the second radiator, and a first radio-frequency (RF) choke electrically connected to the first radiator.
H01Q 5/335 - Individual or coupled radiating elements, each element being fed in an unspecified way using frequency dependent circuits or components, e.g. trap circuits or capacitors at the feed, e.g. for impedance matching
67.
DIGITAL PIXEL SENSOR AND METHOD INCLUDING THE SAME
A digital pixel includes at least one photodetection circuit that receives a light signal and outputs an analog signal corresponding to the light signal, an analog-digital conversion circuit that converts the analog signal into digital data and outputs the digital data, and a plurality of memory banks that store the digital data and output the digital data. Each of the plurality of memory banks includes a pre-charge circuit that controls voltage levels of a first output line and a second output line connected to each of the plurality of memory banks based on a pre-charge enable signal.
H04N 25/771 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
H04N 25/772 - Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
H04N 25/79 - Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
68.
REFRIGERATOR CAPABLE OF PREVENTING DEW CONDENSATION AND METHOD THEREFOR
A refrigerator including: a main body having a storage chamber, two doors rotatably connected to the main body and each configured to open or close the storage chamber, a rotation bar disposed on at least one of the two doors and configured to seal a space between the two doors when the two doors close the storage chamber, and a top cover disposed on an upper portion of the main body, wherein the top cover comprises: a suction port configured to allow communication between an inner space of the top cover and an outside of the top cover, and a fan configured to suction external air through the suction port and discharge the external air toward the rotation bar.
A semiconductor device includes a 1st multi-stack transistor and a 2nd multi-stack transistor arranged in a 1st direction intersecting a 2nd direction, wherein the 1st multi-stack transistor includes a 1st lower transistor and a 1st upper transistor above the 1st lower transistor in a 3rd direction that intersects the 1st direction and the 2nd direction, wherein the 2nd multi-stack transistor structure includes a 2nd lower transistor and a 2nd upper transistor above the 2nd lower transistor in the 3rd direction, and wherein the 1st lower transistor and the 2nd lower transistor have different numbers of effective lower channel layers.
A semiconductor light emitting device may include a first LED cell including a first semiconductor layer of a first conductivity-type, a first active layer, and a second semiconductor layer of a second conductivity-type; a second LED cell including a third semiconductor layer of the first conductivity-type, a second active layer emitting light of a different wavelength from the first active layer, and a fourth semiconductor layer of the second conductivity-type; a third LED cell including a fifth semiconductor layer of the first conductivity-type, a third active layer emitting light of a different wavelength from the first and second active layers, and a sixth semiconductor layer of the second conductivity-type; a first passivation layer on a side surface of the first LED cell; and a second passivation layer on a side surface of the second LED cell and including a different material from a material of the first passivation layer.
H10H 29/14 - Integrated devices comprising at least one light-emitting semiconductor component covered by group comprising multiple light-emitting semiconductor components
71.
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A method of fabricating a semiconductor package includes forming a first wiring structure that includes a first insulating layer and a first wiring pad inside the first insulating layer, forming a first semiconductor chip on the first wiring structure, forming a second wiring structure on the first semiconductor chip, and forming a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer, and the second insulating layer and the plurality of second wiring pads each directly contact one surface of the first semiconductor chip
An electronic device is disclosed. The electronic device can: select an object from among one or more objects included in an input image; identify indication information about a state change of the selected object; and obtain, on the basis of the indication information, a prompt related to the input image. The prompt can include one or more words for changing the state of the selected object included in the input image. The state can be included in different states of the selected object. The electronic device inputs the input image and the prompt into a generative artificial intelligence model, and thus can generate one or more result images in which the state of the selected object has been changed.
The present disclosure relates to a method and an apparatus enabling delay time in an inter-system handover procedure to be reduced. A method performed by means of a first network entity for managing mobility in a first system in an inter-system handover procedure, according to an embodiment of the present disclosure, comprises the steps of: selecting, with respect to a specific service for a terminal, a target cell from among one or more candidate cells for inter-system handover from the first system to a second system; transmitting, to a second network entity for managing mobility in the second system, a first request message including type information about a random access procedure to be performed by the target cell; receiving, in response to the transmission of the first request message, a first response message including configuration information related to the inter-system handover from the second network entity; and transmitting a handover command together with the configuration information related to the inter-system handover to a base station of the first system accessed by the terminal.
A substrate cleaning method may include preparing a substrate having an upper surface opposite a lower surface, contacting a first roll member and a second roll member to the lower surface and the upper surface of the substrate, respectively, and scrub cleaning the lower surface of the substrate and the upper surface of the substrate by rotating the first roll member and the second roll member. The first roll member and the second roll member each may include a copolymer of a first water-soluble polymer and a second water-soluble polymer. The first water-soluble polymer may include a non-ionic polymer, and the second water-soluble polymer may include a cationic polymer.
A multi-foldable electronic device is provided. The multi-foldable electronic device includes a first housing including a first magnet assembly movable to a first position and a second position, a second housing foldably coupled to a first side of the first housing and including a second magnet assembly, a third housing foldably coupled to a second side of the first housing, a first hinge structure coupled between the first housing and the second housing, and a second hinge structure coupled between the first housing and the third housing, wherein when the angle between the first housing and the third housing is a first angle, the first magnet assembly is disposed at the first position, and when the angle between the first housing and the third housing is a second angle, the first magnet assembly moves to the second position, and the first magnet assembly and the second magnet assembly are disposed to face each other so as to have a substantially same polarity.
An operating method of a storage device that includes a non-volatile memory, a cache memory and a storage controller and is connected to an external storage device through a switch, includes: receiving, from an external host, a first request including a source address related to the external storage device, a destination address related to the storage device, and cache update information indicating an update method of the cache memory; providing a second request including the source address to the external storage device; receiving, from the external storage device, a first response including first data corresponding to the source address; generating a first physical address of a first type indicating a cache area; generating a second physical address of a second type indicating a storage area; storing the first data to the storage area; and updating the cache area indicated by the first physical address.
A method performed by an electronic device is provided. The method includes receiving, through a distance detection sensor, second signals in which a first signal transmitted through the distance detection sensor is reflected by an external object, identifying a distance from the external object based on at least a part of the second signals, obtaining a deviation information value for the second signals based on identifying that the distance is less than a reference distance, obtaining an image including a visual object corresponding to the external object through a first camera based on the deviation information value being greater than or equal to a reference value, and obtaining the image including the visual object corresponding to the external object through a second camera according to a camera switching, based on the deviation information value being less than the reference value.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method performed by a user equipment (UE) is provided. The method includes receiving, from a base station, configuration information for a cell discontinuous reception (DRX), identifying whether the cell DRX is activated and a serving cell is not in an active reception period of the cell DRX based on the configuration information, and in case that the cell DRX is activated and the serving cell is not in the active reception period of the cell DRX, determining not to transmit a scheduling request (SR).
Disclosed is a method for UWB multiplexing transmission. A method performed by a first UWB device according to an embodiment disclosed herein may comprise the steps of: transmitting a ranging control message for UWB multiplexing transmission, the ranging control message being transmitted in a first slot within a ranging round through UWB or NB; transmitting a triggering packet for triggering the UWB multiplexing transmission, the triggering packet being transmitted in a second slot within the ranging round through the UWB or NB; receiving, through the UWB, a first packet transmitted in a third slot within the ranging round by the second UWB device on the basis of the ranging control message; and receiving, through the UWB, a second packet transmitted in a third slot within the ranging round by a third UWB device on the basis of the ranging control message.
Disclosed is a method for operating a UWB channel together with an NB channel. A method performed by a first UWB device disclosed herein comprises the steps of: generating an NB AP for providing information about a first UWB session used by a first UWB device; and broadcasting the NB AP through the NB channel. The NB AP may be used by a second UWB device to configure a second UWB session.
A method of operating a user equipment (UE) includes receiving one or more random access (RA) resource configurations. Each RA resource configuration is associated with one or more (x, y) values corresponding to a sounding reference signal (SRS) antenna switching capability TxRy of the UE. The method also includes initiating one of a four-step or two-step RA procedure, during the RA procedure, transmitting a Message 1 (Msg1) or Message A (MsgA) indicating the one or more (x, y) values corresponding to the SRS antenna switching capability TxRy of the UE, and transmitting an SRS according to an SRS resource configuration for an (x, y) value indicated in the Msg1 or MsgA.
A wearable electronic device is provided. The wearable electronic device includes a housing including a rear plate, a first circuit board disposed inside the housing, a biometric sensor disposed on the rear plate and including a second circuit board, a wireless charger disposed on the rear plate and placed to surround at least part of the biometric sensor, a connector configured to connect the first circuit board and the second circuit board and including a plurality of terminals, a switch circuit configured to connect either the biometric sensor or the wireless charger to the connector, memory, comprising one or more storage media, storing instructions, at least one processor disposed on the first circuit board and electrically connected to the connector, the biometric sensor, and the wireless charger.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. Embodiments herein is to provide method for congestion handling while packet discarding for extended reality. UE (101) transmits UE capability message to network apparatus (201) for indicating support of PSI based SDU discard. Further, UE (101) receives signaling message from network apparatus (201) to be configured with discard information for congestion handling. Also, UE (101) receive SDU or PDU of PDU Set associated with PSI value from upper layer. Further, UE start first discard timer for low importance or second discard timer based on PSI value of PDU Set, when PSI based SDU discard status of corresponding DRB is activated. Also, UE discards PDU Set when first discard timer for low importance or second discard timer expires. Further, UE starts second discard timer when PSI based SDU discard status of corresponding DRB is deactivated and discards PDU Set upon expiry of second discard timer.
An electronic device is provided. The electronic device includes an audio output module, a communication module, memory storing instructions, and at least one processor, wherein the instructions, when executed by the at least one processor individually or collectively, cause the electronic device to obtain audio data including first channel audio data and second channel audio data based on an audio output event, when an output channel for outputting the audio data is a mono channel, operate to calculate a first value corresponding to the first channel audio data and a second value corresponding to the second channel audio data, when the first value or the second value is greater than or equal to a first specified value, operate to calculate a third value corresponding to first mixed audio data obtained by mixing the first channel audio data and the second channel audio data, when the third value satisfies a first specified condition, output, through the audio output module, the first mixed audio data or transmit, through the communication module, the first mixed audio data to an external audio output device, and when the third value satisfies a second specified condition, invert a phase of the first channel audio data and output, through the audio output module, second mixed audio data obtained by mixing the phase-inverted first channel audio data and the second channel audio data or transmit, through the communication module, the second mixed audio data to an external audio output device.
The present disclosure relates to a 5G or 6G communication system for supporting a higher data transfer rate. In addition, the present disclosure relates to a method and a device for correctly reporting a network congestion situation to an application server in a wireless communication system.
An electronic device includes: a housing having a ring shape and including an outer housing part and an inner housing part, the inner housing part being coupled to the outer housing part; a circuit board disposed within the housing; at least one optical element disposed within the housing, the at least one optical element being electrically connected to the circuit board; and a plurality of protrusions arranged along an inner circumferential surface of the inner housing part, wherein the at least one optical element faces at least one protrusion of the plurality of protrusions.
An amount of a cache for storing training data in a particular form may be determined based on modeling throughput of a data storage and ingestion pipeline for training machine learning models. The machine learning models may be trained to perform a task using training data in the particular form stored in the cache. A request may be identified for a first instance of the training data in the particular form to include in a training batch. The first instance of the training data in the particular form may not be stored in the cache. A second instance of the training data in the particular form stored in the cache may be determined not to have been used to train the machine learning models. The second instance of the training data in the particular form may be included in the training batch.
An induction heating apparatus may include: first heating portions respectively including: a first coil, and a first sensor configured to detect a container at the respective first heating portion; second heating portions respectively including: a second coil, and a second sensor configured to detect the container at the respective second heating portion; an input portion configured to receive a user input including a heating level; a memory that stores a heating output corresponding to the received heating level, and a number of first and/or second heating portions occupied by the container; and a controller configured to: based on data output by the respective first and/or second sensors, determine the number of first and/or second heating portions occupied by the container, and control at least one first heating portion and/or second heating portion occupied by the container to output a heating output corresponding to the stored heating output.
The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method by a user equipment (UE) associated with a first cell group and a second cell group in a wireless communication system, the UE comprising, receiving, from a base station, a control message including a lower layer triggered mobility (LTM) configuration for performing a LTM measurement and a timer for supervising a LTM cell switch, detecting a radio link failure for the first cell group of the first cell group and the second cell group, while performing a LTM cell switch, identifying whether the timer for supervising the LTM cell switch is running on the second cell group, and transmitting, to the base station, a radio resource control (RRC) reestablishment message, in case that the timer for supervising the LTM cell switch is running on the second cell group.
An image sensor includes a substrate including a plurality of photoelectric convertors and a prism structure on the substrate. The prism structure includes a mold pattern and a plurality of refractive structures provided in the mold pattern. Each refractive structure of the plurality of refractive structures includes a first portion and a second portion on the first portion. The second portion has a first width in a first direction parallel to an upper surface of the substrate. The first width increases in a direction away from the upper surface of the substrate.
H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
Provided is a display device including a light emitting element array substrate including a plurality of light emitting elements, a color conversion structure on the light emitting element array substrate, and a bonding unit between the light emitting element array substrate and the color conversion structure, wherein the color conversion structure includes a transparent substrate, partition walls between pixel regions of a plurality of color pixels and on the transparent substrate, a color conversion layer in at least one pixel region of the pixel, the color conversion layer being configured to convert light incident on the at least one pixel region into a color corresponding to a color pixel in the at least one pixel region, a light transmissive resin layer on the color conversion layer, and a reflective layer on the light transmissive resin layer, the reflective layer including openings corresponding to each color pixel of the plurality of color pixels and configured to guide light from the light emitting elements into the partition walls.
H10H 29/24 - Assemblies of multiple devices comprising at least one light-emitting semiconductor device covered by group comprising multiple light-emitting semiconductor devices
A non-volatile memory device may include: a memory cell region including at least one memory cell array and upper bonding pads, wherein the at least one memory cell array including: a plurality of sub-planes disposed in a first direction; and a plurality of common source plates respectively electrically connected to the plurality of sub-planes; and a peripheral circuit region including: lower bonding pads, the peripheral circuit region being electrically connected to the memory cell region in a vertical direction by the upper bonding pads and the lower bonding pads; and a plurality of common source line drivers respectively electrically connected to the plurality of common source plates, and configured to independently drive the plurality of common source plates.
Provided is a semiconductor device which may include: a 1st channel structure; a 1st source/drain region on the 1st channel structure, the 1st source/drain region and the 1st channel structure connected in a 1st direction; a gate structure on the 1st channel structure; and a 1st gate-etch structure on the 1st channel structure, the 1st gate-etch structure comprising an insulation material, wherein the 1st gate-etch structure is connected to the 1st channel structure in a 2nd direction intersecting the 1st direction, and wherein the 1st gate-etch structure does not extend beyond a length of the 1st channel structure in the 1st direction along a side surface of the 1st source/drain region extending in the 1st direction.
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
H01L 23/528 - Layout of the interconnection structure
H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
An embodiment of the present inventive concept provides a semiconductor device. The semiconductor device comprises: lower channel layers; upper channel layers; gate structures; a first source/drain pattern and a second source/drain pattern, wherein the lower channel layers are disposed between the first source/drain pattern and the second source/drain pattern; a third source/drain pattern and a fourth source/drain pattern, wherein the upper channel layers are disposed between the third source/drain pattern and the fourth source/drain pattern; an upper contact structure; a lower contact structure; and a through-contact structure electrically connecting the second source/drain pattern and the fourth source/drain pattern, wherein the gate structures comprise a first gate structure, a second gate structure and a third gate structure, and a first gap between the second gate structure and the third gate structure is greater than a second gap between the first gate structure and the second gate structure.
An outdoor unit of the air conditioner includes a housing including a base, a refrigerant pipe through which a refrigerant flows, a water pipe through which water flows, a plate heat exchanger disposed inside the housing to exchange heat between water flowing along the water pipe and the refrigerant flowing along the refrigerant pipe, an expansion tank disposed inside the housing connected to the water pipe and configured to regulate a pressure in the water pipe, a control box disposed inside the housing and configured to accommodate a printed circuit board, a first bracket fixing the plate heat exchanger to the base, a second bracket fixing the expansion tank to the base and be fastened to the first bracket, and a third bracket supporting the control box and fastened to an upper surface of the second bracket.
This electronic device may comprise: memory for storing instructions; and at least one processor including processing circuitry. The instructions, when executed individually or collectively by the at least one processor, may control the electronic device to: receive a trigger signal for message synchronization from a server on the basis of the occurrence of at least one event among registration of an auxiliary device, performance of message restoration, or a synchronization request of a user; on the basis of the trigger signal, determine a period of messages to be synchronized among messages stored in the electronic device; upload messages corresponding to the determined period to the server; periodically update state information of the auxiliary device by transmitting state information indicating the upload progress state of the messages to the server; and perform message synchronization again on the basis of receiving a new trigger signal from the server.
H04L 69/04 - Protocols for data compression, e.g. ROHC
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
The present disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. This method performed by a first network entity in a wireless communication system may comprise the steps of: acquiring information related to network sharing activation; determining, on the basis of the information, whether to execute the network sharing activation; identifying a second network entity capable of providing network sharing; and transmitting, to the second network entity, a first message requesting provision of network sharing for a first base station related to the first network entity.
This motor comprises: a stator; a rotor shaft disposed at the center of the stator; and a rotor coupled to the rotor shaft and provided to rotate about the rotor shaft by electromagnetically interacting with the stator. The rotor includes: a plurality of rotor cores disposed to be spaced apart from each other along the circumferential direction of the rotor shaft and stacked in a direction in which the rotor shaft extends; a magnet disposed between the plurality of rotor cores; and a bridge formed in some intermediate layers of the stacked rotor cores to connect the inner diameters of the plurality of rotor cores. The upper end of the bridge is vertically spaced apart from the upper ends of the plurality of rotor cores, and the lower end of the bridge is vertically spaced apart from the lower ends of the plurality of rotor cores.
H02K 21/16 - Synchronous motors having permanent magnetsSynchronous generators having permanent magnets with stationary armatures and rotating magnets with magnets rotating within the armatures having annular armature cores with salient poles
H02K 1/276 - Magnets embedded in the magnetic core, e.g. interior permanent magnets [IPM]
H02K 1/28 - Means for mounting or fastening rotating magnetic parts on to, or to, the rotor structures
H02K 7/00 - Arrangements for handling mechanical energy structurally associated with dynamo-electric machines, e.g. structural association with mechanical driving motors or auxiliary dynamo-electric machines
99.
METHOD AND APPARATUS FOR CHANNEL NOISE REDUCTION AND SHAPING IN A WIRELESS COMMUNICATION SYSTEM
The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). The present application relates to a method performed by an electronic apparatus and an electronic apparatus, the method including: determining first channel state information; partitioning the first channel state information into a plurality of pieces of information in a frequency domain according to at least one partition scale; obtaining second channel state information by performing noise reduction and/or shaping through a neural network based on the plurality of pieces of information; and performing channel estimation based on the second channel state information, wherein if a number of resource blocks of the first channel state information is less than a first predetermined threshold, the first channel state information is partitioned into the plurality of pieces of information in the frequency domain according to a first partition scale, and if the number of the resource blocks of the first channel state information is greater than or equal to the first predetermined threshold, the first channel state information is partitioned into the plurality of pieces of information in the frequency domain according to a second partition scale, wherein the second partition scale is greater than the first partition scale.
H04B 7/06 - Diversity systemsMulti-antenna systems, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas at the transmitting station
A method performed by an electronic device according to an embodiment may comprise the operations of: acquiring data regarding a designated terminal operation according to an abnormal operation type with respect to a target terminal to be checked as to whether same performs an abnormal operation; acquiring output data by applying the data regarding the designated terminal operation of the target terminal to an autoencoder-based artificial intelligence model; and determining whether the target terminal performs an abnormal operation on the basis of whether a reconstruction loss of the output data exceeds a designated reconstruction range.
