Abstract

A semiconductor device with air spacers and air caps and a method of fabricating the same are disclosed. The semiconductor device includes a substrate and a fin structure disposed on the substrate. The fin structure includes a first fin portion and a second fin portion. The semiconductor device further includes a source/drain (S/D) region disposed on the first fin portion, a contact structure disposed on the S/D region, a gate structure disposed on the second fin portion, an air spacer disposed between a sidewall of the gate structure and the contact structure, a cap seal disposed on the gate structure, and an air cap disposed between a top surface of the gate structure and the cap seal.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 30/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 64/01 - Manufacture or treatment

Abstract

The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.

IPC Classes  ?

• H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Abstract

A method of manufacturing an IC device includes performing a leakage test by adding a circuit element to a schematic net of a netlist of the IC device, based on the leakage test, assigning a leakage current constraint to the schematic net, determining a violation of the leakage current constraint based on a dummy gate region adjacent to the schematic net in an IC layout diagram of the IC device, in response to the leakage current constraint violation, modifying the IC layout diagram, and storing the modified IC layout diagram in a storage device.

IPC Classes  ?

• G06F 30/30 - Circuit design
• G06F 30/20 - Design optimisation, verification or simulation
• G06F 111/12 - Symbolic schematics

Abstract

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 84/01 - Manufacture or treatment

Abstract

A method includes forming a metal post over a first redistribution structure; attaching a first device die to the first redistribution structure, the first device die comprising a through via embedded in a semiconductor substrate; encapsulating the metal post and the first device die in an encapsulant, a first top surface of the encapsulant being level with a second top surface of the semiconductor substrate; recessing the second top surface to expose the through via; forming a dielectric isolation layer around the through via; forming a dielectric layer over the dielectric isolation layer; etching the dielectric layer to form a first opening and a second opening in the dielectric layer; forming a first metal via in the first opening and a second metal via in the second opening; and forming a second redistribution structure over the dielectric layer.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

IPC Classes  ?

• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/485 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/01 - Manufacture or treatment

Abstract

Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.

IPC Classes  ?

• H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H10D 30/01 - Manufacture or treatment
• H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Abstract

An opto-electronic module provided herein includes a package substrate; an electronic component disposed on the package substrate; optical transceivers disposed on the package substrate, arranged around the electronic component, and electrically connected to the electronic component; and a first fiber array unit attached to two of the optical transceivers, wherein a width of the first fiber array unit extends across between the two of the optical transceivers.

IPC Classes  ?

• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections

Abstract

The present disclosure relates to an integrated chip including a first ferroelectric layer over a substrate. A first electrode layer is over the substrate and on a first side of the first ferroelectric layer. A second electrode layer is over the substrate and on a second side of the first ferroelectric layer, opposite the first side. A first barrier layer is between the first ferroelectric layer and the first electrode layer. A bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer.

IPC Classes  ?

• H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Abstract

A semiconductor structure includes a first channel region and a second channel region, a first gate structure over the first channel region and a second gate structure over the second channel region, first gate spacers disposed on sidewalls of the first gate structure and over the first channel region, and second gate spacers disposed on sidewalls of the second gate structure and over the second channel region. The first gate structure has a first width, and the second gate structure has a second width greater than the first width. The first gate spacers each have a third width, and the second gate spacers each have a fourth width less than the third width. The first and the second gate structure each extend lengthwise in a first direction. The first width, the second width, the third width, and the fourth width are in a second direction perpendicular to the first direction.

IPC Classes  ?

• H10B 20/25 - One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

A manufacturing method of a metal-insulator-metal (MIM) capacitor is provided, including the following steps. A conductive metal layer is formed on a substrate. A patterned dielectric layer is formed on the substrate. The patterned dielectric layer has a plurality of trenches, and the conductive metal layer is exposed at the bottom of the trenches. A MIM structure is formed above the patterned dielectric layer and in the trenches. The MIM structure includes an upper electrode layer, an insulating layer and a lower electrode layer. The insulating layer is located on the upper electrode layer and the lower electrode layer, wherein the lower electrode layer covers the sidewalls and bottoms of the trenches, and the lower electrode layer is electrically connected to the conductive metal layer.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H10D 1/68 - Capacitors having no potential barriers

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a fin structure from a substrate, the fin structure comprises a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked. The method also includes forming a sacrificial gate structure over a portion of the fin structure, removing portions of the fin structure not covered by the sacrificial gate structure, forming a conformal layer on exposed surfaces of the sacrificial gate structure, the first semiconductor layers, and the substrate. The method also includes converting portions of the conformal layer and a surface portion of the substate into dielectric regions, forming a source/drain feature on opposite sides of the sacrificial gate structure, the source/drain feature being in contact with the dielectric regions and the first semiconductor layers of the fin structure. The method further includes removing the sacrificial gate structure and the second semiconductor layers.

IPC Classes  ?

• H10D 84/01 - Manufacture or treatment
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A method for manufacturing an integrated circuit device is provided. The method includes: providing a photonic structure including an insulating structure and an optical coupler embedded in the insulating structure; and removing a portion of the insulating structure to expose a coupling surface of the optical coupler and form a light reflective structure corresponding to the coupling surface.

IPC Classes  ?

• H10F 77/40 - Optical elements or arrangements
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H10F 71/00 - Manufacture or treatment of devices covered by this subclass
• H10F 77/00 - Constructional details of devices covered by this subclass

Abstract

Various embodiments of the present disclosure are directed towards a camera module comprising flat lenses. Flat lenses have reduced thicknesses compared to other types of lenses, whereby the camera module may have a small size and camera bumps may be omitted or reduced in size on cell phones and the like incorporating the camera module. The flat lenses are configured to focus visible light into a beam of white light, split the beam into sub-beams of red, green, and blue light, and guide the sub-beams respectively to separate image sensors for red, green, and blue light. The image sensors generate images for corresponding colors and the images are combined into a full-color image. Optically splitting the beam into the sub-beams and using separate image sensors for the sub-beams allows color filters to be omitted and smaller pixel sensors. This, in turn, allows higher quality imaging.

IPC Classes  ?

• G02B 13/18 - Optical objectives specially designed for the purposes specified below with lenses having one or more non-spherical faces, e.g. for reducing geometrical aberration
• G02B 7/02 - Mountings, adjusting means, or light-tight connections, for optical elements for lenses
• G02B 27/10 - Beam splitting or combining systems

Abstract

Various embodiments of the present disclosure are directed towards a sensor device comprising a photodetector with a simplified manufacturing process. A semiconductor substrate comprises an avalanche region at which a p-type region and an n-type region form a PN junction. An inner absorption layer is recessed into the semiconductor substrate, wherein the inner absorption layer has a bottom protrusion protruding towards the avalanche region. A peripheral absorption layer is on a sidewall of the inner absorption layer and a bottom of the inner absorption layer and further extends from the sidewall to the bottom protrusion. The inner absorption layer and the peripheral absorption layer share a common semiconductor material and have a smaller bandgap than the semiconductor substrate. Further, the peripheral absorption layer has a doping concentration that is elevated relative to a doping concentration of the inner absorption layer.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A memory device is provided, including a non-volatile memory array including multiple memory cells, in which the memory cells arranged in a same row are configured to store corresponding weight data and are coupled to a same word line in multiple word lines; a word line driver configured to transmit multiple word line signals according to multiple input data signals to the word lines to perform a compute-in-memory (CIM) operation of the input data signals and the weight data stored in the non-volatile memory array; and an adder tree circuit coupled to the memory cells. Each of the memory cells in the same row is configured to generate a corresponding output voltage of the CIM operation to the adder tree circuit.

IPC Classes  ?

• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G06F 7/501 - Half or full adders, i.e. basic adder cells for one denomination
• G11C 16/30 - Power supply circuits
• G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links

Abstract

Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and is devoid of a shallow trench isolation (STI) structure at a photodetector of the pixel sensor. The photodetector and a first transistor form a first portion of the pixel sensor at a first IC chip. A plurality of second transistors forms a second portion of the pixel sensor at a second IC chip. By omitting the STI structure at the photodetector, a doped well surrounding and demarcating the pixel sensor may have a lesser width than it would otherwise have. Hence, the doped well may consume less area of the photodetector. This, in turn, allows enhanced scaling down of the pixel sensor.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

Circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.

IPC Classes  ?

• G06F 1/10 - Distribution of clock signals
• G06F 1/12 - Synchronisation of different clock signals

Abstract

The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.

IPC Classes  ?

• H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
• H01J 37/32 - Gas-filled discharge tubes
• H01L 21/311 - Etching the insulating layers
• H01L 21/3213 - Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

Abstract

The present disclosure discloses a structure and a method directed to a semiconductor structure having a resistor structure and a metal-insulator-metal (MIM) capacitor structure formed by a single mask process. The semiconductor structure includes an interconnect structure on a substrate, a first insulating layer on the interconnect structure, first and second conductive plates on the first insulating layer and separated by a second insulating layer, a dielectric layer on the first conductive plate, and a third conductive plate on the dielectric layer. Bottom surfaces of the first and second conductive plates are coplanar.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/528 - Layout of the interconnection structure
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 1/47 - Resistors having no potential barriers
• H10D 1/68 - Capacitors having no potential barriers

Abstract

A semiconductor device includes: a decoupling capacitance system configured to decouple voltage variations in a first voltage drop between a first reference voltage rail and a second reference voltage rail, the decoupling capacitance system including: a decoupling capacitance circuit; and a filtered biasing circuit, wherein an unswitched series electrical connection couples the decoupling capacitance circuit and the filtered biasing circuit between the first reference voltage rail and the second reference voltage rail.

IPC Classes  ?

• H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
• H03K 5/1252 - Suppression or limitation of noise or interference
• H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• H10D 8/00 - Diodes

Abstract

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) semiconductor structure for wide-bandgap semiconductor devices in which the wide-bandgap semiconductor devices are split amongst a first IC die and a second IC die. The first IC die includes a first substrate and a first semiconductor device. The first substrate includes a first wide-bandgap material, and the first semiconductor device overlies the first substrate and is formed in part by the first wide-bandgap material. The second IC die overlies the first IC die and is bonded to the first IC die by a bond structure between the first and second IC dies. Further, the second IC die includes a second substrate and a second semiconductor device. The second substrate includes a second wide-bandgap material, and the second semiconductor device underlies the second substrate and is formed in part by the second wide-bandgap material.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs

Abstract

The present disclosure provides a substrate bonding apparatus capable of temperature monitoring and temperature control. The substrate bonding apparatus comprises a fluid cooling module and a sensor module for detecting temperatures at multiple zones (e.g., two or more zones) within a substrate. The substrate bonding apparatus according to the present disclosure achieves temperature stabilization within the substrate. The substrate bonding apparatus further improves bonding process performance by reducing distortion residual, reducing bubbles on edges of the substrate, and reducing non-bonded area within the substrate.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• B23K 1/00 - Soldering, e.g. brazing, or unsoldering
• B81C 1/00 - Manufacture or treatment of devices or systems in or on a substrate
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/66 - Testing or measuring during manufacture or treatment
• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components

Abstract

Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H01L 21/762 - Dielectric regions
• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor structure (e.g., an integrated circuit (IC) die) comprising an enhanced cap layer for pad oxidation prevention, as well as a method for forming the IC die. An interconnect pad overlies a substrate at a top of an interconnect structure, and a bond structure overlies and extends from a surface of the interconnect pad. A cap layer and an etch stop layer overlie the surface around the bond structure. Further, the cap layer separates the etch stop layer from the interconnect pad and is soft. Soft may, for example, refer to a hardness less than silicon nitride and/or less than the etch stop layer. Because the cap layer is soft, a probe may be pushed through the cap layer to the interconnect pad for testing without first forming a pad opening exposing the interconnect pad.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a dielectric layer. The semiconductor device structure includes a barrier layer in the dielectric layer. The barrier layer is doped with manganese, the barrier layer has a central portion and a first peripheral portion, the first peripheral portion is between the dielectric layer and the central portion, and a first manganese concentration of the central portion is greater than a second manganese concentration of the first peripheral portion. The semiconductor device structure includes a conductive layer in the barrier layer.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 21/3105 - After-treatment
• H01L 21/762 - Dielectric regions
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device

Abstract

A device includes an electrical circuit. The device further includes a first conductive rail electrically connected to the electrical circuit, wherein the first conductive rail is on a first side of a substrate. The device further includes a power pillar electrically connected to the first conductive rail, the power pillar comprises a plurality of vias extending through the substrate, and adjacent vias of the plurality of vias are offset from one another in a direction parallel to a surface of the first side of the substrate.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

IPC Classes  ?

• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

IPC Classes  ?

• G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
• G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
• G11C 29/52 - Protection of memory contentsDetection of errors in memory contents

Abstract

A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 21/311 - Etching the insulating layers
• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

A method includes removing a damaged lens from a lithography tool; generating an initial profile of a new lens based on a surface profile of the damaged lens; optimizing the initial profile of the new lens by simulating an optical property of the new lens in the lithography tool to generate an optimized profile; fabricating the new lens based on the optimized profile; and mounting the new lens in the lithography tool in place of the damaged lens.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• B24B 13/06 - Machines or devices designed for grinding or polishing optical surfaces on lenses or surfaces of similar shape on other workAccessories therefor grinding of lenses, the tool or work being controlled by information carrying means, e.g. patterns, punched tapes, magnetic tapes
• G02B 5/00 - Optical elements other than lenses
• G02B 27/00 - Optical systems or apparatus not provided for by any of the groups ,
• H01J 37/305 - Electron-beam or ion-beam tubes for localised treatment of objects for casting, melting, evaporating, or etching

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first transistor and a second transistor. The first transistor includes a first plurality of nanostructures over a first lower fin element, and a first source/drain feature adjoining the first plurality of nanostructures. The second transistor includes a second plurality of nanostructures over a second lower fin element, and a second source/drain feature adjoining the second plurality of nanostructures. The semiconductor structure further includes a first dielectric isolation feature between the first source/drain feature and the first lower fin element, and a second dielectric isolation feature between the second source/drain feature and the second lower fin element. The first and second lower fin elements have a first conductivity type, the first source/drain feature has the first conductivity type, and the second source/drain feature has a second conductivity type.

IPC Classes  ?

• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 21/762 - Dielectric regions
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

An extreme ultra violet (EUV) lithography apparatus includes a light source that generates an EUV light beam, a scanner that receives the light from a junction with the light source and directs the light to a reticle stage, and a debris catcher disposed on a EUV beam path between the light source and the scanner. The debris catcher includes a network membrane including a plurality of nano-fibers.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• B01D 39/20 - Other self-supporting filtering material of inorganic material, e.g. asbestos paper or metallic filtering material of non-woven wires
• B82Y 40/00 - Manufacture or treatment of nanostructures

Abstract

An extreme ultraviolet (EUV) photolithography system includes a scanner that directs the EUV light onto an EUV reticle. The photolithography system includes one or more contamination reduction structures positioned within the scanner and configured to attract and decompose contaminant particles within the scanner. The contamination reduction structure includes a surface material that is highly electronegative.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor

Abstract

The present disclosure provides a method for evaluating temperature information of an integrated circuit. The method includes the following steps: identifying an active region in an integrated circuit design layout; dividing the active region into a plurality of segments, wherein each segment comprises a plurality of conductors formed thereon; determining a weight of each conductor with respect to each segment; calculating a self-heat temperature increase of each conductor; and calculating a temperature increase of each segment using the weight and the self-heat temperature increase of each conductor within a valid heat-effective region of each segment.

IPC Classes  ?

• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/08 - Thermal analysis or thermal optimisation

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• C11D 3/30 - AminesSubstituted amines
• G03F 7/42 - Stripping or agents therefor

Abstract

A semiconductor package includes a semiconductor die, an insulating encapsulation, and a redistribution circuitry. The semiconductor die includes a substrate, an electrical terminal disposed over a front side of the substrate, and an insulation layer disposed over the front side of the substrate and laterally covering the electrical terminal. The insulating encapsulation extends along sidewalls of the substrate and the insulation layer of the semiconductor die. The redistribution circuitry is disposed on the insulating encapsulation, the insulation layer of the semiconductor die, and the electrical terminal of the semiconductor die. The redistribution circuitry includes a circuit portion and a first via portion connected to the circuit portion and the electrical terminal, and the first via portion is concaved toward the electrical terminal.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 25/10 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers

Abstract

A method includes forming a conductive layer over a first dielectric layer; etching a recess in the conductive layer, wherein the recess exposes a top surface of the first dielectric layer; selectively depositing a capping layer on exposed sidewalls of the conductive layer within the recess; depositing a liner on the capping layer; forming a sacrificial material in the recess; and forming a second dielectric layer on the sacrificial material and on sidewalls of the recess; and after forming the second dielectric layer, performing a thermal process to remove the sacrificial material.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate including a first well region of a first conductivity type. The semiconductor device structure also includes a first fin structure and an adjacent second fin structure formed in and protruding from the first well region. The semiconductor device structure also includes a first isolation structure formed in the first well region between the first fin structure and the second fin structure. A first sidewall surface of the first fin structure faces to a second sidewall surface of the second fin structure. The first sidewall surface and the second sidewall surface each extend along at least two directions from a bottom of the first isolation structure to a top of the first isolation structure.

IPC Classes  ?

• H01L 21/762 - Dielectric regions
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

An assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. The first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. The second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. This adjustment ability improves the beam quality of the ion source.

IPC Classes  ?

• H01J 27/08 - Ion sourcesIon guns using arc discharge
• H01J 27/02 - Ion sourcesIon guns
• H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
• H01L 21/26 - Bombardment with wave or particle radiation

Abstract

A multiple-etch process is performed to form cavities in which inner spacers of a nanostructure transistor are to be formed. The multiple-etch process includes one or more first etch operations to form the cavities, and one or more second etch operations to trim the corners of the cavities to reduce corner rounding in the corners of the cavities. The corners of the cavities have greater orthogonality between the sidewalls and inner surface of the cavities as a result of the one or more second etch operations being performed. This results in increased uniformity in the lateral thickness of the inner spacers that are subsequently formed in the cavities. The increased uniformity in the lateral thickness of the inner spacers reduces the likelihood of etching through any particular part of the inner spacers during a replacement gate operation to replace sacrificial nanostructure layers with the gate structure of the nanostructure transistor.

IPC Classes  ?

• H01L 21/8234 - MIS technology
• H01L 21/3065 - Plasma etchingReactive-ion etching
• H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

A memory device includes a plurality of word lines (WLs) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of WLs; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of WLs and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.

IPC Classes  ?

• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
• H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
• H10B 43/20 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Abstract

Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• H01L 21/66 - Testing or measuring during manufacture or treatment

Abstract

A semiconductor device including vertical transistors with a back side power structure, and methods of making the same are described. In one example, a described semiconductor structure includes: a gate structure including a gate pad and a gate contact on the gate pad; a first source region disposed below the gate pad; a first drain region disposed on the gate pad, wherein the first source region, the first drain region and the gate structure form a first transistor; a second source region disposed below the gate pad; a second drain region disposed on the gate pad, wherein the second source region, the second drain region and the gate structure form a second transistor; and at least one metal line that is below the first source region and the second source region, and is electrically connected to at least one power supply.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 25/11 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in subclass
• H10D 30/67 - Thin-film transistors [TFT]

Abstract

A representative method of manufacturing a silicon-on-insulator (SOI) substrate includes steps of depositing an etch stop layer on a dummy wafer, growing an epitaxial silicon layer on the etch stop layer, forming a gettering layer on the epitaxial silicon layer, bonding a buried oxide layer of a main wafer to the gettering layer, and removing the dummy wafer and etch stop layer to expose the epitaxial silicon layer. The SOI substrate has an epitaxial silicon layer adjoining the gettering layer, with the gettering layer interposed between the buried oxide layer and the epitaxial silicon layer.

IPC Classes  ?

• H01L 21/322 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to modify their internal properties, e.g. to produce internal imperfections
• H01L 21/762 - Dielectric regions
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Abstract

A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A method includes forming first and second semiconductor fins on a front side of a substrate, removing portions of the first and second semiconductor fins to expose first and second substrate portions, respectively, forming a first source/drain region over the first substrate portion, wherein the first source/drain region comprises an n-type epitaxial material, forming a second source/drain region over the second substrate portion, wherein the second source/drain region comprises a p-type epitaxial material, depositing a dielectric material over the first and second source/drain regions, forming an opening in the dielectric material to expose a portion of the first source/drain region and a portion of the second source/drain region, forming a mask on the exposed portion of the first source/drain region, performing an implantation process to implant a dopant in the second source/drain region, removing the mask, and depositing a conductive contact electrically connected to the first and second source/drain regions.

IPC Classes  ?

• H10B 10/00 - Static random access memory [SRAM] devices
• H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
• H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
• H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
• H01L 29/66 - Types of semiconductor device
• H01L 29/775 - Field-effect transistors with one-dimensional charge carrier gas channel, e.g. quantum wire FET
• H01L 29/786 - Thin-film transistors

Abstract

The present disclosure relates to an integrated circuit (IC) structure. The IC structure includes a semiconductor device having a frontside and a backside opposite the frontside. A first interconnect structure disposed on the frontside of the semiconductor device. The first interconnect structure comprises a first dielectric structure having a plurality of inter-level dielectric (ILD) layers. A second dielectric structure disposed on the backside of the semiconductor device. The second dielectric structure comprises a first high thermal conductivity layer having a thermal conductivity greater than that of the ILD layers.

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/373 - Cooling facilitated by selection of materials for the device
• H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
• H10D 30/43 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 1D charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor package and the method for forming the same are provided. The semiconductor package includes an oxide layer, and a waveguide and a photonic component located on a first side of the oxide layer. The semiconductor package also includes a heater element adjacent to the photonic component and configured to provide thermal energy to the photonic component. The semiconductor package also includes a redistribution structure located on a second side of the oxide layer opposite the first side. The redistribution structure includes a plurality of dielectric layers and conductive features in the dielectric layers. In addition, the semiconductor package includes a thermoelectric cooling device embedded in the dielectric layers of the redistribution structure and located directly below the photonic component.

IPC Classes  ?

• H01L 23/38 - Cooling arrangements using the Peltier effect
• G02B 6/42 - Coupling light guides with opto-electronic elements
• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• H10N 10/01 - Manufacture or treatment

Abstract

Various embodiments of the present disclosure are directed towards a semiconductor package structure including a first integrated circuit (IC) chip overlying a base structure. An electrical IC chip overlies the base structure and is disposed around the first IC chip. The electrical IC chip is electrically coupled to the first IC chip. A photonic IC chip overlies the base structure and is electrically coupled to the electrical IC chip. The photonic IC chip is configured to receive an input optical signal. The photonic IC chip is adjacent to the electrical IC chip.

IPC Classes  ?

• H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
• G02B 6/42 - Coupling light guides with opto-electronic elements
• G02B 6/43 - Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/367 - Cooling facilitated by shape of device
• H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass

Abstract

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and an isolation structure between the first and second vertical structures. The isolation structure can include a center region and footing regions formed on opposite sides of the center region. Each of the footing regions can be tapered towards the center region from a first end of the each footing region to a second end of the each footing region.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 62/822 - Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

Various embodiments of the present disclosure are directed towards a device including an interconnect structure over a substrate. A bond structure is over the interconnect structure. The bond structure includes a first plurality of conductive bond pads disposed in a first region and a second plurality of conductive bond pads disposed in a second region. The second region is adjacent to at least one side of the first region. A first pitch of the first plurality of conductive bond pads is less than a second pitch of the second plurality of conductive bond pads.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices
• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays

Abstract

A semiconductor device includes a circuit layer over a first portion of a substrate, wherein the circuit layer exposes a second portion of the substrate. The semiconductor device includes a test line electrically connected to the circuit layer. The semiconductor device includes a capacitor entirely over the second portion of the substrate. In some embodiments, a top surface of the test line is substantially coplanar with a top surface of the capacitor.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• H10D 1/00 - Resistors, capacitors or inductors
• H10D 64/01 - Manufacture or treatment
• H10D 89/10 - Integrated device layouts

Abstract

A method includes depositing an inter-layer dielectric (ILD) over a source/drain region; forming a contact opening through the ILD, wherein the contact opening exposes the source/drain region; forming a metal-semiconductor alloy region on the source/drain region; depositing a first layer of a conductive material on the metal-semiconductor alloy region; depositing an isolation material along sidewalls of the contact opening and over the first layer of the conductive material; etching the isolation material to expose the first layer of the conductive material, wherein the isolation material extends along sidewalls of the contact opening after etching the isolation material; and depositing a second layer of the conductive material on the first layer of the conductive material.

IPC Classes  ?

• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip comprising a ferroelectric structure disposed between a first conductive interconnect structure and a second conductive interconnect structure. The first conductive interconnect structure overlies a substrate. The second conductive interconnect structure overlies the first conductive interconnect structure. The second conductive interconnect structure comprises a conductive wire segment directly overlying a conductive via segment. The ferroelectric structure continuously extends along opposing sidewalls and a bottom surface of the conductive wire segment and along opposing sidewalls and a bottom surface of the conductive via segment

IPC Classes  ?

• H01L 23/528 - Layout of the interconnection structure
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
• H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
• H10D 30/01 - Manufacture or treatment
• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator

Abstract

A semiconductor device includes: a recess along a top surface of a semiconductor substrate, the recess having a first sidewall and a second sidewall laterally opposite each other; a nitride-based spacer layer extending along the first sidewall of the recess; and a field oxide layer in the recess extending along a bottom surface of the recess. The second sidewall is defined by a shallow trench isolation structure extending into the semiconductor substrate. A lateral tip of the field oxide layer is blocked by the nitride-based spacer layer from laterally extending beyond the first sidewall into the semiconductor substrate.

IPC Classes  ?

• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H01L 21/762 - Dielectric regions
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a substrate comprising a first semiconductor material and a recess in a top surface of the substrate. An absorption structure is disposed within the recess and comprising a second semiconductor material different from the first semiconductor material. The absorption structure has a first doping type. A vertical well region is disposed within the substrate and underlies the absorption structure. The vertical well region has a second doping type different from the first doping type. A liner layer is disposed between the absorption structure and the substrate. The liner layer comprises the second semiconductor material and separates the vertical well region from the absorption structure.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.

IPC Classes  ?

• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group

Abstract

An integrated transformer is disclosed. The integrated transformer includes a magnetic core situated in a first layer from among multiple layers of a semiconductor layer stack, a first conductor and a second conductor from among multiple conductors, and a via. The first conductor is situated within a second layer, above the first layer, from among the multiple layers of the semiconductor layer stack. The second conductor is situated within a third layer, below the first layer, from among the multiple layers of the semiconductor layer stack. The via physically and electrically connects the first conductor and the second conductor. The via, the first conductor, and the second conductor form a primary winding of the integrated transformer. The integrated transformer additionally includes a secondary winding, wrapped around the magnetic core, situated in the first layer, the second layer, and the third layer.

IPC Classes  ?

• H01F 41/04 - Apparatus or processes specially adapted for manufacturing or assembling magnets, inductances or transformersApparatus or processes specially adapted for manufacturing materials characterised by their magnetic properties for manufacturing cores, coils or magnets for manufacturing coils
• G05F 1/656 - Regulating voltage or current wherein it is irrelevant whether the variable actually regulated is AC or DC using variable impedances in series and in parallel with the load as final control devices
• H01F 17/00 - Fixed inductances of the signal type
• H01F 27/24 - Magnetic cores
• H01F 27/28 - CoilsWindingsConductive connections
• H01F 41/08 - Winding conductors onto closed formers or cores, e.g. threading conductors through toroidal cores
• H10D 1/20 - Inductors

Abstract

A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 64/01 - Manufacture or treatment

Abstract

A method of forming a semiconductor device includes forming source/drain regions on opposing sides of a gate structure, where the gate structure is over a fin and surrounded by a first dielectric layer; forming openings in the first dielectric layer to expose the source/drain regions; selectively forming silicide regions in the openings on the source/drain regions using a plasma-enhanced chemical vapor deposition (PECVD) process; and filling the openings with an electrically conductive material.

IPC Classes  ?

• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/01 - Manufacture or treatment

Abstract

A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.

IPC Classes  ?

• G11C 16/08 - Address circuitsDecodersWord-line control circuits
• G11C 16/10 - Programming or data input circuits
• G11C 16/14 - Circuits for erasing electrically, e.g. erase voltage switching circuits
• G11C 16/26 - Sensing or reading circuitsData output circuits

Abstract

A circuit includes a first multiplexer configured to receive a set of data elements from a data bus, a first counter configured to output a first signal sequence, a second counter configured to output a second signal sequence, an inverter configured to output a third signal sequence responsive to the first signal sequence, and a second multiplexer configured to output a fourth signal sequence responsive to each of the first through third signal sequences. Responsive to the fourth signal sequence, the first multiplexer is configured to output bits of alternating data elements of the set of data elements in alternating sequential orders.

IPC Classes  ?

• G06F 3/06 - Digital input from, or digital output to, record carriers

Abstract

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

IPC Classes  ?

• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 64/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first semiconductor device and second semiconductor device disposed on a semiconductor substrate. The first semiconductor device comprises a first gate structure, a first source region, and a first drain region. The first source and drain regions and are disposed in a first well region. The second semiconductor device comprises a second gate structure, a second source region, and a second drain region. The second source and drain regions are disposed in a second well region. The first and second well regions comprise a first doping type. The first well region is laterally offset from the second well region by a first distance. A third well region is disposed in the semiconductor substrate and laterally between the first and second well regions. The third well region comprises a second doping type opposite the first doping type.

IPC Classes  ?

• H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage

Abstract

Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may comprise a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 19/173 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using elementary logic circuits as components

Abstract

In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.

IPC Classes  ?

• G03F 1/24 - Reflection masksPreparation thereof
• G03F 1/54 - Absorbers, e.g. opaque materials
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers

Abstract

In an embodiment, a device includes: an interposer including: a back-side redistribution structure; an interconnection die over the back-side redistribution structure, the interconnection die including a substrate, a through-substrate via protruding from the substrate, and an isolation layer around the through-substrate via; a first encapsulant around the interconnection die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through-substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via that physically contacts the through-substrate via, the isolation layer separating the first conductive via from the substrate.

IPC Classes  ?

• H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
• H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates

Abstract

Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

IPC Classes  ?

• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 30/01 - Manufacture or treatment
• H10D 30/62 - Fin field-effect transistors [FinFET]
• H10D 64/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

IPC Classes  ?

• H10D 30/62 - Fin field-effect transistors [FinFET]
• H01L 21/266 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation using masks
• H01L 21/285 - Deposition of conductive or insulating materials for electrodes from a gas or vapour, e.g. condensation
• H01L 21/3115 - Doping the insulating layers
• H01L 21/762 - Dielectric regions
• H01L 21/764 - Air gaps
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 30/01 - Manufacture or treatment
• H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
• H10D 64/01 - Manufacture or treatment
• H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

A chip package structure is provided. The chip package structure includes. The chip package structure includes a first wiring substrate including a substrate, a first pad, a second pad, and an insulating layer. The chip package structure includes a chip bonded to the second pad. The chip package structure includes a nickel-containing layer under the first pad. The chip package structure includes. a conductive protection layer under the nickel-containing layer. The conductive protection layer has a curved bottom surface, the curved bottom surface is higher than a bottom surface of the insulating layer, and the curved bottom surface and the bottom surface face away from the substrate.

IPC Classes  ?

• H01L 23/498 - Leads on insulating substrates
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

A chip stack structure is provided. The chip stack structure includes a first chip including a first substrate and a first interconnect structure over the first substrate. The first interconnect structure includes a first dielectric layer and a first bonding pad embedded in the first dielectric layer. The chip stack structure includes a second chip over and bonded to the first chip. The second chip has a second interconnect structure and a second substrate over the second interconnect structure, the second interconnect structure includes a second dielectric layer and a second bonding pad embedded in the second dielectric layer, the first bonding pad is connected to the second bonding pad, and the first dielectric layer is connected to the second dielectric layer. The chip stack structure includes a conductive plug penetrating through the insulating layer to the second interconnect structure.

IPC Classes  ?

• H01L 23/00 - Details of semiconductor or other solid state devices

Abstract

Optical modules and methods of forming the same are provided. In an embodiment, an exemplary method includes forming multiple first optical elements over a first wafer, forming multiple second optical elements over a second wafer, forming multiple third optical elements over a third wafer, aligning the first wafer with the second wafer such that, upon the aligning of the first wafer with the second wafer, each first optical element is vertically overlapped with a corresponding second optical element. The method also includes bonding the first wafer with the second wafer to form a first bonded structure, aligning the second wafer with the third wafer such that, and upon bonding the second wafer of the first bonded structure to the third wafer, where upon the aligning of the second wafer with the third wafer, each second optical element is vertically overlapped with a corresponding third optical element.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• B32B 7/12 - Interconnection of layers using interposed adhesives or interposed materials with bonding properties
• B32B 37/12 - Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
• B32B 38/00 - Ancillary operations in connection with laminating processes
• H01S 5/02325 - Mechanically integrated components on mount members or optical micro-benches
• H01S 5/02345 - Wire-bonding
• H01S 5/0236 - Fixing laser chips on mounts using an adhesive
• H01S 5/0238 - Positioning of the laser chips using marks
• H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]

Abstract

A semiconductor structure includes a first dielectric layer, a first metal feature in the first dielectric layer, at least one etch stop layer on the first dielectric layer, a second dielectric layer on the at least one etch stop layer. The semiconductor structure further includes a first barrier sublayer on a sidewall of the second dielectric layer and the at least one etch stop layer, a second barrier sublayer on the first barrier sublayer and the first metal feature, and a second metal feature on the second barrier sublayer.

IPC Classes  ?

• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 23/528 - Layout of the interconnection structure

Abstract

A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a first chip structure over the wiring substrate. The chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. The heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, the top plate has a first opening, the first opening is between the first chip structure and the ring structure in a top view of the heat-spreading lid and the first chip structure, the ring structure has a second opening, the first chip structure is in the second opening, the second opening has an inner wall facing the first chip structure, and the inner wall has a recess.

IPC Classes  ?

• H01L 23/367 - Cooling facilitated by shape of device
• H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
• H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/04 - ContainersSeals characterised by the shape
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a channel structure and a first epitaxial structure and a second epitaxial structure beside opposite sides of the channel structure. The semiconductor device structure also includes a gate stack over the channel structure and a backside conductive structure electrically connected to the second epitaxial structure. A top of the second epitaxial structure is between a top of the backside conductive structure and a top of the gate stack. The semiconductor device structure further includes a dielectric layer extending along a sidewall of the backside conductive structure and extending beyond opposite sidewalls of the gate stack.

IPC Classes  ?

• H10D 30/67 - Thin-film transistors [TFT]
• H10D 30/01 - Manufacture or treatment
• H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
• H10D 86/01 - Manufacture or treatment

Abstract

A semiconductor structure includes a substrate, a gate structure, source/drain structures, a metal contact, a magnetic layer, and a first graphene. The gate structure is disposed over the substrate. The source/drain structures are disposed at opposite sides of the gate structure. The metal contact is disposed over one of the source/drain structures. The magnetic layer is over the metal contact. The first graphene layer is over the magnetic layer.

IPC Classes  ?

• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/321 - After-treatment
• H10D 62/80 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials

Abstract

A semiconductor structure includes a doped region extending in a first direction. The semiconductor structure further includes an electrode extending in a second direction perpendicular to the first direction. The electrode includes a first segment over the doped region; an extension extending beyond the doped region, wherein the extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the extension increases along an entirety of the conductive element in the second direction.

IPC Classes  ?

• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G03F 1/30 - Alternating PSM, e.g. Levenson-Shibuya PSMPreparation thereof
• G03F 1/32 - Attenuating PSM [att-PSM], e.g. halftone PSM or PSM having semi-transparent phase shift portionPreparation thereof
• G03F 1/36 - Masks having proximity correction featuresPreparation thereof, e.g. optical proximity correction [OPC] design processes
• G03F 1/70 - Adapting basic layout or design of masks to lithographic process requirements, e.g. second iteration correction of mask patterns for imaging
• G03F 7/20 - ExposureApparatus therefor
• G06F 30/39 - Circuit design at the physical level
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 111/20 - Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability
• H01L 21/027 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10B 10/00 - Static random access memory [SRAM] devices
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H10D 84/85 - Complementary IGFETs, e.g. CMOS
• H10D 89/10 - Integrated device layouts

Abstract

A semiconductor structure includes a substrate; a first column of active regions over the substrate; a second column of active regions over the substrate; and a dummy padding disposed between the first and the second columns from a top view. The dummy padding includes multiple dummy regions. A first dummy region of the multiple dummy regions is disposed between a first active region in the first column of active regions and a second active region in the second column of active regions. An outer boundary line tracing an edge of the first active region, an edge of the first dummy region, and an edge of the second active region includes at least two substantially 90-degree bends from a top view. The first and the second active regions include a semiconductor material doped with a same dopant.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A semiconductor device structure includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, and a fourth semiconductor structure over a substrate. The second semiconductor structure is between the first semiconductor structure and the third semiconductor structure. The third semiconductor structure is between the second semiconductor structure and the fourth semiconductor structure. A first lateral distance between the first semiconductor structure and the second semiconductor structure is greater than a second lateral distance between the third semiconductor structure and the fourth semiconductor structure. A third lateral distance between the second semiconductor structure and the third semiconductor structure is greater than the second lateral distance. The third lateral distance is shorter than the first lateral distance. The semiconductor device structure also includes a gate stack extending across the first semiconductor structure, the second semiconductor structure, the third semiconductor structure, and the fourth semiconductor structure.

IPC Classes  ?

• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/01 - Manufacture or treatment
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

Wafer taping apparatuses and methods are provided for determining whether taping defects are present on a semiconductor wafer, based on image information acquired by an imaging device. In some embodiments, a method includes applying an adhesive tape on a surface of a semiconductor wafer. An imaging device acquires image information associated with the adhesive tape on the semiconductor wafer. The presence or absence of taping defects is determined by defect recognition circuitry based on the acquired image information.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
• G06T 7/00 - Image analysis
• H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping

Abstract

A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate ESL. The backside gate ESL may comprise a high-k dielectric material. The semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to be electrically coupled to the first gate stack.

IPC Classes  ?

• H10D 64/01 - Manufacture or treatment
• H10D 30/67 - Thin-film transistors [TFT]
• H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

An electronic device and a method for manufacturing the same are provided. The electronic device includes an upper electronic structure, an upper connection structure, a first metal layer, a lower electronic structure, a lower connection structure and a second metal layer. The first metal layer electrically connects the upper electronic structure to the upper connection structure. The second metal layer electrically connects the lower electronic structure to the lower connection structure. The upper connection structure and the lower connection structure are bonded together.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

Abstract

A semiconductor structure includes a first shallow trench isolation (STI) structure within a semiconductor substrate. The first STI structure includes a buffer structure, an adhesion structure, an electromagnetic reflection structure, and a fill structure. The adhesion structure is between and adhesively bonded to the buffer structure and the electromagnetic reflection structure. The electromagnetic reflection structure is between the adhesion structure and the fill structure to reflect electromagnetic radiation.

IPC Classes  ?

• H10F 39/00 - Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group , e.g. radiation detectors comprising photodiode arrays
• H10F 39/18 - Complementary metal-oxide-semiconductor [CMOS] image sensorsPhotodiode array image sensors

Abstract

A method of making an integrated circuit includes forming a first gate electrode structure extending in a first direction. The method further includes forming a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The method further includes forming a conductive feature, wherein the conductive feature includes: a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction. The method further includes forming a third gate electrode structure extending in the first direction, wherein the third gate electrode structure is spaced from the first gate electrode structure in the first direction.

IPC Classes  ?

• H10D 89/10 - Integrated device layouts
• G06F 30/39 - Circuit design at the physical level
• G06F 30/392 - Floor-planning or layout, e.g. partitioning or placement
• G06F 30/398 - Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
• G06F 119/18 - Manufacturability analysis or optimisation for manufacturability
• H01L 23/528 - Layout of the interconnection structure
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

A device includes a package component including an interconnect structure on a first side of a substrate; metal pads on the interconnect structure; a semiconductor die connected to a second side of the substrate; a dielectric material surrounding the package component; a passivation layer extending over the package component and over the dielectric material; a first buffer layer over the passivation layer, wherein the first buffer layer extends over the package component and over the dielectric material, wherein a width of the first buffer layer is greater than a width of the package component and is less than a width of the passivation layer; and conductive connectors penetrating the passivation layer and the first buffer layer to physically contact the metal pads.

IPC Classes  ?

• H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
• H01L 23/00 - Details of semiconductor or other solid state devices
• H01L 23/498 - Leads on insulating substrates
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices

Abstract

An integrated chip including a substrate. A gate layer is over the substrate. A channel layer is over the substrate and vertically spaced apart from the gate layer. A ferroelectric layer is directly between the channel layer and the gate layer. A pair of source/drain electrodes are laterally spaced apart over the channel layer. A plurality of charge traps are along an interface between the ferroelectric layer and the channel layer.

IPC Classes  ?

• G11C 16/12 - Programming voltage switching circuits
• G11C 16/34 - Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A method includes forming an N well and a P well in a substrate; depositing a first layer having silicon over the N well and the P well; depositing a first dielectric layer over the first layer; forming a resist pattern over the first dielectric layer, the resist pattern providing an opening directly above the N well; etching the first dielectric layer and the first layer through the opening, leaving a first portion of the first layer over the N well; removing the resist pattern; and epitaxially growing a second layer having silicon germanium (SiGe) over the first portion of the first layer. The epitaxially growing the second layer includes steps of (a) performing a baking process, (b) depositing a silicon seed layer, and (c) depositing a SiGe layer over the silicon seed layer, wherein the steps (a), (b), and (c) are performed under about a same temperature.

IPC Classes  ?

• H10D 30/69 - IGFETs having charge trapping gate insulators, e.g. MNOS transistors
• H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
• H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
• H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
• H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
• H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/85 - Complementary IGFETs, e.g. CMOS

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a conductive base layer overlying a semiconductor substrate. A plurality of conductive pillar structures vertically extending from the conductive base layer in a direction away from the semiconductor substrate. The conductive pillar structures are laterally offset from one another. A plurality of conductive layers and a plurality of capacitor dielectric layers are disposed over the conductive pillar structures. The conductive layers and the capacitor dielectric layers are stacked alternatingly with one another. The conductive layers and the capacitor dielectric layers laterally wrap around outer perimeters of the conductive pillar structures.

IPC Classes  ?

• H10D 1/00 - Resistors, capacitors or inductors
• H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• H10D 1/68 - Capacitors having no potential barriers

Abstract

Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.

IPC Classes  ?

• H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
• H02H 1/00 - Details of emergency protective circuit arrangements

Abstract

A phase interpolating (PI) system includes: a phase-interpolating (PI) stage configured to receive first and second clock signals and a multi-bit weighting signal, and generate an interpolated clock signal on a PI stage output (PISO) node; and an amplifying stage configured to receive and amplify the interpolated clock signal, the amplifying stage including a capacitive component; the capacitive component being tunable to exhibit non-zero capacitances; and the PI stage including a first bank and a second bank corresponding outputs of which are coupled to PISO node; the first bank including parallel coupled tri-state (3S) inverters; the second bank including parallel coupled gated tri-state (G3S) inverters; each of the first and second banks being configured to receive a first clock signal; and the second bank being further configured to receive an output of the first bank, a multi-bit weighting signal and a second clock signal.

IPC Classes  ?

• H03K 5/135 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
• H03K 5/00 - Manipulation of pulses not covered by one of the other main groups of this subclass
• H03K 5/15 - Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors

Abstract

A semiconductor structure is provided. The semiconductor structure includes a substrate containing a first active region in a first region of the substrate and a second active region in a second region of the substrate, a plurality of first gate structures over the first active region each including a first gate stack having a first high-k gate dielectric and a first gate electrode and first gate spacers surrounding the first gate stack, and a plurality of second gate structures over the second active region each including a second gate stack having a second high-k gate dielectric and a second gate electrode and second gate spacers surrounding the second gate stack. At least a portion of the second gate electrode comprises dopants.

IPC Classes  ?

• H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
• H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
• H10D 64/01 - Manufacture or treatment
• H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
• H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]

Abstract

A semiconductor device includes a substrate. The semiconductor device further includes a first capacitor in the substrate. The semiconductor device further includes a first set of contacts. The first set of contacts includes a first contact electrically connected to the first capacitor, and a second contact electrically connected to the first capacitor, wherein the first contact is spaced from the second contact by a first distance. The semiconductor device further includes a second capacitor in the substrate. The semiconductor device further includes a second set of contacts. The second set of contacts includes a third contact electrically connected to the second capacitor, and a fourth contact electrically connected to the second capacitor, wherein the third contact is spaced from the fourth contact by a second distance, and the second distance is different from the first distance.

IPC Classes  ?

• H10D 1/68 - Capacitors having no potential barriers
• H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
• H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers

Abstract

A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.

IPC Classes  ?

• H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
• H01L 21/762 - Dielectric regions
• H10D 30/01 - Manufacture or treatment
• H10D 84/01 - Manufacture or treatment
• H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology

Abstract

Example implementations described herein include a laser source and associated methods of operation that can balance or reduce uneven beam profile problem and even improve plasma heating efficiency to enhance conversion efficiency and intensity for extreme ultraviolet radiation generation. The laser source described herein generates an auxiliary laser beam to augment a pre-pulse laser beam and/or a main-pulse laser beam, such that uneven beam profiles may be corrected and/or compensated. This may improve an intensity of the laser source and also improve an energy distribution from the laser source to a droplet of a target material, effective to increase an overall operating efficiency of the laser source.

IPC Classes  ?

• G03F 7/00 - Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfacesMaterials therefor, e.g. comprising photoresistsApparatus specially adapted therefor
• H05G 2/00 - Apparatus or processes specially adapted for producing X-rays, not involving X-ray tubes, e.g. involving generation of a plasma

Abstract

A method includes: charging a bit line to a read voltage level; coupling the bit line to a memory element; and adjusting a voltage level of the bit line from the read voltage level according to a data bit stored in the memory element. The read voltage level is smaller than a coercive voltage level of the memory element.

IPC Classes  ?

• G11C 16/26 - Sensing or reading circuitsData output circuits
• G11C 16/24 - Bit-line control circuits

Abstract

Contamination from outgassing during a deposition process is addressed by a series of equipment enhancements, including throttle valves, a dual air curtain, and a residual gas analysis (RGA) monitor. The dual air curtain can be configured to flow a first gas during wafer processing and a second gas during wafer unloading, to re-direct and capture outgassed species. The dual air curtain and the throttle valves can be programmed in an automated feedback control system that utilizes data from the RGA monitor.

IPC Classes  ?

• H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
• C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
• C23C 16/54 - Apparatus specially adapted for continuous coating