According to one exemplary embodiment, a chip is described, comprising a plurality of cascode circuits, wherein each cascode circuit has at least one cascode having at least one respective cascode transistor, a voltage generation circuit which is set up to generate control voltages for controlling the cascode transistors of the cascode circuits, a respective transistor circuit for each cascode, which is connected between the voltage generation circuit and the cascode, has a respective source follower and is set up to generate a cascode transistor control voltage for the at least one cascode transistor of the cascode by means of the respective source follower from a respective control voltage of the control voltages generated by the voltage generation circuit.
Described are solder stop features for electronic devices. An electronic device may include an electrically insulative substrate, a metallization on the electrically insulative substrate, a metal structure attached to a first main surface of the metallization via a solder joint, and a concavity formed in a sidewall of the metallization. The concavity is adjacent at least part of the solder joint and forms a solder stop. A first section of the metal structure is spaced apart from both the metallization and solder joint in a vertical direction that is perpendicular to the first main surface of the metallization. A linear dimension of the concavity in a horizontal direction that is coplanar with the metallization is at least twice the distance by which the first section of the metal structure is spaced apart from the first main surface of the metallization in the vertical direction. Additional solder stop embodiments are described.
The innovative concept described herein relates to a magnetic-field-based current measuring device. The latter includes, inter alia, an at least two-dimensionally measuring magnetic field sensor mounted at a node at which a first, a second and a third electrical conductor, each coming from different directions, are brought together. The magnetic field sensor is configured to determine in each case a magnitude and/or a direction of the magnetic fields which are respectively generated in the first, second and third electrical conductors and meet at the node, and to derive, on the basis thereof, information about a magnitude and/or a direction of the individual electric currents flowing at the node. The innovative concept described herein additionally relates to a corresponding method for magnetic-field-based measurement of electric currents using a magnetic-field-based current measuring device.
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
09 - Scientific and electric apparatus and instruments
10 - Medical apparatus and instruments
11 - Environmental control apparatus
12 - Land, air and water vehicles; parts of land vehicles
25 - Clothing; footwear; headgear
28 - Games; toys; sports equipment
42 - Scientific, technological and industrial services, research and design
Goods & Services
Electricity generators; agricultural, earthmoving,
construction, oil and gas extraction and mining equipment;
industrial robots; pumps [machines]; compressors [machines];
rotary blowers; machines and machine tools for treatment of
materials and for manufacturing. Downloadable and recorded content; information technology
and audio-visual, multimedia and photographic equipment;
scientific and laboratory devices for treatment using
electricity; apparatus, instruments and cables for
electricity; safety, security, protection and signalling
devices; navigation, guidance, tracking, targeting and map
making equipment; measuring, detecting, monitoring and
controlling equipment; scientific research and laboratory
apparatus, educational apparatus and simulators. Physical therapy equipment; medical and veterinary apparatus
and instruments. Lighting and lighting reflectors; heating, ventilating, and
air conditioning and purification equipment (ambient);
cooking, heating, cooling and preservation equipment, for
food and beverages; industrial treatment apparatus and
installations; refrigerating and freezing equipment; heating
elements and filaments. Vehicles and conveyances. Clothing; footwear; headgear. Sporting and physical exercise equipment; toys, games, and
playthings. Science and technology services; IT services.
5.
SEMICONDUCTOR DEVICE INCLUDING TRENCH GATE STRUCTURE AND BURIED SHIELDING REGION AND METHOD OF MANUFACTURING
In an example, for manufacturing a semiconductor device, first dopants are implanted through a first surface section of a first surface of a silicon carbide body. A trench is formed that extends from the first surface into the silicon carbide body. The trench includes a first sidewall surface and an opposite second sidewall surface. A spacer mask is formed. The spacer mask covers at least the first sidewall surface. Second dopants are implanted through a portion of a bottom surface of the trench exposed by the spacer mask. The first dopants and the second dopants have a same conductivity type. The first dopants and the second dopants are activated. The first dopants form a doped top shielding region adjoining the second sidewall surface. The second dopants form a doped buried shielding region adjoining the bottom surface.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
The application relates to a one-time programmable (otp) cell, including a selector device with a channel region, an otp capacitor with an otp capacitor dielectric associated with the selector device, and an isolation dielectric having an isolation dielectric thickness. The otp capacitor dielectric includes a first dielectric in a first area and a second dielectric in a second area. The second dielectric has a second thickness which is smaller than the isolation dielectric thickness. The first dielectric has a first thickness which is smaller than the second thickness. The first area is embedded into the second area.
A common-gate amplifying arrangement. The common-gate amplifying arrangement includes a common-gate amplifier and an inner regulated cascode. The inner regulated cascode amplifies a signal provided by the common-gate amplifier, which is responsive to an input signal.
A method of forming a semiconductor package includes providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and an adjacent stabilizing metal section, arranging the lead frame on a temporary carrier, arranging a semiconductor die on the temporary carrier within the central opening, forming a dielectric material that fills the central opening and encapsulates the semiconductor die, forming a first recess in the dielectric material above the semiconductor die so as to expose a first surface of the semiconductor die, electrically connecting terminals of the semiconductor die with the metal frame, and forming exposed outer contacts of the semiconductor package from the tie bars.
A package and method is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant at least partially encapsulating the electronic component and partially encapsulating the carrier. At least a portion of a bottom surface and at least a portion of a sidewall of the carrier are exposed beyond the encapsulant. Said at least portion of the bottom surface and said at least portion of the sidewall are covered at least partially by a plating structure.
A battery package is provided. The battery package includes a battery, at least one terminal coupled to an antenna, a single wire interface configured to communicate with a processor and coupled to the at least one terminal, a battery authentication circuit arranged on the battery, a choke inductor coupled to the single wire interface, and a clamping transistor circuit including a clamping transistor and coupled to the choke inductor and configured to clamp a voltage applied to the single wire interface to an operating voltage of the battery authentication circuit.
A semiconductor package includes a semiconductor die having a bond pad, an insulating layer covering the bond pad and having an opening with sidewalls, a polymer layer formed over the insulating layer and covering the sidewalls of the opening in the insulating layer, the polymer layer having an opening, and an electrical conductor having a conductive base attached to a part of the bond pad exposed by the insulating layer opening and the polymer layer opening. The polymer layer includes an upper segment and a lower segment. The polymer layer opening is larger in the upper segment than in the lower segment.
A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.
A semiconductor module includes a semiconductor die, a mold compound encasing the semiconductor die, a plurality of terminals electrically connected to the semiconductor die and protruding out of the mold compound, wherein a first one of the terminals has a constricted region covered by the mold compound, wherein the mold compound has a recess or an opening near the constricted region of the first terminal, and a coreless magnetic field sensor disposed in the recess or the opening of the mold compound and isolated from the first terminal by the mold compound. The coreless magnetic sensor is configured to generate a signal in response to a magnetic field produced by current flowing in the constricted region of the first terminal. The magnitude of the signal is proportional to the amount of current flowing in the constricted region of the first terminal. A method of manufacturing the module also is described.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 33/00 - Arrangements or instruments for measuring magnetic variables
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/051 - ContainersSeals characterised by the shape the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body another lead being formed by a cover plate parallel to the base plate, e.g. sandwich type
H01L 23/057 - ContainersSeals characterised by the shape the container being a hollow construction and having an insulating base as a mounting for the semiconductor body the leads being parallel to the base
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/44 - Arrangements for cooling, heating, ventilating or temperature compensation the complete device being wholly immersed in a fluid other than air
H01L 23/473 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids by flowing liquids
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message. The use of key counters may be extended to guard against weak replay attacks via the implementation of a live membership tracking solution, which defines one or more membership groups. Each node within a membership group may request, or “challenge” other nodes with the same membership group at any time to verify their online status, and this online status may be maintained over time.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
A system includes a semiconductor device comprising a source terminal, a drain terminal, and an interface layer between the source terminal and the drain terminal, the interface layer comprising a plurality of interface channels. The system also includes a degradation monitoring circuit comprising an electrical sensor, wherein the degradation monitoring circuit is configured to: generate, using the electrical sensor, a sensor signal corresponding to one or more interface channels of the plurality of interface channels; determine, based on the sensor signal, whether a degradation of a material is present at the one or more interface channels of the plurality of interface channels; and output information indicating whether the degradation of the material is present at the one or more interface channels of the plurality of interface channels.
An electronic device is described herein which may be used as an electronic fuse (smart fuse). The device includes an electronic switch having a load current path coupled between an output node and a supply node and configured to connect or disconnect the output node and the supply node in accordance with a control signal. The device further includes a control circuit configured to generate the control signal based on an input signal, a current sense circuit configured to provide a current sense signal that represents a load current passing through the electronic switch, and a monitoring circuit configured to generate an overcurrent signal based on the current sense signal. The overcurrent signal is indicative of whether, or not, to disconnect the output node from supply node. The control circuit is configured to operate in a normal mode, an idle mode, and in a diagnosis mode.
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
G01R 31/26 - Testing of individual semiconductor devices
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
17.
PACKAGE WITH COMPONENT-CARRYING INTERMEDIATE STRUCTURE AND ADDITIONAL CARRIER HAVING REFERENCE POTENTIAL STRUCTURE
A package is disclosed. In one example, the package includes an at least partially electrically conductive carrier having a coupling structure and a reference potential structure which is electrically decoupled from the coupling structure and which is configured to be brought to an electric reference potential during operation of the package, an intermediate structure at the carrier and having an electrically insulating structure oriented towards the carrier and having a mounting structure facing away from the carrier. An electronic component is mounted on the mounting structure and being electrically coupled with the coupling structure. An encapsulant is encapsulating at least part of the intermediate structure, at least part of the electronic component, and part of the carrier so as to expose at least part of the reference potential structure and at least part of the coupling structure.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
18.
POWER TRANSISTOR CONTROL AND OVERCURRENT DETECTION
In accordance with an embodiment, a circuit includes a power transistor connected between a supply terminal and an output terminal; a control circuit coupled to a control electrode of the power transistor and configured to apply a control current to the control electrode to turn the power transistor on or off; and an overcurrent protection circuit connected to the power transistor. The circuit is configured to operate in a first mode, in which some functions of the circuit are inactive to reduce power consumption, and in a second mode, in which all functions of the circuit are active. The overcurrent protection circuit is configured to: in response to the circuit being in the first mode and a sense signal indicative of a load current passing through the power transistor reaching a first threshold, cause the circuit to change from the first mode to the second mode.
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
19.
SYSTEM AND METHOD FOR FAST MODE CHANGE OF A DIGITAL MICROPHONE USING DIGITAL CROSS-TALK COMPENSATION
A circuit includes a cross-talk compensation component including a power profile reconstruction component for reconstructing the power profile of a digital microphone coupled to a microelectromechanical (MEMS) device, wherein the power profile represents power consumption of the digital microphone over time between at least two operational modes of the digital microphone, and a reconstruction filter for modeling thermal and/or acoustic properties of the digital microphone; and a subtractor having a first input for receiving a signal from the digital microphone, a second input coupled to the cross-talk compensation component, and an output for providing a digital output signal.
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
H04R 3/06 - Circuits for transducers for correcting frequency response of electrostatic transducers
20.
SECURE COMMUNICATIONS USING PRE-SHARED KEYS AND LIVE MEMBERSHIP
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message. The use of key counters may be extended to guard against weak replay attacks via the implementation of a live membership tracking solution, which defines one or more membership groups. Each node within a membership group may request, or "challenge" other nodes with the same membership group at any time to verify their online status, and this online status may be maintained over time.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
In some examples, this disclosure describes a method that comprises controlling power switches to deliver a current to an electric motor, wherein the power switches are arranged in a bridge (e.g., an H-bridge or an h-bridge) comprising a first high-side power switch, a first low-side power switch, and a second low-side power switch. Controlling the power switches to deliver the current to the electric motor may include controlling the first high-side power switch ON and controlling the second low-side power switch ON, wherein the current to the electric motor flows through the high-side power switch and through the second low-side power switch. The method may comprise determining the current to the electric motor based on a voltage drop over one of the power switches arranged in the bridge.
An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine a plurality of addresses of packed data and fetch the packed data from a memory device based on the plurality of addresses. The packed data is stored on the memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the fetched packed data to the processor, where the output data is configured according to the predefined data structure. The memory fetch device is configured to process the packed data in a predefined order.
A chip package includes a chip with at least one contact pad, a contact structure formed from at least one continuous longitudinally extended electrically conductive element by attaching the conductive element to the contact pad in at least three contact positions, wherein the conductive element bends away from the contact pad between pairs of consecutive contact positions, and an encapsulation partially encapsulating the contact structure, wherein the encapsulation includes an outer surface facing away from the chip, and wherein the contact structure is partially exposed at the outer surface.
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method for assigning an address to an electronic device, and devices and circuit arrangements for implementing the method. The method may comprise:
a) sending a general command from a controller of a circuit arrangement to all electronic devices of the circuit arrangement, wherein the general command prompts each electronic device to start sending a respective unique identifier (UID) of the respective electronic device;
b) sending the respective UIDs from the electronic devices bit-by-bit in parallel;
c) performing a bit-by-bit arbitration among the electronic devices based on the UIDs until only one electronic device remains active;
d) sending an electrical parameter from the active electronic device to the controller;
e) determining a property of the active electronic device from the electrical parameter; and
f) assigning an address to the active electronic device from a predetermined set of addresses.
A switched capacitor converter can comprise an input pad for applying an analog input voltage; an input capacitor, the first terminal of which is continuously electrically conductively connected to the input pad and the second terminal of which is electrically conductively connected to an input of an amplifier; the amplifier; and a switched capacitor circuit, which is electrically conductively connected to the amplifier input on the one hand, and can be switched between a reference potential and a predefined reference voltage on the other.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H03M 1/80 - Simultaneous conversion using weighted impedances
A substrate includes a dielectric insulation layer, a first metallization layer attached to a first side of the dielectric insulation layer, and a second metallization layer attached to a second side of the dielectric insulation layer opposite the first side. The second metallization layer includes one or more first areas and one or more second areas. The second metallization layer in the one or more first areas has a first thickness, and in the one or more second areas has a second thickness that is greater than the first thickness. Methods of producing the substrate are also described.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
27.
AREA OPTIMIZED MODIFIED CROSS PARITY CODE FOR FAST ERROR CORRECTION AND DETECTION
A solution is directed to determining an error in k data bits comprising the steps: determining the error, in particular the position of the error, based on M check bits and on n check bits; wherein the k data bits are arranged according to a structure; wherein the structure comprises the M check bits, wherein the M check bits are calculated based on the k data bits; wherein the structure comprises n groups, n being larger or equal to two, wherein each of the k data bits is associated with one of the n groups and wherein each of the n groups is associated with one of the n check bits.
H03M 13/11 - Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
28.
CIRCUIT FOR DISCHARGING A CAPACITOR USING POWER TRANSISTORS OPERATING IN NON-LINEAR MODE
A circuit includes a first power transistor and a second power transistor. The circuit also includes a controller configured to control the first power transistor to perform a sequence of first switching cycles by applying, for each switching cycle of the sequence of first switching cycles, a first gate voltage exceeding a threshold gate voltage so that the first power transistor operates according to a non-linear transfer function. The controller is also configured to control the second power transistor to perform a sequence of second switching cycles by applying, for each switching cycle of the sequence of second switching cycles, a second gate voltage exceeding the threshold gate voltage so that the second power transistor operates according to the non-linear transfer function. The controller is configured to cause the capacitor to discharge according to a sequence of discharge phases.
Motor controller circuitry configured to operate two or more motors by driving the motors connected to output terminals of the motor controller circuitry. Each output terminal of the motor controller circuitry may connect to a driver circuit of the motor controller circuitry. Two, or more, of the motors may share an output terminal. For motors that share an output terminal, the operation of a first motor may affect the operation of other motors connected to that shared output terminal. The motor controller circuitry may store information about which output terminals may be paired, that is, which output terminals may connect to the same motor. Based on pairing information stored by the motor controller circuitry, protection circuitry of the motor controller circuitry may operate to prevent nuisance shutdown of a motor because the operation of another motor that shares the same output pin.
H02P 5/68 - Arrangements specially adapted for regulating or controlling the speed or torque of two or more electric motors controlling two or more DC dynamo-electric motors
30.
METAL-FILLED CONTACT HOLE IN MICRO-FABRICATED DEVICE
A metal-filled contact hole is generated in micro-fabrication technology by forming a first metal layer over a substrate and a first interface metal layer over the first metal layer. A metal of the first interface metal layer is different from a metal of the first metal layer. A dielectric layer is formed over the first interface metal layer. A contact hole is formed in the dielectric layer. A second interface metal layer is formed over the first interface metal layer after forming the contact hole. A second metal layer is formed over the second interface metal layer. A metal of the second interface metal layer is different from a metal of the second metal layer. The substrate is annealed, such that an oxide layer previously formed on the first interface metal layer in a period between the formation of the first and second interface metal layers is diluted by diffusion.
The implementation proposes a magnetoresistive sensor, including at least one xMR sensor element formed from a layer stack, having a magnetically free layer having a magnetically free vortex magnetization, and having at least one reference layer having a reference magnetization in a predetermined direction. Magnetically free layers having a magnetically free vortex magnetization that are arranged along the predetermined direction on opposite sides of the xMR sensor element and laterally adjacent to the xMR sensor element. The adjacent magnetically free layers can act as magnetic flux concentrators for the magnetoresistive sensor element arranged therebetween.
A semiconductor device is disclosed. The semiconductor device includes a chip carrier having a first cavity and a second cavity. A semiconductor die is mounted in the first cavity. The semiconductor die includes a patterned top metallization layer having a first electrical contact pad. An insulating layer is arranged inside the second cavity. A first end of a first electrical conductor is arranged over the insulating layer and a second end of the first electrical conductor is arranged on the first electrical contact pad of the semiconductor die. An encapsulant encapsulates the semiconductor die, both ends of the first electrical conductor, and parts of the chip carrier. A method for manufacturing the semiconductor device is also disclosed.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
33.
ULTRA-WIDEBAND RADAR DEVICE, METHOD FOR AUTHORIZING A CONTROL ACTION AND METHOD FOR SECURE LOCALIZATION
An ultra-wideband (UWB) radar device including a transmitter configured to generate a first radio signal by modulating a first carrier signal with a first M-sequence and transmit the first radio signal, a receiver configured to receive a radio signal and correlate the received radio signal with a predetermined second M-sequence different from the first M-sequence and a controller configured to authorize a predetermined control action in reaction to a determination, based on the correlation result, that a device has responded to the first radio signal with a second radio signal generated by modulating a second carrier signal with the second M-sequence.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Chips [integrated circuits]; semiconductor devices;
authentication software; cloud computing software; computer
operating system software; security software; software
development kit [SDK]; integrated circuit cards [smart
cards]; radio-frequency identification (RFID) tags; internet
of things [IoT] sensors; semiconductor chips;
semiconductors; microprocessors; microcontrollers;
electronic components; wireless transmitting and receiving
equipment; integrated circuit modules; transmitters and
receivers; electronic navigational and positioning apparatus
and instruments; sensors for determining position. Research and development services; software as a service
[SaaS]; cloud computing; consulting in the field of cloud
computing networks and applications; design and development
of computer hardware and software; advisory services
relating to computer programming.
35.
SEMICONDUCTOR DEVICE COMPRISING A CARRIER, A SEMICONDUCTOR DIE AND A C-SHAPED CLIP CONNECTED BETWEEN THEM
A semiconductor device comprising a carrier, a semiconductor die disposed on the carrier and comprising a first contact pad on a first main face remote from the carrier, and a clip. The clip comprises a horizontal portion, a vertical portion, and a bent-back portion connected with the carrier.
A silicon carbide device includes: a transistor cell having a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; at least one source region of a first conductivity type in contact with the first gate sidewall; and a region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. No source regions of the first conductivity type are in contact with a second gate sidewall of the gate structure.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
In accordance with an embodiment, a method for augmenting training data for a neural network includes: running a validation dataset through the neural network to provide a first output; analyzing the first output of the neural network to determine first correct predictions and first incorrect predictions using a classifier; mutating seeds of the validation dataset corresponding to the first correct predictions; running the mutated seeds through the neural network to provide a second output; analyzing the second output of the neural network to determine second correct predictions and second incorrect predictions using the classifier; determining whether there is an increase in neural network coverage for mutated seeds yielding the second correct predictions; and performing steps of mutating the seeds, running the mutated seeds through the neural network, and analyzing the second output of the neural network for the mutated seeds yielding the second correct predictions.
A device is provided. The device includes a first portion having a phase change switch device on a first substrate and a second portion having a semiconductor circuit on a second substrate. The first and second portions are bonded together. A method of manufacturing the device is also described.
A sensor device contains a magnetic field sensor chip having a front face, a rear face and a side surface connecting the front face and the rear face. The magnetic field sensor chip has a sensor element which is arranged on the front face and is configured to detect a magnetic field component running parallel to the front face. The magnetic field sensor chip furthermore has multiple first contact pads arranged on the front face, wherein all of the first contact pads arranged on the front face are arranged at an edge of the magnetic field sensor chip lying between the front face and the side surface.
A semiconductor device includes an electrically conductive carrier, a semiconductor chip arranged over a section of the carrier, and a dielectric material arranged between the carrier section and the semiconductor chip. The dielectric material galvanically isolates the carrier section and the semiconductor chip from one another. The dielectric material includes a polyimide tape, wherein an edge region of the polyimide tape is bent away from the carrier section.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A method for performing a sequential diagnosis in a power network is presented. The method comprises:
a) sending a diagnosis control signal from a controller to a power switch for starting the sequential diagnosis at an initial diagnosis state of the power switch and using timeouts of the diagnosis control signal for changing a present diagnosis state of the power switch;
b) if a timeout matches a predetermined time interval, continuing the sequential diagnosis by going on to a subsequent diagnosis state of the present diagnosis state; and
c) if a timeout exceeds a predetermined time threshold, resetting the sequential diagnosis by restarting at the initial diagnosis state.
A method for performing a sequential diagnosis in a power network is presented. The method comprises:
a) sending a diagnosis control signal from a controller to a power switch for starting the sequential diagnosis at an initial diagnosis state of the power switch and using timeouts of the diagnosis control signal for changing a present diagnosis state of the power switch;
b) if a timeout matches a predetermined time interval, continuing the sequential diagnosis by going on to a subsequent diagnosis state of the present diagnosis state; and
c) if a timeout exceeds a predetermined time threshold, resetting the sequential diagnosis by restarting at the initial diagnosis state.
Further, a power switch is presented.
G01R 31/327 - Testing of circuit interrupters, switches or circuit-breakers
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
42.
Power Semiconductor Device and Method of Producing a Power Semiconductor Device
A power semiconductor device includes: a semiconductor body with a drift region of a first conductivity type and load terminals at opposite first and second sides of the semiconductor body. The power semiconductor device is configured to conduct a forward load current between the load terminals. A trench grid structure extending from the first side into the semiconductor body includes a plurality of macro cells. Each macro cell includes at least one first type micro cell configured for the forward load current conduction and a number of second type micro cells not configured for the forward load current conduction. Each micro cell is laterally confined by a respective portion of the trench grid structure. In each macro cell, the number of the second type micro cells is equal to or greater than the number of first type micro cells.
According to one exemplary embodiment, a data processing device is described, having a plurality of data processing components which are configured to exchange respective synchronization information with one another in pairs at predefined synchronization points, and having a writable configuration memory configured to store, for each reset type of a plurality of reset types, whether the exchange of the respective synchronization information is required for all of the synchronization points, in order that the respective pair of data processing components may continue its processing beyond the synchronization points. The data processing components are configured to continue or not continue their processing beyond synchronization points in accordance with the content of the writable configuration memory in the absence of an exchange of synchronization information.
G06F 21/54 - Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity, buffer overflow or preventing unwanted data erasure by adding security routines or objects to programs
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
44.
ELECTRONIC SYSTEM HAVING AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT
The present disclosure relates to an electronic system including a master IC, a slave IC and a serial communication interface having a bidirectional data line and a clock line. The master IC is configured to send a data request command to the slave IC via the data line. The slave IC is configured to begin providing requested data in response to the data request command. The slave IC is configured to deactivate the clock line after receiving a data read command and until the slave IC can provide the requested data. The master IC is configured to measure a duration of the deactivation of the clock line and to set a wait time between a next data request command and a next data read command according to the measured duration.
A semiconductor device includes an electrically conductive carrier and a semiconductor chip arranged over a first portion of the carrier. The semiconductor device further includes a dielectric material arranged between the first portion of the carrier and the semiconductor chip, wherein the dielectric material galvanically isolates the first portion of the carrier and the semiconductor chip. At least one of the first portion of the carrier or the semiconductor chip includes at least one of a rounded corner or a rounded edge.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/13 - Mountings, e.g. non-detachable insulating substrates characterised by the shape
46.
Methods of Semiconductor Device Fabrication Involving Porous Silicon Carbide
A method includes: providing a layer of porous silicon carbide supported by a silicon carbide substrate; providing a layer of epitaxial silicon carbide on the layer of porous silicon carbide; forming semiconductor devices in the layer of epitaxial silicon carbide; and separating the silicon carbide substrate from the layer of epitaxial silicon carbide at the layer of porous silicon carbide. The layer of porous silicon carbide includes dopants that define a resistivity of the layer of porous silicon carbide. The resistivity of the layer of porous silicon carbide is different from a resistivity of the silicon carbide substrate. Additional methods are described.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
An ultrasonic touch sensor includes a touch structure comprising a touch surface configured to receive a touch; an ultrasonic transmitter configured to transmit at least one ultrasonic transmit wave toward the touch structure; an ultrasonic receiver configured to receive ultrasonic reflected waves produced by a plurality of reflections of the at least one ultrasonic transmit wave and generate a measurement signal representative of the ultrasonic reflected waves; and a measurement circuit configurable in a first operation mode corresponding to an air environment and a second operation mode corresponding to a wet environment. The measurement circuit is configured to calculate a rate of change of a plurality of samples of the measurement signal, perform a first comparison based on the rate of change and a rate of change threshold, and operate in the second operation mode based on the rate of change satisfying the rate of change threshold.
An approach corrects at least one byte error in a binary sequence, the binary sequence comprising multiple bytes and being a codeword of an error code if there is no error. The approach comprises: (i) determining at least one byte error position signal indicating whether or not a byte of the binary sequence is erroneous, (ii) determining at least one byte error correction value on the basis of which an erroneous byte position identified by using the byte error position signal is able to be corrected, (iii) wherein the at least one byte error correction value is determined by determining a first value, a second value and a third value for each of at least three byte positions according to a coefficient of the locator polynomial, and (iv) correcting the at least one byte error on the basis of the at least one byte error correction value.
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
A method of processing a semiconductor wafer includes: forming one or more epitaxial layers over a first main surface of the semiconductor wafer; forming one or more porous layers in the semiconductor wafer or in the one or more epitaxial layers, wherein the semiconductor wafer, the one or more epitaxial layers and the one or more porous layers collectively form a substrate; forming doped regions of a semiconductor device in the one or more epitaxial layers; and after forming the doped regions of the semiconductor device, separating a non-porous part of the semiconductor wafer from a remainder of the substrate along the one or more porous layers.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/288 - Deposition of conductive or insulating materials for electrodes from a liquid, e.g. electrolytic deposition
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
In accordance with an example embodiment, a method includes: obtaining an in-phase and quadrature (IQ) representation of radar data indicating a received radar signal, determining an approximation of the IQ representation, the approximation having a spiral configuration, and determining a phase of the received radar signal based on the approximation.
G01S 7/41 - Details of systems according to groups , , of systems according to group using analysis of echo signal for target characterisationTarget signatureTarget cross-section
51.
SEMICONDUCTOR DEVICE WITH METAL STRUCTURE PASSIVATION
A semiconductor device includes a semiconductor substrate. A metal structure is disposed over the semiconductor substrate. A metal of the metal structure is Cu or a Cu-based alloy. A passivation layer is disposed over the metal structure. The passivation layer includes a first layer including CuSiN, and a second layer including Si, N and H. In atomic numbers, a ratio of Si to N is equal to or greater than 3.3/4. A method of manufacturing the semiconductor device is also described.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
A power amplifier arrangement, for one or more antennae, with a calibratable dummy load. The power amplifier arrangement includes a calibration arrangement that controls or defines an amount of power drawn by the dummy load responsive to a power-responsive parameter that changes responsive to an amount of power drawn by one or more power amplifiers of the power amplifier arrangement when amplifying an input signal to be transmitted by the antenna(e).
A cache system is provided for system with a CPU and memory. The CPU has a stack pointer register for storing a stack pointer. The stack pointer represents an address in main memory at the top of the stack. The cache system has a cache RAM structured into cache lines and cache controller circuitry. The cache controller circuitry is operable to: receive the stack pointer, store a first cache line containing the contents of a first address range of bytes of the main memory, the first address range including the stack pointer; and lock the first cache line to protect the first cache line from cache eviction.
An electronic control unit is presented. The electronic control unit comprises: a plurality of digital drivers, each digital driver being configured for controlling at least one load; a central microcontroller configured for controlling the digital drivers; and an interconnection for communication between the central microcontroller and the digital drivers, the interconnection comprising: at least one serial bus configured for transmitting digital signals between the central microcontroller and the digital drivers; and at least one communication protocol comprising a set of commands and a set of addresses for communication. Further, a method for controlling a load by using the electronic control unit as well as a use for an automotive application of the electronic control unit and the method are presented.
A package configured as power stage is disclosed. In one example, the package includes a first transistor chip and a second transistor chip being interconnected to form a half bridge, a driver chip configured for driving the first transistor chip and the second transistor chip, and an encapsulant at least partially encapsulating the first transistor chip, the second transistor chip. The driver chip, wherein the driver chip comprises electrically conductive driver pads, at least one of which being arranged on each of both opposing main surfaces of the driver chip, and comprises at least one electrically conductive driver through connection extending through the driver chip between said opposing main surfaces.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
The disclosure relates to a semiconductor die, comprising: a first diode chain having a number n1 of diode junctions connected in series, where n1≥1; a second diode chain having a number n2 of diode junctions connected in series, where n2≥1; the first diode chain and the second diode chain to be biased with the same current as a temperature sensor, wherein the first diode chain and the second diode chain differ from each other in their respective number n1, n2 of junctions and/or in a doping concentration of at least one of the junctions.
G01K 7/01 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using semiconducting elements having PN junctions
H01L 27/08 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
57.
SYSTEM AND METHOD FOR USING PSEUDO-LABELS WITH A MACHINE-LEARNING MODEL
In accordance with an embodiment, a method includes obtaining a machine-learning model in a first training state; using the machine-learning model in the first training state to infer predictions based on multiple measurement feature vectors obtained at an agent; based on the predictions, populating a first training dataset using labels for a first subset of the multiple measurement feature vectors; based on the predictions, populating a second training dataset using pseudo-labels for a second subset of the multiple measurement feature vectors; and determining a second training state of the machine-learning model based on the first training dataset and the second training dataset.
A transistor device includes a plurality of transistor cells. Each transistor cell includes two load electrodes and a control electrode. The two load electrodes of the transistor cells are arranged spaced apart from each other in a first direction. A first pitch between adjacent load electrodes of a first subset of pairs of the two load electrodes is smaller than a second pitch between adjacent load electrodes of a second subset of pairs of the two load electrodes. Airgaps are provided between adjacent load electrodes of the second subset of pairs.
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
59.
Switch Module Having a Short Circuit Detection Circuit
Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch and a short circuit detection circuit. The transistor switch includes a control terminal, a first load terminal and a second load terminal. The short circuit detection circuit is configured to detect a short circuit state between the first load terminal and the second load terminal and to automatically switch off the transistor switch without additional signaling, by automatically electrically coupling the control terminal to the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is energized by a voltage between the control terminal and the first load terminal.
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
60.
ENCAPSULATED PACKAGE WITH CARRIER, LAMINATE BODY AND COMPONENT IN BETWEEN
A package and method of manufacturing a package is disclosed. In one example, the method comprises mounting at least one electronic component on a carrier, attaching a laminate body to the mounted at least one electronic component, and filling at least part of spaces between the laminate body and the carrier with mounted at least one electronic component with an encapsulant.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method for calibrating a phase modulator includes determining a set of phase measurement values, calculating a value for each error parameter of a set of error parameters corresponding to an error model related to the phase modulator using the set of phase measurement values and at least one analytical function derived from the error model and storing for each error parameter of the set of error parameters the calculated value in a memory for setting a phase correction to the phase modulator.
H01Q 3/34 - Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elementsArrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the distribution of energy across a radiating aperture varying the phase by electrical means
62.
PROCESSING ARCHITECTURE SUPPORTING AN OUT OF ORDER NUMBER THEORETIC TRANSFORM
The described techniques increase the performance and efficiency of hardware (HW) accelerators that may be used as part of post-quantum cryptography (PQC) applications. Such hardware accelerators comprise those configured to perform so-called “butterfly operations,” which process coefficients of a polynomial over which a number theoretic transform (NTT) operation is performed. The techniques include the use of re-ordering buffers to ensure an efficient memory storage solution that allows for the computation of a single address location when reading the inputs to the next stages of the hardware accelerator. The described architecture facilitates flexible and scalable solutions to meet the high performance demands of PQC processing.
Systems, methods, and circuitries are provided for detecting lost interrupt events in a reduced instruction set computer-V (RISC-V) architecture. An example architecture includes an advanced platform level interrupt controller (APLIC) and an incoming message signaled interrupt (MSI) controller (IMSIC) coupled to the APLIC. The APLIC includes a plurality of respective vectors connected to respective external interrupt inputs, wherein each vector is mapped to an interrupt priority and each vector comprises a vector interrupt lost (IL) bit. The IMSIC is configured to receive MSI from the APLIC and to maintain an interrupt file that includes a set of a set of interrupt lost (IL) bits indexed by interrupt priority.
A driving safety system for a motor vehicle with at least one wheel speed sensor is disclosed, which is configured to determine the actual wheel speed on a wheel, and a driving safety control unit configured to receive a wheel speed signal generated by the wheel speed sensor, where the wheel speed signal represents a determined actual wheel speed. The wheel speed signal is transmitted via an unprotected transmission channel between the wheel speed sensor and the driving safety control unit. The driving safety control unit is configured to receive a travel signal that correlates with the actual vehicle speed and to compare the travel signal with the wheel speed signal to check the wheel speed signal for plausibility. The movement signal is transmitted to the driving safety control unit via a safe transmission channel.
B60W 50/00 - Details of control systems for road vehicle drive control not related to the control of a particular sub-unit
B60W 10/184 - Conjoint control of vehicle sub-units of different type or different function including control of braking systems with wheel brakes
B60W 10/30 - Conjoint control of vehicle sub-units of different type or different function including control of auxiliary equipment, e.g. air-conditioning compressors or oil pumps
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message.
A circuit arrangement for operating a resistive sensor element is described. According to an example implementation, the circuit arrangement includes a first supply terminal and a second supply terminal, between which is applied a supply voltage during operation, and a sensor circuit having at least one resistive sensor element. The sensor circuit has a first circuit node and a second circuit node for applying a sensor voltage, wherein the first circuit node is connected to the first supply terminal. The circuit arrangement further includes a sensor supply circuit, which is configured to electrically couple, during a measurement time interval, a charged capacitor to the second circuit node in such a way that the sensor voltage between the first circuit node and the second circuit node is greater than the supply voltage.
G01N 27/18 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of an electrically-heated body in dependence upon change of temperature caused by changes in the thermal conductivity of a surrounding material to be tested
G01N 33/00 - Investigating or analysing materials by specific methods not covered by groups
A transient voltage suppressor (TVS) circuit is described. The TVS circuit includes a semiconductor substrate having a first TVS device and a second TVS device electrically connected in series. The TVS circuit further includes a resistor. The resistor and at least one of the first TVS device and the second TVS device are electrically connected in parallel. A method of manufacturing the TVS circuit is also described.
H01L 27/02 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
68.
PAD OVER ACTIVE SENSOR CELLS INTEGRATED IN A CHIP PACKAGE
A chip-scale package includes a magnetic sensor integrated circuit (IC) and a conductive contact pad. The magnetic sensor IC includes an IC layer stack comprising a plurality of isolation layers and a plurality of conductive layers; and a magnetoresistive sensing element integrated in the IC layer stack. The magnetoresistive sensing element includes a reference layer having a fixed reference magnetization aligned with a magnetization axis, and a magnetic free layer having a magnetically free magnetization. The magnetically free magnetization is variable in a presence of an external magnetic field. The conductive contact pad is arranged on or integrated in the IC layer stack. Moreover, the conductive contact pad is arranged over the magnetoresistive sensing element such that the conductive contact pad and the magnetoresistive sensing element at least partially vertically overlap.
A magnetic field sensor chip includes an input terminal configured to receive an external bias current from an external current source; an internal current generator configured to split the external bias current into a plurality of internal bias currents, including a first internal bias current and a second internal bias current; a Hall sensor configured to be biased by the first internal bias current and set at a first operating point based on the first internal bias current, wherein the Hall sensor is further configured to generate a sensor signal based on a magnetic field and the first operating point; and an amplifier configured to be biased by the second internal bias current and set at a second operating point based on the second internal bias current. The amplifier is configured to amplify the sensor signal into an amplified sensor signal based on the second operating point.
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
70.
ENCAPSULANT WITH ORGANIC CONSTITUENT AND INORGANIC CONSTITUENT HAVING ADJUSTED RELATIVE DIELECTRIC CONSTANT
An encapsulant for an electronic package is disclosed. In one example, the encapsulant comprises at least one organic constituent, and at least one inorganic constituent. A difference between the relative dielectric constant of the at least one organic constituent and the relative dielectric constant of the at least one inorganic constituent divided by the relative dielectric constant of the at least one organic constituent has an absolute value of not more than 0.2.
A method of manufacturing a superconductive integrated circuit on a substrate includes forming a first superconductive layer of a superconductive material over the substrate. A Josephson junction (JJ) layer stack including a JJ barrier layer is formed over the first superconductive layer. The JJ layer stack is structured to form a JJ structure. The first superconductive layer is structured to form a structured first superconductive layer. A dielectric cover layer is formed over the JJ structure. The dielectric cover layer is structured a first time to expose an upper side of the JJ structure. A second superconductive layer of a superconductive material is formed over the dielectric cover layer. The second superconductive layer is structured to form a structured second superconductive layer.
A semiconductor device includes a plurality of mesas, each mesa including an epitaxial Group III nitride-based multi-layer structure, an insulating matrix having an upper surface and a lower surface, wherein side faces of the mesas are embedded in the insulating matrix and a top surface of the mesas is substantially coplanar with the upper surface of the insulating matrix, and a metallization structure including a gate finger and a drain finger arranged on the top surface of each mesa, a drain bus that electrically couples a first drain finger arranged on a first mesa with a second drain finger arranged on a second mesa, and a gate bus that electrically couples a first gate finger arranged on the first mesa with a second gate finger arranged on a second mesa.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
73.
COMPONENT AND METHOD OF MANUFACTURING A COMPONENT USING AN ULTRATHIN CARRIER
In an embodiment a packaged semiconductor device includes a carrier, a component disposed on the carrier, the component having a substrate with a thickness of about 40 μm or less and a metal block, a single titanium layer connecting the component and the metal block, the single titanium layer functioning as a combined metal adhesion layer and a metal barrier layer, a connection layer connecting the carrier and the component, a conductive wire connecting a component contact pad of the component with a carrier contact pad of the carrier and an encapsulant encapsulating the component.
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
The described techniques address issues to achieve key agreement without the need to exchange separate key agreement messages and, consequently, meets the stringent starting time requirements for real-time control systems. This is achieved using a group-wide key counter, with each node storing the latest value of this counter that was observed via the last received secured message. This counter value increases monotonically, and nodes maintain synchronization by transmitting this counter value (or a representation of the counter value) in each secured message.
A three-dimensional integrated circuit includes a first integrated circuit having a first transistor and a first buried oxide layer; a second integrated circuit having a second transistor and a second buried oxide layer; a bond interface between an upper surface of the first integrated circuit and an upper surface of the second integrated circuit; a passivation layer coupled to the first buried oxide layer; and a mold wafer coupled to the second buried oxide layer.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
76.
DRIVER CIRCUIT WITH A MULTI-FUNCTION PIN USED FOR IN-LINE CHARACTERIZATION OF A POWER SWITCH
This disclosure is directed to a driver circuit configured to control a power switch. The driver circuit may comprise an output pin, wherein the driver circuit is configured to deliver drive signals from the output pin to the power switch to control turn ON of the power switch; a multi-function pin; and a state machine configured to define operation of the driver circuit using the multi-function pin, wherein the state machine is configured to select among a soft turn OFF mode, a clamping mode, and an in-line characterization mode.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes a semiconductor substrate, a phase change switching device formed over the semiconductor substrate and including a strip of phase change material connected between an RF input contact and an RF output contact, and a heating element thermally coupled to the strip of phase change material, and a silicon adhesion layer that forms a direct interface with a first surface of the strip of phase change material and separates the first surface from a dielectric material formed thereon.
The present disclosure relates to a magnetoresistive sensor. The magnetoresistive sensor includes at least one sensor element having a layer stack. The layer stack includes a magnetically free layer with a magnetically free magnetization. A measurement sensitivity of the sensor element is temperature-dependent. The magnetoresistive sensor also includes a device which is configured to induce a temperature-dependent mechanical stress in the magnetically free layer. The temperature dependence of the measurement sensitivity can be at least partially compensated for by the temperature-dependent mechanical stress.
G01L 1/12 - Measuring force or stress, in general by measuring variations in the magnetic properties of materials resulting from the application of stress
According to some embodiments, an electronic device is described, having a counter circuit which is configured to detect first pulses in a received first output signal and to determine a number of the detected first pulses, a counter circuit which is configured to detect second pulses in a received second output signal and to determine a number of the detected second pulses, and an error detection circuit configured to register a first difference between the number of first pulses detected in a first time interval and the number of second pulses detected in the first time interval, determine a second difference between the number of first pulses detected in a second time interval and the number of second pulses detected in the second time interval and indicate an error if the first difference and the second difference differ from one another by at least one predefined threshold value.
A light beam deflection system is configured to transmit a light beam at an output deflection angle that changes over time. The system includes a first resonant structure configured to oscillate about a first rotation axis at first resonant frequency; a second resonant structure configured to oscillate about a second rotation axis at a second resonant frequency, where the first rotation axis is parallel to the second rotation axis, and where the first resonant frequency and the second resonant frequency are different and define a predetermined frequency difference; and a driver circuit configured to generate a first driving signal to drive the first resonant structure while further generating a second driving signal to drive the second resonant structure such that the output deflection angle of the light beam oscillates according to a beat pattern of a beat wave whose extrema amplitudes are modulated and defined by a periodic envelope.
G02B 26/08 - Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
G01S 7/481 - Constructional features, e.g. arrangements of optical elements
G01S 17/34 - Systems determining position data of a target for measuring distance only using transmission of continuous waves, whether amplitude-, frequency-, or phase-modulated, or unmodulated using transmission of continuous, frequency-modulated waves while heterodyning the received signal, or a signal derived therefrom, with a locally-generated signal related to the contemporaneously transmitted signal
81.
VERTICAL POWER SEMICONDUCTOR DEVICE INCLUDING A SENSOR ELECTRODE
A vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having opposite first and second surfaces. The SiC semiconductor body includes a transistor cell area including gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a sensor electrode and a first interlayer dielectric having a first interface to the sensor electrode and a second interface to at least one of the gate electrode or the gate interconnection. A conduction band offset at the first interface ranges from 1 eV to 2.5 eV. The vertical power semiconductor device further includes a second interface to at least one of the gate electrode or the gate interconnection. The second interlayer dielectric laterally adjoins to the first interlayer dielectric.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
G01R 19/165 - Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/082 - Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
82.
CONSUMING DEVICE AND METHOD FOR AUTHENTICATING A CONSUMABLE COMPONENT
In accordance with one embodiment, a consuming device is provided, comprising a power supply for an authentication chip of a consumable component, wherein the internal resistance of the power supply is variable, a detection device configured to capture information about an operating state of the authentication chip for a plurality of values of the internal resistance of the power supply and to determine a dependence of the operating state of the authentication chip on the internal resistance of the power supply, and an authentication circuit configured to authorize the use of the consumable component by the consuming device based on the determined dependence.
G06F 1/28 - Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
G06F 21/75 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation, e.g. to counteract reverse engineering
83.
COIL SENSOR CIRCUIT AND METHOD FOR OPERATING A COIL SENSOR CIRCUIT
The present disclosure proposes a coil sensor circuit including a sensor coil configured to provide an AC sensor signal, a feedforward amplifier stage configured to amplify the AC sensor signal to obtain an amplified sensor signal, a feedback amplifier stage coupled between an output and an input of the feedforward amplifier stage and configured to provide a control signal for cancelling a DC offset of the feedforward amplifier stage, and a switching circuit The switching circuit is configured to, during a first operational mode of the coil sensor circuit, couple the sensor coil to the input of the feedforward amplifier stage, and, during a second operational mode of the coil sensor circuit, decouple the sensor coil from the feedforward amplifier stage, and increase a gain of the coil sensor circuit with respect to the first operational mode.
G01R 15/18 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using inductive devices, e.g. transformers
H03H 7/06 - Frequency selective two-port networks including resistors
84.
FIELD EFFECT TRANSISTOR HAVING AN ELECTRODE TRENCH STRUCTURE
A FET includes a semiconductor substrate having a mesa arranged between an electrode trench structure along a first lateral direction. A groove contact extends into the mesa from a top surface of the mesa. A bottom of the groove contact is located at a first vertical reference level. The mesa includes a source region, a body structure, and a drift region. A pn junction between the drift region and body structure has a minimum vertical distance to the mesa top surface at a second vertical reference level and a maximum vertical distance to the mesa top surface at a third vertical reference level. At a fourth vertical reference level between the second and first vertical reference levels, a doping concentration of the body structure increases by a factor of 5 to 100 along the first lateral direction from the electrode trench structure towards the mesa center. The first vertical distance is by a factor of 1.5 to 10 larger than a second vertical distance from the fourth to the second vertical reference level.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
In accordance with an embodiment, a device includes: a first supply rail; a second supply rail; an input/output terminal; an electrostatic discharge protection device comprising at least two stacked transistors coupled between the input/output terminal and a first one of the first supply rail or the second supply rail; and a trigger circuit coupled to the first supply rail and the second supply rail and configured to: detect an electrostatic discharge event at the input/output terminal based on a voltage of the first supply rail or a voltage of the second supply rail, and switch on the electrostatic discharge protection device in response to detecting the electrostatic discharge event.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Artificial intelligence and machine learning software;
encryption software; firmware and device drivers; cloud
computing software; software development kit [SDK]; software
development kits [SDK]; data processing apparatus;
semiconductor devices; integrated circuits; circuit boards;
microcontrollers; microprocessors; smart cards [integrated
circuit cards]; radio-frequency identification (RFID) tags;
radio-frequency identification (RFID) readers; Internet of
things [IoT] sensors; computer hardware modules for use with
the Internet of things [IoT]; computer application software
for use in implementing the Internet of things [IoT]; speech
analytics software; cryptography software; operating
software; security software; sound processors. Artificial intelligence consultancy; research in the field
of artificial intelligence; platforms for artificial
intelligence as software as a service [SaaS]; software as a
service [SaaS] services featuring software for machine
learning, deep learning and deep neural networks; cloud
computing; consulting services in the field of cloud
computing; design and development of computer hardware and
software; computer and software consultancy services.
A method for assigning an address to an electronic device is described. The method may comprise starting a test system for performing a test of a circuit arrangement comprising the electronic device, and implementing a communication protocol between the circuit arrangement and the test system. The method may also comprise reading out a predetermined unique identifier (UID) of the electronic device by using the test system, assigning the UID to at least one property of the electronic device within a lookup table, wherein the property is determined by using the test system, and assigning an address to the electronic device by using the lookup table.
A carrier for a leadless package is disclosed. In one example, the carrier comprises a component mounting structure for mounting an electronic component thereon, and a plurality of leads arranged around at least part of the component mounting structure, wherein corner leads of said leads are located closer to at least one corner of said component mounting structure than intermediate leads of said leads located farther away from said at least one corner than said corner leads, wherein said corner leads have a larger width along a respective edge of the component mounting structure compared with a smaller width of said intermediate leads, and wherein at least said corner leads comprise a lead tip inspection feature.
A digital microphone includes an analog-to-digital converter (ADC) and a digital filter system coupled to the ADC, wherein the digital filter system switches between a standard IIR filter architecture and a polyphase IIR filter architecture.
In accordance with an embodiment, a circuit includes: a battery monitoring circuit configured to monitor a positive supply voltage and a negative supply voltage with respect to a neutral node; an inverter configured to provide a plurality of modulated phase voltages representing a reference voltage vector; and a space vector modulator configured to generate modulated drive signals for the inverter based on the reference voltage vector, where duty cycles of the modulated drive signals depend on the monitored positive supply voltage and the monitored negative supply voltage.
H02M 7/5395 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency by pulse-width modulation
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A digital microphone includes a logarithmic amplifier; an analog-to-digital converter (ADC) coupled to the logarithmic amplifier; a digital decompression component coupled to the ADC; and a digital filter coupled to the digital decompression component, wherein the digital filter includes a controlled upsampling component coupled to an input of the digital filter and a controlled downsampling component coupled to an output of the digital filter.
This disclosure describes a driver circuit configured to control a gate injection transistor (GIT). The driver circuit is configured to output a control current to a gate of the GIT, detect a voltage at the gate of the GIT, and determine a load current through the GIT based on the voltage detected at the gate of the GIT. The voltage at the gate of the GIT may be dependent on both the load current and the control current.
In some examples, a method comprises communicating first data between a first circuit and a second circuit via a differential communication channel across a galvanic isolation barrier within a circuit package, wherein the first data is coded via a first coding technique that comprises ON-OFF shift Keying (OOK) with a differential carrier signal. The method also includes communicating second data between the first circuit and the second circuit via the differential communication channel across the galvanic isolation barrier within the circuit package, wherein the second data is coded via a second coding technique comprises differential pulse coding.
In accordance with an embodiment, a method for operating a thermal emitter having an electrically conductive semiconductor section includes: providing during an operational cycle, an activation signal having a first energy level to the electrically conductive semiconductor section of the thermal emitter for emitting infrared (IR) radiation; and providing, during a refresh cycle, a refresh signal having a second energy level to the electrically conductive semiconductor section of the thermal emitter, where the second energy level is different from the first energy level.
H05B 3/14 - Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material the material being non-metallic
B81B 7/02 - Microstructural systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
G01N 21/17 - Systems in which incident light is modified in accordance with the properties of the material investigated
G01N 21/3504 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing gases, e.g. multi-gas analysis
G01N 21/3577 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light for analysing liquids, e.g. polluted water
H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material
95.
DEVICE, METHOD, AND SYSTEM FOR DETERMINING ANGLE OF INCIDENCE
Disclosed herein are devices, systems, and methods for determining an angle of incidence between one of two radio devices located at different locations and each having only a single antenna and a radio transmitter. The method includes exchanging radio signals between the first radio device and the second radio device to determine a distance between the first radio device and the second radio device, between the first radio device and the radio transmitter, and between the second radio device and the radio transmitter. The method also includes determining at least one angle of incidence (AoA) between at least one of the radio devices and the radio transmitter based on the exchanged radio signals.
G01S 3/46 - Systems for determining direction or deviation from predetermined direction using antennas spaced apart and measuring phase or time difference between signals therefrom, i.e. path-difference systems
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
(1) Chips [integrated circuits]; semiconductor devices; authentication software; cloud computing software; computer operating system software; security software; software development kit [SDK]; integrated circuit cards [smart cards]; radio-frequency identification (RFID) tags; internet of things [IoT] sensors; semiconductor chips; semiconductors; microprocessors; microcontrollers; electronic components; wireless transmitting and receiving equipment; integrated circuit modules; transmitters and receivers; electronic navigational and positioning apparatus and instruments; sensors for determining position. (1) Research and development services; software as a service [SaaS]; cloud computing; consulting in the field of cloud computing networks and applications; design and development of computer hardware and software; advisory services relating to computer programming.
09 - Scientific and electric apparatus and instruments
42 - Scientific, technological and industrial services, research and design
Goods & Services
Chips [integrated circuits]; semiconductor devices; authentication software; cloud computing software; computer operating system software; security software; software development kit [SDK]; integrated circuit cards [smart cards]; radio-frequency identification (RFID) tags; internet of things [IoT] sensors; semiconductor chips; semiconductors; microprocessors; microcontrollers; electronic components; wireless transmitting and receiving equipment; integrated circuit modules; transmitters and receivers; electronic navigational and positioning apparatus and instruments; sensors for determining position. Research and development services; software as a service [SaaS]; cloud computing; consulting in the field of cloud computing networks and applications; design and development of computer hardware and software; advisory services relating to computer programming.
98.
TRANSISTOR ARRANGEMENT AND METHOD FOR MEASURING AN ON- RESISTANCE OF A TRANSISTOR ARRANGEMENT
A transistor arrangement is disclosed. The transistor arrangement includes a first transistor device and a second transistor device each including a load path and a control node, and each at least partially integrated in a semiconductor body. The load paths of the first and second transistor devices are connected in parallel. The transistor arrangement further includes a first control pad connected to the control node of the first transistor device through a first resistor, and a second control pad connected to the control node of the second transistor device and connected to the first control pad through a second resistor.
A sensor device contains a magnetic field sensor chip. The magnetic field sensor chip contains a semiconductor substrate having a first surface and a second surface opposite the first surface, a sensor element that is arranged at the first surface and is configured to detect a magnetic field present at the location of the sensor element, and at least one trench extending from at least one of the two surfaces into the semiconductor substrate. The sensor element is spaced laterally from the at least one trench.
A method of operating a microelectromechanical system (MEMS) includes, in a first operational mode, converting an analog output of the MEMS into a first internal data stream and a first external data stream having a first sampling rate; transitioning from the first operational mode to a second operation mode without restarting the MEMS; and in the second operational mode, converting the analog output of the MEMS into a second internal data stream having a second sampling rate different from the first sampling rate, and performing a sampling rate conversion of the second internal data stream to generate a second external data stream.
