Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a carbon-doped silicon-germanium and silicon mini-stack is produced with relatively low defects or crystal imperfections. A multi-layered epitaxial stack containing a plurality of the carbon-doped silicon-germanium and silicon mini-stacks is deposited on a substrate. Each multi-layered epitaxial stack contains a carbon-doped silicon germanium stack and a silicon film. The carbon-doped silicon germanium stack contains a carbon-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. The silicon film contains the silicon bulk layer disposed on the silicon seed layer. In some embodiments, a method for fabricating the epitaxial film stack includes sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form the carbon-doped silicon-germanium and silicon mini-stack during a deposition cycle.
H01L 29/165 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form including two or more of the elements provided for in group in different semiconductor regions
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
The present disclosure provides methods and apparatus that facilitate the formation of high-quality carbon gapfill structures and that address the issues related to conventional carbon gapfill methods. In certain embodiments, the carbon gapfill methods and apparatus described herein include plasma enhanced CVD (PECVD) or flowable CVD (FCVD) processes to gapfill structures with high-quality, and stable carbon films.
A method of processing a substrate. The method including delivering, by an RF generator, an RF signal to a processing volume of a processing chamber through an RF match including a configurable impedance altering element. Measuring in real-time, an electrical characteristic of the RF signal. Determining in real-time, a target electrical characteristic based upon a comparison between a calibrated electrical characteristic value and the measured electrical characteristic, in which the calibrated electrical characteristic value is selected to achieve at least one desired plasma processing parameter result. Adjusting in real-time, a setting of the configurable impedance altering element of the RF match to achieve the target electrical characteristic and maintaining, the target electrical characteristic by controlling the setting of the configurable impedance altering element of the RF match.
Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.
A cluster tool for fabricating substrates includes a factory interface; a first processing mainframe coupled to the factory interface, including: a processing chamber monolithic structure including four processing chambers in the same housing; four load locks coupled to the processing chamber monolithic structure, each load lock including a heater assembly configured to increase the temperature of a substrate disposed in the load lock; and a swapper assembly disposed between the four load locks and the processing chamber monolithic structure, wherein the swapper assembly includes four swappers, each swapper configured to swap substrates between one processing chamber and one load lock along a linear trajectory.
B65G 47/26 - Devices influencing the relative position or the attitude of articles during transit by conveyors arranging the articles, e.g. varying spacing between individual articles
B65G 47/90 - Devices for picking-up and depositing articles or materials
H02N 13/00 - Clutches or holding devices using electrostatic attraction, e.g. using Johnson-Rahbek effect
6.
LOW RESISTIVITY METAL STACKS AND METHODS OF DEPOSITING THE SAME
Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a tungsten (W) layer on the semiconductor substrate and depositing a molybdenum (Mo) layer on the tungsten (W) layer. In one method, a tungsten (W) capping layer is deposited on the molybdenum (Mo) layer, followed by formation of a nitride capping layer on the tungsten (W) capping layer). In a second method, a nitride capping layer is formed on the molybdenum (Mo) layer using an ammonia free process. Both processes result in the formation of a metal stack having low resistivity.
An evaporation source arrangement for depositing at least two layers onto a substrate is described. The evaporation source arrangement (100) includes an evaporation source (101) including a first vapor distribution pipe (110) with a first row of nozzles (111) that have a first main evaporation direction (M1) for depositing a first material onto the substrate, a second vapor distribution pipe (120) with a second row of nozzles (121) that have a second main evaporation direction (M2) for depositing a second material onto the substrate, and a third vapor distribution pipe (130) with a third row of nozzles (131) that have a third main evaporation direction (M3) for depositing a third material onto the substrate. The evaporation source arrangement further includes a rotation drive (113) for rotating the evaporation source around a rotation axis. The first main evaporation direction (M1) and the second main evaporation direction (M2) are tilted toward each other to enable a co-deposition of a mixed material layer onto the substrate, and the third row of nozzles is configured to simultaneously deposit a further layer comprising the third material above or below the mixed material layer onto the substrate.
C23C 14/56 - Apparatus specially adapted for continuous coatingArrangements for maintaining the vacuum, e.g. vacuum locks
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
8.
EVAPORATION SOURCE ARRANGEMENT, VACUUM DEPOSITION SYSTEM, AND METHOD OF COATING A SUBSTRATE
An evaporation source arrangement for coating a substrate is described. The evaporation source arrangement includes an evaporation source (101) with a first vapor distribution pipe (110) with a first row of nozzles (111) for depositing a first material on the substrate; a rotation drive (113) for rotating the evaporation source around a rotation axis (R1); and a shield arrangement (200) that partially surrounds the evaporation source and includes an idle shield (202) and a shaper shield (201). The rotation drive is configured to rotate the evaporation source relative to the shield arrangement between an idle position, in which the first row of nozzles is directed toward the idle shield (202), and a first deposition position, in which the first row of nozzles is aligned with a first slit (211) provided in the shaper shield (201), the first slit (211) configured to limit a first opening angle (β1) of vapor plumes emitted by the first row of nozzles. Further described are a vacuum deposition system and methods of coating a substrate.
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
C23C 14/56 - Apparatus specially adapted for continuous coatingArrangements for maintaining the vacuum, e.g. vacuum locks
Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
Embodiments of the disclosure provided herein include an apparatus and method for processing a substrate which may be used to clean the surface of a substrate. The apparatus includes a cleaning module. The cleaning module includes a tank, a processing fluid delivery system configured to deliver a processing fluid includes ozone to the tank, a drain disposed at a bottom of the tank, and an exhaust system disposed at a top of the tank. The processing fluid delivery system includes a front side spray bar port coupled to a front side spray bar located within the tank, and a back side spray bar port coupled to a back side spray bar located within the tank opposite the front side spray bar.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H01L 21/18 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
12.
METHODS FOR TREATMENT OF HIGH-K MATERIALS TO REDUCE LEAKAGE CURRENT AND INCREASE CAPACITANCE
Implementations described herein relate to systems and methods treating high-k materials for use in forming MIM capacitors. Including various high-density plasma nitridation processes or combinations of high-density plasma oxidation processes and high-density plasma nitridation processes are provided.
Disclosed herein are a plasma source, an abatement unit, and a method for detecting a coolant leak. The plasma source includes an RF generation system coupled with a cooling system. The RF generation system includes one or more electrical components comprising a hollow RF antenna for generating a plasma. The cooling system includes a coolant channel extending through the plasma source, including the electrical components of the RF generation system; a first flow control device coupled to the coolant channel to control a flow of the coolant into the coolant channel and electrically isolated from the hollow antenna; a second flow control device coupled to the coolant channel to control a flow of the coolant out of the coolant channel; and a pressure measurement device coupled with the coolant channel to measure a pressure level of the coolant. The coolant channel includes the hollow RF antenna.
Systems and methods for manufacturing energy storage devices are provided. In one or more implementations, which can be combined with other implementations, a temperature control fluid, for example, liquid electrolyte, inert liquified gas, gas, air, cooled gas, or chilled liquid spray, is used to actively cool the anode material. The temperature control fluid can be refrigerated to provide additional cooling benefit. The temperature control fluid can be selected from any liquid electrolyte compatible with the battery or the liquid electrolyte itself. The temperature control fluid can be applied before, during, or after a substrate independent direct transfer process to moderate the temperature of the web.
Embodiments of the disclosure relate to a substrate processing system with improved thermal management. The substrate processing system utilizes a pyrometer for temperature measurement on the outer surface of a chamber body, and a controller to adjust operations based on estimated temperatures at various locations on the inner surface of a chamber body. The system employs a digital twin model, potentially physics-based, data-based, or a hybrid, to simulate process runs and generate temperature mappings inside the chamber body. The chamber structure features a chamber body made from high IR transmission materials and includes a chamber conditioning assembly with variable speed blowers and mechanical flow modulators. The associated method manipulates the system with the digital twin model and the chamber conditioning assembly for enhanced temperature control. Furthermore, an apparatus is presented, equipped with mechanical flow modulators directing air flows for effective thermal regulation, migrating unwanted window coating.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/52 - Controlling or regulating the coating process
09 - Scientific and electric apparatus and instruments
Goods & Services
Semiconductor manufacturing machines used for digital
lithography-based patterning. Recorded software for use in the semiconductor manufacturing
industry, namely, software for digital lithography-based
patterning.
17.
VIA SHAPING BETWEEN METAL LAYERS FOR CONTROLLED RESISTANCE
This disclosure describes structures and methods for forming tapered vias between features in metal layers in semiconductor devices. Instead of straight vias that have 90° vertical sidewalls and a constant cross-sectional area throughout the height of the via, tapered vias may be formed that extend outward from one metal layer to a lower metal layer. The via may be allowed to expand in size in a direction parallel to the feature in the lower metal layer, while remaining a constant width so as not to expand beyond the footprint of the lower feature. This tapered shape results in a larger cross-sectional area at the interface between the via and the lower feature. This lowers the resistance of the via by increasing area for current flow, while also increasing the area of any liners which typically have higher resistances.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
Semiconductor processing chambers and systems, as well as methods of cleaning such chambers and systems are provided. Processing chambers and systems include a chamber body that defines a processing region, a liner positioned within the chamber body that defines a liner volume, a faceplate positioned atop the liner, a substrate support disposed within the chamber body, and a cleaning gas source coupled with the liner volume through a cleaning gas plenum and one or more inlet apertures. Systems and chambers include where at least one of the one or more inlet apertures is disposed in the processing region between the faceplate and a bottom wall of the chamber body.
Embodiments herein are directed to localized stress modulation by implanting a first side of a substrate to reduce in-plane distortion along a second side of the substrate. In some embodiments, a method may include providing a substrate, the substrate comprising a first main side opposite a second main side, wherein a plurality of features are disposed on the first main side, performing a metrology scan to the first main side to determine an amount of distortion to the substrate due to the formation of the plurality of features, and depositing a stress compensation film along the second main side of the substrate, wherein a stress and a thickness of the stress compensation film is determined based on the amount of distortion to the substrate. The method may further include directing ions to the stress compensation film in an ion implant procedure.
H01J 37/147 - Arrangements for directing or deflecting the discharge along a desired path
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H01L 21/66 - Testing or measuring during manufacture or treatment
Embodiments described herein relate to a device. The device includes a substrate, overhang structures disposed over the substrate, and a plurality of sub-pixels. Each overhang structure has a second structure disposed over a first structure. The second structure has an overhang extension extending laterally past the first structure. The first structure includes a first sidewall opposing a second sidewall. The first sidewall and the second sidewall are connected to each other. The plurality of sub-pixels each include an organic light-emitting diode (OLED) material, and a cathode disposed over the OLED material. The cathode extends under the overhang extension such that the cathode contacts the first sidewall and the second sidewall of the first structure under the overhang extension.
A dual-channel showerhead may include a first plate defining two or more channels and a second plate including a bottom surface and defining a plurality of apertures. Each of the two or more channels may be fluidly coupled with one of the plurality of apertures to define a fluid path extending from the first plate through the bottom surface. The plurality of apertures may be arranged in a series of rings. A first subset of apertures of the plurality of apertures may extend through the first plate and the bottom surface. A second subset of apertures in a first ring of the series of rings may include a first opening area. Each aperture of the second subset in a second ring may include a second opening area smaller than the first opening area, such that a flow conductance of the first ring is within 5% of the second ring.
B05B 1/20 - Perforated pipes or troughs, e.g. spray boomsOutlet elements therefor
B05B 1/30 - Nozzles, spray heads or other outlets, with or without auxiliary devices such as valves, heating means designed to control volume of flow, e.g. with adjustable passages
22.
MULTI-PARAMETER IMPLANTATION FOR MANAGING WAFER DISTORTION
A a method of stress management in a substrate. The method may include providing a stress compensation layer on a main surface of the substrate; and performing a chained implant procedure to implant a set of ions into the stress compensation layer. The chained implant procedure may include directing a first implant procedure to the substrate, the first implant procedure generating a first damage profile within the stress compensation layer; directing a second implant to the substrate, different from the first implant, wherein a composite damage profile is generated within the stress compensation layer after the second implant, the composite damage profile resulting in a higher stress response ratio than the first damage profile.
H01J 37/24 - Circuit arrangements not adapted to a particular application of the tube and not otherwise provided for
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
23.
N-CHANNEL COUPLED WITH P-CHANNEL AND METHODS OF MANUFACTURE
Logic devices and methods of manufacturing logic devices are provided. The semiconductor logic device includes an n-channel gate-all-around (n-GAA) field-effect transistor on a substrate integrated with a p-channel gate-all-around (p-GAA) field-effect transistor on the substrate adjacent to the n-channel gate-all-around (p-GAA) field-effect transistor. The n-channel gate-all-around (n-GAA) field effect-transistor has a structure including a plurality of layers comprising silicon and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs extending between a source region and a drain region, and the p-channel gate-all-around (p-GAA) field-effect transistor has a plurality of layers comprising in a range of from 5% to 15% germanium and a corresponding plurality of layers comprising at least 25% germanium alternatingly arranged in stacked pairs.
Techniques to dynamically tune components of an ion implanter are described. A method includes generating a first histogram for a first setting parameter of an ion implanter and a second histogram for a second setting parameter of the ion implanter. The histograms comprise a graphical representation of a distribution of data points across a range of values for each setting parameter. The method includes presenting the histograms on a user interface, receiving a control directive to modify a first range of values for the first setting parameter, predicting a modification to a second range of values for the second setting parameter based on the modification to the first range of values by a machine learning model, and presenting the second histogram for the second setting parameter to indicate the modification to the second range of values for the second setting parameter. Other embodiments are described and claimed.
H01J 37/04 - Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
25.
DIAGNOSTIC TOOL TO TOOL MATCHING AND COMPARATIVE DRILL-DOWN ANALYSIS METHODS FOR MANUFACTURING EQUIPMENT
A method includes receiving first data associated with measurements taken by a sensor during a first manufacturing procedure of a manufacturing chamber. The method further includes receiving second data. The second data includes reference data associated with the first data. The method further includes providing the first and second data to a comparison model. The method further includes receiving a similarity score from the comparison model, associated with the first and second data. The method further includes performance of a corrective action in view of the similarity score.
An RF resonator cavity that includes a resonator coil is disclosed. Unlike traditional RF resonator cavities, no sulfur hexafluoride is used in this cavity. Rather, the volume of the RF resonator cavity is pumped to vacuum conditions. This may be done using a vacuum system, or by hermetically sealing the cavity. This approach eliminates the use of a potent greenhouse gas, while maintaining the integrity of the cavity. Specifically, the dielectric strength of the vacuum is greater than that of sulfur hexafluoride. This RF resonator cavity may be deployed in a linear accelerator used to implant ions into a workpiece.
A method of stress management in a substrate. The method may include comprising providing a stress compensation layer on a main surface of the substrate; and performing a dynamic implant procedure in an ion implanter to implant a set of ions into the stress compensation layer. The dynamic implant procedure may include exposing the substrate to an ion beam under a first set of conditions, the first set of conditions comprising an ion energy, a beam scan rate and a substrate scan rate; and varying at least the ion energy while the substrate is exposed to the ion beam. As such, a stress state of the substrate may change as a function of location on the substrate as a result of the dynamic implant.
H01J 37/317 - Electron-beam or ion-beam tubes for localised treatment of objects for changing properties of the objects or for applying thin layers thereon, e.g. ion implantation
H01J 37/304 - Controlling tubes by information coming from the objects, e.g. correction signals
A method for estimating pressure values within a processing chamber is provided. The method can include receiving a measurement of a pressure at a terminal end of an exit flow path from a processing chamber, and processing the measurement of the pressure using a model including conductance values for a plurality of segments of the exit flow path to estimate one or more pressure values within the processing chamber.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
29.
CONDUIT, SYSTEMS AND METHODS FOR FLUID TEMPERATURE CONTROL
Chemical deliver conduits, systems for substrate processing and methods for supplying a chemical to a substrate processing chamber are described. The conduit has a length and connects a vessel containing the chemical to the substrate processing chamber. The conduit comprises an outer channel surrounding an inner channel. The outer channel is in fluid communication with source of a heat transfer fluid, and the inner channel is in fluid communication with the vessel containing the chemical.
Embodiments of the disclosure provided herein include an apparatus and method for processing a substrate which may be used to clean the surface of a substrate. The apparatus includes a cleaning module. The cleaning module includes a tank, a processing fluid delivery system configured to deliver a processing fluid includes ozone to the tank, a drain disposed at a bottom of the tank, and an exhaust system disposed at a top of the tank. The processing fluid delivery system includes a front side spray bar port coupled to a front side spray bar located within the tank, and a back side spray bar port coupled to a back side spray bar located within the tank opposite the front side spray bar.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of coating a substrate (10) in a vacuum chamber is described. The substrate has a structure formed thereon comprising a first sidewall (11) adjacent to a pixel region (13) and a first overhang (12) projecting from the first sidewall (11) partially over the pixel region (13). The method includes arranging a first evaporation source (101) in a first deposition position, the first evaporation source having a first vapor distribution pipe (110) with a first row of nozzles (111) that have a first main evaporation direction (M1); and transporting the substrate (10) past the first evaporation source (101) while directing a first material toward the substrate from the first row of nozzles (111). In the first deposition position, the first main evaporation direction (M1) is tilted relative to a surface normal (SN) of the substrate by a first tilt angle (α1) to either increase or decrease a deposition of the first material under the first overhang (12). Material layers of an OLED layer stack can be deposited on the substrate.
C23C 14/56 - Apparatus specially adapted for continuous coatingArrangements for maintaining the vacuum, e.g. vacuum locks
C23C 14/22 - Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
32.
CONDUIT, SYSTEMS AND METHODS FOR FLUID TEMPERATURE CONTROL
Chemical deliver conduits, systems for substrate processing and methods for supplying a chemical to a substrate processing chamber are described. The conduit has a length and connects a vessel containing the chemical to the substrate processing chamber. The conduit comprises an outer channel surrounding an inner channel. The outer channel is in fluid communication with source of a heat transfer fluid, and the inner channel is in fluid communication with the vessel containing the chemical.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
33.
IMPROVED SELECTIVITY OF BORON HARD MASKS USING ION IMPLANT
Thicker hardmasks are typically needed for etching deeper capacitor holes in a DRAM structure. Instead of increasing the hardmask thickness, hardmasks may instead be formed with an increased etch selectivity relative to the underlying semiconductor structure. For example, boron-based hardmasks may be formed that include a relatively high percentage of boron (e.g., greater than 90%). The etch selectivity of the hardmask may be improved by performing an ion implant process using different types of ions. The ion implant may take place before or after opening the hardmask with the pattern for the DRAM capacitor holes. Some designs may also tilt the semiconductor substrate relative to the ion implant process and rotate the substrate to provide greater ion penetration throughout a depth of the openings in the hardmask.
Embodiments of the present disclosure generally relate to epitaxial film stacks and vapor deposition processes for preparing the epitaxial film stacks. In one or more embodiments, a carbon-doped silicon-germanium and silicon mini-stack is produced with relatively low defects or crystal imperfections. A multi-layered epitaxial stack containing a plurality of the carbon-doped silicon-germanium and silicon mini-stacks is deposited on a substrate. Each multi-layered epitaxial stack contains a carbon- doped silicon germanium stack and a silicon film. The carbon-doped silicon germanium stack contains a carbon-silicon-germanium layer disposed between a first silicon-germanium layer and a second silicon-germanium layer. The silicon film contains the silicon bulk layer disposed on the silicon seed layer, In some embodiments, a method for fabricating the epitaxial film stack includes sequentially depositing a carbon-doped silicon germanium stack and a silicon film to form the carbon-doped silicon-germanium and silicon mini-stack during a deposition cycle.
A method of processing a substrate. The method including delivering, by an RF generator, an RF signal to a processing volume of a processing chamber through an RF match including a configurable impedance altering element. Measuring in real¬ time, an electrical characteristic of the RF signal. Determining in real-time, a target electrical characteristic based upon a comparison between a calibrated electrical characteristic value and the measured electrical characteristic, in which the calibrated electrical characteristic value is selected to achieve at least one desired plasma processing parameter result. Adjusting in real-time, a setting of the configurable impedance altering element of the RF match to achieve the target electrical characteristic and maintaining, the target electrical characteristic by controlling the setting of the configurable impedance altering element of the RF match.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
A method for estimating pressure values within a processing chamber is provided. The method can include receiving a measurement of a pressure at a terminal end of an exit flow path from a processing chamber, and processing the measurement of the pressure using a model including conductance values for a plurality of segments of the exit flow path to estimate one or more pressure values within the processing chamber.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 21/324 - Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
38.
DUAL CHANNEL SHOWERHEAD CONDUCTANCE OPTIMIZATION FOR UNIFORM RADIAL FLOW DISTRIBUTION
A dual-channel showerhead may include a first plate defining two or more channels and a second plate including a bottom surface and defining a plurality of apertures. Each of the two or more channels may be fluidly coupled with one of the plurality of apertures to define a fluid path extending from the first plate through the bottom surface. The plurality of apertures may be arranged in a series of rings. A first subset of apertures of the plurality of apertures may extend through the first plate and the bottom surface. A second subset of apertures in a first ring of the series of rings may include a first opening area. Each aperture of the second subset in a second ring may include a second opening area smaller than the first opening area, such that a flow conductance of the first ring is within 5% of the second ring.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
39.
A HIGH THROUGHPUT SUBSTRATE PROCESSING CLUSTER TOOL
A cluster tool for fabricating substrates includes a factory interface; a first processing mainframe coupled to the factory interface, including: a processing chamber monolithic structure including four processing chambers in the same housing; four load locks coupled to the processing chamber monolithic structure, each load lock including a heater assembly configured to increase the temperature of a substrate disposed in the load lock; and a swapper assembly disposed between the four load locks and the processing chamber monolithic structure, wherein the swapper assembly includes four swappers, each swapper configured to swap substrates between one processing chamber and one load lock along a linear trajectory.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
The present disclosure provides methods and apparatus that facilitate the formation of high-quality carbon gapfill structures and that address the issues related to conventional carbon gapfill methods. In certain embodiments, the carbon gapfill methods and apparatus described herein include plasma enhanced CVD (PECVD) or flowable CVD (FCVD) processes to gapfill structures with high-quality,, and stable carbon films.
C23C 16/509 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
The present disclosure generally relates to semiconductor processing and, in particular, provides methods of forming a resist underlayer on a substrate for use in EUV lithography processing. In an embodiment, the method includes flowing a precursor gas mixture into the processing region of the process chamber, applying a pulsed RF power to the precursor gas mixture to generate a plasma in the processing region, depositing a resist underlayer on the substrate with the plasma generated from the pulsed RF power, and forming a patterned chemically amplified photoresist (CAR) over the resist underlayer.
G03F 7/11 - Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
A method and apparatus for processing a thin film are provided. An example method includes disposing a first carrier on a base stage; disposing a first portion of the thin film above the first carrier; raising the base stage such that the first carrier contacts the thin film; chucking the first portion of the thin film to the first carrier; and cutting the first portion of the thin film away from a second portion of the thin film.
A method includes receiving, by a processing device, a first small angle scattering image of a substrate. The substrate includes a number of structures oriented at a first angle relative to a base of the substrate. The first small angle scattering image of the substrate is collected at a second angle of incidence of radiation relative to the base of the substrate, different than the first angle. The method further includes determining a first-order Fourier term associated with the first small angle scattering image by performing angular Fourier decomposition of the first small angle scattering image. The method further includes determining a value of the first angle based on the first-order Fourier term.
Exemplary substrate processing methods are described. The methods may include providing a scandium-doped aluminum nitride layer on a metal layer. They may further include etching a portion of the scandium-doped aluminum nitride layer with an etching composition. The etching composition may include greater than or about 80 wt. % phosphoric acid. The compositions may further be characterized by a temperature of greater than or about 90° C. during etching.
The present disclosure relates to pre-heat rings including carbon heaters, and related heating systems, methods and processing chambers for semiconductor manufacturing. In one or more embodiments, a pre-heat ring applicable for use in semiconductor manufacturing includes a ring structure, and a carbon heater coupled to the ring structure. The carbon heater has a carbon content that is at least 99% by atomic percentage.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
F27B 17/00 - Furnaces of a kind not covered by any of groups
H05B 3/14 - Heating elements characterised by the composition or nature of the materials or by the arrangement of the conductor characterised by the composition or nature of the conductive material the material being non-metallic
H05B 3/28 - Heating elements having extended surface area substantially in a two-dimensional plane, e.g. plate-heater non-flexible heating conductor embedded in insulating material
47.
FIN STRUCTURES, PLATE APPARATUS, AND RELATED METHODS, PROCESS KITS, AND PROCESSING CHAMBERS FOR GROWTH RATES AND PROCESS UNIFORMITY
The present disclosure relates to semiconductor processing chambers, and more particularly, to fin structures that facilitate growth rates and process uniformity. In one or more embodiments, a processing chamber applicable for use in semiconductor manufacturing includes one or more gas inlets operable to flow a gas into an internal volume of the processing chamber and a substrate support disposed in the internal volume. The processing chamber includes a plate apparatus disposed in the internal volume and above the substrate support. The plate apparatus includes a plate, and one or more fins disposed at least partially below the plate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
48.
MULTIZONE REFLECTOR FOR TEMPERATURE PLANAR NON-UNIFORMITY
Vapor deposition processing chamber temperature control apparatus and vapor deposition processing chambers incorporating the temperature control apparatus are described. The temperature control apparatus has a base plate with a plurality of reflectors arranged in at least two annular zones, each annular zone separated into at least two sector zones. The reflectors are configured to decrease a specific side-to-side temperature non-uniformity profile of a heated substrate support positioned above the base plate in the vapor deposition processing chamber.
The present disclosure relates to lift pins that include an opening, and related components and chamber kits, for disposition in processing chambers for semiconductor manufacturing. In one or more embodiments, a processing chamber applicable for use in semiconductor manufacturing includes a chamber body and a window. The processing chamber includes one or more heat sources, a substrate support, and a plurality of lift pins disposed in a processing volume. The plurality of lift pins respectively include a shaft section having a first outer dimension, a head section having a second outer dimension, and an opening formed in the shaft section. The opening has a dimension that is a first ratio that is at least 0.3 of the first outer dimension of the shaft section. The dimension of the opening is a second ratio that is at least 0.2 of the second outer dimension of the head section.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
50.
VIRTUAL METROLOGY FOR ENHANCED WINDOW TEMPERATURE CONTROL
Embodiments of the disclosure relate to a substrate processing system with improved thermal management. The substrate processing system utilizes a pyrometer for temperature measurement on the outer surface of a chamber body, and a controller to adjust operations based on estimated temperatures at various locations on the inner surface of a chamber body. The system employs a digital twin model, potentially physics-based, data-based, or a hybrid, to simulate process runs and generate temperature mappings inside the chamber body. The chamber structure features a chamber body made from high IR transmission materials and includes a chamber conditioning assembly with variable speed blowers and mechanical flow modulators. The associated method manipulates the system with the digital twin model and the chamber conditioning assembly for enhanced temperature control. Furthermore, an apparatus is presented, equipped with mechanical flow modulators directing air flows for effective thermal regulation, migrating unwanted window coating.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/66 - Testing or measuring during manufacture or treatment
51.
METHODS FOR TREATMENT OF HIGH-K MATERIALS TO REDUCE LEAKAGE CURRENT AND INCREASE CAPACITANCE
Implementations described herein relate to systems and methods treating high-k materials for use in forming MIM capacitors. Including various high-density plasma nitridation processes or combinations of high-density plasma oxidation processes and high-density plasma nitridation processes are provided.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
The present disclosure generally relates to semiconductor processing and, in particular, provides methods of forming a resist underlayer on a substrate for use in EUV lithography processing. In an embodiment, the method includes flowing a precursor gas mixture into the processing region of the process chamber, applying a pulsed RF power to the precursor gas mixture to generate a plasma in the processing region, depositing a resist underlayer on the substrate with the plasma generated from the pulsed RF power, and forming a patterned chemically amplified photoresist (CAR) over the resist underlayer.
The present disclosure relates to semiconductor processing chambers, and more particularly, to fin structures that facilitate growth rates and process uniformity. In one or more embodiments, a processing chamber applicable for use in semiconductor manufacturing includes one or more gas inlets operable to flow a gas into an internal volume of the processing chamber and a substrate support disposed in the internal volume. The processing chamber includes a plate apparatus disposed in the internal volume and above the substrate support. The plate apparatus includes a plate, and one or more fins disposed at least partially below the plate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/20 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
A showerhead for a process chamber is provided including: a first portion that includes a plurality of gas inlets and a first plurality of gas outlets; and a second portion over the first portion, the second portion including a second plurality of gas outlets, wherein the plurality of gas inlets of the first portion are fluidly coupled to the second plurality of gas outlets of the second portion, the first plurality of gas outlets of the first portion are fluidly coupled to the plurality of gas inlets of the first portion, the second portion is transparent to infrared radiation and ultraviolet radiation, and the first portion is transparent to infrared radiation and opaque to ultraviolet radiation.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/48 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
55.
METHODS AND APPARATUS FOR ANISOTROPIC FILM GROWTH, AND RELATED DEVICE
The present disclosure relates to semiconductor processing methods for anisotropic film growth. The method includes heating a substrate positioned in a processing chamber. The method includes flowing one or more process gases over the substrate. The one or more process gases include trichlorosilane (TCS) and a cleaning gas acid. The method includes depositing one or more layers on one or more fins on the substrate. The deposition of the one or more layers includes forming the one or more layers at a first growth rate along a first dimension and a second growth rate along a second dimension, and the second growth rate is faster than the first growth rate.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
56.
PASSIVATION APPARATUS AND METHOD FOR LITHIUM METAL ANODE
A method and apparatus for passivation of alkali metal surfaces are provided. The method includes conveying a web-based substrate through an interior region of a passivation unit, the web-based substrate having a lithium metal film formed thereon. The method further includes exposing a titanium dioxide (TiO2) photocatalyst to UV/LED light in the presence of a CO2 gas or a fluorocarbon (CxFy) gas to generate either CO2 radicals or CxFy radicals. The method further includes exposing the lithium metal film to the CO2 radicals or the CxFy radicals to form a lithium carbonate film or a lithium fluoride film on the lithium metal film.
Vapor deposition processing chamber temperature control apparatus and vapor deposition processing chambers incorporating the temperature control apparatus are described. The temperature control apparatus has a base plate with a plurality of reflectors arranged in at least two annular zones, each annular zone separated into at least two sector zones. The reflectors are configured to decrease a specific side-to-side temperature non-uniformity profile of a heated substrate support positioned above the base plate in the vapor deposition processing chamber.
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
58.
APPARATUS AND METHOD TO ACHIEVE LOW LOSS PVD SINK WITH CMOS BEOL COMPATIBLE THERMAL BUDGET
Embodiments of the present disclosure generally relate to photonics. The disclosure includes tools, photonic devices, device films for photonics devices, and methods of forming a device film. In at least one embodiment, a photonic device includes a substrate, a buried oxide (BOX) layer disposed over the substrate, a device layer disposed over the BOX layer, the device layer comprising at least one device, a cladding disposed over the device layer, and a lens layer disposed over the cladding, the lens layer comprising a microlens aligned with the device. At least one of the BOX layer, the device layer, the cladding, and the lens layer, of the photonic device includes silicon nitride and has a propagation loss of less than about 1.5 dB/cm
A gas cushion drum for enhanced heat extraction is provided. In an embodiment, the gas cushion drum may include a curved cooling drum having a cooling drum surface extending between opposite circular bases, a pair of rotating discs coupled to the circular bases of the curved cooling drum, a set of nozzle outlets disposed along the cooling drum surface and configured to output a gas across the cooling drum surface, and a substrate coupled to a circumferential surface of each of the pair of rotating discs and disposed above the set of nozzles, wherein a substantially uniform gas cushion is formed between an inner surface of the substrate and the cooling drum surface from the gas outputted from the set of nozzle outlets.
A method for testing a packaging substrate with at least one electron beam column is provided. The method includes a first test operation, wherein the first test operation includes: positioning the packaging substrate in a vacuum chamber; connecting a voltage source to one or more first contact pads of a first large network of the packaging substrate, the first large network comprising a first plurality of contact pads having a large number of contact pads, the first large network further comprising first electrical interconnect paths for interconnecting the first plurality of contact pads; applying a first electric potential to the one or more first contact pads using the voltage source; charging one or more further networks of the packaging substrate to a second electric potential different from the first electric potential, wherein the one or more further networks comprise a further plurality of contact pads; obtaining information about one or more electric potentials of a second plurality of contact pads comprising the further plurality of contact pads, wherein obtaining the information about one or more electric potentials comprises directing an electron beam of the at least one electron beam column via vector addressing onto each of the second plurality of contact pads and obtaining information about an electric potential of each of the second plurality of contact pads; and determining at least one defect of the packaging substrate based on the information about one or more electric potentials of the second plurality of contact pads.
Embodiments of the present disclosure include a thinned device structure and method of forming a thinned device structure. Embodiments of the disclosure provided herein include the use of engineered epitaxial (Epi) layers that are formed on a base substrate. The engineered epitaxial layers include two or more epitaxial layers that each include materials that allow at least one of the two or more epitaxial layers to be selectively removed from the other layer(s). In some embodiments, one of the two or more formed epitaxial layers has etch selectivity (e.g., wet and/or dry etch selectivity) to materials disposed on either side of the formed layer.
A system includes a remote plasma source, a processing chamber comprising a radical sensor, and a controller. The radical sensor is configured to measure the concentration of fluorine radicals in the processing chamber. The controller is to adjust one or more settings of at least one of the remote plasma source or the processing chamber based on the measured concentration of fluorine radicals in the processing chamber.
The present disclosure relates to heaters, and related chamber kits and processing chambers, for semiconductor manufacturing. In one or more embodiments, a chamber kit applicable for semiconductor manufacturing includes a heater and a liner. The heater includes an arcuate heater body including one or more first sections, one or more second sections, and one or more connector sections. The heater includes a first electrode coupled to the arcuate heater body, and a second electrode coupled to the arcuate heater body. The liner includes a ledge sized and shaped to support the arcuate heater body, a first opening sized and shaped to receive at least part of the heater therethrough, and a second opening sized and shaped to receive at least part of the heater therethrough.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H05B 3/62 - Heating elements specially adapted for furnaces
64.
SYSTEM FOR ADJUSTING PROCESS CHAMBER COMPONENT TEMPERATURE
In one or more embodiments, a semiconductor processing kit includes a reflector assembly. The reflector assembly configured to support one or more sensing devices therein. The reflector assembly includes a body having a top surface and a volume at least partially defined by an inner surface and an outer surface. The reflector assembly further includes a baffle and a fluid channel disposed within the baffle. The fluid channel is configured to flow a fluid to adjust a temperature of the one or more sensing devices. A ring is disposed on the top surface. The ring is configured to reduce a flow of a fluid into the volume. A reflector is concentrically disposed radially outward of the outer surface and creates a gap that allows the fluid to partially flow between the inner surface of the reflector and the outer surface.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
This specification describes technologies for creating and coupling word lines of a 3D memory cell array to corresponding word lines of a word line connect area. One aspect is a method that includes positioning a memory cell array on a substrate adjacent to a word line connect area, the word line connect area comprising a plurality of layers, the plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines within the word line connect area and is electrically coupled to memory cell word lines within the memory cell array.
Aspects of the present disclosure relate to apparatus, systems, and methods of using atomic hydrogen radicals with epitaxial deposition. In one aspect, nodular defects (e.g., nodules) are removed from epitaxial layers of substrate. In one implementation, a method of processing substrates includes selectively growing an epitaxial layer on one or more crystalline surfaces of a substrate. The epitaxial layer includes silicon. The method also includes etching the substrate to remove a plurality of nodules from one or more non-crystalline surfaces of the substrate. The etching includes exposing the substrate to atomic hydrogen radicals. The method also includes thermally annealing the epitaxial layer to an anneal temperature that is 600 degrees Celsius or higher.
C30B 35/00 - Apparatus not otherwise provided for, specially adapted for the growth, production or after-treatment of single crystals or of a homogeneous polycrystalline material with defined structure
The present disclosure generally relates to a substrate support that includes a body having a substrate receiving surface, the body comprising a dielectric material. The body also includes a first foil embedded in the body below the substrate receiving surface. The body also includes an electrically conductive mesh embedded in the body below the first foil. The body also includes a center tap structure formed in a bottom surface of the body that is in electrical communication with the mesh.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
Methods of removing molybdenum oxide from a surface of a substrate comprise exposing the substrate having a molybdenum oxide layer on the substrate to a halide etchant having the formula RmSiX4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL) process, and the substrate contains a low-k dielectric material.
The present disclosure relates to an auxiliary flow plate for process kits and semiconductor processing chambers, and related methods and flow guides. In one or more embodiments, a chamber kit includes a liner, a first plate, and a second plate. The liner includes an inner face, a first ledge disposed along the inner face, and a second ledge disposed along the inner face. The second ledge is spaced from the first ledge along the inner face. The first plate is sized and shaped to be disposed within the liner on the first ledge. The second plate is sized and shaped to be disposed within the liner on the second ledge.
A method of capping a metal layer includes performing a conversion process to reduce a metal oxide layer formed on a top surface of the metal layer and form a metal sulfide layer on the top surface of the metal layer, exposing the top surface of the metal layer to an oxidizing environment, and performing a removal process to remove the metal sulfide layer.
A window component, a chamber, and a method of processing substrates are described herein. In one example, a semiconductor process chamber window component comprises a transparent quartz body. The body comprises a top surface, a bottom surface, a central portion disposed near a center axis of the body, and one or more fluid channels formed within the body. The one or more fluid channels are configured to flow a fluid from a first side of the body towards a second side of the body and the first side is disposed opposite the second side.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
72.
METHODS AND APPARATUS FOR ANISOTROPIC FILM GROWTH, AND RELATED DEVICES
The present disclosure relates to semiconductor processing methods for anisotropic film growth. The method includes heating a substrate positioned in a processing chamber. The method includes flowing one or more process gases over the substrate. The one or more process gases include trichlorosilane (TCS) and hydrochloric acid. The method includes depositing one or more layers on one or more fins on the substrate. The deposition of the one or more layers includes forming the one or more layers at a first growth rate along a first dimension and a second growth rate along a second dimension, and the second growth rate is faster than the first growth rate.
H01L 27/088 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
A showerhead for a process chamber is provided including: a first portion that includes a plurality of gas inlets and a first plurality of gas outlets; and a second portion over the first portion, the second portion including a second plurality of gas outlets, wherein the plurality of gas inlets of the first portion are fluidly coupled to the second plurality of gas outlets of the second portion, the first plurality of gas outlets of the first portion are fluidly coupled to the plurality of gas inlets of the first portion, the second portion is transparent to infrared radiation and ultraviolet radiation, and the first portion is transparent to infrared radiation and opaque to ultraviolet radiation.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
74.
PRE-HEAT RINGS, HEATING SYSTEMS, AND PROCESSING CHAMBERS INCLUDING CARBON HEATERS
The present disclosure relates to pre-heat rings including carbon heaters, and related heating systems, methods and processing chambers for semiconductor manufacturing. In one or more embodiments, a pre-heat ring applicable for use in semiconductor manufacturing includes a ring structure, and a carbon heater coupled to the ring structure. The carbon heater has a carbon content that is at least 99% by atomic percentage.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
75.
HEAT TRANSFER JACKETS AND SENSOR ASSEMBLIES, AND RELATED METHODS AND PROCESSING CHAMBERS, FOR SEMICONDUCTOR MANUFACTURING
The present disclosure relates to heat transfer jackets and sensor assemblies, and related methods and processing chambers, for semiconductor manufacturing. In one or more embodiments, a jacket includes one or more outer walls bounding a plurality of fluid channels, and an inner wall at least partially surrounded by at least one of the plurality of fluid channels. The inner wall at least partially defines a receptacle opening. The jacket includes a fluid inlet formed in at least one of the one or more outer walls, a fluid outlet formed in at least one of the one or more outer walls, and a plurality of partition walls separating the plurality of fluid channels. At least one of the plurality of partition walls intersects at least one of the one or more outer walls.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
76.
LIFT PINS INCLUDING OPENING, AND RELATED COMPONENTS AND CHAMBER KITS, FOR PROCESSING CHAMBERS
The present disclosure relates to lift pins that include an opening, and related components and chamber kits, for disposition in processing chambers for semiconductor manufacturing. In one or more embodiments, a processing chamber applicable for use in semiconductor manufacturing includes a chamber body and a window. The processing chamber includes one or more heat sources, a substrate support, and a plurality of lift pins disposed in a processing volume. The plurality of lift pins respectively include a shaft section having a first outer dimension, a head section having a second outer dimension, and an opening formed in the shaft section. The opening has a dimension that is a first ratio that is at least 0.3 of the first outer dimension of the shaft section. The dimension of the opening is a second ratio that is at least 0.2 of the second outer dimension of the head section.
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
77.
APPARATUS AND METHOD OF IN-SITU FILM THICKNESS MEASUREMENT DURING DISPLAY DEPOSITION PROCESS
A processing system herein includes a processing chamber, a metrology system, and a metrology source. The processing chamber includes a lid assembly, a substrate support assembly, a first wall, a second wall, a bottom, and a viewing port. The first wall, the second wall, and the bottom define a processing volume. The metrology system includes a translation stage and a collimator. The metrology source includes a radiation source and a spectrometer. A method herein includes disposing a substrate on a substrate support in a processing chamber; calculating a baseline reflectivity of the substrate; providing a precursor mixture to the processing chamber from the precursor mixture; forming a plasma in a the processing chamber from the precursor mixture; depositing a film on the substrate from the plasma; measuring a thickness of the film; detecting an endpoint of a deposition process; and stopping the deposition process.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
In one embodiment, a flexible substrate processing system is provided comprising: a pickup hub; a lamination unit comprising a first calender roller and a second calender roller; and a drying unit having an interior volume, the pickup hub configured to rotate and assist in conveying a flexible substrate through the interior volume of the drying unit before the flexible substrate passes between the first calender roller and the second calender roller, the drying unit including one or more heating units directed toward the interior volume.
The present disclosure relates to heaters, and related chamber kits and processing chambers, for semiconductor manufacturing. In one or more embodiments, a chamber kit applicable for semiconductor manufacturing includes a heater and a liner. The heater includes an arcuate heater body including one or more first sections, one or more second sections, and one or more connector sections. The heater includes a first electrode coupled to the arcuate heater body, and a second electrode coupled to the arcuate heater body. The liner includes a ledge sized and shaped to support the arcuate heater body, a first opening sized and shaped to receive at least part of the heater therethrough, and a second opening sized and shaped to receive at least part of the heater therethrough.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/46 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for heating the substrate
80.
AUXILIARY FLOW PLATE FOR THICKNESS AND CONCENTRATION UNIFORMITY AND ADJUSTABILITY
The present disclosure relates to an auxiliary flow plate for process kits and semiconductor processing chambers, and related methods and flow guides. In one or more embodiments, a chamber kit includes a liner, a first plate, and a second plate. The liner includes an inner face, a first ledge disposed along the inner face, and a second ledge disposed along the inner face. The second ledge is spaced from the first ledge along the inner face. The first plate is sized and shaped to be disposed within the liner on the first ledge. The second plate is sized and shaped to be disposed within the liner on the second ledge.
m4-m4-m, wherein m is an integer from 1 to 3, X is selected from iodine (I) and bromine (Br) and R is selected from the group consisting of a methyl group, ethyl group, propyl group, butyl group, cyclohexyl group and cyclopentyl group. The methods may be performed in a back-end-of-the line (BEOL) process, and the substrate contains a low-k dielectric material.
In one or more embodiments, a semiconductor processing kit includes a reflector assembly. The reflector assembly configured to support one or more sensing devices therein. The reflector assembly includes a body having a top surface and a volume at least partially defined by an inner surface and an outer surface. The reflector assembly further includes a baffle and a fluid channel disposed within the baffle. The fluid channel is configured to flow a fluid to adjust a temperature of the one or more sensing devices. A ring is disposed on the top surface. The ring is configured to reduce a flow of a fluid into the volume. A reflector is concentrically disposed radially outward of the outer surface and creates a gap that allows the fluid to partially flow between the inner surface of the reflector and the outer surface.
A method for substrate dispatching management at a substrate fabrication facility is provided. The method includes obtaining data about a state of a fabrication facility and providing the data as input to an agent of a predictive subsystem associated with the fabrication facility to obtain one or more outputs indicative of one or more settings of one or more dispatching factors. The one or more dispatching factors comprise a dispatching parameter or ranking order. A dispatching decision is generated using the one or more settings of the one or more dispatching factor and a set of operations on a candidate set of substrates, based on the dispatching decision, is initiated.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
Embodiments of the present disclosure relate to an apparatus for processing a substrate. A processing chamber includes a chamber body. The chamber body includes an upper body, a lower body, a carrier and feed (CF) ring disposed between the upper body and the lower body, an upper liner, a lower liner, and a substrate support. The lower liner includes an upper venting liner. The upper venting liner includes one or more upper vents, and an internal volume. The internal volume includes a processing volume, and a purge volume. The substrate support is disposed within the internal volume. The upper venting liner is disposed below the substrate support.
Embodiments of the present disclosure generally relate to LED pixels and methods of fabricating LED pixels. More specifically, the present disclosure relates to using a release layer to form a color conversion layer separate from a backplane and bonding the color conversion layer to the backplane to form the pixel. The pixel includes a backplane, a plurality of light emitting diodes (LEDs) disposed over the backplane, an adhesive layer disposed at least between each of the LEDs over the backplane, a plurality of sub-pixel isolation (SI) structures, where adjacent SI structures define a well of a sub-pixel such that each well of each sub-pixel includes one LED of the plurality of LEDs, where each LED of the plurality of LEDs is disposed in a second portion of each well, and at least three sub-pixels including a color conversion material in the first portion of each well.
H01L 33/44 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 33/00 - SEMICONDUCTOR DEVICES NOT COVERED BY CLASS - Details thereof
86.
CERAMIC COATED HEAT EXCHANGING DRUM WITH NOZZLES, NON-SEALING AND SEALING MESAS
The present disclosure provides a cooling drum. The cooling drum includes a curved drum surface for supporting a substrate, the curved drum surface, a dielectric portion, a plurality of sealing mesas, a plurality of non-sealing mesas, a plurality of grooves, and a plurality of gas inlets disposed on the plurality of sealing mesas and the plurality of non-sealing mesas.
A system includes a remote plasma source, a processing chamber comprising a radical sensor, and a controller. The radical sensor is configured to measure the concentration of fluorine radicals in the processing chamber. The controller is to adjust one or more settings of at least one of the remote plasma source or the processing chamber based on the measured concentration of fluorine radicals in the processing chamber.
This specification describes technologies for creating and coupling word lines of a 3D memory cell array to corresponding word lines of a word line connect area. One aspect is a method that includes positioning a memory cell array on a substrate adjacent to a word line connect area, the word line connect area comprising a plurality of layers, the plurality of layers alternating between a first material and a second material; replacing at least a portion of the layers of the first material with a third material; and replacing at least a portion of the layers of the second material with a fourth material, wherein the fourth material forms word lines within the word line connect area and is electrically coupled to memory cell word lines within the memory cell array.
09 - Scientific and electric apparatus and instruments
Goods & Services
Optical defect inspection equipment in the nature of an optical microscope used for inspecting and analyzing defects on semiconductor wafers during semiconductor manufacturing
A process chamber including: a chamber body enclosing an interior volume; a substrate support disposed in the interior volume that includes a lower interior volume below the substrate support and an upper interior volume above the substrate support; a first purge gas line configured to provide a first flow of purge gas to the lower interior volume; and a gas flow ring disposed around an outer edge of the substrate support, the gas flow ring comprising: a ring-shaped body; a top surface; a bottom surface; a first overlapping portion extending from a first inner sidewall of the ring-shaped body; and a second overlapping portion extending from a second inner sidewall of the ring-shaped body. The first overlapping portion is spaced apart from and overlies the second overlapping portion to form a gas flow channel that extends from the bottom surface to the top surface of the gas flow ring.
C23C 16/458 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
Exemplary methods and systems of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed within a processing region of a semiconductor processing chamber. Methods may include forming a low quality oxide within one or more of the recesses, where the low quality oxide and a silicon-containing material each contain an exposed surface. Methods include contacting the low quality oxide and the high quality semiconductor material with a passivating agent selective to a surface defect of the low quality oxide. Methods include contacting the substrate with an etching agent and/or a cleaning agent, where the contacting with the cleaning agent removes the high quality semiconductor material at an equal or faster rate than the low quality oxide.
Printable resin precursor compositions and polishing articles including printable resin precursors are provided that are particularly suited for polishing substrates utilized in hybrid bonding applications. Methods and articles may include a plurality of first polishing elements, where at least one of the plurality of first polymer layers forms the polishing surface; and one or more second polishing elements, where at least a region of each of the one or more second polishing elements is disposed between at least one of the plurality of first polishing elements and a supporting surface of the polishing pad. One or more first polishing elements have a Shore D hardness of greater than 60, one or more second polishing elements have a Shore D hardness of from about 20 to less than 60, and the polishing article has a total Shore D hardness of greater than or about 50.
A method for substrate dispatching management at a substrate fabrication facility is provided. The method includes obtaining data about a state of a fabrication facility and providing the data as input to an agent of a predictive subsystem associated with the fabrication facility to obtain one or more outputs indicative of one or more settings of one or more dispatching factors. The one or more dispatching factors comprise a dispatching parameter or ranking order. A dispatching decision is generated using the one or more settings of the one or more dispatching factor and a set of operations on a candidate set of substrates, based on the dispatching decision, is initiated.
G05B 13/02 - Adaptive control systems, i.e. systems automatically adjusting themselves to have a performance which is optimum according to some preassigned criterion electric
95.
HEAT TRANSFER JACKETS AND SENSOR ASSEMBLIES, AND RELATED METHODS AND PROCESSING CHAMBERS, FOR SEMICONDUCTOR MANUFACTURING
The present disclosure relates to heat transfer jackets and sensor assemblies, and related methods and processing chambers, for semiconductor manufacturing. In one or more embodiments, a jacket applicable for semiconductor manufacturing includes one or more outer walls bounding a plurality of fluid channels, and an inner wall at least partially surrounded by at least one of the plurality of fluid channels. The inner wall at least partially defines a receptacle opening. The jacket includes a fluid inlet formed in at least one of the one or more outer walls, a fluid outlet formed in at least one of the one or more outer walls, and a plurality of partition walls separating the plurality of fluid channels. At least one of the plurality of partition walls intersects at least one of the one or more outer walls.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
The methods of the present disclosure enable formation of highly conductive contacts that facilitate in increasing the device speed and lowering the operating voltages of semiconductor devices such as, but not limited to, metal-on-semiconductor (MOS) transistors and the like. In one embodiment, the methods create the optimal contacts, useful in N type or P type MOS devices, by forming metal-insulator-semiconductor (MIS) contact structure or a non-stoichiometric layer contact structure. It is noted that N type or P type contacts require different work function metals to achieve a low Schottky barrier height (SBH).
H01L 21/3205 - Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layersAfter-treatment of these layers
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
97.
SMART FACEPLATE USING SHAPE MEMORY ALLOY POPPET ACTUATORS
Embodiments of the present disclosure relate to a faceplate that implements poppets to vary nozzle cross-sections. In one embodiment, a faceplate is provided. The faceplate includes a body, a plurality of holes in the body, and a plurality of poppet assemblies. The poppet assemblies include a poppet configured to travel in a first portion of the hole and create a variable passage in a second portion of the hole. The poppet assemblies further include a first spring connected to the poppet and operable to move the poppet in a first direction when connected to an electrical power, and a second spring connected to the poppet and operable to move the poppet in a second direction that is opposite the first direction when the electrical power is reduced or terminated.
F03G 7/06 - Mechanical-power-producing mechanisms, not otherwise provided for or using energy sources not otherwise provided for using expansion or contraction of bodies due to heating, cooling, moistening, drying, or the like
Exemplary semiconductor processing systems may include a chamber body including sidewalls and a base. The system may include a substrate support extending through the base of the chamber body. The chamber body may define an access circumferentially extending about the substrate support at the base of the chamber body. The system may include one or more isolators disposed within the chamber body. The one or more isolators may define an exhaust path between the one or more isolators and the chamber body. The exhaust path may extend to the base of the chamber body. The systems may include a fluid source fluidly coupled with the chamber body at the access extending about the substrate support.
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/505 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
99.
METHOD AND SYSTEM FOR DETECTING ANOMALIES IN A SEMICONDUCTOR PROCESSING SYSTEM
The present disclosure relates to systems and methods for detecting anomalies in a semiconductor processing system. According to certain embodiments, one or more external sensors are mounted to a sub-fab component, communicating with the processing system via a communication channel different than a communication channel utilized by the sub-fab component and providing extrinsic sensor data that the sub-fab component is not configured to provide. The extrinsic sensor data may be combined with sensor data from a processing tool of the system and/or intrinsic sensor data of the sub-fab component to form virtual sensor data. In the event the virtual data exceeds or falls below a threshold, an intervention or a maintenance signal is dispatched, and in certain embodiments, an intervention or maintenance action is taken by the system.
Embodiments of the disclosure relate to methods using an oligomer film to protect a substrate surface. The oligomer film is formed on the substrate surface with a first feature and a second feature each having a feature depth. The first feature has a first critical dimension (CD) and the second feature has a second CD. The semiconductor substrate surface is exposed to one or more monomers to form the oligomer film, and the oligomer film forms selectively on the bottom and fills a portion of the feature depth. The oligomer film fills the feature depth to substantially the same or the same height in each of the first feature and the second feature. Methods of forming semiconductor devices using the oligomer film are also disclosed.
