The present disclosure includes apparatuses, methods, and systems for drift compensation for codewords in memory. An embodiment includes a memory device having an array of memory cells, and circuitry to sense a codeword stored in the array, determine a derivative value of a cell metric for each cell of the codeword based on a threshold voltage of that respective cell, a mean of threshold voltage values of each cell of the codeword, and a value proportional to a total quantity of the cells of the codeword and a position of the threshold voltage value of that respective cell in the threshold voltage values of each cell of the codeword, determine the cell metric for which the determined derivative value changes from a first polarity to a second polarity, input the determined cell metric to a Pearson detector, and determine originally programmed data of the codeword using the Pearson detector.
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
Systems, apparatuses, and methods related to an adjustable timer component are described. A memory device includes, a memory controller coupled to the memory device comprising an adjustable timer component. The adjustable timer component is configured to receive a timer generation request and, responsive to receiving the request, store in a cache an active timer entry corresponding to a particular first address, generate a timer corresponding to an active timer entry and the particular first address, and monitor the timer to determine when the timer expires. Responsive to the expiration of the timer, dequeue the timer entry and invalidate the timer entry stored in the cache. The memory device can also include command logic configured to, prior to issuing a second command, query the cache of the adjustable timer component to determine if the cache includes an active timer entry corresponding to the particular second address.
Methods, systems, and devices for multi-plane firmware image management are described. A memory system may store a primary firmware image across multiple planes. The memory system may read the firmware image from the planes using a multi-plane read operation. The memory system may store copies of the firmware image to separate, individual planes and the copies may be accessed (e.g., read) based on detecting an error in the primary firmware image.
Implementations described herein relate to indicating a status of the memory built-in self-test for multiple memory device ranks. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify a first data mask inversion (DMI) bit of the memory device that is associated with a first rank of the memory device and a second DMI bit of the memory device that is associated with a second rank of the memory device. The memory device may set the first DMI bit to a first value based on determining to perform the memory built-in self-test for the first rank of the memory device. The memory device may perform the memory built-in self-test for the first rank of the memory device based on setting the first DMI bit to the first value.
Systems, methods, and apparatus related to memory devices. In one approach, a memory device includes wordlines connected to rows of memory cells in a memory array. Driver circuitry applies voltages to the wordlines for accessing data stored in the memory cells. A row ordering for the wordlines is implemented with non-aligned logical-to-physical addressing so that wordlines on opposite sides of individual drivers are not physically aligned in the memory array.
A memory device includes an off-lining logging circuit. The memory device detects errors in the memory array as well as one or more addresses which identify where in the array the error was located. The off-lining logging circuit counts errors in different portions of the array, such as sections and/or column planes, based on the addresses. If the count value crosses a threshold, the portion may be identified as a candidate for off-lining. In some examples, a host device may receive off-lining candidate address information from the memory and off-line the identified portions.
Some embodiments include an integrated assembly having a memory array over a base. First sense-amplifier-circuitry is associated with the base and includes sense amplifiers directly under the memory array. Vertically-extending digit lines are associated with the memory array and are coupled with the first sense-amplifier-circuitry. Second sense-amplifier-circuitry is associated with the base and is offset from the first sense-amplifier-circuitry. Control circuitry is configured to selectively couple the digit lines to either a voltage supply terminal or to the second sense-amplifier-circuitry.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4094 - Bit-line management or control circuits
G11C 11/4097 - Bit-line organisation, e.g. bit-line layout, folded bit lines
8.
MANUAL DYNAMIC WORD LINE START VOLTAGE (MDWLSV) PREDICTION AND SELF-ADAPTING CACHE PROGRAM FOR MEMORY OPERATIONS
Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.
Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.
Methods, systems, and devices for host verification for a memory device are described. A memory device may receive a first value from a host device that is associated with an identification of the host device after an event. The memory device may transmit a second value to the host device that is based on the first value and comprises a random set of bits. The memory device may receive from the host device data or a command that comprises an encrypted third value that is based at least in part on the second value and a secret shared between the host device and the memory device. The memory device may also enable a functionality of the memory device based on the encrypted third value.
Methods, systems, and devices for phase error detection and correction are described. A system may implement phase detection circuits configured to receive one or more respective clock signals from one or more phase adjustor circuits. The phase detection circuits may perform a comparison between the respective clock signals. The phase detector circuits may utilize multiple sets of transistors to compare the clock signals. The multiple sets of transistors may be coupled between various current sources and outputs of the circuit. The transistors may be operable based on multiple clock signals received from the phase adjustor circuits. The phase detector circuit may compare various voltage levels at respective outputs to detect one or more phase errors and output one or more phase errors to the phase adjustor circuits.
Methods, systems, and devices for zone write operation techniques are described. A memory system may support zone write operations directly to a multiple-level cell cursor of the memory system. For example, the memory system may close a first zone associated with storing a first type of information from being written with additional information. Based on closing the first zone, the memory system may determine a rate at which the first type of information is written to the memory system. The memory system may receive a command to write second information of the first type to a second zone of the memory system. To write the second information to the second zone, the memory system may write the second information to a cursor configured to store information written to the second zone, and the cursor may be associated with multiple-level memory cells based on the first rate.
In some implementations, a memory device may receive a read command instructing the memory device to read a first set of host data stored at a memory component that is associated with a memory component rank, of multiple memory component ranks associated with a channel. The memory device may read, via the channel based on receiving the read command, the first set of host data using a read-only interface associated with the memory component. The memory device may receive a write command instructing the memory device to write a second set of host data to the memory component. The memory device may write, via the channel and based on receiving the write command, the second set of host data to the memory component using a write-only interface associated with the memory component.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to transition a state of a memory sub-system into different panic handling modes. The controller detects failure of a memory sub-system and determines that self-recovery from the failure of the memory sub-system is unavailable. The controller, in response to determining that self-recovery from the failure of the memory sub-system is unavailable, incrementally transitions a state of the memory sub-system to different panic handling modes and returns the memory sub-system to a deployed mode from one of the different panic handling modes in response to successfully recovering the memory sub-system.
An apparatus including a multi-purpose communication mechanism and associated systems and methods are disclosed herein. The apparatus may include the multi-purpose communication mechanism that enables different circuits to process corresponding/different signals communicated through a shared direct access (DA) pad.
A microelectronic device package may include a microelectronic device supported on, and electrically connected to, a package substrate or a redistribution layer. A non-masking material defined (NMMD) contact may facilitate an electrical connection between the microelectronic device and the package substrate or the redistribution layer.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
17.
DYNAMIC READ RETRY VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM
Methods, systems, and apparatuses include determining to apply a read retry operation to a portion of memory. The likelihood of a read retry timeout meeting a threshold is determined. A reverse trim setting is selected in response to determining the likelihood of the read retry timeout meets the threshold. The read retry operation is executed using the selected trim setting.
Methods, systems, and devices for signal delay control with inverted feedback are described. A system may include a delay circuit that is configured with a chain of delay elements along a forward path of the delay circuit and one or more feedback elements that provide electrical feedback to the forward path. Feedback elements may be or include feedback inverters, such as tri-state inverters, with one or more inputs that are operable to control a signal strength at an output of the feedback inverter. A feedback signal may contend with a signal along the forward path, which may reduce a voltage level associated with the forward signal. By controlling the strength of the feedback signal, the delay circuit may be able to dynamically adjust a delay of the forward signal.
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
H03K 5/134 - Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active-delay devices with field-effect transistors
Various reduced power addressing schemes in different configurations are monitored to assess the toggling characteristics of these schemes. The identified toggling characteristics, in relation to different configurations, are then analyzed in consideration of the associated costs of the reduced power addressing schemes. Among these configurations, the one found to optimize the balance between benefits and costs is selected for implementation as part of the reduced power addressing scheme.
Methods, systems, and devices for sparse piers for three-dimensional memory arrays are described. A semiconductor device, such as a memory die, may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide mechanical support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. In some examples, the alternating layers may be formed into one or more pairs of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns to provide mechanical support between instances of the cross-sectional patterns, or between layers of the cross-sectional patterns (e.g., when one or more layers are removed from the cross-sectional patterns), or both.
Methods, systems, and devices for adjusted access operations for replay protected memory blocks (RPMBs) are described. A memory system may communicate one or more commands concurrently with performance of an access operation on a RPMB in response to receiving a first security protocol command. The first security protocol command may be a security protocol out (SPO) command transmitted from a host device. In combination with a ready to transfer response from the memory system and a data out UPIU from the host device, the first security protocol command may indicate a type of the access operation and corresponding data. The one or more commands may include additional SPO commands, security protocol in (SPI) commands, one or more other commands, or any combination thereof. In some cases, the memory device may transmit the data back to the host after the access operation is complete.
Methods, systems, and devices for adjusted access operations for replay protected memory blocks (RPMBs) are described. A memory system may communicate one or more commands concurrently with performance of an access operation on a RPMB in response to receiving a first security protocol command. The first security protocol command may be a security protocol out (SPO) command transmitted from a host device. In combination with a ready to transfer response from the memory system and a data out UPIU from the host device, the first security protocol command may indicate a type of the access operation and corresponding data. The one or more commands may include additional SPO commands, security protocol in (SPI) commands, one or more other commands, or any combination thereof. In some cases, the memory device may transmit the data back to the host after the access operation is complete.
Methods, systems, and devices for manual dynamic word line start voltage (MDWLSV) prediction and a self-adapting cache program for memory operations are described. In some examples, a memory device may receive a sequence of write commands for a memory block, and the memory device may monitor an interval between two consecutive write commands in the sequence. The memory device may compare the interval to a threshold interval. The memory device may utilize a first programming mode associated with a combination of a set feature (SF) and a get feature (GF) for MDWLSV prediction if the interval exceeds the threshold. The memory device may utilize a second programming mode associated with the SF for MDWLSV prediction if the interval is less than the threshold. The described techniques may provide for the host device to transmit commands for MDWLSV prediction in advance by transmitting the MDWLSV commands via a previous write command.
Methods, systems, and devices for management command microcode techniques for memory architectures are described. For example, interface circuitry of a memory system may be configured to determine that a management operation is to be performed, and may indicate a request to a controller of a host system to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation. Such techniques may involve the interface circuitry and controller being configured in accordance with a sequence of operations (e.g., a microcode), and respective management operations may each be associated with a pointer and a length of the sequence of operations. The controller may be configured to determine one or more commands for an indicated management operation by referencing the sequence of operations in accordance with the pointer and length associated with the indicated management operation.
Aspects of the present disclosure configure a memory sub-system processor to use a fin stack to improve heat dissipation to improve a data transfer rate. The processor measures temperature of at least one of the processing device or the set of memory components. The processor accesses a reference temperature for controlling data transfer rate between a host and the set of memory components. The processor compares the measured temperature with the reference temperature and, based on the comparison, adjusts the data transfer rate based on comparing the measured temperature with the reference temperature.
A memory device includes a command interface configured to receive a write command from a host device. The memory device also includes an input/output interface configured to receive a data strobe. Furthermore, the memory device includes capture circuitry configured to capture the data strobe and generate an internal data strobe. The capture circuitry includes gated extend circuitry configured to extend an overlap of the data strobe with a start-to-synchronize signal that indicates that the data strobe is to be used in the memory device. Moreover, the capture circuitry includes re-gating circuitry configured to re-gate an output of the gated extend circuitry based at least in part on the start-to-synchronize signal.
A microelectronic device includes a first microelectronic device and a second microelectronic device structure overlying the first microelectronic device structure. The first microelectronic device structure includes a first base structure, and a first dielectric oxycarbide material overlying the first base structure. The second microelectronic device structure includes a second dielectric oxycarbide material bonded to the first dielectric oxycarbide material of the first microelectronic device structure, and a second base structure overlying the second dielectric oxycarbide material. Related methods and memory devices are also described.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
28.
Integrated Assemblies and Methods of Forming Integrated Assemblies
Some embodiments include an integrated assembly having a channel-material-pillar extending vertically through a stack of alternating conductive levels and insulative levels. The channel-material-pillar includes a first semiconductor material. A second semiconductor material is directly against an upper region of the channel-material-pillar. The second semiconductor material has a higher dopant concentration than the first semiconductor material and joins to the first semiconductor along an abrupt interfacial region such that there is little to no mixing of dopant from the second semiconductor material into the first semiconductor material. Some embodiments include methods of forming integrated assemblies.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material. A heterogenous insulative region is between the gate material and the channel material.
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10B 53/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region
A memory device includes a three-dimensional (3D) memory array comprising a plurality of blocks and control logic coupled to the 3D memory array. The control logic identifies a defective portion of a block of the plurality of blocks, wherein the defective portion is located above a non-defective portion of the block and causes the defective portion to be pre-programmed before programming the non-defective portion. While pre-programming the defective portion, the control logic causes a first voltage to be applied to a top plurality of wordlines of the defective portion and causes a second voltage to be applied to a bottom plurality of wordlines of the defective portion that are located below the top plurality of wordlines, wherein the second voltage is lower than the first voltage.
The present disclosure provides techniques for using a multiple-port buffer to improve a transaction rate of a memory module. In an example, a memory module can include a circuit board having an external interface, first memory devices mounted to the circuit board, and a first multiple-port buffer circuit mounted to the circuit board. The first multiple-port buffer circuit can include a first port coupled to data lines of the external interface, the first port configured to operate at a first transaction rate, a second port coupled to data lines of a first plurality of the first memory devices, and a third port coupled to data lines of a second plurality of the first memory devices. The second and third ports can be configured to operate at a second transaction rate, wherein the second transaction rate is slower than the first transaction rate.
Methods, systems, and devices for techniques for detecting a state of a bus are described. A memory device may receive an access command transmitted to the memory device via a bus. The memory device may transmit data requested by the access command over data lines and a control signal that indicates the bus is in an active state over a control line. The control signal may be transmitted during a first unit interval of a read operation. The control signal may be configured to have a first voltage when the bus is in an idle state and a second voltage when the bus is in the active state. The control line may be configured to have or trend toward the first voltage when the bus is in the idle state.
Protection for a secure boot procedure can be provided in addition to cryptographic verification of boot firmware associated with the boot procedure. While the boot firmware is being verified and executed at a secure sub-system, an open sub-system can be put into a halt state, during which the open sub-system is prevented from performing the boot procedure. The open sub-system is still prevented from performing the boot procedure even if the boot firmware is verified and/or executed unless the open sub-system is put into the resume state again.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
Methods, systems, and devices for operating frequency monitoring for memory devices are described for monitoring one or more operating frequency ranges experienced by a memory device. The memory device may include monitoring circuitry or logic that may identify one or more durations of operating the memory device within the one or more operating frequency ranges. The memory device may store an indication of the one or more durations, or an indication of information associated with the one or more durations. The indication may be accessed a host device associated with the memory device or may be transmitted by the memory device to the host device. The host device may use information included in the indication to perform an operation associated with the memory device.
Methods, systems, and devices for parallel access in a memory array are described. A set of memory cells of a memory device may be associated with an array of conductive structures, where such structures may be coupled using a set of transistors or other switching components that are activated by a first driver. The set of memory cells may be divided into two or more subsets of memory cells, where each subset may be associated with a respective second driver for driving access currents through memory cells of the subset. Two or more of such second drivers may operate concurrently, which may support distributing current or distributing associated circuit structures across a different footprint of the memory device than other different implementations with a single such second driver.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
36.
MEMORY ADDRESS TRANSLATION FOR DATA PROTECTION AND RECOVERY
Address translation of host commands to access host data stored in memory devices that provides a chip kill capability not only involves locating where the host data is stored, but also involves locating where parity data striped with the host data is stored. In locating where the parity data is stored, the address translation can be performed with logical (e.g., arithmetic) operations.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
Systems and devices for semiconductor die coupling with inductive coils are described. A semiconductor device may include one or more inductive coils to enhance signal quality of signals communicated over conductive lines and to support improved processing bandwidth. The semiconductor device may include multiple dies and each die may include respective circuitry. The respective circuitry may be coupled with the one or more inductive coils. In some cases, each die of the semiconductor device may respectively include one or more inductive coils that couple die circuitry with a same channel. In some cases, a redistribution layer that is shared by each die may be configured with one or more inductive coils that are coupled with each die. Each die may be coupled with the one or more inductive coils based on a conductive pillar or based on a hybrid bond.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
Methods, systems, and devices for write temperature recovery from a memory system are described. A memory system may receive a command to provide write temperature information associated with data written to the one or more memory devices. The memory system may read, from the one or more memory devices based on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data. The memory system may read, based on transmitting the write temperature to a host system, one or more subsets of the data.
A memory device logs telemetry information using a resistive element array. A telemetry logging circuit changes a resistance of one or more resistive elements in the array responsive to one or more commands, addresses, mode signals, or combinations thereof. The change to the resistance may be cumulative with other changes. For example if the resistive element is an antifuse, the resistance may decrease each time the information is logged. In some example embodiments, the memory may read out a resistance of one or more of the resistive elements to determine a telemetry value, which may be written to storage such as a mode register or SPD.
Methods, systems, and devices for security for read commands are described. The memory system receive a read command to read data from a read protected memory block (RPMB) region. The read command may include a first message authenticated code (MAC) key. In some cases, the memory system may authenticate the read command using the first MAC key and retrieving the data from the RPMB region. The memory system may transmit the data after retrieving the data from the RPMB region. In some cases, the memory system may determine whether a read protect flag associated with a logical unit identified by the read command indicates that reading of data stored in the logical unit is permitted. The memory system may read the data based on determining that the read protect flag permits reading the data.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
Methods, systems, and devices for multi-plane firmware image management are described. A memory system may store a primary firmware image across multiple planes. The memory system may read the firmware image from the planes using a multi-plane read operation. The memory system may store copies of the firmware image to separate, individual planes and the copies may be accessed (e.g., read) based on detecting an error in the primary firmware image.
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to debug a memory sub-system. The controller receives, from a host over a first bus, authentication information associated with unlocking the debugging component and, in response to successfully authenticating the host based on the authentication information, unlocks a debugging component. The debugging component receives one or more debug commands from the host via a second bus and transmits, to the host via the second bus, debugging information in response to receiving the one or more debug commands.
Aspects of the present disclosure configure a system component, such as memory sub-system controller, to transition a state of a memory sub-system into different panic handling modes. The controller detects failure of a memory sub-system and determines that self-recovery from the failure of the memory sub-system is unavailable. The controller, in response to determining that self-recovery from the failure of the memory sub-system is unavailable, incrementally transitions a state of the memory sub-system to different panic handling modes and returns the memory sub-system to a deployed mode from one of the different panic handling modes in response to successfully recovering the memory sub-system.
Methods, systems, and devices for security for read commands are described. The memory system receive a read command to read data from a read protected memory block (RPMB) region. The read command may include a first message authenticated code (MAC) key. In some cases, the memory system may authenticate the read command using the first MAC key and retrieving the data from the RPMB region. The memory system may transmit the data after retrieving the data from the RPMB region. In some cases, the memory system may determine whether a read protect flag associated with a logical unit identified by the read command indicates that reading of data stored in the logical unit is permitted. The memory system may read the data based on determining that the read protect flag permits reading the data.
Methods, systems, and devices for endurance group for tiered storage applications are described. A memory system may implement a single memory device with different types of memory and corresponding data access categories. The memory device may implement endurance groups, which may each include a set of memory cells configurable as single-level cells, triple-level cells, or quad-level cells. The endurance groups may be configured based on a capacity identifier selected for the memory device from a set of capacity identifiers supported by the memory system. Each capacity identifier of the set of capacity identifiers may be associated with a configuration of the endurance groups. The host system may transmit a capacity identifier to indicate a configuration of the memory system. The memory system may support data movement internal to the memory system between the endurance groups, without transferring data between the host system.
Methods, systems, and devices for write temperature recovery from a memory system are described. A memory system may receive a command to provide write temperature information associated with data written to the one or more memory devices. The memory system may read, from the one or more memory devices based on the command, a write temperature indicative of a temperature of the memory system at a time of writing a subset of the data. The memory system may read, based on transmitting the write temperature to a host system, one or more subsets of the data.
Systems and devices for semiconductor die coupling with inductive coils are described. A semiconductor device may include one or more inductive coils to enhance signal quality of signals communicated over conductive lines and to support improved processing bandwidth. The semiconductor device may include multiple dies and each die may include respective circuitry. The respective circuitry may be coupled with the one or more inductive coils. In some cases, each die of the semiconductor device may respectively include one or more inductive coils that couple die circuitry with a same channel. In some cases, a redistribution layer that is shared by each die may be configured with one or more inductive coils that are coupled with each die. Each die may be coupled with the one or more inductive coils based on a conductive pillar or based on a hybrid bond.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
50.
APPARATUS INCLUDING MULTI-PURPOSE COMMUNICATION MECHANISM AND ASSOCIATED METHODS
An apparatus including a multi-purpose communication mechanism and associated systems and methods are disclosed herein. The apparatus may include the multi-purpose communication mechanism that enables different circuits to process corresponding/different signals communicated through a shared direct access (DA) pad. The shared direct access (DA) pad connected to a vertically extending via and configured to facilitate communication of a first signal and a second signal with an external device.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
Methods, systems, and devices for forming an indium chalcogenide film are described. Precursors that include an indium-cyclopentadienyl compound may enable formation of indium chalcogenide films at a lower temperature as compared to other precursors including indium, as the reactivity of indium-cyclopentadienyl compounds may be higher than these other precursors. Additionally, using ammonia as a reagent during the atomic layer deposition process to form the indium chalcogenide film may enable an increased rate of formation of indium chalcogenide films for a given temperature. A method may include reacting an indium-cyclopentadienyl precursor and a second precursor that includes a selenium compound or a tellurium compound to form an indium chalcogenide.
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C23C 16/44 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
Methods, systems, and devices for dynamic voltage supply for memory circuit are described. An apparatus may adjust a supply voltage based on a process corner and a temperature of the memory system. An apparatus may include a memory array and a controller. The controller may determine a first temperature of the apparatus is less than a first temperature threshold at a first time. The controller may transition a voltage supplied to the controller from a first voltage level to a second voltage level based on determining the first temperature is less than the first temperature threshold. The controller may determine a second temperature is greater than a second temperature threshold at a second time. The controller may transition the voltage supplied to the controller from the second voltage level to the first voltage level based on determining the second temperature is greater than the second temperature threshold.
Apparatus, systems, and methods for analyzing data are described. The data can be analyzed using a hierarchical structure. One such hierarchical structure can comprise a plurality of layers, where each layer performs an analysis on input data and provides an output based on the analysis. The output from lower layers in the hierarchical structure can be provided as inputs to higher layers. In this manner, lower layers can perform a lower level of analysis (e.g., more basic/fundamental analysis), while a higher layer can perform a higher level of analysis (e.g., more complex analysis) using the outputs from one or more lower layers. In an example, the hierarchical structure performs pattern recognition.
Methods, systems, and devices for an output driver with compact inductive peaking are described. A memory system may implement a circuit for communicating signaling with a host system. The circuit may include a transmission component for transmitting signaling, and a reception component for receiving signaling, where the transmission component and the reception component are coupled with a pad. The circuit may include a current stabilization component and a drain capacitor to store charge associated with the transmission component. The circuit may include a series inductor coupled with the transmission component, the reception component, the drain capacitor, the current stabilization component, and the pad. A capacitance of the pad may be based on a resistance and an inductance of the series inductor.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
55.
MEMORY DEVICE SECURITY THROUGH DISABLEMENT OF FUSE BLOWS
A memory device includes a memory array; a plurality of fuses; a disabling fuse; and control logic, operatively coupled with the plurality of fuses and the disabling fuse, to perform operations during manufacturing of the memory device, the operations including: determining whether the plurality of fuses are programmed; and responsive to determining that the plurality of fuses are programmed, blowing the disabling fuse to disable a blow functionality, wherein the blow functionality is triggered by a subsequent blow command to blow the plurality of fuses.
G06F 21/78 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
G11C 29/10 - Test algorithms, e.g. memory scan [MScan] algorithmsTest patterns, e.g. checkerboard patterns
56.
TECHNIQUES FOR TRANSFERRING DATA BETWEEN MEMORY DEVICES
Methods, systems, and devices for techniques for transferring data between memory devices are described. A memory system may pre-fetch one or more subsets of data associated with the data transfer operation from a first die of the memory system and a second die of the memory system prior to initiating a programming operation on either die. For example, to perform a data folding operation for a set of data which includes a first subset of data stored to the first die and a second subset of data stored to the second die, the memory system may retrieve both the first subset from the first die and the second subset from the second die prior to performing a programming operation on either die.
Devices and techniques that provide reconfigurable eMMC partitions are described herein. A flash memory device includes a register to store card specific data including a reconfiguration lock flag indicating whether partitions on the flash memory device are reconfigurable. The flash memory device can include an interface controller and a memory device able to be configured into one or more partitions by the interface controller.
A variety of applications can include devices implementing one or more fin field-effect transistors (FinFETs) with gate oxide thickness that address thicker gate oxide quality with minimum material loss in the fins of the FinFETs for high voltage devices. The gate oxides can be fabricated with thicker oxides than gate oxides of FinFETs used with capacitors in memory cells of memory arrays. These gate oxides can be formed as oxide liners by oxidation with use of a protective liner to maintain uniform composition of material for the fin during FinFET processing.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
59.
MONITORING MEMORY DEVICE HEALTH ACCORDING TO DATA STORAGE METRICS
A plurality of memory device life metrics are determined, where one of the plurality of memory device life metrics comprises a read count metric that specifies a number of read operations performed on the memory device. A plurality of normalized metric values are calculated, where each of the normalized metric values is based on a ratio of a respective memory device life metric to a respective lifetime target value associated with the respective memory device life metric. A normalized metric value that satisfies a selection criterion is identified from the plurality of normalized metric values. The identified normalized metric value corresponds to an amount of used device life of the memory device. An amount of remaining device life of the memory device is determined based on the identified normalized metric value. An indication of the amount of remaining device life is provided to a host system.
Methods, systems, and devices for a memory device with an error correction memory device with fast data access are described. For example, during a read operation, a memory device may be configured to output the data indicated by the read operation concurrent with performing an error correction operation. If the memory device detects an error, the memory device may indicate the error to a host device and, in some cases, output the corrected data to the host device. During a write operation, the memory device may store error detection or correction information associated with data to be stored at the memory device. The memory device may, in some cases, store error detection or correction information generated by the host device.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 13/00 - Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
H03M 13/00 - Coding, decoding or code conversion, for error detection or error correctionCoding theory basic assumptionsCoding boundsError probability evaluation methodsChannel modelsSimulation or testing of codes
H03M 13/19 - Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes
H03M 13/45 - Soft decoding, i.e. using symbol reliability information
Methods, systems, and devices for temperature-dependent refresh operations are described. A memory system may adjust refresh operations based on a temperature of the memory system to reduce a refresh current and improve reliability of the refresh operations. For example, the memory system may include a temperature sensor configured to provide temperature information associated with a memory device. Based on the temperature information, the memory system may, in response to a refresh command, activate a set of access lines (e.g., word lines) to refresh memory cells coupled with the access lines, where a count of the set of access lines (e.g., how many access lines are included in the set) may be based on the temperature information. In some examples, the count of the set may be determined based on comparing the temperature information to one or more temperature thresholds.
A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.
G06F 12/0891 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means
63.
METHODS AND DEVICES FOR PROGRAMMING A STATE MACHINE ENGINE
A state machine engine having a program buffer. The program buffer is configured to receive configuration data via a bus interface for configuring a state machine lattice. The state machine engine also includes a repair map buffer configured to provide repair map data to an external device via the bus interface. The state machine lattice includes multiple programmable elements. Each programmable element includes multiple memory cells configured to analyze data and to output a result of the analysis.
G06N 3/04 - Architecture, e.g. interconnection topology
G05B 19/045 - Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
G06F 15/78 - Architectures of general purpose stored program computers comprising a single central processing unit
A an example method of adjusting voltage offsets utilized by memory access operations based on values of a chosen media endurance metric includes the operations of: identifying a value of a media endurance metric associated with one or more memory blocks of a memory device; performing a programming operation on the one or more memory blocks; identifying a program-verify voltage level associated with the one or more memory blocks; determining a program-verify voltage offset associated with the program-verify voltage level and the value of the media endurance metric; and performing, using the program-verify voltage level and the program-verify voltage offset, a program-verify operation on the one or more memory blocks.
Methods, systems, and devices for forming an indium chalcogenide film are described. Precursors that include an indium-cyclopentadienyl compound may enable formation of indium chalcogenide films at a lower temperature as compared to other precursors including indium, as the reactivity of indium-cyclopentadienyl compounds may be higher than these other precursors. Additionally, using ammonia as a reagent during the atomic layer deposition process to form the indium chalcogenide film may enable an increased rate of formation of indium chalcogenide films for a given temperature. A method may include reacting an indium-cyclopentadienyl precursor and a second precursor that includes a selenium compound or a tellurium compound to form an indium chalcogenide.
C23C 16/455 - Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into the reaction chamber or for modifying gas flows in the reaction chamber
C23C 16/30 - Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C23C 16/04 - Coating on selected surface areas, e.g. using masks
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
Methods, systems, and devices for thermal vias for semiconductor components are described. A semiconductor component may be configured with conductor portions (e.g., thermal vias) that increase a degree of thermal conductivity through dielectric layers of the semiconductor component. In some examples, thermal vias may be implemented as conductor portions that are enclosed by a dielectric layer, and are therefore electrically floating relative to conductors of substrate circuitry, interconnection circuitry, or both. Additionally, or alternatively, thermal vias may be implemented as portions of conductive lines having a thickness portion that projects through at least some but not all of a respective dielectric layer. In various examples, at least some of such thermal vias may be implemented with a pitch dimension that is similar to conductive lines of one or more interconnection layers, or may implement similar processing as other features of the semiconductor component, among other implementations.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
67.
SEMICONDUCTOR DEVICE WITH BACKSIDE INTERFACE MECHANISM AND METHODS FOR MANUFACTURING THE SAME
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through- silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
68.
ACTIVATE INFORMATION ON PRECEDING PRECHARGE COMMAND
A method and a device is provided for utilizing unused valid (V) bits residing on a previous command to transmit additional activate information to a memory device. Additional activate information may be transmitted to the memory device without increasing the tRCD time, or increasing the command/address (CA) bus pins, or adding additional circuit area, thereby reducing the impact on the performance of the memory device.
Methods, systems, and devices for a memory cell sealant material in a three-dimensional memory array are described. After forming a memory cell, a sealant material may be formed. The sealant material may include some material with a relatively high dielectric constant on the memory cell. The sealant material may be located between the memory cell and a pillar and may prevent or reduce diffusion between the memory cell and the pillar while supporting the memory cell being accessed. The sealant material may be formed as one or more layers of materials and may be associated with a relatively high dielectric constant, such that the sealant material may support low temperature deposition.
Processing a memory array with reduced drift is described herein. An example method includes forming, on a substrate material, a first conductive line material, forming, on the first conductive line material, a first electrode material and a second electrode material separated from one another by a sacrificial material, and forming a plurality of openings in the first conductive line material, first electrode material, sacrificial material, and second electrode material. An insulation material is formed in the plurality of openings. A second conductive line material is formed on the second electrode material and insulation material. An additional plurality of openings are formed in the first electrode material, sacrificial material, second electrode material, and second conductive line material. A plurality of recesses are formed between the first electrode material and the second electrode material by selectively removing the sacrificial material. A chalcogenide material is formed in the plurality of recesses.
Methods, systems, and devices for dense piers for three-dimensional memory arrays are described. In some examples, a memory device may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate. For example, a memory device may include alternating layers of a first material and a second material. In some examples, the alternating layers may be formed into a pair of interleaved comb structures. Pier structures may be formed in contact with the cross sectional patterns, and may provide mechanical support of cross-sectional pattern of the remaining material. In some examples, the piers may further act as a separator between memory cells or other features of the memory device. For example, the piers may extend into at least a portion of the interleaved comb structures, and may accordingly act as barriers during subsequent depositions of materials.
In some implementations, a first device may receive, from a second device, a first nonce associated with initiating a firmware update. The first device may generate, for the firmware update, a second nonce. The first device may transmit, for the firmware update and to the second device, the second nonce based on receiving the first nonce. The first device may receive, for the firmware update and from the second device, a firmware update message that is signed by a digital signature. The first device may verify the firmware update message based on the first nonce, the second nonce, and the digital signature. The first device may perform an action based on verifying the firmware update message.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
73.
Ferroelectric Memory Circuitry And Method Used In Forming Ferroelectric Memory Circuitry
Ferroelectric memory circuitry comprises an upper select-gate tier directly above memory-cell tiers and a lower select-gate tier directly below the memory-cell tiers. Channel-material strings extend through such. Memory cells are in individual memory-cell tiers and comprises a vertical ferroelectric transistor that comprises one of the channel-material strings, two separately-controllable control gates in one of the memory-cell tiers on laterally-opposing sides of the one channel-material string, at least a ferroelectric material in the one individual memory-cell tier laterally between one of the two control gates and the one channel-material string, and at least a gate insulator in the one individual memory-cell tier laterally between the other of the two control gates and the one channel-material string. Other embodiments, including method, are disclosed.
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including performing a program operation to program data to a first block of a plurality of blocks of the memory device, wherein the program operation does not include a program verify phase; performing an in-field read operation to the first block, wherein the in-field read operation includes a voltage floating phase, and wherein a voltage supply to a wordline is withdrawn during the voltage floating phase; and responsive to detecting a read status failure as a result of performing the in-field read operation, marking and retiring the first block and performing the program operation to program the data to a second block of the plurality of blocks of the memory device.
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/18 - Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits, e.g. by quadding or by majority decision circuits
75.
MULTIPLE-STACK MEMORY SYSTEM WITH INTEGRATED COOLING UNIT
Methods, systems, and devices for multiple-stack memory system with integrated cooling unit are described. A multiple-stack memory system may include a first memory device that comprises a first logic die and a first stack of memory dies. The multiple-stack memory system may include a second memory device that comprises a second logic die and a second stack of memory dies. A cooling unit of the multiple-stack memory system may be coupled with a bottom memory die of the first stack of memory dies and coupled with a top memory die of the second stack of memory dies.
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A system includes a memory device; and a processing device, operatively coupled with the memory device, to perform operations including exposing, to a host system, a plurality of values of an overprovisioning parameter of the memory device; receiving, from the host system, a selection of value of the plurality of values; and updating, based on the selection, a value of an operating parameter specifying an overprovisioned capacity of the memory device.
Methods, systems, and devices for subblock-dependent word line ramp rates are described. A memory device may select, for writing a first set of data and a second set of data, a block of memory cells that share a word line. The memory device may apply, via the word line as part of a first write operation to write the first set of data, a first voltage pulse having a first ramp rate to a first subblock having a first position within the block. And the memory device may apply, via the word line as part of a second write operation to write the second set of data, a second voltage pulse having a second ramp rate to a second subblock having a second position within the block.
Methods, systems, and devices for thermal vias for semiconductor components are described. A semiconductor component may be configured with conductor portions (e.g., thermal vias) that increase a degree of thermal conductivity through dielectric layers of the semiconductor component. In some examples, thermal vias may be implemented as conductor portions that are enclosed by a dielectric layer, and are therefore electrically floating relative to conductors of substrate circuitry, interconnection circuitry, or both. Additionally, or alternatively, thermal vias may be implemented as portions of conductive lines having a thickness portion that projects through at least some but not all of a respective dielectric layer. In various examples, at least some of such thermal vias may be implemented with a pitch dimension that is similar to conductive lines of one or more interconnection layers, or may implement similar processing as other features of the semiconductor component, among other implementations.
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
79.
MANAGEMENT COMMAND MICROCODE TECHNIQUES FOR MEMORY ARCHITECTURES
Methods, systems, and devices for management command microcode techniques for memory architectures are described. For example, interface circuitry of a memory system may be configured to determine that a management operation is to be performed, and may indicate a request to a controller of a host system to schedule aspects of the management operation. In response, the controller may indicate one or more commands to the interface circuitry to perform the management operation. Such techniques may involve the interface circuitry and controller being configured in accordance with a sequence of operations (e.g., a microcode), and respective management operations may each be associated with a pointer and a length of the sequence of operations. The controller may be configured to determine one or more commands for an indicated management operation by referencing the sequence of operations in accordance with the pointer and length associated with the indicated management operation.
System and techniques for indirectly accessing an object in memory are described herein. A memory allocation request for an object is received that specifies use of a shared pointer. A memory address to fulfill this allocation is identified and a pointer to this address is written in a shared memory location accessible by both a host and a memory device. When the host requests the object, the host references the pointer to get the memory address of the object for the request. The memory device can then return the requested data.
Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes conductive plates adjacent each other; memory cells associated with the conductive plates; drivers coupled to the conductive plates such that one of the drivers is associated with one of the conductive plates; and a short coupled between a first conductive plate of the conductive plate and a second conductive plate of the conductive plates.
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
A memory device may comprise a memory controller configured for controlling access to an array of memory cells. The memory controller may be configured to perform one or more memory device functions that enable the host to perform system operations. The memory controller may include at least one safety mechanism and at least one safety mechanism monitor. The safety mechanism(s) may determine memory device fault condition(s) that has a potential to adversely affect performance of at least one of the one or more memory device functions. The safety mechanism monitor(s) may determine at least one safety mechanism fault condition that has a potential to adversely affect an ability of the safety mechanism(s) to determine the memory device fault condition(s). The host may assess whether the safety mechanism(s) is reliable based on the safety mechanism fault condition(s).
Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes an elemental region having a first width. The elemental region includes a first native portion of a semiconductive material. The integrated assembly further includes a composite region over the elemental region and having a second width that is greater than or equal to the first width. The composite region includes a second native portion of the semiconductive material that is directly conjoined with the first native portion, and a reconstituted portion of the semiconductive material that is directly conjoined with the second native portion and that extends away from the second native portion.
Various embodiments provide for low-latency loading of padding data onto blocks of a memory circuit die, which can be used as part of a memory device of a memory system (e.g., a memory sub-system). According to some embodiments, padding data is transferred once into a data buffer component, such as a set of latches, a primary cache memory, a secondary cache memory, local memory, or the like of the memory circuit die. Then the transferred padding data is retained (in the data buffer component) and used to perform multiple programming operations (or program cycles) on multiple pages of multiple blocks. Additionally, for some embodiments, a program verification operation is skipped after one or more programming operations (or program cycles).
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may have on a backside of a semiconductor substrate an integral electrical connector that includes (1) a pad portion configured to connect to an external component and (2) a through-silicon via (TSV) portion that at least partially extends through the semiconductor substrate. The pad portion and the TSV portion may be connected through an integral joint. The TSV portion can have a narrowing shape with its cross-sectional width decreasing for portions farther away from the pad portion.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
86.
MEMORY CHIP TEST PAD ACCESS MANAGEMENT TO FACILITATE DATA SECURITY
A system for providing memory chip test pad access management to facilitate data security is disclosed. A host issues a command to access a non-volatile memory of a memory chip system via a test pad. A controller acknowledges the command by transmitting a response to the host to authenticate the host for access. The host then issues an authenticated command to modify a reserved byte of a protected memory partition of the non-volatile memory. The controller responds to the authenticated command and the reserved byte is modified. Firmware of the memory chip system monitors the modification of the reserved byte and notifies the memory chip system to activate a switch in an access control unit controlling access to the non-volatile memory. The switch is then activated, thereby closing a circuit to connect the test pad with the non-volatile memory. The host then access the non-volatile memory via the test pad.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 51/40 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the peripheral circuit region
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
Processing a memory array with reduced drift is described herein. An example method includes forming, on a substrate material, a first conductive line material, forming, on the first conductive line material, a first electrode material and a second electrode material separated from one another by a sacrificial material, and forming a plurality of openings in the first conductive line material, first electrode material, sacrificial material, and second electrode material. An insulation material is formed in the plurality of openings. A second conductive line material is formed on the second electrode material and insulation material. An additional plurality of openings are formed in the first electrode material, sacrificial material, second electrode material, and second conductive line material. A plurality of recesses are formed between the first electrode material and the second electrode material by selectively removing the sacrificial material. A chalcogenide material is formed in the plurality of recesses.
System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and a heat-mitigating high-bandwidth memory (HBM) device each integrated with the base substrate. The heat-mitigating HBM device can include a stack of one or more memory dies and an interface die carried by the stack of one or more memory dies. The interface die includes an input/output (IO) circuit that is accessible through an upper surface of the interface die. The SiP device can also include a communication substrate carried by the host device and the heat-mitigating HBM device, as well as a thermal interface material carried by the communication substrate. The communication substrate can include one or more communication channels communicably coupling the IO circuit of the interface die to the host device.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
90.
MICROELECTRONIC DEVICES AND RELATED METHODS AND MEMORY DEVICES
A microelectronic device includes a conductive structure and a conductive contact structure on the conductive structure. The conductive contact structure on the conductive structure includes a conductive pad structure, a metal silicide material over the conductive pad structure, and a conductive fill material surrounded by the metal silicide material. The metal silicide material physically contacts and substantially covers sidewalls and a bottom surface of the conductive fill material. Related methods and memory devices are also described.
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
Methods, systems, and devices for NAND structures with polarized materials are described. A memory device may include a polarized dielectric material located relatively near to a channel, which may reduce interference between cells. The polarized dielectric material may include a dielectric material with a fixed polarity and having a first surface with a negative polarity oriented towards the channel. The negative polarity of the polarized dielectric material may affect an electron distribution of the channel by shifting the electron distribution closer to an associated charge trapping material. The shifted electron distribution may reduce an effect of an electric field of any aggressor cells of the memory device on one or more victim cells, by creating a more uniform channel electron distribution and increasing gate control relative to a channel without the effects of the polarized dielectric material.
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
92.
APPARATUSES AND METHODS FOR ACTIVATION COUNTER INITIALIZATION
Embodiments of the disclosure are drawn to apparatuses, systems, and methods for activation counter initialization (ACI). A memory may be placed in an ACI mode. During the ACI mode, an ACI control circuit initializes the access count values of the memory array to an initialization value. For example, the ACI mode may work through the array on a row-by-row basis initializing the access count values along each of the rows. By controlling the initial state of the access count values, it is less likely to have a false aggressor alert because none of the access count values start at a randomly high number, simulating an aggressor even after a small number of accesses.
Methods, systems, and devices for memory device staircase formation are described. A memory device may include a stack of materials that includes a first staircase portion, at a first surface of the stack, having first contact surfaces for a first subset of word lines and a second staircase portion, at a second surface of the stack, which includes second contact surfaces for a second subset of the word lines. Conductive pillars may couple the word lines of the first subset and the second subset to the supporting circuitry. For example, a first conductive pillar may extend, in a first plane, from a first word line of the first subset toward the first surface of the stack and a second conductive pillar may extend, in the first plane, from a second word line of the second subset toward the second surface of the stack.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
94.
MULTIPLE BIT FLIP THRESHOLD SETS FOR IMPROVED ERROR CORRECTION IN A MEMORY SUB-SYSTEM
A soft input is obtained from a sense word corresponding to encoded host data read from the memory device and decoded using a parity-check matrix. A match array is maintained. Each iteration of an error correcting code operation a number of unsatisfied check nodes of a respective bit of the sense word is calculated for each bit of the sense word. A bit flip threshold value from a threshold value data structure is obtained based on a current iteration of the error correcting code operation, a soft bit associated with the respective bit, and a match bit associated with the respective bit. The respective bit is flipped based on the number of unsatisfied check nodes satisfying the bit flip threshold value.
Methods, systems, and devices for independent flash translation layer (FTL) storage for a memory system are described. A memory system may be configured with multiple independent FTLs each defined by a respective set of instructions stored as metadata in a respective storage region of a memory device. The memory system may perform one or more FTL functions of an independent FTL on data stored in the respective storage region based on the metadata. Each port of the memory system may be mapped to an FTL and a storage region, where a port may couple the memory system with one or more external systems. In response to detecting a corrupted FTL, the storage region associated with the corrupted FTL may enter a first operational mode associated with reduced write capabilities while other storage regions of the memory system may remain in a second operational mode.
Methods, systems, and devices for thin film transistor random access memory are described. A memory device may include memory cells each having one or more transistors formed above a substrate. For example, a memory cell may include a transistor having a channel portion formed by one or more pillars or other structures formed above a substrate, and a gate portion including a conductor formed above the substrate and configured to activate the channel portion based at least in part on a voltage of the gate portion. A memory cell may include a set of two or more such transistors to support latching circuitry of the memory cell, or other circuitry configured to store a logic state, which may or may not be used in combination with one or more transistors formed at least in part from one or more portions of a substrate.
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
This document discloses techniques, apparatuses, and systems for a semiconductor device with a porous air vent. The semiconductor device includes a semiconductor die mounted to a substrate at one or more contact pads. Underfill material is disposed between the semiconductor die and the substrate. The substrate includes a porous portion composed of a porous material. The porous material is such that air, but not the underfill material, may pass from an area between the semiconductor die and the substrate to an area below the substrate. As a result, air may pass through the porous portion during the underfill process and the underfill material may be retained. Thus, voids and back contamination may be limited to assemble a reliable semiconductor device
Memories might include a controller configured to cause the memory to transition a status indicator for a first period of time in response to receiving a write command associated with first address data corresponding to a first plurality of memory cells of the block of memory cells and with first data for a first programming operation, transition the status indicator for a second period of time shorter than the first period of time in response to receiving the write command associated with second address data corresponding to the block of memory cells before completing a verify phase of the first programming operation, and transition the status indicator for the first period of time in response to receiving the write command associated with the second address data and with the second data for the second programming operation after completing the verify phase of the first programming operation.
Disclosed in some examples are methods, systems, and devices for authenticating a firmware object on a device and in some examples to safeguard the attestation process from the execution of malicious firmware. In some examples, a firmware update process may, in addition to updating the firmware on the device, write a hash of the authentic firmware code in a secure storage device (e.g., a register). This may be done in some examples in a protected environment (e.g., a trusted execution environment or a protected firmware update process). Upon first boot after the update, a firmware update checker compares the firmware object that is booted with the value of the secure storage device. If the values match, the alias certificate may be regenerated, and the boot continues. If the values do not match, then the alias certificate may not be regenerated, and the system may have an authenticity failure because the key and the certificate do not match.
G06F 21/57 - Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
100.
HEAT-MITIGATING HIGH-BANDWIDTH DEVICES IN SYSTEM-IN-PACKAGE DEVICES AND ASSOCIATED SYSTEMS AND METHODS
System-in-package (SiP) devices, and associated systems and methods are disclosed herein. In some embodiments, a SiP device can include a base substrate, as well as a host device and a heat-mitigating high-bandwidth memory (HBM) device each integrated with the base substrate. The heat-mitigating HBM device can include a stack of one or more memory dies and an interface die carried by the stack of one or more memory dies. The interface die includes an input/output (IO) circuit that is accessible through an upper surface of the interface die. The SiP device can also include a communication substrate carried by the host device and the heat- mitigating HBM device, as well as a thermal interface material carried by the communication substrate. The communication substrate can include one or more communication channels communicably coupling the IO circuit of the interface die to the host device.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
