Methods, systems, and devices for sorting retired blocks of non-volatile memory cells are described. A memory system may recover a block that has been marked as “bad” using a requalification process. For example, after operating in an error protection mode for the block, the memory system may monitor the block to determine whether a status flag indicating an access error is set. If the status flag is set, the memory system may store information that indicates the block is unrecoverable, and the block may subsequently be retired. Alternatively, if a status flag is not set, the memory system may store information that indicates the block may be recoverable. If one or more additional access operations to the block are successful, the memory system may store information that indicates the block may be used for subsequent access operations.
An apparatus includes an active region; a scribe region surrounding the active region; a test component in the scribe region; a pad electrode in the active region; and a power supply wiring of an upper wiring layer in the active region, the power supply wiring extending between the test component and the pad electrode; and an interconnection structure coupling the test component and the pad electrode across a border between the active region and the scribe region, the interconnection structure including a wiring portion of a lower wiring layer crossing the power supply wiring.
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/525 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
H01L 23/528 - Layout of the interconnection structure
H10B 12/00 - Dynamic random access memory [DRAM] devices
3.
MICROELECTRONIC DEVICES, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
A microelectronic device includes a semiconductor base structure, word lines, digit line contacts, digit lines, and storage node contacts. The semiconductor base structure includes pillar structures horizontally separated from one another by filled isolation trenches. The word lines horizontally extend through the pillar structures and the filled isolation trenches in a first direction. The digit line contacts include conductively doped semiconductor material vertically extending into digit line contact sections of the pillar structures. The digit lines are over and in contact with the digit line contacts and horizontally extend in a second direction orthogonal to the first direction. The digit lines have a different material composition than the digit line contacts. The storage node contacts include additional conductively doped semiconductor material vertically extending into storage node contact sections of the pillar structures. Methods, memory devices, and electronic systems are also described.
An example system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations including: determining that a write request references a partially aligned translation unit; identifying a first entry in a translation map, such that the first entry identifies a first physical block of the memory device, such that the first physical block is mapped to the partially aligned translation unit; creating a second entry in the translation map, wherein the second entry identifies a second physical block of the memory device, wherein the second physical block is mapped to the partially aligned translation unit; linking, in the translation map, the first entry and the second entry; and writing a subset of data corresponding to the partially aligned translation unit to a first portion of the second physical block.
Various embodiments provide for incremental power throttling on a memory system, such as a memory sub-system. In particular, for some embodiments, incremental power throttling is implemented on a memory system using one or more power credit allocations and memory operation progress tracking.
Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.
Systems, devices, and methods related to a deep learning accelerator and memory are described. For example, an integrated circuit device may be configured to execute instructions with matrix operands and configured with random access memory (RAM) to store parameters of an artificial neural network (ANN). The device can generate random bit errors to simulate compromised or corrupted memory cells in a portion of the RAM accessed during computations of a first ANN output. A second ANN output is generated with the random bit errors applied to the data retrieved from the portion of the RAM. Based on a difference between the first and second ANN outputs, the device may adjust the ANN computation to reduce sensitivity to compromised or corrupted memory cells in the portion of the RAM. For example, the sensitivity reduction may be performed through ANN training using machine learning.
G06F 30/27 - Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
An interconnect system includes host devices, one or more memory devices, and a routing system to connect the host devices and the one or more memory devices. Respective ones of the host devices include an interface to communicate packet requests over respective packetized links. Respective ones of the one or more memory devices include an interface to receive and respond to the packet requests over the respective packetized links. The routing system includes devices interconnected in a routing topology. Respective ones of the devices include a switch and interfaces. The routing system is to route the packet requests and responses between the host devices and respective memory device destinations over the respective packetized links. The host devices are to communicate cache coherency traffic to each other over at least one of the respective packetized links.
A method includes receiving user data having a number of first bits. The method further includes encoding the user data by generating a number of second encoded bits having a first quantity of bits greater than that of the number of first bits. The number of second encoded bits can include one or more bits having a particular binary value and a quantity of the one or more bits is less than a threshold quantity. The method further includes writing the number of second encoded bits as the user data to a memory.
H03M 7/30 - CompressionExpansionSuppression of unnecessary data, e.g. redundancy reduction
G06F 7/74 - Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
10.
Memory Circuitry Comprising a Vertical String of Memory Cells and a Conductive Via and Method Used in Forming a Vertical String of Memory Cells and a Conductive Via
A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
H10B 43/30 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
H10B 99/00 - Subject matter not provided for in other groups of this subclass
11.
AUTOMATIC COLLECTION OF AUTONOMOUS VEHICLE LOGGING DATA
A method for an autonomous vehicle includes: controlling at least one system of the vehicle by a host system; automatically collecting, by a memory device, data generated by the at least one system, where the data is collected by the memory device independently of control by the host system; and storing the data in the memory device.
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
B60W 50/02 - Ensuring safety in case of control system failures, e.g. by diagnosing, circumventing or fixing failures
G06F 3/06 - Digital input from, or digital output to, record carriers
G07C 5/00 - Registering or indicating the working of vehicles
12.
AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE
A memory system includes a memory device and a processing device coupled to the memory device. The processing device receives a plurality of codewords; selects a first read voltage associated with the one or more codewords, such that the first read voltage is based on a time elapsed since a last write operation with respect to a management unit comprising the one or more codewords; and applies the first read voltage to a set of memory cells storing the one or more codewords.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Methods, apparatus, and non-transitory machine-readable media associated with mirroring data for a virtual environment. An apparatus can include a memory device and a processor communicatively coupled to the memory device. The processor can receive data for display from a different apparatus that is coupled to the apparatus, wherein the different apparatus is a physical apparatus. The processor can modify image data for a virtual environment using the data. A display system coupled to the processor can display the modified image data of the virtual environment to mirror the data from the different apparatus to the virtual environment.
A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Methods, systems, and devices for top die back-side marking for memory systems are described. One or more alignment marks may be added to the back-side of a top memory die in a multi-layer memory device and used to align a position of the top memory die relative to a position of a memory die below the top memory die. The alignment marks may be formed on the top memory die during the manufacturing process of the multi-layer memory device. Operations for forming the alignment marks are described using various semiconductor fabrication techniques. Operations are also disclosed for using the alignment marks to modify placement of the top memory die to reduce the alignment offset in the manufacturing process of subsequent memory dies.
H01L 23/544 - Marks applied to semiconductor devices, e.g. registration marks, test patterns
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
16.
MEMORY DEVICE HAVING MEMORY CELL STRINGS AND SEPARATE READ AND WRITE CONTROL GATES
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell included in a memory cell string; the memory cell including charge storage structure and channel structure separated from the charge storage structure by a dielectric structure; a first control gate associated with the memory cell and located on a first side of the charge storage structure and a first side of the channel structure; and a second control gate associated with the memory cell and electrically separated from the first control gate, the second control gate located on a second side of the charge storage structure and a second side of the channel structure.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.
G06F 12/06 - Addressing a physical block of locations, e.g. base addressing, module addressing, address space extension, memory dedication
G06F 12/0864 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
G06F 12/0893 - Caches characterised by their organisation or structure
18.
VOLTAGE REGULATION FOR MEMORY ARRAY TEST PROCEDURES
Methods, systems, and devices for voltage regulation for memory array test procedures are described. A system may utilize multiple voltage regulators to concurrently activate sets of antifuses and to compensate for voltage drops across the antifuses. Each voltage regulator may be associated with a respective region of memory cells. The memory system may apply an activation voltage to antifuse circuitry of a memory array. Respective voltage regulators for each region of memory cells may maintain the activation voltage across respective sets of antifuses of the antifuse circuitry, such that the activation voltage exceeds a respective threshold for each antifuse. Each antifuse of the respective sets of antifuses may be activated based on maintain the activation voltage using the multiple voltage regulators. The set of antifuses may transition from a resistive state to a conductive state based on activating the set of antifuses.
G11C 17/18 - Auxiliary circuits, e.g. for writing into memory
G11C 17/16 - Read-only memories programmable only onceSemi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
G11C 29/02 - Detection or location of defective auxiliary circuits, e.g. defective refresh counters
19.
SYSTEMS AND METHODS TO MANAGE MEMORY DURING POWER DOWN AND STORAGE
Systems and methods described herein may enable memory maintenance operations to be performed on a memory device in compliance with a time interval having a duration based on a temperature of the memory device. A system may include a memory device and a memory controller communicatively coupled to the memory device. The memory controller may receive a temperature measurement indicative of a present temperature of the memory device and determine a memory management interval based on the temperature measurement. The memory controller may perform a memory management operation based on the memory management interval. Sometimes, the memory controller powers on the memory device to perform the memory management operation on the memory device.
A host submits a command to a memory device, where a host status indicator (ID) for the host and a memory device status ID for the memory device are assigned with the command in at least one of a status command slot related to the command. An interrupt signal asserted during processing of the command is determined, where the interrupt signal is indicative of a change in at least one of the host status ID and the memory device status ID. After determining that the interrupt signal is asserted at least one of the host status ID and the memory device status ID are read. Based on the read information, a failure in at least one of the host and device is corrected prior to initiation of a timeout process.
A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
G06F 11/16 - Error detection or correction of the data by redundancy in hardware
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G11C 29/00 - Checking stores for correct operationTesting stores during standby or offline operation
G11C 29/14 - Implementation of control logic, e.g. test mode decoders
G11C 29/44 - Indication or identification of errors, e.g. for repair
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor
A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 51/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the top-view layout
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 51/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the memory core region
H10B 53/10 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the top-view layout
H10B 53/30 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
H10D 1/68 - Capacitors having no potential barriers
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
24.
WAFER PROCESSING SYSTEMS, WAFER TRANSPORT DEVICES, AND RELATED METHODS
A wafer storage device may include one or more mutually aligned rails extending from two opposing side walls, each pair of mutually aligned rails configured to support a wafer between the side walls. The wafer storage device includes one or more sensors coupled to at least some of the one or more rails. The one or more sensors may be configured to detect a physical property of the wafer. The wafer storage device may further include a processor configured to analyze data from the one or more sensors, and a memory device. The memory device may be configured to store data produced by at least the one or more sensors or the processor. The wafer storage device may also include a power storage device configured to receive power from an external source and supply power to the one or more sensors and the processor.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
G01N 21/95 - Investigating the presence of flaws, defects or contamination characterised by the material or shape of the object to be examined
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
H01L 21/677 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for conveying, e.g. between different work stations
H01L 21/687 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
A semiconductor device assembly is provided. The assembly includes a substrate and a semiconductor device. The substrate includes a first conductive layer, the first conductive layer having a first trace with a first exposed pad and a second trace with a second exposed pad. A wire bond runs above the first conductive layer to connect the first exposed pad to the second exposed pad, such that the first trace and the second trace are only connected via the wire bond. The semiconductor device includes an electrical connection to the first trace.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Methods, systems, and devices for implicit storage of metadata at a memory device are described. A memory device may perform an error correction code (ECC) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data. The memory device may compare the first set of parity bits to the second set of parity bits based on the ECC decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits. The memory device may recover metadata information, for the set of data, previously received by the memory device, based on the comparison.
Apparatuses and systems including sense amplifiers are disclosed. An apparatus may include a first pull-up sense amplifier, a first pull-down sense amplifier, and a first pair of lines electrically connecting the first pull-up sense amplifier to the first pull-down sense amplifier. The apparatus may further include a second pull-up sense amplifier, a second pull-down sense amplifier, and a second pair of lines including one or more wiring twists and electrically connecting the second pull-up sense amplifier to the second pull-down sense amplifier.
An example system includes a memory device; and a processing device, operatively coupled to the memory device, to perform operations, including: programming a plurality of pages of the memory device; adjusting a program verify voltage associated with the plurality of pages; responsive to determining that a first error rate of a first page of the plurality of pages exceeds a second error rate of a second page of the plurality of pages, performing a recovery operation on the first page to produce recovered data; and storing the recovered data on the memory device.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
An example system includes: memory devices and a processing device operatively coupled to the memory devices. The processing device is configured to perform operations, including: receiving a write command specifying a data item and comprising a dedicated field specifying an identifier of a data stream, the data stream comprising a plurality of data items including the data item, such that the identifier of the data stream is enhanced by one or more data stream attributes shared by data items comprised by the data stream; determining, by parsing the identifier of the data stream, a data stream attribute of the one or more data stream attributes shared by data items comprised by the data stream; identifying, based on the data stream attribute, a memory device managed by the processing device; and transmitting, to the memory device, an instruction specifying the data item.
Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.
G06F 21/79 - Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
G06F 21/10 - Protecting distributed programs or content, e.g. vending or licensing of copyrighted material
G06F 21/55 - Detecting local intrusion or implementing counter-measures
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
32.
Methods of Forming Integrated Assemblies Having Conductive Material Along Sidewall Surfaces of Semiconductor Pillars
Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
H10B 12/00 - Dynamic random access memory [DRAM] devices
G11C 11/402 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration individual to each memory cell, i.e. internal refresh
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A host system to query, during booting up of the host system, a superblock size in a connected memory sub-system. The host system can place write requests into separate streams and send the streams to the memory sub-system to store data of the write requests into separate sets of superblocks for the streams respectively. The host system can allocate, a plurality of log buffers for the streams respectively and record, into the log buffers, sequences of logical addresses as in the streams respectively. The host system can trim a stream, among the plurality of streams, by issuing commands to the memory sub-system to erase, according to the superblock size, an amount of data from a portion of a sequence of logical addresses recorded in a log buffer for the stream, causing the memory sub-system to free at least one superblock.
An example memory device includes: a memory array; and a controller coupled to the memory array, the controller to perform the following operations: identifying a set of memory cells for performing a memory programming operation, such that the memory cells are electrically coupled to a target wordline and a set of target bitlines; causing a first voltage to be applied to the target wordline, such that the first voltage is incremented every time period over a sequence of time periods; causing a second voltage to be applied to a first bitline, such that the second voltage is incremented during a first time period of the sequence of time periods; and causing a third voltage to be applied to a second bitline, such that the third voltage is incremented during a second time period of the sequence of time periods.
Computerized apparatus using characterized devices such as memories for intensive computational applications such as blockchain processing. In one embodiment, the computerized apparatus comprises a computational appliance (e.g., stand-alone box, server blade, plug-in card, or mobile device) that includes characterized memory devices. These memory devices are associated with a range of performances over a range of operational parameters, and can be used in conjunction with a solution density function to optimize memory searching. In one embodiment, the ledger appliance can communicate with other ledger appliances to create and/or use a blockchain ledger so as to facilitate decentralized exchanges between untrusted parties. In some variants, the ledger appliance may additionally use an application programming interface (API) to dynamically generate blockchains on the fly. Various other applications are also described (e.g., social media, machine learning, probabilistic applications and other error-tolerant applications).
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06Q 20/06 - Private payment circuits, e.g. involving electronic currency used only among participants of a common payment scheme
A processing device in a memory sub-system detects an occurrence of a triggering event, determines respective levels of charge loss associated with a first representative wordline of a block of a memory device and with a second representative wordline of the block of the memory device, and determines whether a difference between the respective levels of charge loss satisfies a threshold criterion. Responsive to determining that the difference between the respective levels of charge loss satisfies the threshold criterion, the processing device further determines that the block is in a uniform charge loss state.
Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
Methods and apparatus are provided involving adaptive content inspection. In one embodiment, a content inspection processor may identify information with respect to input data and provide the information to a host controller. The host controller may adapt search criteria or other parameters and provide the adapted parameter to the content inspection processor. Other embodiments may include a content inspection processor having integrated feedback, such that results data is fed back to the content inspection processor. The results data may be processed before being provided to the content inspection processor.
Systems, methods and apparatuses of fine grain data migration in using memory as a service (MaaS) are described. For example, a memory status map can be used to identify the cache availability of sub-regions (e.g., cache lines) of a borrowed memory region (e.g., a borrowed remote memory page). Before accessing a virtual memory address in a sub-region, the memory status map is checked. If the sub-region has cache availability in the local memory, the memory management unit uses a physical memory address converted from the virtual memory address to make memory access. Otherwise, the sub-region is cached from the borrowed memory region to the local memory, before the physical memory address is used.
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
H04L 67/568 - Storing data temporarily at an intermediate stage, e.g. caching
H04W 8/26 - Network addressing or numbering for mobility support
Methods, systems, and devices for a light hibernation mode for memory are described. A memory system may include volatile memory and non-volatile memory and may be configured to operate according to a first mode of operation (e.g., associated with relatively high power consumption), a light hibernation mode (e.g., a second mode associated with decreased power consumption in comparison to the first mode), and a full hibernation mode (e.g., a third mode of operation associated with decreased power consumption in comparison to the light hibernation mode). While operating according to the light hibernation mode, the memory system may maintain a greater quantity of data in the volatile memory relative to the full hibernation mode, which may avoid at least some power consumption related to data transfers between the volatile memory and non-volatile memory that may occur in connection with entering and exiting the full hibernation mode.
Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.
A plurality of context data structures are maintained. Each context data structure corresponds to an active region of a plurality of active regions of a memory device. A write request directed to a first active region is received. Responsive to determining that a first indicator of the first context data structure associated with the first active region characterizes the first active region as closed, a second active region is identified. A buffer associated with the second active region is identified, wherein the buffer stores host data. The host data in the buffer is padded to a predetermined size, and the buffer is flushed to the second active region. The number of padding operations performed with respect to the second active region is incremented and the second context data structure is updated. The first indicator of the first context data structure is updated, characterizing the first context data structure as open.
Methods, systems, and devices for implicit storage of metadata at a memory device are described. A memory device may perform an error correction code (ECC) decoding operation on a first set of parity bits for a set of data and a second set of parity bits for the set of data. The memory device may compare the first set of parity bits to the second set of parity bits based on the ECC decoding operation indicating that the set of data has an uncorrectable error, the first set of parity bits to the second set of parity bits. The memory device may recover metadata information, for the set of data, previously received by the memory device, based on the comparison.
The subject application relates to spatially aware Design for Testability (DFT). For instance, a method may include dividing a layout of a circuit under test (CUT) into a plurality of grids based on a preconfigured policy, creating, based on the preconfigured policy, a plurality of targeted portions from the divided layout of the CUT, applying a DFT test pattern to the plurality of targeted portions; and capturing data output from the plurality of targeted portions.
Systems, apparatuses, and methods related to securing domain crossing using domain access tables are described. For example, a computer processor can have registers configured to store locations of domain access tables respectively for predefined, non-hierarchical domains. Each respective domain access table can be pre-associated with a respective domain and can have entries configured to identify entry points of the respective domain. The processor is configured to enforce domain crossing in instruction execution using the domain access tables and to prevent arbitrary and/or unauthorized domain crossing.
A memory sub-system connectable to a microprocessor to provide network storage services. The memory sub-system has a random-access memory configured with: first queues for the microprocessor and a network interface; second queues for the microprocessor and a processing device; and third queues for the processing device and a storage device. The processing device is configured to: generate first control messages and first data messages from packets received by the network interface; place the first control messages into the first queues for the microprocessor; and place the first data messages into the third queues for the storage device. The microprocessor processes the first control messages to implement security and administrative functions and place second control messages in the second queues. The storage device is configured to retrieve the first data messages from the third queues and second control messages from the second queues for processing.
H04L 49/103 - Packet switching elements characterised by the switching fabric construction using a shared central bufferPacket switching elements characterised by the switching fabric construction using a shared memory
H04L 67/1097 - Protocols in which an application is distributed across nodes in the network for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
47.
Metal-Containing Structures, and Methods of Treating Metal-Containing Material to Increase Grain Size and/or Reduce Contaminant Concentration
Some embodiments include a method of forming a conductive structure. A metal-containing conductive material is formed over a supporting substrate. A surface of the metal-containing conductive material is exposed to at least one radical form of hydrogen and to at least one oxidant. The exposure alters at least a portion of the metal-containing conductive material to thereby form at least a portion of the conductive structure. Some embodiments include a conductive structure which has a metal-containing conductive material with a first region adjacent to a second region. The first region has a greater concentration of one or both of fluorine and boron relative to the second region.
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
C23C 8/06 - Solid state diffusion of only non-metal elements into metallic material surfacesChemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases
C23C 8/36 - Solid state diffusion of only non-metal elements into metallic material surfacesChemical surface treatment of metallic material by reaction of the surface with a reactive gas, leaving reaction products of surface material in the coating, e.g. conversion coatings, passivation of metals using gases using ionised gases, e.g. ionitriding
C23C 28/00 - Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups , or by combinations of methods provided for in subclasses and
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/41 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
48.
Network Storage Products with Options for External Processing
A storage product having: a network interface operable on a computer network; a bus connector adapted to be connected to a computer bus; a storage device having a storage capacity accessible through network storage services provided over the network interface; and a processing device configured to at least generate storage access messages from incoming packets received by the network interface from the computer network. The storage product is operable in a standalone mode when no local host system is connected to the bus connector to control the storage product and operable in a slave mode when a local host system is connected to the bus connector to process a portion of the storage access messages.
Some embodiments include an assembly having a stack of alternating dielectric levels and conductive levels. Channel material pillars extend through the stack. Some of the channel material pillars are associated with a first sub-block, and others of the channel material pillars are associated with a second sub-block. Memory cells are along the channel material pillars. An insulative level is over the stack. A select gate configuration is over the insulative level. The select gate configuration includes a first conductive gate structure associated with the first sub-block, and includes a second conductive gate structure associated with the second sub-block. The first and second conductive gate structures are laterally spaced from one another by an intervening insulative region. The first and second conductive gate structures have vertically-spaced conductive regions, and have vertically-extending conductive structures which electrically couple the vertically-spaced conductive regions to one another. Some embodiments include methods of forming assemblies.
G11C 7/10 - Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G11C 8/12 - Group selection circuits, e.g. for memory block selection, chip selection, array selection
G11C 11/56 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
G11C 16/08 - Address circuitsDecodersWord-line control circuits
G11C 19/32 - Digital stores in which the information is moved stepwise, e.g. shift registers using super-conductive elements
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
50.
BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES
Control logic can perform operations including obtaining, for each dummy wordline of a set of dummy wordlines, a respective set of step-up voltage parameters, wherein each set of step-up voltage parameters includes a step ratio corresponding to the dummy wordline, and causing a bias voltage with respect to each dummy wordline of the set of dummy wordlines to be ramped to a respective program inhibit bias voltage in accordance with the respective set of step-up voltage parameters. Additionally or alternatively, control logic can perform memory operations including causing a bias voltage with respect to each dummy wordline to be ramped to a power supply voltage during a seed first sub-phase of a pre-programming phase, and maintaining the bias voltage of the first dummy wordline at a first dummy wordline seed voltage throughout a bitline setting sub-phase of the pre-programming phase.
A semiconductor device assembly is provided. The assembly includes a substrate and a semiconductor device. The substrate includes a first conductive layer, the first conductive layer having a first trace with a first exposed pad and a second trace with a second exposed pad. A wire bond runs above the first conductive layer to connect the first exposed pad to the second exposed pad, such that the first trace and the second trace are only connected via the wire bond. The semiconductor device includes an electrical connection to the first trace.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/552 - Protection against radiation, e.g. light
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
52.
STACKED SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR DIES OF VARIABLE SIZE
A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
53.
DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES
Methods, systems, and devices for data routing for error correction in stacked memory architectures are described. A system may support error correction of bits of data communicated between a first semiconductor die (e.g., an array die) and a second semiconductor die (e.g., a logic die). For example, an interface of the second semiconductor die may receive data stored at a memory array of the first semiconductor die. The interface may include error correction engines each operable to correct one or more bit errors. The interface may also include logic circuitry operable to route physically-grouped subsets of the received data to respective error correction engines, and such subsets may be configured to allocate the error correction engines in manner that improves a likelihood that physically-grouped errors in the system can be corrected. The interface may output the data to a host system after the error control operations are performed.
Methods, systems, and devices for commands to support adaptive memory systems are described. A memory system may be configured to receive a command to perform an operation on an address of a memory system, the command including an indication of a count of program/erase cycles associated with the address; determine whether the count of program/erase cycles associated with the address satisfies a threshold; adjust a trim parameter for operating the memory system based at least in part on determining that the indication of the count of program/erase cycles satisfies the threshold; and perform the operation associated with the command using the adjusted trim parameter.
Semiconductor devices are disclosed. A semiconductor device may include a hybrid transistor configured in a vertical orientation. The hybrid transistor may include a gate electrode, a drain material, a source material, and a channel material operatively coupled between the drain material and the source material. The source material and the drain material include a first material, and the channel material includes a second, different material.
G11C 5/12 - Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 11/401 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
G11C 13/00 - Digital stores characterised by the use of storage elements not covered by groups , , or
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
H10D 86/40 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
H10D 86/60 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
H10N 70/00 - Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
H10N 70/20 - Multistable switching devices, e.g. memristors
56.
FOLDED ACCESS LINE FOR MEMORY CELL ACCESS IN A MEMORY DEVICE
Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a cross-point memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.
A memory array includes a block including wordlines, bitlines, and strings each connected to a respective bitline. The block is divided into a sub-blocks. Each sub-block includes a respective set of the strings, and each string of the set of strings is located at a sub-block position within its respective sub-block. Control logic performs operations including selecting each sub-block, causing a first voltage to be applied to a dummy wordline to activate a first set of dummy cells and deactivate a second set of dummy cells, and causing a second voltage to be applied to a selected wordline. Each sub-block includes a single string corresponding to an open string connected to a dummy cell of the first set of dummy cells. The second voltage causes data to be read out from each open string to a respective page buffer.
Memories having a controller configured to increase a voltage level applied to a data line and decrease a voltage level applied to a control gate of a transistor connected between the data line and a string of series-connected memory cells during a first period of time, increase the voltage level applied to the data line and increase the voltage level applied to the control gate of the transistor at a same rate in response to an end of the first period of time, and ceasing increasing the voltage level applied to the data line and ceasing increasing the voltage level applied to the control gate of the transistor in response to the voltage level applied to the data line reaching a predetermined voltage level.
Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/07 - Responding to the occurrence of a fault, e.g. fault tolerance
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
60.
APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATION
Apparatuses and methods for controlling sense amplifier operation are described. An example method includes providing a control signal having a first high logic level voltage to activate isolation switches of a sense amplifier. The control signal transitions from the first high logic level voltage to an inactive voltage to deactivate the isolation switches of the sense amplifier before accessing a memory cell. The control signal is provided having the first high logic level voltage to activate the isolation switches of the sense amplifier after accessing the memory cell. The control signal is increased from the first high logic level voltage to a second high logic level voltage.
G11C 11/4091 - Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
G11C 11/4093 - Input/output [I/O] data interface arrangements, e.g. data buffers
61.
BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS
Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H01L 25/075 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
An example apparatus includes a first circuit configured to activate a first control signal, a second circuit configured to activate a first timing signal after receiving the first control signal, a third circuit configured to receive the first timing signal from the second control circuit and return back the first timing signal to the second control circuit, a first signal line conveying the first control signal from the first circuit to the second circuit, a second signal line conveying the first timing signal from the second circuit to the third circuit, and a third signal line conveying the first timing signal from the third circuit to the second circuit. Each of the first to third signal lines is provided on first and second tracks extending in parallel with each other.
Erase operations can be performed selectively on one of erase blocks or a memory array coupled to the same string by creating a pseudo PN junction that is located adjacent to the selected erase block. The pseudo PN junction is created by including channel inversion at least on those portions of the string coupled to unselected erase blocks, which further creates a flow of electrons. As a result of the channel inversion (along with channel accumulation created adjacent to the channel inversion), the flow of gate induced drain leakage (GIDL) holes are further generated from the pseudo PN junction and GIDL holes are induced to tunnel into memory cells of the selected erase block.
A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.
Aspects of the present disclosure configure a system component, such as a memory sub-system controller, to perform adaptive read level threshold voltage operations. The controller determines a first read level offset associated with reading a first set of data from a first level using a first read level of a plurality of read levels. The controller applies the first read level offset to a machine learning model to estimate a second read level offset, associated with reading a second set of data from a second level of the plurality of levels, using a second read level of the plurality of read levels. The controller updates, based on the first read level offset and the estimated second read level offset, a look-up table that includes a set of read level offsets used to read data from the plurality of levels of the individual component.
A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method for modifying a geometry of a wafer comprises measuring a local geometry for each of a plurality edge locations of the wafer, determining, based on the measured local geometry, an amount of additional material for each of the plurality of locations of the wafer calculated to provide a desired wafer-level geometry for the wafer, and dispensing, from a printing nozzle, the determined amount of additional material at each of the plurality of locations of the wafer to provide the wafer with the desired wafer¬ level geometry.
H01L 21/302 - Treatment of semiconductor bodies using processes or apparatus not provided for in groups to change the physical characteristics of their surfaces, or to change their shape, e.g. etching, polishing, cutting
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/66 - Testing or measuring during manufacture or treatment
68.
MICROELECTRONIC DEVICES, MEMORY DEVICES, AND METHODS OF FORMING MICROELECTRONIC DEVICES
A microelectronic device including first insulative structures, each first insulative structure including first sections individually having a first horizontal width in a first direction, and second sections horizontally alternating with the first sections in a second direction orthogonal to the first direction, the second sections individually having a second horizontal width in the first direction greater than the first width. First conductive structures are directly adjacent the first sections of the first insulative structures in the first direction and directly adjacent the second sections of the first insulative structures in the second direction. Second insulative structures are directly adjacent the first conductive structures and the second sections of the first insulative structures in the first direction; and second conductive structures are directly adjacent the second insulative structures in the first direction.
An apparatus comprises a memory array comprising a plurality of physical blocks of memory cells each comprising more than two erase blocks, with each of the more than two erase blocks of each respective physical block comprising memory cells coupled to a same string of memory cells corresponding to the respective physical block. A controller can operate the memory array in accordance with a logical block implementation in which each logical block comprises: a first erase block adjacent to a first end of a particular string corresponding to a first physical block; and a second erase block. The second erase block is either: located in the first physical block and not adjacent to a second end of the particular string corresponding to the first physical block; or located in a second physical block and adjacent to a first end of a particular string corresponding to the second physical block.
Apparatuses and methods for performing read operations on partially programmed blocks are provided. One example apparatus can include a controller configured to apply a read voltage to the first inner word line in the array of memory cells during a read operation on the first inner word line, apply a first pass voltage to a second inner word line adjacent to the first inner word line and to a third inner word line adjacent to the first inner word line, apply a second pass voltage to a number of unprogrammed word lines in the array of memory cells in response to determining the read request is for data stored on the first inner word line of the partially programmed block, and apply a third pass voltage to a first number of inner word lines of the number of word lines that are nonadjacent to the first inner word line.
Apparatuses and methods for performing sensing operations on partially programmed erase blocks are provided. One example apparatus can include a memory array comprising a plurality of erase blocks and a controller coupled to the memory array. The controller can be configured to apply a first sensing voltage to a first access line of a first group of access lines corresponding to the first erase block during a first sensing operation on the first erase block that is partially programmed, apply a first pass voltage to a number of programmed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation, and apply a second pass voltage a number of unprogrammed access lines of the first group of access lines corresponding to the first erase block during the first sensing operation.
A processing unit can include an activation function unit. Data can be received at a plurality of registers of a processing unit of a memory sub-system. The data can be received at a multiply-accumulate (MAC) unit coupled to the plurality of registers. The first plurality of operations can be performed at the MAC unit to generate a first output. The first output can be provided to the activation function unit. The first output can be provided from the AFU to the plurality of registers utilizing a bus or a signal line that couples the plurality of registers to the AFU.
Implementations described herein relate to a power hold-off circuit and power hold-off circuit operation. In some implementations, a system may include a battery, and a power hold-off circuit. The power hold-off circuit may include a step-up regulator, a step-down regulator, a first abrupt power-loss (APL) switch, a second APL switch, and one or more power hold-off capacitors. The system may include a third APL switch between the battery and the power hold-off circuit. The third APL switch and the first APL switch may be in a closed state, and the second APL switch may be connected to the step-up regulator, when a voltage from the battery satisfies a voltage threshold. The third APL switch and the first APL switch may be in an open state, and the second APL switch may be connected to the step-down regulator, when the voltage from the battery does not satisfy the voltage threshold.
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
74.
STACKED SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR DIES OF VARIABLE SIZE
A semiconductor device assembly is disclosed. The semiconductor device assembly includes a first semiconductor die and second semiconductor dies and an additional semiconductor component coupled with the logic die. Dielectric peripheral material is disposed along sidewalls of the first die and extends beyond a first footprint of the first die. A gap fill material is disposed at the first die and at the dielectric peripheral material beyond a second footprint of the second semiconductor dies and a third footprint of the additional semiconductor component such that the gap fill material at least partially surrounds the second semiconductor dies and the additional semiconductor component.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
Systems, methods, and apparatus for a memory device having test mode state machines configured to perform self-testing. In one approach, a memory array has memory cells. Periphery logic of the memory device receives a command from a host device to initiate self-testing. The periphery logic generates trigger signal(s) in response to receiving the command. Control circuitry (e.g., a controller) has state machine(s) that receives the trigger signal(s) and initiates execution of a command sequence. The command sequence includes various orders of operations such as read, write, or delay. A state machine can be integrated into each of multiple partitions of the memory array.
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.
H10B 43/50 - EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/50 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
77.
WAFER CARRIER WITH RETICLE TEMPLATE FOR MARKING RETICLE FIELDS ON A SEMICONDUCTOR WAFER
A wafer carrier assembly comprising a wafer carrier having a first and second side, the first side including: a circular recess configured to receive a semiconductor device wafer, and at least one cut-out arranged along the circumference of the circular recess. The first side also includes a carrier cover having a top and bottom side, the top side including: a plurality of gridlines extending to edges of the carrier cover, and a plurality of reticles extending from the top side to the bottom side where subsets of reticles are arranged to have a common center and each subset of reticles is arranged at each intersection of the plurality of gridlines.
H01L 21/673 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components using specially adapted carriers
G03F 1/44 - Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
78.
MONOLITHIC CONDUCTIVE COLUMNS IN A SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS
A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
79.
METHODS AND SYSTEMS FOR HANDLING DATA RECEIVED BY A STATE MACHINE ENGINE
A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 9/448 - Execution paradigms, e.g. implementations of programming paradigms
Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.
An electronic device comprises a stack comprising tiers of alternating conductive structures and insulative structures overlying a source tier, and strings of memory cells extending vertically through the stack. The strings of memory cells individually comprise a channel material extending vertically through the stack. The electronic device comprises an additional stack overlying the stack and comprising tiers of alternating additional conductive structures and additional insulative structures, and pillars extending through the additional stack and overlying the strings of memory cells. Each of the pillars is horizontally offset in a first horizontal direction and in a second horizontal direction transverse to the first horizontal direction from a center of a corresponding string of memory cells. The electronic device comprises conductive lines overlying the pillars, and interconnect structures directly contacting the pillars and the conductive lines. Related electronic devices, systems, and methods are also described.
H01L 23/528 - Layout of the interconnection structure
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
82.
Integrated Assemblies and Methods of Forming Integrated Assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 21/033 - Making masks on semiconductor bodies for further photolithographic processing, not provided for in group or comprising inorganic layers
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H10B 41/20 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
H10B 41/23 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.
The present disclosure includes apparatuses, methods, and systems for partitioning system data from user data in memory. In an example, a method can include receiving system data at a memory, assigning the system data a first address within a first range of memory addresses, storing the system data in a first portion of the memory operated with a first set of trim settings in response to the system data having the first address within the first range of memory addresses, receiving user data, assigning the user data a second address within a second range of memory addresses, and storing the user data in a second portion of the memory operated with a second set of trim settings in response to the user having the second address within the second range of addresses.
Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/528 - Layout of the interconnection structure
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
87.
Memory Arrays Comprising Vertically-Alternating Tiers of Insulative Material and Memory Cells and Methods of Forming a Memory Array
A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. The capacitor comprises a first electrode electrically coupled to a source/drain region of the transistor. The first electrode comprises an annulus in a straight-line horizontal cross-section and a capacitor insulator radially inward of the first electrode annulus. A second electrode is radially inward of the capacitor insulator. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. A sense line is electrically coupled to another source/drain region of multiple of the transistors that are in different memory-cell tiers. Additional embodiments and aspects are disclosed, including methods.
G11C 11/24 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using capacitors
G11C 5/02 - Disposition of storage elements, e.g. in the form of a matrix array
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
H10B 12/00 - Dynamic random access memory [DRAM] devices
H10B 51/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
H10B 53/20 - Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
Mold chases for molding semiconductor devices and/or components of semiconductor devices, the resulting semiconductor devices and/or their components, and related systems and methods are disclosed herein. In some embodiments, the mold chase includes a first clamp and a second clamp having a substrate engaging surface oriented towards the first clamp. The substrate engaging surface can have a hybrid surface texture that includes a first region and a second region at adjacent the first region (on a lateral side of the first region). The first region can include a first surface texture that is relatively smooth. The second region can include a second surface texture that is relatively rough compared to the first surface texture. The first surface texture can prevent mold bleed during a molding process. The second surface texture can reduce electrostatic discharge events during an ejection from the mold chase.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
89.
Memory Access Control through Permissions Specified in Page Table Entries for Execution Domains
Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.
G06F 12/1009 - Address translation using page tables, e.g. page table structures
G06F 9/455 - EmulationInterpretationSoftware simulation, e.g. virtualisation or emulation of application or operating system execution engines
G06F 12/14 - Protection against unauthorised use of memory
G11C 8/20 - Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access
G11C 11/16 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
90.
SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICE ASSEMBLIES WITH INK-JET PRINTED CONDUCTIVE PADS AND METHODS FOR MAKING THE SAME
A method for forming a semiconductor device assembly is described. The method comprises vertically stacking at least one semiconductor device over a substrate; and ink-jet printing, after vertically stacking the at least one semiconductor device, a conductive pad on an exposed conductor of the at least one semiconductor device or of the substrate. The method can further include testing an electrical circuit of the semiconductor device assembly by electrically probing the electrical circuit through the conductive pad.
H01L 21/66 - Testing or measuring during manufacture or treatment
B41M 5/00 - Duplicating or marking methodsSheet materials for use therein
B41M 7/00 - After-treatment of printed works, e.g. heating, irradiating
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
Methods, systems, and apparatuses for storing operational information related to operation of a non-volatile array are described. For example, the operational information may be stored in a in a subarray of a memory array for use in analyzing errors in the operation of memory array. In some examples, an array driver may be located between a command decoder and a memory array. The array driver may receive a signal pattern used to execute an access instruction for accessing non-volatile memory cells of a memory array and may access the first set of non-volatile memory cells according to the signal pattern. The array driver may also store the access instruction (e.g., the binary representation of the access instruction) at a non-volatile subarray of the memory array.
G06F 11/20 - Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 11/14 - Error detection or correction of the data by redundancy in operation, e.g. by using different operation sequences leading to the same result
G11C 11/22 - Digital stores characterised by the use of particular electric or magnetic storage elementsStorage elements therefor using electric elements using ferroelectric elements
G11C 29/12 - Built-in arrangements for testing, e.g. built-in self testing [BIST]
G11C 29/36 - Data generation devices, e.g. data inverters
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
G11C 29/44 - Indication or identification of errors, e.g. for repair
G11C 29/52 - Protection of memory contentsDetection of errors in memory contents
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers of respective memory cells and control gates, the tier located one over another over a substrate, the control gates including a control gate closest to the substrate, the control gates including respective portions forming a staircase structure; conductive contacts contacting the control gates at a location of the staircase structure, the conductive contacts including a conductive contact contacting the control gate; a dielectric structure located on sidewalls of the control gates; and support structures adjacent the conductive contacts and having lengths extending vertically from the substrate, the support structures including a support structure closest to the conductive contact, the support structure located at a distance from an edge of the dielectric structure, wherein a ratio of a width of the support structure over the distance is ranging from 1.6 to 2.0.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
A system and method for a memory sub-system to reduce latency by prefetching data blocks and preloading them into host memory of a host system. An example system including a memory device and a processing device, operatively coupled with the memory device, to perform operations including: receiving a request of a host system to access a data block in the memory device; determining the data block stored in a first buffer in host memory is related to a set of one or more data blocks stored at the memory device; and storing the set of one or more data blocks in a second buffer in the host memory.
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
G11C 16/04 - Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/10 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 41/40 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
H10B 43/10 - EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
H10B 43/40 - EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Techniques for electronic memory are described. A method for forming a memory array may include forming memory cells, a dielectric material between word lines, and a sealing material on sidewalls of the dielectric material. The method may also include removing at least a portion of the sealing material to expose the dielectric material. Also, the method may include forming one or more voids in the dielectric material, where the one or more voids may separate the word lines from one another. The memory array may include the memory cells, the word lines, pillars, and piers, where the word lines may be separated from one another by the one or more voids to form air gaps.
A system includes a memory device; and a processing device coupled to the memory device, the processing device to perform operations including: identifying at least one unusable management unit (UMU) in a plurality of management units that are designated for wear leveling; storing, in a data structure, a physical address and a logical address of the identified at least one UMU; excluding, from a physical address space for wear leveling, the physical address of the identified at least one UMU; and performing a wear leveling operation using the physical address space, wherein the wear leveling operation moves data of a management unit to a neighboring management unit in a circular manner.
Methods, systems, and apparatuses include determining, by a memory subsystem, use model statistics for a memory portion of the memory subsystem, where the use model statistics include a count of commands received by the memory subsystem from a host system targeting the memory portion and details about the memory subsystem. It is determined that the memory subsystem is powering down. The use model statistics are stored in a use model statistics storage of the memory subsystem by the memory subsystem in response to determining that the memory subsystem is powering down.
A variety of applications can include a memory device having an array of memory cells, with each of the memory cells having a gate-all-around (GAA) transistor arranged as a hexagonal vertical channel transistor coupled to a capacitor. Access lines can be coupled to gates of the GAA transistors and digit lines can be coupled to pillar channels of the GAA transistors. A lattice can be included between the access lines and the digit lines, where the lattice has dielectric regions between and contacting non-dielectric regions. Each non-dielectric region can be positioned on and contacting a digit line and can contain digit contact junctions to the pillar channels of a set of the GAA transistors extending from the non-dielectric region. Additional devices and methods are disclosed.
A variety of applications can include a memory device having an array of memory cells arranged as hexagonal cells, with each of the memory cells having a gate-all-around (GAA) transistor coupled to a capacitor. An access line can be coupled to gates of a first set of multiple GAA transistors of the memory cells. A digit line can be coupled to a second set of multiple GAA transistors of the memory cells, where the digit line is separated from an adjacent digit line by an airgap. Additional devices and methods are disclosed.
