Methods, systems, and devices for enhancements for multiple data plane read commands are described. In some examples, a memory system may receive a set of multiple read commands and may determine whether a quantity of planes associated with the set of multiple read commands satisfies a threshold. Based on determining that the quantity of planes satisfies a threshold, the memory system may output a multi-plane read command. A memory device may obtain a multi-plane read command and may initiate a first transfer for a first plane based on obtaining the multi-plane read command. The memory device may then generate one or more single-plane commands for one or more planes associated with the multi-plane read command and may initiate a respective data transfer for each of the one or more planes.
Methods and apparatus for performing multi-step image processing using a reconfigurable fabric device (RFD) in place of multiple discrete ICs. In one embodiment, the methods and apparatus operate according to a flexible time-divided schedule, and the processing is configured to process image sensor data by at least: (i) receiving RAW image data, programming an RFD to operate as a first functional unit such as an image signal processor (ISP), using the programmed RFD to perform image signal processing on the RAW image data, storing the ISP-result in temporary memory; and (ii) programming the RFD to operate as a second functional unit (e.g., deep learning accelerator (DLA)), using the programmed RFD to read out ISP-result from the temporary memory, perform deep learning processing on the ISP-result, and storing the DLA-result back into the temporary memory. In one variant, an on-die controller and memory are used in support of the RFD operations, thereby enabling a single-die processing solution.
Aspects of the present disclosure are directed to systems and methods to reduce inductance on an integrated circuit package of a memory sub-system. A memory sub-system is also hereinafter referred to as a “memory device.” An example of a memory sub-system is a storage system, such as a SSD, and can be embodied as an integrated circuit package, including but not limited to a pin grid array (PGA), and ball grid array (BGA).
H01L 23/528 - Layout of the interconnection structure
G11C 5/06 - Arrangements for interconnecting storage elements electrically, e.g. by wiring
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
4.
Apparatuses, Systems, and Methods for Authentication of a Memory Module
A memory module includes one or more memory devices and a module logic chip. The module is coupled to a host which operates the memory devices. Certain features of the module may only be accessible once the module has authenticated with the host. For example, the module logic chip may perform asymmetric authentication with the host and the feature may be enabled only after successful authentication. In some embodiments, the module logic may additionally authenticate the memory devices. For example, the module logic chip may perform symmetric authentication on the memory devices after authentication with the host.
Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.
The present disclosure relates to operating an array of memory cells, including storing user data in a plurality of memory cells of the memory array, storing parity data associated with the user data in parity cells of the memory array, in which a number of used parity cells is selected based on a status of the memory cells and is related to a selected Error Correction Code (ECC) correction capability, and performing an ECC operation on the plurality of memory cells, the ECC correction capability being based on the selected number of used parity cells. Related memory devices and systems are also herein disclosed.
Methods, systems, and devices for self-refresh exit detection for memory devices are described. The described techniques provide for a memory system to indicate whether the memory system is in a self-refresh mode or not. The memory system may initiate a self-refresh operation for one or more memory cells of the memory system. The memory system may set a mode register to a first value based on initiating the self-refresh operation. The first value of the mode register may indicate that the self-refresh operation is being executed. The memory system may determine whether to reset the mode register to a second value based on a status of the self-refresh operation. The second value of the mode register may indicate that the self-refresh operation is complete. A host system may poll the mode register to determine the status of the self-refresh operation at the memory system.
An erase operation on a block of a memory device is performed. Whether a program after erase mode is enabled is determined. A programming operation associated with the program after erase mode is performed on an erase distribution of the block responsive to determining that the program after erase mode is enabled.
A first decoding parameter is obtained responsive to the determining that the codeword contains errors. The first decoding parameter includes a first likelihood set and a first transformation set. A decoding operation with the first decoding parameter is performed. A second decoding parameter is obtained responsive to determining that the decoding operation did not correct the errors of the codeword. The second decoding parameter includes a second likelihood set and a second transformation set. The decoding operation with the second decoding parameter is performed.
Systems, methods, and apparatus related to data recovery in memory devices. In one approach, a memory device encodes stored data. The memory device reads a codeword from a storage media and determines that a number errors in the codeword exceeds an error correction capability of the memory device. The errors are due, for example, to one or more stuck bits. In response to this determination, one or more data patterns are written to the storage media at the same address from which the codeword is read. The data patterns are read to identify bit locations of the stuck bits. The identified locations are used to correct bit errors of the read codeword that correspond to the identified locations. The corrected code word is sent to a host device (e.g., which requested data from the memory device using a read command).
G06F 11/10 - Adding special bits or symbols to the coded information, e.g. parity check, casting out nines or elevens
G06F 12/0804 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
11.
DIE-TO-DIE PROBE PAD CONNECTION IN A STACKED SEMICONDUCTOR DEVICE
Methods, systems, and devices for die-to-die probe pad connection in a stacked semiconductor device are described. The stacked semiconductor device may include a first probe pad that is on a physically accessible surface of a stack of semiconductor dies. The stacked semiconductor device may include a second probe pad located at a physically inaccessible surface of (e.g., within) the stack of semiconductor dies. And the stacked semiconductor device may include a conductive path that electrically couples the first probe pad with the second probe pad.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
12.
SEMICONDUCTOR DEVICE WITH BACKSIDE CONNECTION MECHANISM AND METHODS FOR MANUFACTURING THE SAME
Methods, apparatuses, and systems related to a memory device having on its backside one or more integrally-formed structures is described. A memory device may include a backside pad-via structure, a backside redistribution layer structure, or a combination thereof. Such backside structures may include integrally-formed portions that extend in different directions to laterally route electrical signals on the backside.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.
Apparatuses, machine-readable media, and methods related to vehicle diagnosis and repair are described. Receiving vehicle status information from a control panel and/or on board diagnostic (OBD) unit of a vehicle at a vehicle diagnosis and repair too can provide valuable information to an owner and/or user of a vehicle. Computing devices (e.g., mobile devices and/or modules having a computing device) can be configured to run an application (e.g., a vehicle diagnosis and repair tool) to determine whether a vehicle needs to be repaired or serviced according to examples of the present disclosure. The vehicle diagnosis and repair tool can receive vehicle status information, determine the repairs and/or service that the vehicle needs, and initiate the vehicle repairs and/or service.
G07C 5/00 - Registering or indicating the working of vehicles
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
A method includes identifying and tracking host threads. A read command is received including a first logical block address (LBA). The first LBA and a first stored LBA in a cache are determined to share a spatial locality. The first LBA and the first stored LBA share a spatial locality when the first LBA is within a predetermined number of LBAs from the first stored LBA. The first stored LBA is removed from the cache responsive to the determination that the first LBA and the first stored LBA share the spatial locality. The first LBA is then added to the cache.
G06F 3/06 - Digital input from, or digital output to, record carriers
G06F 12/0862 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
16.
METHODS TO IMPROVE SECURITY OF MULTI-TENANT MEMORY MODULES
An example system includes a host computing device configured to host a first tenant and a second tenant, non-volatile memory configured to store data for the first tenant and data for the second tenant, and a memory controller including a cache of a volatile memory configured to store a first encrypted key associated with the first tenant used to access the data stored at the non-volatile memory and a second encrypted key associated with a second tenant used to access the data stored at the non-volatile memory. The memory controller further includes a processor having encryption logic configured to detect an attack on a portion of the cache storing the second encrypted key by the first tenant, and to erase the stored second encrypted key from the cache in response to detection of the attack.
A method of transmitting a data packet from a first virtualized server to a second virtualized server includes copying, by the first virtualized server, the data packet into a send queue associated with the first virtualized server, where the send queue is located at a fabric attached memory, where the fabric attached memory is accessible by the first virtualized server and the second virtualized server. The method further includes retrieving, by one or more processors associated with the fabric attached memory, the data packet from the send queue and forwarding, by the one or more processors, the data packet to a receive queue associated with the second virtualized server, where the receive queue is located at the fabric attached memory. The method further includes retrieving, by the second virtualized server, the data packet from the receive queue.
H04L 43/20 - Arrangements for monitoring or testing data switching networks the monitoring system or the monitored elements being virtualised, abstracted or software-defined entities, e.g. SDN or NFV
H04L 41/40 - Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks using virtualisation of network functions or resources, e.g. SDN or NFV entities
H04L 49/901 - Buffering arrangements using storage descriptor, e.g. read or write pointers
18.
VALID WRITE OPERATION DETECTION FOR MEMORY DEVICES
Methods, systems, and devices for valid write operation detection for memory devices are described. The described techniques provide for a memory system to set a flag in accordance with a status of an access operation. The memory system may receive a command to write data and may adjust a value of a mode register based on whether a write operation is valid. In some examples, the memory system may set the mode register value after successfully receiving, decoding, or completing the write command. In some other examples, if the memory system experiences a fault in receiving, decoding, or executing the write command, the memory system may refrain from setting the mode register value. A host device may poll the mode register to identify the validity of the write operation, and may perform one or more corrective actions if the write operation is invalid.
A memory access request is initiated by a first peripheral device. The memory access request includes a virtual address. A host physical address (HPA) associated with the virtual address is determined. An identifier of a base address register (BAR) associated with the HPA is determined by the first peripheral device. The memory access request is transmitted using the identifier of the BAR to a second peripheral device.
Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
21.
APPARATUSES AND METHODS FOR ALIASING IN DEVICE LEVEL ERROR CORRECTION BASED ON MODULE LEVEL ERROR CORRECTION
A memory module includes a number of memory devices. During a read operation the memory device reads data and parity bits. An error correction circuit of the memory device determines if there is an uncorrectable error in the data and parity bits. If there is an uncorrectable error, the error correction circuit aliases a bit within a specified subset of the data bits. The specified subset may be based on which patterns of errors are correctable by a module level error correction scheme.
A method includes identifying and tracking host threads. A read command is received including a first logical block address (LBA). The first LBA and a first stored LBA in a cache are determined to share a spatial locality. The first LBA and the first stored LBA share a spatial locality when the first LBA is within a predetermined number of LBAs from the first stored LBA. The first stored LBA is removed from the cache responsive to the determination that the first LBA and the first stored LBA share the spatial locality. The first LBA is then added to the cache.
Methods, systems, and devices for write buffer flush techniques are described. A memory system may be triggered to flush (e.g., transfer, write) data from a volatile memory device to a non-volatile memory device of the memory system. The memory system may support flushing data to blocks including single level cells (SLCs) or blocks including multiple-level memory cells. The memory system may determine whether a quantity of the data to be flushed satisfies a threshold quantity of data. If the quantity of data fails to satisfy the threshold quantity of data, the memory system may flush the data to a block including SLCs, which may be referred to as a small chunk SLC cursor. The SLC cursor may temporarily store the flushed data, such as at least until the threshold quantity of data is satisfied in the volatile memory device and/or to data recovery in case of a power loss event.
Methods, systems, and devices for receiver decision feedback equalization calibration are described. A memory system may support implementing respective decision feedback equalization (DFE) values at respective receivers using interpolation logic. For example, a calibration circuit may generate and store a quantity of candidate voltage values corresponding to the application of different DFE values at the receivers. The memory system may use the interpolation logic to generate (e.g., interpolate, generate) respective voltage values corresponding to a DFE value for application at a respective receiver based on the stored candidate voltage values. The interpolation logic may output the voltage values via a serial bus to each receiver, and each receiver may apply, to respectively received data, a DFE value corresponding to a respectively received voltage value.
A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.
An example apparatus including a first, second, third, and fourth inverter, each having an input and an output; a first wiring structure including a first wiring portion in an upper wiring layer, the first wiring structure coupled to the input of the first inverter; a second wiring structure including a second wiring portion in the lower wiring layer, the second wiring structure coupled to the output of the first inverter and the input of the second inverter; and a third wiring structure including a third wiring portion in the upper wiring layer, the third wiring structure coupled to the output of the second inverter and the input of the third inverter. The first wiring portion and the second wiring portion partially overlap with each other; and wherein the second wiring portion and the third wiring portion partially overlap with each other.
An apparatus includes circuitry configured to generate multiple results, each result using a different read voltage, in response to a data access command. The multiple read results may be used to dynamically calibrate a read level voltage.
Devices and techniques for thread replay to preserve state in a barrel processor are described herein. An apparatus includes a barrel processor, which includes a temporary memory; and a thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle; store the current thread in the temporary memory; detect that no thread is available on a clock cycle subsequent to the cycle that the current thread is scheduled; and in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on the contents of the temporary memory.
G06F 9/50 - Allocation of resources, e.g. of the central processing unit [CPU]
G06F 12/0875 - Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
Methods, systems, and devices for distributed power up for a memory system are described. The method may include a memory system receiving, from a host system, a command to initialize a set of memory devices included in a memory system. Upon receiving the command, the memory system may select a first memory device from the set of memory devices and read, from a second memory device in a controller separate from the set of memory devices, a first operational parameter corresponding to the first memory device. The memory system may then read, from the first memory device, a set of second operational parameters, each second operational parameter of the set of second operational parameters corresponding to a respective memory device of the set of memory devices.
Methods, systems, and apparatuses include receiving, by a memory subsystem, a power down notification. A memory usage pattern for the memory subsystem is retrieved in response to receiving the power down notification. A power mode is selected using the current time and the memory usage pattern. The selected power mode is enabled.
Various embodiments provide for page-level and stripe-based read error handling for a memory system, such as a memory sub-system. For various embodiments, the page-level and stripe-based read error handling reduces the overall latency of a read error handling process (e.g., a multi-stage REH process). Additionally, various embodiments reduce the amount of memory space (e.g., buffer space) used during the stripe-based read error handling.
Methods, systems, and apparatuses include detecting a failure to decode a first codeword, the first codeword including user data and first level parity data for the user data. A second codeword is read in response to the detected failure, the second codeword including second level parity data for the user data. A first set of one or more reliability values is selected for the second level parity data, the first set of reliability values differing from a second set of reliability values for the user data and the first level parity data. The user data is decoded using the first level parity data, the second level parity data, the selected first set of reliability values, and the second set of reliability values.
Methods, systems, and devices for shared parity release and reconstruction are described. A memory system may receive a command to store data to non-volatile memory associated with the memory system. The memory system may write the data to the non-volatile memory device at a location indicated by one or more cursors in a volatile memory of the memory system and generate first parity information based on the data. The memory system may determine that a size of the data indicated by the one or more cursors satisfies a threshold and may release the first parity information from the volatile memory. The memory system may generate second parity information using a portion of the data associated with the first parity information.
A memory sub-system, such as a solid-state drive, configured to map a write stream to superblocks without the stream identifying a zone having a predetermined size in a namespace. The memory sub-system is configured to maintain, for the stream, a cursor configured to identify one of the plurality of superblocks as being reserved entirely for the stream; map, based on a superblock identified by the cursor, logical addresses of write commands in a contiguous segment of the stream to physical addresses in the superblock until the superblock is full; store data of write commands in the stream into based on mapping from logical addresses to physical addresses identified via the cursor; and allocate, for the cursor and in response to the superblock identified by the cursor being full, a free superblock available to continue mapping logical addresses to physical address.
A method can comprise applying, to program memory cells of a first erase block coupled to a first string of a memory array, a seed voltage through a sense line coupled to the first string. The method can further comprise applying, to program memory cells of the first erase block sequentially from a source side to a drain side, a respective programming voltage to access lines of the first erase block sequentially from a first access line of the first erase block to a second access line of the first erase block. The first access line can be located adjacent to one or more dummy access lines separating the first erase block from a second erase block coupled to the first string. The second access line can be located at the drain side of the first string.
Implementations described herein relate to temperature-based charge pump control. In some implementations, a memory device may comprise one or more components configured to receive a command to perform an operation. The memory device may comprise one or more components configured to detect, responsive to receiving the command, a temperature associated with the memory device. The memory device may comprise one or more components configured to selectively configure, based on the temperature, a clock frequency of a charge pump of the memory device.
G11C 7/04 - Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
G11C 7/22 - Read-write [R-W] timing or clocking circuitsRead-write [R-W] control signal generators or management
Methods, systems, and devices for techniques for memory cell degradation protection are described. In some cases, a memory system may perform a protection operation on blocks of memory cells in response to monitoring the temperature of the memory system. For example, the memory system may monitor the temperature associated with the system over a duration. If the temperature exceeds a threshold, a counter may be adjusted by a first value. If the counter exceeds a second threshold, the memory system may trigger one or more protection operations on the blocks of memory cells. These protection operations may include programming a data pattern to each block of memory cells.
Memory controller commands to be sent to a memory device may be prioritized based one or more factors. For instance, a memory controller may employ a first-ready, first-come, first-served (FRFCFS) policy in which certain types of commands (e.g., read) are prioritized over other types of commands (e.g., write). The policy may be modified so when deciding which bank to open, the bank with the oldest read command is opened. While continuing to issue commands per this modified FRFCFS policy, the controller may keep track of banks whose pages are ready to receive their respective read commands. Once a number of ready banks meets or exceeds a threshold, issuance of write commands are paused and read commands for the ready banks are issued.
Processing logic in a memory sub-system receives a request to execute a programming operation to program cells of a memory device to a set of programming levels. The processing logic executes a first program verify loop associated with a programming level of the set of programming levels, where the first program verify loop comprises applying an initial bitline voltage to a subset of the cells having a threshold voltage in a range between a pre-program verify voltage and a program verify voltage. The processing logic executes a subsequent program verify loop associated with the programming level, wherein the subsequent program verify loop comprises applying an adjusted bitline voltage to the subset of the cells.
The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 43/27 - EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10D 84/03 - Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
41.
PAGE REQUEST INTERFACE SUPPORT IN HANDLING HOST SUBMISSION QUEUES AND COMPLETION AUTOMATION ASSOCIATED WITH CACHING HOST MEMORY ADDRESS TRANSLATION DATA
A memory sub-system controller includes a host queue interface circuit to interact with submission queues of a host system, an address translation circuit to handle address translation requests sent to the host system from the host queue interface circuit, and a cache to store address translations associated with the address translation requests. The host queue interface circuit pauses command fetch arbitration on a submission queue of the host system that is targeted by an address translation request that has missed at the cache and causes a page request interface (PRI) handler to send a page miss request to a translation agent of the host system. The host queue interface circuit further receives a restart message from the PRI handler upon the PRI handler receiving a page miss response from the translation agent and restarts command arbitration on the submission queue.
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
Disclosed in some examples are improvements to data placement architectures in NAND that provide additional data protection through an improved NAND data placement schema that allows for recovery from certain failure scenarios. The present disclosure stripes data diagonally across page lines and planes to enhance the data protection. Parity bits are stored in SLC blocks for extra protection until the block is finished writing and then the parity bits may be deleted.
G11C 16/26 - Sensing or reading circuitsData output circuits
G11C 29/42 - Response verification devices using error correcting codes [ECC] or parity check
H03K 19/02 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
43.
MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS IN MEMORY DEVICES
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a set of write operations on a first block in a first plane of the memory device and on a second block in a second plane of the memory device, performing a program verification check on the first block, and responsive to determining that the first block fails the program verification check, retiring the first block and the second block.
Control circuitry is coupled to a first voltage regulation circuit and a second voltage regulation circuit. The control circuitry determines whether a signal criterion is met or not. In response to the determination that the signal criterion has been met, the control circuitry controls application of a current generated by first voltage regulation circuit and the second voltage regulation circuit to adjust a ratio between current levels corresponding to the signals generated by the first and second voltage regulation circuits.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/567 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation
G05F 1/573 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overcurrent detector
Systems, methods and apparatus are provided for bi-directional I/O bandwidth enhancement via capacitive reactance reduction. An example apparatus can comprise a first signal driver of a transceiver, a second signal driver of the transceiver, an input/output (I/O) pad, and a y-coil, wherein the y-coil includes a first inductor coupled to the first signal driver of the transceiver, a second inductor coupled to the second signal driver of the transceiver, and a third inductor coupled to the I/O pad.
H04B 1/58 - Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.
An active drop scheme is selected from multiple drop schemes based on the active drop scheme having an associated drop request. The active drop scheme is associated with a first flash translation layer (FTL) table. A drop group is selected based on the active drop scheme. The drop group includes multiple segments of the first FTL table. The drop group is flushed to a memory device. Mapping information for the drop group is updated in a second FTL table based on flushing the drop group to the memory device.
Customization of deep learning models for accelerators of multiplication and accumulation operations. Based on a type of an accelerator to be used to implement the computation of an artificial neural network, a weight matrix of an artificial neural network can be adjusted, during training or via re-training, based on energy consumption characteristics of the type of accelerators. Patterns of weights that can consume more energy in computations implemented via the accelerator can be suppressed via penalizing by a loss function during training, or via pruning and re-training. The adjusted weight matrix can be configured in a computing device having an accelerator of the type. When the computing device performs computations of the artificial neural network using the weight matrix, the accelerator can be used to accelerate multiplication and accumulation operations involving the weight matrix.
Systems and methods are provided for trimming RTTs in a memory device. The effective termination resistance (RTT) of the ODT may be adjusted by adjusting one or more driver units having predefined values (e.g., 240Ω). Because PVT characteristics may impact the driver unit values, resistances of the driver units may be fluctuated away from the predefined values (e.g., 240Ω). ZQ calibration signals may be used to calibrate the resistances of the driver units to the predefined values (e.g., 240Ω) to trim the RTTs. Separate ZQ calibration signals may be generated for different circuits (e.g., a circuit associated with DQ pad, a circuit associated with CA pad).
Systems and methods are provided for trimming RTTs in a memory device. The effective termination resistance (RTT) of the ODT may be adjusted by adjusting one or more driver units having predefined values (e.g., 240 Ω. Because PVT characteristics may impact the driver unit values, resistances of the driver units may be fluctuated away from the predefined values (e.g., 240 Ω. ZQ calibration signals may be used to calibrate the resistances of the driver units to the predefined values (e.g., 240 Ω to trim the RTTs. Separate ZQ calibration signals may be generated for different circuits (e.g., a circuit associated with DQ pad, a circuit associated with CA pad). In addition, two ZQ calibration signals may be generated simultaneously by a ZQ circuit during the same time period.
A method of forming a microelectronic device includes forming first trenches in a semiconductor structure having semiconductor pillars interposed therebetween, and forming first insulative structures having a second insulative structure therein in the first trenches. The method also includes forming first conductive structures adjacent first ends of the semiconductor pillars and portions of the first insulative structures, and forming masks adjacent the first conductive structures and exposed portions of the first insulative structures, an uppermost mask being a neutral layer mask used to form a polymeric mask via directed self-assembly. The method further includes forming second trenches utilizing the polymeric mask, and removing portions of the first conductive structures exposed by third trenches to form first conductive members having openings therebetween. The method also includes forming second conductive structures adjacent sidewalls of the semiconductor pillars, and forming third conductive structures adjacent second ends of the semiconductor pillars.
An active drop scheme is selected from multiple drop schemes based on the active drop scheme having an associated drop request. The active drop scheme is associated with a first flash translation layer (FTL) table. A drop group is selected based on the active drop scheme. The drop group includes multiple segments of the first FTL table. The drop group is flushed to a memory device. Mapping information for the drop group is updated in a second FTL table based on flushing the drop group to the memory device.
Methods, systems, and devices for read disturb charge loss handling are described. A memory system may be configured to perform a scan to identify errors from voltage threshold shift, due to performing read operations at high temperatures. The scan may be initiated based on detecting an operating temperature of the memory system and that a memory die of the memory system is unreliable. The memory system may determine a frequency for performing the scan, and perform the scan based on satisfying a threshold associated with the frequency. The scan may include scanning pages associated with word lines to determine whether a quantity of errors satisfies a threshold. After satisfying the threshold, the memory system may fold a block associated with the quantity of errors. In some examples, the pages scanned may be selected based on a priority level defined by a type of memory cells associated with the word lines.
A variety of applications can include an apparatus having an electronic device including a number of transistors in a pair-wise arrangement that can enhance on-state current. The transistors of the pair can be structured as transistors having a single-gate separated by a gate dielectric from a vertical channel structure. The pair-wise arrangement can include multiple conductive shields between a channel structure of a transistor of the pair and a channel structure of the other transistor of the other pair. The multiple conductive shields can be stacked vertically on each other with each given conductive shield in the stack contacting another conductive shield above or below the given conductive shield. The multiple conductive shields can include a low work function material and a high work function material.
H10B 12/00 - Dynamic random access memory [DRAM] devices
55.
CONTROL OF MEMORY DEVICES OVER COMPUTER NETWORKS USING DIGITAL SIGNATURES GENERATED BY A SERVER SYSTEM FOR COMMANDS TO BE EXECUTED IN THE MEMORY DEVICES
A system, method and apparatus to control memory devices over computer networks. For example, a server system establishes a secure authenticated connection with a client computer system. Over the connection, the server receives from the client computer system a request identifying a memory device and determine, based on data stored in the server system, that the client computer system is eligible to control the memory device. In response to a request from the client computer system, the server system generates a digital signature for a command using at least a cryptographic key stored in the server system in association with the memory device. The client computer system receives the digital signature from the server system and submits the command with the digital signature to the memory device. The memory device validates the digital signature prior to execution of the command.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
G06F 3/06 - Digital input from, or digital output to, record carriers
The disclosed embodiments relate to securing operations accessing a non-volatile storage area of a memory device. In one embodiment, a method is disclosed comprising generating, by firmware of a memory device, a cryptographic key using a value of a physically unclonable function (PUF); writing, by the firmware, the cryptographic key to a volatile storage area; receiving, by the firmware, a command accessing a non-volatile storage area from a host processor; and processing, by the firmware, the command using the cryptographic key.
H04L 9/32 - Arrangements for secret or secure communicationsNetwork security protocols including means for verifying the identity or authority of a user of the system
57.
BOND PADS FOR SEMICONDUCTOR DIE ASSEMBLIES AND ASSOCIATED METHODS AND SYSTEMS
Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 41/27 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.
Described are systems and methods for prioritization of background media management operations in memory systems. An example system comprises a controller coupled to a memory array comprising a plurality of memory cells. The controller is configured to perform operations, comprising: identifying a plurality of address ranges referencing respective sets of memory cells of the memory array, wherein each address range is associated with a respective memory access operation counter reflecting a number of memory access operations that have been performed with respect to a corresponding set of memory cells; identifying, among the plurality of address ranges, an address range associated with a maximum value of a corresponding memory access operation counter; and causing a media management operation to be performed with respect to a set of memory cells referenced by the identified address range.
Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. For example, a microphone may be configured to execute instructions with matrix operands and configured with: a transducer to convert sound waves to electrical signals; an analog to digital converter to generate audio data according to the electrical signals; random access memory to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; and a controller to store the audio data in the random access memory as an input to the Artificial Neural Network. The Deep Learning Accelerator can execute the instructions to generate an output of the Artificial Neural Network, which may be provided as the primary output of the microphone to a computer system, such as a voice-based digital assistant.
G06N 3/10 - Interfaces, programming languages or software development kits, e.g. for simulating neural networks
G10L 17/00 - Speaker identification or verification techniques
G10L 17/04 - Training, enrolment or model building
G10L 25/30 - Speech or voice analysis techniques not restricted to a single one of groups characterised by the analysis technique using neural networks
G10L 25/63 - Speech or voice analysis techniques not restricted to a single one of groups specially adapted for particular use for comparison or discrimination for estimating an emotional state
H04R 1/04 - Structural association of microphone with electric circuitry therefor
Methods, systems, and devices for source line configurations for a memory device are described. In some cases, a memory cell of the memory device may include a first transistor having a floating gate for storing a logic state of the memory cell and a second transistor coupled with the floating gate of the first transistor. The memory cell may be coupled with a word line, a digit line, and a source line. During a write operation, the source line may be clamped to the digit line using one or more memory cells in the memory device. During a read operation, the source line may be grounded using one or more memory cells in the memory device.
A variety of applications can include an apparatus having an electronic device including a number of transistors in a pair-wise arrangement that can enhance on-state current. The transistors of the pair can be structured as transistors having a single-gate separated by a gate dielectric from a vertical channel structure. The pair-wise arrangement can include multiple conductive shields between a channel structure of a transistor of the pair and a channel structure of the other transistor of the other pair. The multiple conductive shields can be stacked vertically on each other with each given conductive shield in the stack contacting another conductive shield above or below the given conductive shield. The multiple conductive shields can include a low work function material and a high work function material.
A processing device in a memory sub-system receives a plurality of requests to write data to a non-volatile memory device, the plurality of requests comprising respective numbers of input/output (I/O) chunks of a fixed size, and performs a plurality of write operations to write the data to the non-volatile memory device using respective translation units, wherein the respective translation units comprise two or more different translation unit sizes selected based on the respective numbers of I/O chunks of the plurality of requests.
Methods and systems for computing in-dynamic random access memory (DRAM) computing include loading a first group of cells of the DRAM with input parameters and loading a second group of cells of the DRAM with inverted input parameters that are each complementary to corresponding input parameters. An offset group of cells of the DRAM is loaded with an indication of an offset voltage. An operation is performed on weights with corresponding stored input parameters or the stored inverted input parameters, and a column of the first group and the second group is activated to perform an accumulation of the operations of weights for cells in the column to store a sum. An offset voltage is generated using the indication, and an output is generated based on the comparison of the sum and the offset voltage and is stored in an output group of cells of the DRAM.
Systems and methods include a memory device that includes a dual-interlocked cell (DICE) latch and upstream circuitry coupled to the DICE latch and including a common node configured to receive a control signal for an operation for the DICE latch. The upstream circuitry also includes a first divided control path coupled to common node and configured to generate a first divided control signal from the control signal. The upstream circuitry comprises a second divided control path coupled to the common node and configured to generate a second divided control signal from the control signal. The second divided control path includes a delay configured to delay the second divided control signal to stagger propagation of a potential neutron strike at the common node or upstream of the common node from the DICE latch.
A processing device in a memory sub-system receives a plurality of requests to write data to a non-volatile memory device, the plurality of requests comprising respective numbers of input/output (I/O) chunks of a fixed size, and performs a plurality of write operations to write the data to the non-volatile memory device using respective translation units, wherein the respective translation units comprise two or more different translation unit sizes selected based on the respective numbers of I/O chunks of the plurality of requests.
A memory module includes a number of memory devices. During a read operation the memory device reads data and parity bits. An error correction circuit of the memory device determines if there is an uncorrectable error in the data and parity bits. If there is an uncorrectable error, the error correction circuit aliases a bit within a specified subset of the data bits. The specified subset may be based on which patterns of errors are correctable by a module level error correction scheme.
Methods, systems, and devices for dielectric windows for groups of vias through semiconductor substrates are described. For example, a semiconductor component (e.g., a semiconductor die, a semiconductor wafer) may be formed with one or more dielectric windows through a substrate of the semiconductor component, through which a group of multiple vias may be formed to support signaling with circuitry of the semiconductor component. In some implementations, a set of multiple cavities may be formed through a given dielectric portion and, in each of the multiple cavities, a conductive portion (e.g., one or more conductive materials) may be formed to support multiple electrically isolated contacts. In various examples, such vias may include contacts themselves (e.g., for vias that extend to the surface of the semiconductor component), or may be otherwise coupled with (e.g., contiguous with, electrically coupled with) a contact portion that has a different cross-section than the vias.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H10B 80/00 - Assemblies of multiple devices comprising at least one memory device covered by this subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
Methods, systems, and devices for on-die testing for a memory device are described. In some examples, a memory die may include processing circuitry configured to perform evaluations of the memory die based on commands or instructions received from an external device. The processing circuitry may be configured to detect failures of the memory die and transmit related indications to the external device based on the on-die detection. In some examples, the processing circuitry may be configured to communicate failure information at a finer granularity than information associated with expected or nominal behavior. Additionally or alternatively, the processing circuitry may be configured to perform operations according to an internally-generated clock signal that operates at a faster rate or speed than a clock signal from the external device. In some examples, the processing circuitry may include an analog-to-digital conversion capability for digital communication of analog characteristics internal to the memory die.
Methods, systems, and devices for a common error protection buffer for multiple cursors are described. A memory device may receive a command to write data to a memory system. The memory device may assign portions of the data to respective pages of a first cursor and generate error protection data for the assigned data. The memory device may assign the generated error protection data to an error protection buffer common to multiple cursors, for example, by performing an combination operation. The memory device may increment a counter associated with the error protection buffer. The memory device may write a summary of contents of the error protection buffer and a position of each cursor related to the error protection data based on the counter satisfying a threshold. The memory device may perform a readback operation to facilitate garbage collection without losing error protection data.
A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.
A system includes a memory device including a plurality of dies; and a processing device, operatively coupled with the memory device, to perform operations including: obtaining, by performing a plurality of scan operations on a die of the plurality of dies, a value of a data state metric characterizing the die; identifying, in a set of criteria, a particular criterion that is satisfied by the value of the data state metric, wherein each criterion of the set of criteria corresponds to a respective rating of a plurality of ratings; assigning, to the die, a rating corresponding to the particular criterion; and performing a plurality of subsequent scan operations on the die at a frequency determined by the rating.
A system including sensors of an advanced driver assistance system and a data recorder. The data recorder has: a volatile memory; a non-volatile memory configured with a file system region and a buffer region; and a processor configured to implement a file system mounted in the file system region. The data recorder records outputs from the sensors via the volatile memory into the buffer region in a cyclic way and, in response to an event, retrieve sensor data from the buffer region and store the sensor data into files organized under the file system mounted in the file system region.
G06F 3/06 - Digital input from, or digital output to, record carriers
G07C 5/08 - Registering or indicating performance data other than driving, working, idle, or waiting time, with or without registering driving, working, idle, or waiting time
Systems and methods are provided for trimming RTTs in a memory device (10). The effective termination resistance (RTT) of the ODT may be adjusted by adjusting one or more driver units (102, 122) having predefined values (e.g., 240 Ω). Because PVT characteristics may impact the driver unit (102, 122) values, resistances of the driver units (102, 122) may be fluctuated away from the predefined values (e.g., 240 Ω). ZQ calibration signals may be used to calibrate the resistances of the driver units (102, 122) to the predefined values (e.g., 240 Ω) to trim the RTTs. Separate ZQ calibration signals may be generated for different circuits (e.g., a circuit associated with DQ pad, a circuit associated with CA pad).
Systems and methods are provided for trimming RTTs in a memory device (10). The effective termination resistance (RTT) of the ODT may be adjusted by adjusting one or more driver units (102, 122) having predefined values (e.g., 240 Ω). Because PVT characteristics may impact the driver unit (102, 122) values, resistances of the driver units (102, 122) may be fluctuated away from the predefined values (e.g., 240 Ω). ZQ calibration signals may be used to calibrate the resistances of the driver units to the predefined values (e.g., 240 Ω) to trim the RTTs. Separate ZQ calibration signals may be generated for different circuits (e.g., a circuit associated with DQ pad, a circuit associated with CA pad). In addition, two ZQ calibration signals may be generated simultaneously by a ZQ circuit (60) during the same time period.
A microelectronic device comprises a periphery circuitry region, bank regions, a control circuitry structure, and a memory array structure. The periphery circuitry region comprises a central sub-region, and two arm sub-regions extending from the central sub-region from the central sub-region in a first horizontal direction. Each of the two arm sub-regions has a different length than the central sub-region in a second horizontal direction orthogonal to the first horizontal direction. The bank regions are horizontally outward of the periphery circuitry region. The control circuitry structure comprises relatively more speed-critical circuitry within a horizontal area of the periphery circuitry region, and relatively less speed-critical circuitry within horizontal areas of the bank regions. The memory array structure vertically underlies the control circuitry structure and comprises arrays of memory cells within the horizontal areas of the bank regions. Additional microelectronic devices and memory devices are also described.
G11C 11/4096 - Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
G11C 11/4074 - Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
Some embodiments of the disclosure provide an apparatus comprising: a word line array including a plurality of word lines each extending through a memory mat in a first horizontal direction, the plurality of word lines including first and second word lines arranged adjacent to each other in a second horizontal direction; and a word line contact of the first word line, the word line contact separated from the second word line by a gap. The first and second word lines each have a first oxide film at a center area of the word line array in the memory mat. The first and second word lines each have a second oxide film at an edge area of the word line array outside the memory mat, the second oxide film having a thickness greater than a thickness of the first oxide film.
The present disclosure includes apparatuses, methods, and systems for memory maintenance operations. An embodiment includes a memory having a plurality of groups of memory cells, wherein one of the plurality of groups of memory cells does not have data stored therein and all other ones of the plurality of groups of memory cells have data stored therein, and a controller coupled to the memory and having circuitry configured to determine one of the plurality of groups of memory cells that has data stored therein is a bad group of memory cells, recover the data stored in the bad group of memory cells, program the recovered data to the one of the plurality of groups of memory cells that does not have data stored therein, and retire the bad group of memory cells.
Methods, systems, and devices for memory fault notification are described. A memory device may receive a configuration corresponding to a circuit node of the memory device, where the circuit node may be selectively coupled with a set of resistors. The memory device may determine a fault condition and couple the circuit node to at least a first resistor based on determining the fault condition. The memory device may bias the circuit node to a first voltage value that satisfies a voltage threshold based on coupling the circuit node to the first resistor. The memory device may output an indication of a fault state to notify a host device that a fault has been detected.
In some implementations, a device may cause a single host device to load data to a first memory device of a plurality of memory devices configured in a fabric. The device may cause the first memory device to propagate the data to one or more second memory devices, of the plurality of memory devices, via one or more peer-to-peer transfer operations to replicate the data from the first memory device to the one or more second memory devices without involvement of the single host device.
Apparatuses, systems, and methods for indicating data corruption are described. An example method can include receiving a write command to write user data to one or more memory units of a number of memory units. The method can further include generating a number of first bits that are invalid as error correction information or error detection information for the user data responsive to the user data being determined to be corrupted. The method can further include writing the user data to a first portion of the number of memory units and writing, along with the user data and instead of a number of second bits corresponding to the error correction information or the error detection information, the number of first bits to a second portion of the number of memory units.
Memories might include an array of memory cells having a plurality of strings of series-connected memory cells and a controller configured to cause to memory to apply an erase pulse having a target voltage level and having an erase pulse flattop; for each suspend of a plurality of suspends initiated during the application of the erase pulse flattop, increase a value of the target voltage level; and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the plurality of suspends. Such controllers might further be configured to cause the memory to maintain the value of the target voltage level for each suspend of one or more additional suspends initiated during the application of the erase pulse flattop, and resume applying the erase pulse having the target voltage level until initiation of any subsequent suspend of the one or more additional suspends.
A processing device in a memory sub-system receives a request to execute a programming operation to program a target portion of a memory array of a memory device. In response to the request, a target wordline group associated with the target portion of the memory array is identified. Information associated with the target wordline group is identified, where the information identifies a first good portion of the target wordline group and a second bad portion of the target wordline group. The programming operation is caused to be executed to program the first good portion of the target wordline group and skip programming of the second bad portion of the target wordline group.
Various embodiments provide for temperature-based read error handling on the memory system. In particular, some embodiments enable a memory system to handle an uncorrectable error for a read operation with respect to a memory device (of the memory system) based on a cross temperature associated with the read operation.
Methods, systems, and devices for memory systems having a selectively interfaceable memory subsystem are described. A memory system may include the memory subsystem that may be configurable to provide volatile storage, nonvolatile storage, or both to a host system. The memory subsystem may include a plurality of ports each capable of communicating with the host system using different interfaces. The memory subsystem may be dynamically configurable to perform different functions based on the demands of the host system. In some examples, memory systems described herein may include a first memory subsystem to provide nonvolatile storage to the host system, a second memory subsystem to provide volatile storage to the host system, and a third memory subsystem configurable to provide volatile storage or nonvolatile storage or both to the host system.
Methods, systems, and devices for managing regions of a memory system are described. A memory system may include a non-volatile memory device and may receive a host performance booster (HPB) command (e.g., a read command) associated with one or more regions of the non-volatile memory device. The memory system may determine whether the region(s) associated with the HPB command are active. In instances where one or more of the associated regions are inactive, the memory system may activate the region(s) and deactivate one or more other regions based on a recency parameter (e.g., a timing parameter). The memory system may process the received HPB command based on the associated region(s) being active.
An electronic device comprising multilevel bitlines comprising first bitlines and second bitlines. The first bitlines and the second bitlines are positioned at different levels. Pillar contacts are electrically connected to the first bitlines and to the second bitlines. Level 1 contacts are electrically connected to the first bitlines and level 2 contacts are electrically connected to the second bitlines. A liner is between the first bitlines and the level 2 contacts. Each bitline of the first bitlines is electrically connected to a single pillar contact in a subblock adjacent to the level 1 contacts and each bitline of the second bitlines is electrically connected to a single pillar contact adjacent to the level 2 contacts. Methods of forming an electronic device and related systems are also disclosed.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H10B 43/35 - EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
89.
PERFORMING SELECT GATE INTEGRITY CHECKS TO IDENTIFY AND INVALIDATE DEFECTIVE BLOCKS
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value by measuring a voltage at a select gate of a block while applying a maximum voltage to a drain select line, responsive to determining that the parameter value satisfies a threshold criterion, concluding that the select gate of the block is defective, and responsive to receiving an enhanced erase command referencing the block, discarding the enhanced erase command.
Methods and non-transitory machine-readable media associated with treatment plan identification are described. Treatment plan identification can include receiving first signaling configured to monitor user health data and receiving second signaling configured to monitor user behavior data. Treatment plan identification can include writing data that is based at least in part on a combination of the first signaling and the second signaling and identifying output data representative of a treatment plan for the user based at least in part on input data representative of the written data and additional user data. Output data representative of the treatment plan can be transmitted to a computing device accessible by the user, a computing device accessible by a provider, or both.
G16H 20/00 - ICT specially adapted for therapies or health-improving plans, e.g. for handling prescriptions, for steering therapy or for monitoring patient compliance
G16H 10/60 - ICT specially adapted for the handling or processing of patient-related medical or healthcare data for patient-specific data, e.g. for electronic patient records
G16H 50/20 - ICT specially adapted for medical diagnosis, medical simulation or medical data miningICT specially adapted for detecting, monitoring or modelling epidemics or pandemics for computer-aided diagnosis, e.g. based on medical expert systems
Apparatuses and methods can be related to encoding traffic between a host and a DLA. Traffic between a host can be encoded utilizing an autoencoder. Encoding traffic between a host and a DLA changes the bandwidth of the traffic. Changing the bandwidth of the traffic prevents the correlation between the bandwidth and the input from which the traffic is generated.
G06N 3/063 - Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
G06F 12/123 - Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
G06F 21/14 - Protecting executable software against software analysis or reverse engineering, e.g. by obfuscation
Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a memory cell including a first transistor, a second transistor, and a dielectric structure formed in a trench. The first transistor includes a first channel region, and a charge storage structure separated from the first channel region. The second transistor includes a second channel region formed over the charge storage structure. The dielectric structure includes a first dielectric portion formed on a first sidewall of the trench, and a second dielectric portion formed on a second sidewall of the trench. The charge storage structure is between and adjacent the first and second dielectric portions.
H10B 41/35 - Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
The disclosure configures a memory sub-system controller to efficiently perform block migration (e.g., from SLC cache to QLC blocks) in a Zone Namespace (ZNS) device. The controller associates a plurality of zones of the set of memory components with a plurality of internal zone groups (IZGs) each associated with a different write cursor. The controller programs data to a first portion of a set of memory components using the plurality of write cursors, the first portion being associated with a first type of storage, and determines that an individual IZG of the plurality of IZGs satisfies a migration criterion. The controller migrates a portion of the data stored in the first portion of the set of memory components corresponding to the individual IZG to a second portion of the set of memory components, the second portion of the set of memory components being associated with a second type of storage.
Some implementations herein provide a semiconductor package and methods of formation. The semiconductor package includes a semiconductor die having a first set of conductive structures connected with a substrate having a second set of conductive structures, where a profile of heights of the second set of conductive structures includes a curvature relative to a surface of the substrate. The curvature is configured to compensate for warpage (e.g., offset warpage) that may be induced to the semiconductor die and/or the substrate during a reflow process that joins the semiconductor die and the substrate. By compensating for the warpage, a planarity of an interface region including solder joints between the first and second sets of conductive structures is increased. Increasing the planarity may reduce solder joint defects in the semiconductor package relative to another semiconductor package including another substrate having conductive structures without the profile having the curvature.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
95.
WORDLINE GROUP-BASED IDENTIFICATION OF GOOD MEMORY BLOCKS DURING A PROGRAMMING OPERATION
A processing device in a memory sub-system receives a request to execute a programming operation to program a target portion of a memory array of a memory device. In response to the request, a target wordline group associated with the target portion of the memory array is identified. Information associated with the target wordline group is identified, where the information identifies a first good portion of the target wordline group and a second bad portion of the target wordline group. The programming operation is caused to be executed to program the first good portion of the target wordline group and skip programming of the second bad portion of the target wordline group.
Methods, systems, and devices for power envelope modification for memory systems based on time to thermal throttle are described. A memory system may dynamically change the power limit based on operating conditions associated with the memory system. For example, the memory system may measure the time before entering a thermal throttle mode. If the time is relatively short, the memory system may decrease the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to increase. Alternatively, if the time is relatively long, the memory system may increase the power limit, which may cause the time before entering the thermal throttle mode during a subsequent burst of host activity to decrease.
An electronic device includes a stack structure including vertically alternating dielectric materials and conductive materials. The dielectric materials define air gaps between vertically adjacent conductive materials and include a first oxide material vertically adjacent to the conductive materials and laterally adjacent to the tunneling material, and a nitride material laterally and vertically adjacent to the first oxide material. The stack structure includes pillars extending vertically through the stack structure, the pillars including cell films adjacent to the dielectric and conductive materials. The cell films include a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material, wherein segments of each of the high-k dielectric material, the barrier oxide material, and the storage node material are adjacent to the conductive materials. Related methods and systems are also disclosed.
H01L 21/768 - Applying interconnections to be used for carrying current between separate components within a device
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
98.
PERFORMING MODULATION OPERATIONS IN A MEMORY SUB-SYSTEM
Systems and methods are disclosed including a memory device and a processing device, operatively coupled with the memory device, to perform operations comprising: receiving a write command to store data on the memory device; identifying a block of the memory device referenced by the write command; identifying, based on a number of pages in the block, a number of bits of an address referenced by the write command; generating a seed value by performing one or more transformation operations on a subset of bits comprising the identified number of bits of the address; generating an output sequence using the seed value; generating modulated data by performing one or more bitwise operations on the output sequence and the data; and storing, in the block of the memory device, the modulated data.
A variety of applications can include an interface for partition settings of data in a memory system. The memory system can be arranged having logical units, where each logical unit holds data of a data type different from data types in other logical units of the logical units. The memory system can include one or more buffers. An interface can be arranged in the memory system to configure a first set of the logical units to a first performance setting and configure a second set of the logical units to a second performance setting. Operation of the interface can include directing data from the first set of the logical units to the one or more buffers and include directing data from the second set of the logical units to a storage area of the memory system by bypassing the one or more buffers.
A method can be performed using a memory device. The method can include receiving a refresh command for first data or second data in the memory device. The method can include accessing a first of at least two registers in the memory device. The first register can be configured to store a first logical block address (LBA) at which the first data is stored in the memory device. A second of the at least two registers can be configured to store a range of LBAs at which at least the second data is stored in the memory device. The method can include performing a refresh operation to refresh one or both of the first data and the second data based on at least one of the first LBA and the range of LBAs.
