A switching device includes a switching transistor provided between a first terminal connected to an inductive load and a second terminal, and turns the switching transistor on and off. A driver turns the switching transistor on by supplying a charging current to a gate of the switching transistor, and turns the switching transistor off by discharging charges stored in the gate of the switching transistor. The driver discharges the stored charges via an external resistor provided outside the switching device and between a resistor connection terminal and a ground.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
2.
VOLTAGE REGULATING DEVICE AND CHARGE STORAGE SYSTEM
A voltage regulating device connected to a series circuit of electrolytic capacitors provided between a ground wiring and an input voltage wiring, includes: a high-side terminal connected to the input voltage wiring; a low-side terminal connected to the ground wiring; a middle terminal connected to a connection node between the electrolytic capacitors; and a voltage limiting circuit configured to limit a voltage between the high-side terminal and the middle terminal to a high-side limit voltage or lower by controlling a high-side regulating current between the high-side terminal and the middle terminal according to the voltage between the high-side terminal and the middle terminal, and configured to limit a voltage between the middle terminal and the low-side terminal to a low-side limit voltage or lower by controlling a low-side regulating current between the middle terminal and the low-side terminal according to the voltage between the middle terminal and the low-side terminal.
H02J 7/00 - Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
This isolation transformer includes: an isolation layer; a transformer having a first coil and a second coil; and a capacitor having a first capacitor electrode and a second capacitor electrode disposed between the first coil and the second coil. The isolation layer includes a first isolation film in which the first coil is embedded, a second isolation film on the upper surface of the first isolation film, a protective film on the upper surface of the second isolation film, a third isolation film on the upper surface of the protective film, a fourth isolation film on the upper surface of the third isolation film, and a fifth isolation film on the upper surface of the fourth isolation film. The second capacitor electrode is formed between the third isolation film and the fourth isolation film. The second coil is formed between the fourth isolation film and the fifth isolation film.
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
4.
CONTROLLER, POWER FACTOR CORRECTION CIRCUIT, ELECTRONIC DEVICE, AND OFFSET SETTING METHOD
A controller configured to control a power factor correction (PFC) circuit including a DC/DC converter, includes: a first external terminal receiving a full-wave rectified first voltage; a second external terminal receiving a first detection voltage generated by a current flowing through a sense resistor connected to a ground potential; an error amplifier circuit generating a second voltage by amplifying an error between a second detection voltage corresponding to the DC/DC converter's output voltage and a reference voltage; an arithmetic circuit generating a third voltage by multiplying the first and second voltages; an inverting amplifier generating a fourth voltage from the first detection voltage; a comparator comparing the third and fourth voltages; and a drive circuit driving a switching element in the PFC circuit to be turned on or off such that the switching element is turned off each time the fourth voltage becomes higher than the third voltage.
H02M 1/42 - Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
G01R 1/20 - Modifications of basic electric elements for use in electric measuring instrumentsStructural combinations of such elements with such instruments
Provided is a signal reception device including a processing circuit that outputs a processed signal obtained by applying predetermined processing to a received signal, a function block that receives the processed signal and executes processing determined on the basis of the processed signal, and a self-test circuit that outputs a test signal to the processing circuit and makes defective or non-defective state determination according to the signal output from the processing circuit.
A semiconductor device includes: a switching element including a drain electrode, a gate electrode, and a source electrode; a base supporting the switching element; and a first terminal, a second terminal, a third terminal, and a fourth terminal that each extend in the same direction. The switching element includes a temperature detection diode having a first electrode provided on the element obverse surface. Each of the drain electrode, the gate electrode, and the source electrode is electrically connected to a corresponding one of the first terminal, the second terminal, and the third terminal. The first electrode is electrically connected to the fourth terminal via a first wire.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
7.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, RELAY UNIT, BATTERY UNIT, AND VEHICLE
A semiconductor device includes a first terminal for a battery, a second terminal for an inverter circuit, and a transistor. The semiconductor device is configured to control a voltage applied to a control terminal of the transistor to allow supply of a current from the first terminal to the second terminal and allow supply of a current from the second terminal to the first terminal. A withstand voltage between the first terminal and the second terminal is greater than or equal to a voltage between the battery and the inverter circuit.
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
B60L 3/00 - Electric devices on electrically-propelled vehicles for safety purposesMonitoring operating variables, e.g. speed, deceleration or energy consumption
B60L 15/00 - Methods, circuits or devices for controlling the propulsion of electrically-propelled vehicles, e.g. their traction-motor speed, to achieve a desired performanceAdaptation of control equipment on electrically-propelled vehicles for remote actuation from a stationary place, from alternative parts of the vehicle or from alternative vehicles of the same vehicle train
B60L 50/60 - Electric propulsion with power supplied within the vehicle using propulsion power supplied by batteries or fuel cells using power supplied by batteries
H01H 47/00 - Circuit arrangements not adapted to a particular application of the relay and designed to obtain desired operating characteristics or to provide energising current
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/40 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or with at least one component covered by groups or , e.g. integration of IGFETs with BJTs
8.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, VEHICLE
A signal transmission device includes a first and a second circuit, in which the first circuit includes: a transmitter configured to generate a transmission signal according to an input signal; a first receiver configured to feed a first reception signal to a first logic circuit to generate a first single output signal; and at least one first isolating element arranged between the transmitter and the first receiver and configured to constitute a first signal transmission path for transmission of the transmission signal from the transmitter and output the first reception signal to the first receiver. The second circuit includes: a second receiver configured to generate a second single output signal; and a second isolating element arranged between the first logic circuit and the second receiver and configured to constitute a second signal transmission path, different from the first signal transmission path, for transmission of the transmission signal from the transmitter.
A semiconductor device includes a semiconductor element, an electrode on a first side in a thickness direction of the semiconductor element, a re-wiring connected to the electrode, a terminal connected to the re-wiring, and a conductive bonding layer connected to the terminal. The terminal includes a first terminal and a second terminal. The conductive bonding layer includes a first conductive bonding layer connected to the first terminal and a second conductive bonding layer connected to the second terminal. The area of the second terminal is greater than the area of the first terminal. The area of the second conductive bonding layer is greater than the area of the first conductive bonding layer.
A semiconductor device includes a chip, an electrode that is formed on the chip, an inorganic insulating layer that covers the electrode and has a first opening exposing the electrode, an organic insulating layer that covers the inorganic insulating layer, has a second opening surrounding the first opening at an interval from the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and an Ni plating layer that covers the electrode inside the first opening and covers the inner peripheral edge of the inorganic insulating layer inside the second opening.
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/367 - Cooling facilitated by shape of device
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
11.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE AND VEHICLE
A signal transmission device that transmits a driving signal for a power transistor from a primary circuit system to a secondary circuit system while isolating between the primary and secondary circuit systems includes: a first fault detection circuit configured to detect a fault in the primary circuit system; a second fault detection circuit configured to detect a fault in the secondary circuit system; a first signal transmission path configured to transmit the result of detection by the second fault detection circuit from the secondary circuit system to the primary circuit system while isolating between the primary and secondary circuit systems; and a self-test circuit configured to perform a self-test on each of the first fault detection circuit, the second fault detection circuit, and the first signal transmission path.
The present disclosure provides an electronic device. The electronic device includes a first resin layer, having a first resin layer main surface and a first resin layer inner surface; a first conductor, having a first conductor main surface and a first conductor inner surface; a first wiring layer, formed adjacent to the first resin layer main surface and connected to the first conductor main surface; a first electronic component, electrically connected with the first wiring layer; a second resin layer, having a second resin layer main surface facing same direction as the first resin layer main surface and a second resin layer inner surface being in contact with the first resin layer main surface; an external electrode; and a second conductor, penetrating the second resin layer, wherein the second conductor is disposed on a periphery of the first electronic component.
The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
A semiconductor device includes an SiC chip that has a first principal surface and a second principal surface, an element structure that is formed in the first principal surface, and an electrode that is formed on the second principal surface and is electrically connected to the element structure and an arithmetic mean roughness (Ra) of the second principal surface is not less than 30 nm. An ohmic contact of low resistance can thereby be formed at the second principal surface at the opposite side to the element structure.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/64 - Electrodes comprising a Schottky barrier to a semiconductor
A semiconductor device includes: a semiconductor element; a lead; a bonding target; a conductive bonding material that electrically bonds the bonding target and the lead; and a sealing resin that covers the bonding target and the lead. The lead includes a lead body including an obverse surface facing the bonding target, and a metal layer disposed on the obverse surface. A material of the metal layer has better wettability to the conductive bonding material in a molten state than a material of the lead body. The conductive bonding material is bonded to the metal layer. The obverse surface includes an uneven region spaced apart from the metal layer in plan view, and a smooth region located between the metal layer and the uneven region.
A power control device is provided, in which an output stage circuit includes an output transistor provided between an input terminal and a switch terminal, and a rectifier element provided between the switch terminal and ground. When the output stage circuit, an output coil, and an output capacitor are provided, a control drive circuit generates an output voltage by switching drive corresponding to a feedback voltage. The feedback voltage is applied to a feedback terminal. A controller controls whether to have the control drive circuit perform switching drive based on voltages of the switch terminal and the feedback terminal at a determination timing when the switching drive is not executed.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
G05F 1/577 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices for plural loads
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a switch circuit and a leakage cancellation circuit. The switch circuit has at least one switch configured as a MOSFET connected between two terminals of a specific element. The leakage cancellation circuit has at least one MOS transistor configured as a MOSFET, is connected to the switch circuit at a specific node, and is configured to inject or extract a leakage current with respect to the specific node.
G05F 1/59 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
18.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, an electrode located on a first side in a thickness direction of the semiconductor element, a re-wiring located on the first side in the thickness direction with respect to the electrode and electrically connected to the electrode, and a terminal located on the first side in the thickness direction with respect to the re-wiring and electrically connected to the re-wiring. The re-wiring includes a first re-wiring and a second re-wiring. The dimension of the second re-wiring in the thickness direction is greater than the dimension of the first re-wiring in the thickness direction.
A semiconductor device comprises a first conductive layer, a first semiconductor element bonded to one side in a first direction of the first conductive layer, a first power terminal conductive to the first conductive layer and the first semiconductor element, a first sealing resin covering the first conductive layer and the first semiconductor element, and a first extension terminal conductively bonded to the first power terminal. The first power terminal has a first exposed portion exposed from the first sealing resin. The first extension terminal is conductively bonded to the first exposed portion.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/373 - Cooling facilitated by selection of materials for the device
H01L 23/49 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of soldered or bonded constructions wire-like
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A semiconductor device comprises: a package including a first side, a second side parallel to the first side, a third side orthogonal to the first side and the second side, and a fourth side parallel to the third side and orthogonal to the first side and the second side; a first power supply terminal and a second power supply terminal either on the first or second side; a first power ground terminal and a second power ground terminal either on the first or the second side; a first switch output terminal and a second switch output terminal on the second side; a first upper switch between the first power supply terminal and the first switch output terminal; a first lower switch between the first switch output terminal and the first power ground terminal; a second lower switch between the second switch output terminal and the second power ground terminal.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/36 - Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
H02M 3/00 - Conversion of DC power input into DC power output
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A terminal includes a first conductive layer; a wiring layer on the first conductive layer; a second conductive layer on the wiring layer; and a conductive bonding layer that is in contact with a bottom surface and a side surface of the first conductive layer, a side surface of the wiring layer, a portion of a side surface of the second conductive layer, and a portion of a bottom surface of the second conductive layer, wherein an end portion of the second conductive layer protrudes from an end portion of the first conductive layer and an end portion of the wiring layer, and wherein the conductive bonding layer is in contact with a bottom surface of the end portion of the second conductive layer.
H01L 23/528 - Layout of the interconnection structure
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
22.
ELECTRONIC COMPONENT AND ELECTRONIC COMPONENT MODULE
An electronic component includes an insulating layer, a low voltage conductor pattern formed inside the insulating layer, a high voltage conductor pattern formed inside the insulating layer such as to face the low voltage conductor pattern in an up/down direction, and a withstand voltage enhancement structure of conductive property formed inside the insulating layer and along the high voltage conductor pattern such as to protrude further outside than the low voltage conductor pattern in plan view.
This semiconductor device includes: a chip having a main surface; a first region of a first conductivity type extending in a first direction along the main surface at a peripheral surface layer part of the main surface; a plurality of second regions of a second conductivity type extending in the first direction on both sides of the first region at the peripheral surface layer part of the main surface; and a shield region, which divides at least a portion of the first region into a region on an end-part side of the chip and a region on an inner-part side of the chip at the peripheral edge surface layer part of the main surface, and which has a resistance value higher than the resistance value of the first region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device (1) includes: a logic circuit (11); and a diagnostic circuit (120), configured so as to perform a diagnostic process of diagnosing whether the logic circuit is in a state capable of normal operation based on output data of the logic circuit when a test pattern is supplied to the logic circuit. The diagnostic circuit executes multiple diagnostic processes with operating conditions of the logic circuit differing from each other.
A semiconductor device includes: an internal power supply circuit configured to generate an internal power supply voltage based on an input power supply voltage; a function circuit configured to operate based on the internal power supply voltage; a chassis accommodating the internal power supply circuit and the function circuit; a specific terminal that is a terminal exposed from the chassis and is configured to be applied with the internal power supply voltage; and a mode setting circuit configured to set an operation mode of the function circuit according to a terminal current flowing through the specific terminal.
A power factor correction circuit including a DC/DC converter includes: at least one selected from the group of first voltage dividing resistors and a first switch connected to an application end of a first voltage with a full-wave rectified waveform, and second voltage dividing resistors and a second switch connected to an application end of an output voltage of the DC/DC converter; and a controller configured to control the power factor correction circuit, wherein an on-off operation of at least one selected from the group of the first switch and the second switch is controlled based on a control signal which is input to the controller from outside to switch between a normal state and a standby state.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
An SiC semiconductor device includes an SiC layer of a first conductivity type that has a main surface, an active region set in an inner portion of the main surface, an outer peripheral region set in a peripheral edge portion of the main surface, and a column region of a second conductivity type that is formed in the SiC layer at an interval in a horizontal direction along the main surface and includes impurity regions positioned in both the active region and the outer peripheral region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device includes a substrate having a main surface, a plurality of first wirings, each having a first embedded part embedded in the substrate and exposed from the main surface, and a mounted part which is in contact with the main surface and is connected to the first embedded part, a semiconductor element having an element rear surface and a plurality of electrodes bonded to the mounted parts, a plurality of second wirings, each having a second embedded part embedded in the substrate and exposed from the main surface and a columnar part protruding from the second embedded part in the thickness direction, and being located outward from the semiconductor element as viewed in the thickness direction; and a passive element located on the side facing the main surface in the thickness direction more than the semiconductor element, and electrically connected to the plurality of second wirings.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
A semiconductor device disclosed herein comprises: an MIS transistor structure including a first impurity region of a first conductivity type formed in a surface layer portion of a first main surface of a chip, a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region, a third impurity region of a first conductivity type formed in a surface layer portion of the second impurity region, and control electrodes facing each other in a first channel region of the second impurity region via a control insulating film; a rectifying element structure including shield regions of the second conductivity type formed in a surface layer portion of the first impurity region and facing each other, in a direction crossing the thickness direction of the chip, in the first impurity region, and a second channel region provided by a portion of the first impurity region sandwiched between the shield regions; a first main surface electrode ohmic-connected to the third impurity region, the shield regions, and the second channel region; and a second main surface electrode ohmic-connected to the first impurity region.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
The present disclosure provides a motor drive circuit. The motor drive circuit includes a first-phase half bridge circuit and a second-phase half bridge circuit. The first and second-phase half bridge circuits include first-phase and second-phase high-side FETs and first-phase and second-phase low-side FETs. The first-phase and second-phase high-side FETs are configured to apply a first voltage to a first end. A second end of the first-phase and second-phase high-side FETs is connected to the first end. A second voltage lower than the first voltage is applied to the second end. The first-phase low-side FET or the second-phase high-side FET is disposed between the first-phase high-side FET and the second-phase low-side FET. The second-phase low-side FET or the first-phase high-side FET is disposed between the first-phase low-side FET and the second-phase high-side FET.
H02H 7/08 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H03K 17/06 - Modifications for ensuring a fully conducting state
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
An SiC semiconductor device includes an SiC chip having a main surface, a channel region formed in a surface layer portion of the main surface, a drift region adjacent to the channel region in the surface layer portion of the main surface, a gate insulating film that is formed on the main surface and has a channel covering portion which covers the channel region and a drift covering portion which covers the drift region, a planar gate electrode that is arranged on the channel covering portion and opposes the channel region across the channel covering portion in a vertical direction, and a planar source electrode that is arranged on the drift covering portion at an interval from the planar gate electrode such as to oppose the planar gate electrode in a horizontal direction and opposes the drift region across the drift covering portion in the vertical direction.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
A semiconductor device according to an embodiment of the present invention includes: a first delay circuit which generates a third signal and a fourth signal by delaying, by a first period, a first signal having a low level at a first voltage and a second signal that is an inversion signal of the first signal; a first current supply unit which includes a first current supply terminal in which current supply capacity is switched according to the third signal and a second current supply terminal in which current supply capacity is switched according to the fourth signal; and a first voltage conversion unit which outputs either or both of a first voltage conversion signal and a second voltage conversion signal obtained by level-shifting the low levels of the first signal and the second signal from the first voltage to a third voltage.
A semiconductor device includes a semiconductor substrate of a first conductivity type, and a semiconductor layer of the first conductivity type. The semiconductor layer includes a trench gate, a source region of the first conductivity type, a contact region of a second conductivity type and a column region of the second conductivity type. The semiconductor layer has formed therein a plurality of trench gates arranged at certain intervals along a first direction and a second direction, respectively. The source region is in contact with the trench gate and surrounds the trench gate. The contact region is disposed between source regions adjacent to each other along the second direction, and the column region extends toward the semiconductor substrate from one end of the contact region that is closer to the semiconductor substrate.
An SiC semiconductor device includes a first SiC layer of a first conductivity type which has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type which has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type which extends along the first axis channel in the first SiC layer, and a second region of the second conductivity type which extends along the second axis channel in the second SiC layer and overlaps the first region in the lamination direction.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
35.
GATE DRIVER, INSULATION MODULE, LOW-VOLTAGE CIRCUIT UNIT, AND HIGH-VOLTAGE CIRCUIT UNIT
A gate driver includes a low-voltage circuit chip and a high-voltage circuit chip. The low-voltage circuit chip includes a low-voltage circuit configured to be actuated by application of a first voltage. The high-voltage circuit chip includes a high-voltage circuit configured to be actuated by application of a second voltage that is higher than the first voltage. The gate driver further includes multiple transformer chips connected in series to each other. The low-voltage circuit chip and the high-voltage circuit chip are connected by the multiple transformer chips and configured to transmit a signal through the multiple transformer chips. Each of the multiple transformer chips includes first and second insulation layers, a first coil arranged on the first insulation layer, and a second coil arranged on the second insulation layer and opposed to the first coil in a direction from the first insulation layer toward the second insulation layer.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
H01F 19/04 - Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
H01F 27/32 - Insulating of coils, windings, or parts thereof
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
A self-diagnosis circuit (BST1) configured to diagnose a fault detection circuit including a first comparator (CMP1) configured to be fed with a voltage based on a fault sensing target voltage (Vo1) and a first reference voltage (Vref1) includes a voltage switch circuit configured to switch the level of a voltage based on a second reference voltage (Vref2) and output the resulting voltage, a first path switch circuit configured to switch between a path through which the voltage output from the voltage switch circuit is fed to the first comparator and a path through which the voltage based on the fault sensing target voltage is fed to the first comparator, and a control circuit configured to control the voltage switch circuit and the path switch circuit.
An SiC semiconductor device includes an SiC layer that includes a main surface and has an axis channel in a lamination direction, an impurity region of a p-type formed in the SiC layer, a trench that is formed shallower than the impurity region in the main surface and defines a lower region including a part of the impurity region between a bottom portion of the SiC layer and the trench, and an inversion column of an n-type that is formed in the lower region such as to extend along the axis channel and that inverts a conductivity type of the impurity region.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes: a main body including a semiconductor layer; an electrode located on one side of the main body in a thickness direction of the main body, and electrically connected to the semiconductor layer; a rewiring located on an opposite side of the main body with respect to the electrode in the thickness direction, and electrically connected to the electrode; a first protective film located on a same side as the rewiring with respect to the electrode in the thickness direction, and overlapping with the rewiring when viewed in the thickness direction; and a second protective film located between the main body and the first protective film in the thickness direction, wherein the rewiring has a facing surface facing the first protective film, wherein the facing surface has at least one recess, and wherein the first protective film is inserted into each of the at least one recess.
Provided is a power source control device for a DC/DC converter including a high-side transistor, a low-side transistor, and an inductor, the power source control device including a first error amplifier configured to receive a first reference voltage and a feedback voltage based on an output voltage of the DC/DC converter, a second error amplifier configured to receive an output of the first error amplifier and a signal indicating information regarding a current flowing through the inductor, a first comparator configured to receive an output of the second error amplifier and a ramp voltage, a switching control unit configured to perform switching control of the high-side transistor and the low-side transistor according to an output of the first comparator, and a clamp circuit configured to clamp a second amplifier output voltage outputted from the second error amplifier, to a predetermined clamp voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
B60R 16/033 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems characterised by the use of electrical cells or batteries
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
40.
NITRIDE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/265 - Bombardment with wave or particle radiation with high-energy radiation producing ion implantation
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H01L 21/306 - Chemical or electrical treatment, e.g. electrolytic etching
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
There is provided a semiconductor device, including: a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface; a first conductive member electrically connected to the first electrode; a second conductive member electrically connected to the second electrode; and a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element.
An SiC semiconductor device includes an SiC layer of a first conductivity type that includes a main surface and has an axis channel in a lamination direction, a trench that is formed in the main surface and demarcates a lower region between the trench and a bottom portion of the SiC layer, and a column region of a second conductivity type that is formed in the lower region inside the SiC layer and extends along the axis channel.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
This semiconductor device comprises: an insulating layer; a conductive layer positioned on the insulating layer in a first direction; a heat dissipation layer on the opposite side of the insulating layer to the conductive layer; a first semiconductor element having a first electrode and a second electrode; and a second semiconductor element having a third electrode and a fourth electrode. The second electrode is positioned on the opposite side to the first electrode in the first direction. The fourth electrode is positioned on the opposite side to the third electrode in the first direction. The second electrode and the third electrode have different polarities from each other. The second electrode and the third electrode are bonded to the conductive layer. When viewed in the first direction, the conductive layer overlaps the heat dissipation layer.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A light-emitting component according to the present invention comprises a base, a semiconductor light-emitting element, a first lead, and a second lead. The base includes a first surface and a second surface on a side opposite from the first surface. The semiconductor light-emitting element is mounted on the first surface and is electrically connected to the base. The first lead is connected to the second surface. The second lead penetrates the base and is electrically insulated from the base. The light-emitting component is electrically connected to a first electroconductive layer by the first lead and the second lead. The semiconductor light-emitting element is joined to the first surface of the base.
H01S 5/11 - Comprising a photonic bandgap structure
H01S 5/18 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
H01S 5/023 - Mount members, e.g. sub-mount members
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/02208 - MountingsHousings characterised by the shape of the housings
H01S 5/02255 - Out-coupling of light using beam deflecting elements
This semiconductor device includes a semiconductor layer, an insulating film, and a first electrode. The semiconductor layer has an element region and a terminal region. The insulating film is formed on a first main surface of the semiconductor layer across the element region and the terminal region. The first electrode is formed on part of the insulating film. The semiconductor layer includes a semiconductor region of a first conductivity type and a RESURF layer of a second conductivity type. The first electrode has an outer peripheral portion including the outer peripheral end that is a terminal-region-side end portion. The RESURF layer includes an intermediate region, an inner region formed continuously from the intermediate region to the inner side, and an outer region formed continuously from the intermediate region to the outer side. The intermediate region is positioned below the outer peripheral portion of the first electrode and is partially thinner.
A terahertz device (A1, A2, A3, A31, A4, A5, A6, A7, A71, A8, A9) comprising: a terahertz element (7); a current limiting unit (2, 24, 25, 26) that is connected in series with the terahertz element (7); a first rectifying element (31) that is electrically connected in parallel with the terahertz element (7) between the terahertz element (7) and the current limiting unit (2, 24, 25, 26); and a second rectifying element (32) that is electrically connected in parallel with the terahertz element (7) and the first rectifying element (31) between the terahertz element (7) and the current limiting unit (2, 24, 25, 26), in a manner in which the forward direction thereof is the reverse from the forward direction of the first rectifying element (31).
H10D 62/815 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wellsSemiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
A semiconductor device includes a semiconductor substrate, an insulating layer, and a resistor. The resistor includes a first resistor layer. A first embedded electrode is electrically connected to the first resistor layer. A second resistor layer is disposed adjacent to the first resistor layer and electrically connected to the first resistor layer. A second embedded electrode is electrically connected to the second resistor layer. A first supplemental electrode extends in a lengthwise direction of the first resistor layer, is electrically connected to the first embedded electrode, and has a thickness greater than a thickness of the first resistor layer. A second supplemental electrode extends in the lengthwise direction, is electrically connected to the second embedded electrode, has a thickness greater than a thickness of the second resistor layer, is adjacent to the first supplemental electrode, and constitutes a capacitor together with the first supplemental electrode.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H10D 1/47 - Resistors having no potential barriers
H10D 1/68 - Capacitors having no potential barriers
An SiC semiconductor device includes a first SiC layer, a second SiC layer laminated on the first SiC layer, a first impurity region of a p-type formed in the first SiC layer, a second impurity region of the p-type formed in the second SiC layer, first inversion columns of an n-type that are formed at an interval in the first SiC layer such as to invert a conductivity type of the first impurity region; and second inversion columns of the n-type that are formed at an interval in the second SiC layer such as to invert a conductivity type of the second impurity region.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
An SiC semiconductor device includes a first SiC layer of a first conductivity type that has a first axis channel oriented along a lamination direction, a second SiC layer of the first conductivity type that has a second axis channel oriented along the lamination direction and is laminated on the first SiC layer, a first region of a second conductivity type that extends along the first axis channel in the first SiC layer in cross-sectional view and extends in a first extension direction in plan view, and a second region of the second conductivity type that extends along the second axis channel in the second SiC layer in cross-sectional view and extends in a second extension direction intersecting the first extension direction such as to intersect the first region in plan view.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
50.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a conductive layer; a semiconductor element including an electrode located on one side in a first direction; and a bonding layer electrically bonding the conductive layer and the semiconductor element. The conductive layer includes an obverse surface facing the semiconductor element in the first direction, and a pedestal portion protruding from the obverse surface. The bonding layer includes a portion located between the pedestal portion and the electrode. The pedestal portion includes a first surface that is an interface with the obverse surface, and a second surface that faces a same side as the obverse surface in the first direction and that is in contact with the bonding layer. An area of the second surface is larger than an area of the first surface. As viewed in the first direction, a periphery of the second surface surrounds the first surface.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
51.
SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE INCLUDING A COPPER PILLAR AND AN INTERMEDIATE LAYER
A semiconductor device includes a semiconductor layer having a first surface, an insulating layer formed at the first surface of the semiconductor layer, a Cu conductive layer formed on the insulating layer, the Cu conductive layer made of a metal mainly containing Cu, a second insulating layer formed on the insulating layer, the second insulating layer covering the Cu conductive layer, a Cu pillar extending in a thickness direction in the second insulating layer, the Cu pillar made of a metal mainly containing Cu and electrically connected to the Cu conductive layer, and an intermediate layer formed between the Cu conductive layer and the Cu pillar, the intermediate layer made of a material having a linear expansion coefficient smaller than a linear expansion coefficient of the Cu conductive layer and smaller than a linear expansion coefficient of the Cu pillar.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
52.
PIEZOELECTRIC ACTUATOR, AND METHOD FOR MANUFACTURING PIEZOELECTRIC ACTUATOR
This piezoelectric actuator, which has a cantilever structure, includes: a vibrating membrane which has a fixed end and a free end, and a first main surface and a second main surface that face in opposite directions; a membrane supporting portion to which the fixed end is connected; a piezoelectric element on the first main surface; and a projecting portion which projects from the second main surface and intersects a direction (X direction) connecting the fixed end and the free end. The ratio (r/L) of the distance from the fixed end to the position of the center of gravity of the projecting portion with respect to the distance from the fixed end to the free end is in the range of 0.60 to 0.75.
A semiconductor device includes a substrate including a first substrate surface and a second substrate surface opposite to the first substrate surface, a first wiring pattern provided on the first substrate surface, and a sensor chip used to detect a current flowing through the first wiring pattern. The first wiring pattern includes a detection pattern having a predetermined width. The sensor chip is mounted on the first substrate surface in a state of being disposed to cross the detection pattern. The sensor chip includes a first detection element and a second detection element as detection elements that detect a magnetic field generated by a current flowing through the detection pattern.
G01R 33/00 - Arrangements or instruments for measuring magnetic variables
G01R 15/20 - Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks using galvano-magnetic devices, e.g. Hall-effect devices
G01R 19/00 - Arrangements for measuring currents or voltages or for indicating presence or sign thereof
An SiC semiconductor device includes an SiC layer that includes a main surface, a trench structure that is formed in the main surface and extends in a first extension direction in plan view, and a gate structure of a planar electrode type that is arranged on the main surface and extends in a second extension direction other than the first extension direction in plan view.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
55.
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
An electronic device includes a support member, a wiring layer, a barrier metal, a bonding layer, and an electronic component. The support member includes an obverse surface facing a side in a thickness direction. The wiring layer is formed on the obverse surface. The barrier metal is formed on the wiring layer. The bonding layer is formed on the barrier metal. The electronic component is bonded to the wiring layer via the bonding layer and the barrier metal, and is electrically connected to the wiring layer. The barrier metal and the wiring layer contain mutually different metals. The barrier metal is smaller than the wiring layer as viewed in the thickness direction.
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
H05K 1/09 - Use of materials for the metallic pattern
H05K 3/06 - Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
H05K 3/30 - Assembling printed circuits with electric components, e.g. with resistor
H05K 3/34 - Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
The semiconductor device includes a chip having side surface, and an ornamental pattern formed in the side surface. The chip includes a semiconductor layer of a first conductivity type, and the ornamental pattern includes a mark of a second conductivity type that is formed in a portion constituted of the semiconductor layer in the side surface. The side surface includes a first side surface extending in a first direction in plan view and a second side surface extending in a second direction intersecting the first direction in plan view, and the ornamental pattern includes at least one of mark formed in one or both of the first side surface and the second side surface.
H10D 62/00 - Semiconductor bodies, or regions thereof, of devices having potential barriers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes a first semiconductor element, a second semiconductor element, a first lead, a second lead, a first wire, and a first bump-stacked body. The first lead is electrically connected to the first semiconductor element. The second lead is electrically connected to the second semiconductor element and is separated from the first lead. The first wire electrically connects the first semiconductor element and the second semiconductor element. The bump-stacked body includes a plurality of bumps stacked in a thickness direction of the first semiconductor element. The first wire includes a first end overlapping with the first semiconductor element and a second end overlapping with the second semiconductor element in the thickness direction. The first bump-stacked body is located between the first semiconductor element and the first end or between the second semiconductor element and the second end.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
58.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device, the method includes mounting a semiconductor element on a lead frame, placing a mold to position the semiconductor element within a cavity of the mold, forming a resin intermediate by introducing a resin material into the cavity and hardening the resin material, and cutting the lead frame and the resin intermediate. The mold includes: a mold first surface and a mold second surface, a mold third surface, a mold fourth surface, and a mold fifth surface. The mold fifth surface includes a mold first section, a mold second section, and a mold third section. At least a portion of the mold third section is inclined relative to the second direction and the third direction as viewed in the first direction.
The level voltage generation circuit includes: a resistor string that outputs multiple level voltages having different voltage levels respectively from multiple taps; a reference voltage generation part that generates m reference voltages having different voltage values respectively according to a desired gamma characteristic; and first to mth gamma buffers that operate by receiving supply of power supply voltages to individually amplify the m reference voltages, and generate and output m gamma voltages to m taps. At least one gamma buffer includes: an offset cancellation amplifier including an offset cancellation circuit that removes an offset occurring in the gamma voltage output by the gamma buffer itself in response to a binary control signal; and a control signal output circuit that generates the control signal with two voltages as the binary, and outputs the control signal to the offset cancellation circuit. The two voltages are selected from the m gamma voltages and the power supply voltages, and have a voltage difference lower than the power supply voltages.
G09G 3/20 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
The switch device includes an input terminal, an output terminal, an output transistor provided between the input terminal and the output terminal, and a control circuit configured to, under its control, turn on or off the output transistor in response to a control signal. The control circuit is enabled to execute a protective operation by which the output transistor is switched over from on to off independent of the control signal on a basis of an outside temperature of the switch device and an output current flowing through the output transistor.
A signal transmission device includes a first logic, a second logic, a plurality of isolation devices configured to isolate and transmit a plurality of sets of first signals and second signals between the first logic and the second logic, and a plurality of output circuits configured to generate a plurality of output signals according to instructions from the second logic. The first logic is capable of simultaneously transmitting a plurality of combinations of signals from different sets among the plurality of sets of the first signals and the second signals. The second logic performs operations according to the combination of signals received via the plurality of isolation devices from among the plurality of sets of the first signals and the second signals.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
A RAM includes a first bit line and a second bit line arranged on different layers. One of the first bit line and the second bit line has a first connection line formed on the same layer as the other of the first bit line and the second bit line, so as to be connected to a memory cell. A first inverted bit line and a second inverted bit line are arranged on different layers, and one of the first inverted bit line and the second inverted bit line has a second connection line formed on the same layer as the other of the first inverted bit line and the second inverted bit line, so as to be connected to the memory cell.
A motor controller includes a control circuit configured to perform vector control of a motor, and a driver configured to supply the motor with an applied voltage on the basis of an output from the control circuit. The control circuit compares the applied voltage with an induced voltage of the motor obtained by calculation, and if the induced voltage is higher than the applied voltage, the control circuit determines that the motor is in an out-of-step state.
A semiconductor device comprises a die pad having a penetration portion that penetrates in a first direction, a semiconductor element bonded to the die pad and a sealing resin covering the semiconductor element, the sealing resin having an attachment portion that penetrates in the first direction and is surrounded by the penetration portion as viewed in the first direction. The die pad includes a first portion having a reverse surface that faces the first direction, and a second portion having the penetration portion and connected to the first portion. The second portion is offset on one side of a second direction with respect to the first portion. The reverse surface is exposed from the sealing resin. The second portion is covered with the sealing resin.
The semiconductor device includes a first die pad, a second die pad, a first suspension lead, a second suspension lead and a sealing resin. The first and second suspension leads are spaced apart from two first side faces of the sealing resin and exposed to the outside from the second side face of the sealing resin. The first suspension lead includes a first inner portion covered by the sealing resin and a first outer portion connected to the first inner portion. As viewed in a third direction, the first inner portion includes a first portion extending from a boundary defined by the extension line of a first edge of the first die pad to the first die pad. The cross-sectional area of the first portion in its extension direction is larger than that of the first outer portion in its extension direction.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
66.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device includes a semiconductor region of a first conductivity type, a plurality of base impurity regions of a second conductivity type that each extend in a first direction and are arranged in a second direction, a first impurity region that is located in a second surface layer section of each of the plurality of base impurity regions, and a plurality of second impurity regions that are each arranged in a separated manner in the first direction and have the opposite conductivity type from the first impurity region. Each of the plurality of second impurity regions neighbors the first impurity region in the second direction. The plurality of second impurity regions that are arranged in the second direction include at least one outside second impurity region that is located furthest to the outside in the second direction, and a plurality of inside second impurity regions that are located further to the inside than the outside second impurity region. The inside second impurity regions are sandwiched by the first impurity region from both sides in the second direction. The first impurity region is positioned on one side of the outside second impurity region in the second direction, and is not positioned on the other side of the outside second impurity region in the second direction.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A drive circuit includes: a level shift circuit configured to convert a plurality of first pulse signals to a plurality of low-level set pulse signals, respectively, and output the set pulse signals sequentially to a first transmission line, and configured to convert a second pulse signal to a low-level reset pulse signal and output the reset pulse signal to a second transmission line; a detection circuit configured to output a first detection signal in response to detecting that a first voltage is at a low level, and output a second detection signal in response to detecting that a second voltage is at a low level; and a restoration circuit configured to set a switching element, which is provided between a power supply line of a high-side power supply potential and the first transmission line, to the on state in response to a first-first detection signal output from the detection circuit.
A semiconductor device includes a first semiconductor chip and a second semiconductor chip connected to each other. The first semiconductor chip includes a first alignment mark and a second alignment mark composed of conductors electrically isolated from each other, and a first terminal and a second terminal electrically connected to the first alignment mark and the second alignment mark. The second semiconductor chip includes a guard ring including an annular conductor provided along an outer edge of the second semiconductor chip, and a third alignment mark and a fourth alignment mark composed of conductors electrically connected to the guard ring. The first semiconductor chip and the second semiconductor chip are connected such that the first alignment mark and the third alignment mark overlap with each other, and the second alignment mark and the fourth alignment mark overlap with each other.
A switch device has a control circuit that turns on or off an output transistor disposed between two terminals in accordance with a control signal. When an abnormality is detected in an ON period of the output transistor, the control circuit turns off the output transistor or restricts a current value of the output transistor and switches a state of a diagnostic terminal from a first state to a second state, so as to switch a voltage level of the diagnostic terminal from a first level to a second level. During the ON period of the output transistor, when no abnormality is detected and the voltage level of the diagnostic terminal is changed from the first level to the second level, the control circuit turns off the output transistor.
H03K 17/0814 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the output circuit
H03K 3/3565 - Bistables with hysteresis, e.g. Schmitt trigger
H03K 17/14 - Modifications for compensating variations of physical values, e.g. of temperature
A semiconductor device includes an n-type (a first conductivity type) semiconductor layer having a first main surface; a p-type (a second conductivity type) first region extending in a first direction along the first main surface within the semiconductor layer; a p-type second region formed in a region on the first main surface side relative to the first region within the semiconductor layer and extending in a second direction along the first main surface so as to intersect the first region three-dimensionally; and a p-type low-concentration region formed at least at an intersection portion of the first region and the second region within the semiconductor layer and having a concentration lower than both a maximum concentration of the first region and a maximum concentration of the second region.
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
71.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
The signal transmission device includes first, second and third chips. The first and second chips includes respectively: a first input pad; an ADC that converts a first analog signal inputted to the first input pad into a first digital signal; a first transmission circuit that generates a first pulse signal in correspondence to the first digital signal; a first output pad that outputs the first pulse signal; a second input pad; a first reception circuit that generates a second digital signal in correspondence to a second pulse signal inputted to the second input pad; a DAC that converts the second digital signal into a second analog signal; and a second output pad that outputs the second analog signal. The third chip, upon receiving the first pulse signal from the first output pad of the first chip, outputs the second pulse signal to the second input pad of the second chip.
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
In the semiconductor device, when bridge select data contained in received data indicates on status of through output of bit data, i.e. output of bit data as it is intact, between a first bus and a second bus, first device-dedicated data contained in the received data is through-outputted to the second bus, and moreover, when the bridge select data indicates on status of the through output and when communication by a specified second serial communication method dedicated to the first device has been set to the semiconductor device, a clock signal synchronized with the through-outputted data as well as a chip select signal are outputted.
A switching control device includes: a PWM duty cycle conversion unit configured to convert voltage command signals of three phases into PWM duty cycles; a PWM duty cycle adjustment unit configured to simultaneously adjust the PWM duty cycles of the three phases at the same time using the same adjustment value; a pulse generation unit configured to generate pulse signals from the PWM duty cycles adjusted by the PWM duty cycle adjustment unit; and an inverter circuit configured to include a plurality of switching elements that are driven by the pulse signals generated by the pulse generation unit.
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
A motor drive device includes: a check performance unit configured to perform an abnormality check operation for at least one of an upper transistor, a lower transistor and a motor in a state where a second main electrode is pulled up or pulled down by bringing one of a second main electrode pull-down switch and a second main electrode pull-up switch into an on state; and a control circuit configured to control a combination of on/off states of the upper transistor, the lower transistor and a motor relay connected to the motor.
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
H02H 7/08 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for dynamo-electric motors
H02K 7/14 - Structural association with mechanical loads, e.g. with hand-held machine tools or fans
H02K 19/10 - Synchronous motors for multi-phase current
75.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE AND VEHICLE
A signal transmission device includes: a signal transmission circuit that transmits a pulse signal from a primary circuit system to a secondary circuit system in an isolated manner; a power supply circuit that generates an output voltage from an input voltage in an isolated manner; first and second abnormality detection circuits that detect an abnormality in the primary circuit system and secondary circuit system; a signal transmission path that transmits an output of the second abnormality detection circuit from the secondary circuit system to the primary circuit system in an isolated manner; and a self-diagnosis circuit that performs self-diagnosis on each of the first and second abnormality detection circuits and the signal transmission path. The first abnormality detection circuit includes, as a diagnostic target, a power supply abnormality detector that detects an abnormality in the power supply circuit. The self-diagnosis circuit first diagnoses on the power supply abnormality detector.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A power supply circuit includes: a feedback control circuit configured to control a switch output stage for generating an output voltage of a secondary circuit system from an input voltage of a primary circuit system while isolating between the primary circuit system and the secondary circuit system; and an overcurrent protection circuit configured to restrict a sense voltage corresponding to a primary current of the switch output stage to a predetermined overcurrent detection value or less. The overcurrent protection circuit stepwise increases the overcurrent detection value over a soft start period when a second power supply voltage is started or restarted.
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
77.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.
This semiconductor light-emitting device includes a semiconductor light-emitting element mounted on a first substrate surface of a substrate, and a drive circuit for driving the semiconductor light-emitting element. The substrate includes a second surface electrode and a first surface electrode. The semiconductor light-emitting element includes: a first element surface that includes a light-emitting region from which light is emitted; an anode electrode that is provided on the side opposite from the first element surface and is electrically connected to the second surface electrode; a cathode electrode that is provided on the side opposite from the first element surface and is electrically connected to the first surface electrode; a semiconductor substrate; and a semiconductor layer that is configured to generate light. The semiconductor light-emitting element is mounted on the substrate such that the semiconductor layer is disposed between the semiconductor substrate and the substrate in a Z-axis direction.
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
H01S 5/0239 - Combinations of electrical or optical elements
This semiconductor device comprises a first-conductivity-type semiconductor layer having a main surface, a plurality of trench-electrode-type gate structures formed at intervals on the main surface, a first mesa partitioned on the semiconductor layer by the plurality of gate structures, a second mesa partitioned on the semiconductor layer by the plurality of gate structures outside the first mesa, an FET structure that is formed in the first mesa and has a bipolar diode, and a rectification structure that is formed in the second mesa and has a unipolar diode.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A test method according to one embodiment includes: a step of preparing a test circuit having first and second series circuits; a drive step of driving a first driven switch unit in the first series circuit by means of a two-pulse type first drive signal having first and second pulses, and driving a second driven switch unit in the second series circuit by means of a one-pulse type second drive signal having a third pulse; and a monitoring step of monitoring the voltage of the first driven switch unit and the voltage of a switch unit that is among the two switch units in the first series circuit and different from the second driven switch unit. The time difference between the rising timing of the second pulse and the falling timing of the third pulse is defined as an interference time, and conditions for oscillation to occur in the second driven switch unit are acquired while adjusting the interference time.
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
81.
SEMICONDUCTOR DEVICE, METHOD FOR DESIGNING THE SAME, AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device is provided with a first lead and a second lead spaced apart from each other in a first direction, a first semiconductor element including a first functional part and supported by the first lead, and a second semiconductor element including a second functional part and supported by the second lead. Each of the first functional part and the second functional part transmits an electrical signal in an insulated state. The distance d1 between the first lead and the second lead in the first direction is greater than a predetermined distance d0.
A semiconductor light emitting device includes a substrate, a common conductive portion formed on the substrate, a semiconductor light emitting element mounted on the common conductive portion, and an electronic component mounted on the common conductive portion and electrically connected to the semiconductor light emitting element by the common conductive portion. This structure shortens the conductive path between the semiconductor light emitting element and the electronic component, thereby reducing capacitance caused by the conductive path between the semiconductor light emitting element and the electronic component. Thus, while reducing parasitic capacitance, the semiconductor light emitting element and the electronic component are electrically connected.
H01S 5/0239 - Combinations of electrical or optical elements
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
A semiconductor device includes a plurality of leads, a semiconductor element supported by the leads and connected to at one or more of the leads, and a sealing resin covering a part of each lead and the semiconductor element. As viewed in the thickness direction, the center of the semiconductor element is offset with respect to the center of the sealing resin in a first direction. The plurality of leads includes a first lead located closest to the first corner of the sealing resin on the one side of the first direction. The end face and the reverse surface of the first lead are exposed from the sealing resin. The area of the exposed reverse surface is greater than that of the reverse surface of a lead provided adjacent to the first lead.
A semiconductor device including: a chip having a main surface; a trench electrode type gate structure formed on the main surface, the gate structure including a trench formed on the main surface, a trench insulating film that covers an inner surface of the trench, and a buried conductive layer embedded in the trench via the trench insulating film; a recess defined by an upper surface of the buried conductive layer and side surfaces of the trench; and a buried insulating layer embedded in the recess. The buried conductive layer is formed of a conductive material having a lower resistance than polysilicon.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/60 - Electrodes characterised by their materials
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
85.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor chip including first and second main surfaces. A first semiconductor region of a first conductivity type is formed in the semiconductor chip near the first main surface. A second semiconductor region of a second conductivity type is formed closer to the second main surface than the first semiconductor region is. A trench structure includes a trench extending from the first main surface and partitioning the first semiconductor region into first and second regions. A control insulation film covers a wall of the trench. A control electrode is embedded in the trench with the control insulation film interposed to electrically connect the first and second regions. A third semiconductor region of the first conductivity type is formed closer to the second main surface than the second semiconductor region. The third semiconductor region and the trench structure sandwich the second semiconductor region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
86.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes multiple GaN units arranged separately from each other in a first direction in a first encapsulation resin. The GaN unit includes a substrate, a GaN transistor arranged at a substrate front surface side of the substrate, and a post arranged on a source pad, a drain pad, and a gate pad of the GaN transistor and exposed from the first encapsulation resin. The post includes a source post formed on the source pad in one of two adjacent ones of the GaN units in the first direction, and a drain post formed on the drain pad in the other one of the two adjacent ones of the GaN units in the first direction. The semiconductor device includes an interconnect layer arranged on an encapsulation front surface and electrically connects the source post and the drain post.
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/00 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
An electronic device includes a wiring layer, an electronic element conductively bonded to the wiring layer, and a sealing resin covering the electronic element. The sealing resin includes a top surface facing in a first direction and located opposite to the wiring layer with respect to the electronic element in the first direction. The electronic device further includes a pillar extending in the first direction and electrically connected to the wiring layer, and a shield covering at least a portion of the top surface and electrically connected to the pillar. The pillar includes a peripheral surface facing in a direction orthogonal to the first direction and a connection surface facing a same side as the top surface in the first direction. The peripheral surface is covered with the sealing resin. The connection surface is in contact with the shield.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
A storage device includes a first and a second storage portion configured to store data with opposite polarities, and an error sensing portion configured to sense an error if the outputs of the first and second storage portions have the same polarity.
G01P 15/125 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration by making use of inertia forces with conversion into electric or magnetic values by capacitive pick-up
G01P 15/18 - Measuring accelerationMeasuring decelerationMeasuring shock, i.e. sudden change of acceleration in two or more dimensions
H03K 19/21 - EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one inputCOINCIDENCE circuits, i.e. giving output only if all input signals are identical
A semiconductor chip being a transient voltage suppressor (TVS) diode includes: a first pin junction part and a second pin junction part which are in a first polarity direction; and a diode pair region which, when viewed in plan view, is provided spaced apart from both the first pin junction part and the second pin junction part. The diode pair region includes: a first reverse pin junction part and a second reverse pin junction part which are in a second polarity direction; and a pn junction part in the first polarity direction, which, when viewed in plan view, is provided at a position overlapping the first reverse pin junction part and the second reverse pin junction part and which constitutes the first reverse pin junction part, the second reverse pin junction part and a diode pair. When viewed in plan view, the diode pair region is arranged between the first pin junction part and the second pin junction part.
A semiconductor device according to the present invention comprises: a chip that has a main surface; a first conductivity type semiconductor region that is formed in a surface layer part of the main surface; an active region that is provided in the inner part of the main surface; an outer peripheral region that is provided in the peripheral part of the main surface; a device structure that is formed in the active region; and a plurality of annular second conductivity type field regions that are formed in the outer peripheral region at intervals in the surface layer part of the semiconductor region and that surround the active region, wherein the intervals between the plurality of field regions each become wider in the direction from the active region toward the outer peripheral region, the widths of the plurality of field regions each decrease in the direction from the active region toward the outer peripheral region, the field regions each have a first upper end part on the main surface side and a first lower end part on the opposite side, and the field regions each have a concentration gradient which gradually decreases from the first upper end part toward the first lower end part.
A semiconductor device according to the present invention includes a chip that has a principal surface, a trench electrode–type gate structure that is formed on the principal surface and includes a trench that is formed in the principal surface, a trench insulation film that covers an inner surface of the trench, and a buried electroconductive layer that is buried in the trench with the trench insulation film therebetween, a recess that is defined by an upper surface of the buried electroconductive layer and a side surface of the trench, and a buried insulation layer that is buried in the recess. The buried electroconductive layer has a layered structure that includes a first electroconductive layer that is formed from polysilicon and a second electroconductive layer that is formed from an electroconductive material that has a lower resistance than the polysilicon.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/60 - Electrodes characterised by their materials
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
92.
ADJUSTMENT CIRCUIT AND ADJUSTMENT METHOD USING THE SAME, CURRENT ADJUSTMENT CIRCUIT AND CURRENT ADJUSTMENT METHOD USING THE SAME, OPERATIONAL AMPLIFIER, AND OFFSET ADJUSTMENT METHOD
An adjustment circuit is disposed between a first node and a second node. The adjustment circuit comprises a plurality of disconnection target elements connected in series and is configured such that the first node and the second node are electrically connected via the adjustment circuit when none of the plurality of disconnection target elements are disconnected, and the adjustment circuit is open as viewed from the first node when at least one of the plurality of disconnection target elements is disconnected.
A semiconductor chip of a TVS diode includes a first surface and a second surface at aside opposite the first surface. The semiconductor chip includes first and second pin junctions fora first polarity direction, and a diode-paired region. The diode-paired region includes a high-concentration region of a first conductance type, first and second low-concentration regions that have a lower impurity concentration than the high-concentration region, an isolation region isolating the first and second low-concentration regions, first and second contact regions of a second conductance type, and an internal region of the second conductance type contacting the high-concentration region and arranged closer to the second surface than the high-concentration region. The internal region is arranged overlapping both the first and second low-concentration regions in plan view.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor device includes a semiconductor element with an element main surface facing in a thickness direction and being provided with an electrode, and a sealing resin including a resin top surface facing a first side of the thickness direction. The sealing resin covers the semiconductor element. The element main surface and the resin top surface are rectangular. The first edge of the element main surface is inclined with respect to the second edge of the resin top surface, as viewed in the thickness direction.
A semiconductor device comprises a conductive support member that includes a die pad including an obverse surface facing a first side in a thickness direction, and the first terminal apart from the die pad and entirely on a first side in a first direction regarding the die pad; a semiconductor element on the obverse surface; a wire conducted to the semiconductor element and the terminal; and a sealing resin. The resin includes a top surface facing the first side in the thickness direction; a side surface facing the first side in the first direction; the terminal exposed from the side surface; and an inclined surface connected to the top and side surfaces. The inclined surface forming a greater angle with the obverse surface than the top surface does. A portion of the wire bonded to the terminal does not overlap the inclined surface, viewed in the thickness direction.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A semiconductor chip of a TVS diode includes a first pin junction portion of a first polarity direction and a diode pair region. The diode pair region includes a first reverse pin junction portion of a second polarity direction provided spaced apart from the first pin junction portion in a plan view, and a pn junction portion of the first polarity direction that forms a diode pair with the first reverse pin junction portion. The first pin junction portion includes a p-type first-terminal-side high-concentration region, an n-type first-terminal-side low-concentration region at a position overlapping the first-terminal-side high-concentration region in the plan view, an n-type first-terminal-side contact region, and a p-type first buffer region in contact with the first-terminal-side high-concentration region between the first-terminal-side high-concentration region and the first-terminal-side low-concentration region in a thickness direction of the semiconductor chip.
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
97.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE INCORPORATING THE SIGNAL TRANSMISSION DEVICE, AND VEHICLE INCORPORATING THE ELECTRONIC DEVICE
A signal transmission device includes a transmission circuit, a reception circuit, and an isolation circuit. The transmission circuit is configured to drive at least one of a first internal signal and a second internal signal at a specific period according to an external signal. The reception circuit includes: a detection circuit configured to be able to detect that the period of at least one of the first internal signal and the second internal signal is the specific period; a first driving circuit configured to set the gate of a switching device to high impedance state according to the detection result of the detection circuit; and a second driving circuit configured to turn ON the switching device by inputting a specific voltage to the gate according to the detection result. The specific voltage has a voltage value higher than or equal to the ON threshold voltage of the switching device.
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
H02P 23/00 - Arrangements or methods for the control of AC motors characterised by a control method other than vector control
98.
SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING SAME
A semiconductor device includes: a semiconductor element configured to output a compensation voltage; a constant current circuit configured to output a constant current so as to compensate for temperature dependence according to the comparison of the compensation voltage and a reference voltage; an oscillation circuit configured to output an oscillation signal according to the constant current; a check voltage generation circuit configured to output a check voltage; and a signal generation circuit configured to output a temperature information signal corresponding to the compensation voltage and the check voltage.
A semiconductor device includes a chip that has a main surface, a trench that is formed in the main surface, and that has a side wall and a bottom wall, an embedded electrode that is embedded in the trench, and that has an electrode surface positioned on the bottom wall side with respect to the main surface and a recess edge portion recessed toward the bottom wall side at an edge portion along the side wall in the electrode surface, and an edge portion insulator that is embedded in the recess edge portion.
A semiconductor device includes a first semiconductor element, a plurality of leads, a plurality of wires and a sealing resin covering the first semiconductor element, the plurality of wires, and at least a part of each of the plurality of leads. The plurality of leads include a first lead. The plurality of wires include a plurality of first wires each having a first bonding portion connected to the first semiconductor element and a second bonding portion connected to the first lead. The first lead includes a first portion extending in an x first direction. The second bonding portions of the plurality of first wires are connected to the first portion and arranged in a plurality of rows along the x direction.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
