A semiconductor device includes: a semiconductor chip including a single layer having a first principal surface and a second principal surface on an opposite side to the first principal surface; a first semiconductor region of a first conductivity type formed on the first principal surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second principal surface side with respect to the first semiconductor region of the semiconductor chip; and a first trench structure including a first trench that penetrates the first semiconductor region from the first principal surface and partitions the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view, a control insulating film that covers an inner wall of the first trench, and a control electrode that is embedded in the first trench with the control insulating film interposed therebetween and controls a channel in the second semiconductor region that makes the first region and the second region conductive in a lateral direction along the first principal surface.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A successive approximation A/D converter includes a D/A converter that generates an analog output signal including an analog signal corresponding to a digital input, a comparator that outputs a comparison result between the analog signal and an analog input signal, and a control circuit that generates a digital input on the basis of the comparison result. The control circuit includes a reference register and a plurality of comparison registers each synchronized with the reference register. The reference register outputs a comparison signal obtained by capturing the comparison result. Each of the plurality of comparison registers corresponds to each bit from a most significant bit to a least significant bit, captures the comparison signal of a corresponding bit, and outputs a data signal indicating each bit from the most significant bit to the least significant bit.
H03M 1/46 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives avec convertisseur numérique/analogique pour fournir des valeurs de référence au convertisseur
3.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR TESTING DEVICE
A semiconductor device manufacturing method including a reverse bias test for a device structure includes a step of applying a reverse bias voltage to the device structure, and a monitor step of monitoring a decrease rate of a leak current of the device structure at a time of applying the reverse bias voltage.
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
4.
SEMICONDUCTOR DEVICE, BATTERY MODULE, ELECTRIC POWER MODULE, AND ELECTRIC VEHICLE
A semiconductor device includes a low-voltage side frame configured to be connected to a low-voltage chip driven by an input voltage and connected to a ground potential; and a high-voltage side frame configured to be insulated from the low-voltage side frame and connected to a high-voltage chip supplied with a supply voltage having a higher voltage than the input voltage. The high-voltage side frame is connected to a reference potential.
B60L 50/60 - Propulsion électrique par source d'énergie intérieure au véhicule utilisant de la puissance de propulsion fournie par des batteries ou des piles à combustible utilisant de l'énergie fournie par des batteries
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10D 80/30 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex. des ensembles comprenant des puces de processeur à circuit intégré
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A power supply control device includes: an output stage circuit having a high-side transistor provided between an application terminal of an input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal; a high-side driver; a low-side driver; a switching control circuit for controlling on/off state of the high-side and low-side transistors using the low-side and high-side drivers; a boot terminal for applying a boot voltage; a rectifying element for supplying a charging current to a boot capacitor during an on period of the low-side transistor; a reverse current detection circuit for detecting a specific reverse current state in which a reverse current flows from an output terminal to which the output voltage is applied, toward the low-side transistor via the coil and the switch terminal; and a monitor circuit for monitoring a height of the boot voltage.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
A semiconductor device includes a chip having a principal surface, a gate electrode formed on the principal surface, an interlayer film covering the gate electrode, an opening formed in the interlayer film such as to be separated from the gate electrode in a lateral direction along the principal surface and exposing a part of the chip as a contact portion, and a front surface electrode formed on the interlayer film and mechanically and electrically connected to the contact portion in the opening, wherein the contact portion includes a mesa contact portion that protrudes from the principal surface and has a mesa side portion and a mesa upper portion, and the front surface electrode covers the mesa side portion and the mesa upper portion.
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
7.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
A signal transmission device includes a first chip fed with an input pulse signal and a second chip that drives a switching device by generating an output pulse signal according to the input pulse signal through isolated communication with the first chip. The second chip includes a self-diagnosis circuit that checks whether individual parts of the second chip are operating properly in response to a self-diagnosis instruction transmitted from the first chip only when the output pulse signal is at a logic level corresponding to an off state.
G06F 11/22 - Détection ou localisation du matériel d'ordinateur défectueux en effectuant des tests pendant les opérations d'attente ou pendant les temps morts, p. ex. essais de mise en route
G06F 11/25 - Tests de fonctionnement logique, p. ex. au moyen d'analyseurs logiques
The semiconductor device includes an element support, first and second semiconductor elements on the element support, an insulating element insulating the first and the second semiconductor elements from each other, and an insulating substrate. The insulating element includes a first transceiver electrically connected to the first semiconductor element, a second transceiver electrically connected to the second semiconductor element, and an interfacing member for transmitting and receiving signals between the first and the second transceivers. The interfacing member is closer to the element support than the first and the second transceivers. The insulating substrate is between the element support and the insulating element and bonded to the element support. The insulating element is bonded to the insulating substrate.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
This nitride semiconductor device includes: a gate layer that is formed on an electron supply layer; a gate electrode that is formed on the gate layer; a passivation layer that covers the electron supply layer, the gate layer, and the gate electrode and has a first opening and a second opening that are separated in the X direction; and a field plate electrode that is formed on the passivation layer and is electrically connected to a source electrode. The field plate electrode includes a plate extension that extends to a region between the gate layer and a drain electrode in a plan view and opposes the electron supply layer with the passivation layer therebetween. An opening is formed in the plate extension of the field plate electrode.
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/824 - Hétérojonctions comprenant uniquement des hétérojonctions de matériaux du groupe III-V, p. ex. des hétérojonctions GaN/AlGaN
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
This semiconductor device comprises: a first semiconductor unit; a second semiconductor unit; and a sealing resin that covers a portion of the first semiconductor unit and the second semiconductor unit, the sealing resin having a resin main surface facing a first-direction first side and a resin reverse surface facing a first-direction second side. Each of the first semiconductor unit and the second semiconductor unit has a main surface exposed from the sealing resin to the first-direction first side and a reverse surface exposed from the sealing resin to the first-direction second side.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
11.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
A semiconductor device, including: a semiconductor chip having an element forming surface; an insulating layer formed on the element forming surface of the semiconductor chip; a barrier conductive layer formed on the insulating layer; a pad wiring layer including a plurality of conductive layers, one of the plurality of conductive layers including an eaves portion protruding to an outward direction; a bonding member that is bonded to the pad wiring layer and supplies electric power to an element of the element forming surface; and a coating insulating film that is selectively formed on the insulating layer below the eaves portion, exposes an upper surface of the insulating layer to a peripheral region of the pad wiring layer, and coats both an upper surface and a side surface of an end portion of the barrier conductive layer.
A controller circuit includes a major controller and a minor controller. The major controller controls a major loop in which a rotational speed of a motor serves as a controlled variable. The minor controller controls a minor loop in which a current flowing through the motor serves as a controlled variable. A sixth coefficient that defines a bandwidth of the minor controller is determined relative to a third coefficient that defines a bandwidth of the major controller.
H02P 23/00 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par un procédé de commande autre que la commande par vecteur
H02P 23/16 - Commande de la vitesse angulaire d’un arbre
A semiconductor module includes a cooler, a plurality of semiconductor devices, and a capacitor. The cooler includes a housing having a receiving portion and a hollow portion that is disposed externally around the receiving portion as viewed in a first direction. The housing has a first surface, a second surface, and a third surface on which the plurality of semiconductor devices are respectively mounted. Each of the first surface, the second surface, and the third surface faces away from the receiving portion with respect to the hollow portion in a direction orthogonal to the first direction. The first surface, the second surface and the third surface each have a different normal direction. At least a part of the capacitor is housed in the receiving portion.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
B60L 15/20 - Procédés, circuits ou dispositifs pour commander la propulsion des véhicules à traction électrique, p. ex. commande de la vitesse des moteurs de traction en vue de réaliser des performances désiréesAdaptation sur les véhicules à traction électrique de l'installation de commande à distance à partir d'un endroit fixe, de différents endroits du véhicule ou de différents véhicules d'un même train pour la commande du véhicule ou de son moteur en vue de réaliser des performances désirées, p. ex. vitesse, couple, variation programmée de la vitesse
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
The PI compensator generates a manipulated variable based on an error between a detected value of a motor controlled variable and a reference value of the controlled variable. An automatic tuning circuit optimizes the parameters of the PI compensator. An integrator integrates the error. A first coefficient circuit multiplies the output of the integrator by a first coefficient B. An adder adds the output of the first coefficient circuit and the error. A second coefficient circuit multiplies the output of the adder by a second coefficient A. The automatic tuning circuit varies the first coefficient B and adjusts it to a value where the phase difference between the error and the controlled variable becomes 90 degrees.
G05B 11/42 - Commandes automatiques électriques avec les dispositions nécessaires pour obtenir des caractéristiques particulières, p. ex. proportionnelles, intégrales, différentielles pour obtenir une caractéristique à la fois proportionnelle et dépendante du temps, p. ex. P.I., P.I.D.
15.
SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
A semiconductor light emitting device is provided with: a substrate; an end surface emitting element that is mounted on the substrate; a cap that houses the end surface emitting element; and an adhesive that bonds the cap and the substrate to each other. The substrate is provided with a substrate through hole at a position where the substrate overlaps with the adhesive in a plan view. The semiconductor light emitting device comprises a bonding pattern that is formed on the substrate so as to surround the end surface emitting element in a plan view. The adhesive is provided on the bonding pattern and bonds the bonding pattern and the cap to each other. A pattern through hole, which is in communication with the substrate through hole, is formed in the bonding pattern. Some of the adhesive is in the pattern through hole.
A semiconductor device comprising a terminal, a semiconductor element and a sealing resin. The semiconductor element is disposed on one side of the terminal in a first direction and electrically connected to the terminal. The sealing resin covers the semiconductor element and a part of the terminal. The sealing resin has a bottom surface disposed on an opposite side to the semiconductor element with respect to the terminal in the first direction. The terminal extends beyond the bottom surface.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A display driver and a display device including the same include multiple circuit blocks, each of which generates a signal representing, through time division multiplexing, voltage values corresponding to brightness levels indicated by respective K pixel data pieces as a drive signal, and generates first to Qth pixel data signals representing the K pixel data pieces with Q signals by time division multiplexing at least one pair of pixel data pieces consisting of two data pieces from among the K pixel data pieces. Each of the circuit blocks converts the first to Qth pixel data signals into first to Qth gradation voltages, for each of horizontal scanning periods, generates a gradation voltage signal representing, through time division multiplexing, voltage values corresponding to the respective K pixel data pieces expressed by the first to Qth gradation voltages, and outputs a signal amplified from the gradation voltage signal as the drive signal.
G09G 3/36 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques pour la présentation d'un ensemble de plusieurs caractères, p. ex. d'une page, en composant l'ensemble par combinaison d'éléments individuels disposés en matrice en commandant la lumière provenant d'une source indépendante utilisant des cristaux liquides
G09G 3/3275 - Détails des circuits de commande pour les électrodes de données
18.
DRIVING CIRCUIT, SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
A driving circuit includes a first transistor between an application terminal for an on-voltage and the control terminal of a switching device, a second transistor and a constant current circuit in parallel between an application terminal for an off-voltage and the control terminal of the switching device, and a logic circuit configured to control the driving of the first and second transistors and the constant current circuit. The logic circuit includes, as driving phases for the switching device, a first phase where the first transistor is on and the second transistor and the constant current circuit are off, a second phase where the first transistor is off and the second transistor and the constant current circuit are on, and a third phase where the first and second transistors are off and the constant current circuit is on.
H03K 19/003 - Modifications pour accroître la fiabilité
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
A conduction circuit includes a first primary coil that is connected to a pulse supply circuit, and a first secondary coil that is electromagnetically coupled to the first primary coil. The pulse supply circuit is configured to supply a pulse signal to the first primary coil under a state in which a control signal is at a first level, and supply a pulse signal to a second primary coil for a certain period after a time point when the control signal is switched from the first level to a second level that is different from the first level.
H03K 17/691 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ avec une isolation galvanique entre le circuit de commande et le circuit de sortie utilisant un couplage par transformateur
H03K 17/082 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension par réaction du circuit de sortie vers le circuit de commande
H03K 17/74 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de diodes
A semiconductor device includes a drift region of a first conductivity type that is formed in an interior of a chip and a plurality of FLRs that are formed in a surface layer portion of a first principal surface in an outer peripheral region such as to surround an active region, each FLR has FLR curve portions, each being of a curve shape in plan view shape, in four corner portions, each FLR has FLR rectilinear portions, each being of a rectilinear shape in plan view shape, between the four corner portions, and each FLR curve portion has a double-diffused structure including a first diffusion region at an inner side and a second diffusion region at an outer side that is lower in impurity concentration of a second conductivity type than the first diffusion region.
A semiconductor device comprises a receiving section configured to receive a reception data as serial data from an outside, and an anomaly check section configured to check for a presence or absence of an anomaly, whose cause can be identified, by checking the reception data.
A semiconductor device includes a first die pad, a first semiconductor element, a second die pad, a second semiconductor element, a sealing resin, a first lead, a second lead, a third lead, and a fourth lead. The first lead, the second lead, the third lead, and the fourth lead are each spaced apart from the third side and the fourth side of the sealing resin and are exposed externally from either the first side surface or the second side surface of the sealing resin. Viewed in a third direction perpendicular to the first direction and the second directions, an area of the first die pad is larger than an area of the second die pad. Viewed in the third direction, each of the first lead and the third lead is separated away in the first direction from a first virtual line toward a side where the first side surface of the sealing resin is located.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A semiconductor device (10) comprises: a semiconductor layer (20) including a first surface (20S); an IGBT region (21); a diode region (22); anode regions (25A) provided in the diode region (22); an insulating layer (30) provided on the first surface (20S) so as to cover the IGBT region (21) while exposing the diode region (22); a first electrode layer (40) including a first electrode section (41) provided on the insulating layer (30) correspondingly with respect to the IGBT region (21), and a second electrode section (42) that and is provided correspondingly with respect to the diode region (22) on the first surface (20S) and set apart from the first surface (20S); and an electroconductive protective layer (90) that is provided between the second electrode section (42) and the first surface (20S) and electrically connects the second electrode section (42) and the anode regions (25A). The protective layer (90) is constituted by electroconductive polysilicon.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
This terahertz system includes: a first oscillation element capable of generating a first terahertz wave by oscillation; and a second oscillation element capable of generating a second terahertz wave by oscillation. The terahertz system includes a detection element disposed at a position where the first terahertz wave and the second terahertz wave are detected. The terahertz system includes: a superimposing circuit that applies, to the first oscillation element, a first drive signal on which a first modulation signal having a first modulation frequency is superimposed; and a superimposing circuit that applies a second drive signal on which a second modulation signal having a second modulation frequency is superimposed.
G01N 21/3581 - CouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge en utilisant la lumière de l'infrarouge lointainCouleurPropriétés spectrales, c.-à-d. comparaison de l'effet du matériau sur la lumière pour plusieurs longueurs d'ondes ou plusieurs bandes de longueurs d'ondes différentes en recherchant l'effet relatif du matériau pour les longueurs d'ondes caractéristiques d'éléments ou de molécules spécifiques, p. ex. spectrométrie d'absorption atomique en utilisant la lumière infrarouge en utilisant un rayonnement térahertz
G01V 3/12 - Prospection ou détection électrique ou magnétiqueMesure des caractéristiques du champ magnétique de la terre, p. ex. de la déclinaison ou de la déviation fonctionnant par ondes électromagnétiques
H03B 7/14 - Production d'oscillations au moyen d'un élément actif ayant une résistance négative entre deux de ses électrodes avec un élément déterminant la fréquence comportant des inductances et des capacités réparties l'élément actif étant un dispositif à semi-conducteurs
H10D 89/00 - Aspects des dispositifs intégrés non couverts par les groupes
A machine learning apparatus includes: a model holder that holds a machine learning model; and a computing unit. The computing unit is configured to: input the input data to the machine learning model and perform inference to calculate a first computation result; input, out of the first computation result, output data contained in the output layer to the machine learning model and perform inference to calculate a second computation result; and calculate a middle-layer error according to a loss function based on a first middle-layer anomaly level calculated based on, out of the first computation result, data contained in the middle layer and a second middle-layer anomaly level calculated based on, out of the second computation result, data contained in the middle layer.
A machine learning device includes a model holding section and a calculation section. The model holding section is configured to hold a machine learning model. The calculation section calculates a first calculation result by inputting input data to the machine learning model so as to perform inference, calculates a second calculation result by inputting output data of the first calculation result to the machine learning model so as to perform inference, and calculates an intermediate layer error on the basis of first intermediate data included in the intermediate layer of the first calculation result and second intermediate data of the second calculation result.
In the simulation apparatus, a model setting unit executes setting related to a chunk as a batch block of data in a case where data are sequentially entered into a machine learning model on a basis of loaded data. A model computing unit executes computations of unsupervised training and computations of prediction by sequentially entering the chunk into the machine learning model. A model storage unit is configured to non-temporarily store not only the machine learning model before execution of the computations of training but also the machine learning model after execution of at least part of the computations of training.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
28.
SIMULATION APPARATUS, RECORDING MEDIUM, AND SIMULATION METHOD
In the simulation apparatus, a model setting unit executes setting related to a chunk as a batch block of data in a case where data are sequentially entered into a machine learning model on a basis of a loaded sequence of data. A model computing unit executes computations of unsupervised training and computations of prediction by sequentially entering the chunk into the machine learning model. The model setting unit sets a range of data for use in computations of unsupervised training from within the sequence of data by a chunk designated with input by an operation input portion.
A manufacturing method of a semiconductor device includes forming a semiconductor layer of a first conductivity type that is located on a substrate, simultaneously forming a first trench having the semiconductor layer as a bottom surface and a second trench that runs through the semiconductor layer, simultaneously forming an insulator that fills up the first trench and an insulating layer that covers the second trench, removing a part of the insulator such that the bottom surface of the first trench is not exposed, removing a part of the insulating layer such that the semiconductor substrate is exposed in the second trench, embedding in the first trench a first conductor that is separated from the semiconductor layer, and embedding in the second trench a second conductor that is in contact with the semiconductor substrate. A width of the second trench is greater than a width of the first trench.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
30.
SIMULATION APPARATUS, PROGRAM, AND SIMULATION METHOD
The simulation apparatus includes a model storage unit in which a motor physical model derived from modeling of a brushed motor has been stored, and a model computing unit configured to execute computing process by using the motor physical model. The motor physical model includes a winding circuit portion derived from modeling of permanent magnets, windings, commutator segments connected to the windings, and brushes contactable with the commutator segments, all of which are of the brushed motor.
A model setting unit executes setting related to a first chunk of input data and a second chunk of training data on a basis of loaded training-purpose data as well as setting related to a third chunk of test input data and a fourth chunk of expected data on a basis of loaded test-purpose data. A model computing unit executes computations of training with use of a machine learning model on a basis of the first chunk and the second chunk, further executes computations of prediction with use of the machine learning model on a basis of results of the training and the third chunk and arithmetically compares results of the prediction and the fourth chunk with each other. The machine learning model after execution of at least part of the computations of training is stored non temporarily.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
32.
SEMICONDUCTOR DEVICE WITH VOLTAGE RESISTANT STRUCTURE
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
This insulating chip comprises: an insulating layer; a first coil and a second coil disposed in the insulating layer; and a second electrode electrically connected to the second coil. The second coil has an annular shape in a plan view as seen from the Z direction. The second electrode includes a second inner electrode that is disposed, when viewed in the plan view, over both an inner region surrounded by the second coil and a region overlapping the second coil. A passivation film formed on the upper surface of the insulating layer includes a second inner opening that exposes at least a portion of the second inner electrode. The second inner opening is formed at a position that is over the second inner electrode, and is over both the inner region and the region overlapping the second coil.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
Provided is a semiconductor device that includes a chip with a principal surface, on which a gate electrode is formed. An interlayer film covers the gate electrode, and an opening is formed in the film, laterally separated from the gate electrode's side portion. This opening exposes part of the principal surface as a contact surface. A front surface electrode is formed on the interlayer film and connects mechanically and electrically to the contact surface. The interlayer film comprises an insulating upper portion in contact with the gate electrode's top, an insulating side portion along its side, and an insulating corner portion along its corner. The thickness of the interlayer film at the corner portion is greater than at least one of the thicknesses at the upper or side portions. This structure enhances insulation and mechanical stability while allowing efficient electrical contact.
A semiconductor light emitting device includes an edge-emitting element including emitters, a first front-surface electrode, a second front-surface electrode, first wires, and second wires. The emitters include a first emitter including a first element electrode, and a second emitter including a second element electrode. The first front-surface electrode is electrically connected to the first element electrode. The second front-surface electrode is electrically connected to the second element electrode. The first wires are electrically connecting the first element electrode to the first front-surface electrode. The second wires are electrically connecting the second element electrode to the second front-surface electrode. In plan view, a largest distance between adjacent ones of the second wires in the first direction is greater than a largest distance between adjacent ones of the first wires in the first direction.
An electrode structure includes a plurality of FLR electrodes, each having, in at least one of four corner portions, an electrode curve portion defined by an inner edge and an outer edge that are circular arcs in plan view. The inner and outer edges of each electrode curve portion have different centers of curvature and different curvatures. For two mutually adjacent electrode curve portions, the relative magnitudes of the curvatures of the inner and outer edges are opposite. Each electrode curve portion thereby includes a region of large width and a region of narrow width between the inner and outer edges. A part of the region of large width in each electrode curve portion is electrically connected to a corresponding FLR through an FLR connection electrode that penetrates an insulating film.
This semiconductor laser element comprises a substrate and at least one light-emitting layer. The at least one light-emitting layer includes a first n-type cladding layer, a second n-type cladding layer, an active layer, a first p-type cladding layer, and a second p-type cladding layer. The aluminum composition of the first n-type cladding layer is smaller than the aluminum composition of the second n-type cladding layer. The aluminum composition of the first p-type cladding layer is smaller than the aluminum composition of the second p-type cladding layer.
H01S 5/323 - Structure ou forme de la région activeMatériaux pour la région active comprenant des jonctions PN, p. ex. hétérostructures ou doubles hétérostructures dans des composés AIIIBV, p. ex. laser AlGaAs
H01S 5/343 - Structure ou forme de la région activeMatériaux pour la région active comprenant des structures à puits quantiques ou à superréseaux, p. ex. lasers à puits quantique unique [SQW], lasers à plusieurs puits quantiques [MQW] ou lasers à hétérostructure de confinement séparée ayant un indice progressif [GRINSCH] dans des composés AIIIBV, p. ex. laser AlGaAs
38.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer, a trench with the semiconductor layer being a bottom surface thereof, and an insulating layer covering a surface of the trench. The semiconductor layer includes a first contact region, a second contact region located on a first impurity region in a surface portion of the semiconductor layer and separated from the first contact region, and a second impurity region located on the first impurity region below the second contact region and in contact with both the first impurity region and the second contact region. The first impurity region and the first contact region are separated from each other.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
39.
SIMULATION APPARATUS, RECORDING MEDIUM, SIMULATION METHOD, AND INFORMATION PROCESSING APPARATUS
In the simulation apparatus, a model setting unit executes setting related to a chunk as a batch block of data in a case where data are sequentially entered into a machine learning model on a basis of loaded data. A model computing unit executes computations of unsupervised training and computations of prediction by sequentially entering the chunk into the machine learning model. The model setting unit executes settings related to calculation accuracy of the machine learning model.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
A machine learning apparatus includes a model holder, a data storage, and a model computing unit. The model holder holds a first machine learning model having undergone supervised learning and a second machine learning model having undergone unsupervised learning. The model computing unit inputs input data to the first machine learning model to generate first output data and inputs the input data also to the second machine learning model to generate accuracy data. The accuracy data is calculated based on a value in at least one of the input layers, the middle layer, and the output layer of the second machine learning model such that the accuracy data changes its tendency in response to the first output data.
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p. ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/17 - Conception mécanique paramétrique ou variationnelle
A semiconductor device includes a first semiconductor layer of a first conductivity type having a first impurity concentration C11, an epitaxial semiconductor layer disposed on the first semiconductor layer, a first device region formed in a first region of the epitaxial semiconductor layer in a plan view, a second device region formed in a second region of the epitaxial semiconductor layer in a plan view, and to which a higher voltage is applied than a voltage applied to the first device region, and a second semiconductor layer of the first conductivity type having a second impurity concentration C12. The second semiconductor layer is formed on the first semiconductor layer within the first region but is not formed on the first semiconductor layer within the second region. The following relationship is satisfied: C11
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
A semiconductor device includes an n-type semiconductor layer, trenches, an insulating layer, a third electrode, and a p-type well region. The trenches extend in a first direction orthogonal to the thickness direction of the semiconductor layer and are spaced apart in a second direction orthogonal to the first direction. The insulating layer covers the trenches. The third electrode is formed in the insulating layer in contact with the first electrode. The well region is formed in the surface of the semiconductor layer. The well region extends in a direction intersecting the first direction and is one well regions spaced apart in the first direction. The surface of the semiconductor layer is in ohmic contact with the first electrode at the well surface of the well region. The surface of the semiconductor layer is in Schottky contact with the first electrode at an exposed surface between the well surfaces.
A semiconductor device of the present invention includes a semiconductor layer of a first conductivity type having a cell portion and an outer peripheral portion disposed around the cell portion, formed with a gate trench at a surface side of the cell portion, and a gate electrode buried in the gate trench via a gate insulating film, forming a channel at a portion lateral to the gate trench at ON-time, the outer peripheral portion has a semiconductor surface disposed at a depth position equal to or deeper than a depth of the gate trench, and the semiconductor device further includes a voltage resistant structure having a semiconductor region of a second conductivity type formed in the semiconductor surface of the outer peripheral portion.
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/60 - Distribution ou concentrations d’impuretés
H10D 62/83 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 62/85 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe III-V, p. ex. GaAs
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/66 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS]
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
44.
AUTONOMOUS MOBILE DEVICE, AUTONOMOUS MOVEMENT IMPROVEMENT SYSTEM, AND METHOD FOR IMPROVING MOVEMENT OF AUTONOMOUS MOBILE DEVICE
A movement improvement method for an autonomous moving apparatus that autonomously moves based on a received signal and an autonomous movement algorithm, the method comprising: acquiring data of a signal received by the autonomous moving apparatus and an image captured by a camera mounted on the autonomous moving apparatus; identifying the data of the signal and the image in a predetermined movement state of the autonomous moving apparatus; and changing the autonomous movement algorithm of the autonomous moving apparatus, based on the identified data of the signal and the image.
G05D 101/10 - Détails des architectures logicielles ou matérielles utilisées pour la commande de la position utilisant des techniques d’intelligence artificielle [IA]
G06V 10/94 - Architectures logicielles ou matérielles spécialement adaptées à la compréhension d’images ou de vidéos
G06V 20/52 - Activités de surveillance ou de suivi, p. ex. pour la reconnaissance d’objets suspects
G06V 20/58 - Reconnaissance d’objets en mouvement ou d’obstacles, p. ex. véhicules ou piétonsReconnaissance des objets de la circulation, p. ex. signalisation routière, feux de signalisation ou routes
A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.
H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives
H01L 21/04 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives les dispositifs ayant des barrières de potentiel, p. ex. une jonction PN, une région d'appauvrissement ou une région de concentration de porteurs de charges
H10D 30/60 - Transistors à effet de champ à grille isolée [IGFET]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 64/23 - Électrodes transportant le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. sources, drains, anodes ou cathodes
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 64/62 - Électrodes couplées de manière ohmique à un semi-conducteur
H10D 64/68 - Électrodes ayant un conducteur couplé capacitivement à un semi-conducteur par un isolant, p. ex. électrodes du type métal-isolant-semi-conducteur [MIS] caractérisées par l’isolant, p. ex. par l’isolant de grille
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
This semiconductor device comprises: a chip having a first main surface and a second main surface; a first-conductivity-type first impurity region on the surface layer portion of the first main surface; a plurality of trenches that are on the first main surface and are arranged at a first pitch; a second-conductivity-type second impurity region and a first-conductivity-type third impurity region that are on the surface layer portion of the first impurity region and are disposed in sequence from the second-main-surface side along the side surfaces of the trenches; an embedded electroconductive layer that is embedded in the trenches and faces the second impurity region with a trench-insulating film interposed therebetween; a plurality of second-conductivity-type bottom wells respectively formed at the bottoms of the plurality of trenches; and a plurality of second-conductivity-type first lower pillars that are arranged, at a second pitch different from the first pitch, within the first impurity region below the plurality of bottom wells.
ppnnn of a second inversion buffer 104. A latch circuit 114 is connected to a first node n1 and a second node n2. A first output buffer 116 and a second output buffer 118 receive a voltage Vn1 of the first node n1 and a voltage Vn2 of the second node n2.
This semiconductor device includes: a function assembly including a semiconductor element; a sealing member that covers the semiconductor element, and contacts the function assembly; and a barrier member having permeability lower than that of the sealing member. The interface between the function assembly and the sealing member includes at least one exposed end. The at least one exposed end is exposed to the outside. The barrier member covers at least a part of the at least one exposed end.
This semiconductor device comprises: a control terminal; a semiconductor element that has a first electrode, a second electrode, and a control electrode; a conductive member that is conductively bonded to the control terminal and the control electrode; and a sealing resin that covers a part of the control terminal, a part of the semiconductor element, and the conductive member. The first electrode has a first pad portion and a first terminal portion electrically connected to the first pad portion. The sealing resin has a first surface and a second surface that face opposite directions along a first direction. The first terminal portion is exposed from the first surface. The second electrode is exposed from the second surface. The control terminal is exposed from either the first surface or the second surface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
50.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element and at least one metal bump. The semiconductor element includes a first electrode. The metal bump is bonded to the first electrode. The metal bump includes a fractured portion spaced apart from the first electrode in a thickness direction of the semiconductor element. As viewed in the thickness direction, a center of the fractured portion is offset from a center of the metal bump. The metal bump includes a large-diameter portion in contact with the first electrode, and a small-diameter portion having a diameter smaller than that of the large-diameter portion. The small-diameter portion is located on a side of the large-diameter portion opposite the first electrode.
A semiconductor device includes a wiring layer, a first semiconductor element, and a first sealing resin. The wiring layer includes a first wiring and a second wiring. The first semiconductor element includes a first electrode and a second electrode disposed opposite to each other in a first direction. The first electrode is electrically bonded to the first wiring. The first sealing resin covers the first semiconductor element. The first sealing resin includes a first surface and a second surface facing away from each other in the first direction. The first surface is closer to the first electrode than to the second electrode. The second wiring is exposed from each of the first surface and the second surface. As viewed in the first direction, the second wiring is spaced apart from the first semiconductor element.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 25/03 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses
A semiconductor device includes a first chip and a second chip. Each chip includes a high-side pad that receives a high-side voltage, a low-side pad that receives a low-side voltage, two or more control pads, an input pad, an output pad, and a functional circuit. In each chip, the two or more control pads are each pulled down to the low-side voltage or pulled up to the high-side voltage. In each chip, the two or more control pads include a target control pad that receives an external control signal. In each chip, an internal control signal is generated on the basis of two or more signals applied to the two or more control pads, and an operation of the functional circuit is controlled on the basis of the internal control signal.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
A semiconductor device includes: a first input terminal configured to be connected to an external voltage; a second input terminal configured to be connected to the external voltage via an external discrete element; a first output terminal configured to be connected to an input node of a first external light emitting element; a second output terminal configured to be connected to an input node of a second external light emitting element; a current driver configured to provide a current to the first output terminal and the second output terminal, and a current distributor configured to control a ratio between a first current flowing from the first input terminal to the current driver and a second current flowing from the second input terminal to the current driver.
B60Q 1/04 - Agencement des dispositifs de signalisation optique ou d'éclairage, leur montage, leur support ou les circuits à cet effet les dispositifs étant principalement destinés à éclairer la route en avant du véhicule ou d'autres zones de la route ou des environs les dispositifs étant des phares
B60Q 1/34 - Agencement des dispositifs de signalisation optique ou d'éclairage, leur montage, leur support ou les circuits à cet effet les dispositifs ayant principalement pour objet d'indiquer le contour du véhicule ou de certaines de ses parties, ou pour engendrer des signaux au bénéfice d'autres véhicules pour indiquer un changement de direction
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/156 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation
An electronic device comprises a first electronic component, a support member including a support surface supporting the first electronic component, a columnar conductor disposed in a direction where the support surface faces with respect to the support member, and a sealing resin formed on the support surface and covering the first electronic component. The columnar conductor includes a conductor top surface facing the same side as the support surface in a thickness direction of the support member. The conductor top surface is covered with the sealing resin.
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
55.
DRIVING DEVICE, SIGNAL PROCESSING DEVICE, ULTRASONIC SENSOR, AND VEHICLE
A driving device includes a transmission wave signal generation circuit configured to generate a transmission wave signal, and a driving circuit configured to drive an ultrasonic oscillation element based on the transmission wave signal. The driving circuit has an initial driving sequence in which the driving circuit generates the transmission wave signal at an initial frequency, a first transition sequence in which the driving circuit generates the transmission wave signal during its transition from the initial frequency to a first frequency, and a second transition sequence in which the driving circuit generates the transmission wave signal during its transition from the first frequency to a second frequency. The initial frequency and the second frequency are closer than the first frequency, to the resonance frequency of the ultrasonic oscillation element. The first transition sequence is allotted a longer time than the time allotted to the second transition sequence.
A voltage detection circuit includes: a self-bias unit, generating a self-bias voltage based on a reference voltage; and detection units, comparing magnitudes of each voltages as a detection target and a reference voltage, and outputting first to nth voltage detection signals indicating whether the voltage is higher than the reference voltage. Each detection units includes: fifth and sixth transistors, respective drains being connected, and, with respective gates receiving one of the voltages, the fifth and sixth transistors outputting a voltage generated at the respective drains as one of the voltage detection signals; seventh and eighth transistors, respectively supplying a current corresponding to the self-bias voltage to the fifth and sixth transistors. The voltage detection circuit includes a current source transistor, causing an operating current based on a bias voltage received by the gate to flow through the self-bias unit and the detection units.
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
G09G 3/00 - Dispositions ou circuits de commande présentant un intérêt uniquement pour l'affichage utilisant des moyens de visualisation autres que les tubes à rayons cathodiques
57.
SEMICONDUCTOR DEVICE, INSULATION SWITCH, AND RECTIFIER CHIP
A semiconductor device includes: a first transformer; a second transformer; a first rectifier chip; a second rectifier chip; and a first frame. Each of the first rectifier chip and the second rectifier chip includes: a first output pad and a second output pad; a semiconductor substrate of a first conductivity type including a first surface; a first semiconductor region of a second conductivity type disposed on the first surface; a first transistor provided in the first semiconductor region and electrically connected to the first output pad; and a second semiconductor region of the second conductivity type provided at a position spaced apart from the first transistor in the first semiconductor region and electrically connected to the second output pad. The second semiconductor region is in contact with the semiconductor substrate. The first rectifier chip and the second rectifier chip are disposed to be spaced apart from each other.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10D 80/20 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif couvert par la présente sous-classe l’au moins un dispositif étant couvert par les groupes , p. ex des ensembles comprenant des condensateurs, des transistors FET de puissance ou des diodes Schottky
A semiconductor device includes: a semiconductor element; a support member; a bonding layer interposed between the semiconductor element and the support member; and a sealing resin that covers the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state, and wherein the support member includes a first surface facing in a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses located outside the bonding layer and recessed from the first surface when viewed along the thickness direction.
A signal transmission device includes a first die, a second die, and a third die that transmits a signal between the first and second dies while isolating between them. The third die includes a first isolating device and a second isolating device. In a first operation mode, a rising edge and a falling edge in an input pulse signal are transmitted from the first die via the first and second isolating devices to the second die. In a second operation mode, a first data signal and a first clock signal are transmitted from the first die via the first and second isolating devices to the second die.
H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
An autonomous moving apparatus identifies a first attraction signal that is output from a first target object as an attraction signal, and causes a moving object to move, based on an incoming direction of the first attraction signal. When a position of the moving object relative to the first target object satisfies a predetermined condition, the attraction signal is switched from the first attraction signal to a second attraction signal that is output from a second target object, and the second attraction signal is identified as the attraction signal. An operation control unit causes the moving object to move, based on an incoming direction of the second attraction signal.
An electronic device includes a conductive support, an electronic element on the conductive support, and a sealing resin covering the electronic element and the conductive support. The sealing resin has a first resin side surface facing in a first direction perpendicular to a thickness direction of the conductive support. The first resin side surface has a first gate mark. The conductive support includes a first region nearest to the first gate mark in the first direction. The first region is positioned inward of the first gate mark in a second direction perpendicular to the thickness direction and the first direction. The first gate mark has a first dimension in the thickness direction. The first gate mark and the first region are spaced in the first direction by a first distance. The ratio of the first distance to the first dimension is less than or equal to 500%.
This semiconductor device includes: a semiconductor element; a first wire connected to the semiconductor element; a second wire connected to the semiconductor element and electrically conductive with the first wire; a first terminal to which the first wire is electrically connected; and a second terminal to which the second wire is electrically connected. The first wire contains a first metal as a main component. The second wire contains, as a main component, a second metal having a different thermoelectric power from the first metal. The first terminal includes a portion including the first metal, and the second terminal includes a portion including the second metal.
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
G01K 7/02 - Mesure de la température basée sur l'utilisation d'éléments électriques ou magnétiques directement sensibles à la chaleur utilisant des éléments thermo-électriques, p. ex. des thermocouples
H01L 21/60 - Fixation des fils de connexion ou d'autres pièces conductrices, devant servir à conduire le courant vers le ou hors du dispositif pendant son fonctionnement
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A semiconductor module according to the present invention comprises a first semiconductor element, a second semiconductor element, a first connection member, and a second connection member. At the first semiconductor element, a first diode is formed between a first electrode and a third electrode, and a second diode is formed between a second electrode and the third electrode. At the second semiconductor element, a third diode is formed between a fourth electrode and a sixth electrode, and a fourth diode is formed between a fifth electrode and the sixth electrode. The first connection member connects the first electrode and the sixth electrode. The second connection member connects the fourth electrode and the third electrode.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/52 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre
H01L 25/04 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
A semiconductor device, including: a semiconductor substrate; the semiconductor layer including a first potential region having a drain region extending in a first direction, a second potential region having a source region surrounding the first potential region, and a drift region between the drain region and the second potential region; a field insulation film covering the drift region; and a field resistive film provided on the field insulation film and electrically connected to the first and second potential regions. The first potential region includes a linear region, and an end region that is continuously connected to the linear region and has a curved outer edge. A distance in the first direction between an end of the drain region and the end of the first potential region is shorter than a distance in a second direction between the drain region and an outer edge of the linear region.
H10D 64/00 - Électrodes de dispositifs ayant des barrières de potentiel
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
The semiconductor device includes a switching element having a first electrode, a second electrode and a third electrode, a semiconductor element having a fourth electrode and a fifth electrode, a sealing resin covering the switching element and the semiconductor element, and a plurality of terminals partially exposed from the sealing resin. The first electrode and the fourth electrode are electrically connected inside the sealing resin. The plurality of terminals include a first terminal, a second terminal, and a third terminal. The first terminal electrically conducts to the second electrode. The second terminal electrically conducts to the fifth electrode. The third terminal electrically conducts to each of the first electrode and the fourth electrode. The first terminal and the second terminal are adjacent to each other.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
A semiconductor device includes leads, a semiconductor element, a sealing resin covering the semiconductor element, and a heat dissipator. The semiconductor element includes first and second electrodes on a first side in a thickness direction. The leads include a first lead, a second lead, and an island lead. The semiconductor element is mounted on the first side in the thickness direction of the island lead. The first lead includes a first comb portion bonded to the first electrode and including a first face facing the first side in the thickness direction. The second lead includes a second comb portion bonded to the second electrode and including a second face facing the first side in the thickness direction. The first face is located on the first side in the thickness direction from the second face. The heat dissipator is bonded to the first face and exposed from the sealing resin.
A semiconductor device includes a first semiconductor layer of a first conductivity type that is positioned on a substrate, an insulator positioned in a recess provided in the first semiconductor layer, a second semiconductor layer of the first conductivity type positioned in the recess and at least directly below the insulator, an insulating layer positioned above the first semiconductor layer and the insulator, and a gate positioned on the insulating layer. The first semiconductor layer includes a source region and a drain region of the first conductivity type, a first impurity region positioned around the source region, and a second impurity region that is in contact with a bottom surface of the second semiconductor layer and that is of the first conductivity type. A diffusion coefficient for impurities in the second semiconductor layer is higher than a diffusion coefficient for impurities in the first semiconductor layer.
A controller circuit for a step-up/step-down DC/DC converter generating an output voltage according to an input voltage includes: step-down and step-up switch circuits respectively including high-side and low-side transistors and respectively receiving the input voltage and outputting the output voltage; ramp voltage and middle voltage generation circuits respectively generating a ramp voltage based on a first clock signal and a middle voltage of the ramp voltage; an error amplifier circuit generating an error signal from an error between a feedback voltage of the output voltage and a reference voltage; an inverting amplifier generating an inverted signal by inverting the error signal based on the middle voltage; first and second comparators generating first and second PWM signals by respectively comparing the ramp voltage with the error and inverted signals; and a logic circuit generating a control signal for the high-side and low-side transistors based on the first and second PWM signals.
H02M 3/157 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation avec commande numérique
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
69.
DETECTION DEVICE, SEMICONDUCTOR CHIP, AND DETECTION METHOD
A detection device includes: a detector configured to detect a resistance value of at least one wiring arranged along an outer edge of a semiconductor chip, wherein when the at least one wiring has no defect, the detector detects a first resistance value required for the at least one wiring having no defect, and when the at least one wiring has a defect, the detector detects a second resistance value larger than the first resistance value.
A semiconductor device includes: an insulating layer formed on a semiconductor substrate; a first resistor embedded in the insulating layer; a second resistor embedded in the insulating layer and connected in series with the first resistor; and a first capacitor comprising: a first upper electrode formed on the insulating layer and electrically connected to one end of the first resistor; and a first lower electrode formed in the insulating layer and electrically connected to one end of the second resistor, wherein the first lower electrode is electrically connected to the second resistor and is electrically connected to a reference electrode formed on the insulating layer.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
H10D 1/68 - Condensateurs n’ayant pas de barrières de potentiel
The semiconductor device includes: an insulating layer provided on a semiconductor substrate; a first resistor embedded in the insulating layer and electrically connected to a node on a first potential side; a second resistor embedded in the insulating layer; a third resistor embedded in the insulating layer; and a reference electrode electrically connected to a node on a second potential side of the third resistor. An absolute value of the first potential is greater than an absolute value of the second potential. The first resistor, the second resistor, and the third resistor are connected in series. The first resistor is formed by connecting N resistors in parallel, the second resistor is formed by connecting M resistors in parallel, and the third resistor is formed by connecting L resistors in parallel, with N
An electrode terminal of a semiconductor element includes a terminal portion and a pedestal portion. The terminal portion includes a terminal portion rear surface and a terminal portion side surface. The terminal portion side surface intersects with the terminal portion rear surface. The pedestal portion protrudes outwardly from a part of the terminal portion side surface of the terminal portion. The pedestal portion includes a pedestal portion rear surface, a pedestal portion side surface, and a curved surface. The pedestal portion rear surface is in contact with an insulating layer. The pedestal portion side surface intersects with the pedestal portion rear surface and is located outside the terminal portion side surface. The curved surface is disposed between the pedestal portion rear surface and the pedestal portion side surface.
A signal processing device is configured to output, via a transformer to a sonic wave transmission device, a transmission signal for transmitting a sonic wave. The signal processing device includes a resonance frequency measuring portion. The resonance frequency measuring portion is configured to find the resonance frequency of the sonic wave transmission device from at least one of a first frequency at which, while the frequency of the transmission signal is down-chirped, the amplitude of the secondary voltage of the transformer is at its minimum and a second frequency at which, while the frequency of the transmission signal is up-chirped, the amplitude of the secondary voltage of the transformer is at its minimum.
A driving circuit includes a voltage sense circuit that senses, in the on-period of a switching device as a driving target, a node voltage corresponding to the on-resistance of the switching device and a logic circuit that externally transmits a voltage sense signal (e.g., duty signal) corresponding to the sense value of the node voltage.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
H03K 17/0812 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande par des dispositions prises dans le circuit de commande
A semiconductor device includes a semiconductor chip having a first principal surface and a second principal surface opposite to the first principal surface, and a trench-type IGBT structure formed on the first principal surface of the semiconductor chip, wherein the IGBT structure includes a trench formed in the first principal surface of the semiconductor chip and extending in a plurality of directions, an insulating film formed on a side surface of the trench, an embedded conductor embedded inside the trench through the insulating film, and an intersection portion formed by the trenches extending in the plurality of directions, and a curvature index of a corner portion of the intersection portion is 1.5 μm or more.
A semiconductor device includes: a supporting conductor including a first obverse surface facing a first side in a thickness direction; a plurality of semiconductor elements including four or more semiconductor elements disposed on the first obverse surface; and a sealing resin covering the plurality of semiconductor elements and the supporting conductor. The plurality of semiconductor elements are disposed side by side in a first direction perpendicular to the thickness direction, and include a first semiconductor element and a second semiconductor element that are located near a center in the first direction. A first distance, which is a distance between a center of the first semiconductor element and a center of the second semiconductor element, is greater than a second distance, which is a distance between the center of one of the first semiconductor element and the second semiconductor element and a center of one of a third semiconductor element and a fourth semiconductor element that is adjacent to the one of the first semiconductor element and the second semiconductor element in the first direction.
An under voltage detection circuit compares a potential difference between a bootstrap line and an output line with a threshold voltage. A first resistor comprises a first end connected to the bootstrap line. A Zener diode comprises a cathode connected to the bootstrap line and has a parasitic capacitance between the cathode and a substrate. A first transistor comprises a source connected to the output line, and a drain and a gate connected to a second end of the first resistor. A comparator compares a voltage drop across a second resistor with a threshold voltage and generates an under voltage detection signal.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
H02P 23/00 - Dispositions ou procédés pour la commande de moteurs à courant alternatif caractérisés par un procédé de commande autre que la commande par vecteur
An under voltage detection circuit compares a potential difference between a bootstrap line and an output line with a threshold voltage. A voltage line generates a voltage lower by a predetermined voltage than the bootstrap line. A current mirror circuit is connected to the bootstrap line. A first resistor and a MOS diode are connected in series between an input node of the current mirror circuit and the output line. A second resistor is connected between an output node of the current mirror circuit and the voltage line. A comparator compares a voltage drop across the second resistor with a threshold voltage.
A semiconductor module includes: a first transistor and a second transistor connected in parallel to each other, wherein a parallel resonant circuit of the first transistor and the second transistor has a first pole frequency (ωp1), a second pole frequency (ωp2) higher than the first pole frequency (ωp1), and a zero frequency (ωz), and wherein an absolute value of a phase lag between the second pole frequency (ωp2) and the zero frequency (ωz) is set to be smaller than 180 degrees.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03K 17/56 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs
A semiconductor module includes a conductive substrate, a semiconductor element, a control terminal, and a sealing resin. The conductive substrate has an obverse surface and a reverse surface that are spaced apart from each other in a thickness direction. The semiconductor element is electrically bonded to the obverse surface and has a switching function. The control terminal is configured to control the semiconductor element. The sealing resin has a resin obverse surface and a resin reverse surface, and covers the conductive substrate, the semiconductor element, and a part of the control terminal. The control terminal protrudes from the resin obverse surface, and extends along the thickness direction.
In a power supply device, the state of an output stage circuit is controlled based on a feedback voltage (Vfb) corresponding to an output voltage and a reference voltage (Vref) generated by a first voltage generation circuit (11), thereby stabilizing the output voltage at a target voltage. An abnormality of the output voltage is monitored based on the feedback voltage and an output monitoring voltage (V_H, V_L) generated by a second voltage generation circuit (12). Abnormalities of the first and second voltage generation circuits are detected distinctively based on a first determination voltage (V1a, V1b) generated by the first voltage generation circuit, a second determination voltage (V2a, V2b) generated by the second voltage generation circuit, and a third determination voltage (V3a, V3b, V3c, V3d) generated by a third voltage generation circuit.
H02M 1/00 - Détails d'appareils pour transformation
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
82.
POWER SUPPLY CONTROL DEVICE AND SWITCHING POWER SUPPLY APPARATUS
Provided is a power supply control device for use in a switching power supply apparatus configured to generate a plurality of switch voltages having a rectangular wave shape at switch terminals of a plurality of channels by individually switching an input voltage by using output stage circuits of the plurality of channels, the output stage circuits each including an output transistor, and generate an output voltage by rectifying and smoothing the plurality of switch voltages, the power supply control device including an error voltage generating circuit, a ramp voltage generating circuit, a comparing circuit, and a switching control circuit.
H02M 3/155 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs
H02M 1/14 - Dispositions de réduction des ondulations d'une entrée ou d'une sortie en courant continu
83.
Clock Signal Generation Circuit, Semiconductor Device, Semiconductor System, and Power Supply Control Device
A clock signal generation circuit comprises a counter that updates a count value in synchronization with an internal clock signal; a timing setting circuit that sets a sampling timing based on a signal asynchronous to the internal clock signal; a holding circuit that acquires and holds the count value at the sampling timing as a parameter value; a signal generation circuit that generates a modulation signal having characteristics corresponding to the parameter value held in the holding circuit; and an oscillator that generates a target clock signal having a frequency corresponding to the modulation signal.
A signal transmitter includes: a transmission circuit; a reception circuit; and a plurality of insulating elements configured to transmit a plurality of signals, respectively, from the transmission circuit to the reception circuit while insulating between the transmission circuit and the reception circuit, wherein the transmission circuit includes: an oscillator circuit configured to generate a plurality of clock signals having different phases; and a plurality of driving circuits configured to drive the plurality of insulating elements in synchronization with the plurality of clock signals, respectively.
A power module apparatus includes a power module having a package configured to seal a perimeter of a semiconductor device, and a heat radiator bonded to one surface of the package; a cooling device having a coolant passage through which coolant water flows, in which the heat radiator is attached to an opening provided on a way of the coolant passage, wherein the heat radiator of the power module is attached to the opening of the cooling device so that a height (ha) and a height (hb) are substantially identical to each other. The power module in which the heat radiator is attached to the opening formed at the upper surface portion of the cooling device can also be efficiently cooled, and thereby it becomes possible to reduce degradation due to overheating.
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
B60K 1/00 - Agencement ou montage des ensembles de propulsion électriques
B60K 6/22 - Agencement ou montage de plusieurs moteurs primaires différents pour une propulsion réciproque ou commune, p. ex. systèmes de propulsion hybrides comportant des moteurs électriques et des moteurs à combustion interne les moteurs primaires étant constitués de moteurs électriques et de moteurs à combustion interne, p. ex. des VEH caractérisés par des appareils, des organes ou des moyens spécialement adaptés aux VEH
B60K 11/02 - Dispositions des ensembles de propulsion relatives au refroidissement avec liquide de refroidissement
F28F 3/04 - Éléments ou leurs ensembles avec moyens pour augmenter la surface de transfert de chaleur, p. ex. avec des ailettes, avec des évidements, avec des ondulations les moyens faisant partie intégrante de l'élément
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/10 - ConteneursScellements caractérisés par le matériau ou par la disposition des scellements entre les parties, p. ex. entre le couvercle et la base ou entre les connexions et les parois du conteneur
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H02M 1/32 - Moyens pour protéger les convertisseurs autrement que par mise hors circuit automatique
H02M 7/00 - Transformation d'une puissance d'entrée en courant alternatif en une puissance de sortie en courant continuTransformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif
H02M 7/5387 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant alternatif sans possibilité de réversibilité par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs, p. ex. onduleurs à impulsions à un seul commutateur dans une configuration en pont
H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H10D 62/832 - Corps semi-conducteurs, ou régions de ceux-ci, de dispositifs ayant des barrières de potentiel caractérisés par les matériaux étant des matériaux du groupe IV, p. ex. Si dopé B ou Ge non dopé étant des matériaux du groupe IV comprenant deux éléments ou plus, p. ex. SiGe
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
86.
METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND SEMICONDUCTOR MODULE
This method for manufacturing a semiconductor module comprises: a first step for bonding a plurality of base materials to a heat dissipation member; a second step for individually bonding a plurality of first semiconductor elements to the plurality of base materials; and a third step for forming a sealing resin which covers the plurality of base materials and the plurality of first semiconductor elements. The third step is performed after the first step and the second step are completed. In the third step, the sealing resin is integrally formed.
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 23/28 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
This semiconductor device comprises a base material that includes a first conductive layer, a first semiconductor element that is joined to one side of the first conductive layer in a first direction, a first power terminal that is electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin that covers the first semiconductor element. When viewed in the first direction, the first power terminal is surrounded by the sealing resin. The sealing resin includes a first surface facing the one side in the first direction. The first power terminal includes a first engagement part exposed from the first surface.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/29 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par le matériau
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
88.
CONCENTRATION DETECTION DEVICE AND CONCENTRATION DETECTION METHOD
A concentration detection device according to the present invention comprises a hydrogen sensor, a sensor module, and a microcomputer. The hydrogen sensor detects the concentration of hydrogen contained in a gas. The sensor module detects a correction parameter that is at least one of the flow velocity of the gas, the pressure of the gas, the temperature of the gas, and a methane concentration. The microcomputer corrects the hydrogen concentration using the correction parameter and outputs the corrected hydrogen concentration.
G01N 27/18 - Recherche ou analyse des matériaux par l'emploi de moyens électriques, électrochimiques ou magnétiques en recherchant l'impédance en recherchant la résistance d'un corps chauffé électriquement dépendant de variations de température produite par des variations de la conductivité thermique d'un matériau de l'espace environnant à tester
Provided is a semiconductor device including a drive voltage generation circuit configured to generate a drive voltage on the basis of a first external resistor externally attached to a first external terminal, a first signal generation circuit configured to generate a first clock signal for pulse driving based on the drive voltage and a second external resistor externally attached to a second external terminal, a second signal generation circuit configured to generate a second clock signal for pulse driving based on an internal resistor and the drive voltage, a count circuit configured to generate a count signal according to a count value obtained by counting pulses of the first clock signal in a determination section while counting the determination section according to pulses of the second clock signal, and a multifunction output circuit configured to output an output signal of an output value that differs depending on the count signal.
H02M 1/088 - Circuits spécialement adaptés à la production d'une tension de commande pour les dispositifs à semi-conducteurs incorporés dans des convertisseurs statiques pour la commande simultanée de dispositifs à semi-conducteurs connectés en série ou en parallèle
H02M 3/158 - Transformation d'une puissance d'entrée en courant continu en une puissance de sortie en courant continu sans transformation intermédiaire en courant alternatif par convertisseurs statiques utilisant des tubes à décharge avec électrode de commande ou des dispositifs à semi-conducteurs avec électrode de commande utilisant des dispositifs du type triode ou transistor exigeant l'application continue d'un signal de commande utilisant uniquement des dispositifs à semi-conducteurs avec commande automatique de la tension ou du courant de sortie, p. ex. régulateurs à commutation comprenant plusieurs dispositifs à semi-conducteurs comme dispositifs de commande finale pour une charge unique
90.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a terminal having a connection surface facing one side in a first direction; a semiconductor element electrically connected to the connection surface; and a sealing resin covering a portion of the terminal and the semiconductor element, wherein the terminal is located on the other side in the first direction with respect to the connection surface and has a first surface recessed into the terminal and a second surface connected to the connection surface and the first surface, wherein the first surface overlaps the connection surface when viewed in the first direction, and wherein the second surface is convex and is in contact with the sealing resin.
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
A semiconductor device includes at least one terminal, and the terminal includes a cylindrical holder having electrical conductivity and a metal pin inserted in the holder. The semiconductor device further includes a terminal support supporting the holder, and a sealing resin covering a part of the holder and covering the terminal support. The sealing resin includes a resin obverse surface facing a first side in a thickness direction. The holder includes a first surface located at one end on the first side in the thickness direction and a first outer side surface extending in the thickness direction. The first surface is located at a position different from the resin obverse surface in the thickness direction. The first outer side surface is in contact with the sealing resin. The metal pin protrudes beyond the resin obverse surface toward the first side in the thickness direction.
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/07 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans la sous-classe
92.
NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR DEVICE
This nitride semiconductor device comprises: a conductive substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface; a high resistance layer provided on the first substrate surface and having a resistance higher than that of the conductive substrate; a nitride semiconductor layer provided on the high resistance layer; a source electrode as a first electrode formed on the nitride semiconductor layer; and a via electrically connected to the source electrode and penetrating through the nitride semiconductor layer and the high resistance layer and in contact with the conductive substrate. The high resistance layer is composed of GaN and is in contact with the first substrate surface.
H10D 30/87 - Transistors FET avec électrodes de grille Schottky, p. ex. transistors FET à métal semiconducteur [MESFET]
H10D 30/47 - Transistors FET ayant des canaux à gaz de porteurs de charge de dimension nulle [0D], à une dimension [1D] ou à deux dimensions [2D] ayant des canaux à gaz de porteurs de charge à deux dimensions, p. ex. transistors FET à nanoruban ou transistors à haute mobilité électronique [HEMT]
H10D 30/83 - Transistors FET avec des électrodes de grille à jonction PN
H10D 62/10 - Formes, dimensions relatives ou dispositions des régions des corps semi-conducteursFormes des corps semi-conducteurs
Provided is an oscillation circuit including a ramp voltage generation circuit generating a ramp voltage according to a first reference voltage, and a comparator generating a pulse-driven clock signal according to the first reference voltage and the ramp voltage. The ramp voltage generation circuit includes a first signal generation circuit generating a first signal that rises or falls according to a duty ratio of a first pulse width modulation signal generated according to a pulse period of the clock signal, and a second signal generation circuit generating a second signal that rises or falls in a direction opposite to the first signal according to the duty ratio of the first pulse width modulation signal. The ramp voltage generation circuit generates the ramp voltage according to the lowest voltage among a second reference voltage based on the first reference voltage, the first signal, and the second signal.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
H03K 3/017 - Réglage de la largeur ou du rapport durée période des impulsions
94.
SEMICONDUCTOR DEVICE AND SIGNAL TRANSMISSION DEVICE
An insulating chip includes a first via and a second via provided within an insulating body. The insulating body includes an insulating layer in which the first via is embedded, and an insulating layer in which the second via is embedded. Both insulating layers include a thin insulating layer made of a material having a smaller coefficient of thermal expansion than each of the first via and the second via, and a thick insulating layer laminated on the thin insulating layer and made of a material having a smaller coefficient of thermal expansion than the thin insulating layer. A lower surface of the second via includes an extending portion that protrudes beyond an upper surface of the first via in plan view. An end portion of the extending portion is in contact with the thick insulating layer of the insulating layer.
An insulating chip includes a first coil and a second coil that faces the first coil in the Z direction. The second coil includes a second upper surface, a second lower surface on the opposite side of the second upper surface, a second side surface provided between the second upper surface and the second lower surface in the Z direction, and a second corner portion between the second side surface and the second upper surface. The second corner portion includes a second recess having a second curved surface so as to be convex inward toward the second coil.
A semiconductor device includes a source region extending along a Y axis direction, a first drain region, a first gate electrode disposed between the source region and the first drain region, a second drain region positioned across the source region from the first drain region, and extending along the Y axis direction, and a second gate electrode disposed between the source region and the second drain region. The first gate electrode extends in a meander along the Y axis direction, and the second gate electrode extends in a meander along the Y axis direction. In the source region disposed between the first gate electrode and the second gate electrode, a conductive region having a conductivity type opposite to the source region is formed, and the source region and the conductive region are electrically connected to each other.
A magnetic sensor chip includes a detection coil arranged with the X-direction as its axial direction, a detection terminal used to detect an induced voltage generated by the detection coil, a test coil disposed at a position spaced apart from the detection coil, and a test terminal used to supply a test current to the test coil. The test coil is disposed at a position where an induced voltage is generated in the detection coil when the test current flows through the test coil.
G01R 15/18 - Adaptations fournissant une isolation en tension ou en courant, p. ex. adaptations pour les réseaux à haute tension ou à courant fort utilisant des dispositifs inductifs, p. ex. des transformateurs
G01R 35/00 - Test ou étalonnage des appareils couverts par les autres groupes de la présente sous-classe
A semiconductor device includes a semiconductor layer having first and second principal surfaces, an insulated gate bipolar transistor (IGBT) region formed in the semiconductor layer, and a diode region formed adjacent to the IGBT region in a first direction. A plurality of gate trenches are arranged in the IGBT region and extend in a second direction intersecting the first direction. Each trench includes a gate conductive layer embedded through a gate insulating layer, and unit cells are defined between adjacent trenches. An emitter region is formed on the first principal surface of each unit cell. The emitter region of a unit cell located closer to the diode region has a smaller area than the emitter region of a unit cell located farther from the diode region.
H10D 84/00 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si
A semiconductor device includes a semiconductor layer, an insulation gate-type first transistor which is formed in the semiconductor layer, an insulation gate-type second transistor which is formed in the semiconductor layer, and a control wiring which is formed on the semiconductor layer such as to be electrically connected to the first transistor and the second transistor, and transmits control signals that control the first transistor and the second transistor to be in ON states in a normal operation and that control the first transistor to be in an OFF state and the second transistor to be in an ON state in an active clamp operation.
H10D 30/66 - Transistors FET DMOS verticaux [VDMOS]
H01L 21/76 - Réalisation de régions isolantes entre les composants
H10D 12/00 - Dispositifs bipolaires contrôlés par effet de champ, p. ex. transistors bipolaires à grille isolée [IGBT]
H10D 30/65 - Transistors FET DMOS latéraux [LDMOS]
H10D 30/69 - Transistors IGFET ayant des isolateurs de grille à piégeage de charges, p. ex. transistors MNOS
H10D 62/13 - Régions semi-conductrices connectées à des électrodes transportant le courant à redresser, amplifier ou commuter, p. ex. régions de source ou de drain
H10D 62/17 - Régions semi-conductrices connectées à des électrodes ne transportant pas de courant à redresser, amplifier ou commuter, p. ex. régions de canal
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
A transconductance amplifier that generates an output voltage by amplifying a difference between an input voltage and a reference voltage, includes: a differential amplifier circuit including an input differential pair configured to receive the input voltage and the reference voltage and operate according to a tail current, and an output circuit provided as an active load of the input differential pair to generate the output voltage; and a current control circuit configured to control the tail current, wherein the current control circuit is configured to increase the tail current when a current supply condition is satisfied, and the current supply condition is that the input voltage falls below a first threshold voltage which is equal to or lower than the reference voltage, or that the input voltage exceeds a second threshold voltage which is equal to or higher than the reference voltage.
