A switching power supply device includes a first switch, a second switch, a current sensing portion configured to sense current flowing in the second switch, and a controller configured to control the first and second switches in accordance with the current sensed by the current sensing portion. The controller includes an accumulating portion configured to accumulate information of the current sensed by the current sensing portion during a predetermined period of time while the first switch is in the off state, and reflecting portion configured to start the transmission of the current information accumulated by the accumulating portion before the first switch is changed from the off state to the on state so as to reflect the current information accumulated by the accumulating portion on the slope voltage, and controls the first and second switches in accordance with the slope voltage.
H02H 7/12 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for convertersEmergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for rectifiers for static converters or rectifiers
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
2.
SEMICONDUCTOR DEVICE, AND PACKAGE OF SEMICONDUCTOR DEVICE
This semiconductor device is configured so as to improve bonding strength to a wiring board. The semiconductor device includes a first lead, a semiconductor element, and a sealing resin. The semiconductor element is electrically connected to the first lead. The sealing resin covers a part of the first lead and the semiconductor element. The first lead has a first outer part that protrudes from the sealing resin. The first outer part has a first mounting surface that faces one side in a first direction. The first outer part is provided with a first opening that penetrates through the first outer part from the first mounting surface.
A micro-electromechanical systems (MEMS) Z-axis accelerometer can comprise a substrate, a sensor configured to measure an acceleration along an axis that extends in a direction perpendicular to a plane of the substrate, and a spring axis configured to deform axially in response to the acceleration. The sensor can include a comb finger arrangement in which a comb finger overlap area is parallel with the spring axis. Fingers of the comb finger arrangement can extend in a non-sensing direction of lowest restoring force.
A first integrated circuit and a second integrated circuit are coupled via a single-line communication line so as to form a circuit system. Multiple low times are defined in a protocol corresponding to multiple commands. The first integrated circuit fixes the electric potential of the communication line to a low level during the low time that corresponds to a command to be transmitted, so as to allow the command to be transmitted to the second integrated circuit.
H03L 7/00 - Automatic control of frequency or phaseSynchronisation
H03K 17/56 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices
The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; and an interlayer insulating layer formed in the first separation trench.
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
6.
COOLER AND COOLING STRUCTURE FOR SEMICONDUCTOR DEVICE
A cooler includes: a housing that includes an opening, an internal space, and a bottom; and a partition wall that rises in a first direction from the bottom and that is accommodated in the internal space. The housing includes an inlet channel and an outlet channel that are connected to the internal space. The internal space includes a first reservoir and a second reservoir that are partitioned by the partition wall. The first reservoir is connected to the inlet channel. The second reservoir is connected to the outlet channel. The partition wall includes an overflow section that overlaps with the opening as viewed in the first direction and is farthest from the bottom. The overflow section is located between the bottom and the opening.
H01L 23/46 - Arrangements for cooling, heating, ventilating or temperature compensation involving the transfer of heat by flowing fluids
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.
H01L 21/67 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
H01L 23/16 - Fillings or auxiliary members in containers, e.g. centering rings
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 89/00 - Aspects of integrated devices not covered by groups
This semiconductor module includes a substrate, an encapsulating resin, a filling part, and a metal layer. The substrate has a front surface and a back surface. The back surface is located on the reverse side from the front surface. The encapsulating resin is provided on the front surface. The metal layer covers the filling part in a plan view of the front surface. The substrate has a recess extending from the front surface to the back surface. The filling part is connected to the recess.
A semiconductor device according to the present invention comprises at least one lead, at least one semiconductor element that is provided on one side in the thickness direction of the at least one lead, a plurality of wires that are each electrically connected to at least one of the at least one lead and the at least one semiconductor element, and a sealing resin that covers the at least one semiconductor element, the plurality of wires, and at least a portion of the at least one lead. The plurality of wires include a first wire and a second wire. The second wire is curved so as to protrude toward the first wire as seen in the thickness direction. The second wire straddles the first wire as seen in the thickness direction and is separated from the first wire in the thickness direction.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
10.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device comprises a plurality of terminals, a semiconductor chip mounted on the plurality of terminals, and a sealing resin for sealing the plurality of terminals and the semiconductor chip. Each of the plurality of terminals includes: a rear surface, at least a part of which is exposed from the sealing resin; a front surface on which the semiconductor chip is mounted; a tip surface which is provided within the sealing resin and which is an end surface in a first direction orthogonal to the Z direction; and a projecting portion which is positioned at an intermediate portion in the Z direction on the tip surface.
This semiconductor device comprises: a plurality of terminals that include a terminal obverse surface and a terminal reverse surface facing the opposite side from the terminal obverse surface; a semiconductor chip that is mounted on the plurality of terminals; and an encapsulating resin for encapsulating the plurality of terminals and the semiconductor chip. The plurality of terminals include: a terminal portion that includes a terminal portion reverse surface, which is exposed from the encapsulating resin on the terminal reverse surface; a mounting portion that extends from the terminal portion in a first direction orthogonal to a Z direction, which is the thickness direction of the terminal, and has the semiconductor chip mounted thereon; a groove portion that is provided at least in the mounting portion and extends in the first direction; and wall portions that are positioned at both ends in a second direction orthogonal to both the Z direction and the first direction by the groove portion and extend in the first direction.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
12.
SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, LED DRIVE DEVICE, DC/DC CONVERTER, AND VEHICLE
A semiconductor device for controlling a driver circuit configured to drive an electronic device includes: a processing circuit configured to control the driver circuit according to a device address setting signal from outside and a control signal from outside; and an autonomous processing circuit provided independently of the processing circuit and configured to control the driver circuit under a preset condition, wherein when the device address setting signal falls within a predetermined condition, the processing circuit is enabled and the autonomous processing circuit is disabled, and when the device address setting signal deviates from the predetermined condition, the autonomous processing circuit is enabled and the processing circuit is disabled.
This semiconductor device includes: a first impurity region, a second impurity region, and a third impurity region, which are formed on a chip; a trench which is formed in the chip; a trench insulating film which is formed on the inner surface of the trench; a conductive embedded body which is embedded in the trench; and an electric field attenuated layer which is formed on a bottom part of the trench. The electric field attenuated layer includes: a first layer which is formed away from the bottom part of the trench toward a second main surface side, and has a first impurity concentration; and a second layer which is formed between the first layer and the bottom part of the trench, and has a second impurity concentration that is higher than the first impurity concentration.
This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed on a surface layer part of the main surface; a device structure having a source structure and formed in the semiconductor region in a part inside the main surface; a peripheral source electrode part having a first outer edge, disposed on a peripheral edge part of the main surface, and electrically connected to the source structure; and a termination region of a second conductivity type having a second outer edge positioned closer to the peripheral edge side of the main surface than the first outer edge and formed in the surface layer part of the semiconductor region at the peripheral edge part of the main surface, the termination region being electrically connected to the peripheral source electrode part. A first distance between the first outer edge of the peripheral source electrode part and the second outer edge of the terminal region is 10 μm or more.
The wafer structure includes a wafer which has a first surface on one side and a second surface on the other side, a first electrode which covers the first surface, a second electrode which covers an inward portion of the second surface such as to expose a peripheral edge portion of the second surface, and a protective tape which has characteristics that an adhesion to the peripheral edge portion of the second surface is higher than an adhesion to the second electrode and which is adhered to the peripheral edge portion of the second surface and the second electrode.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
A mounting structure includes: a substrate; a conductive portion (a first conductive portion and a second conductive portion); a resistor arranged on a path through which a current flows in the conductive portion; and a detection wiring portion (a first detection wiring and a second detection wiring) electrically connected to the resistor. The first conductive portion includes a first pad portion arranged on a first side in a first direction. The second conductive portion includes a second pad portion offset from the first pad portion to a second side in the first direction. The mounting structure further includes a first conductive bonding member for bonding a first pad obverse surface and the resistor (the first portion), and a second conductive bonding member for bonding a second pad obverse surface and the resistor (the second portion). A first wiring obverse surface (a second wiring obverse surface) is offset to a second side in a thickness direction relative to the first pad obverse surface (the second pad obverse surface).
This resistance circuit 71 includes pads P11 and P12, unit resistance elements R(1)-R(5) having a unit resistance value r, wiring L11 conductively connecting the pad P11 and the unit resistance element R(1), and wiring L12 conductively connecting the pad P12 and the unit resistance element R(5). The unit resistance elements R(1)-R(5) are each formed in a rectangular shape having a direction x as a lateral direction and a direction y as a longitudinal direction in plan view, and are arranged so as to be adjacent to each other along the direction x. The unit resistance elements R(1)-R(4) are connected so as to have a combined resistance value equal to the unit resistance value r between a contact point S and a contact point E. The contact point S is formed at the upper end in the longitudinal direction of the unit resistance element R(1). The contact point E is formed at the lower end in the longitudinal direction of the unit resistance element R(5). The wiring L11 is extended out in the direction x from the contact point S. The wiring L12 is extended out in the direction y from the contact point E.
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
This semiconductor device includes: a chip that has a main surface; a semiconductor region of a first conductivity type that is formed in a surface layer section of the main surface; a trench-type gate structure that is formed in the main surface and is located within the semiconductor region; a rectification region of the first conductivity type that is formed in the surface layer section of the main surface, neighboring the gate structure; and a main surface electrode that is electrically isolated from the gate structure on the main surface, and forms a Schottky junction with the rectification region.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
This semiconductor device includes: a chip having a major surface; a trench-electrode type capacitor structure which is formed on the major surface and to which a first potential is applied; a dielectric film which covers the capacitor structure on the major surface; and a pad electrode disposed on the dielectric film so as to form a capacitive coupling with the capacitor structure via the dielectric film and to which a second potential different from the first potential is applied.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 1/68 - Capacitors having no potential barriers
This semiconductor device includes: a chip having a main surface; a pad region provided on the main surface; a first electrode that is disposed on the main surface of the pad region, a first potential being applied to the first electrode; a side wall dielectric film that covers the side wall of the first electrode in the pad region; and a second electrode that is disposed on the main surface so as to form a capacitive coupling with the first electrode via the side wall dielectric film in the pad region, a second potential different from the first potential being applied to the second electrode.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 1/68 - Capacitors having no potential barriers
This semiconductor device comprises: a semiconductor substrate 1; an insulation layer 2 provided on the semiconductor substrate 1; a resistor R embedded in the insulation layer 2 and composed of a plurality of resistance layers electrically connected together; a first electrode E1 electrically connected to a first end part of the resistor R; a second electrode E2 electrically connected to a second end part of the resistor R; and a plurality of first dummy wires 5 arranged around the first electrode E1 and respectively capacitively coupled to the plurality of resistance layers in the resistor R.
This semiconductor device is provided with: a first lead that includes a first pad part; a first semiconductor element; a first wire; and a sealing resin. The first pad part has a first mounting surface that faces in a first direction. The first semiconductor element is bonded to the first mounting surface. The first wire has a first bonding part and a second bonding part. The first wire is provided with a first protrusion that covers the second bonding part and is covered by the sealing resin. The first pad part is provided with a first hole which is located closer to the second bonding part than to the first bonding part, and which penetrates through the first pad part in the first direction from the first mounting surface. A part of the sealing resin is housed in the first hole.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor device includes: a chip which has a main surface; an active region which is provided in the main surface; a pad region which is provided outside the active region in the main surface; an insulated gate typed transistor structure which is formed on the main surface of the active region; a trench electrode typed capacitor structure which is formed on the main surface of the pad region and forms a capacitive coupling with the chip; and a pad electrode which is disposed on the main surface of the pad region and is electrically connected to the capacitor structure.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 1/68 - Capacitors having no potential barriers
This semiconductor device includes: a chip having a main surface; an active region provided on the main surface; a pad region provided outside the active region on the main surface; an insulated gate transistor structure formed on the main surface of the active region; a trench-electrode-type capacitor structure formed on the main surface of the pad region, the trench-electrode-type capacitor structure forming a capacitive coupling with the chip; and a pad electrode disposed on the main surface of the pad region, the pad electrode being electrically connected to the capacitor structure.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 1/68 - Capacitors having no potential barriers
A semiconductor light emitting device comprises a current confinement layer and a semiconductor light emitting stack. The semiconductor light emitting stack is disposed on the current confinement layer and has a bottom surface in contact with the current confinement layer. The current confinement layer includes an insulating layer and a plurality of conductive portions. The plurality of conductive portions are disposed in the insulating layer in contact with the bottom surface. An area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less.
H01S 5/22 - Structure or shape of the semiconductor body to guide the optical wave having a ridge or a stripe structure
H01S 5/34 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
H01S 5/343 - Structure or shape of the active regionMaterials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser
A semiconductor light emitting device includes: a surface emitting laser element including an element front surface and configured to emit laser light from the element front surface; an element container including a bottom wall where the surface emitting laser element is arranged and a peripheral wall surrounding the surface emitting laser element when viewed from a direction perpendicular to the element front surface, the bottom wall and the peripheral wall constituting a containing space which contains the surface emitting laser element and is open on a same side as the element front surface; a diffusion layer covering the element front surface in the containing space and including a diffusion material; and a reflector covering at least one selected from the group of the bottom wall and the peripheral wall in the containing space and made of a resin material having a higher reflectivity than the diffusion layer.
H01S 5/02255 - Out-coupling of light using beam deflecting elements
H01S 5/02234 - Resin-filled housingsMaterial of the housingsFilling of the housings the housings being made of resin
H01S 5/183 - Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
27.
GATE DRIVER CIRCUIT, MOTOR DRIVE DEVICE USING SAME, AND ELECTRONIC DEVICE
A gate driver circuit for driving an N-type power transistor that constitutes a switching circuit, includes: a high-level line on which a voltage higher than a source of the power transistor is generated; a turn-on transistor configured to source a current to a gate of the power transistor; a turn-off transistor configured to sink a current from the gate of the power transistor; and a control circuit, wherein the turn-on transistor includes a plurality of transistors connected between the gate of the power transistor and the high-level line, and wherein the control circuit controls on/off states of the plurality of transistors so that when turning the power transistor on, the turn-on transistor has a first drive capability in a first period, a second drive capability lower than the first drive capability in a second period, and a third drive capability higher than the second drive capability in a third period.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
28.
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY DEVICE
A semiconductor integrated circuit device configured to be used as a part of a power supply device includes: an error amplifier configured to output an error voltage according to a difference between a feedback voltage, which is based on an output voltage of the power supply device, and a reference voltage; a first switching element and a second switching element that are connected in series; a first controller configured to control switching of the first switching element and the second switching element based on the error voltage; an output transistor; a second controller configured to linearly control the output transistor based on the error voltage; and a first terminal configured so that a connection node between the first switching element and the second switching element and an output terminal of the output transistor are connected to the first terminal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a semiconductor substrate having a first conductivity type; a gate electrode positioned on the semiconductor substrate; and a semiconductor part embedded in the semiconductor substrate and having the first conductivity type, in which the semiconductor substrate is provided with at least a part of a drift region being adjacent to the semiconductor part and having a second conductivity type, and a surface of the semiconductor part and a first portion included in a surface of the drift region are positioned higher than a second portion in a surface of the semiconductor substrate, the second portion being positioned below the gate electrode.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/308 - Chemical or electrical treatment, e.g. electrolytic etching using masks
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
A semiconductor device includes a lead frame, a semiconductor element mounted on the top surface of the bonding region, and a case covering part of the lead frame. The bottom surface of the bonding region is exposed to the outside of the case. The lead frame includes a thin extension extending from the bonding region and having a top surface which is flush with the top surface of the bonding region. The thin extension has a bottom surface which is offset from the bottom surface of the bonding region toward the top surface of the bonding region.
A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivity type that is formed in a surface layer portion of the well region, an impurity region of the second conductivity type that is formed in the surface layer portion of the well region and that is electrically connected to the drain region, and a gate structure that has a gate insulating film covering the channel region on the main surface and a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/08 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/36 - Semiconductor bodies characterised by the concentration or distribution of impurities
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
There is provided a semiconductor device including: a first substrate and a second substrate mounted in an overlapping manner, wherein the first substrate includes: plural conductive first pads that are arranged on a substrate surface of the first substrate at intervals; plural conductive second pads that are arranged on the substrate surface at intervals; and a conductive member, and the second substrate includes: plural conductive third pads; plural conductive fourth pads; a first measurement pad that is measures whether or not the third pad is conductive with the fourth pad; and a second measurement pad that is checks whether or not the third pad is conductive with the fourth pad.
A signal transmission device 200X comprises a transmission circuit 410, a reception circuit 420 configured to output a driving control signal Ga in accordance with a first internal signal S2 and a second internal signal S1; an insulated circuit 430; and a driving circuit 510. The transmission circuit 410 drives at least one of the first internal signal S2 and the second internal signal S1 at a specific period in accordance with an external signal ASC. The reception circuit 420 detects that the period of at least one of the first internal signal S2 and the second internal signal S1 is a specific period and outputs a driving suspension signal Gb which differs from the driving control signal Ga. The driving circuit 510 receives the driving suspension signal Gb, suspends driving of a driving target switch element SW, and puts an output node OUT of the driving circuit 510 in a high impedance state.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
34.
SIGNAL TRANSMISSION APPARATUS, ELECTRONIC DEVICE PROVIDED WITH SIGNAL TRANSMISSION APPARATUS, AND VEHICLE PROVIDED WITH ELECTRONIC DEVICE
A signal transmission apparatus 200X comprises: a transmission circuit 410x that outputs a first internal signal S1 and a second internal signal S2 according to an input signal IN; a reception circuit 420x; a first drive circuit 501; and a second drive circuit 502. The transmission circuit 410x drives at least one of the first internal signal S1 and the second internal signal S2 at a specific cycle different from the cycle of the input signal IN according to an external signal ASC. The reception circuit 420x, upon detecting that the cycle of at least one of the first internal signal S1 and the second internal signal S2 is the specific cycle, disables the first drive circuit 501, and enables the second drive circuit 502.
H03K 17/16 - Modifications for eliminating interference voltages or currents
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
35.
THERMAL PRINTING HEAD, THERMAL PRINTING SYSTEM, AND METHOD FOR MANUFACTURING THERMAL PRINTING HEAD
A thermal printing head according to the present invention comprises a substrate, a first insulating film, and a second insulating film. The substrate has a first main surface and a second main surface on the reverse surface from the first main surface. A protruding portion that protrudes toward the side opposite the second main surface is formed on the first main surface. A recessed section is formed in the surface of the protruding portion. The first insulating film is disposed on the first main surface so as to cover the protruding portion. The second insulating film is disposed on a surface with the first insulating film interposed therebetween. A through hole is formed in a portion of the first insulating film that faces the bottom surface of the recessed section with a gap therebetween.
A semiconductor device includes a semiconductor layer made of SiC. A transistor element having an impurity region is formed in a front surface portion of the semiconductor layer. A first contact wiring is formed on a back surface portion of the semiconductor layer, and defines one electrode electrically connected to the transistor element. The first contact wiring has a first wiring layer forming an ohmic contact with the semiconductor layer without a silicide contact and a second wiring layer formed on the first wiring layer and having a resistivity lower than that of the first wiring layer.
H01L 29/78 - Field-effect transistors with field effect produced by an insulated gate
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/10 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
H01L 29/16 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System in uncombined form
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
A semiconductor device includes an insulating layer, a conductive layer, a heat dissipation layer, a semiconductor element, and a bonding layer. The conductive layer includes an obverse surface facing away from the insulating layer in a first direction and is bonded to the insulating layer. The heat dissipation layer is located opposite to the conductive layer with respect to the insulating layer and bonded to the insulating layer. The semiconductor element is bonded to the obverse surface. The bonding layer bonds the obverse surface and the semiconductor element. The conductive layer is formed with a recess that is recessed from the obverse surface. The bonding layer includes a first portion located between the semiconductor element and the recess as viewed in the first direction, and the first portion covers the obverse surface.
H01L 23/10 - ContainersSeals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
38.
SEMICONDUCTOR DEVICE, ELECTRONIC APPARATUS AND VEHICLE
The present disclosure provides a semiconductor device. The semiconductor device includes: a semiconductor substrate; a well, formed in the semiconductor substrate; an output terminal, electrically connected to the semiconductor substrate; a ground terminal, configured to receive a ground voltage; a detection signal generating circuit, configured to generate a negative current detection signal when an output voltage present at the output terminal is detected to be less than the ground voltage; and a control circuit, configured to apply the ground voltage or the output voltage to the well in response to the negative current detection signal. The detection signal generating circuit includes: a comparator, configured to generate the negative current detection signal by comparing an output detection voltage with the ground voltage or the threshold voltage; a bias circuit, configured to switch between applying the output voltage or a bias voltage as the output detection voltage; and a clamp circuit.
A first current source is configured to generate a first current switchable between a first current amount and a second current amount less than the first current amount. A first current mirror circuit has an input node to which the first current source is connected and is configured to fold and supply the first current to a gate of a power transistor. An on-fixing switch is connected between the gate of the power transistor and a high-level line in which a high voltage equivalent to a high level of a gate voltage of the power transistor is generated. A control circuit is configured to control the on-fixing switch and the first current source.
A semiconductor light emitting device includes a surface-emitting laser element including an element front surface from which a laser beam is emitted, a light-transmissive first resin portion that encapsulates the surface-emitting laser element and includes a first resin surface, and a second resin portion that differs from the first resin portion and is at least partially formed on the first resin surface facing the element front surface in a direction orthogonal to the element front surface.
Provided is a semiconductor device that can suppress flash/burrs from forming on a lower surface of a die pad in a configuration in which the lower surface of the die pad is exposed from a sealing resin. The semiconductor device includes a lead frame, a semiconductor chip, and a sealing body. The lead frame includes a plate-shaped die pad and a lead. The die pad has one principal surface with a mounting region for mounting the semiconductor chip. The die pad includes a side portion and a frame-shaped protrusion on the side portion in top view. The protrusion overhangs in a lateral direction in an eave shape along the one principal surface. The semiconductor chip is mounted on the mounting region. The sealing body covers a side surface of the die pad while exposing the other principal surface of the die pad and sealing the semiconductor chip on the one principal surface of the die pad. The sealing body holds the die pad and the lead. The die pad has a through hole penetrating the protrusion in a direction intersecting with the one principal surface.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
42.
ABNORMAL VOLTAGE PROTECTION CIRCUIT, SIGNAL TRANSMISSION DEVICE COMPRISING ABNORMAL VOLTAGE PROTECTION CIRCUIT, ELECTRONIC EQUIPMENT COMPRISING SIGNAL TRANSMISSION DEVICE, AND VEHICLE COMPRISING ELECTRONIC EQUIPMENT
An abnormal voltage protection circuit 502 comprises voltage-current conversion circuits 507, 511, a current-voltage conversion circuit, and abnormal voltage detection circuits C3, C4. The voltage-current conversion circuits 507, 511 are configured to convert a monitored voltage VEE2 that is negative with respect to a reference voltage into current signals I1, I3. The current-voltage conversion circuit is configured to convert the current signals I1, I3 into voltage signals V7, V11 that are positive with respect to the reference voltage. The abnormal voltage detection circuits C3, C4 are configured to compare the voltage signals V7, V11 with threshold voltages V8, V12 to detect whether the monitored voltage VEE2 is equal to or higher than an upper-limit voltage V8, or equal to or lower than a lower-limit voltage V12.
H02H 9/04 - Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
H02H 11/00 - Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
H03K 17/08 - Modifications for protecting switching circuit against overcurrent or overvoltage
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
This electronic device comprises: a first member having a first main surface; an electronic element disposed on the first member; a connection member electrically connected to the electronic element; a second member having a second rear surface; and a sealing resin covering portions of the first member and the second member, as well as covering the electronic element and the connection member. The second member has a connection unit to which a terminal unit and the connection member are connected. The first main surface has a first flat section and a first convex section. The first convex section protrudes further to a first side in the thickness direction as compared to the first flat section. The second rear surface has a second flat section and a second convex section. The second convex section protrudes further to a second side in the thickness direction as compared to the second flat section.
Provided is a light-emitting element drive system including a leader light-emitting element drive device configured to be capable of driving light-emitting elements, and to include a DC/DC controller configured to be capable of controlling an output stage that can output an output voltage; and a plurality of follower light-emitting element drive devices configured to be capable of driving the light-emitting elements applied with the output voltage. The follower light-emitting element drive device includes at least one signal output terminal capable of outputting an operation information signal related to driving of the light-emitting elements. A plurality of the signal output terminals are connected to the same node, and the same node is connected to a signal input terminal of the leader light-emitting element drive device.
G09G 3/32 - Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
An electronic component of the present disclosure includes a first insulating layer that includes impurities, a thin film resistor formed on the first insulating layer, and a barrier layer that is formed in at least one part of a region between the thin film resistor and the first insulating layer and that obstructs transmission of the impurities. The first insulating layer includes a first surface and a concave portion that is hollowed with respect to the first surface, and the barrier layer may include a first part embedded in the concave portion and a second part formed along the first surface of the first insulating layer from an upper area of the first part.
H01C 1/034 - HousingEnclosingEmbeddingFilling the housing or enclosure the housing or enclosure being formed as coating or mould without outer sheath
H01C 1/032 - HousingEnclosingEmbeddingFilling the housing or enclosure plural layers surrounding the resistive element
H01C 7/00 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
A semiconductor device has an electrode structure that includes source electrodes, a gate electrode, and drain electrodes disposed on a semiconductor laminated structure and extending in parallel to each other and in a predetermined first direction and a wiring structure that includes source wirings, drain wirings, and gate wirings disposed on the electrode structure and extending in parallel to each other and in a second direction orthogonal to the first direction. The source wirings, the drain wirings, and the gate wirings are electrically connected to the source electrodes, the drain electrodes, and the gate electrode, respectively. The semiconductor device includes a conductive film disposed between the gate electrode and the drain wirings and being electrically connected to the source electrodes.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A photodiode comprises a substrate and a semiconductor stack. The substrate has a major surface. The semiconductor stack is disposed on the major surface. The semiconductor stack includes a buffer layer disposed on the major surface and a light absorption layer disposed on the buffer layer. The light absorption layer is formed of InxGa1-xAsyP1-y, where x and y are larger than 0 and smaller than 1. The buffer layer is formed of InzGa1-zAs, where z is larger than 0 and smaller than 1.
H01L 31/0304 - Inorganic materials including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 31/109 - Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN heterojunction type
In a power conversion circuit, a first end of an inductor is connected to a connection point between a first and a second switching elements. The first switching element is turned on and turned off by a gate driver. When the first switching element is turned on, a conduction current flows through the inductor and energy is stored. When the first switching element is turned off, due to release of the energy, a rectified current is generated through the second switching element. A loop of a gate current supplied by the gate driver is formed inside a loop of the rectified current. A magnetic flux that is in an opposite direction of a magnetic flux of the rectified current and is generated in the loop of the gate current generates an induced current in a direction opposite to the gate current, and charges accumulated in a gate are drawn out.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/5387 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
A nitride semiconductor device includes a first nitride semiconductor layer that constitutes an electron transit layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, is larger in bandgap than the first nitride semiconductor layer, and constitutes an electron supply layer, and a gate portion that is formed on the second nitride semiconductor layer. The gate portion includes a first semiconductor gate layer of a ridge shape that is disposed on the second nitride semiconductor layer and is constituted of a nitride semiconductor containing an acceptor type impurity, a second semiconductor gate layer that is formed on the first semiconductor gate layer and is constituted of a nitride semiconductor with a larger bandgap than the first semiconductor gate layer, and a gate electrode that is formed on the second semiconductor gate layer and is in Schottky junction with the second semiconductor gate layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A signal transmission apparatus 400 comprises: an insulation element 435 for performing signal transmission between a primary circuit system 400p and a secondary circuit system 400s while providing insulation therebetween; a self-diagnosis circuit 424 which is provided in the secondary circuit system 400s and performs self-diagnosis of the secondary circuit system 400s; a storage circuit 425 which is provided in the secondary circuit system 400s and in which memory access is permitted after completion of the self-diagnosis; and a transmission circuit 422 which is provided in the secondary circuit system 400s and outputs a transmission pulse signal S1 to the insulation element 435. The transmission circuit 422 generates one pulse or a group of a plurality of pulses in the transmission pulse signal S1 at the completion timing of each of the self-diagnosis and the memory access, and continues generating pulses at the period of a first time T1 in the transmission pulse signal S1 when an abnormality in the memory access is being detected.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
This semiconductor device includes: a base impurity region of a second conductivity type strip-shaped to be long in a first direction and formed in a surface layer part of a semiconductor region of a first conductivity type; a first impurity region formed in a surface layer part of the base impurity region; a gate electrode formed in a strip shape long in the first direction and opposed to a channel region of the base impurity region with a gate insulating film interposed; a Schottky region formed by a part of the semiconductor region and dividing the base impurity region into a plurality of unit cells along a second direction intersecting the first direction; and a main surface electrode making a Schottky junction to the Schottky region.
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
H01L 29/06 - Semiconductor bodies characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H01L 29/12 - Semiconductor bodies characterised by the materials of which they are formed
H01L 29/739 - Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field effect
This electronic device includes: a first connection object; a first connection member having a first connecting part connected, on a first side in a thickness direction, to the first connection object and a first loop part linked to the first connecting part, a first metal being used as a principal component of the first connection member; and a second connection member having a second connecting part connected to the first connecting part and a second loop part linked to the second connecting part and spaced apart from the first loop part, a second metal having a different thermoelectric power from that of the first metal being used as a principal component of the second connection member. The first connecting part has: a first peak-shaped section which has a protruding shape on the first side in the thickness direction and which extends in a first direction intersecting the thickness direction; and two first extending sections which extend on both sides in a direction intersecting the first direction.
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
G01K 7/20 - Measuring temperature based on the use of electric or magnetic elements directly sensitive to heat using resistive elements the element being a linear resistance, e.g. platinum resistance thermometer in a specially-adapted circuit, e.g. bridge circuit
A pull-up circuit contains a variable current source structured to supply current to a CC pin of a connector. A voltage detection circuit is structured to measure voltage at a CC1 pin and at a CC2 pin. A processor is structured to control the variable current source, and to detect moisture adhered to the CC1 pin and the CC2 pin, with reference to an output of the voltage detection circuit.
In a switching power supply apparatus configured to generate an output voltage from an input voltage, the output voltage is obtained by rectifying and smoothing a switch voltage obtained by alternately turned on and off first and second transistors connected in series to each other in accordance with the output voltage. A light-load support circuit includes a reverse current detection circuit that outputs a reverse current detection signal when a magnitude of the switch voltage is lower than an offset voltage during an on period of the second transistor, and an offset correction circuit. In response to the reverse current detection signal, a transition to a specific state occurs, in which the first and second transistors are off. The offset correction circuit corrects the offset voltage on the basis of the switch voltage at a specific timing of being switched to the specific state.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A linear power source circuit includes: an input unit to which an input signal is input and which outputs a first current signal; a current-voltage convertor which converts the first current signal into a first voltage signal; a voltage-current convertor configured to convert the first voltage signal into a second current signal; and an output unit configured to generate an output voltage signal from the second current signal by a first current mirror unit, a second current mirror unit, and a third current mirror unit, and configured to output the output voltage signal to an output terminal. The input unit and the current-voltage convertor constitute a current feedback type operational amplifier.
H03F 3/21 - Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
H03F 3/42 - Amplifiers with two or more amplifying elements having their DC paths in series with the load, the control electrode of each element being excited by at least part of the input signal, e.g. so-called totem-pole amplifiers
This semiconductor device includes a semiconductor element including a surface electrode formed on the element surface thereof. The element surface includes an active region in which power transistors are formed, and a control circuit region in which a control circuit for controlling the power transistors is formed. The active region is formed so as to surround the control circuit region from both sides in a second direction and one side in a first direction. The surface electrode is disposed on the active region at a position different from the control circuit region, and is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction thereof.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/822 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
H01L 27/04 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
H01L 27/06 - Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
58.
OVERCURRENT PROTECTION CIRCUIT, SEMICONDUCTOR DEVICE, ELECTRONIC EQUIPMENT, AND VEHICLE
An overcurrent protection circuit 34 comprises: a sense signal generation circuit 50 that generates a sense signal Vsns 1 in accordance with a monitored current IOUT; a count maximum value setting circuit 60 that sets a count maximum value Cmax in accordance with the results of comparing a second sense signal Vsns 2 corresponding to the sense signal Vsns 1 with thresholds Vth(0) to Vth(n); and a counter 70 that counts up a count value CNT when the monitored current IOUT is larger than a count start threshold Ith(0) (when Vsns 2 < Vth1(0) in this drawing), and forcibly stops the monitored current IOUT when the count value CNT reaches the count maximum value Cmax.
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
59.
MACRO MODEL, CIRCUIT DESIGN SIMULATION PROGRAM INCLUDING MACRO MODEL AND CIRCUIT DESIGN SIMULATOR CAPABLE OF EXECUTING CIRCUIT DESIGN SIMULATION PROGRAM
A macro model is used in a circuit design simulator based on a nodal method. The macro model is configured to include a behavior model the function of which is defined by one conditional branch that includes a plurality of conditional branches as options.
A semiconductor device includes an insulating layer, a barrier electrode layer formed on the insulating layer, a Cu electrode layer that includes a metal composed mainly of copper and that is formed on a principal surface of the barrier electrode layer, and an outer-surface insulating film that includes copper oxide, that coats an outer surface of the Cu electrode layer, and that is in contact with the principal surface of the barrier electrode layer.
H01L 23/522 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H01L 23/528 - Layout of the interconnection structure
H01L 23/532 - Arrangements for conducting electric current within the device in operation from one component to another including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
61.
SEMICONDUCTOR DEVICE, VEHICLE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device comprises a support, a first semiconductor element that is supported by the support, and a first bonding layer that is interposed between the support and the first semiconductor element. The first bonding layer has a flat portion and a protruding portion. The dimension of the protruding portion in the thickness direction of the support is greater than that of the flat portion, and the protruding portion is in contact with an edge of the first bonding layer that extends in a first direction orthogonal to said thickness direction. The protruding portion has a top portion farthest from the support in the thickness direction. When viewed in the thickness direction, the flat portion overlaps the first semiconductor element. When viewed in the thickness direction, the top portion is separated from the first semiconductor element toward a first side in a second direction orthogonal to the thickness direction and the first direction.
This semiconductor device comprises: a main transistor that has a main surface on which a main source electrode and a main gate electrode are formed; and a sub-transistor at least a part of which is disposed over the main gate electrode. The sub-transistor has a sub-drain electrode electrically connected to the main gate electrode, and a sub-source electrode electrically connected to the main source electrode.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 21/60 - Attaching leads or other conductive members, to be used for carrying current to or from the device in operation
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A chip resistor includes: an insulating substrate having a front surface, a back surface on an opposite side of the insulating substrate from the front surface, a first end surface connected to the front surface and the back surface, and a second end surface on an opposite side of the insulating substrate from the first end surface; a resistor layer disposed over the front surface; a first electrode connected to the resistor layer; and a second electrode connected to the resistor layer, wherein the first end surface and the second end surface are spaced apart from each other in a direction in which the first electrode and the second electrode are spaced apart from each other, and wherein the first electrode includes a first back surface electrode disposed over the back surface and electrically connected to the resistor layer.
H01C 17/00 - Apparatus or processes specially adapted for manufacturing resistors
H01C 1/028 - HousingEnclosingEmbeddingFilling the housing or enclosure the resistive element being embedded in insulation with outer enclosing sheath
H01C 1/142 - Terminals or tapping points specially adapted for resistorsArrangements of terminals or tapping points on resistors the terminals or tapping points being coated on the resistive element
H01C 7/06 - Non-adjustable resistors formed as one or more layers or coatingsNon-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material including means to minimise changes in resistance with changes in temperature
H01C 17/23 - Apparatus or processes specially adapted for manufacturing resistors adapted for trimming by opening or closing resistor tracks of predetermined resistive values
An insulating substrate comprises a ceramic substrate having a major surface, a plurality of first ribs formed on the major surface, and a glaze layer disposed on the major surface so as to cover the plurality of first ribs. The plurality of first ribs in plan view extend in a first direction and are spaced in a second direction orthogonal to the first direction and thus aligned.
A power semiconductor device used in a boost converter to boost an input voltage comprises: an output terminal; a switching circuit including a switching transistor and configured to generate an output terminal voltage at the output terminal using an inductor that receives the input voltage, the output terminal voltage resulting from boosting of the input voltage; a feedback terminal to receive a monitoring subject voltage responsive to the output terminal voltage via an external wire of the power semiconductor device; and a control driving circuit configured to control the switching circuit on the basis of error between a comparison voltage and a predetermined reference voltage, the comparison voltage being determined on the basis of a feedback voltage applied to the feedback terminal and the output terminal voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
This semiconductor device comprises a first terminal, a second terminal, a third terminal, a fourth terminal, a first lead, a second lead, a semiconductor element, and a sealing resin. A dimension of a first exposed surface of the first lead is larger than a dimension of a first mounting surface of the first terminal. A dimension of a second exposed surface of the second lead is larger than a dimension of a second mounting surface of the second terminal. When viewed in a third direction, which is a direction normal to the bottom surface of the sealing resin, a first end of the first exposed surface and a third end of the second exposed surface are positioned further inward than the peripheral edge of the sealing resin. When viewed in the third direction, a fourth end of the second exposed surface overlaps the peripheral edge of the sealing resin.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
This semiconductor device is provided with a first lead, a semiconductor element, and a sealing resin. The first lead has a pad part and a first support part. The first support part has a first surface, a second surface, and a first end surface. The pad part is exposed from a bottom surface of the sealing resin. The dimension of the sealing resin in a first direction from the bottom surface to the second surface is smaller than the dimension of the sealing resin in the first direction z from a top surface of the sealing resin to the first surface. The dimension of the second surface in a second direction is 50% or more of the dimension of a region of the bottom surface, the region being adjacent to the pad part on one side in the second direction and overlapping with the second surface when viewed in the first direction.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
68.
METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A method for producing a semiconductor device according to the present invention comprises a first step, a second step, a third step, and a fourth step. In the third step, a pad part is exposed from the bottom surface of a sealing resin. In the third step, the dimensions of the sealing resin from the bottom surface to a second surface of a first support part in a first direction are made smaller than the dimensions of the sealing resin from the top surface of the sealing resin to a first surface of the first support part in the first direction. In the fourth step, the first support part is cut by applying a compressive force to the top surface while supporting the second surface with a support body. In the fourth step, a first end surface that faces one side of a second direction and that is exposed from the sealing resin is formed on the first support part.
This semiconductor device includes a support, a first semiconductor element supported by said support, and a first bonding sheet interposed between the support and the first semiconductor element. The first bonding sheet has a first portion and a second portion. The first portion includes an area that overlaps the first semiconductor element when viewed in the thickness direction of the support. The second portion includes an area that does not overlap the first semiconductor element when viewed in said thickness direction. The second portion is thinner than the first portion in said thickness direction.
A semiconductor device includes: a first chip including a first semiconductor substrate, a first circuit, and a first element insulating layer formed over the first semiconductor substrate; a second chip spaced apart from the first chip in a first direction and including a second semiconductor substrate, a second circuit, and a second element insulating layer formed over the second semiconductor substrate; a sub-mount chip separate from the first and second chips; and a transformer chip disposed over the sub-mount chip and including a transformer through which the first and second circuits transmit signals or power, wherein the transformer chip includes a third semiconductor substrate and a third element insulating layer formed over the third semiconductor substrate, wherein the transformer is embedded in the third element insulating layer, and wherein the sub-mount chip includes a fourth semiconductor substrate and an insulating layer formed over the fourth semiconductor substrate.
A nitride semiconductor device includes an electron transit layer, an electron supply layer, a gate layer, a gate electrode on the gate layer, a source electrode, and a drain electrode. The gate layer includes a first gate portion, a second gate portion, and a recess between the first gate portion and the second gate portion. The gate electrode is arranged over both the first gate portion and the second gate portion. The nitride semiconductor device further includes an insulator located in the recess.
H01L 29/423 - Electrodes characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
A simulation apparatus comprises a model storage unit storing a motor physical model modeled by a wiring circuit section and a rotation motion equation section, and an abnormal state model obtained by modeling a motor abnormal state; and a model arithmetic unit configured to perform arithmetic processing using the motor physical model. The abnormal state model calculates an abnormal parameter indicating a deviation amount from a normal state, and the abnormal parameter is input to the motor physical model.
A pulse transmission circuit is incorporated in a signal transmission device employing a capacitive insulation method, and configured to cause a transmission pulse signal, which is transmitted to a capacitor of a subsequent stage, to make a gradual logic-level transition when a logic level of an input pulse signal switches. For example, the pulse transmission circuit may be configured to trigger the transmission pulse signal a plurality of times, while causing the transmission pulse signal to make a gradual logic-level transition, so as to repeat raising and lowering of the transmission pulse signal.
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
H03M 1/78 - Simultaneous conversion using ladder network
74.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, a lead frame, a conductive member, a resin composition and a sealing resin. The semiconductor element has an element front surface and an element back surface facing away in a first direction. The semiconductor element is mounted on the lead frame. The conductive member is bonded to the lead frame, electrically connecting the semiconductor element and the lead frame. The resin composition covers a bonded region where the conductive member and lead frame are bonded while exposing part of the element front surface. The sealing resin covers part of the lead frame, the semiconductor element, and the resin composition. The resin composition has a greater bonding strength with the lead frame than a bonding strength between the sealing resin and lead frame and a greater bonding strength with the conductive member than a bonding strength between the sealing resin and conductive member.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A semiconductor device includes a semiconductor element, a sealing resin covering the semiconductor element, a terminal electrically connected to the semiconductor element and protruding from the sealing resin in a first direction orthogonal to a thickness direction, and a plating layer located on the terminal. The terminal includes an end surface at a distal end protruding from the sealing resin, a first surface facing a first side in the thickness direction, and a recess recessed from both the end surface and the first surface. The plating layer includes a recess plating section located on at least a portion of the recess.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes a semiconductor element and a first connection member. The semiconductor element includes a substrate and an electrode pad. The substrate includes a transistor formation region, in which a transistor is formed and which is shaped to be non-quadrangular. The electrode pad is located on the transistor formation region. The first connection member is connected to the electrode pad at one location. The electrode pad is arranged to cover a center of gravity of the transistor formation region in a plan view of the electrode pad. In the plan view, a connection region in which the first connection member is connected to the electrode pad includes a center of gravity position of the transistor formation region.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 21/765 - Making of isolation regions between components by field-effect
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
A semiconductor device includes: a supporting body having first and second principal faces, and semiconductor elements; a thin film metal electrode on the first principal face; a thick film metal body on the thin film metal electrode; and a resin structure on the supporting body. The thick film metal body has a thickness greater than that of the thin film metal electrode. The resin structure includes a first resin body that covers a side of the thick film metal body. The resin structure has at least one of structures 1 and 2 as follows: in the structure 1, the resin structure further includes a second resin body on the second principal face; and in the structure 2, the first resin body includes first and second regions on the first principal face, and the second region has a thickness greater than that of the first region.
H01L 23/14 - Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
H01L 23/08 - ContainersSeals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
A semiconductor device includes: a first chip including a first circuit; a second chip disposed to be spaced apart from the first chip in a first direction and including a second circuit; and a transformer chip disposed over the first chip and including a transformer. The first circuit and the second circuit are configured to transmit a signal or power via the transformer. The transformer chip includes: an element insulating layer; and an outer coil and an inner coil disposed as the transformer in the element insulating layer. The inner coil is disposed inside the outer coil so as not to overlap the outer coil when viewed from a thickness direction of the element insulating layer.
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
The present disclosure provides a nitride semiconductor device. The nitride semiconductor device includes: an electron travelling layer; an electron supply layer; a gate layer, formed on the electron supply layer; a gate electrode, formed on the gate layer; and a passivation layer, having a source opening and a drain opening. The electron travelling layer includes: a first portion, located under the gate layer; and a second portion, located between the gate layer and the source opening, and located between the gate layer and the drain opening. The electron supply layer includes: a first electron supply layer, formed on the first portion and located below the gate layer; and a second electron supply layer, formed on the second portion and connected to the first electron supply layer.
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
The present disclosure provides a Hall element. The Hall element includes: a substrate; a magnetosensitive layer, disposed on a top surface of the substrate; a protective layer, covering the magnetosensitive layer and having an opening exposing a predetermined region of the magnetosensitive layer; an ohmic contact layer, electrically connected to the magnetosensitive layer exposed from the opening, wherein a portion of the ohmic contact layer is in contact with the protective layer around the opening; and a metal layer, disposed on the ohmic contact layer, wherein a portion of the metal layer is in contact with the protective layer around the ohmic contact layer.
A power supply control device includes a feedback terminal, a feedback control circuit, and a terminal inspection circuit. The feedback control circuit is configured to control an output stage of a power supply device according to a feedback voltage applied to the feedback terminal. The terminal inspection circuit is configured to forcibly stop driving the output stage when it is detected that the feedback voltage is lower than a first threshold and an output current flowing through the output stage is higher than a second threshold during a first period at start-up, or when it is detected that the feedback voltage is lower than the first threshold at completion of the first period.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
H02M 1/36 - Means for starting or stopping converters
Provided is a semiconductor package including a Si substrate, a drift layer, a buffer layer, an anode electrode, a trench, a semiconductor apparatus, an anode terminal, a cathode terminal, and a sealing resin.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/24 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only inorganic semiconductor materials not provided for in groups , , or
H01L 29/417 - Electrodes characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
GATE DRIVE CIRCUIT, POWER GOOD CIRCUIT, OVERCURRENT DETECTION CIRCUIT, OSCILLATION PREVENTION CIRCUIT, SWITCHING CONTROL CIRCUIT AND SWITCHING POWER SUPPLY DEVICE
A high-side pre-driver includes a first high-side transistor and a second high-side transistor, a low-side pre-driver includes a third high-side transistor and a fourth high-side transistor and a delay is provided in at least one of a time period between a first gate signal configured to turn on the first high-side transistor and a second gate signal configured to turn on the second high-side transistor and a time period between a third gate signal configured to turn on the third high-side transistor and a fourth gate signal configured to turn on the fourth high-side transistor.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
In order both to accommodate instantaneous current as well as overcurrent protection in accordance with the load, an overcurrent protection circuit has: a threshold value generation unit that, in accordance with a threshold value control signal, switches between setting an overcurrent detection threshold value to a first set value (∝Iref) and a second set value (∝Iset) lower than the first set value; an overcurrent detection unit that compares a sense signal in accordance with the current being monitored and the overcurrent detection value and generates an overcurrent protection signal; a reference value generation unit that generates a reference value (∝Iset) in accordance with the seconds set value; a comparison unit that compares the sense signal and the reference value, and generates a comparison signal; and a threshold value control unit that monitors the comparison signal, and generates a threshold value control signal.
H02H 1/00 - Details of emergency protective circuit arrangements
B60R 16/02 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric
B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
H02H 3/087 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current for DC applications
H02H 3/093 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current with timing means
H02H 7/20 - Emergency protective circuit arrangements specially adapted for specific types of electric machines or apparatus or for sectionalised protection of cable or line systems, and effecting automatic switching in the event of an undesired change from normal working conditions for electronic equipment
85.
JOINT STRUCTURE, SEMICONDUCTOR DEVICE, AND JOINING METHOD
A joint structure includes a first and a second metal member overlapping with each other as viewed in a first direction. The first metal member and the second metal member are joined together. The joint structure includes a welded portion at which the first metal member and the second metal member, overlapping with each other, are partly fused to each other. The welded portion has an outer circumferential edge and a plurality of linear marks. The outer circumferential edge is annular as viewed in the first direction. The plurality of linear marks each extend from an inside of the welded portion toward the outer circumferential edge as viewed in the first direction. Each of the plurality of linear marks is curved to bulge to one sense of an annular direction along the outer circumferential edge.
A semiconductor device includes a first wire, a first semiconductor element including an electrode electrically connected to the first wire, and a bump electrically bonded to the electrode. The first wire includes a first bonding portion located at one end and a second bonding portion located at another end. The bump includes a disc portion in contact with the electrode, and a pillar portion protruding from the disc portion in a first direction. The second bonding portion is electrically bonded to the pillar portion. A dimension of the pillar portion in the first direction increases as approaching the first bonding portion.
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
A semiconductor device includes a plurality of first switching parts, a first control element, at least one lead, a plurality of first connection members and a plurality of second connection members. Each first switching part includes a first switching element and a second switching element. In the plurality of first switching parts, the first switching element and the second switching element are electrically connected in parallel to each other and are of different types. The first switching element and the second switching element of each first switching part are disposed around the first control element as viewed in a thickness direction.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/065 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
88.
NITRIDE SEMICONDUCTOR DEVICE COMPRISING LAYERED STRUCTURE OF ACTIVE REGION AND METHOD FOR MANUFACTURING THE SAME
A nitride semiconductor device includes a channel layer, a barrier layer made of AlxInyGa1-x-yN (x>0, x+y≤1), an active region that has a layered structure including the channel layer and the barrier layer, an inactive region that is formed at the layered structure around the active region and that is a concave portion having a bottom portion that reaches the channel layer, a gate layer made of a nitride semiconductor selectively formed on the barrier layer in the active region, a gate electrode formed on the gate layer, a first insulating film that covers the gate electrode and that is in contact with the barrier layer in the active region, and a second insulating film that covers the first insulating film and that is in contact with the inactive region.
H01L 29/20 - Semiconductor bodies characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
H01L 29/778 - Field-effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT
A semiconductor device includes a semiconductor element circuit, a conductive support and a sealing resin. The conductive support includes a die pad, first terminals spaced in a first direction, second terminals spaced in the first direction and opposite to the first terminals in a second direction perpendicular to the first direction, and a support terminal connected to the die pad. The sealing resin encapsulates portions of the first and second terminals, a portion of the support terminal, the semiconductor element circuit and the die pad. The sealing resin has two first side surfaces spaced apart in the second direction and two second side surfaces spaced apart in the first direction. The first terminals and second terminals are exposed from the first side surfaces, while none of the elements of the conductive support is exposed from the second side surfaces.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
A linear regulator includes: a first transistor of an N-channel type configured to be connected between an application terminal for an input terminal and an application terminal for a stabilized voltage; a second transistor of an N-channel type configure to, by forming a current mirror type output stage with the first transistor, generate an output current flowing in the first transistor by mirroring a bias current flowing in the second transistor itself; a feedback controller circuit configured to control the bias current according to the difference between a feedback voltage corresponding to the stabilized voltage and a predetermined reference voltage; and a load configured to draw a first leakage current from a control terminal common to the first and second transistors.
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.
The present disclosure provides a thermal print head. The thermal print head includes: a substrate; a glaze layer; a wiring layer; a heat element; and a protective layer. The glaze layer is disposed on the substrate. The wiring layer is disposed on the glaze layer. The wiring layer has a common electrode and a plurality of individual electrodes. The common electrode has protrusions arranged in intervals along a first direction in a plan view and extending along a second direction perpendicular to the first direction in the plan view. The plurality of individual electrodes have tip portions extending along the second direction. The protrusions and the tip portions are alternately arranged in intervals along the first direction in the plan view. The heat element extends along the first direction in the plan view, is disposed on the glaze layer, and overlaps with the protrusions and the tip portions.
A bootstrap circuit includes a first switch configured to have a first terminal to which a constant voltage is applied, a capacitor configured to have a first terminal to which a second terminal of the first switch is connected and a second terminal to which a switching voltage is applied, and a controller configured to control the first switch based on the switching voltage and a control signal. The switching voltage is a voltage generated at a connection node between a first switching element and a second switching element. The second switching element is a switching element provided on a lower potential side with respect to the first switching element and configured to perform switching based on the control signal.
H02M 3/145 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
This semiconductor device includes: a chip having a main surface; a body region formed in a surface layer portion of the main surface; a plurality of gate electrodes disposed on both sides of the body region on the main surface; and a connection electrode formed in a region between the plurality of gate electrodes on the main surface so as to overlap the body region in the thickness direction, and connected to the plurality of gate electrodes.
An overcurrent protection circuit that limits a current to be monitored based on a current limit signal includes: a first transistor and a second transistor configured to form an amplifier input stage that receives input of a detection signal according to the current to be monitored; a third transistor configured to generate a current output signal according to a difference between the detection signal and a reference signal, and configured to form an amplifier output stage that inputs the current output signal as a negative feedback to the amplifier input stage; and a current mirror circuit configured to generate the current limit signal by replicating a signal based on the current output signal.
A piezoelectric film device 90 includes a substrate 80 having a lower surface 81 and an upper surface 82 facing opposite directions, a support portion 41 supporting the lower surface 81 and fixed to an installation surface, and a piezoelectric film 12 provided on the upper surface 82 and displaced in a vertical direction together with the substrate 80 in response to application of a bias voltage and a drive voltage, in which the substrate 80 has a first region 81x supported by the support portion 41 and a second region 81y not supported by the support portion 41 as regions of the lower surface 81, and in a state where the bias voltage and the drive voltage are not applied, the substrate 80 is formed to be warped such that the second region 81y is located closer to the installation surface than the first region 81x.
An output feedback control circuit includes, for example, a first amplifier configured to generate a first error signal commensurate with a difference between an output voltage, which is fed to a load, or a feedback voltage commensurate therewith and a reference voltage, a second amplifier configured to be faster than the first amplifier and to generate a second error signal commensurate with a difference between the output voltage or the feedback voltage and the first error signal (or the reference voltage), a calculator configured to superimpose a remote sense signal, which is derived from a grounded terminal of the load, on the reference voltage, which is fed to the first amplifier, and a capacitor connected between an application terminal for the first error signal and an application terminal for the remote sense signal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device according to the present invention comprises a plurality of first leads, a semiconductor element, and a sealing resin. The plurality of first leads each has: a first lead first surface that faces a first side of the thickness direction and that is exposed from a resin first surface; a first lead second surface that faces a second side of the thickness direction; and a first lead first end surface that is located between the first lead first surface and the first lead second surface in the thickness direction, that faces the outer side of a first direction, and that is exposed from a resin side surface. The first lead first surface has a first narrow-width part that connects to the first lead first end surface and a first wide-width part that is located on the inner side of the first direction with respect to the first narrow-width part. The first narrow-width part has a first edge that is in contact with the first lead first end surface. A first width that is the size of the first edge in a second direction is smaller than a second width that is the size of the first wide-width part in the second direction.
H01L 23/50 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements for integrated circuit devices
An operational amplifier includes: an input circuit including a PMOS input differential pair and an NMOS input differential pair, an operating input differential pair being switchable between the PMOS input differential pair and the NMOS input differential pair; a current generation circuit structured to generate a reference current; and an output circuit through which an idling current that increases according to an increase in the reference current flows, and structured to generate an output voltage according to output signals of the PMOS input differential pair and the NMOS input differential pair. The current generation circuit is structured to make the reference current larger in a case where a decreasing condition of the idling current is satisfied than in a case where the decreasing condition is not satisfied.
The present disclosure provides a transducer. The transducer includes: a support substrate, having a first cavity; an oscillating device; and a lid, having a second cavity and bonded to the oscillating device by an adhesive. The oscillating device includes a first frame and an oscillating unit. A portion of the oscillating unit is connected to the first frame. When viewed from a connection direction of the oscillating device and the lid, the portion of the oscillating unit other than a connecting portion between the oscillating unit and the first frame is separated from the first frame by a slit penetrating the oscillating device along the connection direction. The lid has a second frame surrounding the second cavity and including a second bonding surface bonded to the first bonding surface by the adhesive. The first cavity and the second cavity are connected by the slit.
