A light-emitting element driving device includes a monitoring section that monitors a voltage of a connection terminal with a driving current in an on state and holds a monitoring result; an output section that outputs a terminal voltage detection signal indicating whether a voltage of the connection terminal of at least one channel is lower than a reference voltage based on the held monitoring result; an output terminal that outputs the terminal voltage detection signal to an outside; an input terminal; and a control signal generation section that generates a control signal used for feedback control of a power supply circuit that generates a power supply voltage based on a signal input to the input terminal and the held monitoring result, wherein the on state of the driving current is controlled during one period of a synchronization signal, and the control signal generation section updates the control signal when the next period of the synchronization signal starts.
A signal transmission device is configured to transmit a pulse signal while isolating between a primary circuit system and secondary circuit system to drive a switching element. The signal transmission device includes: a first external terminal configured to receive a first input signal for driving a state of a driver output; a second external terminal configured to receive a second input signal for ASC operation; and a third external terminal configured to output the driver output and follow a logic level at the second external terminal.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
H03K 17/567 - Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
A semiconductor device includes semiconductor elements. Each semiconductor element, including first, second and third electrodes, is controlled to turn on and off current flow between the first electrode and the second electrode by drive signals inputted to the third electrode. The first electrodes of the semiconductor elements are electrically connected mutually, and the second electrodes of the semiconductor elements are electrically connected mutually. The semiconductor device further includes a control terminal receiving the drive signals, a first wiring section connected to the control terminal, a second wiring section, and third wiring sections, and further a first connecting member electrically connecting the first and the second wiring sections, a second connecting member electrically connecting the second wiring section and each third wiring section, and third connecting members connecting the third wiring sections and the third electrodes of the semiconductor elements.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
The semiconductor light-emitting device includes: a substrate; a light-receiving chip that includes a light-receiving element having a light-receiving surface formed on the chip surface; an edge-emitting chip that has a first light-emitting surface that emits first laser beam and a second light-emitting surface that emits second laser beam in an opposite direction, and that is joined to a position different from the light-receiving surface on the chip surface; a sealing member with a material through which the first and second laser beams can pass, the sealing member covering the edge-emitting chip and the light-receiving chip; and a reflection part provided in the sealing member and that reflects at least a portion of the second laser beam toward the light-receiving surface. The light-receiving surface is formed in a position on the chip surface for receiving at least a part of the reflected light by the reflection part.
H10F 55/00 - Radiation-sensitive semiconductor devices covered by groups , or being structurally associated with electric light sources and electrically or optically coupled thereto
H10F 77/00 - Constructional details of devices covered by this subclass
A semiconductor light-emitting device comprising: a substrate including a substrate surface; a first end surface light-emitting element disposed on the substrate, including a first front light-emitting surface and a first rear light-emitting surface that are both end surfaces in a first direction intersecting a thickness direction perpendicular to the substrate surface, and configured such that light is emitted from both the first front light-emitting surface and the first rear light-emitting surface; a first reflector having a first reflection surface facing the first front light-emitting surface; a second reflector having a second reflection surface facing the first rear light-emitting surface; and a translucent sealing member disposed in a region surrounded by the first reflector and the second reflector and sealing the first end surface light-emitting element.
This electronic device comprises a first bonded object, a second bonded object, and a first wire having a first bonding section, a second bonding section, and a loop section. The first bonding section is connected to one end of the loop section and is bonded to the first bonded object. The second bonding section is connected to the other end of the loop section and is bonded to the second bonded object. The first bonding section has a first raised section and two first extension sections. The first raised section protrudes to one side in the thickness direction and extends in a first direction. The two first extension sections extend from the first raised section to both sides in a second direction when viewed in the thickness direction.
A semiconductor device comprises a first upper arm switching element, a first lower arm switching element, a first upper arm control element, a first lower arm control element, a first main power supply lead, a main ground lead, a first output lead, a plurality of control leads, a first upper arm secondary-side control power supply lead, a first upper arm secondary-side control ground lead, and a sealing resin. The first main power supply lead, the main ground lead, the first output lead, the first upper arm secondary-side control power supply lead, and the first upper arm secondary-side control ground lead protrude from the sealing resin to a first side in a first direction. The plurality of control leads protrude from the sealing resin to a second side in the first direction.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
8.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device comprises a first semiconductor element. The semiconductor device includes a first object, a second object, and a bonding layer interposed between the first object and the second object. The bonding layer includes a first surface layer bonded to the first object, a second surface layer bonded to the second object, and a base layer positioned between the first surface layer and the second surface layer. The first surface layer is bonded to the first object by solid-phase diffusion bonding, and includes a plurality of first crystal grains having a median diameter of 0.001 μm to 1.0 μm, inclusive.
This light-emitting device comprises: a multilayer substrate (20) including a substrate front surface (21), a substrate rear surface on the side opposite the substrate front surface (21), a front surface conductive layer (30) provided on the substrate front surface (21), a rear surface conductive layer provided on the substrate rear surface, and a first power-supply through-hole electrically connected to the front surface conductive layer (30); and a light-emitting element electrically connected to the front surface conductive layer (30). The front surface conductive layer (30) includes first power-supply wiring (40) that electrically connects the first power-supply through-hole to the light-emitting element. The first power-supply wiring (40) includes a plurality of pad regions (46) for mounting elements. The multilayer substrate (20) includes a pad-use heat dissipation via (90) provided in the multilayer substrate (20). The pad-use heat dissipation via (90) is provided at a position overlapping both the pad region (46) and the rear surface conductive layer in plan view.
A switching power supply circuit includes: a rectifier circuit; a DC/DC converter; a power factor correction IC configured to have a power factor correction function; and a control IC. The control IC includes: a first terminal configured to receive a feedback voltage based on a DC output voltage output from the DC/DC converter; and a second terminal. The control IC is configured to control a switching element according to the feedback voltage. The control IC is further configured to output a voltage for ON/OFF-controlling the power factor correction function from the second terminal.
H02M 3/335 - Conversion of DC power input into DC power output with intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate AC using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
Provided is a power supply control apparatus including an output stage provided between an input terminal to which an input voltage is applied and an output terminal to which an output voltage is applied and generating the output voltage from the input voltage. The power supply control apparatus includes a stabilization control circuit causing the output voltage to stabilize to a target voltage by controlling a state of the output stage according to a feedback voltage corresponding to the output voltage, a parameter storage circuit storing a plurality of internal parameters for defining a temperature characteristic of the stabilization control circuit, a communication circuit receiving a command signal from an external apparatus outside the power supply control apparatus, and a setting circuit setting the temperature characteristic of the stabilization control circuit by setting any one of the plurality of internal parameters to valid on the basis of the command signal.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 1/36 - Means for starting or stopping converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A MEMS resonator includes a pantograph that is a parallelogram, an oscillator connected to each vertex of the pantograph, and an electrode disposed opposite each oscillator, and forming a capacitor with the oscillator. A set of the electrodes disposed opposite to a set of the oscillators along an extension direction of a diagonal line of the pantograph that is the parallelogram have applied thereto a voltage differing in phase by 180° from another set of the electrodes disposed opposite to another set of the oscillators along an extension direction of another diagonal line of the pantograph. At least two of the MEMS resonators are connected so as to share one oscillator.
Provided is a mounting component held so as to be capable of attachment and detachment by a mounting machine. The mounting component includes a membrane support, a vibrating membrane connected to the membrane support and displaceable in a membrane thickness direction, and a contact member that is located on the membrane support and is subjected to an upward attractive force by the mounting machine without generating stress leading to shape deformation or breakage of the vibrating membrane during the attachment and detachment.
This semiconductor device comprises a base material, a first semiconductor element, a support member, and a heat dissipation member. The first semiconductor element is mounted on one side of the base material in a first direction. The support member and the heat dissipation member are positioned on a side opposite to the first semiconductor element with respect to the base material. The heat dissipation member is a member different from the support member and is supported by the base material. The support member has a first surface facing a side on which the first semiconductor element is located with respect to the base material in the first direction. The base material is supported by the first surface.
A terahertz system (10) comprises: a plurality of first terahertz elements (21) that oscillate and detect terahertz waves; a plurality of second terahertz elements (22) that oscillate and detect terahertz waves; and a control device (30) configured to switch between a first state in which the plurality of first terahertz elements (21) oscillate terahertz waves and the plurality of second terahertz elements (22) detect the terahertz waves, and a second state in which the plurality of second terahertz elements (22) oscillate terahertz waves and the first terahertz elements (21) detect the terahertz waves.
H03B 7/08 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device being a tunnel diode
G01N 21/3581 - Investigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light using far infrared lightInvestigating relative effect of material at wavelengths characteristic of specific elements or molecules, e.g. atomic absorption spectrometry using infrared light using Terahertz radiation
H10D 8/40 - Transit-time diodes, e.g. IMPATT or TRAPATT diodes
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/81 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wellsSemiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures having periodic or quasi-periodic potential variation
H10D 62/815 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wellsSemiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
16.
Control Circuit, Power Supply Circuit, and Electronic Apparatus
A control circuit is configured to be used as part of a switched capacitor converter, which includes a plurality of switch elements and at least one capacitor, and is configured to generate a second voltage from a first voltage. The control circuit includes a mode switching circuit configured to switch between a first mode and a second mode. The first mode is a mode in which switching control of the plurality of switch elements is stopped to set the second voltage to a voltage value that can be regarded as the same as the first voltage. The second mode is a mode in which the plurality of switch elements is switching-controlled to set the second voltage to a voltage value lower than the first voltage.
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
G05F 1/565 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
H02M 3/137 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
Provided is a power supply control device provided in a switching power supply apparatus that converts an input voltage into an output voltage through switching of an output transistor, including a switching control circuit that stabilizes the output voltage by switching control of the output transistor, based on a feedback voltage corresponding to the output voltage, a signal output terminal, and a signal output circuit that is capable of outputting a signal corresponding to whether the output voltage is normal from the signal output terminal, based on the feedback voltage, the switching control circuit being capable of performing an overcurrent protecting operation that limits a current flowing through the output transistor to a limit current or less, and the signal output circuit outputting a specific signal indicating execution of the overcurrent protecting operation from the signal output terminal when the current flowing through the output transistor reaches the limit current.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 1/36 - Means for starting or stopping converters
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
This semiconductor device comprises a chip having a first main surface and a second main surface, a first impurity region of a first conductivity type in a surface layer portion of the first main surface, a first pillar region of a second conductivity type extending in the thickness direction of the chip from the first main surface toward the second main surface in the first impurity region, and a second pillar region of the first conductivity type formed by a part of the first impurity region, the second pillar region providing a super junction structure by a pn junction portion between the first pillar region and the second pillar region. The first pillar region partitions a closed region such that the pn junction portion having an annular shape in a plan view is provided, and the second pillar region is disposed inside the closed region.
This semiconductor module comprises: first and second semiconductor elements that are arranged along a first direction; a support member that includes a first electrical conductor to which the first semiconductor element is bonded and a second electrical conductor to which the second semiconductor element is bonded; a plurality of signal terminals that are electrically connected to the first semiconductor element or the second semiconductor element; a signal board that is supported by the support member, and a signal wiring portion that relays signal transmission between the first semiconductor element and the signal board. The plurality of signal terminals are joined to the signal board. The signal wiring portion is located outside the first semiconductor element and the second semiconductor element in a second direction intersecting the first direction.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
This semiconductor device comprises a first insulating layer, a first conductive layer, a second conductive layer, a first heat dissipation layer, a first semiconductor element, a second semiconductor element, a first sealing body, a second sealing body, a second insulating layer, a third conductive layer, a second heat dissipation layer, a first wiring layer, and a second wiring layer. A second electrode of the first semiconductor element is conductively bonded to the first conductive layer. A third electrode of the second semiconductor element is conductively bonded to the second conductive layer. The third conductive layer is conductively bonded to a first electrode of the first semiconductor element and a fourth electrode of the second semiconductor element. The first wiring layer and the second wiring layer are disposed on a first mounting surface of the first insulating layer and a second mounting surface of the second insulating layer, respectively.
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/29 - Encapsulation, e.g. encapsulating layers, coatings characterised by the material
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
21.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
This semiconductor device comprises: an SiC chip having a first main surface on one side and a second main surface on the other side; a device structure formed on the surface layer portion of the first main surface; and a main surface electrode covering the second main surface. The second main surface includes a roughened surface region that has a plurality of recesses formed with space therebetween in a first direction and a second direction intersecting the first direction, and that is in contact with the main surface electrode.
A clock signal generation circuit (10) includes: a first modulation signal generation circuit (11) that generates a first modulation signal (Sm1) having a first frequency (f1); a second modulation signal generation circuit (12) that generates a second modulation signal (Sm2) having a second frequency (f2) lower than the first frequency; a signal combining circuit (13) that generates a composite modulation signal (Smc) by combining the first modulation signal and the second modulation signal; and an oscillator (14) that generates a clock signal (CLK) having a frequency according to the composite modulation signal.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/44 - Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
H03K 4/06 - Generating pulses having essentially a finite slope or stepped portions having triangular shape
A semiconductor device includes: a first lead including a base portion; a semiconductor element mounted on a first side of the base portion in the thickness direction and including a first electrode; a second lead spaced apart from the base portion in a first direction perpendicular to the thickness direction; a first conductive member electrically bonded to the first electrode and the second lead; and a sealing resin. The first conductive member includes a first portion bonded to the first electrode via a conductive first bonding layer. The first portion includes a first surface and a second surface respectively facing the first side and a second side in the thickness direction. The first portion includes a plurality of first recesses that are recessed from the first surface and a plurality of second recesses that are recessed from the second surface.
This semiconductor device comprises: a first semiconductor element; a second semiconductor element; a first conductive member having a first terminal; a second conductive member having a second terminal; a third conductive member having a third terminal; a fourth conductive member having a fourth terminal; and a sealing resin covering the first semiconductor element and the second semiconductor element. The first semiconductor element has a first electrode and a second electrode, and a third electrode. The second semiconductor element has a fourth electrode and a fifth electrode, and a sixth electrode. A second path length, which is the length of a conductive path of the fourth electrode and a third external connection part, is shorter than a first path length, which is the length of a conductive path of the first electrode and the third external connection part.
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
25.
CONTROL SIGNAL GENERATION CIRCUIT, ELECTRIC POWER CONVERSION DEVICE, AND VEHICLE
A control signal generation circuit 5 according to one embodiment comprises: an insulated gate driver that is configured to output a control pulse signal corresponding to a common input pulse signal to first and second switching elements; a delay signal generation unit that is configured to generate at least one delay pulse signal using the control pulse signal; and a logic synthesis unit that is configured to generate first and second control pulse signals by performing different logic synthesis on two signal sets among a plurality of signal sets that are defined by the at least one delay pulse signal and the control pulse signal, wherein the first control pulse signal is different from the control pulse signal, and the second control pulse signal is different from the control pulse signal and the first control pulse signal.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
H03K 17/12 - Modifications for increasing the maximum permissible switched current
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
A semiconductor module includes: a substrate; and a semiconductor device that is located on one side of the substrate in a first direction and is conductively bonded to the substrate, wherein the semiconductor device includes: a first terminal, a second terminal, and a third terminal; a semiconductor element that is located on one side of the first terminal, the second terminal, and the third terminal in the first direction; and a sealing resin that covers the semiconductor element, wherein the semiconductor element includes a first circuit and a second circuit that are connected in series with each other, wherein the first circuit is electrically connected to the first terminal and the third terminal, wherein the second circuit is electrically connected to the second terminal and the third terminal, wherein the sealing resin has a bottom surface facing the substrate.
H01L 23/58 - Structural electrical arrangements for semiconductor devices not otherwise provided for
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/482 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements consisting of lead-in layers inseparably applied to the semiconductor body
A semiconductor device includes a support including a base member having a first main surface facing a thickness direction, a semiconductor element, and a bonding material that bonds the support and the semiconductor element. The bonding material includes a sintered metal portion and a resin portion. The support includes a metal layer located on the first main surface and having a stronger sintered bonding with the sintered metal portion than the base member. The bonding material includes a first portion in contact with the semiconductor element and the metal layer, and a second portion in contact with the semiconductor element and the base member.
A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.
A semiconductor device includes a substrate, a conductive part formed on a front surface of the substrate, a semiconductor chip disposed on the front surface of the substrate, a control unit that controls the semiconductor chip, a sealing resin that covers the semiconductor chip, the control unit and the conductive part, and a first lead bonded to the conductive part and partially exposed from the sealing resin. The conductive part includes a first pad and a second pad disposed apart from each other. The first lead is bonded to the first pad and the second pad.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
30.
SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND VEHICLE
A semiconductor device includes a heat sink, a base material including an insulating layer and mounted on the heat sink on one side in a first direction, a first conductive layer bonded to the base material and located on a side opposite the heat sink with respect to the base material, a first semiconductor element bonded to the first conductive layer, a first power terminal electrically connected to the first conductive layer and the first semiconductor element, and a sealing resin covering the first conductive layer and the first semiconductor element. The first power terminal is exposed from the sealing resin. The first power terminal is surrounded by a peripheral edge of the sealing resin as viewed in the first direction.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/367 - Cooling facilitated by shape of device
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 25/16 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different subclasses of , , , , or , e.g. forming hybrid circuits
31.
SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a semiconductor layer having a first face with a trench formed thereon and a second face opposite to the first face, a gate electrode, and a gate insulating layer. The semiconductor layer includes a first n-type semiconductor layer, a second n-type semiconductor layer, a p-type semiconductor layer, and an n-type semiconductor region. The trench is formed to penetrate through the p-type semiconductor layer and to reach the second n-type semiconductor layer. The p-type semiconductor layer includes an extended portion extending to a position closer to the second face of the semiconductor layer than the trench is. Such structure allows suppressing dielectric breakdown in the gate insulating layer.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
A semiconductor device, including: a semiconductor substrate having a first substrate surface and a second substrate surface opposite to each other; a trench recessed from the first substrate surface toward the second substrate surface, and has a width when viewed from a thickness direction of the semiconductor substrate; an insulating layer disposed inside the trench; and an electrode part disposed inside the trench and surrounded by the insulating layer, the electrode part having conductivity. The trench includes: a first trench part having a first width in a width direction of the trench, and a second trench part formed at a position different from that of the first trench part in the thickness direction and having a second width that is greater than the first width in the width direction.
This semiconductor module comprises a heat dissipation member, a first semiconductor element, a second semiconductor element, a first power terminal, a second power terminal, and a first external connection member. The first power terminal is electrically connected to the first semiconductor element. The second power terminal is electrically connected to the second semiconductor element. The first external connection member has a first housing part, a first conductive part, and a second conductive part. The first power terminal is conductively joined to the first conductive part. The second power terminal is conductively joined to the second conductive part. When viewed in a first direction, the first housing part overlaps the heat dissipation member. In the first direction, a part of the first housing part is positioned between the heat dissipation member, and the first conductive part and the second conductive part.
H01L 23/32 - Holders for supporting the complete device in operation, i.e. detachable fixtures
H01L 23/40 - Mountings or securing means for detachable cooling or heating arrangements
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H02M 7/48 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
A semiconductor device according to the present invention comprises: an insulating layer that covers a wiring layer and a device structure formed on a chip; a plurality of first contacts that are embedded in the insulating layer, are connected to a plurality of unit cells, and have a line width designed in accordance with a first design rule; a plurality of second contacts that are embedded in the insulating layer and connected to the wiring layer, the respective second contacts being disposed in a striped shape and having a line width designed in accordance with the first design rule using the same material as the first contacts; a first main surface electrode connected to the first contacts; and a second main surface electrode connected to the second contacts.
A controller includes a clock signal generation circuit configured to generate a clock signal, and a first pulse signal generation circuit configured to generate a first pulse signal that has the same frequency as the clock signal and in which one of a rising edge or a falling edge is synchronized with the clock signal. The first pulse signal generation circuit is configured to adjust a timing of the other of the rising edge or the falling edge of each of cycles of the first pulse signal, according to content of each of data of a first data transmission.
A signal transmission device includes a transmission circuit which outputs a control signal, a reception circuit and an insulating circuit. The reception circuit receives an input of an external signal. The reception circuit drives a drive target switch based on the control signal in a state where the external signal is at a first logic level at which the voltage of the external signal is equal to or lower than a first threshold voltage, and drives and controls the drive target switch based on the external signal regardless of the control signal in a state where the external signal is at a second logic level at which the voltage of the external signal is higher than the first threshold voltage.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
37.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE AND VEHICLE
A signal transmission device includes a transmission-side circuit, a reception-side circuit, an insulating circuit and a protection circuit configured to monitor an SAT voltage for a drive target switch during the on period of the drive target switch. The transmission-side circuit includes a first drive circuit, a second drive circuit and a drive control circuit. When the first drive circuit is enabled and the second drive circuit is disabled, the protection circuit starts monitoring the SAT voltage after a first blanking period has elapsed since a starting point of a transition period of the drive target switch whereas when the first drive circuit is disabled and the second drive circuit is disabled, the protection circuit starts monitoring the SAT voltage after a second blanking period longer than the first blanking period has elapsed since the starting point.
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
H02H 1/00 - Details of emergency protective circuit arrangements
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
38.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a support member, a semiconductor element and a sealing member. The semiconductor element is disposed on a first side in a thickness direction relative to the support member. The sealing member covers a part of the support member and the semiconductor element. The support member has a first surface facing a second side in the thickness direction and exposed from the sealing member. The first surface is formed with a first uneven region. In an example, the first uneven region has an arithmetic mean roughness between 0.2 μm and 13 μm. In an example, the first uneven region includes a plurality of uneven lines in an arc shape.
H01L 21/48 - Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups or
H01L 21/56 - Encapsulations, e.g. encapsulating layers, coatings
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
A semiconductor device includes a semiconductor layer that includes a semiconductor substrate having a first thickness and has a main surface, a main surface electrode that is arranged at the main surface and has a second thickness less than the first thickness, and a pad electrode that is arranged on the main surface electrode and has a third thickness exceeding the first thickness.
H01L 23/31 - Encapsulation, e.g. encapsulating layers, coatings characterised by the arrangement
H01L 23/00 - Details of semiconductor or other solid state devices
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
40.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a gate electrode buried in a gate trench of a first conductivity-type semiconductor layer, a first conductivity-type source region, a second conductivity-type channel region, and a first conductivity-type drain region formed in the semiconductor layer, a second trench selectively formed in a source portion defined in a manner containing the source region in the surface of the semiconductor layer, a trench buried portion buried in the second trench, a second conductivity-type channel contact region selectively disposed at a position higher than that of a bottom portion of the second trench in the source portion, and electrically connected with the channel region, and a surface metal layer disposed on the source portion, and electrically connected to the source region and the channel contact region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/00 - Electrodes of devices having potential barriers
A semiconductor device includes a first die pad having a main surface, a second die pad having a second main surface, a first switching element connected to the first main surface, a second switching element connected to the second main surface, a first connecting member connecting the first main surface electrode of the first switching element to the second die pad, an encapsulation resin encapsulating the first switching element, the second switching element, the first die pad, the second die pad, and the first connecting member, and leads projecting out of one of the resin side surfaces of the encapsulation resin.
This semiconductor device is provided with a base material, a first semiconductor element, and a heat dissipation member. The heat dissipation member includes a first heat dissipation body extending in a first direction. The first heat dissipation body has a first base part, a second base part, a first main part, a second main part 714, and a connection part. The first base part and the second base part are supported by the base material. The first main part includes a first cross section and a third cross section. The second main part includes a second cross section and a fourth cross section. A distance L in the first direction from the second cross section to the fourth cross section is equal to a distance in the first direction from the first cross section to the third cross section. An interval in a second direction between the third cross section and the fourth cross section is larger than an interval in the second direction between the first cross section and the second cross section.
In a motor drive device, a control clock signal is generated on the basis of a position detection signal obtained by detecting the position of a rotor of a three-phase motor with a first angular amount as a minimum unit. On the basis of the control clock signal and the position detection signal, an electrical angle indicating the position of the rotor with a second angular amount smaller than the first angular amount as a minimum unit is estimated and updated as a control electrical angle, and a drive control signal for the coil of each phase is generated on the basis of the control electrical angle. The detection electrical angle based on the position detection signal is compared with the control electrical angle at the generation timing of a unique signal in the position detection signal, and the update cycle of the control electrical angle is adjusted according to the difference between them.
H02P 6/08 - Arrangements for controlling the speed or torque of a single motor
H02P 27/08 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters with pulse width modulation
A driving device includes: for example, a supply circuit configured to generate a supply voltage; a driving circuit configured to generate a driving signal for a switching device by being supplied with the supply voltage; and a logic circuit configured to control the driving circuit according to a first input signal and a second input signal. The supply circuit sets the supply voltage to a first voltage value in a first mode and sets the supply voltage to one of a second voltage value that is less than the first voltage value and the first voltage value in a second mode. The logic circuit enables the second input signal in the first mode and disables the second input signal in the second mode.
H03K 19/08 - Logic circuits, i.e. having at least two inputs acting on one outputInverting circuits using specified components using semiconductor devices
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
H02H 3/08 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess current
H03K 3/017 - Adjustment of width or dutycycle of pulses
A device module is provided, which includes a communication path, a semiconductor device, an interface connected to the communication path, and a second control unit. The second control unit, in a first state, generates a setting signal including setting information and inputs the setting signal to the semiconductor device.
H04N 23/66 - Remote control of cameras or camera parts, e.g. by remote control devices
B60R 16/023 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for transmission of signals between vehicle parts or subsystems
47.
SEMICONDUCTOR POWER DEVICE AND METHOD FOR PRODUCING SAME
A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/28 - Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/83 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes a semiconductor layer having a main surface in which a gate trench is formed, a gate insulating layer formed along an inner wall of the gate trench, a gate electrode layer constituted of a polysilicon and embedded in the gate trench across the gate insulating layer, and a low resistance electrode layer including a conductive material having a sheet resistance less than a sheet resistance of the gate electrode layer and covering the gate electrode layer.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/00 - Electrodes of devices having potential barriers
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
50.
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes a step of preparing a semiconductor substrate that has a first main surface on one side and a second main surface on the other side, the semiconductor substrate on which a plurality of device forming regions and an intended cutting line that demarcates the plurality of device forming regions are set, a step of forming a first electrode that covers the first main surface in each of the device forming regions, a step of forming a second electrode that covers the second main surface, a step of partially removing the second electrode along the intended cutting line such that the semiconductor substrate is exposed, and forming a removed portion that extends along the intended cutting line, and a step of cutting the semiconductor substrate along the removed portion.
The semiconductor device includes a semiconductor layer which has a main surface, a switching device which is formed in the semiconductor layer, a first electrode which is arranged on the main surface and electrically connected to the switching device, a second electrode which is arranged on the main surface at an interval from the first electrode and electrically connected to the switching device, a first terminal electrode which has a portion that overlaps the first electrode in plan view and a portion that overlaps the second electrode and is electrically connected to the first electrode, and a second terminal electrode which has a portion that overlaps the second electrode in plan view and is electrically connected to the second electrode.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
52.
Power Supply Control Device, Power Supply Device, and Electronic Apparatus
A power supply control device includes an output feedback terminal, a power supply control circuit that controls an output voltage according to a terminal voltage of the output feedback terminal when enabled, an output monitoring circuit that monitors the terminal voltage regardless of whether the power supply control circuit is enabled or disabled, and a logic circuit that switches an enable/disable setting of the power supply control circuit and generate an output signal according to a monitoring result of the terminal voltage.
G05F 1/571 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector
G05F 1/575 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
A capacitor includes a semiconductor substrate including a first substrate surface, an insulating layer provided over the first substrate surface, and a first electrode and a second electrode that are provided in the insulating layer and that oppose each other. The first electrode includes a first electrode plate and a plurality of first electrode parts. The second electrode includes a second electrode plate and a plurality of second electrode parts. The second electrode plate is positioned across the first electrode plate from the first substrate surface within the insulating layer so as to oppose the first electrode plate. The plurality of first electrode parts and the plurality of second electrode parts are disposed alternately in the X direction and oppose each other in the X direction. The first electrode plate is interposed between the plurality of second electrode parts and the semiconductor substrate.
A power supply control device, which is a main controller of a switching power supply, includes an error amplifier, a ramp signal generation circuit, a comparison signal generation circuit, a logic circuit, a switch drive circuit, a reverse current detection circuit, and a ramp signal holding circuit. The logic circuit adjusts an input offset of the comparison signal generation circuit, the error signal, or the ramp signal in a direction that reduces a difference between the error signal and the ramp signal in response to a predetermined trigger signal.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A power module includes a insulation substrate, a first and a second input terminal supported by the insulation substrate, a plurality of arm circuits provided on the insulation substrate, and a plurality of output terminals corresponding to the plurality of arm circuits. The arm circuits each include a part of a wiring pattern formed on the insulation substrate, and a first switching element and a second switching element mutually connected in series via the part of the wiring pattern. The output terminals are each connected to a connection point between the first switching element and the second switching element in a corresponding one of the plurality of arm circuits. The plurality of arm circuits are located so as to overlap with a circle surrounding the first input terminal, as viewed in a thickness direction the insulation substrate.
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
H02M 7/483 - Converters with outputs that each can have more than two voltage levels
H02M 7/539 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters with automatic control of output wave form or frequency
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
H05K 1/18 - Printed circuits structurally associated with non-printed electric components
A signal transmission device includes a primary side circuit that receives a primary side control signal from the external device, a secondary side circuit that drives a gate of the target transistor, and an insulation circuit that transmits a primary side control signal as a secondary side control signal to the secondary side circuit in an insulation form. The secondary side circuit is configured to control a gate voltage of the target transistor in accordance with the secondary side control signal so as to switch the target transistor between ON and OFF, and to be capable of adjusting a slew rate of change of the gate voltage of the target transistor in multiple steps. The secondary side circuit generates temperature information according to temperature of the target transistor, and compares the temperature information with reference information, so as to adjust the slew rate.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
H03K 17/0812 - Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit by measures taken in the control circuit
H03K 17/693 - Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
In a semiconductor device, a first receiving section and a first transmitting section are configured to through-output data for a first device included in reception data from a second output terminal when bridge selection data included in the reception data indicates an on state of a through-output in which bit data is output as is; a second transmitting section keeps a signal level of a first output terminal so that a signal of a first bus, which a first transmitting/receiving device uses to receive the reception data from a transmitting device, becomes recessive when the through-output is being performed.
Provided is a step-up DC/DC converter including an input line configured to allow an input power supply voltage to be applied thereto, an output line configured to allow an output voltage to be applied thereto, a coil connected between the input line and the output line, a load switch connected between the input line and the output line, and a semiconductor device. The semiconductor device includes a voltage monitoring circuit configured to output an abnormal voltage notification signal when a potential difference across the coil exceeds a threshold value, a control circuit configured to control the load switch, based on the abnormal voltage notification signal, and a current control circuit configured to control a current flowing through the coil so as to match the output voltage with a target value.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
In a semiconductor device, a first receiving section and a first transmitting section are configured such that when a bridge selection data included in a reception data indicates that a through-output between a first bus and a second bus is on, data for a first device included in the reception data is through-output from the first output terminal to the second bus; a clock signal output section is configured to output a clock signal synchronized with the through-output data; and a second receiving section is configured to receive an acknowledgment transmitted from the first device via the first input terminal in response to a reception of the through-output data.
Provided is a semiconductor device including an external terminal, an internal node, a control circuit configured to change an output according to a first voltage applied to the internal node, a current/voltage conversion element that is connected between the external terminal and the internal node, and a current generation circuit configured to flow a first current to the current/voltage conversion element such that a second voltage applied to the external terminal matches a predetermined third voltage.
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
61.
SEMICONDUCTOR COMPOSITE SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR COMPOSITE SUBSTRATE
This semiconductor composite substrate comprises: a substrate that contains silicon; a first buffer layer that is disposed on a main surface of the substrate and that is made of silicon nitride; and a monocrystalline layer that is disposed on the first buffer layer and that is made of a compound semiconductor.
A sensor element according to the present invention comprises a substrate and an insulating layer disposed on the substrate. The substrate has a cavity penetrating the substrate in the thickness direction formed therein. The insulating layer has a peripheral part disposed on the part of the substrate around the cavity, and a membrane part disposed on the cavity. In a portion of a peripheral part of the substrate positioned under said peripheral part, a groove is formed so as to extend from the cavity toward an outer periphery part of the substrate. It is possible, by having this configuration, to provide a sensor element for which a possibility of damage due to pressure changes is reduced.
G01N 27/18 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of an electrically-heated body in dependence upon change of temperature caused by changes in the thermal conductivity of a surrounding material to be tested
G01N 27/12 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon absorption of a fluidInvestigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of a solid body in dependence upon reaction with a fluid
63.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE ASSEMBLY
This semiconductor device comprises a support, a plurality of semiconductor elements mounted on the support, a plurality of first leads, and an encapsulating resin. The encapsulating resin covers each semiconductor element, a part of the support, and a part of each first lead. The support includes an insulating layer and a first metal layer. Each first lead has a bonding portion bonded to the first metal layer, and a first terminal portion protruding from the encapsulating resin. The first metal layer includes a non-conductive portion not electrically connected to any of the plurality of semiconductor elements. The plurality of first leads include first terminal leads having bonding portions bonded to the non-conductive portion.
Provided is a semiconductor device including a common terminal connected to an external capacitor outside of the semiconductor device, a function selection unit configured to execute a selection operation for outputting a selection signal for selecting a designated function according to an amount of charge accumulated in the external capacitor, and an internal power supply unit configured to supply a voltage to an internal circuit provided inside the semiconductor device, in which the external capacitor is electrically connected to the function selection unit when the selection operation is performed, and the external capacitor is electrically connected to the internal power supply unit and the internal circuit when a supply operation for supplying a supply voltage from the internal power supply unit to the internal circuit is performed.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 3/07 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode
In a target transistor, a first conductive electrode, a second conductive electrode, and a control electrode are respectively connected to first, second, and third wirings. The control circuit responds to an input control signal so as to supply a high side voltage or a low side voltage to the third wiring, thereby controlling the target transistor to be ON or OFF. If the low side voltage is lower than the voltage of the second wiring by a predetermined threshold voltage or more, an overvoltage signal in an asserted state is output. When the overvoltage signal in the asserted state is output, the control circuit supplies the low side voltage to the third wiring regardless of the input control signal, and a protection switching element, which is disposed between the second wiring and a fourth wiring applied with the low side voltage, is set to be ON.
A MEMS device includes a substrate having a front surface and a rear surface, a recess formed in the front surface of the substrate, and a movable electrode and a fixed electrode connected to the substrate and disposed in such a manner as to face each other in the air above the recess. The movable electrode includes an embedded oxide layer embedded in a trench formed in the movable layer. A manufacturing method of a MEMS device includes forming a trench by etching the front surface of the substrate, and forming the embedded oxide layer in the trench by oxidating side surfaces and bottom surface of the trench.
A power loss protection controller circuit for receiving an input voltage and supplying an output voltage to a load includes a bidirectional converter and a converter controller, wherein the bidirectional converter includes a bootstrap circuit, a high-side transistor, a low-side transistor, a high-side driver, a low-side driver, and a voltage maintenance circuit provided separately from the bootstrap circuit, and wherein the converter controller includes a feedback circuit, a logic circuit, and a high-side forced-on circuit.
H02J 9/06 - Circuit arrangements for emergency or stand-by power supply, e.g. for emergency lighting in which the distribution system is disconnected from the normal source and connected to a standby source with automatic change-over
H02M 3/155 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
A semiconductor device includes a chip that has a main surface, a high concentration region of a first conductivity type that is formed in a surface layer portion of the main surface on an inner portion side of the chip, and a low concentration region of the first conductivity type that is formed in the surface layer portion of the main surface on a peripheral edge portion side of the chip, and has an impurity concentration lower than an impurity concentration of the high concentration region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
69.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
A semiconductor device includes a chip that has a main surface, a drift region of a first conductivity type that is formed in a surface layer portion of the main surface, and a body region of a second conductivity type that is formed in a tapered shape in a surface layer portion of the drift region such that a width in a horizontal direction decreases in a thickness direction, and includes a peripheral edge portion inclined in an oblique direction with respect to the main surface.
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
70.
VDMOS HAVING A GATE ELECTRODE FORMED ON A GATE INSULATING FILM COMPRISING A THICK PORTION AND A THIN PORTION
A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.
H01L 21/02 - Manufacture or treatment of semiconductor devices or of parts thereof
H01L 21/04 - Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/13 - Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/62 - Electrodes ohmically coupled to a semiconductor
H10D 64/68 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
71.
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
The semiconductor device includes a chip that includes SiC and has a main surface, a gate electrode that is arranged on the main surface, includes polysilicon, and has an electrode surface, a silicide portion that is partially formed in a surface portion of the electrode surface, and a polysilicon portion that is formed in a portion of the surface portion of the electrode surface other than the silicide portion.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/66 - Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
A semiconductor device includes: a semiconductor chip having a principal surface, a drift region formed in the semiconductor chip, a drain region, body and a source region, a gate electrode facing a channel region formed in the body region through a gate insulating film, a plurality of insulating isolation structures embedded in a surface layer portion of the principal surface of the semiconductor chip along a first direction between the body region and the drain region, a first active area sandwiched between the adjacent insulating isolation structures in a second direction, and a gate field plate extending from the gate electrode to a region on the insulating isolation structure, wherein the gate insulating film includes a first portion formed on the channel region and a second portion integrally extending from the first portion toward the drain region, formed on the drift region, and having a second thickness larger than a first thickness of the first portion.
H10D 1/47 - Resistors having no potential barriers
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 64/00 - Electrodes of devices having potential barriers
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device includes a substrate, a conductive section, a sealing resin, and a conductive section wire. The substrate includes a substrate obverse face and a substrate reverse face oriented in opposite directions to each other in a thickness direction. The conductive section is formed of a conductive material and located on the substrate obverse face. The conductive section includes a first section and a second section spaced apart from each other. The sealing resin covers at least a part of the substrate and an entirety of the conductive section. The conductive section wire is conductively bonded to the first section and the second section of the conductive section.
H01L 23/538 - Arrangements for conducting electric current within the device in operation from one component to another the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
74.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes: a conductive portion; and a semiconductor element mounted on the conductive portion, wherein the conductive portion is made of a plating layer, wherein the conductive portion includes a mounting portion having a mounting surface on which the semiconductor element is mounted, and a terminal portion extending to an opposite side of the semiconductor element with respect to the mounting portion, wherein the mounting portion extends in a first direction along the mounting surface more than the terminal portion, and wherein the mounting portion and the terminal portion are integrally formed.
This semiconductor device manufacturing method comprises: a step for preparing a semiconductor module including a main substrate having a back surface that is exposed to the outside; and a step for bonding a main surface of a heat dissipation member and the back surface by diffusion bonding. The step for bonding by diffusion bonding of the manufacturing method includes a process for heating the main surface and the back surface from room temperature to a first temperature range. The manufacturing method comprises, after the step for preparing the semiconductor module and before the step for bonding by diffusion bonding: a step for heating the semiconductor module from room temperature to the first temperature range; and a step for flattening the back surface of the semiconductor module heated to the first temperature range.
A semiconductor device comprises a receiving section configured to receive reception data as serial data from an outside, a frame counter configured to count up a count value when it is determined that there is no anomaly based on the reception data, a register, and a transmitting section configured to transmit a first response data, including the count value from the frame counter read from the register, to an outside when Write/Read information included in the reception data indicates Write.
A semiconductor integrated circuit includes a test target circuit which is subjected to a scan test and configured to generate an output signal for controlling an operation of an analog circuit in response to an input signal, a test controller for controlling the scan test in the test target circuit, and a holder for holding the output signal. When the analog circuit is in an active state, the test controller executes the scan test on the test target circuit in response to a signal requesting execution of the scan test being transmitted to the semiconductor integrated circuit. While the scan test is being executed, the holder holds the output signal available after the signal is transmitted to the semiconductor integrated circuit and before the scan test begins, and outputs the held output signal so as to keep the analog circuit in the active state.
A gate driver circuit includes: a drive control circuit for receiving a pulse signal and upper and lower voltages, generate a drive signal which drives in a pulse manner between the upper and lower voltages at a period corresponding to the pulse signal, and input the drive signal to a gate of a switch element to be driven to drive and control the switch element; a reference voltage generation circuit for generating a reference voltage; and an upper voltage generation circuit for generating the upper voltage based on the reference voltage with reference to a source voltage generated at a source of the switch element according to a drain current of the switch element. The drive control circuit sets the drive signal to the upper voltage to turn on the switch element to be driven and sets the drive signal to the lower voltage to turn off the switch element.
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
H02M 3/156 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
A semiconductor device includes one and the other wiring groups that are arranged at an interval in a first direction X, the one and the other wiring groups each including first lower wirings and second lower wirings arrayed as stripes extending in the first direction X, a first pad wiring that is arranged over the one and the other wiring groups and is electrically connected to at least one of the first lower wirings of each of the wiring groups, and a second pad wiring that is arranged over the one and the other wiring groups at an interval from the first pad wiring in a second direction Y intersecting the first direction X and is electrically connected to at least one of the second lower wirings of each of the wiring groups.
H01L 23/535 - Arrangements for conducting electric current within the device in operation from one component to another including internal interconnections, e.g. cross-under constructions
H01L 23/00 - Details of semiconductor or other solid state devices
80.
SIC COMPOSITE SUBSTRATE, METHOD FOR MANUFACTURING SIC COMPOSITE SUBSTRATE, AND SEMICONDUCTOR DEVICE
This SiC composite substrate includes an SiC substrate and a polycrystalline SiC layer laminated on the top surface of the SiC substrate. The polycrystalline SiC layer is formed by alternately laminating a high concentration layer containing an impurity at a first doping amount and a low concentration layer containing an impurity at a second doping amount less than the first doping amount. The impurity of the high concentration layer and the impurity of the low concentration layer may both be nitrogen.
H01L 21/205 - Deposition of semiconductor materials on a substrate, e.g. epitaxial growth using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
B32B 9/00 - Layered products essentially comprising a particular substance not covered by groups
B32B 9/04 - Layered products essentially comprising a particular substance not covered by groups comprising such substance as the main or only constituent of a layer, next to another layer of a specific substance
C30B 25/20 - Epitaxial-layer growth characterised by the substrate the substrate being of the same materials as the epitaxial layer
This semiconductor device includes: a chip having a main surface; a first pillar region of a first conductivity type disposed in the chip and extending in a band shape along a first direction in plan view; and a second pillar region of a second conductivity type adjacent to the first pillar region in the chip and extending in a band shape along the first direction in plan view. The second pillar region includes a width-changing part where the width in a second direction crossing the first direction changes in plan view.
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
This semiconductor device comprises a plurality of mesa parts including first mesa parts each having a first width and second mesa parts having a second width in a direction crossing a trench in a chip, a second impurity region of a second conductivity type and a third impurity region of a first conductivity type formed in a surface layer part of a first impurity region in at least the first mesa parts, a control electrode facing the second impurity region via a control insulating film, a Schottky region provided at least in the second mesa part by the first impurity region, a first electrode forming a Schottky junction part between the first electrode and the Schottky region, and a second electrode ohmic-connected to the first impurity region.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
An electric power supply device (1) comprises: a test voltage determination unit (4) that is configured to generate a test voltage (Vt) on the basis of a voltage applied to an electric power supply terminal (T1), and is configured to determine that the test voltage indicates a test mode when the voltage applied to the electric power supply terminal is an overvoltage; a communication circuit (5) that is configured to be able to receive a communication input signal (Sin) by applying an overvoltage to an output terminal (T2); a non-volatile memory (7); and a program control unit (6) that is configured to write data relating to setting of an output voltage (Vout) included in the communication input signal to the non-volatile memory by a command from the communication circuit, on the basis of the determination result by the test voltage determination unit.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
A semiconductor device includes a semiconductor substrate, a semiconductor layer, a high voltage element region and a low voltage element region, and an isolation structure formed on an insulating film on the semiconductor layer. The isolation structure surrounds the high voltage element region to isolate the high voltage element region from the low voltage element region. An embedded layer is interposed between the semiconductor substrate and the semiconductor layer. In a plan view, the high voltage element region includes outer edges having linear sides and corners. The embedded layer has an overlap section where the embedded layer overlaps the high voltage element region, and outer edge sections that protrude from the outer edges. The outer edge sections include extending sections corresponding to the sides and curved sections corresponding to the corners. A width of each of the extending sections is greater than a width of each of the curved sections.
In a semiconductor device, when bridge selection data included in reception data indicates an on-state of a through-output in which bit data is output as is, data for a first device included in the reception data is through-output from a second output terminal; transmission data received by a second receiving section via a second input terminal during the through-output of the reception data is stored in a buffer; and the transmission data read from the buffer after the through-output of the reception data is output via a first output terminal by a second transmitting section.
A manufacturing method for a semiconductor device includes a preparation step of preparing a wafer that has a first surface on one side and a second surface on the other side, a first supporting step of supporting the wafer from the first surface side by a first member of a plate shape, a thinning step of thinning the wafer in a state where the wafer is supported by the first member, a second supporting step of supporting the wafer from a peripheral edge portion side of the second surface by a second member of a plate shape that exposes an inner portion of the second surface after the thinning step, and a removing step of removing the first member from the first surface side in a state where the wafer is supported by the second member.
H01L 21/683 - Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereofApparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components for supporting or gripping
H01L 21/304 - Mechanical treatment, e.g. grinding, polishing, cutting
H01L 21/66 - Testing or measuring during manufacture or treatment
H01L 21/78 - Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
87.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device includes a chip having a first main surface and a second main surface on the opposite side of the first main surface, and, within the chip, a semiconductor region provided in a surface layer part of the first main surface, and a device structure formed in a surface layer part of the semiconductor region. The semiconductor region includes a stacked structure formed by a first layer positioned on the second main surface side and made from a first semiconductor material being a wide bandgap semiconductor material, and a second layer positioned on the first main surface side and having an absorption coefficient higher than that of the first layer.
This semiconductor device comprises a semiconductor element, first rewiring, and a first sealing resin that covers a portion of the semiconductor element. The semiconductor element has a first electrode, a second electrode, and a control electrode. The first rewiring is electrically connected to the control electrode. The first sealing resin has a first surface and a second surface that face opposite directions along a first direction. The first electrode is exposed from the first surface. The second electrode is exposed from the second surface. The first sealing resin has a first opening that opens from the first surface. The first rewiring is housed in the first opening. The first opening includes a first cavity defined by the first rewiring and exposed from the first surface.
H01L 25/04 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
This terahertz device includes: a substrate including a substrate surface; an active element provided on the substrate surface and oscillating or detecting an electromagnetic wave; an antenna electrically connected to the active element; and a circuit member provided on the substrate surface and electrically connected to the antenna. The circuit member includes a curved part curved in a plan view viewed from a Z-axis direction perpendicular to the substrate surface.
H10D 89/00 - Aspects of integrated devices not covered by groups
H03B 7/08 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device being a tunnel diode
This semiconductor device comprises: a MIS transistor structure including a first impurity region of a first conductivity type in a surface layer portion of a main surface of a chip, a second impurity region of a second conductivity type, a third impurity region of the first conductivity type, and a gate structure facing a channel region in the second impurity region; a gate electrode film on an insulating layer on the main surface, the gate electrode film including a pad portion and a finger portion extending linearly from the pad portion and surrounding an active region; a main surface electrode film on the insulating layer in the active region and electrically connected to the third impurity region; and a main surface contact region of the second conductivity type, which is located on a portion of the surface layer portion of the second impurity region along the finger portion at the outer peripheral edge of the active region, electrically connected to the main surface electrode film, and has a higher impurity concentration than the second impurity region.
This semiconductor device comprises: a device structure which includes a plurality of conductive structures that are formed in an active region of an SiC chip; an insulating film which covers the conductive structures; and a main surface electrode which covers the conductive structures with the insulating film being interposed therebetween. The insulating film has a layered structure of a first insulating film and a second insulating film, and a first film thickness ratio of a first lateral film thickness, which is the film thickness of a portion that covers a first side wall of the conductive structure in the first insulating film, to a first upper film thickness, which is the film thickness of a portion that covers a first upper wall of the conductive structure in the first insulating film is different from a second film thickness ratio of a second lateral film thickness, which is the film thickness of a portion that covers the first side wall in the second insulating film, to a second upper film thickness, which is the film thickness of a portion that covers the first upper wall in the second insulating film.
This semiconductor device includes: a chip including a trench, a first impurity region, a second impurity region, and a third impurity region; a first embedded conductive layer embedded in the trench of the chip and facing the second impurity region; a trench insulating film between the inner surface of the trench and the first embedded conductive layer; a second embedded conductive layer forming a Schottky junction or a heterojunction with the first impurity region on the inner surface of the trench; a separation insulating film separating the first embedded conductive layer from the second embedded conductive layer; a first electrode electrically connected to the third impurity region and the second embedded conductive layer; and a second electrode electrically connected to the first impurity region.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A power supply control device includes: an output stage circuit having a high-side transistor provided between an application terminal of an input voltage and a switch terminal, and a low-side transistor provided between the switch terminal and a ground terminal; a high-side driver; a low-side driver; a switching control circuit for controlling on/off state of the high-side and low-side transistors using the low-side and high-side drivers; a boot terminal for applying a boot voltage; a rectifying element for supplying a charging current to a boot capacitor during an on period of the low-side transistor; a reverse current detection circuit for detecting a specific reverse current state in which a reverse current flows from an output terminal to which the output voltage is applied, toward the low-side transistor via the coil and the switch terminal; and a monitor circuit for monitoring a height of the boot voltage.
H02M 3/157 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
The semiconductor device includes an element support, first and second semiconductor elements on the element support, an insulating element insulating the first and the second semiconductor elements from each other, and an insulating substrate. The insulating element includes a first transceiver electrically connected to the first semiconductor element, a second transceiver electrically connected to the second semiconductor element, and an interfacing member for transmitting and receiving signals between the first and the second transceivers. The interfacing member is closer to the element support than the first and the second transceivers. The insulating substrate is between the element support and the insulating element and bonded to the element support. The insulating element is bonded to the insulating substrate.
H01L 23/00 - Details of semiconductor or other solid state devices
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
A semiconductor device includes a chip having a principal surface, a gate electrode formed on the principal surface, an interlayer film covering the gate electrode, an opening formed in the interlayer film such as to be separated from the gate electrode in a lateral direction along the principal surface and exposing a part of the chip as a contact portion, and a front surface electrode formed on the interlayer film and mechanically and electrically connected to the contact portion in the opening, wherein the contact portion includes a mesa contact portion that protrudes from the principal surface and has a mesa side portion and a mesa upper portion, and the front surface electrode covers the mesa side portion and the mesa upper portion.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
96.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR TESTING DEVICE
A semiconductor device manufacturing method including a reverse bias test for a device structure includes a step of applying a reverse bias voltage to the device structure, and a monitor step of monitoring a decrease rate of a leak current of the device structure at a time of applying the reverse bias voltage.
H01L 21/66 - Testing or measuring during manufacture or treatment
H10D 12/00 - Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
This nitride semiconductor device includes: a gate layer that is formed on an electron supply layer; a gate electrode that is formed on the gate layer; a passivation layer that covers the electron supply layer, the gate layer, and the gate electrode and has a first opening and a second opening that are separated in the X direction; and a field plate electrode that is formed on the passivation layer and is electrically connected to a source electrode. The field plate electrode includes a plate extension that extends to a region between the gate layer and a drain electrode in a plan view and opposes the electron supply layer with the passivation layer therebetween. An opening is formed in the plate extension of the field plate electrode.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 64/00 - Electrodes of devices having potential barriers
A successive approximation A/D converter includes a D/A converter that generates an analog output signal including an analog signal corresponding to a digital input, a comparator that outputs a comparison result between the analog signal and an analog input signal, and a control circuit that generates a digital input on the basis of the comparison result. The control circuit includes a reference register and a plurality of comparison registers each synchronized with the reference register. The reference register outputs a comparison signal obtained by capturing the comparison result. Each of the plurality of comparison registers corresponds to each bit from a most significant bit to a least significant bit, captures the comparison signal of a corresponding bit, and outputs a data signal indicating each bit from the most significant bit to the least significant bit.
H03M 1/46 - Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
99.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
A signal transmission device includes a first chip fed with an input pulse signal and a second chip that drives a switching device by generating an output pulse signal according to the input pulse signal through isolated communication with the first chip. The second chip includes a self-diagnosis circuit that checks whether individual parts of the second chip are operating properly in response to a self-diagnosis instruction transmitted from the first chip only when the output pulse signal is at a logic level corresponding to an off state.
A semiconductor device includes: a semiconductor chip including a single layer having a first principal surface and a second principal surface on an opposite side to the first principal surface; a first semiconductor region of a first conductivity type formed on the first principal surface side of the semiconductor chip; a second semiconductor region of a second conductivity type formed on the second principal surface side with respect to the first semiconductor region of the semiconductor chip; and a first trench structure including a first trench that penetrates the first semiconductor region from the first principal surface and partitions the first semiconductor region into a first region on one side and a second region on the other side in a cross-sectional view, a control insulating film that covers an inner wall of the first trench, and a control electrode that is embedded in the first trench with the control insulating film interposed therebetween and controls a channel in the second semiconductor region that makes the first region and the second region conductive in a lateral direction along the first principal surface.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
