A semiconductor device includes a chip having a main surface, a capacitor structure of a trench electrode type which is formed in the main surface and to which a first potential is to be applied, a dielectric film covering the capacitor structure on the main surface, and a pad electrode which is arranged on the dielectric film so as to form a capacitive coupling with the capacitor structure via the dielectric film, and to which a second potential different from the first potential is to be applied.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 1/68 - Capacitors having no potential barriers
A signal transmission device 200X comprises a transmission circuit, a reception circuit configured to output a drive control signal in accordance with a first internal signal and a second internal signal; an insulation circuit; and a driving circuit. The transmission circuit drives at least one of the first internal signal and the second internal signal at a specific period in accordance with an external signal. The reception circuit detects that the period of at least one of the first internal signal and the second internal signal is a specific period and outputs a drive control signal. The driving circuit receives the drive control signal, suspends driving of a driving target switch element, and puts an output node of the driving circuit in a high impedance state.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
3.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device includes a plurality of terminals, a semiconductor chip mounted on the plurality of terminals, and a sealing resin for sealing the plurality of terminals and the semiconductor chip. Each of the plurality of terminals includes: a rear surface, at least a part of which is exposed from the sealing resin; a front surface on which the semiconductor chip is mounted; a tip surface which is provided within the sealing resin and which is an end surface in a first direction orthogonal to the Z direction; and a projecting portion which is positioned at an intermediate portion in the Z direction on the tip surface.
A semiconductor device includes a chip having a principal surface, a first conductivity type drift region formed at a surface layer portion of the principal surface, a trench electrode type gate structure formed on the principal surface such as to be placed in the drift region, and a second conductivity type well region formed along a bottom wall of the gate structure in a region below the gate structure in the drift region, wherein the well region includes a plurality of first well regions each of which is a first well region having a first bottom portion having a first depth and which are formed at an interval of a first interval from each other in a depth direction of the gate structure, and the first well regions adjacent each other face each other in the depth direction of the gate structure across a portion of the drift region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A semiconductor device includes a chip having a main surface, an active region provided in the main surface, a pad region provided outside the active region in the main surface, a transistor structure formed in the main surface in the active region, and a capacitor structure of a trench electrode type that is formed in the main surface in the pad region and forms capacitive coupling with the chip.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 1/66 - Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
A semiconductor device includes: a semiconductor element; a plurality of leads; and a sealing resin, wherein the leads each include a body and a metal layer covering at least a portion of the body, wherein at least one of the leads includes a covered portion and an exposed portion, respectively covered with and exposed from the sealing resin, wherein the body in the exposed portion includes a bottom surface facing a first side in a thickness direction of the semiconductor element, an end surface with a tip facing a first direction intersecting the thickness direction, and a concave surface between the bottom and end surfaces, wherein the concave surface occupies only a portion of the body in a second direction intersecting the thickness direction and the first direction, and wherein the metal layer includes a bottom surface portion and a concave surface portion covering the bottom and concave surfaces respectively.
ABNORMAL VOLTAGE PROTECTION CIRCUIT, SIGNAL TRANSMISSION DEVICE COMPRISING ABNORMAL VOLTAGE PROTECTION CIRCUIT, ELECTRONIC EQUIPMENT COMPRISING SIGNAL TRANSMISSION DEVICE, AND VEHICLE COMPRISING ELECTRONIC EQUIPMENT
An abnormal voltage protection circuit 502 includes a voltage-current conversion circuit 507, 511, a current-voltage conversion circuit, and an abnormal voltage detection circuit C3, C4. The voltage-current conversion circuit 507, 511 is configured to convert a monitor target voltage VEE2 that is negative with respect to a reference voltage into a current signal I1, I3. The current-voltage conversion circuit is configured to convert the current signal I1, I3 into a voltage signal V7, V11 that is positive with respect to the reference voltage. The abnormal voltage detection circuit C3, C4 is configured to compare the voltage signal V7, V11 with a threshold value voltage V8, V12, so as to be able to detect the monitor target voltage VEE2 is an upper limit voltage V8 or higher, or a lower limit voltage V12 or lower.
H02H 3/20 - Emergency protective circuit arrangements for automatic disconnection directly responsive to an undesired change from normal electric working condition, with or without subsequent reconnection responsive to excess voltage
A semiconductor device includes: one or more leads; one or more semiconductor elements disposed on a first side in a thickness direction with respect to the one or more leads; a plurality of wires each of which is electrically connected to at least one of the one or more leads and the one or more semiconductor elements; and a sealing resin that covers the one or more semiconductor elements, the plurality of wires, and at least a portion of the one or more leads. The plurality of wires include a first wire and a second wire. The second wire is curved in a convex shape toward the first wire as viewed in the thickness direction. The second wire extends across the first wire as viewed in the thickness direction and is spaced apart from the first wire in the thickness direction.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A semiconductor device includes a semiconductor element and a conductive support member. The conductive support member includes a plurality of external terminals including a first external terminal and a second external terminal. The semiconductor element includes a plurality of pads including a first pad in a conductive state with the first external terminal and a second pad in a conductive state with the second external terminal. The semiconductor device further includes a capacitor mounted on the semiconductor element in a conductive state with the first pad.
A semiconductor device includes a GaN power device of which the gate breakdown voltage has a positive temperature response, a voltage supplying portion that supplies, when the GaN power device is turned on, a voltage at a high level with a positive temperature response to the gate of the GaN power device, and a heat conducting portion that conducts heat between the GaN power device and the voltage supplying portion.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
An overvoltage protection element of the present invention comprises a semiconductor substrate having: a first groove and a second groove formed on a first main surface; a first well region that is of a first conductivity type and is embedded so as to surround the first groove; and a second well region that is of a second conductivity type and is embedded so as to surround the second groove. The overvoltage protection element further comprises: a first diffusion region that is of the second conductivity type and is embedded in an upper part of the first well region while contacting a side surface of the first groove; a second diffusion region that is of the first conductivity type and is embedded in an upper surface, of the first well region, located at a bottom surface of the first groove; a third diffusion region that is of the first conductivity type and is embedded in an upper part of the second well region while contacting a side surface of the second groove; and a fourth diffusion region that is of the second conductivity type and is embedded in an upper surface, of the second well region, located at a bottom surface of the second groove.
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 89/60 - Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
A semiconductor device includes: terminals that include a terminal obverse surface and a terminal reverse surface; a semiconductor chip that is mounted on the terminals; and an encapsulating resin for encapsulating the terminals and the semiconductor chip. The terminals include: a terminal portion that includes a terminal portion reverse surface, which is exposed from the encapsulating resin on the terminal reverse surface; a mounting portion that extends from the terminal portion in a first direction orthogonal to a Z direction, which is the thickness direction of the terminal, and has the semiconductor chip mounted thereon; a groove portion that is provided at least in the mounting portion and extends in the first direction; and wall portions that are positioned at both ends in a second direction orthogonal to both the Z direction and the first direction by the groove portion and extend in the first direction.
A semiconductor device includes a chip having a principal surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the principal surface, and a device structure having a source structure formed in the semiconductor region at an inner portion of the principal surface. A peripheral edge source electrode portion having a first outer edge is arranged on a peripheral edge portion of the principal surface and electrically connected to the source structure. A terminal region of a second conductivity type is formed in the semiconductor region at the peripheral edge portion and electrically connected to the peripheral edge source electrode portion. The terminal region includes a second outer edge positioned closer to a peripheral edge of the principal surface than the first outer edge, wherein a distance between the first and second outer edges is not less than 10 μm.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A semiconductor device includes an electrically insulating substrate including a substrate main surface and a substrate back surface facing opposite to each other in a thickness direction and at least one substrate side surface facing a direction intersecting the thickness direction, a semiconductor element arranged at a side of the substrate main surface, a heat-dissipating conductive portion that is provided at a position overlapping with at least a portion of the semiconductor element when viewed from the thickness direction and is exposed from the substrate back surface, a sealing resin that seals the semiconductor element while covering the substrate main surface, and at least one wiring portion that is connected to the heat-dissipating conductive portion, extends from the heat-dissipating conductive portion to the substrate side surface while being exposed from the substrate back surface, and is exposed from the substrate side surface.
A semiconductor device includes a lead with a pad portion having a mount surface facing in a thickness direction, a semiconductor element on the mount surface, a wire bonded to the semiconductor element and the mount surface, and a sealing resin covering the semiconductor element, the wire, and a part of the pad portion. The wire includes a first bonding portion bonded to the semiconductor element and a second bonding portion bonded to the mount surface. The wire is provided with a protrusion overlapping the second bonding portion and being covered by the sealing resin. The pad portion is formed with a hole disposed closer to the second bonding portion than to the first bonding portion. The hole extends to penetrate through the pad portion in the thickness direction. A part of the sealing resin is disposed in the hole.
The semiconductor module includes a first device that has an IGBT and a second device that has a reflux diode which is anti-parallel connected to the IGBT, which has a forward threshold voltage less than a reverse withstand voltage of the IGBT, and which has a forward breakdown voltage in excess of the reverse withstand voltage of the IGBT.
A semiconductor device includes a chip having a main surface, an active region provided in the main surface, a pad region provided outside the active region in the main surface, a transistor structure of an insulated gate type formed in the main surface in the active region, a capacitor structure of a trench electrode type that is formed in the main surface in the pad region and forms capacitive coupling with the chip, and a pad electrode that is arranged on the main surface in the pad region and is electrically connected to the capacitor structure.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
Ancora Semiconductors Inc. (Taiwan, Province of China)
Inventor
Fujimaki, Takumi
Nate, Satoru
Liu, Ying-Chen
Chao, Wei-Hsiang
Abstract
A semiconductor device includes: a resistor; a gallium nitride (GaN) power element; and a drive circuit configured to drive the GaN power element based on a pulse voltage, wherein the drive circuit includes a Schmitt trigger circuit, a high-side switch, and a low-side switch, wherein the pulse voltage is applied to a first end of the resistor, wherein a second end of the resistor is connected to an input terminal of the Schmitt trigger circuit and a first terminal of the high-side switch, wherein a second terminal of the high-side switch is connected to a first terminal of the low-side switch, and wherein each of the high-side switch and the low-side switch is switch-controlled based on an output of the Schmitt trigger circuit.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/08 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Ancora Semiconductors Inc. (Taiwan, Province of China)
Inventor
Fujimaki, Takumi
Nate, Satoru
Liu, Ying-Chen
Chao, Wei-Hsiang
Abstract
A semiconductor device includes: a GaN power element configured to include a gate, a drain and a source; a drive circuit configured to drive the GaN power element; and a monitoring circuit configured to monitor a voltage between the drain and the source of the GaN power element. The drive circuit is configured to turn off the GaN power element based on an output of the monitoring circuit. The monitoring circuit includes a diode a cathode of which is connected to the drain of the GaN power element. The drive circuit is mounted on a Si chip. The GaN power element and the diode are mounted on a GaN chip.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
1011011010(cm-311(x) is the concentration of the first transition region at a depth x, and x is the depth from the main surface of the epitaxial layer.)
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
The control device includes a control block configured to generate, on a basis of feedback signals derived from an actuator, control output signals intended for control of the actuator, and an anomaly detection block configured to detect an anomaly on a basis of intermediate arithmetic data which are generated by computation in a generation process of the control output signals according to the feedback signals in the control block.
A signal transmission device comprises: an insulation element for performing signal transmission between a primary circuit system and a secondary circuit system while providing insulation therebetween; a self-diagnosis circuit which is provided in the secondary circuit system and performs self-diagnosis of the secondary circuit system; a storage circuit which is provided in the secondary circuit system and in which memory access is permitted after completion of the self-diagnosis; and a transmission circuit which is provided in the secondary circuit system and outputs a transmission pulse signal to the insulation element. The transmission circuit generates one pulse or a group of a plurality of pulses in the transmission pulse signal at the completion timing of each of the self-diagnosis and the memory access and continues generating pulses at the period of a first time in the transmission pulse signal when an abnormality in the memory access is being detected.
H03K 17/691 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit using transformer coupling
A rectifier includes a first transistor of a drain/source common field effect type and a second transistor of a drain/source common field effect type in which the second transistor is diode-connected to the first transistor so as to allow the first transistor to perform a diode operation, and configures a rectifier stage with the first transistor.
H02M 7/217 - Conversion of AC power input into DC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
H10D 84/83 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
A semiconductor device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a resistor embedded in the insulating layer and formed by electrically connecting a plurality of resistance layers, a first electrode connected electrically to a first end of the resistor, a second electrode connected electrically to a second end of the resistor, and a plurality of first dummy wiring lines arranged around the first electrode and respectively coupled capacitively to the plurality of resistance layers in the resistor.
H10D 1/47 - Resistors having no potential barriers
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
H10D 80/30 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising integrated circuit processor chips
A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
This semiconductor device comprises: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; an inorganic insulating film covering the metal electrode; and an organic insulating film covering the metal electrode with the inorganic insulating film interposed therebetween. The metal electrode has a pad electrode. The organic insulating film has a first organic opening exposing the pad electrode as a first pad and a second organic opening exposing the pad electrode as a second pad. The inorganic insulating film includes a first pad inorganic film having a first inorganic opening exposing the first pad and a second pad inorganic film having a second inorganic opening exposing the second pad. The first pad inorganic film and the second pad inorganic film are separated from each other and are not mechanically connected to each other.
This semiconductor device includes: a chip having a main surface; a device structure formed on the main surface; a metal electrode covering the main surface; and an inorganic insulating film covering the metal electrode. The inorganic insulating film has a first film thickness larger than a second film thickness of the metal electrode.
An electronic component includes an insulating layer that has a principal surface, a passive device that includes a low voltage pattern that is formed in the insulating layer and a high voltage pattern that is formed in the insulating layer such as to oppose the low voltage pattern in a normal direction to the principal surface and to which a voltage exceeding a voltage to be applied to the low voltage pattern is to be applied, and a shield conductor layer that is formed in the insulating layer such as to be positioned in a periphery of the high voltage pattern in plan view, shields an electric field formed between the low voltage pattern and the high voltage pattern, and suppresses electric field concentration with respect to the high voltage pattern.
A thermal print head includes a substrate, a first insulating film, and a second insulating film. The substrate has a first main surface and a second main surface opposite to the first main surface. A protruding portion protruding toward a side opposite to the second main surface is formed at the first main surface. A recessed portion is formed in a surface of the protruding portion. The first insulating film is disposed on the first main surface to cover the protruding portion. The second insulating film is disposed on the surface with the first insulating film interposed therebetween. A through hole is formed in a portion of the first insulating film that faces a bottom surface of the recessed portion with a space interposed therebetween.
B41J 2/345 - Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of heat to a heat sensitive printing or impression-transfer material using thermal heads characterised by the arrangement of resistors or conductors
This monitoring device monitors a comparison result between a first transfer amount, which is a transfer amount of data when data is read from a transfer source area of a memory under control of a direct memory access (DMA) control device, and a second transfer amount, which is a transfer amount of data when the data read from the transfer source area is written to a transfer destination area of the memory under control of the DMA control device.
G06F 13/28 - Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access, cycle steal
31.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
This semiconductor device includes: a chip formed of a wide bandgap semiconductor, the chip having a main surface in which a semiconductor region of a first conductive type is formed; a base impurity region of a second conductive type formed in a surface layer part of the semiconductor region; a first impurity region of the first conductive type formed in a surface layer part of the base impurity region; and a second impurity region of the second conductive type formed in the surface layer part of the base impurity region, the second impurity region of the second conductive type being adjacent to the first impurity region in a first direction. The base impurity region includes an exposure part which is a region exposed to the main surface, where the exposure part extends in a belt shape in the first direction so as to cross the base impurity region in the first direction, and divides the first impurity region in a second direction orthogonal to the first direction.
A gate driver circuit, which drives a switching circuit including a high-side transistor and a low-side transistor, includes: a bootstrap terminal connected to a capacitor; a high-side gate terminal connected to a gate of the high-side transistor; a low-side gate terminal connected to a gate of the low-side transistor; a switching terminal connected to an output of the switching circuit; a bootstrap switch connected to the bootstrap terminal; a high-side driver including power supply terminals connected to the terminals and generating a high-side gate voltage in response to a high-side control signal; a low-side driver which generates a low-side gate voltage in response to a low-side control signal; a sensor which asserts a detection signal when the high-side transistor or the low-side transistor is electrically changed; and a control circuit which generates the high-side and low-side control signals and turns on the bootstrap switch in response to the detection signal.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02P 27/06 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using DC to AC converters or inverters
An insulated switch includes: a switch circuit connected between a first node and a second node and configured to be turned on and off by a switch drive signal; a pulse generation circuit configured to generate a first drive pulse and a second drive pulse in different phases; a switch drive circuit configured to receive a third drive pulse and a fourth drive pulse to generate the switch drive signal; and a first insulation capacitor and a second insulation capacitor configured to transmit the first drive pulse and the second drive pulse as the third drive pulse and the fourth drive pulse, respectively, while insulating the pulse generation circuit and the switch drive circuit from each other.
H03K 17/689 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors with galvanic isolation between the control circuit and the output circuit
H03K 17/74 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of diodes
34.
SEMICONDUCTOR DEVICE, POWER SUPPLY SYSTEM, AND VEHICLE
A semiconductor device includes: a multi-channel power supply circuit; a first input terminal configured to receive an enable signal; and a controller configured to control a first power supply circuit included in the multi-channel power supply circuit to start up and shut down in accordance with the enable signal, and to control a second power supply circuit included in the multi-channel power supply circuit to maintain an output-on state after startup irrespective of the enable signal.
B60R 16/03 - Electric or fluid circuits specially adapted for vehicles and not otherwise provided forArrangement of elements of electric or fluid circuits specially adapted for vehicles and not otherwise provided for electric for supply of electrical power to vehicle subsystems
A plurality of high-side driver units correspond to a plurality of high-side transistors. A first output sensor asserts a first output detection signal when an output voltage crosses a predetermined first threshold voltage. A timer circuit measures a timing of assertion of the first output detection signal. Each of the plurality of high-side driver units has an adjustable drive strength. A control circuit adjusts the drive strength of each of the high-side driver units such that the timings of assertion of the first output detection signal are aligned when each of the high-side driver units is operated individually.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
H02P 27/00 - Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
An input stage includes a differential pair and an active load. An output stage includes an output transistor that receives an output signal of the input stage. A phase-compensation circuit supplies a feedback current to the active load in accordance with an output voltage. An offset-cancellation circuit supplies a correction current to the active load in accordance with an input voltage of an operational amplifier.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
37.
ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE
An electronic device includes a first member with a first obverse surface, an electronic element on the first member, a connecting member connected to the electronic element, a second member with a second reverse surface, and a sealing resin covering the first member, the second member, the electronic element, and the connecting member. The second member includes a terminal portion and a connecting portion connected to the connecting member. The first obverse surface includes a first flat portion and a first projecting portion. The first projecting portion projects to the first side in the thickness direction relative to the first flat portion. The second reverse surface includes a second flat portion and a second projecting portion. The second projecting portion projects to the second side in the thickness direction relative to the second flat portion.
A semiconductor device includes at least one terminal, and the terminal includes a cylindrical holder having electrical conductivity and a metal pin inserted in the holder. The semiconductor device further includes a terminal support supporting the holder, and a sealing resin covering a part of the holder and covering the terminal support. The sealing resin includes a resin obverse surface facing a first side in a thickness direction. The holder includes a first surface located at one end on the first side in the thickness direction and a first outer side surface extending in the thickness direction. The first surface is located at a position different from the resin obverse surface in the thickness direction. The first outer side surface is in contact with the sealing resin. The metal pin protrudes beyond the resin obverse surface toward the first side in the thickness direction.
A semiconductor device includes a plurality of semiconductor elements, each of which has a first electrode, a second electrode, and a third electrode, and is subjected to an ON-OFF control between the first electrode and the second electrode in accordance with a driving signal input to the third electrode. Further, the semiconductor device includes a control terminal to which the driving signal is input, a first wiring portion to which the control terminal is connected, a second wiring portion separated from the first wiring portion, a first connection member to conduct the first wiring portion and the second wiring portion, and a second connection member to conduct the second wiring portion and the third electrode of one of the plurality of semiconductor elements. The respective first electrodes of the plurality of semiconductor elements are electrically connected to one another, and respective second electrodes of the plurality of semiconductor elements are electrically connected to one another.
A controller circuit of a DC/DC converter, which generates an output voltage according to an input voltage, includes: a pulse width modulation (PWM) comparator configured to compare a periodic ramp voltage with a comparison voltage; and a voltage supply circuit configured to supply an initial voltage of the comparison voltage to the PWM comparator, wherein the initial voltage is a voltage corresponding to a ratio between the input voltage and the output voltage.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes: a first lead having a first surface facing one side in a thickness direction; a semiconductor element mounted on the first surface and including a plurality of electrodes; one or more second leads electrically connected to the semiconductor element; a sealing resin configured to cover the semiconductor element and at least a portion of each of the first lead and the one or more second leads; one or more conductors; first wires connected to the electrodes and the conductors; and second wires connected to the second leads, wherein a conductive path between the electrodes and the second leads includes the first wires, the conductors, and the second wires.
Disclosed herein is a semiconductor device including a plurality of first external terminals configured such that a voltage signal as a detection target is applicable thereto, a first amplifier or a first comparator, a plurality of first internal wires each having a first end connected to a respective one of the plurality of first external terminals, a second internal wire having a first end connected to a first input terminal of the first amplifier or the first comparator, and a first switch configured to select one second end to be connected to a second end of the second internal wire from among the second ends of the plurality of first internal wires.
A video freeze detection circuit has a frame memory that stores and outputs video data constituted of a plurality of consecutive data pieces. The video freeze detection circuit includes a bit substitution circuit that receives the video data, substitutes data values of particular bits of the plurality of data pieces with “0” and “1” alternately for each frame to which the data piece belongs, and then supplies the video data to the frame memory so that the plurality of data pieces are stored therein. The video freeze detection circuit further includes a data holding unit that holds data of the particular bits of the video data outputted from the frame memory, and a comparison unit compares a data value of the particular bit in the video data for one frame outputted from the frame memory with a data value of the particular bit held in the data holding unit.
Provided is an abnormality detecting method using a computing device, one cluster of data in a case where data is sequentially supplied to a machine learning model being referred to as a chunk. The abnormality detecting method includes obtaining a learning result by performing unsupervised learning by the machine learning model with a predetermined chunk width on a basis of first data, obtaining an inference result by performing inference by the machine learning model with the chunk width on a basis of second data and the learning result, and calculating an interval abnormality degree for each interval obtained by dividing the chunk width into a plurality of intervals on a basis of the second data and the inference result.
G05B 19/418 - Total factory control, i.e. centrally controlling a plurality of machines, e.g. direct or distributed numerical control [DNC], flexible manufacturing systems [FMS], integrated manufacturing systems [IMS] or computer integrated manufacturing [CIM]
G06N 3/088 - Non-supervised learning, e.g. competitive learning
A voltage control circuit includes a voltage-controlled oscillator including an odd number of inverter elements connected in a loop. Each inverter element operates by an operating current corresponding to a control voltage. The voltage-controlled oscillator outputs an output from one of the odd number of inverter elements as the oscillation signal. The voltage control circuit further includes a threshold detection circuit including a first transistor in a diode connection, and a first resistor having a first end connected to a drain of the first transistor and a second end that has applied thereto a prescribed voltage. The threshold detection circuit detects a voltage of the drain of the first transistor as a threshold voltage of the first transistor. The voltage-controlled oscillator includes an operating current adjustment circuit that adjusts the operating current up or down if the threshold voltage is outside of a prescribed allowable voltage range.
H03L 7/099 - Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
H03L 7/085 - Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
An input stage includes a differential pair and an active load. An output stage includes an output transistor coupled to receive an output signal of the input stage. An output variation detection circuit is connected to an output terminal of an operational amplifier and generates a first current corresponding to an output voltage generated at the output terminal. A phase compensation circuit supplies, to the output terminal, a second current corresponding to a gate voltage of the output transistor, and supplies, to the active load, a third current corresponding to the second current.
G05F 1/56 - Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
A terahertz device includes: a support substrate; a terahertz element that is mounted to the support substrate and that emits an electromagnetic wave in a terahertz band; and a reflection body that is disposed on the opposite side to an element rear surface with respect to an element main surface in a z direction and at an interval in the z direction from the element main surface and that has a reflection surface for reflecting, in a direction crossing the z direction, an electromagnetic wave emitted in the z direction by the terahertz element.
H01Q 19/13 - Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using reflecting surfaces wherein the surfaces are concave the primary radiating source being a single radiating element, e.g. a dipole, a slot, a waveguide termination
H01Q 19/15 - Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using reflecting surfaces wherein the surfaces are concave the primary radiating source being a line source, e.g. leaky waveguide antennas
H03B 7/08 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device being a tunnel diode
A package for a gas sensor has: a substrate on which a semiconductor chip is mounted; and a side surface section and an upper surface section that are integrated. The side surface section includes a first side surface section and a second side surface section that are disposed so as to face each other with a gap therebetween in one direction. The first side surface section is positioned on the upstream side with respect to the flow of a gas, and the second side surface section is positioned on the downstream side. A slit-like first opening is formed at a corner section where the first side surface section and the upper surface section are connected. A slit-like second opening is formed in the upper surface section.
G01N 27/18 - Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating impedance by investigating resistance of an electrically-heated body in dependence upon change of temperature caused by changes in the thermal conductivity of a surrounding material to be tested
This terahertz device (A1) comprises a terahertz element (20), a support substrate (30), and a waveguide (10). The terahertz element (20) is configured to emit terahertz waves from an oscillation point (P1) on a first element surface (21). The waveguide (10) has a transmission region (18) for transmitting terahertz waves. The support substrate (30) supports the terahertz element (20) and includes a disposition region (37) disposed in the transmission region (18). The terahertz element (20) is disposed in the waveguide (10) such that the oscillation point (P1) is located in the disposition region (37). The transmission region (18) includes a first opening (11A) communicating with the outside of the waveguide (10), a first transmission region (18A) extending from the first element surface (21) toward the first opening (11A), a second opening (12A) communicating with the outside of the waveguide (10), and a second transmission region (18B) extending from the first element surface (21) toward the second opening (12A).
H01P 5/08 - Coupling devices of the waveguide type for linking lines or devices of different kinds
H03B 7/14 - Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising distributed inductance and capacitance active element being semiconductor device
This semiconductor device includes: an SiC substrate; an SiC epitaxial layer of a first conductivity type laminated on the SiC substrate; a vertical element structure which is formed in a surface layer part of a main surface of the SiC epitaxial layer and in which a current flows in a vertical direction that is a lamination direction of the SiC substrate and the SiC epitaxial layer; a diode formed by a junction between a first impurity region of a second conductivity type which is a part of the element structure and the SiC epitaxial layer; and a first carrier inhibition part formed in the surface layer part of the main surface of the SiC epitaxial layer and composed of crystal defects formed by a distribution of carrier lifetime killers. The first carrier inhibition part is selectively distributed in a partial region of the SiC epitaxial layer.
A semiconductor device includes a base impurity region of a second conductivity type formed in a surface layer portion of a semiconductor region of a first conductivity type and having a band shape that is long in a first direction, a first impurity region formed in a surface layer portion of the base impurity region, a gate electrode formed in a band shape that is long in the first direction and facing a channel region of the base impurity region via a gate insulating film, a Schottky region formed by a portion of the semiconductor region and dividing the base impurity region into a plurality of unit cells in a second direction intersecting the first direction, and a principal surface electrode that is in Schottky junction with the Schottky region.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
A semiconductor device includes a semiconductor element including a surface electrode formed on the element surface thereof. The element surface includes an active region in which power transistors are formed, and a control circuit region in which a control circuit for controlling the power transistors is formed. The active region is formed so as to surround the control circuit region from both sides in a second direction and one side in a first direction. The surface electrode is disposed on the active region at a position different from the control circuit region, and is formed so as to surround the control circuit region from both sides in the second direction and one side in the first direction when viewed from the thickness direction thereof.
A semiconductor device includes a first terminal, a second terminal, a third terminal, a fourth terminal, a first lead, a second lead, a semiconductor element, and a sealing resin. A dimension of a first exposed surface of the first lead is greater than a dimension of a first mounting surface of the first terminal. A dimension of a second exposed surface of the second lead is greater than a dimension of a second mounting surface of the second terminal. As viewed in a third direction that is the normal to the bottom surface of the sealing resin, a first end of the first exposed surface and a third end of the second exposed surface are positioned inward of a perimeter of the sealing resin. As viewed in the third direction, a fourth end of the second exposed surface overlaps with the perimeter of the sealing resin.
An electronic device which can suppress peeling off and damaging of the bonding material is provided. The electronic device includes an electronic component, a mounting portion, and a bonding material. The electronic component has an element front surface and an element back surface separated in the z-direction. The mounting portion has a mounting surface opposed to the element back surface on which the electronic component is mounted. The bonding material bonds the electronic component to the mounting portion. The bonding material includes a base portion and a fillet portion. The base portion is held between the electronic component and the mounting portion in the z-direction. The fillet portion is connected to the base portion and is formed outside the electronic component when seen in the z-direction. The electronic component includes two element lateral surface and ridges. The ridges are intersections of the two element lateral surface and extend in the z-direction. The fillet portion includes a ridge cover portion which covers at least a part of the ridges.
In the present invention, a plurality of trenches are recessed from a first substrate surface toward a second substrate surface. A dielectric layer covers the first substrate surface and the inner surfaces of the plurality of trenches. A first conductive layer is provided on the dielectric layer. A first external electrode is provided so as to cover a portion of the first conductive layer. A second external electrode is disposed apart from the first external electrode when viewed from the Z-axis direction, and is in contact with the first substrate surface. A second conductive layer is provided on the second substrate surface. The dielectric layer includes a plurality of inner surface dielectric layers provided on the inner surfaces of the plurality of trenches. The first conductive layer includes a plurality of internal electrodes provided so as to fill at least a part of an internal region surrounded by the plurality of inner surface dielectric layers. A semiconductor substrate and the plurality of internal electrodes face each other with the plurality of inner surface dielectric layers interposed therebetween, and thereby constitute a capacitor.
This insulation module is provided with: a first conductor and a second conductor, which are buried in an insulating layer so as to face each other at a distance in the thickness direction of the insulating layer; a first electrode which is connected to the first conductor; a second electrode which is connected to the second conductor, while being arranged at a position that is away from the first electrode when viewed from the thickness direction of the insulating layer; a passivation layer which is formed on the surface of the insulating layer; a low dielectric constant layer which is formed on the surface of the passivation layer, and has a lower dielectric constant than the passivation layer; and a mold resin which covers the low dielectric constant layer.
H10D 86/85 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.
A semiconductor device includes a support, a first semiconductor element supported on the support, and a first bonding sheet interposed between the support and the first semiconductor element. The first bonding sheet includes a first portion and a second portion. The first portion includes a part that overlaps with the first semiconductor element as viewed in the thickness direction of the support. The second portion includes a part that does not overlap with the first semiconductor element as viewed in the thickness direction. The second portion is smaller in thickness in the thickness direction than the first portion.
H10D 80/20 - Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups , e.g. assemblies comprising capacitors, power FETs or Schottky diodes
A method for manufacturing a semiconductor device includes a first step, a second step third step, and a fourth step. In the third step, a pad portion is exposed from a bottom surface of a sealing resin. In the third step, a dimension of the sealing resin in a first direction extending from the bottom surface to a second surface of a first support portion is made smaller than a dimension of the sealing resin in the first direction extending from a top surface of the sealing resin to a first surface of the first support portion. In the fourth step, the first support portion is cut by applying a compressive force to the top surface while the second surface is supported by a supporting member. In the fourth step, a first end surface, which faces one side in a second direction and is exposed from the sealing resin, is formed in the first support portion.
A semiconductor device includes a first lead, a semiconductor element, and a sealing resin. The first lead includes a pad portion and a first support part. The first support part has a first surface, a second surface, and a first end surface. The pad portion is exposed from the bottom surface of the sealing resin. The dimension of the sealing resin in the first direction from the bottom surface to the second surface is smaller than the dimension of the sealing resin in the first direction from the top surface to the first surface. The dimension of the second surface in the second direction is at least 50% of a dimension in the second direction of a region of the bottom surface that is adjacent, on one side in the second direction, to the pad portion and overlaps with the second surface as viewed in the first direction.
A semiconductor device includes a CPU, a cache memory, and multiple memories. Each of the multiple memories is switchable between being connected to the CPU through the cache memory and being connected to the CPU without going through the cache memory.
A method for manufacturing an SiC semiconductor device includes a step of setting, on a main surface of an SiC wafer, a scheduled cutting line that demarcates a plurality of chip regions including a first chip region in which a functional device is formed and a second chip region in which a monitor pattern for performing process control of the first chip region is formed, a step of forming, on the main surface, a plurality of main surface electrodes respectively covering the chip regions such as to expose the scheduled cutting line and respectively forming a portion of the functional device and a portion of the monitor pattern, a step of irradiating laser light to the scheduled cutting line and forming a modified region, and a step of cleaving the SiC wafer with the modified region as a starting point.
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A monitoring circuit includes first and second oscillators, first and second frequency dividers, first and second counters, a determination portion, and an identification portion. The first and second frequency dividers respectively divide frequencies of first and second clock signals outputted from the first and second oscillators, respectively. The first and second counters respectively count the numbers of clocks of the second and first clock signals at first and second numbers of periods of first and second frequency-divided signals outputted from the first and second frequency dividers, respectively. The determination portion determines, based on results of counting by the first and second counters, whether or not an abnormality has occurred in either of the first and second clock signals. The identification portion identifies, at the occurrence of an abnormality in either of the first and second clock signals, which of the first and second clock signals is in an abnormal state.
G01R 31/28 - Testing of electronic circuits, e.g. by signal tracer
G01R 31/00 - Arrangements for testing electric propertiesArrangements for locating electric faultsArrangements for electrical testing characterised by what is being tested not provided for elsewhere
G06F 1/06 - Clock generators producing several clock signals
A pressure sensor, including: a substrate having first and second main surfaces opposite to each other; a first chamber recessed from the first main surface into the substrate; a second chamber recessed from the first main surface into the substrate and adjacent to the first chamber in a lateral direction orthogonal to a thickness direction; a fluid passage recessed from the first main surface into the substrate and configured to place the first chamber in fluid communication with an outside; a cover structure disposed on the first main surface and closing openings of at least the first chamber and the second chamber at the first main surface; and at least one membrane partitioned by the first chamber and the second chamber in the substrate between the first chamber and the second chamber in the lateral direction, the at least one membrane extending in a plane that includes the thickness direction.
G01L 9/00 - Measuring steady or quasi-steady pressure of a fluid or a fluent solid material by electric or magnetic pressure-sensitive elementsTransmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
A semiconductor device is manufactured which includes a SiC epitaxial layer, a plurality of transistor cells that are formed in the SiC epitaxial layer and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode that faces a channel region of the transistor cells in which a channel is formed when the semiconductor device is in an ON state, a gate metal that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode while being physically separated from the gate electrode, and a built-in resistor that is made of polysilicon and that is disposed below the gate metal so as to electrically connect the gate metal and the gate electrode together.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/17 - Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a semiconductor chip (Q) disposed on the first pattern; a power terminal (ST, DT) and a signal terminal (CS, G, SS) electrically connected to the semiconductor chip; and a resin layer (12) configured to cover the semiconductor chip and the insulating substrate. The signal terminal is disposed so as to be extended in a vertical direction with respect to a main surface of the insulating substrate.
A semiconductor laser element includes an element body which outputs laser light from a first end surface. The element body includes a first recessed part, and a second recessed part. The first recessed part includes a first inner surface that faces the same side as a first side surface, and first connection surface that connects the first inner surface and the first side surface. The second recessed part includes a second inner surface that faces the same side as a second side surface, and a second connection surface that connects the second inner surface and the second side surface. The first connection surface and the second connection surface each include an inclined surface which is inclined with respect to an element front surface at an angle differing from the that of first side surface and that of the second side surface.
A semiconductor device includes a chip that has a main surface, a body region that is formed in a surface layer portion of the main surface, gate electrodes that are arranged on both sides of the body region on the main surface, and a connection electrode that is formed in a region between the gate electrodes on the main surface so as to overlap the body region in a thickness direction.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
The power conversion device includes a first semiconductor module, a second semiconductor module, a third semiconductor module, and a capacitor module. As viewed in a z direction, the first center line of the first semiconductor module, the second center line of the second semiconductor module, and the third center line of the third semiconductor module intersect the capacitor body. The first angle formed by the first center line and the second center line and the second angle formed by the second center line and the third center line are equal to each other. The lengths of the first busbar, the second busbar and the third busbar are equal to each other.
H02M 7/537 - Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
H02M 7/00 - Conversion of AC power input into DC power outputConversion of DC power input into AC power output
In an ion implantation processing system including an ion implantation device, the ion implantation device acquires, from a server, off-angle data of a wafer that is an ion implantation processing target and controls an ion implantation angle with respect to the wafer based on the off-angle data.
An electrostatic protection circuit includes: a first protection element configured with an anode connected to a first pad; a second protection element configured with a cathode connected to the first pad; a third protection element configured with a cathode connected to a cathode of the first protection element and an anode connected to a reference potential terminal; and a fourth protection element configured with an anode connected to an anode of the second protection element and a cathode connected to the reference potential terminal.
This semiconductor device comprises a substrate, a first semiconductor element, a heat dissipation member, and a bonding layer. The first semiconductor element is mounted on one side of the substrate in a first direction thereof. The heat dissipation member is positioned, with reference to the substrate, on the side opposite the first semiconductor element. The bonding layer bonds the heat dissipation member and the substrate. The heat dissipation member and the bonding layer each contain metal. The bonding layer has: a first bonding surface facing the heat dissipation member; and an end surface facing a direction orthogonal to the first direction. The bonding layer is provided with an opening that opens from the first bonding surface and/or the end surface.
A semiconductor device includes a semiconductor substrate, an insulating layer provided on the semiconductor substrate, a first high resistance unit embedded in the insulating layer and disposed so as to surround a first electrode in a plan view, a second high resistance unit embedded in the insulating layer and disposed so as to surround a second electrode in a plan view, and low resistance units for voltage detection that are electrically connected to the first high resistance unit and the second high resistance unit, and have lower resistances than the first high resistance unit and the second high resistance unit.
H10D 84/00 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
H10D 1/47 - Resistors having no potential barriers
74.
SIGNAL TRANSMISSION DEVICE, ELECTRONIC DEVICE, AND VEHICLE
A signal transmission device includes a transmission circuit, a reception circuit, and an isolating element that transmits a pulse signal between the transmission circuit and the reception circuit while isolating between them. The transmission circuit includes an input terminal that receives an analogue signal, a comparison circuit that compares the analogue signal with each of a plurality of threshold values to generate a plurality of comparison signals, and a pulse signal generation circuit that generates the pulse signal according to the plurality of comparison signals.
In a power module, multiple second power semiconductor elements are arranged on the second mount layer in one direction. Corresponding to the second power semiconductor elements, multiple second control-side connection members and multiple second drive-side connection members are arranged. A third conductive path is a path between a control electrode of the second power semiconductor element and a second control terminal, and a fourth conductive path is a path between a second drive electrode of the second power semiconductor element and a second detection terminal. At least one of a second control layer and a second drive layer includes a second detour portion that detours to reduce a difference between the multiple second power semiconductor elements in a sum of a length of the third conductive path and a length of the fourth conductive path.
A method for manufacturing a semiconductor device including a base material bonded to the heat dissipating member is configured to more reliably retain the shape of a sealing resin. The method includes a first process, a second process, and a third process. The first process includes bonding a base material to a heat dissipating member, where the base material includes an insulating layer and a conductive layer positioned on a first side in a first direction relative to the insulating layer. The second process includes bonding a semiconductor element to the conductive layer. The third process includes forming the sealing resin that covers the semiconductor element. In the first process, the base material is bonded to the heat dissipating member with the insulating layer positioned between the heat dissipating member and the conductive layer. The third process is performed after completion of each of the first process and the second process.
Provided is a semiconductor element including a semiconductor substrate; a semiconductor layer laminated to the semiconductor substrate, and having a circuit formed within the semiconductor layer; a conductive layer disposed on an opposite side of the semiconductor layer from the semiconductor substrate and including a part electrically connected to the circuit; and a conductive portion disposed between the semiconductor layer and the conductive layer, and electrically connected to the conductive layer. The conductive layer includes a check pattern not electrically connected to the circuit, and the conductive portion includes a superimposition portion superimposed on the check pattern as viewed in a thickness direction of the semiconductor substrate.
A semiconductor light-emitting device includes: a substrate; front-surface electrodes; back-surface electrodes; a semiconductor light-emitting element; a first drive circuit; and a second drive circuit. The substrate includes a substrate front surface, and a substrate back surface. The front-surface electrodes are formed on the substrate front surface. The back-surface electrodes are formed on the substrate back surface and configured for mounting the semiconductor light-emitting device. The semiconductor light-emitting element includes a first light emitter and a second light emitter. The first drive circuit is configured to drive the first light emitter. The second drive circuit is configured to drive the second light emitter. The semiconductor light-emitting element, the first drive circuit, and the second drive circuit are mounted on the front-surface electrodes.
H01S 5/062 - Arrangements for controlling the laser output parameters, e.g. by operating on the active medium by varying the potential of the electrodes
H01S 5/40 - Arrangement of two or more semiconductor lasers, not provided for in groups
80.
SEMICONDUCTOR DEVICE, SWITCHING POWER SUPPLY, AND LIGHTING DEVICE
A semiconductor device includes: a control terminal configured to receive an electrical input; multiple LED current detection terminals; a current detection signal generator configured to generate a current detection signal from current information obtained via the multiple LED current detection terminals; a voltage detection signal generator configured to generate a voltage detection signal according to an LED driving voltage; a switching element; a driver configured to drive the switching element; and a controller configured to control the driver, in which the controller is configured to control the driver by switching between a constant current operation and a constant voltage operation based on a comparison result between the voltage level of the control terminal and a predetermined threshold level.
H05B 45/34 - Voltage stabilisationMaintaining constant voltage
H05B 45/345 - Current stabilisationMaintaining constant current
H05B 45/50 - Circuit arrangements for operating light-emitting diodes [LED] responsive to malfunctions or undesirable behaviour of LEDsCircuit arrangements for operating light-emitting diodes [LED] responsive to LED lifeProtective circuits
An output node of a high-side driver circuit is coupled to the gate of a high-side transistor. The high-side driver circuit is structured to operate in a first mode in which the high-side driver circuit outputs a driving current with a first current amount during a first period from the transition of a high-side control signal HGCTL from the off level to the on level, and outputs the driving current with a second current amount that is smaller than the first current amount during a second period subsequent to the first period.
H03K 17/687 - Electronic switching or gating, i.e. not by contact-making and -breaking characterised by the use of specified components by the use, as active elements, of semiconductor devices the devices being field-effect transistors
82.
SEMICONDUCTOR DEVICE, POWER SUPPLY DEVICE, AND VEHICLE
A pattern (2, 2A, 2B, 2C) of a semiconductor device (100, 100A, 100B, 100C) includes a first node (21, 21a, 21b, 21c) formed in an outer circumferential portion and configured to be connected to a first potential and a second node (22, 22b, 22c) insulated from the first node (21, 21a, 21b, 21c) and configured to receive application of a second potential different from the first potential. The first node (21, 21a, 21b, 21c) and the second node (22, 22b, 22c) are configured to be at least partly opposed to each other.
A semiconductor device comprises: a semiconductor element having a first electrode and a second electrode; a sealing resin covering a part of the semiconductor element; and a conductive member positioned outward from the sealing resin and conductively bonded to the first electrode. The sealing resin has a first surface and a second surface facing opposite sides from each other in a first direction. The first electrode is exposed from the first surface. The second electrode is exposed from the second surface. The conductive member has a first mounting surface facing the same side as the second surface in the first direction. The sealing resin has a third surface facing, in a second direction, the side on which the first mounting surface is located with respect to the semiconductor element. The conductive member is separated from the third surface.
H01L 23/12 - Mountings, e.g. non-detachable insulating substrates
H01L 23/34 - Arrangements for cooling, heating, ventilating or temperature compensation
H01L 23/48 - Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
H01L 25/07 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices all the devices being of a type provided for in a single subclass of subclasses , , , , or , e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in subclass
H01L 25/18 - Assemblies consisting of a plurality of individual semiconductor or other solid-state devices the devices being of types provided for in two or more different main groups of the same subclass of , , , , or
This semiconductor light-emitting device comprises: a substrate having a substrate obverse surface and a substrate reverse surface that is on the reverse side from the substrate obverse surface; an edge-emission-type light-emitting element disposed on the substrate obverse surface; a drive circuit that is disposed on the substrate obverse surface and drives the light-emitting element; and a case that is attached to the substrate, accommodates the light-emitting element and the drive circuit, and is configured such that light from the light-emitting element can pass therethrough. The substrate obverse surface includes a first substrate obverse surface on which both the light-emitting element and the drive circuit are arranged, and a second substrate obverse surface which is positioned closer to the substrate reverse surface than the first substrate obverse surface in the Z direction and is positioned at least in the light emission direction of the light-emitting element with respect to the light-emitting element. The case is attached to the second substrate obverse surface.
A semiconductor light-emitting device (10) comprises a substrate (20) that includes a surface-side conductive layer (30), a light-emitting element (60) that is mounted on the surface-side conductive layer, a transistor (90), and a capacitor (80). The capacitor is provided between the light-emitting element and the transistor. The transistor includes a gate electrode (93), a near source electrode (91N), a far source electrode (91F), and a drain electrode. The transistor is disposed such that the near source electrode is located nearer to the capacitor than the drain electrode and the far source electrode is located on the side opposite from the capacitor with respect to the drain electrode. Each source electrode (91) extends such that the longitudinal direction thereof is the direction (X direction) orthogonal to the direction in which the transistor and the capacitor are arranged in plan view. The gate electrode is disposed such that the gate electrode is adjacent to the far source electrode and the drain electrode is sandwiched between the gate electrode and the near source electrode.
Provided is a power supply control device provided in a switching power supply apparatus configured to convert an input voltage into an output voltage through switching of an output transistor, the power supply control device including a switching control circuit configured to stabilize the output voltage by performing switching control of the output transistor, based on a feedback voltage corresponding to the output voltage, and a temperature detecting circuit configured to detect a target temperature within the power supply control device and output a signal indicating a result of the detection of the target temperature to the switching control circuit, the switching control circuit being configured to be capable of performing an overcurrent protecting operation that limits a current flowing through the output transistor to a limit current or less, and the switching control circuit adjusting the limit current according to the target temperature.
H02M 1/32 - Means for protecting converters other than by automatic disconnection
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
First to fourth switching elements are connected in series from a reference node to a power supply node applied with an input voltage. Each switching element is constituted of an N-channel type MOSFET. In order to turn on the second to the fourth switching elements, first to third boot voltages supplied to the gates of the second to fourth switching elements are generated in first to third boot wirings. The boot voltages are generated using first to third boot capacitors and first to third boot switches, which are disposed corresponding to the first to third boot wirings.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
H02M 1/088 - Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
88.
NITRIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A nitride semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer that is formed on the first nitride semiconductor layer, and a gate portion that is formed on the second nitride semiconductor layer. The gate portion includes a semiconductor gate layer of a ridge shape that is formed on the second nitride semiconductor layer and a gate electrode that is formed on the semiconductor gate layer. The semiconductor gate layer includes a first semiconductor gate layer that is constituted of a nitride semiconductor and a second semiconductor gate layer that is formed between the first semiconductor gate layer and the gate electrode. The nitride semiconductor device further includes a first dielectric film that covers a side surface of the semiconductor gate layer and that extends onto the second nitride semiconductor layer.
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/85 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A semiconductor device includes a chip having a first principal surface, a first impurity region of a first conductivity type formed in a surface layer portion of the first principal surface, a second impurity region of a second conductivity type formed in a surface layer portion of the first impurity region, and a third impurity region of the first conductivity type formed in a surface layer portion of the second impurity region. A plurality of trenches are arranged at intervals in a first direction and extend in a second direction intersecting the first direction. First and second electric field relaxation structures of the second conductivity type are formed integrally with the second impurity region, are in contact with the trenches, are disposed on opposite sides of the trenches in the first direction, and are alternately arranged along the second direction.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/60 - Impurity distributions or concentrations
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
A chip resistor includes an insulating substrate, a resistance element, a rear-surface electrode, and a side-surface electrode. The insulating substrate includes a rear surface and a side surface. The resistance element and the rear-surface electrode are arranged at the rear surface. The side-surface electrode is arranged on the side surface and the rear-surface electrode. The side-surface electrode includes a lowermost point arranged at a position most distant from the rear surface in a direction perpendicular to the rear surface. The side-surface electrode includes a lowermost surface inclined with respect to the rear surface. The lowermost surface is an area from the side surface to the lowermost point. The lowermost surface includes a first area including the lowermost point. In the first area, an angle of inclination of the lowermost surface with respect to the rear surface is larger than or equal to 1° and smaller than or equal to 10°.
This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.
H10D 86/00 - Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
H10D 30/47 - FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
H10D 62/824 - Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
A semiconductor device includes at least one terminal, and the terminal includes a cylindrical holder having electrical conductivity and a metal pin inserted in the holder. The semiconductor device further includes a terminal support supporting the holder, and a sealing resin covering a part of the holder and covering the terminal support. The sealing resin includes a resin obverse surface facing a first side in a thickness direction. The holder includes a first surface located at one end on the first side in the thickness direction and a first outer side surface extending in the thickness direction. The first surface is located at a position different from the resin obverse surface in the thickness direction. The first outer side surface is in contact with the sealing resin. The metal pin protrudes beyond the resin obverse surface toward the first side in the thickness direction.
First to fourth switching elements are connected in series from a reference node to a power supply node that receives an input voltage. A power supply device controls states of the switching elements so as to divide the input voltage, and steps down an intermediate voltage obtained by the division so as to generate an output voltage. The states of the first to the fourth switching elements are switched among first to third states, on the basis of information of the output voltage and current information of an inductor. In the first state, the second and the fourth switching elements are ON while the first and the third switching elements are OFF. In the second state, the second and the fourth switching elements are OFF while the first and the third switching elements are ON. In the third state, the first to the fourth switching elements are all OFF.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes a chip having a main surface, a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface, a terminal region of a second conductivity type formed in a surface layer portion of the semiconductor region in a peripheral edge portion of the main surface, and a high concentration region of the first conductivity type formed in the surface layer portion of the main surface so as to be positioned in a thickness range between the main surface and a bottom portion of the terminal region, and having an impurity concentration higher than an impurity concentration of the semiconductor region.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
H10D 64/23 - Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
95.
SWITCHING POWER SUPPLY DEVICE, SWITCHING CONTROL DEVICE, AND VEHICLE-MOUNTED APPLIANCE
A switching power supply device includes a first switch, a second switch; a third switch; a detector detecting occurrence or a sign or occurrence of an overshoot in an output voltage; and a controller configured to turn on and off the first switch, the second switch, and the third switch. The third switch is a bidirectional element having a first drain terminal, a second drain terminal, a first gate terminal, and a second gate terminal and in addition a common source terminal. As seen in a sectional view of the bidirectional element, the third switch is structured to have a first gate region, a second gate region, and a source region between a first drain region and a second drain region, and to have the source region between the first and second gate regions.
H02M 3/158 - Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
A semiconductor device includes: a plurality of semiconductor elements connected in parallel; a rectifier element connected in anti-parallel to the plurality of semiconductor elements; a power terminal electrically connected to the plurality of semiconductor elements; and an electrical conductor electrically connected to the power terminal and the plurality of semiconductor elements and including a pad portion to which the plurality of semiconductor elements are bonded. The plurality of first semiconductor elements include a first element and a second element. The minimum conduction path of the first element to the power terminal is shorter than the minimum conduction path of the second element to the power terminal. The pad portion includes a first section to which the first element is bonded and a second section to which the second element is bonded. The rectifier element is located in the first section of the pad portion.
This semiconductor device includes an object to be connected containing silicon, an insulating interlayer film for covering the object to be connected, a via hole formed in the interlayer film and having a via bottom wall partitioned by the object to be connected, a silicide formed following the via bottom wall in the via hole, and a via electrode electrically connected to the object to be connected via the silicide in the via hole.
H10D 64/60 - Electrodes characterised by their materials
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
This semiconductor device includes a chip, an insulating film covering the chip, and a shield opening formed in the insulating film at the periphery of the chip and partitioning the insulating film into a region on the inner-side of the chip and a region on the periphery-side of the chip.
This electronic component includes: a base electrode having an upper surface and a side walls; a first via electrode disposed on the base electrode and having a first connection portion for the upper surface of the base electrode and second connection portions for the side walls of the base electrode; and a first electrode disposed on the first via electrode and electrically connected to the base electrode via the first via electrode.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 64/20 - Electrodes characterised by their shapes, relative sizes or dispositions
H10D 64/27 - Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
H10D 64/60 - Electrodes characterised by their materials
H10D 84/80 - Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups or , e.g. integration of IGFETs
A semiconductor device includes first, second, and third impurity regions of alternating conductivity types formed in surface layer portions of a chip. A trench extends from a first principal surface to the first impurity region, and an electric field relaxation structure of the second conductivity type is formed at a bottom of the trench. First and second contact regions are formed along opposite side surfaces of the trench from the first principal surface toward a second principal surface. The first and second contact regions are electrically connected to the second impurity region and the electric field relaxation structure. A plurality of the first contact regions and a plurality of the second contact regions are arranged along a length direction of the trench.
H10D 62/10 - Shapes, relative sizes or dispositions of the regions of the semiconductor bodiesShapes of the semiconductor bodies
H10D 62/832 - Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
