An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes
H01L 21/56 - Capsulations, p.ex. couches de capsulation, revêtements
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/31 - Capsulations, p.ex. couches de capsulation, revêtements caractérisées par leur disposition
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs sous-groupes différents du même groupe principal des groupes , ou dans une seule sous-classe de ,
3.
Circuits And Methods For Generating Adjustable Signal Pulses That Control Writes To Memory Cells
An integrated circuit includes a memory bit cell having a transistor coupled to a data line and a write pulse generation circuit coupled to the memory bit cell. The write pulse generation circuit generates a pulse in a word line signal that controls the transistor. The write pulse generation circuit adjusts a width of the pulse in the word line signal based on a write time of a write operation to the memory bit cell performed through the data line and the transistor.
G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p.ex. circuits de commande E/S de données, mémoires tampon de données E/S
G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]; Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
G11C 8/08 - Circuits de commande de lignes de mots, p.ex. circuits d'attaque, de puissance, de tirage vers le haut, d'abaissement, circuits de précharge, pour lignes de mots
Integrated circuit devices, methods, and circuitry for implementing filters based on multipliers in tensor circuits are provided. Integrated circuitry may include a first tensor circuit with a first set of multipliers of a first precision and first summation circuitry and a second tensor circuit with a second set of multipliers of a second precision and second summation circuitry. The first tensor circuit and the second tensor circuit may collectively perform a multiplication operation at a third precision higher than the first precision and the second precision.
Integrated circuit devices, methods, and circuitry for implementing and using a hybrid modular multiplier circuit using a number of different modular reduction techniques are provided. Integrated circuitry may include multiplication circuitry to multiply an input multiplicand value with an input multiplier value to obtain a product, first coarse-grain modular reduction circuitry to partially reduce the product based on a modulus value using a first type of modular reduction, second coarse-grain modular reduction circuitry to further reduce the product based on the modulus value using a second type of modular reduction, and fine-grain modular reduction circuitry to finally reduce the product based on the modulus value using a third type of modular reduction to produce a final modular reduction result.
Systems or methods of the present disclosure may provide systems and methods for adjusting a system design for a field-programmable gate array (FPGA) in response to a compilation error based on one or more language-based machine learning (ML) models trained on error messages of prior system designs. A method may include receiving an error message associated with a system design of an FPGA, generating a language-based machine learning (ML) prompt based at least on the error message, and determining an adjustment to the system design based on providing the language-based ML prompt to one or more language-based ML models trained on prior error messages.
An apparatus and method for redundant data processing with graceful degrading functionality. For example, one embodiment of an apparatus comprises: three processing elements operable in a first redundancy mode, the three processing elements to execute a same sequence of instructions to produce three corresponding results; detection circuitry to detect when any one processing element of the three processing elements produces a different result from the other two processing elements of the three processing elements; tracking circuitry to associate an error with the one processing element when it produces the different result from the other two processing elements, wherein if an error threshold is reached for the one processing element, the other two processing elements are to operate in a second redundancy mode excluding the one processing element.
G06F 11/18 - Détection ou correction d'erreur dans une donnée par redondance dans le matériel en utilisant un masquage passif du défaut des circuits redondants, p.ex. par logique combinatoire des circuits redondants, par circuits à décision majoritaire
8.
MULTICHIP PACKAGE WITH PROTOCOL-CONFIGURABLE DATA PATHS
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a substrate, a main die that is mounted on the substrate, and multiple transceiver daughter dies that are mounted on the substrate and that are coupled to the main die via corresponding Embedded Multi-die Interconnect Bridge (EMIB) interconnects formed in the substrate. Each of the main die and the daughter dies may include configurable adapter circuitry for interfacing with the EMIB interconnects. The adapter circuitry may include FIFO buffer circuits operable in a 1× mode or 2× mode and configurable in a phase-compensation mode, a clock-compensation mode, an elastic mode, and a register bypass mode to help support a variety of communications protocols with different data width and clocking requirements. The adapter circuitry may also include boundary alignment circuitry for reconstructing (de) compressed data streams.
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
9.
Circuits And Methods For Memory Built-In-Self-Tests
An integrated circuit includes memory circuits, a selector circuit, a bus coupled to the selector circuit, and a controller circuit. The controller circuit provides test signals from the controller circuit through the bus to the selector circuit for transmission to the memory circuits during a memory built-in-self-test mode. Each of the memory circuits can include a comparator circuit configurable to compare a read data bit read from one of the memory circuits to an expected data bit in the test signals to generate a sticky error bit during the memory built-in-self-test mode.
An integrated circuit includes an output circuit. The output circuit includes first, second, and third external contacts, a first output buffer circuit coupled to the first external contact, a first resistive circuit coupled between the first external contact and the second external contact, a second output buffer circuit coupled to the third external contact, and a second resistive circuit coupled between the second external contact and the third external contact. The output circuit has a test mode of operation to test for leakage current on the first and the third external contacts in response to receiving a first voltage applied externally to the first and the second resistive circuits through the second external contact. The output circuit has a user mode of operation wherein a supply voltage is applied externally to the first and the second resistive circuits through the second external contact.
A circuit system includes a platform baseboard, an integrated circuit coupled to the platform baseboard, and an auxiliary control board mounted on the platform baseboard. The auxiliary control board includes an interface device that is in communication with the integrated circuit through the platform baseboard. The auxiliary control board can perform power sequencing functions for the circuit system. The auxiliary control board can also perform telemetry gathering, hardware security functions, and configuration of the integrated circuit.
An array of antennas includes transmitter and receiver circuits. The transmitter includes a digital-to-analog converter (DAC), splitter and filter circuits, and mixer circuits. The DAC circuit converts a digital signal into an analog signal. The splitter and filter circuits separate frequencies of the analog signal into split signals. The mixer circuits multiply frequencies from the split signals by different frequencies of carrier signals to generate modulated signals that are converted into radio frequency (RF) signals. The receiver includes mixer circuits, a summing circuit, and an analog-to-digital converter (ADC). RF signals are converted into electrical signals. The mixer circuits multiply frequencies from the electrical signals with different frequencies of carrier signals. The outputs of the mixer circuits are summed by the summing circuit to generate a summed signal that is converted to digital by the ADC.
H01Q 13/08 - Terminaisons rayonnantes de lignes de transmission micro-ondes à deux conducteurs, p.ex. lignes coaxiales ou lignes micro-rayées
H04B 7/06 - Systèmes de diversité; Systèmes à plusieurs antennes, c. à d. émission ou réception utilisant plusieurs antennes utilisant plusieurs antennes indépendantes espacées à la station d'émission
H04L 27/20 - Circuits de modulation; Circuits émetteurs
13.
Circuits And Methods For Preventing Row Hammer Attacks To Memory Circuits
An integrated circuit includes a control circuit configured to send a first command for accessing a row of a memory circuit to the memory circuit during a refresh cycle of the memory circuit. The integrated circuit also includes a first buffer circuit configured to store data accessed from the row of the memory circuit in response to the first command. The integrated circuit also includes a second buffer circuit configured to store an address for the data. The control circuit services a second command for accessing the row during the refresh cycle by accessing the first buffer circuit using the address stored in the second buffer circuit and by preventing the memory circuit from performing an activation command of the row in response to the second command.
An integrated circuit includes a region of configurable logic circuits, and a control circuit that generates a digital signature based on a private key and data using a signing engine for verifying that data stored in the region of the configurable logic circuits has been erased. A method is provided for verifying that the region of the configurable logic circuits in the integrated circuit has been erased. The method includes receiving a public key, data, and a digital signature at a control circuit comprising a signature verifier engine, and generating an output that verifies whether the region of the configurable logic circuits has been erased by performing a signature verification of the digital signature using the data and the public key with the signature verifier engine.
H04L 9/32 - Dispositions pour les communications secrètes ou protégées; Protocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
An Advanced extensible Interface (AXI)-to-memory IP protocol bridge and associated apparatus and methods. The protocol bridge includes a first interface configured to be coupled to Write Address (AW), Write Data (W), Write Response (B), Read Address (AR) and Read Data (R) channels for the AXI manager and to implement AW, W, B, AR, and R signaling in accordance with an AXI protocol. A second interface is configured to couple I/O signals with the memory IP, with the I/O signals including a memory IP input channel to convey input data and input addresses with first I/O control signals, and a memory IP output channel to receive output data from the memory IP with second I/O control signals. The protocol bridge also includes logic for bridging the AXI protocol used by the AW, W, B, AR, and R signaling with a protocol used by the memory IP I/O signals.
Multiplexing circuitry comprises first switch and second switches coupled in series between a first node to receive a first supply voltage and a second node to provide an output voltage, and third and fourth switches coupled in series between a third node to receive a second supply voltage and the second node. First circuitry is to generate a first switch control signal to operate the first switch. Second circuitry is to generate a second switch control signal to operate the third switch. A first driver circuit is to generate a third switch control signal to operate the second switch. A second driver circuit is to generate a fourth switch control signal to operate the fourth switch. In a cross-coupled arrangement, the third switch control signal is based on the second switch control signal, and the fourth switch control is based on the second switch control signal.
Methods, apparatus, and systems for efficient partitioning and construction of graphs for scalable high-performance search applications. In one aspect a graph-based method for performing a longest prefix match (LPM) is disclosed. A plurality of ternary keys and created or accessed, each representing an Internet Protocol (IP) mask and having a length w and a number of specific bits comprising a prefix length followed by one or more wildcards. The ternary keys are partitioned into subsets as a function of the prefix lengths of the ternary keys. For each subset, a graph is constructed, and the graph is stored in memory. The graphs are searched for a match for an IP address. A result associated with the graph associated with the subset of prefixed with the longest prefix length is returned. Associated apparatus and systems for implementing the methods are also disclosed. In some embodiments, a graph memory engine (GME) is used.
An integrated circuit includes an output driver circuit having first and second transistors coupled to an external pad of the integrated circuit and first and second multiplexer circuits. The first multiplexer circuit is configurable to cause the first transistor to be controlled by a first voltage during a data output mode of operation and to couple a first control input of the first transistor to the external pad during a hot-socket protection mode of operation. The second multiplexer circuit is configurable to cause the second transistor to be controlled by a second voltage during the data output mode of operation and to couple a second control input of the second transistor to the external pad during the hot-socket protection mode of operation.
To increase logic density at relatively low silicon area and power cost and limiting the adverse impacts on routability and placement flexibility, an enhanced programmable logic architecture may be implemented with a hybrid architecture including a combination of the configurable gate-based logic and lookup tables (LUTs) (and/or other heterogeneous logic resources). The hybrid combination of heterogeneous logic resources may share one or more interconnects and inputs, such that the various logic resources may be cascaded rather than mutually exclusive. Sharing of the interconnect may be beneficial as the interconnect may use the majority of the area, power, and delay on the FPGA, more than the logic itself. Accordingly, the shared interconnects may reduce die area, power consumption, and delay on the FPGA. The configurable gate-based logic may include Configurable NOR-Inverts (CNIs). The CNIs may share inputs with existing LUTs or may use LUTs outputs as OR-Invert inputs.
Systems or methods of the present disclosure may provide an integrated circuit system including data plane circuitry that includes a packet processing pipeline and extraction circuitry, wherein the extraction circuitry is configurable to extract one or more features of a packet via the packet processing pipeline. The integrated circuit system also includes inferencing circuitry configurable to perform machine learning inferencing based on the one or more features.
H04L 41/16 - Dispositions pour la maintenance, l’administration ou la gestion des réseaux de commutation de données, p.ex. des réseaux de commutation de paquets en utilisant l'apprentissage automatique ou l'intelligence artificielle
H04L 43/026 - Capture des données de surveillance en utilisant l’identification du flux
21.
Enhanced Adaptive Logic Circuitry with Improved Function Coverage and Packing Ability
To utilize unused or underused input and output pins without a large and undesirable impact on power and die area consumption, an adaptive logic module (ALM) of a programmable logic device may be implemented with an additional 2LUT to improve small function packing density and wide function mapping coverage. The 2LUT may also serve as a route-through to provide direct access to ALM registers with or without input inversion. The enhanced ALM may also use route-through configurations of the additional 2LUT to improve the connectivity of the ALM inputs and outputs.
H03K 19/17728 - Blocs logiques reconfigurables, p.ex. tables de consultation
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/1776 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de configuration pour les mémoires
Systems and methods for controlling clock drift of an integrated circuit device are provided. Such a system may include a local oscillator to provide a reference clock signal, a phase-locked loop to provide a system clock signal based on the reference clock signal and a drift control signal, and processing circuitry to generate the drift control signal. In a synchronization mode, the processing circuitry may generate the drift control signal based on an input time reference signal. In a holdover mode, the processing circuitry may generate the drift control signal based on a trained machine learning model.
H03L 7/08 - Commande automatique de fréquence ou de phase; Synchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase - Détails de la boucle verrouillée en phase
23.
Content-Addressable Memory based Nondeterministic Finite Automata Accelerator
Systems and methods are provided for using TCAM tables in an NFA accelerator to achieve high throughput regular expression matching, improved scalability, improved resource utilization, and runtime and compile time reconfigurability, while remaining easy-to-deploy (no reliance on specialized hardware) thereby reducing customer barrier-to-entry. The architecture is programmable at runtime due to its dependency on TCAM for its configuration data. Moreover, FPGA gates may be used in the NFA accelerator and may be replaced at runtime using partial reconfiguration to allow limitations in the number of indirection tables and the capacities of the TCAMs to be adjusted at runtime.
G06F 12/06 - Adressage d'un bloc physique de transfert, p.ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
24.
CONFIGURABLE SEMICONDUCTOR PACKAGE CAPACITORS AND METHOD
An electronic device and associated methods are disclosed. In one example, the electronic device includes plurality of metal-insulator-metal capacitor units and a control circuit to dynamically select different amounts of the plurality of metal-insulator-metal capacitor units in correlation to a type of operation in a semiconductor die.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des groupes principaux , ou dans une seule sous-classe de , , p.ex. circuit hybrides
25.
Electronic Devices Having Oval Power Delivery Pads
An electronic device includes conductive pads that are formed on a surface of the electronic device. Each of the conductive pads has an oval shape. The conductive pads are coupled to deliver at least one of a power supply voltage or a ground voltage between an external device and the electronic device.
An integrated circuit includes first and second pads, a buffer circuit coupled to the first pad, a first pass gate circuit coupled to the first pad and to the buffer circuit, a second pass gate circuit coupled to the second pad, and a test bus coupled to the first pass gate circuit and the second pass gate circuit. The first pass gate circuit and the second pass gate circuit are configurable to couple the second pad to the buffer circuit through the test bus during a test of the buffer circuit that is performed using the second pad.
G01R 31/28 - Test de circuits électroniques, p.ex. à l'aide d'un traceur de signaux
H03K 17/687 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
27.
Techniques For Transferring Heat From Electronic Devices Using Heatsinks
An electronic device includes a first layer and a thermal heatsink that comprises a conductive region in a second layer of the electronic device. The thermal heatsink further comprises a first via that extends through the first layer. The first via is filled with conductive material that is coupled to the conductive region. The conductive material in the first via is coupled to an external terminal of the electronic device. The electronic device can also include a second via filled with conductive material that is coupled to the conductive region.
A computer system is provided for protecting an original circuit design for an integrated circuit. The computer system includes a logic circuit replacement tool that generates a redacted circuit design for the integrated circuit by replacing logic circuits in the original circuit design with first and second configurable circuits that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the first and the second configurable circuits. The logic circuit replacement tool couples one of the storage circuits that stores a bit in the bitstream to an input in each of the first and the second configurable circuits in the redacted circuit design.
An integrated circuit package includes first and second integrated circuit dies stacked vertically and coupled together, a connection device coupled to the first integrated circuit die, and a power delivery device coupled to the connection device. The power delivery device includes an inductor. The inductor generates supply current. The inductor is coupled to provide the supply current from the inductor to the first integrated circuit die through the connection device.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
An apparatus is provided. The apparatus comprises interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions. The machine-readable instruction may be stored on a storage device. The machine-readable instructions is to receive, from an interface apparatus, user data indicative of a hardware microservice requested by a user. Further, it is to receive, from a database, microservice data indicative of a plurality of hardware microservices. Further, it is to determine a hardware microservice based on the plurality of hardware microservices and the requested hardware microservice of the user.
Integrated circuit devices, methods, and circuitry for selectively blocking a voltage signal on receiver circuitry to reduce or eliminate unequal aging on the receiver circuitry. A device may include a first input/output (IO) pin to receive a first voltage and a second IO pin to receive a second voltage. The device may include a differential signal receiver that includes a first terminal coupled to the first IO pin and a second terminal coupled to the second IO pin. Transmission gate circuitry may selectively block the first voltage or the second voltage from being applied to the differential signal receiver. The transmission gate circuitry may include transistors having a lower junction voltage limit than the first voltage or the second voltage, or both.
H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande
H04B 1/12 - Montages de neutralisation, d'équilibrage ou de compensation
Anti-tamper systems and methods for protecting integrated circuit devices are provided. An integrated circuit device making use of an anti-tamper system may include memory and a device manager. The memory may store a count of resets of the integrated circuit device having a duration less than a threshold reset duration. The device manager may perform an anti-tamper operation when the count of resets exceeds a threshold number of resets.
G06F 21/79 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du stockage de données dans les supports de stockage à semi-conducteurs, p.ex. les mémoires adressables directement
An integrated circuit includes a network-on-chip and a core fabric coupled to the network-on-chip. Additionally, the integrated circuit also includes a voltage regulator configured to regulate a voltage rail to the core fabric. Furthermore, the integrated circuit includes a power management processor that is configured to control whether power is provided to the core fabric from the voltage regulator via the voltage rail. Moreover, the power management processor is configured to fence and drain the network-on-chip by causing the network-on-chip to deliver in-flight transactions to and from the core fabric before a change in power provided to the core fabric via the voltage rail occurs.
A device of the present disclosure may include interface circuitry and a decision feedback equalization (DFE) tuner. The interface circuitry may be coupled to DFE circuitry by data interconnect. The DFE tuner may control adaptation of the DFE circuitry to a channel associated with the data interconnect using an oscillating reference voltage provided to the DFE circuitry. The interface circuitry may be coupled between the DFE tuner and the DFE circuitry.
An integrated circuit includes an anti-tamper circuit having a resistor. The resistor includes conductors in a conductive layer of the integrated circuit. Each of the conductors extends across a width of the integrated circuit. The conductors are spaced apart across a length of the integrated circuit. The anti-tamper circuit generates an output signal indicative of changes in a resistance of the resistor caused by tampering that affects the conductors.
A circuit system includes an interposer comprising conductors and switch circuits coupled to the conductors, a first integrated circuit die coupled to the interposer, and a second integrated circuit die coupled to the interposer. The first integrated circuit die comprises a primary controller circuit for configuring the switch circuits. The second integrated circuit die comprises a secondary controller circuit. The primary controller circuit configures configurable logic circuits in the second integrated circuit die by providing configuration bits to the secondary controller circuit through the interposer.
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
37.
NETWORK FUNCTIONS VIRTUALIZATION PLATFORMS WITH FUNCTION CHAINING CAPABILITIES
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
An integrated circuit includes configurable logic circuit blocks that are configurable with a first configuration bitstream according to a coarse grained configuration. The coarse grained configuration implements an aggregate circuit structure of the configurable logic circuit blocks. The configurable logic circuit blocks are configurable with a second configuration bitstream according to a fine grained configuration. A total number of the first and the second configuration bits is fewer than a single fine grained configuration bitstream.
Integrated circuits of the present disclosure may include a temperature dependent voltage source, a divider circuit, an adder circuit, and a voltage regulator. The divider circuit may apply a gradient tuning parameter to a first voltage provided by the temperature dependent voltage source to provide a second voltage to the adder circuit. The adder circuit may apply a level shift voltage to the second voltage to provide a third voltage to the voltage regulator. The voltage level may provide a fourth voltage to digital circuitry of an integrated circuit based on the third voltage.
G05F 1/56 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final
40.
FPGA Compiler Flow for Heterogeneous Programmable Logic Elements
Embodiments herein are directed to systems and techniques for supporting heterogeneous logic architecture in programmable devices, such as field-programmable gate arrays (FPGAs). heterogeneous logic architectures may include additional logic elements (e.g., AND-inverter cones (AICs)) in addition to lookup tables (LUTs). Accordingly, it may be desirable to provide a compiler flow that supports heterogeneous FPGA architecture, taking advantage of a combination of LUTs and other logic elements (e.g., AICs) to improve resource utilization (e.g., die area, wire length) and improve maximum clock frequency and compile time.
A receiver circuit includes a first sense amplifier circuit that generates a first data signal based on a second data signal that has a first common-mode voltage during a first mode of operation. The receiver circuit includes a second sense amplifier circuit that generates a third data signal based on a fourth data signal that has a second common-mode voltage less than the first common-mode voltage during a second mode of operation. The receiver circuit includes a switch circuit that provides first data bits indicated by the first data signal to an output during the first mode of operation. The switch circuit provides second data bits indicated by the third data signal to the output during the second mode of operation.
H03F 3/04 - Amplificateurs comportant comme éléments d'amplification uniquement des tubes à décharge ou uniquement des dispositifs à semi-conducteurs comportant uniquement des dispositifs à semi-conducteurs
H03K 19/20 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion caractérisés par la fonction logique, p.ex. circuits ET, OU, NI, NON
42.
HOST MANAGED MEMORY SHARED BY MULTIPLE HOST SYSTEMS IN A HIGH AVAILABILITY SYSTEM
A high availability system including multiple host systems includes a host managed device memory that is shared between the multiple host systems allowing faster communication between the host systems. Access to the host managed device memory in a memory expander card is via direct memory access from the host system. Memory expander card control circuitry in the memory expander card performs memory translation, gatekeeping and synchronization. A host system can access the host managed device memory in the memory expander card directly using cxl.cache and cxl.mem protocols. From the host system perspective, the host managed device memory in the memory expander card is directly attached using a memory mapped interface.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
An active interposer device includes a multiplexer circuit configurable to provide a first signal from a first integrated circuit to an external terminal of the active interposer device in a first configuration of the active interposer device. The multiplexer circuit is further configurable to provide a second signal from a second integrated circuit to the external terminal in a second configuration of the active interposer device. The second integrated circuit is larger than the first integrated circuit, and the active interposer device is configurable to couple the first integrated circuit or the second integrated circuit to a package substrate through the external terminal.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H03K 17/00 - Commutation ou ouverture de porte électronique, c. à d. par d'autres moyens que la fermeture et l'ouverture de contacts
Circuitry, systems, and methods are provided for an integrated circuit device including a programmable logic fabric. The programmable logic fabric is configured to implement software-defined vector engines. The programmable logic fabric also includes a data movement engine (DME) that uses multiple DME threads to programmably insert data within an interior of the software-defined vector engines.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
(1) Semiconductors; integrated circuits; programmable logic devices (PLD); microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus and embedded computer software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for use in customizing integrated circuits; downloadable and recorded computer software for use in manufacturing customized integrated circuits; field programmable gate arrays (FPGA); field programmable gate array (FPGA) development kits; downloadable and recorded computer software for use in the design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for use on computer networks and a global computer network for use in accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; computer programs for use in the design and application of semiconductor devices; computer hardware, namely, design boards, development boards, and evaluation boards; circuit boards, namely, design boards, development boards, and evaluation boards (1) Computer hardware and software consulting services; information relating to computer hardware or software provided on-line from a global computer network or the internet; support and consultation services for managing computer systems, databases and applications; providing information online in the fields of semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technical consultation and research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; providing customers and technicians with information relating to computer project management; designing and developing standards for others in the design and implementation of computer software, computer hardware and telecommunications equipment
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
47.
Techniques For Storing States Of Signals In Configurable Storage Circuits
An integrated circuit includes a logic circuit block that includes a first adaptive logic module configurable to store a first state of a first signal received from a device-under-test in a first register, a second adaptive logic module configurable to store a second state of a second signal in a second register during a user mode of the integrated circuit simultaneously with the first state of the first signal being stored in the first register, and a third adaptive logic module configurable to store a third state of the first signal in a third register. The first and the third states of the first signal are stored for consecutive clock cycles in the first register and the third register. The logic circuit block is configurable to scan out the second state in the second register and the third state in the third register.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD) in the nature of electronic component used to build reconfigurable digital circuits; microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus in the nature of host bus adapters and downloadable computer operating software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for customizing integrated circuits; downloadable and recorded computer software for manufacturing customized integrated circuits; field programmable gate arrays (FPGA) in the nature of integrated circuits; field programmable gate array (FPGA) development kits comprised primarily of integrated circuits; downloadable and recorded computer software for design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for computer networks and a global computer network for accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; Downloadable computer operating programs for design and application of semiconductor devices; computer hardware in the nature of circuit design boards, circuit development boards, and circuit evaluation boards; circuit boards in the nature of circuit design boards, circuit development boards, and circuit evaluation boards Consultancy in the design and development of computer hardware and software; Providing information relating to design and development of computer hardware and software provided on-line from a global computer network or the internet; Computer technology support services, namely, help desk services for managing computer systems, databases and applications; Providing online information in the field of electronic and electrical systems design services for semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technology consultation and scientific research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; Computer project management services for customers and technicians; Developing quality control standards for computer software, computer hardware and telecommunications equipment
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD) in the nature of electronic component used to build reconfigurable digital circuits; microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus in the nature of host bus adapters and downloadable computer operating software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for customizing integrated circuits; downloadable and recorded computer software for manufacturing customized integrated circuits; field programmable gate arrays (FPGA) in the nature of integrated circuits; field programmable gate array (FPGA) development kits comprised primarily of integrated circuits; downloadable and recorded computer software for design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for computer networks and a global computer network for accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; Downloadable computer operating programs for design and application of semiconductor devices; computer hardware in the nature of circuit design boards, circuit development boards, and circuit evaluation boards; circuit boards in the nature of circuit design boards, circuit development boards, and circuit evaluation boards Consultancy in the design and development of computer hardware and software; Providing information relating to design and development of computer hardware and software provided on-line from a global computer network or the internet; Computer technology support services, namely, help desk services for managing computer systems, databases and applications; Providing online information in the field of electronic and electrical systems design services for semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technology consultation and scientific research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; Computer project management services for customers and technicians; Developing quality control standards for computer software, computer hardware and telecommunications equipment
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD) in the nature of electronic component used to build reconfigurable digital circuits; microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus in the nature of host bus adapters and downloadable computer operating software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for customizing integrated circuits; downloadable and recorded computer software for manufacturing customized integrated circuits; field programmable gate arrays (FPGA) in the nature of integrated circuits; field programmable gate array (FPGA) development kits comprised primarily of integrated circuits; downloadable and recorded computer software for design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for computer networks and a global computer network for accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; Downloadable computer operating programs for design and application of semiconductor devices; computer hardware in the nature of circuit design boards, circuit development boards, and circuit evaluation boards; circuit boards in the nature of circuit design boards, circuit development boards, and circuit evaluation boards Consultancy in the design and development of computer hardware and software; Providing information relating to design and development of computer hardware and software provided on-line from a global computer network or the internet; Computer technology support services, namely, help desk services for managing computer systems, databases and applications; Providing online information in the field of electronic and electrical systems design services for semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technology consultation and scientific research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; Computer project management services for customers and technicians; Developing quality control standards for computer software, computer hardware and telecommunications equipment
51.
Techniques For Configuring Computing Nodes In A Computing System
An integrated circuit includes logic circuits that are configurable by a bitstream of configuration data to perform a computing service requested in a computing system. The integrated circuit communicates with a central processing unit in the computing system according to interface features indicated by meta-data provided to the central processing unit to perform the computing service.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
52.
VIRTUAL MULTI-PORT MEMORY PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
A processor includes a shared memory, and an instruction unit to receive a single instruction, multiple thread (SIMT) instruction having a first source register identifier and a second source register identifier. The SIMT instruction indicates a number of data values to be written to the shared memory concurrently. A SIMT processor includes processor elements each to execute instructions of a different corresponding thread of a parallel thread group. Each of a number of processor elements, equal in number to the number of data values, is to execute the SIMT instruction to concurrently write a different corresponding one of the number of data values from a first source register of the respective processor element identified by the first source register identifier to the shared memory at an address based on address information from a second source register of the respective processor element identified by the second source register identifier.
Systems and methods may provide recommendations for a circuit design based on components of the circuit and machine-learning techniques. For example, a system may include a processor-based device storing or accessing a computer-aided design application for an integrated circuit, where the computer-aided design application, when executed by the processor-based device, causes acts to be performed including receiving an indication of a first selected component from a library for a design for the integrated circuit, retrieving one or more suggested components from the library based at least in part on the first selected component, and populating a user interface with the first selected component and a first suggested component of the one or more suggested components for display on the processor-based device.
G06F 30/31 - Saisie informatique, p.ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/27 - Optimisation, vérification ou simulation de l’objet conçu utilisant l’apprentissage automatique, p.ex. l’intelligence artificielle, les réseaux neuronaux, les machines à support de vecteur [MSV] ou l’apprentissage d’un modèle
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
Systems or methods of the present disclosure may provide protection to gate-driving circuitry from anomalous electrical conditions. A method may include detecting an anomalous electrical condition at an input/output (I/O) terminal of an electrical component. The method may also include determining whether the anomalous electrical condition comprises an undershoot condition or an overshoot condition. Additionally, the method may include generating a bias voltage based on the determination that the anomalous electrical condition comprises the undershoot condition or the overshoot condition and applying the bias voltage to the I/O terminal of the electrical component.
H03K 17/081 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension sans réaction du circuit de sortie vers le circuit de commande
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD); microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus and embedded computer software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for use in customizing integrated circuits; downloadable and recorded computer software for use in manufacturing customized integrated circuits; field programmable gate arrays (FPGA); field programmable gate array (FPGA) development kits; downloadable and recorded computer software for use in the design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for use on computer networks and a global computer network for use in accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; computer programs for use in the design and application of semiconductor devices; computer hardware, namely, design boards, development boards, and evaluation boards; circuit boards, namely, design boards, development boards, and evaluation boards. computer hardware and software consulting services; information relating to computer hardware or software provided on-line from a global computer network or the internet; support and consultation services for managing computer systems, databases and applications; providing information online in the fields of semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technical consultation and research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; providing customers and technicians with information relating to computer project management; designing and developing standards for others in the design and implementation of computer software, computer hardware and telecommunications equipment.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD); microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus and embedded computer software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for use in customizing integrated circuits; downloadable and recorded computer software for use in manufacturing customized integrated circuits; field programmable gate arrays (FPGA); field programmable gate array (FPGA) development kits; downloadable and recorded computer software for use in the design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for use on computer networks and a global computer network for use in accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; computer programs for use in the design and application of semiconductor devices; computer hardware, namely, design boards, development boards, and evaluation boards; circuit boards, namely, design boards, development boards, and evaluation boards. computer hardware and software consulting services; information relating to computer hardware or software provided on-line from a global computer network or the internet; support and consultation services for managing computer systems, databases and applications; providing information online in the fields of semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technical consultation and research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; providing customers and technicians with information relating to computer project management; designing and developing standards for others in the design and implementation of computer software, computer hardware and telecommunications equipment.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
Produits et services
semiconductors; integrated circuits; programmable logic devices (PLD); microprocessors; semiconductor devices; programmable integrated circuits; integrated circuit layouts; user configurable metal oxide silicon (CMOS) integrated circuits for programmable logic applications; configurable logic integrated circuits; reconfigurable logic integrated circuits and programmable logic integrated circuits; embedded semiconductor processor chips; embedded computer bus and embedded computer software facilitating the communication to and among microprocessors and subordinate peripherals for improving performance and data flow; downloadable and recorded computer software for use in customizing integrated circuits; downloadable and recorded computer software for use in manufacturing customized integrated circuits; field programmable gate arrays (FPGA); field programmable gate array (FPGA) development kits; downloadable and recorded computer software for use in the design and operation of semiconductors, semiconductor devices, microprocessors, integrated circuits and programmable logic integrated circuits; downloadable and recorded computer software to program a function into semiconductor devices; computer hardware; downloadable and recorded communications software for use on computer networks and a global computer network for use in accessing on-line databases used in the design and application of semiconductor devices and integrated circuits; computer programs for use in the design and application of semiconductor devices; computer hardware, namely, design boards, development boards, and evaluation boards; circuit boards, namely, design boards, development boards, and evaluation boards. computer hardware and software consulting services; information relating to computer hardware or software provided on-line from a global computer network or the internet; support and consultation services for managing computer systems, databases and applications; providing information online in the fields of semiconductors, integrated circuits, programmable logic devices, reconfigurable logic devices, storage networks, networking, wireless applications, industrial and automotive controls and technology; custom programming services and technical consultation and research in the fields of semiconductors, integrated circuits, configurable logic devices, programmable logic devices, associated computer-aided engineering logic development tools, computer networks, storage networks, networking, and wireless applications; design and development of computer hardware, semiconductors, integrated circuits, and programmable logic devices; development and design of computer hardware; providing customers and technicians with information relating to computer project management; designing and developing standards for others in the design and implementation of computer software, computer hardware and telecommunications equipment.
58.
Digital Signal Processing Circuitry with Multiple Precisions and Dataflows
Integrated circuit devices, methods, and circuitry for a digital signal processing (DSP) block that can selectively perform higher-precision DSP multiplication operations or lower-precision AI tensor multiplication operations. Flexible digital signal processing circuitry may include hardened multipliers, hardened summation circuitry, and an intermediate multiplexer network. The intermediate multiplexer network may be configurable to, in a first configuration, route data between the plurality of hardened multipliers and the hardened summation circuitry to perform a plurality of lower-precision multiplication operations. In a second configuration, the intermediate multiplexer network may route the data between the plurality of hardened multipliers and the hardened summation circuitry to perform at least one higher-precision multiplication operation.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
59.
Techniques For Managing Packet Scheduling From Queue Circuits
An integrated circuit includes queue circuits for storing packets, a scheduler circuit that schedules the packets received from the queue circuits to be provided in an output, and a traffic manager circuit that disables one of the queue circuits from transmitting any of the packets to the scheduler circuit based at least in part on a bandwidth in the output scheduled for a subset of the packets received from the one of the queue circuits.
H04L 47/52 - Ordonnancement selon la bande passante des files d'attente
H04L 47/12 - Prévention de la congestion; Récupération de la congestion
H04L 47/6295 - Ordonnancement des files d’attente caractérisé par des critères d’ordonnancement par utilisation de plusieurs files d’attente pour chaque cas particulier de qualité de service, de connexion, de flux ou de priorité
60.
Flexible Circuit for Real and Complex Filter Operations
Integrated circuit devices, methods, and circuitry for implementing and using a flexible circuit for real and complex filter operations are provided. An integrated circuit may include programmable logic circuitry and digital signal processor (DSP) blocks. The DSP blocks may be configurable to receive inputs from the programmable logic circuitry and may include first and second multiplier pairs. The first multiplier pair may include a first multiplier that may receive a first input and a second input and a second multiplier that may receive the second input and a third input of the inputs. The second multiplier pair may include a third multiplier that may receive the first input or a fourth input and a fifth input and a fourth multiplier that may receive the third input or a fifth input and a sixth input.
An integrated circuit includes conversion circuitry for converting first data in a first data format optimized for efficient data storage into second data in a second data format optimized for processing by a processing circuit. The integrated circuit also includes filter circuitry for filtering the second data to generate filtered data in the second data format. The integrated circuit outputs the filtered data for processing by the processing circuit.
An active interconnection device has a repeater circuit that includes a storage circuit. The storage circuit is coupled to store a configuration bit for configuring the repeater circuit to transmit a signal between a first integrated circuit die and a second integrated circuit die. The storage circuit is coupled to receive the configuration bit through a conductor during a configuration mode. A buffer circuit in the repeater circuit is configurable to transmit the signal through the conductor during a transmission mode in response to the configuration bit.
An integrated circuit includes first external conductive pads, second external conductive pads, and third external conductive pads. The second external conductive pads are between the first external conductive pads and the third external conductive pads. Repair group circuitry is configurable to shift signal transmission away from one of the first external conductive pads to one of the third external conductive pads if the one of the first external conductive pads has a defect.
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 27/105 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive comprenant des composants à effet de champ
64.
METHOD AND SYSTEM FOR EFFICIENT PARTITIONING AND CONSTRUCTION OF GRAPHS FOR SCALABLE HIGH-PERFORMANCE SEARCH APPLICATIONS
Methods, apparatus, and systems for efficient partitioning and construction of graphs for scalable high-performance search applications. A method for partitioning a set of ternary keys having one or more wildcards includes analyzing patterns of the set of ternary keys and storing ternary keys with the same pattern in the same subset. The patterns may include uncompressed patterns and compressed patterns. When there are more patterns than a target number of subgraphs, patterns are repeatedly merged until the number of merged patterns matches the target number of subgraphs. Table entries having ternary keys corresponding to the ternary keys in a final set of merged patterns of ternary keys are generated and partitioned into sub-tables, with each sub-table associated with a respective sub-graph. Tables with hundreds of thousands or millions of entries are supported.
A circuit system includes a support device having an interconnection conductor. The circuit system also includes first, second, and third integrated circuits that are mounted on the support device. The interconnection conductor couples the first integrated circuit to the third integrated circuit. The second integrated circuit is between the first integrated circuit and the third integrated circuit.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
66.
ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM
An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.
G06F 13/12 - Commande par programme pour dispositifs périphériques utilisant des matériels indépendants du processeur central, p.ex. canal ou processeur périphérique
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 17/14 - Transformations de Fourier, de Walsh ou transformations d'espace analogues
67.
Translation Circuitry for Access Control Identifier Mechanisms
Systems or methods of the present disclosure may provide a system that includes a secure processor subsystem that includes a processor and a first programmable lookup table. The first programmable lookup table is to receive global identifiers for initiators of operations using a resource and to translate the global identifiers to respective local identifiers for use in the secure processor subsystem. The initiators are external to the secure processor subsystem. The secure processor subsystem also includes a second programmable lookup table to translate the local identifiers to respective global identifiers for egresses from the secure processor subsystem.
Circuitry, systems, and methods are provided for an integrated circuit device including a memory storing a data structure, a cache storing a portion of the structure data, and an acceleration function unit providing hardware acceleration for a host device. The acceleration function unit may provide the hardware acceleration by intercepting a request from the host device to access the memory, where the request comprises an address corresponding to a data node of the data structure, identifying a next data node based at least in part on decoding the data node, and loading the next data node into the cache for access by the host device.
Circuitry, systems, and methods are provided for an integrated circuit including an acceleration function unit to provide hardware acceleration for a host device. The integrated circuit may also include interface circuitry including a cache coherency bridge/agent including a device cache to resolve coherency with a host cache of the host device. The interface circuitry may also include cacheline state tracker circuitry to track states of cachelines of the device cache and the host cache. The cacheline state tracker circuitry provides insights to expected state changes based on states of the cachelines of the device cache, the host cache, and a type of operation performed.
Integrated circuit devices, methods, and circuitry are provided for performing timing analysis for chip-to-chip connections between integrated circuits in a multichip package. A system may include an integrated circuit package and a computing system. The integrated circuit package may have a first integrated circuit connected to a second integrated circuit via a chip-to-chip connection. The chip-to-chip connection may also be connected to a package ball. The computing system may perform timing analysis on a circuit design for the first integrated circuit with respect the chip-to-chip connection based on user-specified parasitic data relating to the connection to the package ball.
G06F 30/398 - Vérification ou optimisation de la conception, p.ex. par vérification des règles de conception [DRC], vérification de correspondance entre géométrie et schéma [LVS] ou par les méthodes à éléments finis [MEF]
71.
EFFICIENT LOGIC BLOCKS ARCHITECTURES FOR DENSE MAPPING OF MULTIPLIERS
An integrated circuit includes a logic block configured to perform multiplication operations. The logic block includes a plurality of lookup tables configured to receive a plurality of inputs and generate a first plurality of outputs. Additionally, the logic block includes adding circuitry configured to receive the first plurality of outputs and generate a second plurality of outputs. Furthermore, the logic block includes circuitry configured to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.
An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.
H04L 49/109 - TRANSMISSION D'INFORMATION NUMÉRIQUE, p.ex. COMMUNICATION TÉLÉGRAPHIQUE Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p.ex. interrupteurs sur puce
73.
Systems And Methods For Thermal Monitoring In Integrated Circuits
A method is provided for thermally monitoring an integrated circuit during operation of the integrated circuit. The method includes receiving a measurement of a temperature in a circuit design for the integrated circuit from a temperature sensor, and determining a hottest temperature in the circuit design based on the measurement of the temperature. A non-transitory computer readable storage medium includes computer readable instructions stored thereon for causing a computing system to receive a measurement of a first temperature in a circuit design for an integrated circuit from a temperature sensor, and determine a second temperature of a cold spot in an active region of the circuit design by adjusting the measurement of the first temperature generated by the temperature sensor by an offset.
An integrated circuit device may include a first network on chip (NOC) circuit configured to receive a set of data and transfer the set of data to a first node of the first NOC circuitry. The first node is configured to transfer the set of data to a second NOC circuit of an additional integrated circuit device separate from the integrated circuit device.
Systems or methods of the present disclosure may provide a library including multiple macros that may be pre-compiled prior to implementation of the design. For example, a design may be mapped to one or more macros in the library, and the one or more macros may be placed into and routed between a portion of a region, one region, one or more regions of the integrated circuit device to implement the design. Since the macros may be pre-compiled, compilation time experienced by the designer may correspond to the placement and routing of the one or more macros, which may be less than compilation time for fine-grained operations. The pre-compiled logic within the macros may be set using a lookup table mask to set and/or adjust a functionality of the macro. Additionally or alternatively, the place and route operation may be performed at finer granularities to reduce bottle necks.
An integrated circuit includes a region of configurable logic circuits and a configuration controller circuit that generates a first health condition report indicating a first health condition of the region before configuring the configurable logic circuits according to a circuit design. The configuration controller circuit generates a second health condition report indicating a second health condition of the region after configuring the configurable logic circuits according to the circuit design.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
77.
MULTIPLE CHANNEL DIRECT ACCESS MEMORY-BASED CONFIGURATION SYSTEM
A system including a host device and an integrated circuit. The host device includes a host memory, the host memory storing configuration data. The integrated circuit device includes an integrated circuit and a direct memory access circuitry. The direct memory access circuitry pulls the configuration data from the host memory. The direct memory access circuitry also programs the integrated circuit based on the configuration data.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
G06F 15/167 - Communication entre processeurs utilisant une mémoire commune, p.ex. boîte aux lettres électronique
78.
Techniques For Controlling Access To Provisioning Integrated Circuits
An integrated circuit includes a cryptographic engine that generates a cryptographic version of a password, a secure storage area, and a security controller circuit that stores an enable bit and at least a portion of the cryptographic version of the password in the secure storage area to enable a security feature. The security controller circuit enables provisioning of the integrated circuit in response to receiving the password from a user if the enable bit stored in the secure storage area indicates that the security feature is enabled.
G06F 21/74 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information opérant en mode dual ou compartimenté, c. à d. avec au moins un mode sécurisé
Systems and methods for dynamically sizing inter-kernel communication channels implemented on an integrated circuit (IC) are provided. Implementation characteristics of the channels, predication, and kernel scheduling imbalances may factor into properly sizing the channels for self-synchronization, resulting in optimized steady-state throughput.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G06F 30/327 - Synthèse logique; Synthèse de comportement, p.ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliers; Eléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c. à d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p.ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
An integrated circuit includes a first cryptographic module that enables debugging of the first cryptographic module and a second cryptographic module that disables debugging of the second cryptographic module. Each of the first and the second cryptographic modules has a logical cryptographic boundary that includes a first block. The logical cryptographic boundary of the first cryptographic module includes a second block that is not included within the logical cryptographic boundary of the second cryptographic module. The logical cryptographic boundary of the second cryptographic module includes a third block that is not included within the logical cryptographic boundary of the first cryptographic module.
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/498 - Connexions électriques sur des substrats isolants
H03K 19/17704 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/17796 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la disposition physique des blocs
H04L 41/5019 - Pratiques de respect de l’accord du niveau de service
85.
Methods and apparatus for reducing microbumps for inter-die double-data rate (DDR) transfer
An inter-die double data rate (DDR) data transfer scheme is provided. In particular, the data transfer scheme utilizes an error correction code (ECC) encoding scheme that exploits the DDR property that a single microbump defect can only yield four possible error scenarios. A specialized single error correcting, double error detecting, and double adjacent error correcting (SEC-DED-DAEC) encoding scheme that imposes at least four parity check matrix constraints may be used. Configured and operated in this way, a fewer number of parity check bits are required to detect data bit errors associated with a single defective microbump.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p.ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p.ex. contrôle de parité, exclusion des 9 ou des 11
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes
H03M 13/29 - Codage, décodage ou conversion de code pour détecter ou corriger des erreurs; Hypothèses de base sur la théorie du codage; Limites de codage; Méthodes d'évaluation de la probabilité d'erreur; Modèles de canaux; Simulation ou test des codes combinant plusieurs codes ou structures de codes, p.ex. codes de produits, codes de produits généralisés, codes concaténés, codes interne et externe
86.
EXTENDED FLOATING-POINT RANGE ADDITION AND MULTIPLICATION
A first storage location is to store a first floating-point data element. The first data element has a sign bit, an N-bit first exponent value, and M bits. A second storage location is to store a second floating-point data element that is to have a same number of bits as the first floating-point data element. The second data element has a sign bit, an N-bit first exponent value, and M bits. The N-bit first exponent value of the second data element is all zeroes and the M bits of the second data element include a significand and a second exponent value. A floating-point arithmetic unit is coupled with the first and second storage locations. The floating-point arithmetic unit is to perform either multiplication or addition on the first and second data elements to generate a result data element based at least in part on the second exponent value.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p.ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
An integrated circuit includes a package substrate that includes first and second electrical traces. The integrated circuit includes first, second, third, and fourth configurable dies, which are mounted on the package substrate. The first and second configurable dies are arranged in a first row. The third and fourth configurable dies are arranged in a second row, which is approximately parallel to the first row. The first and third configurable dies are arranged in a first column. The second and fourth configurable dies are arranged in a second column, which is approximately parallel to the first column. The first electrical trace couples the first and third configurable dies, and the second electrical trace couples the second and third configurable dies. The second electrical trace is oblique with respect to the first electrical trace. The oblique trace improves the latency of signals transmitted between dies and thereby increases the circuit operating speed.
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/14 - Gestion de demandes d'interconnexion ou de transfert
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
88.
METHODS AND APPARATUS FOR PROFILE-GUIDED OPTIMIZATION OF INTEGRATED CIRCUITS
Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.
An integrated circuit with specialized processing blocks is provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p.ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
90.
Architecture and Testing for an Integrated Circuit Package
Systems and methods are provided to enable efficient testing of an integrated circuit package. Such a system may include an integrated circuit package and a testing device to test a first portion of socket pins of the integrated circuit package corresponding to a first portion of a die area using a socket during a first pass, and test a second portion of socket pins of the integrated circuit package corresponding to a second portion of the die area using the socket during a second pass.
An integrated circuit includes first and second memory controller circuits and a load balancing multiplexer circuit that redirects a first read operation from the first memory controller circuit to the second memory controller circuit in response to receiving an indication that the second memory controller circuit has available memory bandwidth. A circuit system includes first and second memory devices, first and second memory controller circuits, and a load balancing multiplexer circuit that sends a write operation to the first memory controller circuit to store data in the first memory device and to the second memory controller circuit to store the data in the second memory device, while performing a number of memory traffic shaping operations.
A circuit system includes a support device that has first and second conductors. The circuit system also includes first, second, and third integrated circuits that are coupled to the support device. The second integrated circuit includes a peripheral region. The peripheral region includes a third conductor coupled between the first and the second conductors. The circuit system is configured to transmit a signal from the first integrated circuit through the first conductor, the third conductor, and the second conductor to the third integrated circuit. The first and the third integrated circuits are positioned diagonally in the circuit system
G06F 13/10 - Commande par programme pour dispositifs périphériques
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
Integrated circuit devices, methods, and circuitry for implementing and using a systolic array are provided. Such circuitry may include processing elements arranged in a triangular systolic array. The processing elements may receive an input matrix and perform Cholesky decomposition in a first stage, triangular matrix inversion in a second stage, and matrix multiplication in a third stage to produce an inverse of the input matrix as an output matrix.
Systems or methods of the present disclosure may provide a library including multiple regional bits streams that may be pre-generated by a manufacturer and/or custom generated by a designer that may be used to implement a design onto an integrated circuit device. The design may be decomposed into one or more regional bitstreams and stitched to form a larger combined bitstream to be implemented as coarse-grained operations on the integrated circuit device, thereby decreasing compilation time experienced by the designer. The combined bitstreams may be loaded into all or a portion of the integrated circuit device to realize the design. Additionally or alternatively, the integrated circuit device may include a hardened networks-on-chip to improve data routing within the combined bitstream.
An integrated circuit package includes a support device, first and second integrated circuits mounted on the support device, and a power jumper circuit selectable to couple a decoupling capacitor to one of a first power supply input of the first integrated circuit or a second power supply input of the second integrated circuit.
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p.ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
96.
SINGLE INSTRUCTION, MULTIPLE THREAD (SIMT) PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
A processor of an aspect includes an instruction unit to receive a single instruction, multiple thread (SIMT) instruction. The SIMT instruction has at least one field to provide at least one value. The at least one value is to indicate a plurality of threads that are to execute the SIMT instruction. The processor also includes a SIMT processor coupled with the instruction unit. The SIMT processor is to execute the SIMT instruction for each of the plurality of threads. Other processors, methods, systems, and machine-readable medium storing such a SIMT instructions are also disclosed.
A virtualization platform for Network Functions Virtualization (NFV) is provided. The virtualization platform may include a host processor coupled to an acceleration coprocessor. The acceleration coprocessor may be a reconfigurable integrated circuit to help provide improved flexibility and agility for the NFV. The coprocessor may include multiple virtual function hardware acceleration modules each of which is configured to perform a respective accelerator function. A virtual machine running on the host processor may wish to perform multiple accelerator functions in succession at the coprocessor on a given data. In one suitable arrangement, intermediate data output by each of the accelerator functions may be fed back to the host processor. In another suitable arrangement, the successive function calls may be chained together so that only the final resulting data is fed back to the host processor.
G06F 9/455 - Dispositions pour exécuter des programmes spécifiques Émulation; Interprétation; Simulation de logiciel, p.ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p.ex. acces direct à la mémoire, vol de cycle
An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans le même sous-groupe des groupes , ou dans une seule sous-classe de , , p.ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
G06F 13/38 - Transfert d'informations, p.ex. sur un bus
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
H01L 23/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H03K 19/173 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p.ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
G06F 15/78 - Architectures de calculateurs universels à programmes enregistrés comprenant une seule unité centrale
H03K 19/17736 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels des ressources de routage
H03K 19/17796 - Circuits logiques, c. à d. ayant au moins deux entrées agissant sur une sortie; Circuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle - Détails structurels pour l'adaptation des paramètres physiques pour la disposition physique des blocs
H04L 12/43 - Réseaux en boucle avec commande décentralisée avec transmission synchrone, p.ex. multiplexage à division de temps (TDM), anneaux à tranches de temps
Systems and methods are provided for supporting wide-protocol interface across a multi-die interconnect interface. Data signals of a wide-protocol interface are split into a plurality of data streams. A handshake signal is established between a first circuit and a second circuit, whereby the first circuit and second circuit are dies of a multi-die device. The first circuit transmits the plurality of data streams to the second circuit via a plurality of multi-die interconnect channels. Each data stream of the plurality of data streams are compressed based on the handshake signal in order to provide wide-protocol interface with reduced number of required pins.
G06F 13/42 - Protocole de transfert pour bus, p.ex. liaison; Synchronisation
G06F 5/06 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour modifier la vitesse de débit des données, c. à d. régularisation de la vitesse
H04L 69/14 - Protocoles multicanaux ou multi-liaisons
H04L 49/25 - Routage ou recherche de route dans une matrice de commutation
