Systems or methods of the present disclosure may provide a programmable logic device including one or more power monitors and one or more thermal sensors. The programmable logic device may include control circuitry that may receive power data and thermal data for multiple die of the programmable logic device, and may implement one or more response based on the thermal and power data.
An apparatus to facilitate clock gating and clock scaling based on runtime application task graph information is disclosed. The apparatus includes a processor to: receive, from a compiler, a bitstream generated from code of an application, the bitstream related to a workload of the application; generate a task graph of the application using at least part of the bitstream, the task graph to represent one of a relationship and dependency of the code; program the bitstream to an accelerator device, wherein the bitstream to configure the accelerator device to support the workload of the application; execute one or more kernels of the code using the accelerator device; identify one or more optimizations for the accelerator device based on the task graph of the application; and transmit a command to cause the one or more optimizations to be implemented in the at least one region of the accelerator device.
The present disclosure describes programmable logic that may be operated in a turbo processing mode to cause an ongoing operation to be completed faster than a scheduled completion time. With at least some of the remaining time to the scheduled completion time, power savings may be realized by operating the programmable logic into a deep sleep mode, where configuration memory associated with the programmable logic may be set to a suitable voltage level as to not cause data loss at lower or zero voltage levels but otherwise realize power savings relative to an amount of power consumed during average processing operations.
G06F 1/3287 - Économie d’énergie caractérisée par l'action entreprise par la mise hors tension d’une unité fonctionnelle individuelle dans un ordinateur
G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge
A method comprising: retrieving a predefined power threshold; determining a transmission power of a transmitting antenna, wherein the transmitting antenna is actively transmitting a signal; retrieving a predefined transmission time interval; determining that the transmission power exceeds the predefined power threshold; determining a duration of transmitting the signal; comparing the duration with the predefined transmission time interval; and switching transmitting the signal from the transmitting antenna to a further antenna when the duration equals the predefined transmission time interval.
H04W 52/22 - Commande de puissance d'émission [TPC Transmission power control] le TPC étant effectué selon des paramètres spécifiques tenant compte des informations ou des instructions antérieures
Systems and methods for determining a partial reconfiguration region and/or boundary ports into or out of the partial reconfiguration region are provided. A system may include a programmable logic device and a data processing system. The programmable logic device may be configurable to be programmed with a plurality of partial reconfiguration personas in a partial reconfiguration region of the programmable logic device. The data processing system may determine a boundary of the partial reconfiguration region based on a superimposition of the plurality of partial reconfiguration personas.
The presently disclosed programmable fabric die includes a direct fabric die-to-fabric die interconnect interface column disposed in a sector of programmable logic fabric. Each row of the interconnect interface column includes at least one interconnect interface that is electrically coupled to a microbump. The microbump is configured to be electrically coupled to another microbump of another interconnect interface of another fabric die through an interposer. The fabric die may include multiple interconnect interface columns that each extend deep into the sector, enabling low latency connections between the fabric dies and reducing routing congestion. In some embodiments, the fabric die may include interconnect interfaces that are instead distributed throughout logic blocks of the sector.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/498 - Connexions électriques sur des substrats isolants
H03K 19/17704 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle les fonctions logiques étant réalisées par l'interconnexion des lignes et des colonnes
7.
Systems and Methods for a Multi-Mode Programmable IO
Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes programmable logic units implementing a user design and programmable input/output (IO) circuitry including multiple receiver instances that include a first type of multiplexer to receive a pad input, a second type of multiplexer to receive a voltage, and a third type of multiplexer to receive a clock. The first type of multiplexer is a high-speed multiplexer that has electrical overstress (EOS) protection, the second type of multiplexer has EOS protection and responds slower than the first type of multiplexer, and the third type of multiplexer does not have EOS protection. The programmable IO circuitry also includes a receiver to selectively receive outputs of the first type of multiplexer, the second type of multiplexer, and the third type of multiplexer at an input of the receiver.
H03K 19/173 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants
H03K 17/08 - Modifications pour protéger le circuit de commutation contre la surintensité ou la surtension
Systems or methods of the present disclosure may provide an integrated circuit system that includes a host comprising multiple Ethernet channels and a programmable logic device including a programmable logic fabric coupled to the multiple Ethernet channels. The programmable logic device is configured to dynamically associate a direct memory access (DMA) engine of the programmable logic fabric to an Ethernet channel of the multiple Ethernet channels during runtime of the programmable logic device without bringing the programmable logic device or other Ethernet channels down. The programmable logic device is also configured to store routing information configuration details in tables of a quality of service (QOS) arbiter and provide QOS services, via the QOS arbiter of the programmable logic device, for packets that use the dynamically associated DMA engine.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
In some examples, a self-starting bandgap circuit is provided. It may include one or more chopping circuits to reduce pre-trim inaccuracies. It may also, or alternatively, include an adaptive bandgap supply regulator and/or a start-up comparator to speed up the bandgap circuit's ability to come up with an adequate bandgap reference voltage.
Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes a clock, one or more local controllers, programmable logic units implementing a systolic array to compute a matrix multiplication, and embedded memory blocks. The embedded memory blocks include a single port random access memory (SPRAM). The one or more local controllers are configured to, on a first set of alternating clock cycles of the clock, load matrix sub-elements from two rows of a matrix into corresponding matrix element of the SPRAM. The one or more local controllers are configured to, on a second set of alternating clock cycles of the clock, read out the matrix elements from the SPRAM to the systolic array to compute the matrix multiplication.
An integrated circuit includes temperature sensors that generate temperature sensor data indicating temperatures in the integrated circuit, a thermal management controller circuit that identifies at least one hot spot in at least one location that is different from locations of the temperature sensors using the temperature sensor data and thermal coefficient data, and a power management controller circuit that decreases power of at least one circuit block corresponding to the at least one hot spot in a circuit design for the integrated circuit to reduce a temperature of the at least one hot spot.
Systems, methods, and circuitry for load balancing on communication interfaces are provided. A receiver may include an integrated circuit device which may include a communication interface, such as a Peripheral Component Interconnect Express (PCIe) interface. The integrated circuit device may receive packets and provide the packets to an application program. The integrated circuit device may include multiple buffers for providing the packets to the application program. The integrated circuit device may distribute the packets to the buffers based on functions associated with the packets. In some cases, a buffer may become overloaded based on an increased volume of packets associated with a function. A load balancing stream dispatcher may monitor each of the buffers, identify congestion metrics, and remap the functions to the buffers based on the congestion metrics. In these ways, the load balancing stream dispatcher may provide a technique for efficiently distributing packets on the communication interface.
H04L 47/129 - Prévention de la congestionRécupération de la congestion au point de destination final, p. ex. réservation des ressources du terminal ou de l’espace en mémoire tampon
Some examples include a resistor structure formed from interconnect line segments in multiple metalization layers of an integrated circuit device. The line segments include contacts from at least one dummy transistor.
H10D 84/80 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H10D 1/47 - Résistances n’ayant pas de barrières de potentiel
14.
OPTICAL INTERCONNECTS FOR FLEXIBLE CALIBRATION OF AN OPTICAL TRANSCEIVER IN A FREE-SPACE OPTICAL COMMUNICATION SYSTEM
Disclosed herein are devices, systems, and methods for selectively configuring an optical coupling network between a modem and optical head to calibrate the timing delay of the entire receive path and entire transmit path. The device includes a modem with a transmit and receive path and an optical head with an optical transmit path, an optical receive path, and a calibration path. The device includes an optical coupling network for selectively routing signals (i) through a first loopback path comprising the transmit path and the receive path; (ii) through a second loopback path comprising the transmit path, the optical transmit path, the optical receive path, and the receive path; (iii) through a third loopback path comprising the transmit path, twice the calibration path, and the receive path; and (iv) through a fourth loopback path comprising the transmit path, the calibration path, the optical receive path, and the receive path.
H04B 10/035 - Dispositions pour le rétablissement de communication après défaillance utilisant des boucles de retour
H04B 1/58 - Dispositions hybrides, c.-à-d. dispositions pour la transition d’une transmission bilatérale sur une voie à une transmission unidirectionnelle sur chacune des deux voies ou vice versa
H04B 10/11 - Dispositions spécifiques à la transmission en espace libre, c.-à-d. dans l’air ou le vide
An input receiver driver is provided that can accommodate a range of different IO standard signal voltage levels. In some examples, the driver includes an input stack circuit and a resistor ladder. The input stack circuit may include a P-type circuit and an N-type circuit coupled together at an input node and an output node. The resistor ladder may be coupled to the input stack circuit to make it capable of operating in at least three different modes that include a push-pull mode, a P-type source follower mode, and an N-type source follower mode based on an input voltage level at the input node.
Disclosed herein are devices, systems, and methods for selectively configuring an optical coupling network between a modem and optical head to calibrate the timing delay of the entire receive path and entire transmit path. The device includes a modem with a transmit and receive path and an optical head with an optical transmit path, an optical receive path, and a calibration path. The device includes an optical coupling network for selectively routing signals (i) through a first loopback path comprising the transmit path and the receive path; (ii) through a second loopback path comprising the transmit path, the optical transmit path, the optical receive path, and the receive path; (iii) through a third loopback path comprising the transmit path, twice the calibration path, and the receive path; and (iv) through a fourth loopback path comprising the transmit path, the calibration path, the optical receive path, and the receive path.
H04B 10/035 - Dispositions pour le rétablissement de communication après défaillance utilisant des boucles de retour
H04B 10/079 - Dispositions pour la surveillance ou le test de systèmes de transmissionDispositions pour la mesure des défauts de systèmes de transmission utilisant un signal en service utilisant des mesures du signal de données
17.
Controlled Transition Between Configuration Mode and User to Reduce Current-Resistance Voltage Drop
Systems or methods of the present disclosure may provide for gradually adjusting a frequency of a clock signal. When transitioning from a configuration mode to a user mode, a clock of an integrated circuit (e.g., a field-programmable gate array or FPGA) may quickly (e.g., instantaneously) switch from a low configuration mode frequency to a high user mode frequency. This rapid increase in clock frequency may cause an inrush current and corresponding current-resistance voltage (IR) drop. To reduce or avoid the inrush current and IR drop, a frequency of the clock may be gradually ramped up from the configuration mode frequency to the user mode frequency.
An apparatus of an aspect includes a storage having a plurality of storage locations, including a storage location to store data, an execution unit to execute an instruction to access the data, and an error correction code (ECC) decoder. The ECC decoder, when the data is erroneous data having one or more correctable errors, is to detect the one or more correctable errors in the erroneous data and correct the one or more correctable errors. The apparatus also includes circuitry to store information to indicate the storage location in an error log and circuitry to transition to an exception handler corresponding to an exception due to the one or more correctable errors. Other apparatus, methods, and systems are disclosed.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
A systolic array circuit includes memory circuits, storage circuits, and processing elements. Each of the memory circuits accesses first read data and second read data in response to a read address. The systolic array circuit is coupled to provide the first read data accessed from each of the memory circuits to a first one or more of the processing elements. The systolic array circuit is coupled to provide the second read data accessed from each of the memory circuits through one of the storage circuits to a second one or more of the processing elements.
Some examples include tracking switches that may be used as passgates such as for sensing circuit multiplexers. The tracking switches include tracking circuits to provide off-state voltages at inner passgate junction nodes to reduce leakage current in the tracking switch when it is to be off.
H03K 17/687 - Commutation ou ouverture de porte électronique, c.-à-d. par d'autres moyens que la fermeture et l'ouverture de contacts caractérisée par l'utilisation de composants spécifiés par l'utilisation, comme éléments actifs, de dispositifs à semi-conducteurs les dispositifs étant des transistors à effet de champ
21.
METHOD AND SYSTEM FOR ON-THE-FLY GRAPH PARTITIONING RESOURCE UTILIZATION
Methods, apparatus, and software for on-the-fly graph partitioning resource utilization. The graph includes a plurality of subgraphs comprising hierarchies of subsets of ternary keys having one or more wildcards. A move operation to be executed is identified under which ternary keys and associated structures for a subset in a source subgraph are to be moved to a destination subgraph. Prior to executing the move operation, a projection is made to whether there are sufficient memory and hardware resources to execute the move operation without hitting resource capacity limits. The move operation is executed when it is projected resource capacity limits will not be hit. Under one approach, an emulation of the move operation considering resource utilization required to execute the move is performed. Under another approach, current resource utilization for the graph across memory resources and hardware resources are compiled and peak resource utilization for the move operation is projected.
Systems and methods for a modular heatsink system for integrated circuit devices are provided. A modular heatsink system may include a base spreader to attach to an integrated circuit package die. A secondary heat dissipation device may be selectively attachable to the base spreader. The base spreader dissipates a first amount of heat from the integrated circuit package die when the secondary heat dissipation device is not mated to the base spreader. The base spreader and the secondary heat dissipation device collectively dissipate a greater amount of heat when the secondary heat dissipation device is mated to the base spreader.
A tensor circuit includes first storage circuits coupled to store first activation values from an activation matrix, second storage circuits coupled to store second activation values from the activation matrix, multiplexer circuits configurable to output a subset of the first and the second activation values stored in the first and the second storage circuits, multiplier circuits coupled to multiply weight values from a sparse weight matrix by the subset of the first and the second activation values output by the multiplexer circuits to generate products, and a summation circuit coupled to sum the products.
Methods and apparatus for performing profile-guided optimization of integrated circuit hardware are provided. Circuit design tools may receive a source code and compile the source code to generate a hardware description. The hardware description may include profiling blocks configured to measure useful information required for optimization. The hardware description may then be simulated to gather profiling data. The circuit design tools may then analyze the gathered profiling data to identify additional opportunities for hardware optimization. The source code may then be modified based on the analysis of the profiling data to produce a smaller and faster hardware that is better suited to the application.
G06F 111/06 - Optimisation multi-objectif, p. ex. optimisation de Pareto utilisant le recuit simulé, les algorithmes de colonies de fourmis ou les algorithmes génétiques
G06F 117/08 - Co-conception matériel-logiciel, p. ex. partitionnement matériel-logiciel
25.
Methods And Apparatus For Selectively Extracting And Loading Register States
Integrated circuits may include registers that store register states. Only a subset of the registers may store critical register states. The subset of registers may be specially demarcated, such as using synthesis directions in the hardware description, and may be coupled to dedicated extraction/loading circuitry. The extraction/loading circuitry may be implemented using soft or hard logic or can leverage existing programming or debugging circuitry on a programmable integrated circuit. The extraction/loading mechanism may also be implemented using multiplexers and associated control circuitry, scan chain circuitry, a memory-mapped interface, a tool-instantiated or user-instantiated finite state machine, or external memory interface logic. Accessing critical register states in this way can help improve efficiency with live migration events, debugging, retiming, and other integrated circuit operations.
Systems or methods of the present disclosure may provide a compiler that generates a package layout for a multi-die package based on a common specification provided by a Flexible Scaffold Chiplet Interconnect (FlexSCI). The compiler may generate a scaffold interconnect network formed by a subset of interconnects provided by integrated circuits within the multi-die package. The compiler may also identify and/or assign a functionality to nodes of the scaffold interconnect network. The nodes may route data, verify and/or validate, and/or debug dies within the multi-die package. Then, the compiler may identify a position of each die within the scaffold interconnect network. The compiler may instruct a display to display the package layout and/or automatically implement the package layout on a multi-die package via a system design configuration. As such, the systems and methods of the present disclosure may simplify the design process for multi-die packages.
Systems, methods, and circuitry for supporting high speed data transfers across link partners that are coupled by a communication link, such as a Peripheral Component Interconnect Express (PCIe). More specifically, integrated circuits, such as field programmable gate arrays (FPGAs), in a receiver may include multiple streams that are coupled to an application main band to improve the throughput of buffering and providing received packets to an application. The multiple streams may be first in, first out (FIFO) buffers that include a credit check to limit the risk of packet overflow. In some embodiments, integrated circuits in a transmitter may include multiple streams that are coupled to transmission processing circuitry. The transmitter may include a dynamic credit allocation system that adjusts credit allocations among the streams based on credit consumption data and congestion metrics.
A circuit system includes an electronic device having a first external terminal, a second external terminal, a third external terminal, and a power supply rail coupled to the first external terminal, the second external terminal, and the third external terminal. The circuit system also includes a capacitor coupled to the power supply rail in the electronic device through the third external terminal of the electronic device. The capacitor is configured to provide voltage overshoot protection to an integrated circuit die coupled to the first external terminal during an electrostatic discharge event occurring in the power supply rail. The capacitor is external to the integrated circuit die.
H02H 9/00 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion
H02H 7/00 - Circuits de protection de sécurité spécialement adaptés aux machines ou aux appareils électriques de types particuliers ou pour la protection sectionnelle de systèmes de câble ou de ligne, et effectuant une commutation automatique dans le cas d'un changement indésirable des conditions normales de travail
H02H 9/02 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de courant
Systems, methods, and circuitry for supporting high speed data transfers across link partners that are coupled by a communication link, such as a Peripheral Component Interconnect Express (PCIe). More specifically, integrated circuits, such as field programmable gate arrays (FPGAs), in a receiver may include multiple streams that are coupled to an application main band to improve the throughput of buffering and providing received packets to an application. The multiple streams may be first in, first out (FIFO) buffers that include a credit check to limit the risk of packet overflow. In some embodiments, integrated circuits in a transmitter may include multiple streams that are coupled to transmission processing circuitry. The transmitter may include a dynamic credit allocation system that adjusts credit allocations among the streams based on credit consumption data and congestion metrics.
Systems or methods of the present disclosure may relate to integrated circuits, such field-programmable gate arrays (FPGAs). The present disclosure includes an integrated circuit including one or more sectors of programmable logic circuitry, one or more I/O blocks respectively positioned proximate to the one or more sectors of programmable logic circuitry, and one or more voltage regulators. Each I/O block of the one or more I/O blocks includes a voltage regulator of the one or more voltage regulators. The voltage regulator may include one or more regulator phases that adjust voltage from a single power rail to a voltage level usable by the component. For example, the voltage regulator may turn on or off any suitable number of regulator phases to adjust the voltage to a suitable voltage level.
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
31.
Networks-On-Chip For Configuration And Emulation Of Integrated Circuits
An integrated circuit includes logic circuits and a network-on-chip in a region of the integrated circuit. The network-on-chip is configurable to transmit at least two of user data, configuration data, and emulation data to the logic circuits. The network-on-chip is configurable to transmit the user data to and from the logic circuits during a user mode of the integrated circuit. The network-on-chip is configurable to transmit the configuration data to the logic circuits for configuring the logic circuits during a configuration mode of the integrated circuit. The network-on-chip is configurable to transmit the emulation data to and from the logic circuits during an emulation mode of the integrated circuit.
A computing system includes a processor circuit configured to receive test data generated from testing integrated circuit dies in a test flow. The computing system includes a machine learning model that uses the test data generated from the test flow to predict bench results that are indicative of which ones of the integrated circuit dies fail to satisfy a manufacturing protocol when the integrated circuit dies are coupled to circuit boards.
G06F 30/3323 - Vérification de la conception, p. ex. simulation fonctionnelle ou vérification du modèle utilisant des méthodes formelles, p. ex. vérification de l’équivalence ou vérification des propriétés
G06N 20/20 - Techniques d’ensemble en apprentissage automatique
33.
EMBEDDED FARADAY ROTATORS AND COMPONENTS FOR INCREASING BANDWIDTH AND/OR REDUCING FIBER COUNT IN PHOTONICS MULTI CHIP PACKAGES
Embodiments disclosed herein include photonics systems with a dual polarization module. In an embodiment, a photonics patch comprises a patch substrate, and a photonics die over a first surface of the patch substrate. In an embodiment, a multiplexer is over a second surface of the patch substrate. In an embodiment, a first optical path from the photonics die to the multiplexer is provided for propagating a first optical signal, and a second optical path from the photonics die to the multiplexer is provided for propagating a second optical signal. In an embodiment, a Faraday rotator is provided along the second optical path to convert the second optical signal from a first mode to a second mode before reaching the multiplexer.
G02B 27/28 - Systèmes ou appareils optiques non prévus dans aucun des groupes , pour polariser
G02F 1/01 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur
G02F 1/09 - Dispositifs ou dispositions pour la commande de l'intensité, de la couleur, de la phase, de la polarisation ou de la direction de la lumière arrivant d'une source lumineuse indépendante, p. ex. commutation, ouverture de porte ou modulationOptique non linéaire pour la commande de l'intensité, de la phase, de la polarisation ou de la couleur basés sur des éléments magnéto-optiques, p. ex. produisant un effet Faraday
A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.
A computing system or an integrated circuit includes a key storage circuit for storing a key and an access control enforcer circuit that grants access to the key stored in the key storage circuit in response to receiving a request based on a hardware identifier that identifies a hardware system and a subcomponent of the hardware system that is an owner of the key. The access control enforcer circuit accesses a hardware property for a key from an access control attributes circuit in response to a request to access the key. The access control enforcer circuit prevents the key from being returned to an initiator of the request if the hardware property indicates that the key is protected. The access control enforcer circuit permits the key to be used to derive, wrap, or unwrap other keys if the hardware property indicates that the key is protected.
An analog-to-digital converter (ADC) circuit includes a first comparator circuit, a second comparator circuit, and an interpolation circuit. The first comparator circuit includes a first input terminal to receive a first reference voltage signal and a second input terminal to receive an input voltage signal. The second comparator circuit includes a first input terminal to receive a second reference voltage signal and a second input terminal to receive the input voltage signal. The interpolation circuit includes a first input terminal coupled to a first output terminal of the first comparator and a second input terminal coupled to a first output terminal of the second comparator.
Systems or methods of the present disclosure may provide an integrated circuit system, including programmable logic fabric and transceiver circuitry coupled to the programmable logic fabric, wherein the transceiver circuitry includes a parser configurable to parse a packet to identify a number of headers, a number of header offsets, or both, an extractor configurable to extract a number of fields from the number of heads, the number of header offsets, or both, and a classifier configurable to classify the packet to a stream based on the number of fields.
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include input circuitry, mixed-radix partial product generation circuitry, and partial product addition circuitry. The input circuitry may receive the multiplicand value and the multiplier value. The mixed-radix partial product generation circuitry may generate partial products that include a first radix partial product according to a first radix coding and a second radix partial product according to a second radix coding. The partial product addition circuitry may add the partial products to generate a product of the multiplicand value and multiplier value.
Systems and devices are provided for receiving or transmitting IQ data (e.g., suitable for passband quadrature amplitude modulation (QAM)) over a wireline using pairs of baseband pulse amplitude modulation (PAM-n) signals. Encoding circuitry may map data from an input bit stream to IQ data that includes an in-phase component and a quadrature-phase component. Modulator circuitry may determine an in-phase PAM-n signal based on the in-phase component and a quadrature-phase PAM-n signal based on the quadrature-phase component. Driver circuitry may transmit the in-phase PAM-n signal and the quadrature-phase PAM-n signal across a wireline channel. The in-phase PAM-n signal may be different by 90° from the quadrature-phase PAM-n signal. This may enable a remote receiver on the wireline channel to detect the in-phase PAM-n signal independently of the quadrature-phase PAM-n signal.
Systems, methods, and circuitry for determining a delay through a modem of a transceiver are provided. An integrated circuit system may include a transmit signal path, delay calibration circuitry, and a phase detector. The delay calibration circuitry may allow determination of a delay through a transmit signal path between a calibration sequence signal source and an output of the transmit signal path. The transmit signal path may include a number of processing stages having a possible delay variation under different conditions. The phase detector may determine a fractional baud rate difference between the calibration sequence signal source and a signal representative of the output of the transmit signal path
Layers in a deep neural network (DNN) may be executed based on spatial similarity in input data to improve computational efficiency. For example, a convolution may be performed based on spatial similarity between activations in the input feature map (IFM). A DNN accelerator may identify an anchor tensor in the IFM and measure similarity between the anchor tensor and one or more other tensors in the IFM. After determining that the similarity between the anchor tensor and another tensor is above a threshold, the DNN accelerator may store the result of a multiply-accumulate (MAC) operation on the anchor tensor as the result of a MAC operation on the other tensor and skip the MAC operation on the other tensor. The IFM may be an output of a previous layer in the DNN. In the previous layer, the DNN accelerator may store the anchor tensor and bypass storing the other tensor.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
42.
TWO-DIMENSIONAL ACTUATOR BEAM FOR ADJUSTABLE OPTICAL COUPLING ON PHOTONIC INTEGRATED CIRCUIT STRUCTURES
An apparatus comprises an integrated circuit (IC) package substrate, a photonic integrated circuit (PIC) die over or under the IC package substrate and comprising a first waveguide, and an optical component adjacent the PIC die and comprising an optical path. A beam cantilevered from a surface of the PIC die or the optical component has a second waveguide between the first waveguide and the optical path. The beam comprises a first plate portion extending in a horizontal or vertical plane, and a second plate portion distal from the first plate portion along a length of the beam and extending transversely to the first plate portion. The second waveguide extends along both the first and second plate portions.
Methods and apparatus are disclosed for waveguide alignment between optical components. An example apparatus includes a first component having a first surface and a first waveguide, the first component having a first magnet array on the first surface; and a second component having a second surface and a second waveguide, the second component having a second magnet array on the second surface, the first magnet array to be attracted towards the second magnet array to urge the first magnet array into alignment with the second magnet array, the first waveguide positioned to at least one of transmit or receive an optical signal to or from the second waveguide when the first magnet array is in alignment with the second magnet array.
A transmitter circuit includes a security circuit that masks mutable fields in a packet during an algorithm that generates an authentication tag for the packet, an extraction circuit that extracts the mutable fields from the packet to generate extracted fields, a calculation circuit that calculates updated values for the mutable fields using the extracted fields, and an inserter circuit that inserts the updated values for the mutable fields into the packet.
G06F 21/72 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information dans les circuits de cryptographie
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
The present disclosure describes a digital signal processing (DSP) block that includes a plurality of columns of weight registers and a plurality of inputs configured to receive a first plurality of values and a second plurality of values. The first plurality of values is stored in the plurality of columns of weight registers after being received. Additionally, the DSP block includes a plurality of multipliers configured to simultaneously multiply each value of the first plurality of values by each value of the second plurality of values.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/17748 - Détails structurels des ressources de configuration
H03M 7/24 - Conversion en, ou à partir de codes à virgule flottante
46.
Power Management using Voltage Islands on Programmable Logic Devices
Systems or methods of the present disclosure may provide efficient electric power consumption of programmable logic devices based on providing different voltage levels to different portions (e.g., voltage islands) of the programmable logic device. For example, the programmable logic device may include circuitry to provide different voltage levels to different voltage islands. The programmable logic device may implement and operate logic configurations with different operating parameters using different operating voltages for efficient electric power consumption.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
47.
SELECTIVE USE OF DIFFERENT ADVANCED INTERFACE BUS WITH ELECTRONIC CHIPS
A digitally communicative circuit may use standardized interfaces for connection and communication with other circuit components. Such digitally communicative circuit may benefit from using wider variety of interconnect schemes with the respective interfaces for transmission and reception of data. Some chiplets may communicate using a high data bandwidth interface while other chiplets may communicate using interfaces with lower data bandwidth. Alternate interface is introduced that may facilitate scaled communication with Advanced Interface Bus 2.0 without translation circuitry and with different data bandwidth.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/14 - Supports, p. ex. substrats isolants non amovibles caractérisés par le matériau ou par ses propriétés électriques
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A system, method, and apparatus for graph memory. In one embodiment, the method includes: traversing program instructions disposed in an associative memory for operating a computer, the method comprising: receiving input data to be processed; identifying a next instruction to be fetched in the memory for processing the input data via: receiving a current node ID of a current state; performing a computational test on the input data resulting in a computed value; generating a search key by combining at least a portion of the computed edge value with the current node ID; and accessing the next instruction in associative memory via the search key.
G06F 12/0875 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec mémoire cache dédiée, p. ex. instruction ou pile
49.
METHODS AND APPARATUS TO EXPOSE A MICROSERVICE TO A SOFTWARE LAYER
Methods, apparatus, systems and articles of manufacture disclosed herein expose a microservice to a software layer. A disclosed method includes composing an API execution recipe, initializing a software service to be called, and checking, by executing an instruction with the at least one processor. The connection is between a software layer and a microservice, is defined by the API execution recipe, and is to expose the microservice to the software layer.
Systems or methods of the present disclosure may provide efficient power consumption for programmable logic devices based on reducing guardband voltages. A programmable logic device may include circuit monitors to mimic critical paths of an implemented circuit design and generate timing information based on the critical paths. A controller on the programmable logic device may adjust the voltage guardband based on the timing information.
G05B 19/042 - Commande à programme autre que la commande numérique, c.-à-d. dans des automatismes à séquence ou dans des automates à logique utilisant des processeurs numériques
51.
Systems and Methods for Dynamically Adjusting Clock Skips to Mitigate Voltage Droop
To mitigate voltage droop while reducing the power and space consumed on the board and reducing switching activity, a clock skipping scheme may be implemented for an FPGA. The clock skipping scheme may be implemented in the FPGA design via an Electronic Design Automation (EDA) tool. The EDA tool may define clock skipping cycles based on customer needs for current ramp up speed (e.g., for an inrush current or an operating current) and clock frequency. The EDA tool may adjust clock skipping based on a power target and/or usage conditions of a user software design. In addition to mitigating voltage droop and reducing space consumed on the board and power consumed by the FPGA, the clock skipping scheme may maintain a base clock frequency, enable timing closure at the base clock frequency, and alleviate the need to reclose timing during clock skipping operations.
G06F 30/31 - Saisie informatique, p. ex. éditeurs spécifiquement adaptés à la conception de circuits
G06F 30/327 - Synthèse logiqueSynthèse de comportement, p. ex. logique de correspondance, langage de description de matériel [HDL] à liste d’interconnections [Netlist], langage de haut niveau à langage de transfert entre registres [RTL] ou liste d’interconnections [Netlist]
52.
Multiplier Circuit with Carry-Based Partial Product Encoding
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include, among other things, input circuitry and carry-based coding circuitry. The input circuitry may receive the multiplicand value and the multiplier value. The carry-based coding circuitry may receive bits of the multiplier value and generate multiplication codes using a carry-based coding scheme that includes multiplication codes according to a Booth's coding scheme but with at least one multiplication code that is removed and replaced with another at least one multiplication code with a different value. A first encoder of the carry-based coding circuitry may receive a carry signal to adjust a multiplication code value of the first encoder based on a second encoder of the carry-based coding circuitry encoding the multiplication code with the different value.
Systems or methods of the present disclosure may provide for interrupt migration using a processor and/or system on a chip. The system includes multiple processing cores and an interrupt controller. The interrupt controller includes an input terminal configured to receive an interrupt request and an interrupt controller timer. The interrupt controller also includes an output terminal configured to output an interrupt based on the interrupt request. Furthermore, the interrupt controller includes an interface configuration and status circuitry configured to track a period of time that the interrupt is transmitted to a first processing core of the multiple processing cores.
The present disclosure relates to an integrated circuit device that includes a plurality of vector registers configurable to store a plurality of vectors and switch circuitry communicatively coupled to the plurality of vector registers. The switch circuitry is configurable to route a portion of the plurality of vectors. Additionally, the integrated circuit device includes a plurality of vector processing units communicatively coupled to the switch circuitry. The plurality of vector processing units is configurable to receive the portion of the plurality of vectors, perform one or more operations involving the portion of the plurality of vector inputs, and output a second plurality of vectors generated by performing the one or more operations.
A digital signal processing (DSP) block includes a Fast Fourier Transform (FFT) unit capable of performing an FFT operation. The FFT unit includes a first FFT engine capable of converting a signal between a time-domain and a frequency-domain and the first FFT engine is a fixed size FFT engine. The FFT unit also includes a second FFT engine communicatively coupled to the first FFT engine and the second FFT engine is a variable size FFT engine. The FFT unit also includes a scale/offset block communicatively coupled to the second FFT engine and the scale/offset block is capable of performing a multiplication operation, an addition operation, or a combination thereof on an output of the second FFT engine.
An integrated circuit includes a delay controller circuit that generates delay signals based on a current data bit, an adjustable delay circuit that delays the current data bit, and a driver circuit that drives the current data bit outside the integrated circuit. The driver circuit transitions the current data bit at a first voltage to a second voltage over a first delay provided by the adjustable delay circuit based on the delay signals. The driver circuit transitions the current data bit at the second voltage to a third voltage over a second delay provided by the adjustable delay circuit based on the delay signals. The second voltage is less than the first voltage, and the second voltage is greater than the third voltage.
An integrated circuit includes a central region having first multiplexer circuits and first busses that interconnect the first multiplexer circuits. The integrated circuit also includes a network-on-chip. The network-on-chip includes switch circuits, second multiplexer circuits, second busses that interconnect the switch circuits, third busses that interconnect the switch circuits and the second multiplexer circuits, and fourth busses that interconnect the first multiplexer circuits and the second multiplexer circuits. Each of the second multiplexer circuits is coupled to at least two of the switch circuits through a subset of the third busses.
An integrated circuit includes a central region having logic circuits and networks-on-chip. Each of the networks-on-chip traverses the central region. The integrated circuit also includes an interface region having input and output buffer circuits. The networks-on-chip are configurable to exchange data between the logic circuits and the input and output buffer circuits. One of the networks-on-chip is configurable to place each source that receives the data from one of the logic circuits at one of multiple locations in the one of the networks-on-chip. The one of the networks-on-chip is also configurable to place each sink that provides the data to one of the logic circuits at one of the multiple locations in the one of the networks-on-chip. The input and output buffer circuits are coupled to exchange the data with an external device.
Systems or methods of the present disclosure may provide transmit circuitry that receives one or more input signals and an enable signal, the enable signal indicating whether a three-level communication scheme is enabled, and generates one or more data signals based on the one or more input signals and the enable signal. Equalization circuitry receives the one or more data signals and selectively generates a first set of equalization voltages based on the one or more data signals indicating the three-level communication scheme or selectively generates a second set of equalization voltages based on the one or more data signals not indicating the three-level communication scheme.
A system includes a first chiplet that includes at least one demodulator for demodulating at least one received signal from a receiver to generate hard bits and soft information from the received signal and a second chiplet coupled to exchange information with the first chiplet. The second chiplet includes at least one correlator to detect a symbol pattern indicating frame boundaries of frames having a known frame symbol period length in an acquisition state and transitioning the first and second chiplets to a connected state in response to a threshold number of successful frame boundary detections. The at least one correlator uses soft bit representations to correlate and deduce the frame boundaries in a windowed mode using the known frame length and previous frame boundary information while in the connected state and transitions the first and second chiplets out of the connected state and back to the acquisition state in response to at least one unsuccessful frame boundary detection.
An optical receiver implements a method to provide a digital output of a received on-off keyed optical signal. The method includes receiving an on-off keyed optical signal via a coherent optical front-end receiver utilizing a locally mixed laser LO for a reference signal to perform quadrature detection of the optical signal to generate an electrical signal, performing symbol/slot timing recovery on the electrical signal using a timing error detector, performing carrier frequency and phase recovery on a symbol/slot signal to generate a frequency and phase recovered signal, and demodulating the frequency and phase recovered signal via a demodulation circuit to provide a digital output representative of the received on-off keyed optical signal.
A self-calibrating transceiver includes a set of digital to analog converters configured to process a comb calibration waveform, at least one IQ modulator configured to generate at least one optical signal comprising I and Q components operably coupled from the set of digital to analog converters. A receiver photonics circuit is configured to convert the coupled optical signals to electrical signals. The receiver photonics circuit includes a set of analog to digital converters coupled to convert the electrical signals to digital signals representative of the comb calibration waveform in cartesian IQ format. Processing circuitry is coupled to determine at least magnitude and/or phase of the digital signals and generate filter coefficients based on a comparison of at least magnitude and/or phase to the comb calibration waveform.
Integrated circuit devices, methods, and circuitry for an efficient multiplier are provided. Multiplier circuitry to multiply a multiplicand value with a multiplier value may include, among other things, decoding circuitry, tripler circuitry, and partial product multiplexing circuitry. The decoding circuitry may decode bits of the multiplier value using a decoding scheme that includes at least a coding that indicates a triple, the tripler circuitry may generate a triple of the multiplicand value and may include circuitry to generate the triple of the multiplicand value that sums at least two different vectors, and the partial product multiplexing circuitry may select the triple of the multiplicand as a partial product when the coding indicates the triple.
Systems or methods of the present disclosure may provide an integrated circuit system including programmable logic circuitry and a transceiver tile coupled to the programmable logic circuitry, the transceiver tile including a transceiver subsystem. The transceiver subsystem may be configurable to store a precision time protocol (PTP) packet, generate a first copy of the PTP packet with a first timestamp, a second copy of the PTP packet with a second timestamp, and a third copy of the PTP packet with a third timestamp, encrypt each of the first copy of the PTP packet, the second copy of the PTP packet, and the third copy of the PTP packet, and transmit either the first copy of the PTP packet, the second copy of the PTP packet, or the third copy of the PTP packet.
This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.
H04L 49/109 - Éléments de commutation de paquets caractérisés par la construction de la matrice de commutation intégrés sur micropuce, p. ex. interrupteurs sur puce
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H04L 49/15 - Interconnexion de modules de commutation
A decoder device can include an input to provide a stream of data elements to a data decoding pipeline. The device can further include an early termination element coupled at a coupling point of one or more of the input or at a pipeline stage of the data decoding pipeline. The early termination element can remove a data element from the stream at the respective coupling point based on a determination that the data element is to be removed from the stream. The early termination element can further provide the removed data element to output circuitry of the decoder device. Other methods and apparatuses are described.
H03M 13/15 - Codes cycliques, c.-à-d. décalages cycliques de mots de code produisant d'autres mots de code, p. ex. codes définis par un générateur polynomial, codes de Bose-Chaudhuri-Hocquenghen [BCH]
Techniques for handling block format floating point and/or integer numbers are described. In some examples, circuitry for handling block format floating point and/or integer numbers includes a plurality of multiplexers to select between the output of the mantissa multiplier circuits and outputs of the shift circuits to allow for support for block and non-block numbers.
G06F 5/01 - Procédés ou dispositions pour la conversion de données, sans modification de l'ordre ou du contenu des données maniées pour le décalage, p. ex. la justification, le changement d'échelle, la normalisation
G06F 7/24 - Tri, c.-à-d. extraction de données d'un ou de plusieurs supports, nouveau rangement des données dans un ordre de succession numérique ou autre, et réinscription des données triées sur le support original ou sur un support différent ou sur une série de supports
Techniques for dot products using block format numbers are described. In some examples, a single instruction including one or more fields for an identifier of at least a first source operand, one or more field for an identifier of a second source operand, and one or more fields for an identifier of a destination operand, and a field for an opcode, the opcode to at least indicate execution circuitry is to perform a dot product utilizing data that is in the block format to encode one or more numbers, wherein a block number of the block format has a value of a scale multiplied by a value of a scalar element and wherein the data that is in the block format is to use data from at least the first and second source operands is used for performing dot products.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/345 - Adressage de l'opérande d'instruction ou du résultat ou accès à l'opérande d'instruction ou au résultat d'opérandes ou de résultats multiples
Techniques for converting block format numbers are described. In some examples, a single instruction is used that is to at least include fields for an opcode, a first source operand, and a destination operand, wherein the opcode is to at least indicate execution circuitry is to perform a conversion of one or more block format numbers associated with the first source operand that each have a value of a scale multiplied by a value of a data element to a non-block format and store the non-block formatted numbers in the destination operand.
Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
Signal lines that are useful for high speed I/O applications are provided. The signal lines can be used in, for example, semiconductor chip packaging applications. The signal lines include a conductive region and one or more meta-conductive regions having alternating layers of a magnetic material and a non-magnetic material.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
72.
MACHINE LEARNING TRAINING ARCHITECTURE FOR PROGRAMMABLE DEVICES
A programmable device may be configured to support machine learning training operations using matrix multiplication circuitry. In some embodiments, the multiplication is implemented on a systolic array. The systolic array includes an array of processing elements, each of which includes hybrid floating-point dot-product circuitry.
An integrated circuit includes a hard logic circuit block, a routing block, and a logic gate circuit block that includes configurable logic gate circuits. The logic gate circuit block is configurable to provide either first output signals of the configurable logic gate circuits to the routing block or second output signals of the hard logic circuit block to the routing block.
H03K 19/177 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion utilisant des éléments spécifiés utilisant des circuits logiques élémentaires comme composants disposés sous forme matricielle
H03K 19/20 - Circuits logiques, c.-à-d. ayant au moins deux entrées agissant sur une sortieCircuits d'inversion caractérisés par la fonction logique, p. ex. circuits ET, OU, NI, NON
SoftMax operation is one part of a deep neural network (DNN). Because computing SoftMax is complex and time-consuming, the SoftMax operation can limit the overall execution latency of the DNN. To address this issue, an in-line data path is added to pass output data from a matrix-to-matrix multiplication core to a hardware SoftMax accelerator. During a denominator phase of the SoftMax operation, the SoftMax accelerator can operate in-line to produce a denominator value using output values generated by the matrix-to-matrix multiplication core and received over the in-line data path. During a numerator phase of the SoftMax operation, the SoftMax accelerator can calculate SoftMax outputs using output values generated by the matrix-to-matrix multiplication core and retrieved from a memory. In other words, the SoftMax accelerator can produce partial results while the matrix-to-matrix multiplication is in-flight to cut down overall latency and reduce memory transactions.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 9/448 - Paradigmes d’exécution, p. ex. implémentation de paradigmes de programmation
75.
LATENT SUPPLEMENTARY PROTOCOL FOR ENHANCING PERFORMANCE & FUNCTIONALITY OF COMMUNICATION SYSTEMS
Methods and apparatus for a Latent Supplementary Protocol (LSP) for enhancing performance and functionality of communication systems. The LSP implements a PAM (Pulse Amplitude Modulation) 6 (PAM6) modulation scheme utilizing 36 constellation points comprising a multiplex of 32-QAM and shifted 32-QAM constellations, each comprising 32 PAM6 symbols. Supplementary data are added to constellation points comprising conveyors and shifted constellation points without affecting the bandwidth of transfer of payload data between link partners implementing the LSP. The supplementary data may be employed for various purposes, including but not limited to payload data protection, an auxiliary communication channel between link partners, and transfer of additional payload data.
H04L 27/34 - Systèmes à courant porteur à modulation de phase et d'amplitude, p. ex. en quadrature d'amplitude
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding.
This disclosure relates to a phase-locked loop (PLL) of a programmable logic device (PLD) (e.g., a field programmable gate array (FPGA)) with reduced static phase error (SPE). The PLD may perform various operations using an internal clock signal generated by the PLL. The PLL may include a charge pump maintaining a phase alignment of the internal clock signal based on a reference clock signal. The charge pump may include a first pair of source follower transistors to reduce the leakage current when the charge pump is deactivated. Alternatively or additionally, the charge pump may include a second pair of source follower transistors to reduce a differential voltage between internal nodes and an output terminal when the charge pump is activated. As such, the charge pump may generate the internal clock signal with reduced SPE and/or phase drift based on including the first and/or second pair of source follower transistors.
Integrated circuit devices, methods, and circuitry for a timestamp engine to dynamically provision ports in accordance with PTP synchronization are provided. An integrated circuit device may include a number of ports configurable to communicate using timestamps corresponding to a number of Precision Time Protocol (PTP) clock domains. The integrated circuit may further include a timestamp engine configurable to receive timestamp requests and route a time of day (ToD) from a ToD circuit of a plurality of ToD circuits to different ports of the plurality of ports, where each ToD circuit is based on a PTP clock domain of the plurality of PTP clock domains.
Integrated circuit devices, methods, and circuitry for a virtual time of day (ToD) engine to generate timestamps by using offsets associated with PTP clock domains. An integrated circuit device may include a number of ports configurable to communicate using timestamps corresponding to a number of Precision Time Protocol (PTP) clock domains. The integrated circuit device may also include a host data processing system to determine an offset for a first PTP clock domain of the plurality of PTP clock domains by calculating a difference between a first ToD provided by a clock source on the integrated circuit and one or more ToDs associated with the first PTP clock domain. The integrated circuit may further include a virtual ToD engine to generate a timestamp by adding the offset for the first PTP clock domain to a second ToD from the clock source and provide the timestamp to a port.
Systems, methods, and circuitry for dynamic control of a network-on-chip (NOC) of an integrated circuit device are provided. An integrated circuit device may include first circuitry, second circuitry, and a network-on-chip (NOC). The NOC may transfer packetized data from an initiator bridge connected to the first circuitry to a target bridge connected to the second circuitry and dynamically limit a transmission rate of the initiator bridge based on a network condition of the NOC.
An integrated circuit includes a device coherency circuit, first and second traffic generator processor circuits, first and second interfaces, and a processor control finite state machine circuit that causes the first traffic generator processor circuit to perform first coherency data validation for first data sets and that causes the second traffic generator processor circuit to perform second coherency data validation for second data sets. The first traffic generator processor circuit transmits first traffic for the first data sets to the device coherency circuit through the first interface. The second traffic generator processor circuit transmits second traffic for the second data sets to the device coherency circuit through the second interface.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
83.
Systems and Methods for Efficient Convergence for Time Servo
Systems and methods for packet-based network clock synchronization are provided. An integrated circuit device may include a local clock and a packet-based synchronization servo to apply a control loop to synchronize the local clock with a remote clock. The control loop may include a frequency correction to accelerate convergence.
Integrated circuit devices, methods, and circuitry to are provided to track and compensate for integrated circuit aging. An integrated circuit device may include first logic circuitry, a first replica of part of the first logic circuitry, a second replica of the part of the first logic circuitry, programmable voltage regulators to supply programmable voltage levels to the circuitry, and counter circuitry to measure a first oscillator count from the first replica of the part of the first logic circuitry and a second oscillator count from the second replica of the part of the first logic circuitry. A controller may control a first programmable voltage regulator to adjust a voltage level of the first logic circuitry based on the first oscillator count and the second oscillator count.
Systems, methods, and computer-readable media for performing evolutionary algorithms using an FPGA-GPU hybrid system. A system for performing an evolutionary algorithm may include an integrated circuit device with circuitry to perform population selection and evolution operations of the evolutionary algorithm and a parallel processing system to perform population evaluation of the evolutionary algorithm.
Integrated circuit devices, methods, and circuitry for linearity feedback to enable signal adjustment in multi-level signaling communication are provided. A system may include a first integrated circuit device with transmitter circuitry to controllably adjust levels of a multi-level signal and transmit the multi-level signal over a communication link. The system may also include a second integrated circuit device with receiver circuitry to receive the multi-level signal and instruct the transmitter circuitry to adjust the levels of the multi-level signal.
H04L 25/49 - Circuits d'émissionCircuits de réception à conversion de code au transmetteurCircuits d'émissionCircuits de réception à pré-distorsionCircuits d'émissionCircuits de réception à insertion d'intervalles morts pour obtenir un spectre de fréquence désiréCircuits d'émissionCircuits de réception à au moins trois niveaux d'amplitude
H04L 25/03 - Réseaux de mise en forme pour émetteur ou récepteur, p. ex. réseaux de mise en forme adaptatifs
Integrated circuits with dot product circuitry are provided. The dot product circuitry may be configured to generate partial products of different ranks based on the inputs. The partial products may be organized into corresponding groups based on their ranks. Each group of partial products having the same rank can then be compressed using a compressor/reduction tree. At least some of the compressed partial product values may be shifted between the different groups to maintain the proper offset. Each partial product may have an associated one's to two's complement conversion bit. The conversion bits of the various partial product groups can be separately aggregated and then injected into the compressor tree at one or more locations.
Circuitry for decomposing block floating-point numbers into lower precision floating-point numbers is provided. The circuitry may include a high precision storage circuit configured to provide high precision floating-point numbers, input selectors configured to receive the high precision floating-point numbers from the high precision storage circuit and to generate corresponding lower precision floating-point components with adjusted exponents, and a low precision block floating-point vector circuit configured to combine the various lower precision floating-point components generated by the input selectors. The lower precision floating-point components may be processed spatially or over multiple iterations over time.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 7/499 - Maniement de valeur ou d'exception, p. ex. arrondi ou dépassement
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
An integrated circuit includes a first amplifier circuit coupled to receive a first voltage, a second amplifier circuit coupled to receive the first voltage, and a transistor. The second amplifier circuit is coupled to an output of the first amplifier circuit. An input of the transistor is coupled to an output of the second amplifier circuit. The transistor is coupled to the output of the first amplifier circuit. The second amplifier circuit varies a current through the transistor to the output of the first amplifier circuit based on a difference between the first voltage and a second voltage at the output of the first amplifier circuit to supply leakage current drawn by load circuits.
G05F 1/575 - Régulation de la tension ou de l'intensité là où la variable effectivement régulée par le dispositif de réglage final est du type continu utilisant des dispositifs à semi-conducteurs en série avec la charge comme dispositifs de réglage final caractérisé par le circuit de rétroaction
90.
Systems and Methods for Simulating Hardened Circuitry via Virtual Interface
Embodiments herein are directed to systems and methods for elaborating and simulating hard intellectual property (IP) cores via virtual interface. Such a system may include a processing circuitry and a memory. The memory may include computer-readable instructions that the processing circuitry may execute to produce a simulation of soft logic circuitry, a simulation of hard logic circuitry, and a simulation wrapper around the simulation of hard logic circuitry to provide a virtual interface between the simulation of the soft logic circuitry and the simulation of the hard logic circuitry.
Integrated circuit devices, methods, and circuitry for configuring input/output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.
Systems or methods of the present disclosure may provide a dual bump design to support both high voltage input/output (HVIO) connections and medium speed input/output (MSIO) connections. The present disclosure includes an MSIO lane that couples to a first bump that couples to MSIO pins, a second bump that couples to an HVIO circuit, and a ball grid array (BGA) ball. The present disclosure also includes a multiplexer that selectively couples the MSIO pins to the BGA ball or the HVIO circuit to the BGA ball based on user input. As such, the MSIO lane may provide MSIO connections, HVIO connections, or both.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
An integrated circuit includes filter circuits that partition a wideband digital signal in a frequency domain to generate narrowband digital signals each having a different frequency band, digital-to-analog converter circuits that convert the narrowband digital signals to generate analog signals, and an analog combiner circuit that combines the analog signals into a single wideband analog signal.
The embodiment disclosed herein include a system for a data center that includes processing units (xPUs) and programmable logic devices. The xPUs may implement a design in hardware to perform specialized operations suited for the design. The programmable logic devices may implement different designs based on operations to be performed. For example, a schedule may be generated to process a workload received by the system. The schedule may include multiple phases that may be mapped to either the xPUs or the programmable logic devices based on an efficiency of performing operations of the phases using the xPU or the programmable logic device. In this way, the system may operate at maximum efficiency when processing the workload.
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
96.
DEVICE, METHOD AND SYSTEM FOR COMMUNICATING BETWEEN NETWORKED AGENTS VIA A CREDIT MANAGEMENT BUS
Techniques and mechanisms for dynamically changing a distribution of credits with which initiator agents of a network access a shared target resource of the network. In various embodiments, a target agent and multiple initiator agents are coupled to each other via a switched network, and further via a credit management bus (CMB). The target agent manages a credit-based scheme according to which the initiator agents share access to a target resource. Communications via the CMB enable the target agent to determine, during a runtime of the network, whether a given initiator agent has been allocated an excessive number of credits, or an insufficient number of credits. In another embodiments, the target agent changes the distribution of credits to the initiator agents by allocating credits via the CMB.
Integrated circuit devices, methods, and circuitry that program disaggregated dies and programmable logic devices at least partially in parallel are described herein. A host device may program a programmable logic device using a configuration bitstream having a first protocol and sent via a first portion (e.g., first layer) of a communication link. The host device may program disaggregated dies using image files having a second protocol and sent via a second portion (e.g., second layer) of a communication link. The host device may send the configuration data and the image files at a same or overlapping time since the data may be sent in separate layers of the communication link, thereby avoiding interference.
G06F 30/34 - Conception de circuits pour circuits reconfigurables, p. ex. réseaux de portes programmables [FPGA] ou circuits logiques programmables [PLD]
98.
OPTICAL CO-PACKAGING ON A GLASS SUBSTRATE WITH 3D DIE-STACKING
The substrate of an integrated circuit component comprises a multi-layer die structure conductively coupled to the substrate. The multi-die layered structure includes a first primary integrated circuit die attached to the substrate and communicatively coupled to a first photonic integrated circuit (PIC) die, and a second primary integrated circuit die vertically spaced from the first primary integrated circuit die and communicatively coupled to a second PIC die. The integrated circuit component further includes a first intermediate waveguide optically coupling a first PIC waveguide of the first PIC die to a first substrate waveguide in the substrate, and a second intermediate waveguide optically coupling a second PIC waveguide of the second PIC die to a second substrate waveguide in the substrate. The integrated circuit component may further include a third intermediate waveguide optically coupling the first PIC die to the second PIC die.
G02B 6/12 - Guides de lumièreDétails de structure de dispositions comprenant des guides de lumière et d'autres éléments optiques, p. ex. des moyens de couplage du type guide d'ondes optiques du genre à circuit intégré
99.
TECHNOLOGIES FOR AN OPTICAL INTERPOSER WITH ACTUATOR BEAMS
Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator beam underneath it, causing the actuator beam and the waveguides to be deflected. In this manner, the waveguides in the optical interposer can be positioned to align to waveguides in the PIC die.
Some embodiments include an apparatus having a supply node, a conductive pad, and an electrostatic discharge (ESD) protection circuitry. The ESD protection circuitry includes a transistor including levels of semiconductor materials separated from each other and located one over another over a substrate. Respective portions of the levels of semiconductor materials form part of a channel, a source terminal, and a drain terminal of the transistor. The transistor includes a conductive material separated from the channel by a dielectric material and surrounding at least part of the channel. At least a portion of the conductive material forms part of a gate terminal of the transistor. The gate terminal is coupled to the supply node. The source terminal is coupled to the supply node. And the drain terminal is coupled to the conductive pad.
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H02H 9/04 - Circuits de protection de sécurité pour limiter l'excès de courant ou de tension sans déconnexion sensibles à un excès de tension
