Abrégé

The present invention relates to the technical field of integrated circuits. Provided are a semiconductor structure and a manufacturing method therefor, and an electronic device. In the manufacturing method, by means of optimizing a process, after a first trench (141) is formed, a groove (142) extending in a direction parallel to a substrate (100) is formed on a side wall of the first trench (141); then, isolation trenches (121) are formed to expose part of a dummy gate structure (400) in the groove (142); during the process of etching to remove the dummy gate structure (400), the dummy gate structure which covers a side wall of the groove (142) is retained, such that after a semiconductor layer (510), a gate dielectric layer and a word line are formed, the semiconductor layer (510) in the groove (142) can be etched and removed on the basis of the isolation trenches (121), thereby preventing the semiconductor layer (510) remaining in the groove (142) from forming a parasitic device.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the field of microelectronic manufacturing technology, in particular to a SOT-MRAM memory cell and a method of manufacturing a SOT-MRAM memory cell. The SOT-MRAM memory cell includes a bottom electrode layer, a magnetic tunnel junction, an antiferromagnetic layer and a top electrode layer provided sequentially from bottom to top, where the magnetic tunnel junction includes a free layer, a tunneling layer and a pinning layer, the bottom electrode layer is a stack of odd number of layers, and the odd number of layers include at least one W metal layer and at least one Ta metal layer.

Classes IPC  ?

• H10N 50/10 - Dispositifs magnéto-résistifs
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]
• H10N 50/01 - Fabrication ou traitement
• H10N 50/20 - Dispositifs à courant commandé à polarisation de spin
• H10N 50/85 - Matériaux de la région active

Abrégé

A thin film transistor memory array based on a photonic crystal isolation dielectric, the thin film transistor memory array comprising: memory cells, which are arranged in rows and columns; and write word lines, write bit lines, read bit lines and ground lines, which connect the memory cells, wherein lines in a row direction and lines in a column direction are orthogonal; and a read transistor and a write transistor constituting a memory cell are both thin film transistors, isolation capacitors are provided in intersection areas of the lines in the row direction and the lines in the column direction, and isolation dielectrics in the isolation capacitors are photonic crystals. In the thin film transistor memory array, the photonic crystals are used to reduce parasitic capacitances of bit lines and word lines of a memory, so that the density of the memory array is improved, the read-write speed of the memory array is increased, and read-write disturbance is reduced.

Classes IPC  ?

• G11C 13/00 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage non couverts par les groupes , ou

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a first transistor and a second transistor which are vertically stacked; the first transistor comprises a first electrode (51), a second electrode (52), a first semiconductor layer (21), and a first gate electrode (26) which are sequentially stacked; the second transistor comprises a third electrode (53), a second semiconductor layer (22), and a second gate electrode (27) which are sequentially stacked on the side of the first gate electrode (26) facing away from a substrate (1); the second semiconductor layer (22) is connected to the third electrode (53) and the first gate electrode (26); the first semiconductor layer (21) comprises a first semiconductor sub-layer (211), a second semiconductor sub-layer (212) and a third semiconductor sub-layer (213); the second semiconductor layer (22) comprises a fourth semiconductor sub-layer (221), a fifth semiconductor sub-layer (222) and a sixth semiconductor sub-layer (223).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A thin film transistor, a memory, and a method of manufacturing a thin film transistor are provided, which relate to a field of semiconductor device technology. The thin film transistor includes a substrate; a gate on a surface of the substrate; an insulation layer covering the gate; a source and a drain; a channel between the insulation layer and the source and the drain, wherein the source and the drain are located on a surface of the channel away from the substrate; and an insulation dielectric layer between the source and the drain, wherein the insulation dielectric layer partially overlaps with the channel in a first direction, wherein the substrate, the gate, the insulation layer, the source and the drain, the channel, and the insulation dielectric layer are stacked in the first direction.

Classes IPC  ?

• H10D 30/67 - Transistors à couche mince [TFT]
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10D 30/01 - Fabrication ou traitement

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises a substrate (1), and at least one transistor provided on the substrate (1). The transistor comprises a gate electrode (26) and a semiconductor layer (23). The semiconductor layer (23) comprises a first semiconductor sub-layer (231) at least partially surrounding the gate electrode (26) and a second semiconductor sub-layer (232) arranged on the side of the first semiconductor sub-layer (231) facing away from the gate electrode (26). The doping concentration of the second semiconductor sub-layer (232) is greater than the doping concentration of the first semiconductor sub-layer (231). The second semiconductor sub-layer (232) comprises a first part (2321) and a second part (2322) arranged at an interval on the surface of the first semiconductor sub-layer (231) facing away from the gate electrode (26).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of integrated circuits, and relates to a memory manufacturing method, a memory, and an electronic device. In order to manufacture as many device units as possible on a limited substrate, the memory manufacturing method comprises: on a substate (100), forming a stack structure (200) in which first sub-layers (210) and second sub-layers (210) are alternately arranged; forming an isolation trench (130) to divide the stack structure (200) into strip-shaped structures (300); in a direction perpendicular to the substrate (100), forming first trenches (121) between adjacent first sub-layers (210); using the strip-shaped structures (300) to block trench walls of the first trenches (121); forming a first semiconductor channel (161) and a first gate dielectric layer (171) in each first trench (121); and removing all film layers outside the first trenches (121) by etching, thereby preventing conductive film layers remained outside the first trenches (121) from forming a parasitic device affecting the performance of the memory. The number of layers of a three-dimensional stack of a memory can be increased, and the integration density can be improved.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

Classes IPC  ?

• H01L 21/225 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase solide, p. ex. une couche d'oxyde dopée
• H01L 21/02 - Fabrication ou traitement des dispositifs à semi-conducteurs ou de leurs parties constitutives

Abrégé

Embodiments of the present disclosure relate to the technical field of storage, and provide a sense amplifier, a control method therefor, a storage array structure, and a memory. The sense amplifier comprises: a first signal amplification unit, wherein a first end and a second end of the first signal amplification unit are respectively adapted to be electrically connected to a first voltage end and a second voltage end, and a third end and a fourth end of the first signal amplification unit are respectively used as a first node and a second node; and a second signal amplification unit, wherein a first end, a second end, and a third end of the second signal amplification unit are respectively adapted to be electrically connected to a third voltage end, a fourth voltage end, and a bit line, and a fourth end of the second signal amplification unit is electrically connected to the first node. The sense amplifier is configured to amplify the voltage of the first node to a first voltage or a second voltage in a first signal amplification stage, and to write the second voltage or the first voltage back to a storage unit in a second signal amplification stage. The structure of the sense amplifier in the embodiments of the present disclosure can replace an edge reference array, and no additional reference array needs to be provided, thereby reducing the size of chips and reducing the chip cost.

Classes IPC  ?

• G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées

Abrégé

A memory and an access method therefor, and an electronic device. The memory comprises a multi-layer storage array stacked in a third direction perpendicular to a substrate, the storage array comprising a plurality of storage units (100) distributed in an array. The memory further comprises a plurality of second word lines (WL2) corresponding to rows of the multi-layer storage array, and a plurality of first word lines (WL1) corresponding to columns of the multi-layer storage array. Each storage unit comprises a transistor, the transistor comprises a first gate electrode (G1) and a second gate electrode (G2), the first gate electrode (G1) is connected to the first word line (WL1) corresponding to the column where the storage unit is located, and the second gate electrode is connected to the second word line (WL2) corresponding to the row where the storage unit is located.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 11/4097 - Organisation de lignes de bits, p. ex. configuration de lignes de bits, lignes de bits repliées

Abrégé

The present application relates to the technical field of semiconductors. Disclosed in the present disclosure are a semiconductor structure and a preparation method therefor, and an electronic device. The method comprises: providing a substrate, and forming a first laminated structure (104) on the substrate; forming a first mask layer (112) on the first laminated structure (104); using the first mask layer (112) as a mask, and forming in the first laminated structure (104) a first sacrificial layer (218) that extends from the upper surface of the first laminated structure (104) to the upper surface of a first electrically conductive layer (202); removing the first mask layer (112), and alternately forming second mask layers (114) on the first sacrificial layer (218); using the second mask layers (114) as masks, and removing the exposed first sacrificial layer (218); performing lateral etching to remove part of a channel sacrificial layer (204), so as to form first recesses (306) and channel layers (116); removing the second mask layers (114); and performing lateral etching to remove the remaining channel sacrificial layer (204), so as to form second recesses (310) and gate layers (120) that surround the channel layers (116). The requirements for the material of mask layers are reduced, the cost is low, and the manufacturing process is simple.

Classes IPC  ?

• H10B 41/27 - Dispositifs de mémoire morte reprogrammable électriquement [EEPROM] comprenant des grilles flottantes caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U
• H10B 43/27 - Dispositifs EEPROM avec des isolants de grille à piégeage de charge caractérisés par les agencements tridimensionnels, p. ex. avec des cellules à des niveaux différents de hauteur la région de source et la région de drain étant à différents niveaux, p. ex. avec des canaux inclinés les canaux comprenant des parties verticales, p. ex. des canaux en forme de U

Abrégé

A memory cell, a memory and an access method therefor, and an electronic device. The memory comprises: multiple layers of memory arrays stacked in a direction perpendicular to a substrate, and a plurality of first word lines (WL1) in one-to-one correspondence with the multiple layers of memory arrays. The memory arrays comprise a plurality of memory cells distributed along the arrays, and a plurality of second word lines (WL2) corresponding to rows of the multiple layers of memory arrays. Each memory cell comprises a transistor, the transistor comprising a first gate (G1) and a second gate (G2); the first gates (G1) of memory cells of the same layer are connected to first word lines (WL1) corresponding to the layer, and the second gates (G2) of memory cells in the same row of different layers are connected to second word lines (WL2) corresponding to the row.

Classes IPC  ?

• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage
• G11C 8/14 - Organisation de lignes de motsDisposition de lignes de mots

Abrégé

Disclosed are a semiconductor device, a manufacturing method therefor, and an electronic equipment, the semiconductor device includes: at least one vertical channel transistor disposed on a base substrate, and a bit line; the transistor includes a semiconductor pillar extending along a direction perpendicular to the base substrate, the semiconductor pillar includes a channel region, and a first region and a second region respectively disposed on two sides of the channel region, the second region is disposed between the base substrate and the first region, the bit line is in contact with the second region, and a plasma dopant concentration of a contact surface between the second region and the bit line is greater than or equal to 1e14 atoms/square centimeter.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/223 - Diffusion des impuretés, p. ex. des matériaux de dopage, des matériaux pour électrodes, à l'intérieur ou hors du corps semi-conducteur, ou entre les régions semi-conductricesRedistribution des impuretés, p. ex. sans introduction ou sans élimination de matériau dopant supplémentaire en utilisant la diffusion dans ou hors d'un solide, à partir d'une ou en phase gazeuse
• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H10D 84/01 - Fabrication ou traitement

Abrégé

The present disclosure relates to the technical field of semiconductors, and relates to a semiconductor device structure and a preparation method therefor. The semiconductor device structure comprises: a substrate (10): a stack structure located on the substrate (10) and formed by alternately stacking interlayer dielectric layers (20) and conductive layers (40); and at least one through hole (11) penetrating the stack structure, a first word line (61), a first channel layer, a second word line (62), a second channel layer, and conductive connection layers (63) being arranged in the through hole (11). The first word line (61) and the second word line (62) both extend in a second direction perpendicular to the substrate (10) and are spaced apart in a first direction parallel to the substrate (10). The first channel layer surrounds a side wall of the first word line (61) and has a break between adjacent conductive layers (40). The second channel layer surrounds a side wall of the second word line (62) and has a break between adjacent conductive layers (40). The conductive connection layers (63) are located between adjacent conductive layers (40) and are integrally connected to both the first word line (61) and the second word line (62) in the first direction. By using the semiconductor device structure of the present disclosure, a driving current can be increased.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors, in particular to a semiconductor device and a manufacturing method therefor, a transistor and an electronic device, which are used for solving the technical problems of how to improve storage density and reduce manufacturing costs. The manufacturing method for the semiconductor device comprises: alternately stacking a plurality of insulating layers and metal layers on a substrate (100) to form a stacked structure; and forming a plurality transistors arranged in a multi-layer array in the stacked structure (104). Each transistor (104) comprises a first isolation layer (106), a second isolation layer (107), a semiconductor layer (108), a gate dielectric layer (109) and a gate electrode (110), the first isolation layer (106) and the second isolation layer (107) being opposite to each other and spaced apart in a first direction parallel to the substrate (100). The semiconductor layer (108) comprises a first sub-semiconductor layer (111) and a second sub-semiconductor layer (112) respectively covering the two side walls of the first isolation layer (106) facing away from each other in the first direction, and a third sub-semiconductor layer (113) and a fourth sub-semiconductor layer (114) respectively covering the two side walls of the second isolation layer (108) facing away from each other in the first direction. The gate dielectric layer (109) covers the semiconductor layer (108), and the gate electrode (110) covers the gate dielectric layer (109).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A CXL memory module, a controller, a method for accessing data, and a storage system are provided, which relate to data storage technologies. The CXL memory module includes a controller and a group of memory chips connected to the controller. The controller has a KV interface based on a CXL protocol. The controller is configured to receive a KV instruction sent by an external device through the KV interface, store object-based data into a memory chip or acquire object-based data from a memory chip.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

The present disclosure relates to the technical field of storage, and to a semiconductor device, a memory and a manufacturing method therefor, and an electronic device, for use in improving the performance and reliability of the semiconductor device and the memory. The semiconductor device comprises: a first gate (11), a second gate (21), a third gate (31), a first semiconductor layer (14), a second semiconductor layer (24), and a common source line (SL). The first semiconductor layer (14) is arranged in insulated fashion around the periphery of a side wall of the first gate (11). The second gate (21) is located on the side of the first semiconductor layer (14) facing away from the first gate (11), and comprises: a first portion (A) electrically connected to the first semiconductor layer (14), and a second portion (B) located on the side of the first portion (A) facing away from the first semiconductor layer (14) and electrically connected to the first portion (A). The second semiconductor layer (24) is arranged in insulated fashion around the periphery of a side wall of the second portion (B) and the side of the second portion (B) facing away from a bottom wall of the first portion (A). The third gate (31) and the common source line (SL) are spaced and arranged in insulated fashion around the periphery of the second semiconductor layer (24) facing away from the side wall of the second portion (B).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A CXL memory module, a controller, a method for accessing data and a storage system, relating to the data storage technology. The CXL memory module comprises a controller and a group of memory chips connected to the controller, and the controller is provided with a CXL protocol-based KV interface. The controller is configured to receive a KV instruction sent by an external device by means of the KV interface, and store object-based data into the memory chips or take out the object-based data from the memory chips.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

WRWRRR) further comprises: a third gate electrode (31), which is insulatedly provided on a side of a connection portion between the second source-drain electrode (13) and the second gate electrode (21). The third gate electrode (31) is electrically connected to a read word line (WL2), the fourth source-drain electrode (23) is electrically connected to a read bit line (BL2), and the third source-drain electrode (22) is electrically connected to a common source line (SL).

Classes IPC  ?

• G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice

Abrégé

The embodiments of the present application relate to a three-dimensional memory and a manufacturing method therefor, and an electronic device. The three-dimensional memory comprises a plurality of layers of storage units stacked at intervals in a third direction, wherein each layer of storage units comprises a plurality of storage units arranged at intervals in a second direction, each storage unit comprises a transistor, and a first direction and the second direction intersect and are both perpendicular to the third direction; and the transistor comprises a gate (60) and a semiconductor layer (50) extending in the first direction, and the gate (60) is arranged around the circumferential side wall of the semiconductor layer (50); a plurality of bit lines (90) extending in the third direction, wherein each bit line (90) is connected to the transistors in a column of storage units arranged in the third direction; and a plurality of word lines (70) extending in the second direction, the gates (60) of the transistors in a column of storage units arranged in the second direction being connected to form a word line (70).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device, which belong to the technical field of semiconductors. The semiconductor device comprises: a plurality of transistors, which are distributed at different layers and are stacked in the direction perpendicular to a substrate (1), wherein each transistor comprises a gate electrode (26) and a semiconductor layer (23); a bit line (30), which extends in the direction perpendicular to the substrate (1) and is connected to a plurality of semiconductor layers (23) of the plurality of transistors; and a word line (40), which extends in a first direction (X) parallel to the substrate (1), and comprises the gate electrodes (26) and connection electrodes (27) that are distributed in the first direction (X), wherein the connection electrodes (27) extend in the first direction (X) and are in contact with the gate electrodes (26). Side walls of the semiconductor layers extend in a second direction (Y) parallel to the substrate (1), the gate electrodes (26) are insulated from the semiconductor layers (23), and the first direction (X) intersects with the second direction (Y).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a plurality of conductive layers which are stacked vertically at intervals, each conductive layer comprising a common connection area and a memory cell area located on at least one side of the common connection area; a plurality of through holes which are formed in the common connection areas and are arranged at intervals in the extension direction of the common connection areas, wherein the through holes pass through the plurality of conductive layers, and the number of the through holes is equal to the number of the conductive layers; and a plurality of conductive columns, wherein one conductive column is correspondingly arranged in one through hole, and one conductive column is correspondingly electrically connected to one conductive layer.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
• G11C 11/403 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe

Abrégé

Provided in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor, and a memory. The semiconductor structure comprises: a lower group of electrically-conductive layers and an upper group of electrically-conductive layers located on the lower group of electrically-conductive layers, wherein the two groups of electrically-conductive layers have the same number of layers, and each electrically-conductive layer is provided with a common connecting area and a storage unit area located on at least one side of the common connecting area; a plurality of through holes, which are provided in the common connecting area and are arranged at intervals in the extending direction of the common connecting area, wherein the through holes penetrate the plurality of electrically-conductive layers, and the number of through holes is equal to the number of layers of the lower group of electrically-conductive layers; a plurality of electrically-conductive posts, wherein one electrically-conductive post is correspondingly arranged in one through hole, the electrically-conductive post comprises a lower electrically-conductive section and an upper electrically-conductive section, which are separated from each other by an insulating section, one lower electrically-conductive section is correspondingly electrically connected to one electrically-conductive layer of the lower group of electrically-conductive layers, and one upper electrically-conductive section is correspondingly electrically connected to one electrically-conductive layer of the upper group of electrically-conductive layers.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice
• G11C 11/403 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge commune à plusieurs cellules de mémoire, c.-à-d. rafraîchissement externe

Abrégé

Provided are a semiconductor device and a preparation method therefor and an electronic device. The semiconductor device comprises a substrate, and a storage part, a wiring part, and a peripheral circuit part which are arranged on one side of the substrate; the positions of the storage part, the wiring part, and the peripheral circuit part are different in a direction perpendicular to the substrate; the storage part comprises at least two sub-storage arrays, and the at least two sub-storage arrays are sequentially arranged in a first direction parallel to the substrate; each sub-storage array comprises at least one storage unit, and the storage unit comprises a transistor; the wiring part comprises at least one shared word line; and in the at least two sub-storage arrays, the gates of the transistors of the storage units located in different sub-storage arrays are electrically connected to the same shared word line, and the shared word line is connected to the peripheral circuit part.

Classes IPC  ?

• G11C 5/06 - Dispositions pour interconnecter électriquement des éléments d'emmagasinage

Abrégé

A semiconductor device, a manufacturing method therefor and an electronic apparatus. The semiconductor device comprises a plurality of storage units which are distributed in different layers, are stacked in the direction perpendicular to a substrate and are periodically distributed, each layer comprising a plurality of columns of storage units; and a relaxation buffer layer which is located between the substrate and the storage units.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou

Abrégé

The present disclosure provides a three-dimensional memory and a manufacturing method therefor, and an electronic device. The three-dimensional memory of the present disclosure comprises multiple layers of storage unit arrays stacked in a third direction, and a word line. Each layer of storage unit array comprises a first column of storage units and a second column of storage units adjacent to the first column of storage units. The first column of storage units and the second column of storage units are arranged in a first direction. The first column of storage units is connected to a bit line extending in a second direction. The second column of storage units is connected to another bit line extending in the second direction. The storage units each comprise a transistor and a capacitor. The capacitor comprises a first electrode and a second electrode. The transistor is electrically connected to the first electrode. The word line extends in the third direction. The transistor has a channel region only on at least one side of the word line connected thereto in the second direction. The first direction intersects with the second direction. The first direction and the second direction are both perpendicular to the third direction. Each channel region of the first column of storage units or the second column of storage units and the connected bit line are different regions of the same film layer. The film layer is a monocrystalline silicon layer. The bit line region of the film layer comprises a metal silicide.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a fabrication method therefor, and an electronic apparatus, which relate to the technical field of semiconductors and aim to solve the problem of how to avoid surface oxidation of source/drain electrodes. The fabrication method for a semiconductor device comprises: forming a through hole (T) in a stacked structure, wherein the through hole (T) runs through a second source/drain electrode (2) and an interlayer dielectric layer (5) in a direction perpendicular to a substrate (10), and extends to at least a first source/drain electrode (1); exposing at least the interlayer dielectric layer (5) to a side wall of the through hole (T), and forming on the side wall a self-assembled monolayer (6) having an adsorption relationship with the interlayer dielectric layer (5), so that the first source/drain electrode (1) and the second source/drain electrode (2), which are not covered by the self-assembled monolayer (6), are exposed in the through hole (T); by using the self-assembled monolayer (6) as a mask, forming contact layers (3) on the first source/drain electrode (1) and the second source/drain electrode (2); removing the self-assembled monolayer (6); isolating the contact layer (3) on the first source/drain electrode (1) from the contact layer (3) on the second source/drain electrode (2) by means of the interlayer dielectric layer (5); and forming a semiconductor layer (4) on the side wall in the through hole (T), wherein the semiconductor layer (4) is connected to the contact layers (3) on the first source/drain electrode (1) and the second source/drain electrode (2).

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/76 - Réalisation de régions isolantes entre les composants
• H01L 21/336 - Transistors à effet de champ à grille isolée

Abrégé

A semiconductor device and a method for manufacturing the same. A substrate is provided. A first source-drain layer, a channel layer, and a second source-drain layer are sequentially stacked on the substrate. Both a gate dielectric layer and a gate structure surround the channel layer laterally. The gate structure includes a first portion extending laterally and a second portion extending upward from a periphery of the first portion. A second portion is located at a periphery of the second source-drain layer. A spacer layer is formed at an outer sidewall of the gate structure. The gate structure is etched to reduce a thickness of the gate structure. A sacrificial structure covering the gate structure is formed, and a capping layer covering the second source-drain layer, the sacrificial structure, and the spacer layer is formed. Thereby, the sacrificial structure is located at the periphery of the second source-drain layer and enclosed by the spacer layer. The capping layer is etched to obtain a first contact hole reaching the sacrificial structure. The sacrificial structure at the bottom of the first contact hole is removed to form a gap under the first contact hole. A first contact structure is formed in the first contact hole and the gap. Self-alignment between a bottom of the first contact structure and the gate structure is achieved, and the device has higher reliability.

Classes IPC  ?

• H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H01L 29/786 - Transistors à couche mince

Abrégé

The present disclosure relates to a three-dimensional memory chip array circuit, a three-dimensional memory and an electronic device. The three-dimensional memory chip array circuit comprises at least one layer of functional circuit (1) stacked in a direction perpendicular to a substrate. The functional circuit (1) comprises a plurality of cell array circuits (2) arranged in rows and columns in a direction parallel to the substrate. Selection switches (3) of at least one cell array circuit (2) are arranged corresponding to memory cell selection lines (4), wherein each selection switch (3) is configured such that a first input end is connected to a corresponding row selection signal line (Lr), a second input end is connected to a corresponding column selection signal line (Lc), and an output end is connected to a corresponding memory cell selection line (4) to jointly control the turning-on or turning-off of the selection switch (3) via the row selection signal line (Lr) and the column selection signal line (Lc), so as to select or deselect the corresponding memory cell selection line (4).

Classes IPC  ?

• G11C 16/06 - Circuits auxiliaires, p. ex. pour l'écriture dans la mémoire
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 16/24 - Circuits de commande de lignes de bits
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The manufacturing method comprises: alternately depositing sacrificial layers and insulating layers to obtain a stack structure; forming multiple through holes distributed at intervals in the stack structure, and forming dummy word lines in the through holes; forming, at intervals of two through holes, a first trench passing through the stack structure, wherein multiple insulating layers and multiple sacrificial layers which are alternately stacked are distributed between any two adjacent first trenches; etching back the insulating layers in each first trench to form multiple grooves, wherein the two grooves in the two first trenches corresponding to each insulating layer expose parts of the side walls of the dummy word lines, respectively; forming conductive layers in the two grooves corresponding to each insulating layer, wherein the conductive layer in each groove surrounds two exposed dummy word lines; and separating the conductive layer surrounding each dummy word line to form a first electrode and a second electrode of a transistor.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/82 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants

Abrégé

A semiconductor device, manufacturing method therefor, and electronic equipment are provided. The manufacturing method includes: alternately depositing sacrificial layers and insulation layers to obtain a stacked structure; forming in the stacked structure a plurality of via holes distributed at intervals, and forming dummy word lines in the via holes; forming a first trench penetrating through the stacked structure every two via holes apart; forming a plurality of grooves by re-etching the plurality of insulation layers within the first trench, wherein two grooves of each insulation layer in two first trenches respectively expose partial side walls of a dummy word line; forming conductive layers within the two grooves corresponding to each insulation layer, wherein a conductive layer within each groove surrounds two exposed dummy word lines; and disconnecting a conductive layer surrounding a dummy word line to form a first electrode and a second electrode of a transistor.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 23/528 - Configuration de la structure d'interconnexion

Abrégé

Provided is a memory. The memory includes: a plurality of memory cells, word lines, and bit lines; wherein each of the memory cells comprises: a first transistor, wherein a first source of the first transistor is electrically connected to the bit line; a second transistor, connected in series to the first transistor; and a capacitor, electrically connected to a second drain of the second transistor. The first transistor and the second transistor are both n-type transistors or p-type transistors, and a first gate of the first transistor and a second gate of the second transistor are electrically connected to the word line.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
• H01L 29/786 - Transistors à couche mince

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate (1), and word lines (40) passing through the different layers and extending in the direction perpendicular to the substrate (1). Each transistor comprises a first electrode (51), a second electrode (52), and a semiconductor layer (23) surrounding the side wall of the corresponding word line (40). The semiconductor layer (23) comprises a first portion (231) in contact with the first electrode (51) or the second electrode (52), and a second portion (232) located between the first electrode (51) and the second electrode (52); the first portion (231) extends only in the direction perpendicular to the substrate (1); the second portion (232) comprises a first extension portion (2321) extending in the direction perpendicular to the substrate (1) and a second extension portion (2322) extending from the first extension portion in a direction moving away from the side wall of the corresponding word line (40) and parallel to the substrate (1); and a plurality of semiconductor layers (23) are disconnected.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided in the present application are a memory and a read-write method therefor, and an electronic device. The memory comprises a three-dimensional storage array located on one side of a substrate, wherein the three-dimensional storage array comprises several storage array layers; each storage array layer comprises storage units, bit lines perpendicular to the substrate, and word lines parallel to the substrate; each storage array layer further comprises a selection circuit, a first select line, a second select line, several third select lines and several low-level potential ends; the first select line and the second select line are parallel to the substrate; the third select lines and the word lines are arranged in one-to-one correspondence; the selection circuit is connected to the word lines, the first select line, the second select line, the several third select lines and the several low-level potential ends; and a plurality of selection circuits are used for determining selected storage array layers on the basis of the level states of the first select lines and the second select lines of corresponding storage array layers, and determining, on the basis of the level states of the third select lines of the selected storage array layers, word lines selected during a read-write operation.

Classes IPC  ?

• G11C 11/40 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors
• H01L 27/10 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration répétitive

Abrégé

Provided are a semiconductor device and manufacturing method thereof, and an electronic device. The semiconductor device includes multiple storage cells distributed in a direction perpendicular to a base substrate, the multiple storage cells include multiple transistors and capacitors distributed in different layers and stacked in the direction perpendicular to the base substrate; a word line penetrating different layers and extending in the direction perpendicular to the base substrate; a transistor includes a first source/drain electrode, a second source/drain electrode and a semiconductor layer surrounding a sidewall of the word line; first insulating layers and conductive layers alternately distributed in the direction perpendicular to the base substrate, at least one first hole penetrating the different layers; and the second electrode of the capacitor includes an inner electrode disposed in the first hole on the first electrode.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor apparatus and a manufacturing method therefor, and an electronic device, which relate to apparatus design and manufacturing in the technical field of semiconductors. The semiconductor apparatus comprises: a plurality of storage units, wherein the plurality of storage units are distributed in a direction perpendicular to a substrate (1) and comprise a plurality of transistors and capacitors, which are distributed on different layers and are stacked in the direction perpendicular to the substrate (1); a word line (40), which penetrates through the different layers and extends in the direction perpendicular to the substrate (1), each transistor comprising a first source/drain electrode (51), a second source/drain electrode (52) and a semiconductor layer (23) surrounding a side wall of the word line (40); first insulating layers and electrically conductive layers which are alternately distributed in the direction perpendicular to the substrate (1); and at least one first hole (K1), which penetrates through the different layers. A second electrode (42) of each capacitor comprises an inner electrode provided in the first hole (K1), which is formed in a first electrode (41).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate (1); and a word line (40) passing through the different layers and extending in the direction perpendicular to the substrate (1). The transistors each comprise a first electrode (51) and a semiconductor layer (23) surrounding the side wall of the word line (40); the semiconductor layer (23) comprises a first groove having an opening facing away from the word line (40); and the first electrode (51) is located in the first groove and is connected to the semiconductor layer (23).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to a substrate (1); and word lines (40) passing through the different layers and extending in the direction perpendicular to the substrate (1). Each transistor comprises a first electrode (51), a gate insulating layer (24), a semiconductor layer (23) surrounding the side walls of the word lines (40), and a protective layer (32) arranged between the semiconductor layer (23) and the side wall of the gate insulating layer (24), wherein the first electrode (51) is arranged in a first groove of the semiconductor layer (23).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

Abrégé

A 3D stacked semiconductor device, a manufacturing method therefor, and an electronic equipment are disclosed. The 3D stacked semiconductor device includes a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a base substrate; a word line penetrating through the transistors of the different layers; and a plurality of protective layers corresponding to the plurality of transistors respectively; wherein each transistor includes a semiconductor layer surrounding a side wall of the word line, a gate insulation layer disposed between the side wall of the word line and the semiconductor layer, a plurality of semiconductor layers of the plurality of transistors are disposed at intervals in a direction in which the word line extends; each of the protective layers respectively surrounds and covers an outer side wall of a corresponding semiconductor layer, and two adjacent protective layers are disconnected from each other.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular to a semiconductor structure, a memory cell and a manufacturing method therefor, a memory, and an electronic device, which are used for enhancing the gate control capability and improving the storage density. The semiconductor structure comprises an active pillar (2), a first gate (3), and a second gate (4), and the active pillar (2) is located in a substrate (1) and extends in a direction perpendicular to the substrate (1); and the top surface of the active pillar (2) is provided with a first accommodating hole (H1) extending towards the bottom surface in the axial direction of the active pillar (2); the first gate (3) fills the first accommodating hole (H1); and the second gate (4) is located on the outer side wall of the active pillar (2).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A vertical transistor, and a memory cell and a manufacturing method therefor are provided. The vertical transistor includes: a source electrode disposed on a substrate; a drain electrode which is disposed at a side, away from the substrate, of the source electrode; and a gate electrode and a semiconductor layer, which are in the same layer, and are disposed between the source electrode and the drain electrode in a first direction which is perpendicular to the substrate. The gate electrode at least comprises a column-shaped first gate electrode extending in the first direction. The semiconductor layer comprises a first semiconductor layer and a second semiconductor layer which are in the same layer and spaced apart from each other, and the first gate electrode is disposed between the first semiconductor layer and the second semiconductor layer.

Classes IPC  ?

• H01L 29/786 - Transistors à couche mince
• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]

Abrégé

A chip and a manufacturing method therefor, and an electronic device. The chip comprises: a pixel chip layer (10), comprising a plurality of pixel units, each pixel unit at least comprising a photoelectric conversion unit (110), a pass transistor (120), a source follower (150), and a floating diffusion portion (130); a memory chip layer (20) arranged below the pixel chip layer (10) and comprising a plurality of memories, wherein each memory comprises a transistor and a capacitor (290) that are vertically stacked; and a logic circuit chip layer (30) arranged below the memory chip layer (20) and comprising a plurality of logic circuits for controlling read and write of the memories, wherein one pixel unit in the pixel chip layer (30) is directly connected to some of the capacitors (290) of the memory chip layer (20).

Classes IPC  ?

• H01L 27/146 - Structures de capteurs d'images

Abrégé

A memory and a manufacturing method therefor, and an electronic device. The memory comprises a substrate and a plurality of memory cells stacked in a direction perpendicular to the substrate. Each memory cell comprises a transistor. The transistor comprises a semiconductor layer (14), a first electrode (11), a second electrode (12), and a gate electrode (13). The first electrode (11) is connected to the second electrode (12) by means of the semiconductor layer (14). The semiconductor layer (14), the first electrode (11), and the second electrode (12) are arranged in the same layer. The gate electrode (13) surrounds the semiconductor layer (14), and a gate insulating layer (21) is arranged between the gate electrode (13) and the semiconductor layer (14). The wrap-around gate can effectively enhance the control capability of the gate electrode on the transistor.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The embodiments of the present disclosure relate to a semiconductor device structure and a preparation method therefor, and an electronic device, which relate to the field of semiconductors, and are used for simplifying the preparation process of the semiconductor device structure and improving the space utilization rate. The semiconductor device structure comprises: a substrate (10), a transistor (20) array, and a plurality of capacitors (30). The transistor (20) array is located on the substrate (10), and the transistor (20) array comprises a plurality of transistors (20), wherein the plurality of transistors (20) are arranged at intervals in a first direction, a second direction and a third direction respectively. The first direction is perpendicular to the upper surface of the substrate (10), the second direction and the third direction are both parallel to the upper surface of the substrate (10), and the second direction intersects with the third direction. One electrode of at least one capacitor (30) surrounds one transistor (20).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor preparation method, comprising: sequentially stacking a first silicon film layer (11), a germanium-silicon film layer (12) and a second silicon film layer (13) on a silicon substrate (00); etching the silicon substrate (00), the first silicon film layer (11), the germanium-silicon film layer (12) and the second silicon film layer (13) in a bit line direction to form a first etched groove, filling the first etched groove with a metal material (20), and performing annealing to generate a bit line; etching the second silicon film layer (13) and the germanium-silicon film layer (12) in a word line direction to form a second etched groove, and after a channel is generated on the basis of the germanium-silicon film layer (12), filling the second etched groove with a gate material (30) to form a word line; and depositing a low-K material (40) in the first and second etched grooves and on the second silicon film layer (13), and forming an air gap by means of etching the low-K material (40) and depositing a silicon dielectric material (50) on the top, so as to isolate the gate material (30), such that a vertical gate-all-around transistor is obtained. Further disclosed are a transistor array and an electronic device.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

The present application belongs to the technical field of semiconductors. Disclosed are a transistor preparation method and an electronic device. The method comprises: etching a first silicon layer (301), a silicon germanium layer (302) and a second silicon layer (303), so as to form a plurality of first silicon pillars (304) in a first direction; etching the first silicon layer (301), the silicon germanium layer (302) and the second silicon layer (303) according to a plurality of columns of second masks (305); forming laterally epitaxial silicon on the first silicon layer (301), a lateral groove and the second silicon layer (303); depositing a gate material above the first silicon layer (301); performing anisotropic etching of the gate material according to a plurality of side walls (305-1), so as to form a plurality of second silicon pillars (306); and forming a vertical gate-all-around transistor on the basis of the plurality of second silicon pillars (306). The method prevents a source/drain from being contaminated with metal.

Classes IPC  ?

• H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
• H01L 29/00 - DISPOSITIFS À SEMI-CONDUCTEURS NON COUVERTS PAR LA CLASSE - Détails des corps semi-conducteurs ou de leurs électrodes

Abrégé

A transistor manufacturing method and an electronic device. The method comprises: stacking a first silicon layer (301), a silicon germanium layer (302), and a second silicon layer (303) on a silicon substrate (300); forming a plurality of columns of first masks (304) on the second silicon layer (303) in a first direction; etching the second silicon layer (303) according to the plurality of columns of first masks (304), and covering the surfaces of the etched second silicon layer (303) and the plurality of columns of first masks (304) with a first isolation material (305); etching the silicon substrate (300), the first silicon layer (301), the silicon germanium layer (302), and the second silicon layer (303) according to the plurality of columns of first masks (304) to form a plurality of first silicon pillars (307); forming a plurality of columns of second masks (308) on the plurality of first silicon pillars (307) in a second direction; etching the first silicon layer (301), the silicon germanium layer (302), and the second silicon layer (303) according to the plurality of columns of second masks (308); depositing a gate material in an etching area of the silicon germanium layer (302) to form a plurality of second silicon pillars (309); and etching the first isolation material (305) covered by the plurality of second silicon pillars (309). Therefore, a source/drain is prevented from being contaminated by metal.

Classes IPC  ?

• H01L 21/336 - Transistors à effet de champ à grille isolée
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée

Abrégé

Provided in the embodiments of the present application are a memory cell, a memory and a manufacturing method therefor, and an electronic device. The present application relates to the technical field of semiconductors. The memory cell comprises a vertical transistor. The vertical transistor comprises: a semiconductor column extending in the direction perpendicular to a substrate, wherein the semiconductor column comprises a drain region, a channel region and a source region which are sequentially arranged; a gate insulating layer; and a gate electrode, wherein at least part of the gate insulating layer and the gate electrode are sequentially arranged on the periphery of the channel region of the semiconductor column. The vertical transistor involves at least one of the following: the dielectric constant of the gate insulating layer close to the source region is greater than the dielectric constant of the gate insulating layer close to the drain region; and the work function of the gate electrode close to the source region is greater than the work function of the gate electrode close to the drain region. The embodiments of the present application can inhibit the turning-on of a parasitic triode, and thus electric leakage can be reduced.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/76 - Dispositifs unipolaires
• H01L 21/28 - Fabrication des électrodes sur les corps semi-conducteurs par emploi de procédés ou d'appareils non couverts par les groupes

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a substrate (101); a second bonding layer (22), which is arranged on the substrate (101); a first bonding layer (21), which is arranged on the side of the second bonding layer (22) away from the substrate (101); bit lines (13), which are arranged on the side of the first bonding layer (21) away from the substrate (101); and semiconductor pillars (50), which are arranged on the side of the bit lines (13) away from the substrate (101), wherein each semiconductor pillar (50) comprises a first electrode (51), a channel (52) and a second electrode (53), the first electrode (51) being electrically connected to the bit lines (13); and the bit lines (13) of the semiconductor device have a uniform and tight internal structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic apparatus, relating to, but not limited to, the technical field of storage. The manufacturing method for the semiconductor device comprises: forming a first metal silicide thin film on a first silicon substrate (71); forming a second metal silicide thin film on a second silicon substrate (101); using a flip-chip bonding mode to bond the first metal silicide thin film of the first silicon substrate (71) with the second metal silicide thin film of the second silicon substrate (101), such that the first metal silicide thin film and the second metal silicide thin film form a metal silicide layer (78); using an etching process to etch the metal silicide layer (78) so as to form linear bit lines (13); and making the first silicon substrate (71) form semiconductor columns (50). The present disclosure solves the problems of circuit breaking of the bit lines (13), poor contact between the bit lines (13) and the semiconductor columns (50), etc., and ensures the uniformity of the heights of the semiconductor columns (50).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A memory cell, an array read-write method, a control chip, a memory, and an electronic device. The memory cell comprises: a first transistor (TR_R) and a second transistor (TR_W); the first transistor comprises a first electrode, a second electrode, a third electrode, and a fourth electrode; the third electrode is a first gate, and the fourth electrode is a second gate; the second transistor comprises a fifth electrode, a sixth electrode, and a seventh electrode; the seventh electrode is a third gate; the first electrode is connected to a read bit line, the second electrode is connected to a reference signal, the first gate is connected to a read word line, the second gate is connected to the fifth electrode; the sixth electrode is connected to a write bit line, the third gate is connected to a write word line.

Classes IPC  ?

• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits
• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

A method for implementing a universal content addressable memory on the basis of N-type and P-type ferroelectric field effect transistors, which relates to the technical fields of novel storage and computation. According to the method, the complementary characteristics of an N-type FeFET and a P-type FeFET are utilized, so that it is possible to simultaneously achieve the functions of a TCAM, MACM and ACAM without extra hardware overhead. Moreover, a simpler search operation is provided, so that the storage density and search energy efficiency of a CAM are improved. When quantized into an MCAM that stores multi-level entry states, the CAM also has the ability to compress entry states, allowing the storage density of the CAM to be further improved, which is of great significance for CAM-based table lookup search operations.

Classes IPC  ?

• G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: the storage unit comprises a transistor and a capacitor. The transistor comprises a channel, a first electrode, a second electrode, and a gate (13); the second electrode is connected to a bit line; the first electrode is connected to the capacitor; and the gate (13) surrounds the channel and is connected to the channel by means of a gate insulating layer (21). The capacitor comprises a first capacitor electrode, a second capacitor electrode (32) and a capacitor dielectric layer (33); the first capacitor electrode is connected to the first electrode; and the first capacitor electrode, the first electrode, the channel, and the second electrode are of integrated structures (10), and are formed of a same metal oxide conductive material. The semiconductor device of the present disclosure reduces the production costs, is easy to manufacture, and improves the performance of semiconductor devices.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and in particular relates to a memory and a preparation method therefor, and an electronic device, which are used for reducing the processing complexity and costs of a prepared product while improving the data bandwidth each time the prepared product is accessed. The memory comprises a plurality of memory cells 100 stacked in the thickness direction perpendicular to the surface of a substrate (10); a write word line (20) and a read word line (30), both extending in a second direction parallel to the surface of the substrate (10); a write bit line (60) and a read bit line (90), both extending to the substrate (10) in a direction perpendicular to the substrate (10); a write transistor (70), comprising a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction; a read transistor (101), comprising a back gate and a source contact region, a channel region, and a drain contact region sequentially distributed in the second direction, the back gate being located between the write word line (20) and the read transistor (101).

Classes IPC  ?

• G11C 5/02 - Disposition d'éléments d'emmagasinage, p. ex. sous la forme d'une matrice

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises one or more layers of memory cells, which are vertically stacked in a third direction, word lines (90), which extend in the third direction, and bit lines (100), which extend in a second direction and at least partially surround the word lines (90), wherein the multiple layers of vertically stacked memory cells share the same word line (90), and are connected to different bit lines (100); semiconductor layers (70) of transistors of the memory cells extend in the third direction and all surround the word lines (90); first electrodes (200) of capacitors of the memory cells extend in a first direction and at least partially surround the semiconductor layers (70), and the first direction and the second direction intersect with each other and are both located in a plane perpendicular to the third direction; the first electrodes (200) and the bit lines (100) respectively surround different regions of side walls of the semiconductor layers (70) in the third direction; and the channel direction of each transistor is consistent with the extension direction of the word lines (90).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application provides a transistor, a manufacturing method therefor, a memory and an electronic device, and belongs to the field of semiconductor devices and manufacturing. The transistor is a vertical transistor, and comprises a first source/drain, a first dielectric layer, a second source/drain and a second dielectric layer which are stacked on a substrate, and an active layer extending in a first direction perpendicular to the substrate. The active layer penetrates through the second dielectric layer, the second source/drain, the first dielectric layer and part or all of the first source/drain, the bottom of the active layer penetrating through the first source/drain or being in contact with part of the first source/drain. The work function of the material of the first source/drain is different from the work function of the material of the second source/drain. The active layer is a metal oxide semiconductor layer. The present application can suppress channel leakage and help to suppress short-channel effects.

Classes IPC  ?

• H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
• H01L 29/43 - Electrodes caractérisées par les matériaux dont elles sont constituées

Abrégé

Disclosed is a memory, a method for manufacturing the memory. The memory includes: one or more layers of memory cell arrays stacked in a direction perpendicular to a substrate; a plurality of wordlines that penetrate through one or more layers of the memory cell arrays; and a plurality of bitlines, wherein each memory cell includes a semiconductor layer that surrounds a sidewall of the wordline and extends along the sidewall and each bitline is connected to the semiconductor layers of a column of memory cells in one layer of the memory cell array, wherein the bitline is composed of different branch lines, and the semiconductor layer of each memory cell is connected to two adjacent first branch lines but is not connected to at least a part of the region of the second branch line between the two adjacent first branch lines.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application relates to a manufacturing method for a metal interconnect structure, a metal interconnect structure, and a semiconductor assembly. The manufacturing method for a metal interconnect structure comprises the following steps: providing a dielectric layer (110), the dielectric layer (110) being internally provided with an interconnect groove (111); manufacturing a metal interconnect layer (150) in the interconnect groove (111); and manufacturing a cobalt metal layer (160) on the metal interconnect layer (150) by means of an atomic layer deposition method by using raw materials comprising a cobalt organic compound.

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

Provided in the present invention are a three-dimensional stacked memory and a manufacturing method therefor. In the manufacturing method for the three-dimensional stacked memory provided by the present invention, single crystal semiconductors which are formed by means of an epitaxy process and made of a material the same as that of a substrate are used as semiconductor structures, or polycrystalline semiconductors which are formed by means of a deposition process are used as the semiconductor structures, so that misfit dislocation and interface limitation of the formed semiconductor structures can be prevented, thereby ensuring the performance of the semiconductor structures, and reducing the difficulty of manufacturing the three-dimensional stacked memory. Moreover, in the manufacturing method for the three-dimensional stacked memory provided by the present invention, multiple layers of the semiconductor structures can be formed at the same time, thus improving the efficiency of three-dimensional stacked memory production.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Embodiments of the present disclosure relate to, but are not limited to, the technical field of semiconductors, and provide a semiconductor device and a manufacturing method therefor, a memory, and an electronic device. The semiconductor device comprises one or at least two capacitors stacked in a direction perpendicular to a substrate. At least one capacitor comprises a first electrode plate (41), a second electrode plate (42), and a dielectric layer (13) located between the first electrode plate (41) and the second electrode plate (42). The first electrode plate (41) comprises a first body structure (411) and at least two first branch layers (81); the at least two first branch layers (81) are arranged at intervals in the direction perpendicular to the substrate; the first body structure (411) comprises first conductive layers (85) and second conductive layers (84) which are alternately stacked in the direction perpendicular to the substrate; the first electrode plate (41) further comprises grooves (83); a groove (83) is located between every adjacent first branch layers (81); the grooves (83) extend in a direction parallel to the substrate; and at least part of the dielectric layer (13) and at least part of the second electrode plate (42) are located in the grooves (83). The capacity of capacitors is increased.

Classes IPC  ?

• H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

CW1CW1) is applied to a second electrode (B) of a capacitor (C), the second transistor (T2) is turned on, and a storage node (SN) is pre-charged, the sum of a maximum data voltage corresponding to data and a threshold voltage of the first transistor (T1) being a reference voltage, and the first reference voltage (v1) being greater than the reference voltage; and in a data write stage, in response to a write command, the auxiliary signal line (BL2) floats, the data signal line (BL1) provides a data voltage to the first transistor (T1), the first transistor (T1) is turned on, the storage node (SN) is discharged to a stable state, and data corresponding to the data voltage is written.

Classes IPC  ?

• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques
• G11C 11/409 - Circuits de lecture-écriture [R-W]
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present disclosure relates to the technical field of storage, and relates to a data read-write circuit and a method therefor, a memory and a driving method therefor, and an electronic device, used for improving the accuracy of data reading. The data read-write method is applied to a storage unit (U), and comprises the following steps: in a pre-charging phase, a data signal line (BL1) provides a first reference voltage (v1) to a storage transistor (T1), an auxiliary signal line (BL2) simultaneously provides the first reference voltage (v1) to the storage transistor (T1) and a write transistor (T2), and the write transistor (T 2) is turned on to pre-charge a storage node (SN) between the write transistor (T2) and the storage transistor (T1), wherein the sum of the maximum data voltage corresponding to data that can be stored by the storage unit (U) and a threshold voltage of the storage transistor (T1) is a reference voltage, and the first reference voltage (v1) is greater than the reference voltage; and in a data writing phase, in response to a write command, the auxiliary signal line (BL2) floats, and the data signal line (BL1) provides a data voltage to the storage transistor (T1), the storage transistor (T1) is turned on, and the storage node (SN) discharges to a stable state to write data corresponding to the data voltage.

Classes IPC  ?

• G11C 11/401 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques

Abrégé

The present disclosure provides a dynamic random access memory (DRAM) cell circuit and a write method therefor, and a DRAM array circuit composed of the DRAM cell circuit and a row driving method in the write operation thereof. The DRAM cell circuit according to the present disclosure comprises: an N-type access transistor, a gate electrode of which is connected to a word line and a first source/drain electrode of which is connected to a bit line; and a memory capacitor, a first plate of which is connected to a second source/drain electrode of the N-type access transistor and a second plate of which is connected to a source electrode line. In the write operation, the word line operates at a ground voltage, a first voltage higher than or equal to a power supply voltage, and a second voltage between a threshold voltage of the N-type access transistor and the first voltage; and in the write operation, the source electrode line operates at the power supply voltage when the word line operates at the second voltage. According to the inventive concept of the present disclosure, the data storage time can be prolonged, and the interruption frequency due to refreshing is reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: a first wafer (100) and a second wafer (200) arranged on the first wafer (100), the first wafer (100) comprising a substrate (1) and a bit line arranged on the substrate (1), and the second wafer (200) comprising at least one transistor, wherein the transistor comprises a semiconductor pillar (10) extending in a direction perpendicular to the substrate (1); the semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) which are respectively arranged on two sides of the channel region (11); the second region (13) is arranged on the side of the channel region (11) that faces the substrate (1); and the bit line (30) is in contact with the second region (13).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided in the present disclosure are a dynamic random access memory (DRAM) cell circuit and a writing method therefor, and a DRAM array circuit composed of the DRAM cell circuit, and a row driving method in a writing operation of the DRAM array circuit. The DRAM cell circuit in the present disclosure comprises: a writing transistor, of which a gate electrode is connected to a writing word line, a first source/drain electrode is connected to a writing bit line, and a second source/drain electrode is connected to a storage node; a storage transistor, of which a gate electrode is connected to the storage node, and a first source/drain electrode is connected to a source line; and a read transistor, of which a gate electrode is connected to a read word line, a first source/drain electrode is connected to a second source/drain electrode of the storage transistor, and a second source/drain electrode is connected to a read bit line, wherein in a writing operation, the writing word line operates at a first voltage lower than a ground voltage, and at a second voltage higher than or equal to a power supply voltage. According to the inventive concept in the present disclosure, a data storage time can be extended, and the frequency of interruption caused by refreshing operations can be reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation

Abrégé

Provided in the present disclosure are a dynamic random access memory (DRAM) cell circuit and a writing method therefor, and a DRAM array circuit composed of the DRAM cell circuit. The DRAM cell circuit in the present disclosure comprises: a writing transistor, of which a gate electrode is connected to a writing word line, a first source/drain electrode is connected to a writing bit line, and a second source/drain electrode is connected to a storage node; and a storage transistor, of which a gate electrode is connected to the storage node, a first source/drain electrode is connected to a read word line, and a second source/drain electrode is connected to a read bit line, wherein in a writing operation, the writing word line operates at a first voltage lower than a ground voltage, and at a second voltage higher than or equal to a power supply voltage. According to the inventive concept in the present disclosure, a data storage time can be extended, and the frequency of interruption caused by refreshing operations can be reduced, thereby reducing the power consumption.

Classes IPC  ?

• G11C 11/4063 - Circuits auxiliaires, p. ex. pour l'adressage, le décodage, la commande, l'écriture, la lecture ou la synchronisation
• G11C 11/4094 - Circuits de commande ou de gestion de lignes de bits

Abrégé

The present application relates to the technical field of semiconductors, and in particular, to a method for preparing a semiconductor structure, and the semiconductor structure, which are used for solving the problem of reduction of the mobility of carriers. The method for preparing the semiconductor structure comprises: providing a substrate (10); and executing at least one epitaxial period, so as to form, on the substrate (10), a first epitaxial layer (201) and a second epitaxial layer (202) which are sequentially stacked from bottom to top, wherein the epitaxial period comprises: forming the first epitaxial layer (201) on the substrate (10), the first epitaxial layer (201) comprising a compound of a first element and a second element having a segregation characteristic; performing surface treatment on an upper surface of the first epitaxial layer (201) by using a halogen compound of the first element; and forming the second epitaxial layer (202) on the upper surface of the first epitaxial layer (201) having undergone surface treatment, the second epitaxial layer (202) comprising a first element.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to a semiconductor device, a memory and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: semiconductor layers (11), each having two opposite main surfaces, wherein the two opposite main surfaces are respectively a first side and a second side of the semiconductor layer (11), and the semiconductor layer (11) comprises a source contact region, a drain contact region, and a channel region between the source contact region and the drain contact region which are provided at intervals on the first side; bit lines (12), provided on the first sides of the semiconductor layers (11) and connected to the drain contact regions, wherein the bit lines (12) extend in a first direction, and the first direction is perpendicular to the surface of a substrate (2); and word lines (13), provided on the second sides of the semiconductor layers (11), wherein the word lines extend in a second direction, and the second direction is parallel to the surface of the substrate (2). The semiconductor device has a three-directional structure, and can increase the storage density.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of design and manufacturing of integrated circuits, and particularly relates to a semiconductor device and a preparation method therefor, and a memory and an electronic device, which are used for improving the etching effect of a stacked structure and reducing the etching difficulty. The preparation method comprises: providing a substrate (11), and forming a stacked structure (12) on the substrate (11), wherein the stacked structure (12) comprises a dielectric layer (121) and a sacrificial layer (122), which are alternately stacked in the thickness direction of the substrate (11); on the basis of the stacked structure (12), forming initial semiconductor pillars (13) which are arranged at intervals in a first direction, and reference word line trenches (16) which are arranged at intervals in the first direction, wherein each initial semiconductor pillar (13) comprises a dielectric portion (131) and a sacrificial portion (132), which are alternately stacked in the thickness direction; removing the sacrificial portion (132), and replacing the sacrificial portion (132) with an electrically conductive portion (181); and forming a target word line trench (22) on the basis of the reference word line trenches (16), so as to form a target word line structure in the target word line trench (22).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to a semiconductor device, a storage structure, a memory, and a manufacturing method therefor. The semiconductor device comprises at least two target unit structures stacked in a target direction. A gate structure in each target unit structure comprises protruding portions and horizontal portions connected to the bottom surfaces of the protruding portions. Each protruding portion passes through a conductive portion (132) directly above the protruding portion in the thickness direction of the conductive portion (132), and each horizontal portion is located between adjacent conductive portions (132) in the thickness direction and is connected to the protruding portion directly above the horizontal portion; the target direction is the thickness direction of the conductive portions (132); and a target channel layer (27) circumferentially surrounds the outer side wall of each protruding portion.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure provides a memory, an access method therefor and an electronic device. The memory comprises multiple memory cells, each memory cell comprising a first transistor and a second transistor; the first transistor is configured as a read transistor, and the second transistor is configured as a write transistor; the first transistor and the second transistor are sequentially distributed along a direction parallel to a substrate; the first transistor comprises a first gate electrode, a first semiconductor layer, a first electrode and a second electrode, and the second transistor comprises a second gate electrode, a second semiconductor layer, a third electrode and a fourth electrode; the first semiconductor layer is connected to the second semiconductor layer, and the second gate electrode multiplexes a back gate electrode of the first transistor, so that during a read operation, a second voltage is applied to the second gate electrode of the second transistor of a memory cell that does not need to be accessed, so as to adjust a threshold voltage of the first transistor, causing the first transistor of the memory cell that does not need to be accessed to be turned off. Using the present disclosure, data can be reliably read, and crosstalk can be avoided or effectively reduced.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• G11C 11/402 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules nécessitant un rafraîchissement ou une régénération de la charge, c.-à-d. cellules dynamiques avec régénération de la charge propre à chaque cellule de mémoire, c.-à-d. rafraîchissement interne
• G11C 11/4074 - Circuits d'alimentation ou de génération de tension, p. ex. générateurs de tension de polarisation, générateurs de tension de substrat, alimentation de secours, circuits de commande d'alimentation
• G11C 11/408 - Circuits d'adressage
• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

The present disclosure relates to the technical field of semiconductors, and particularly relates to a memory and a manufacturing method therefor, and an electronic device, which are used for reducing the parasitic capacitance of a memory. The memory comprises a substrate (1), a word line (WL) and a transistor (2). The word line (WL) extends in a direction perpendicular to the substrate (1). The transistor (2) comprises a semiconductor layer (21) at least partially surrounding the word line (WL) and a gate insulating layer (22) disposed between the word line (WL) and the semiconductor layer (21). The semiconductor layer (21) comprises a channel region (Q3) located on at least one side of the word line (WL) in a first direction, and two contact regions located on two sides of the word line (WL) in a second direction. The first direction and the second direction are both parallel to the substrate (1), and the first direction and the second direction intersect. The shortest distance from the channel region (Q3) to the word line (WL) is less than the shortest distance from at least one contact region to the word line (WL). The two contact regions comprise a first source/drain contact region (Q1) and a second source/drain contact region (Q2).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors, and relates to a memory and a manufacturing method therefor, and an electronic device, for use in improving the performance of memories. The memory comprises a substrate (1), and one or more repeating units (U) and a plurality of word lines (WL) arranged on the substrate (1). Each repeating unit (U) comprises: two bit lines (BL) which extend in a first direction and are arranged at an interval, and an isolation layer (24) provided in the interval between the two bit lines (BL); support layers (222) provided on the side walls of the bit lines (BL) facing away from the isolation layer (24), each support layer (222) comprising a plurality of sub-support portions (2221) distributed at intervals in the first direction, and the intervals between adjacent sub-support portions (2221) forming word line holes; and transistors (M) which are located in the word line holes and each comprise a semiconductor layer (25) surrounding the side wall of a word line (WL) and a gate insulating layer (26) arranged between the side wall of the word line (WL) and the inner side wall of the semiconductor layer (25), wherein the outer side wall of the semiconductor layer (25) facing away from the corresponding bit line (BL) is flush with the side wall of the adjacent sub-support portion (2221) facing away from the same bit line (BL).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic device, relating to the field of semiconductor devices. The semiconductor device comprises: at least one transistor (20) and bit line (30) provided on a substrate (10); the transistor (20) comprises a semiconductor pillar (21) extending in the direction perpendicular to the substrate (10), the semiconductor pillar (21) having a side wall, and the side wall of the semiconductor pillar (21) being in contact with the bit line (30) and being entirely surrounded by the bit line (30).

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and stacked in a direction perpendicular to a substrate (1); and a word line (40), which penetrates the transistors in different layers. The transistor comprises a first electrode (51), a second electrode (52), a semiconductor layer (23) surrounding a side wall of the word line (40), a gate insulating layer (24) arranged between the side wall of the word line (40) and the semiconductor layer (23), a first contact layer (61) arranged between the first electrode (51) and the semiconductor layer (23), and a second contact layer (62) arranged between the second electrode (52) and the semiconductor layer (23); a plurality of first contact layers (61) of the plurality of transistors are arranged at intervals in a direction in which the word line (40) extends; and a plurality of second contact layers (62) of the plurality of transistors are arranged at intervals in the direction in which the word line (40) extends.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors. The present disclosure relates to a memory, a manufacturing method therefor and an electronic device, and is used for improving the performance of the memory. The manufacturing method for the memory comprises the following steps: forming initial first insulation layers (L3) that cover side walls of conductive pattern layers (L111) and side walls of sacrificial pattern layers (L21); forming in a direction perpendicular to a substrate (1) wordline holes (G11) that pass through conductive units (111) and corresponding sacrificial pattern layers (L21); sequentially forming on side walls of the wordline holes (G11) initial semiconductor layers (L6), first dielectric layers (L7), and wordlines (WL) that cover the surfaces of the first dielectric layers (L7) facing away from the initial semiconductor layers (L6) and fill the wordline holes (G11); removing the initial first insulation layers (L3) on the side walls of the sacrificial pattern layers (L21), so as to form first insulation layers (L31); removing the sacrificial pattern layers (L21), so as to expose the initial semiconductor layers (L6) inside the wordline holes (G11) in the sacrificial pattern layers (L21); and etching the initial semiconductor layers (L6), so as to form semiconductor parts respectively located inside the conductive units (111).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present disclosure relates to the technical field of semiconductors, and relates to a memory and a manufacturing method therefor, and an electronic device, for use in solving the problem of how to reduce the parasitic capacitance of the memory. The memory comprises transistors (2), a word line (WL), and a bit line (BL); the word line (WL) extends in a direction perpendicular to a substrate (1); the transistors (2) each comprise a semiconductor layer (21) located on a side wall of the word line (WL), and a gate insulating layer (22) provided between the side wall of the word line (WL) and the semiconductor layer (21); the bit line (BL) comprises a bit line main body (111) and different first branches (112) corresponding to different transistors (2); the bit line main body (111) extends in a first direction parallel to the substrate (1); the first branches (112) extend towards the semiconductor layer (21) and are connected to the semiconductor layer (21). The present disclosure can reduce the parasitic capacitance of the memory, thereby further improving the performance of the memory.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device, a manufacturing method therefor, and an electronic device, relating to the technical field of semiconductors. The semiconductor device comprises: at least one transistor (10) provided on a substrate (1'), and bit lines (20). The transistor (10) comprises a silicon semiconductor pillar (30) extending in a direction perpendicular to the substrate (1'), and the silicon semiconductor pillar (30) successively comprises a first electrode region (31), a channel region (32) and a second electrode region (33) in a direction approaching the substrate (1'). The bit lines (20) are arranged between the second electrode region (33) and the substrate (1') and are connected to the second electrode region (33). The second electrode region (33) contains a doping material which is used for doping by means of a self-aligned ion implantation process, the average bulk density of the doping material in the second electrode region (33) being greater than or equal to 5e19 atoms/cubic centimeters.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée

Abrégé

Embodiments of the present application relate to the technical field of semiconductors. Disclosed are a memory, a manufacturing method for the memory, and an electronic device. The memory comprises: one or more memory cell array layers stacked in a direction perpendicular to a substrate; a plurality of wordlines penetrating through the one or more memory cell array layers, each memory cell comprising a semiconductor layer surrounding the side wall of the wordline and extending on the side wall; and a plurality of bitlines, each bitline being connected to each semiconductor layer of a column of memory cells in a memory cell array layer. Each bitline is composed of different branch lines, and the semiconductor layer of each memory cell is separately connected to two adjacent first branch lines and is not connected to at least partial region of a second branch line located between the two adjacent first branch lines. According to the memory provided by the embodiments of the present application, the contact area between the semiconductor layer of the memory cell and the bitline can be reduced, thereby reducing the parasitic capacitance between the wordline and the bitline.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor structure, a memory and a manufacturing method therefor, and an electronic device. The semiconductor structure comprises: a substrate (10), a back gate (30), a semiconductor layer (50), a drain electrode (65), a magnetic tunnel junction (90), and a first source electrode (63), a first gate electrode (66), a second source electrode (64) and a second gate electrode (67), which are located on the side of the semiconductor layer (50) that is away from the substrate (10). The semiconductor layer (50) and the back gate (30) are stacked in a direction away from the substrate (10) and are insulated from each other; the magnetic tunnel junction (90) is located on the side of the drain electrode (65) that is away from the substrate (10), and is in contact with the drain electrode (65); and the first source electrode (63) and the first gate electrode (66) are located on one side of the drain electrode (65), and the second source electrode (64) and the second gate electrode (67) are located on the other side of the drain electrode (65).

Classes IPC  ?

• H10B 61/00 - Dispositifs de mémoire magnétique, p. ex. dispositifs RAM magnéto-résistifs [MRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor and an electronic device. The manufacturing method comprises: sequentially and alternately depositing a first insulating layer (11) and a sacrificial layer (20) on a substrate (1) to obtain a stacked structure; etching the stacked structure, forming in the stacked structure a plurality of through holes (31) extending towards the substrate (1), and depositing a second insulating layer (12) in the through holes (31); performing patterning etching on the stacked structure provided with the through holes (31) to obtain a patterned sacrificial layer (20), the patterned sacrificial layer (20) comprising a plurality of bit line regions (41) and a plurality of electrode regions (50) each distributed between any two adjacent bit line regions (41); and replacing the patterned sacrificial layer (20) with a patterned conductive layer (60), the patterned conductive layer (60) comprising a plurality of bit lines (40) extending in a first direction and a plurality of electrodes (51) distributed on two sides of the bit lines (40) and connected to the bit lines (40).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device comprises: at least one transistor, an insulating layer covering the transistor, and a bit line (30) arranged on the side of the insulating layer away from the transistor. Each transistor comprises a semiconductor pillar (10) extending in a third direction, and the semiconductor pillar (10) comprises a channel region (11), and a first region (12) and a second region (13) respectively arranged on both sides of the channel region (11); the insulating layer is provided with a groove exposing the second region (13); the bit line (30) is arranged in the groove, the bit line (30) is in contact with the second region (13), and the contact surface between the bit line (30) and the second region (13) is perpendicular to the third direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A transistor, a 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device, relating to the field of semiconductor devices. The transistor comprises: first electrodes (10) and second electrodes (20) arranged on a substrate (1), semiconductor layers (30) arranged between the first electrodes (10) and the second electrodes (20), and gate electrodes (40) insulated from the semiconductor layers (30). The first electrodes (10) and the second electrodes (20) are distributed at intervals in a first direction parallel to the substrate (1). The gate electrodes (40) extend in a second direction parallel to the substrate (1). Each gate electrode (40) comprises a side wall extending in the second direction and two end faces, and one of the end faces is used for being connected to a word line (80). At least part of the side wall of the gate electrode (40) is surrounded by the corresponding semiconductor layer (30). The first direction intersects the second direction.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A CXL memory module, a memory data replacement method, and a computer system. The CXL memory module may comprise a flash memory chip (11), a memory chip (12), and a controller chip (13) connected to the flash memory chip (11) and the memory chip (12), wherein the controller chip (13) is configured to replace part of the data in the memory chip (12) into the flash memory chip (11).

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

A CXL memory module, a memory data swap method and a computer system. The CXL memory module may include a flash memory chip, a memory chip, and a controller chip connected with the flash memory chip and the memory chip. The controller chip is configured to be able to swap a part of data in the memory chip into the flash memory chip.

Classes IPC  ?

• G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

Classes IPC  ?

• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 21/027 - Fabrication de masques sur des corps semi-conducteurs pour traitement photolithographique ultérieur, non prévue dans le groupe ou
• H01L 21/306 - Traitement chimique ou électrique, p. ex. gravure électrolytique
• H01L 29/10 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode ne transportant pas le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
• H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
• H01L 29/66 - Types de dispositifs semi-conducteurs

Abrégé

The present application relates to the technical field of semiconductors, and in particular to a semiconductor structure, a memory structure, and preparation methods therefor, for use in solving the problems of a low doping utilization rate and inability to precisely control a doping position when doping is carried out on a substrate at the bottom of a trench. The preparation method for the semiconductor structure comprises: providing a substrate (100); forming a plurality of patterned structures arranged at intervals, wherein the patterned structures are located in the substrate (100) or on the substrate (100), each patterned structure has a region (201) to be doped, and said region (201) has a spacing at least with the bottom of the patterned structure; forming a first dielectric layer (11) in a gap between adjacent patterned structures, wherein the upper surface of the first dielectric layer (11) is not higher than the bottom of said region (201); forming a doped layer (12) at least on the side wall of said region (201); and carrying out heat treatment on the obtained structure, such that doped particles in the doped layer (12) are diffused into said region (201) to form a doped region (211).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]
• H01L 21/67 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants

Abrégé

The present disclosure relates to the technical field of integrated circuit design and manufacturing, and particularly relates to a semiconductor structure, a manufacturing method therefor, a memory, and an electronic device, which are used for solving the technical problem of hole defects or slit defects of node contact interfaces of vertical channel transistors. The method comprises: providing a target substrate (100), a plurality of active pillars (110) arranged at intervals in a first direction and a second direction being formed in the target substrate (100), the plurality of active pillars (110) all extending in a third direction, and insulating layers (120) being formed between adjacent active pillars (110); and forming target conductive contact structures (20) covering the top surfaces of the active pillars (110) and target insulating structures (30) covering the top surfaces of the insulating layers (120), the adjacent target conductive contact structures (20) all being isolated by the target insulating structures (30).

Classes IPC  ?

• H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
• H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
• H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

The present application relates to the technical field of semiconductors. Disclosed are a memory and a preparation method therefor, and an electronic device, which are used for solving the problem of the miniaturization of a storage unit being relatively difficult. The memory comprises at least one layer of periodically stacked storage units, each storage unit (104) comprising a read transistor (202) and a write transistor (204), wherein the read transistor (202) and the write transistor (204) are sequentially distributed in a row direction; each read transistor (202) comprises a first semiconductor layer (302), a main gate electrode (306) and a gate insulating layer (304); each write transistor (204) comprises a second semiconductor layer (402); and the main gate electrode (306) of each read transistor (202) is located between the first semiconductor layer (302) and the second semiconductor layer (402) of the storage unit (104), and the main gate electrode (306) is connected to the first semiconductor layer (302) by means of the gate insulating layer (304), and is connected to the second semiconductor layer (402).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A high-density ferroelectric memory, and a manufacturing method therefor and an application thereof, relating to the field of semiconductor memories. The memory consists of multiple memory cells arranged in an array, and two sides of the array of the memory cells are connected by substantially orthogonal word lines and bit lines. Each memory cell has a stack structure of a top electrode, a resistive dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, and the structure is electrically equivalent to a ferroelectric capacitor and a resistive selector connected in series. By regulating the RC delay of the memory cells, the voltage distributed to a ferroelectric capacitor in an unselected cell is reduced, so that the disturbance to the unselected cell is reduced; additionally, the capacitance value of the ferroelectric capacitor is stable, and the effect of a disturbance voltage can be effectively reduced by means of RC regulation. The present invention improves the memory window of a memory and reduces the bit error rate, without increasing additional area overhead.

Classes IPC  ?

• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire

Abrégé

A high-speed and high-density ferroelectric memory, and a manufacturing method therefor and an application thereof, relating to the field of semiconductor memories. The memory consists of multiple memory cells arranged in an array, and two sides of the array of the memory cells are connected by substantially orthogonal word lines and bit lines. Each memory cell has a structure in which a top electrode, a variable capacitance dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode are stacked, and the structure is electrically equivalent to a ferroelectric capacitor and a variable capacitance selector connected in series. By regulating a voltage distribution relationship among the memory cells, the voltage distributed to a ferroelectric capacitor in an unselected cell is reduced, so that the disturbance to the unselected cell is reduced; additionally, the serial connection of capacitors reduces the RC delay of the memory cells and improves the memory access speed. Therefore, the present invention reduces the disturbance to an unselected cell, improves the memory window of a memory, reduces the bit error rate of the memory, and improves the memory access speed, without increasing additional area overhead.

Classes IPC  ?

• H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
• H10B 53/10 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la configuration vue du dessus
• H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
• G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques

Abrégé

A storage unit, a semiconductor device and a preparation method therefor, and an electronic device, relating to the technical field of semiconductors. The storage unit (100) comprises a first transistor (110) and a second transistor (120) which are arranged in a first direction parallel to a substrate; a first gate (111) of the first transistor (110) extends in a second direction perpendicular to the substrate, and a first semiconductor layer (112) of the first transistor (110) at least partially surrounds the side wall of the first gate (111); a second gate (121) of the second transistor (120) is connected to the first semiconductor layer (112), and the second gate (121) partially surrounds a second semiconductor layer (122) of the second transistor (120); the first semiconductor layer (112), the second gate (121) and the second semiconductor layer (122) are sequentially arranged in the first direction in a plane parallel to the substrate.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of memory cells (120), which are distributed on different layers, stacked in the direction perpendicular to a substrate (1) and periodically distributed, wherein each layer comprises a plurality of memory cells (120), which are distributed in an array in a first direction and a second direction; each memory cell (120) comprises a transistor and a capacitor; the transistor comprises a pillar (54), which extends in the second direction, and a gate electrode (100), which surrounds a side wall of the pillar (54), the pillar (54) comprising a first conductive region (55), a semiconductor region (57) and a second conductive region (56); the semiconductor region (57) contains a body material of the pillar (54), and the first conductive region (55) and the second conductive region (56) contain a first doped material and a second doped material, respectively; and the first doped material is evenly distributed in the first conductive region (55), and the second doped material is evenly distributed in the second conductive region (56).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided in the embodiments of the present application are a semiconductor device and a manufacturing method therefor, and an electronic device. The semiconductor device in the embodiments of the present application comprises a plurality of layers of memory cells stacked in a direction perpendicular to a substrate (10), bit lines extending through the layers of memory cells, and word lines extending in a first direction perpendicular to the bit lines, wherein each memory cell comprises a transistor and a capacitor; a plurality of first memory cells connected to a first word line (91) and a plurality of second memory cells connected to a second word line (92) are comprised between every two adjacent word lines; and a first electrode (81) and a second electrode (82) of the transistor of each memory cell are connected to a semiconductor layer (80) surrounding a corresponding word line, and the first electrode (81) and the second electrode (82) of each transistor are located between the first word line (91) and the second word line (92) and are spaced apart from each other in the first direction.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A 3D stacked semiconductor device and a manufacturing method therefor, and an electronic device. The 3D stacked semiconductor device comprises: a plurality of transistors, which are distributed in different layers and are stacked in a direction perpendicular to a substrate (1). Each transistor comprises: a first electrode (51); a second electrode (52); an insulation portion (14), which connects the first electrode (51) and the second electrode (52); a semiconductor layer (23), by which the first electrode (51), the insulation portion (14) and the second electrode (52) are surrounded; a gate electrode (26), by which a side wall of the semiconductor layer (23) is surrounded; and a gate insulation layer (24), which is disposed between the gate electrode (26) and the semiconductor layer (23), wherein the first electrode (51), the insulation portion (14) and the second electrode (52) are connected to form an integrated structure.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

Provided is a semiconductor structure. The semiconductor structure includes a substrate including a die region and a non-die region, wherein an accommodation recess is formed in a side of the substrate and positioned in the non-die region; a buffer disposed in the accommodation recess; a functional film layer disposed on the side, where the accommodation recess is formed, of the substrate; and a passivation layer covering the functional film layer and the substrate. A buffer cavity with an opening facing away from the substrate is formed in the buffer. An orthographic projection of the functional film layer on the substrate is within the die region. A first through-via is formed in the passivation layer. An orthographic projection of the first through-via on the substrate is at least partially overlapped with an orthographic projection of the opening on the substrate. The opening is in communication with the first through-via.

Classes IPC  ?

• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 21/56 - Encapsulations, p. ex. couches d’encapsulation, revêtements

Abrégé

The present disclosure relates to a semiconductor structure, a memory, a manufacturing method therefor, and an electronic device, relating to the field of semiconductors, and used to simplify the structure and processing of a high-performance memory. The method comprises: forming on a substrate (1) multiple isolation layers (L1) and multiple metal oxide conductive layers (L2), which are stacked along a direction perpendicular to the substrate (1) and alternatingly distributed; performing a one-step etching process on the multiple isolation layers (L1) and the multiple metal oxide conductive layers (L2), simultaneously forming multiple stacked patterned metal oxide conductive layers (L2), each patterned metal oxide conductive layer (L2) comprising bit lines (BL) located in different regions and integrally connected, multiple first initial channel regions (21a) and multiple first electrodes (31); performing oxygen treatment on the metal oxide conductive layer (L2) of each first initial channel region (21a), such that the metal oxide conductive layer (L2) of the first initial channel region (21a) becomes a first semiconductor layer (211) of the first channel region (21); and sequentially coating a dielectric layer and a conductive layer on the exposed surface of each first semiconductor layer (211), to form a first gate electrode (23) and a word line (WL).

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]

Abrégé

A manufacturing method for a semiconductor device, the method comprising: by means of a one-step patterning process, forming a laminated structure into a patterned laminated structure, and forming a through hole, wherein the patterned laminated structure comprises a patterned conductive layer and a patterned insulating layer, which are alternately disposed in sequence; the through hole penetrates the patterned laminated structure in a direction perpendicular to a substrate; the patterned conductive layer and the patterned insulating layer are exposed from a side wall of the through hole; and the through hole is configured to accommodate a word line.

Classes IPC  ?

• H10B 12/00 - Mémoires dynamiques à accès aléatoire [DRAM]