An example thin-film transistor includes a source and a gate. The source includes a body of source metal and a body of capacitance-tuning material disposed on the body of source metal. The body of capacitance-tuning material is configured to control a capacitance between the source and the gate. A drain of the thin-film transistor may also include a body of capacitance-tuning material. Capacitance-tuning material may be provided outside the source/drain, for example, adjacent a gate dielectric material. The thin-film transistor may further include a body of reducing material to draw oxygen out of other materials of the thin-film transistor. The thin-film transistor may further include a body of hardmask material used during the making of the thin-film transistor.
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H10D 89/60 - Dispositifs intégrés comprenant des dispositions pour la protection électrique ou thermique, p. ex. circuits de protection contre les décharges électrostatiques [ESD].
H10D 99/00 - Matière non prévue dans les autres groupes de la présente sous-classe
A novel adhesion layer of hafnium nitride useful in the fabrication of semiconductor devices is disclosed. In particular, semiconductor devices such as, for example, thin film transistors which include one or more elements formed of metals with high electron concentrations, such as molybdenum, tungsten, nickel, ruthenium, cobalt and alloys thereof, can employ the present invention to better adhere the metal elements to the dielectric material on which the semiconductor devices are formed and the adhesion layer can also serve as a diffusion barrier.
A novel gate stack for a field effect transistor reduces the net charge in the dielectric material of the gate stack adjacent the semiconductor material of the transistor. The gate stack includes a gradient region between the dielectric layer abutting the semiconductor material and the diffusion barrier abutting the gate material, wherein the stoichiometry of the materials in the gradient region changes from the stoichiometry of the dielectric material to the stoichiometry of the diffusion barrier while avoiding abrupt changes in stoichiometry.
A novel gate stack for a field effect transistor reduces the net charge in the dielectric material of the gate stack adjacent the semiconductor material of the transistor. The gate stack includes a gradient region between the dielectric layer abutting the semiconductor material and the diffusion barrier abutting the gate material, wherein the stoichiometry of the materials in the gradient region changes from the stoichiometry of the dielectric material to the stoichiometry of the diffusion barrier while avoiding abrupt changes in stoichiometry.
A novel SRAM cell employs two or more MBT transistors formed on a plane of a semiconductor die over the plane of the die on which CMOS logic circuitry is formed. By using MBT transistors formed over the CMOS logic plane of the die, the area required on that CMOS logic plane is reduced. Reducing the required area provides several advantages, including increased memory cell densities, reduced length of signal and power leads to the SRAM cells with a commensurate decrease in power losses, thermal heating and parasitic capacitances.
H10B 10/00 - Mémoires statiques à accès aléatoire [SRAM]
G11C 11/40 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors
G11C 11/412 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des dispositifs à semi-conducteurs utilisant des transistors formant des cellules avec réaction positive, c.-à-d. des cellules ne nécessitant pas de rafraîchissement ou de régénération de la charge, p. ex. multivibrateur bistable, déclencheur de Schmitt utilisant uniquement des transistors à effet de champ
H10N 97/00 - Dispositifs électriques à l’état solide à film mince ou à film épais, non prévus ailleurs
An active semiconductor package includes an active structure fabricated on the package substrate, the active structure including one or more circuits acting between a semiconductor die mounted to the substrate and the package connection points. The circuits can include, without limitation, test circuitry, switches, voltage converters, etc. and can be formed with lateral or vertical transistors.
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H02M 1/00 - Détails d'appareils pour transformation
An active via is taught which comprises at least one via and at least one transistor which acts as a switch element. The resulting active via can be used with 1D, 2.5D or 3D chips to: control circuit elements; reduce EMI between vias; increase the density of vias; improve power and thermal efficiencies of chips; simplify power, data and other routing networks on chips; enable a higher level stacking of dies or layers in a chip while maintaining modularity; etc. A control strategy system can be provided to remove the supply of power to one or more regions of the chip when the regions are not in use and to supply power to those regions when the regions are in use, or to control input and output to regions of the chip. The active vias can be fabricated with Back or Front End Of Line processes.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/66 - Types de dispositifs semi-conducteurs
9.
SYSTEM AND METHOD FOR THE VERIFICATION AND CHARACTERIZATION OF VLSI DEVICES
A test network, implemented with BEOL and/or MOL devices, provides on-chip test probes allowing direct access to selected test points within circuits on a VLSI integrated circuit. The test network allows inputs to be directly applied to and outputs to be directly observed at test points of interest, greatly improving Observability and Controllability of the integrated circuit. Multiple test networks can be employed on an integrated circuit to allow circuits and/or functional blocks of the chip to be tested independently and/or in parallel. As the test circuitry and networks are implemented with BEOL and/or MOL devices, they can be manufactured on layers of the integrated circuit stacked atop the primary circuitry and thus do not require any significant increase in the chip's die area.
H01L 27/00 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun
G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
[0035] A oxide semiconductor channel stack for semiconductor devices having an oxide semiconductor channel layer, an optional mediating material layer formed over the oxide semiconductor channel layer and a setting layer formed over the mediating material layer, if present, or over the oxide semiconductor channel layer. The setting layer draws surplus oxygen atoms from an adjacent region of the oxide semiconductor to reduce defects therein, thus increasing the current carrying capacity through a channel formed in the oxide semiconductor channel layer. The setting layer can also serve as a contact, such as a gate contact, or a separate metal layer can be formed over the setting layer to serve as a contact.
A novel adhesion layer of hafnium nitride useful in the fabrication of semiconductor devices is disclosed. In particular, semiconductor devices such as, for example, thin film transistors which include one or more elements formed of metals with high electron concentrations, such as molybdenum, tungsten, nickel, ruthenium, cobalt and alloys thereof, can employ the present invention to better adhere the metal elements to the dielectric material on which the semiconductor devices are formed and the adhesion layer can also serve as a diffusion barrier.
A novel adhesion layer of hafnium nitride useful in the fabrication of semiconductor devices is disclosed. In particular, semiconductor devices such as, for example, thin film transistors which include one or more elements formed of metals with high electron concentrations, such as molybdenum, tungsten, nickel, ruthenium, cobalt and alloys thereof, can employ the present invention to better adhere the metal elements to the dielectric material on which the semiconductor devices are formed and the adhesion layer can also serve as a diffusion barrier.
A novel isothermal transistor structure and method of forming the isothermal transistor structure is disclosed that enables isothermal operation of two or more transistors which are in thermal proximity to one another. The structure includes at least two transistors which are manufactured in a middle of line or back end of line process and includes a layer of thermally conductive material which is thermally adjacent to the at least two transistors and which dissipates heat from the at least two transistors. The isothermal structures can be formed over MOS circuitry formed conventionally by front end of line processes or can be formed over other layers of transistors which are manufactured in a middle of line or back end of line processes. In one embodiment, the isothermal structures are formed on the side of a semiconductor die opposite the side on which the conventional MOS circuitry is formed and the isothermal structures are connected to the MOS circuitry through vias.
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
A system and method to increase the yield of manufactured integrated circuits by providing remedial circuit elements including alternate plane transistors, manufactured by middle of line and/or back end of line processes, to enable and disable the remedial circuit elements which provide additional circuit functions, when needed, as determined by post- manufacture testing of the integrated circuits and/or by in-operation monitoring of circuit operation. The system and method can address the distribution of the power supply and signals, such as clock signals, and/or high speed I/O signals, through problem areas resulting from sub-optimal designs, circuit aging and/or failures due to manufacturing process variations.
H01L 21/00 - Procédés ou appareils spécialement adaptés à la fabrication ou au traitement de dispositifs à semi-conducteurs ou de dispositifs à l'état solide, ou bien de leurs parties constitutives
H01L 21/66 - Test ou mesure durant la fabrication ou le traitement
H01L 23/58 - Dispositions électriques structurelles non prévues ailleurs pour dispositifs semi-conducteurs
A novel method of passivizing the surface of elements intended to act as the source and/or drain of a thin film transistor to inhibit the formation of oxides on the surface of those elements during subsequent plasma enhanced deposition process steps is taught. The resulting passivized elements have a layer of plasma enhanced deposition compatible nitride formed on their surface and those structures with that layer of passivation nitride can act as the source and/or drain in a thin film metal oxide transistor, with the plasma enhanced deposition compatible nitride also able to serve as a source channel interfacial member.
A system and method to increase the yield of manufactured integrated circuits by providing remedial circuit elements including alternate plane transistors, manufactured by middle of line and/or back end of line processes, to enable and disable the remedial circuit elements which provide additional circuit functions, when needed, as determined by post-manufacture testing of the integrated circuits and/or by in-operation monitoring of circuit operation. The system and method can address the distribution of the power supply and signals, such as clock signals, and/or high speed I/O signals, through problem areas resulting from sub-optimal designs, circuit aging and/or failures due to manufacturing process variations.
A novel thin film transistor (TFT) includes a source channel interfacial member between at least the source of the transistor and the semiconductor member in which the channel will be formed. The TFT further includes at least a source carrier reservoir in contact with the source and the source end of the semiconductor member. The interaction of the source channel interfacial member and the carrier reservoir provides the TFTs with an increased threshold voltage to place the TFT into an ON state and with reduced current leakage when the TFTs are in an OFF state and the source carrier reservoir provides a source of charge carriers to inhibit carrier starvation through the channel. The materials selected for formation of the TFTs also allow the TFTs to be formed with MOL and/or BEOL processes over logic and other circuitry formed in conventional FEOL processes to obtain three dimensional circuits on semiconductor dies.
A novel thin film transistor (TFT) includes a source channel interfacial member between at least the source of the transistor and the semiconductor member in which the channel will be formed. The TFT further includes at least a source carrier reservoir in contact with the source and the source end of the semiconductor member. The interaction of the source channel interfacial member and the carrier reservoir provides the TFTs with an increased threshold voltage to place the TFT into an ON state and with reduced current leakage when the TFTs are in an OFF state and the source carrier reservoir provides a source of charge carriers to inhibit carrier starvation through the channel. The materials selected for formation of the TFTs also allow the TFTs to be formed with MOL and/or BEOL processes over logic and other circuitry formed in conventional FEOL processes to obtain three dimensional circuits on semiconductor dies.
An active via is taught which comprises at least one via and at least one transistor which acts as a switch element. The resulting active via can be used with 1D, 2.5D or 3D chips to: control circuit elements; reduce EMI between vias; increase the density of vias; improve power and thermal efficiencies of chips; simplify power, data and other routing networks on chips; enable a higher level stacking of dies or layers in a chip while maintaining modularity; etc. A control strategy system can be provided to remove the supply of power to one or more regions of the chip when the regions are not in use and to supply power to those regions when the regions are in use, or to control input and output to regions of the chip. The active vias can be fabricated with Back or Front End Of Line processes.
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 23/552 - Protection contre les radiations, p. ex. la lumière
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/16 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types couverts par plusieurs des sous-classes , , , , ou , p. ex. circuit hybrides
H01L 27/02 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface
H01L 29/66 - Types de dispositifs semi-conducteurs
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
Novel semiconductor devices are taught. The novel devices include a thin film transistor (TFT) with an n-type semiconductor layer to form a channel between a source and a drain. The TFT further includes a source-channel interfacial member adjacent to at least the source contact of the device to provide depletion layer control of the operation of the TFT.
An active via is taught which comprises at least one via and at least one transistor which acts as a switch element. The resulting active via can be used with 1D, 2.5D or 3D chips to: control circuit elements; reduce EMI between vias; increase the density of vias; improve power and thermal efficiencies of chips; simplify power, data and other routing networks on chips; enable a higher level stacking of dies or layers in a chip while maintaining modularity; etc. A control strategy system can be provided to remove the supply of power to one or more regions of the chip when the regions are not in use and to supply power to those regions when the regions are in use, or to control input and output to regions of the chip. The active vias can be fabricated with Back or Front End Of Line processes.
H01L 23/535 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions internes, p. ex. structures d'interconnexions enterrées
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Semi-conductors; semi-conductor chips; semi-conductor memory units; electronic semi-conductors; structured semi-conductor wafers; optical semi-conductors; semi-conductor power elements and semi-conductor materials, namely thin film metal oxides Providing information relating to research in the area of semiconductor processing technology; and Scientific and technological design services, namely, technological design and development of apparatus and instruments used for semi-conductors Licensing of intellectual property rights; licensing of technology in the field of integrated circuit design
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Semi-conductors; semi-conductor chips; semi-conductor memory units; electronic semi-conductors; structured semi-conductor wafers; optical semi-conductors; semi-conductor power elements and semi-conductor materials, namely thin film metal oxides Providing information relating to research in the area of semiconductor processing technology; and Scientific and technological design services, namely, technological design and development of apparatus and instruments used for semi-conductors Licensing of intellectual property rights; licensing of technology in the field of integrated circuit design
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
Semi-conductors; semi-conductor chips; semi-conductor memory units; electronic semi-conductors; structured semi-conductor wafers; optical semi-conductor; semi-conductor elements; and crystalline semi-conduct material. Providing information relating to the area of semiconductor processing technology; and Scientific and technological design and development of apparatus and instruments used for semi-conductors. Licensing of intellectual property rights; licensing of technology of integrated circuit design.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
(1) Semi-conductors; semi-conductor chips; semi-conductor memory units, namely semi-conductor memory chips and semi-conductor memory circuit boards; electronic semi-conductors; structured semi-conductor wafers; optical semi-conductor; semi-conductor elements; crystalline semi-conduct material. (1) Providing information relating to the area of semiconductor processing technology; Scientific and technological design and development of apparatus and instruments used for semi-conductors.
(2) Licensing of intellectual property rights; licensing of technology of integrated circuit design.
09 - Appareils et instruments scientifiques et électriques
42 - Services scientifiques, technologiques et industriels, recherche et conception
45 - Services juridiques; services de sécurité; services personnels pour individus
Produits et services
(1) Semi-conductors; semi-conductor chips; semi-conductor memory units, namely semi-conductor memory chips and semi-conductor memory circuit boards; electronic semi-conductors; structured semi-conductor wafers; optical semi-conductor; semi-conductor elements; crystalline semi-conduct material. (1) Providing information relating to the area of semiconductor processing technology; Scientific and technological design and development of apparatus and instruments used for semi-conductors.
(2) Licensing of intellectual property rights; licensing of technology of integrated circuit design.
