The disclosed device can include a bitcell array located on a first metal layer including a first subarray of bitcells and a second subarray of bitcells; a first write driver device coupled to the first subarray of bitcells from a first end of the first subarray; a second write driver device coupled to the second subarray of bitcells from a first end of the second subarray; a third write driver device coupled to the first subarray of bitcells from a second end of the first subarray; and a fourth write driver device coupled to the second subarray of bitcells from the second end of the second subarray. Various other devices, systems, and methods of manufacture are also disclosed.
Systems and methods for efficient memory management during ray tracing are described. A ray tracing system assigns a memory stack to a ray. The ray, when intersection tested against objects of a node, accesses data that is stored in the memory stack. When data is to be consumed from the memory stack by the ray, the ray tracing system uses a memory pointer associated with the ray to locate the requested data. When data is to be stored to the memory stack, the memory allocation circuitry stores data in a free memory block and uses a linked list to link the memory block with other memory blocks storing additional data for the ray.
An exemplary apparatus includes a through-silicon via (TSV) and circuit that protects against the antenna effect and electrostatic discharge (ESD). The circuit can include a plurality of transistors whose gates are each electrically coupled to a signal that passes through the TSV. Various other apparatuses, systems, and methods are also disclosed.
A method for collapsing operations into super operations in a computing system includes dispatching a super operation corresponding to a collapsible sequence of operations to a scheduler, performing a lookup in a super operation table for the collapsible sequence of operations in response to the super operation being picked from the scheduler, and multi-pumping the collapsible sequence of operations to a pipe operationally coupled to the scheduler. For example, the multi-pumped collapsible sequence of operations may then be sequentially executed by an execution unit. The collapsible sequence of operations may be identified as collapsible according to a set of rules.
A network of thermal sensors can be integrated within a semiconductor chip in a manner effective to provide local temperature monitoring and dynamic control of an associated device or system. The thermal sensors can include small area thermal ring oscillators located proximate to the core of a central processing unit (CPU), for example, and can be disposed on the chip at locations based on a designed output power density and attendant thermal gradients encountered during operation. In certain implementations, the presently-disclosed sensor configuration can be used to measure deviation from set threshold temperatures. Closed-loop control can be implemented to mitigate performance loss while adjusting the clock speed of the CPU independent of the system management unit.
Memory layers and a digital device layer are configured into a three-dimensional integrated circuit (IC) die stack. The digital device layer (304) has a first surface (side) located closest to a cooling solution (308) and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer (304) and the memory layers (302). Through-silicon vias (TSV) (314) running through the memory layers and to the digital device layer are used to interconnect the signal, control and power supply voltages to circuits in these layers. Some of the TSVs are used to couple to external connections of a memory stack device. The digital device layer may be a complex electronic device layer such as a microprocessor or microcontroller for improved high speed signal transfers.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 21/98 - Assemblage de dispositifs consistant en composants à l'état solide formés dans ou sur un substrat communAssemblage de dispositifs à circuit intégré
H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés
Disclosed herein is an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes first plurality of integrated circuit dice disposed in a first tier of the die stack, and the first plurality of integrated circuit dice include a first integrated circuit die and a bridge die. The integrated circuit die stack further includes a second plurality of integrated circuit dice disposed in a second tier of the die stack, and the second plurality of integrated circuit dice are stacked vertically above the first plurality of the integrated circuit dice of the first tier and include a second integrated circuit die and a third integrated circuit die. The bridge die couples with both the second integrated circuit die and the third integrated circuit die.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A processing system (100) includes one or more DMA engines (150, 160) that load data from memory (140) or another cache location without storing the data after loading it. As the data propagates past caches located between the memory or other cache location that stores the requested data ("intermediate caches"), the data is selectively copied to the intermediate caches based on a cache replacement policy. Rather than the DMA engine manually storing the data into the intermediate caches, the cache replacement policies (512) of the intermediate caches determine whether the data is copied into each respective cache and a replacement priority of the data. By bypassing storing the data, the DMA engine effectuates prefetching to the intermediate caches without expending unnecessary bandwidth or searching for a memory location to store the data, thus reducing latency and saving energy.
G06F 13/28 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus d'entrée/sortie utilisant le transfert par rafale, p. ex. acces direct à la mémoire, vol de cycle
G06F 12/0862 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache avec pré-lecture
The disclosed high-performance time-to-digital converter (TDC) incorporates ratiometric signal quantization with correlated double sampling (CDS). The TDC includes an input voltage circuit that outputs an input voltage signal and a fractional reference voltage circuit that outputs a fractional reference voltage signal. The TDC also includes a quantizer circuit that provides a differential output of the input voltage signal and the fractional reference voltage signal as a digital time value. Various other methods, systems, and computer-readable media are also disclosed.
H03M 1/50 - Convertisseurs analogiques/numériques avec conversion intermédiaire en intervalle de temps
H03M 1/38 - Valeur analogique comparée à des valeurs de référence uniquement séquentiellement, p. ex. du type à approximations successives
H03L 7/06 - Commande automatique de fréquence ou de phaseSynchronisation utilisant un signal de référence qui est appliqué à une boucle verrouillée en fréquence ou en phase
H03M 1/06 - Compensation ou prévention continue de l'influence indésirable de paramètres physiques
H03M 1/18 - Commande automatique pour modifier la plage des signaux que le convertisseur peut traiter, p. ex. réglage de la plage de gain
10.
SYSTEMS AND METHODS FOR REDUCING SEMICONDUCTOR DEVICE DELAMINATION
A method for reducing semiconductor device delamination can include depositing a top barrier layer on top of a metal layer plating a bottom barrier layer. The method can also include depositing dielectric material on top of the top barrier layer and adjacent to the metal layer and the bottom barrier layer. Various other methods and systems are also disclosed.
Memory layers and a digital device layer are configured into a three-dimensional integrated circuit (IC) die stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers. Through-silicon vias (TSV) running through the memory layers and to the digital device layer are used to interconnect the signal, control and power supply voltages to circuits in these layers. Some of the TSVs are used to couple to external connections of a memory stack device. The digital device layer may be a complex electronic device layer such as a microprocessor or microcontroller for improved high speed signal transfers.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/48 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
A system and technique for buffering data locally within a memory device to allow access to data associated with multiple different rows within the memory device. The memory device includes memory bank circuitry having memory cells and sense amplifier circuitry coupled to the memory bank circuitry. The memory device further includes buffer circuitry coupled to an output of the sense amplifier circuitry. Further, the memory device includes selection circuitry. The selection circuitry receives a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and outputs a selected one of the first data signal and the second data signal.
G11C 11/4091 - Amplificateurs de lecture ou de lecture/rafraîchissement, ou circuits de lecture associés, p. ex. pour la précharge, la compensation ou l'isolation des lignes de bits couplées
G11C 7/06 - Amplificateurs de lectureCircuits associés
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
13.
APPARATUS, SYSTEM, AND METHOD FOR MITIGATING WARPAGE IN INTEGRATED CIRCUIT PACKAGES
An exemplary stiffener comprises an inner perimeter that substantially surrounds at least one dimension of an integrated circuit coupled to a substrate. The inner perimeter of stiffener comprises a set of boundaries and at least one recess formed into at least one of the boundaries. In addition, the exemplary stiffener also comprises an outer perimeter that extends further outward from the integrated circuit than the inner perimeter. Various other apparatuses, systems, and methods are also disclosed.
A system on a chip (SOC) includes a critical domain including components configured to perform critical operations and a non-critical domain including components configured to perform non-critical operations. To help perform such operations, the critical domain and non-critical domain share a static random-access memory (SRAM) that includes a first subset of memory banks assigned to the critical domain and a second subset of memory banks assigned to the non-critical domain. The SOC further includes a memory scrubbing circuitry configured to sequentially check each memory bank of the SRAM for errors. To this end, the memory scrubbing circuitry is configured to check a respective memory bank for errors each time an event trigger occurs by implementing one or more error correction codes.
An electronic device, chip package and methods for fabricating the same are disclosed herein. In one example, a chip package includes one or more integrated circuit IC dies, a package substrate, a raised surface, and a package lid. The package substrate has a first surface that includes a first region and a second region disposed outward of the first region. The first region is covered by the one or more IC dies, where at least one of the one or more integrated circuit IC dies is mounted to the first surface. The raised surface is formed on the second region of the first surface of the package substrate. The package lid is mounted to the raised surface.
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 21/52 - Montage des corps semi-conducteurs dans les conteneurs
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
16.
SYSTEMS AND METHODS FOR COOLING AN INTEGRATED CIRCUIT
A disclosed method for cooling an integrated circuit can include positioning a first blower to draw air through a first air inlet in a first side of a housing. The method can additionally include positioning a second blower to draw air through a second air inlet in a second side of the housing that is opposite the first side, wherein the second blower is mirror-stacked with the first blower. Various other methods and systems are also disclosed.
H01L 23/467 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de gaz, p. ex. d'air
H01L 23/433 - Pièces auxiliaires caractérisées par leur forme, p. ex. pistons
Supply chain security for chiplets is described. In accordance with the described techniques, a chiplet manufacturing interface obtains first test results, and stores an encrypted version of the first test results in a database accessible by the chiplet manufacturing interface and a chiplet integration interface. The chiplet integration interface obtains second test results from at least one chiplet, retrieves, from the database, the encrypted version of the first test results, decrypts the encrypted version of the first test results to obtain a first hash of the first test results, and selectively integrates the at least one chiplet into an integrated circuit based on a comparison of the first test results and the second test results and a comparison of the first hash and a second hash of the second test results generated by the chiplet integration interface.
A system and technique for buffering data locally within a memory device to allow access to data associated with multiple different rows within the memory device. The memory device includes memory bank circuitry having memory cells and sense amplifier circuitry coupled to the memory bank circuitry. The memory device further includes buffer circuitry coupled to an output of the sense amplifier circuitry. Further, the memory device includes selection circuitry. The selection circuitry receives a first data signal from the sense amplifier circuitry and a second data signal from the buffer circuitry, and outputs a selected one of the first data signal and the second data signal.
Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
20.
Multipurpose wordline underdrive circuits, devices, and systems
A multipurpose wordline underdrive circuit includes a wordline driver and a pulldown network. The pulldown network includes a first current-carrying terminal electrically coupled to the wordline driver and a second current-carrying terminal electrically coupled to a control signal. The pulldown network also includes a current-regulation terminal electrically coupled to an additional control signal. Various other devices, systems, and methods are also disclosed.
Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating a type of an error detected in the memory.
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
A processing system includes one or more sensors configured to generate sensor data while a memory of the processing system is in a low-power state. As the sensors generate the sensor data, the sensor data is stored in a buffer. The processing system further includes a sensor data management circuitry that tracks a usage of the buffer. Based on the usage of the buffer exceeding a threshold, the sensor data management circuitry is configured to wake at least a portion of the memory from the low-power state. Once the memory exits the low-power state, the processing system transfers the sensor data from the buffer to one or more locations within the memory. After writing the sensor data to the memory, the processing system then places at least a portion of the memory back in the low-power state.
Embodiments herein describe a method and system for configuring device equalization self-training mode (DESTM) controls using in-band signaling, the DESTM controls including at least setting a minimum duration time, using a host to enable the DESTM controls, triggering a buffer to perform a self-training mode, sending linear-feedback shift register (LFSR) patterns to the buffer for the minimum duration time, and waiting for the minimum completion time to end before disabling the DESTM. The minimum duration time indicates a time that the self-training mode is active and is predefined. The buffer executes the self-training mode within the predefined minimum duration time.
A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.
Error alert encoding for improved error mitigation is described. In one or more implementations, a system includes a processor configured to receive an encoded signal indicating a type of an error detected in a memory, and output one or more mitigation commands to mitigate the type of the error detected in the memory based on the encoded signal. In one or more implementations, a memory system includes a memory and a buffer. The buffer is configured to output an encoded signal indicating a type of an error detected in the memory.
A processing system preconditions block-compressed texture blocks by separately streaming color components and index components for lossless compression. The processing system preconditions the color components for linear compression, such that color component data for adjacent compressed blocks in a row are further compressed using lossless compression. Lossless compression is performed for color components spanning multiple rows to leverage patterns in color components that extend vertically across a frame. The processing system further divides input color component and index component data into pages of memory (e.g., 64 kB pages), such that each page can be independently losslessly compressed and decompressed. The processing system applies delta encoding to color component data so that a single instance of color data and differences from the stored color data are stored for each page.
A method for dimensioning a land grid array pad can include forming an initial landing area of a land grid array pad, wherein the initial landing area is dimensioned to cause at least a majority of a landing surface of one or more socket pins to land off of the initial landing area prior to actuation of one or more sockets including the one or more socket pins. The method can also include forming a final landing area of the land grid array pad, wherein the final landing area is dimensioned to maintain electrical contact with the landing surface of the one or more socket pins after actuation of the one or more sockets including the one or more socket pins. Various other methods and systems are also disclosed.
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 21/48 - Fabrication ou traitement de parties, p. ex. de conteneurs, avant l'assemblage des dispositifs, en utilisant des procédés non couverts par l'un uniquement des groupes ou
H01R 12/71 - Dispositifs de couplage pour circuits imprimés rigides ou structures similaires
28.
Soft Disconnect and Reconnect for USB Tunneled Path
A method of operating a Universal Serial Bus (USB) host system includes: disabling, by a USB host driver of the USB host system, a first tunneled path between a first port of a USB host controller of the USB host system and a first port of a USB device controller of a USB device, where the first tunneled path is configured to, through protocol tunneling, transmit first data packets of a first protocol format; sending, by the USB host driver, a request for protocol switching to a connection manager of the USB host system; disconnecting, by the connection manager, the first tunneled path; and establishing, by the connection manager, a second tunneled path between a second port of the USB host controller and a second port of the USB device controller.
With minimal preprocessing of trees of materials in textures, this approach progressively caches outputs of some material nodes that are evaluated while rendering a scene. A node may be the root of a subtree, and the node may generate a value of a texel based on values of other nodes in the subtree. The subtree of a cacheable node contains no shading-point dependent node as a descendant other than texture coordinates. When reaching the cacheable node during a material evaluation for rendering, a descriptor of the node is used as a key to store or reuse the texel value of the cacheable node in a materials cache in memory. By defining cacheable nodes at highest possible levels in a tree, repeated evaluation of most nodes in the tree is avoided. For multithreaded acceleration, a materials cache is designed for thread-safe operation with an atomic instruction.
Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
31.
DATA COLLECTION AND STORAGE DURING LOW-POWER STATES
A processing system includes one or more sensors configured to generate sensor data while a memory of the processing system is in a low-power state. As the sensors generate the sensor data, the sensor data is stored in a buffer. The processing system further includes a sensor data management circuitry that tracks a usage of the buffer. Based on the usage of the buffer exceeding a threshold, the sensor data management circuitry is configured to wake at least a portion of the memory from the low-power state. Once the memory exits the low-power state, the processing system transfers the sensor data from the buffer to one or more locations within the memory. After writing the sensor data to the memory, the processing system then places at least a portion of the memory back in the low-power state.
A memory controller includes a command queue stage for storing decoded memory access requests, a first arbiter operable to select first decoded memory access requests for a first pseudo channel from the command queue stage, and a second arbiter operable to select second decoded memory access requests for a second pseudo channel from the command queue stage. Each of the first arbiter and the second arbiter is operable to select a first streak of a first type of accesses, and to change to selecting a second streak of a second type of accesses in response to the first arbiter and the second arbiter meeting a cross mode condition.
A masked atomic update instruction is described that atomically performs compare and exchange operations on select bits of a data structure. Executing the masked atomic update instruction compares respective source values with respective values of bits stored at a destination data storage location. If the respective bit values match, one or more of the respective bit values at the destination are replaced with one or more defined replacement values. Alternatively, if the respective bit values do not match, the destination is not modified. The masked atomic update instruction enables a processing unit to mask out bits of the destination data storage location that are not involved in the comparison or update. The masked atomic update instruction thus provides bit-level granularity by which another thread is prevented from accessing bits of the destination data storage location. This bit-level granularity advantageously permits multiple threads to simultaneously access a common data storage location.
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A security framework for virtual machines is described. In one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. The system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. Further, the system includes a root framework-secure virtual machine instantiated by the virtual machine monitor. In accordance with the described techniques, the root framework-secure virtual machine is configured to control access to the hardware platform by the framework-secure virtual machines instantiated by the virtual machine monitor.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
Embodiments herein use constraints from a target process (e.g., testing a semiconductor wafer or designing a new integrated circuit) and historical real-world samples (e.g., probe test sample, fault detection, or measured signals) to generate synthesized samples using AI synthesis embedded in a digital twin. These test samples can be combined with real-world test samples and then evaluated to determine next actions. In another example, a digital twin can use an new IC design and a design from an older, but related, IC to synthesize new IC design samples.
Embodiments herein describe a method and system for configuring device equalization self-training mode (DESTM) controls using in-band signaling, the DESTM controls including at least setting a minimum duration time, using a host to enable the DESTM controls, triggering a buffer to perform a self-training mode, sending linear-feedback shift register (LFSR) patterns to the buffer for the minimum duration time, and waiting for the minimum completion time to end before disabling the DESTM. The minimum duration time indicates a time that the self-training mode is active and is predefined. The buffer executes the self-training mode within the predefined minimum duration time.
G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel "T-bit" in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. Each entry in the guest page table for the root-trusted guest additionally includes a "C-bit" that indicates whether the corresponding memory page is a protected page. Combined C-bit and T-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.
G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
38.
METHODS OF FORMING SEMICONDUCTOR CLADDING LAYERS FOR SOURCE AND DRAIN CONTACTS AND SIDEWALL METAL CONTACTS OF A SEMICONDUCTOR DEVICE
Aspects of the present disclosure provide a method of fabricating a semiconductor device. The method includes forming a plurality of first channels over a substrate of the semiconductor device, the plurality of first channels being stacked over each other and extending along a top surface of the substrate; forming one or more first source-and-drain (S/D) contacts for the plurality of first channels; and forming one or more cladding layers that cover the one or more first S/D contacts, a material of the one or more cladding layers being complementary to a material of the one or more first S/D contacts.
H10D 84/03 - Fabrication ou traitement caractérisés par l'utilisation de technologies basées sur les matériaux utilisant une technologie du groupe IV, p. ex. technologie au silicium ou au carbure de silicium [SiC]
H10D 84/40 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou avec au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET avec des transistors BJT
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
39.
Transforming All-Bank Processing-in-Memory Operations into Multiple Masked Processing-in-Memory Operations
A system includes memory hardware including a memory and a processing-in-memory component. A system includes a host including at least one core. A system includes a memory controller including a scheduling system. The scheduling system transforms an all-bank processing-in-memory command into multiple masked processing-in-memory commands. The scheduling system also schedules the multiple masked processing-in-memory commands to the processing-in-memory component.
Embodiments herein describe creating multiple packet fragments from a large data chunk that, for example, exceeds a maximum transmission unit (MTU) supported by a network. In one embodiment, a network interface controller or card (NIC) receives a direct memory access (DMA) from a connected host to transmit an IP packet or data using remote direct memory access (RDMA) technologies. The NIC can evaluate the data chunk associated with the DMA request and determine whether it exceeds the MTU for the network. Assuming it does, the NIC determines how many fragments to divide the data chunk into, and can fragment any portion of the data at flexible packet/payload offsets. The NIC can then retrieve the data chunk from host memory fragment-by-fragment, rather than reading the data chunk all at once, generating headers for the fragments, and then transmit them as packet fragments.
H04L 67/1097 - Protocoles dans lesquels une application est distribuée parmi les nœuds du réseau pour le stockage distribué de données dans des réseaux, p. ex. dispositions de transport pour le système de fichiers réseau [NFS], réseaux de stockage [SAN] ou stockage en réseau [NAS]
A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
A memory controller includes a command queue stage, an arbitration stage, and a dispatch queue. The command queue stage stores decoded memory access requests. The arbitration stage is operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shred resource. The dispatch queue has first and second upstream ports for receiving the first and second memory commands, and a downstream port for conducting first data of the first memory commands time-multiplexed with second data of the second memory commands.
Systems and methods described herein for storing primitive data for ray tracing and/or rasterization. The data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal or rasterization. Vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. Mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. Further, triangle identifiers are derived from the triangle's position in the strip. The block can further store geometry identifiers and opacity maps corresponding to primitive data.
Systems and methods for ray intersection against primitives are described. Primitive data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal. Vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. Mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. Primitives can alternatively be quantized to generate primitive packets, that are stored compactly in, with, or near a leaf node of an acceleration structure. Low-precision intersection testers test a ray simultaneously against primitives to find candidate triangles that require full-precision intersection. Primitives that generate an inconclusive result during low-precision testing are retested using full-precision testers to definitively determine ray-triangle hits or misses.
Systems and methods described herein for encoding geometrical primitives into data blocks are disclosed. In an implementation, these data blocks can be directly consumed by an application programming interface (API) for ray traversal or rasterization. A graphics application running on a ray tracing system provides primitive data to the graphics API using a data format that defines fixed-point, compressed, and fixed-size data blocks to store encoded primitive data. The stored data can be decompressed to construct an acceleration structure. Data from the graphics application undergoes geometry clustering in a manner that these can be directly exposed by the API to be consumed by a processing circuitry when constructing acceleration structures.
An apparatus and method for efficiently migrating the execution of threads between multiple parallel lanes of execution. In various implementations, a computing system includes multiple vector processing circuits of a compute circuit that executes multiple lanes of multiple waves. Each lane includes a key indicating a path of execution. When a lane of the multiple lanes of execution executes a stream wave coalescing (SWC) reorder instruction, a control circuit compares keys of waves that have previously executed the SWC reorder instruction. When the number of lanes with a matching key exceeds a threshold and after identifying at least this number of lanes to swap, the control circuit swaps continuation state information (live active state information) between lanes of an emitting wave that do not have a matching key and lanes of contributing waves that do have a matching key. The resulting (reordered) emitting wave executes more efficiently, which increases performance.
G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
The disclosed circuit can select micro-operations specifically for converting a value in a first number format to a second number format. The circuit can include micro-operations for various conversions between different number formats, including number formats of different floating-point precisions. Various other methods, systems, and computer-readable media are also disclosed.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
48.
INTERSECTION TESTING ON DENSE GEOMETRY DATA USING TRIANGLE PREFILTERING
Systems and methods for ray intersection against primitives are described. Primitive data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal. Vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. Mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. Primitives can alternatively be quantized to generate primitive packets, that are stored compactly in, with, or near a leaf node of an acceleration structure. Low-precision intersection testers test a ray simultaneously against primitives to find candidate triangles that require full-precision intersection. Primitives that generate an inconclusive result during low-precision testing are retested using full-precision testers to definitively determine ray-triangle hits or misses.
Systems and methods described herein for storing primitive data for ray tracing and/or rasterization. The data is encoded efficiently into arrays of fixed-size data blocks using a data format which can be directly consumed for ray traversal or rasterization. Vertex data in a block is pre-quantized and stored using a fixed-bit quantization grid. Mesh connectivity is encoded using a triangle strips based on control values representing triangle interconnectivity, and a compressed index buffer storing indices for vertices in each strip. Further, triangle identifiers are derived from the triangle's position in the strip. The block can further store geometry identifiers and opacity maps corresponding to primitive data.
A memory controller includes a command queue stage, an arbitration stage, and a dispatch queue. The command queue stage stores decoded memory access requests. The arbitration stage is operable to select first and second memory commands from the command queue stage for first and second pseudo-channels, respectively, using a shred resource. The dispatch queue has first and second upstream ports for receiving the first and second memory commands, and a downstream port for conducting first data of tire first memory commands time-multiplexed with second data of the second memory commands.
The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
The disclosed circuit is configured to round a value in a first number format using a random value. Using the rounded value, the circuit can convert the rounded value to a second number format that has a lower precision than a precision of the first number format. Various other methods, systems, and computer-readable media are also disclosed.
The disclosed circuit can interpret a bit sequence as a value based on one of multiple floating point number formats in a bias mode indicated by a bias mode indicator. The circuit can and perform an operation using the value in the bias mode. Various other methods, systems, and computer-readable media are also disclosed.
G06F 7/556 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul de fonctions logarithmiques ou exponentielles
G06F 7/483 - Calculs avec des nombres représentés par une combinaison non linéaire de nombres codés, p. ex. nombres rationnels, système de numération logarithmique ou nombres à virgule flottante
The disclosed processing circuit can perform an operation with a first operand having a first number format and a second operand having a second number format by directly using the first operand in the first number format and the second operand in the second number format to produce an output result. Various other methods, systems, and computer-readable media are also disclosed.
Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel “T-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. Each entry in the guest page table for the root-trusted guest additionally includes a “C-bit” that indicates whether the corresponding memory page is a protected page. Combined C-bit and T-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.
A security framework for virtual machines is described. In one or more implementations, a hardware platform comprises physical computer hardware, the physical computer hardware including one or more processing units and one or more memories. The system also includes a virtual machine monitor configured to virtualize the physical computer hardware of the hardware platform to instantiate a plurality of framework-secure virtual machines. Further, the system includes a root framework-secure virtual machine instantiated by the virtual machine monitor. In accordance with the described techniques, the root framework-secure virtual machine is configured to control access to the hardware platform by the framework-secure virtual machines instantiated by the virtual machine monitor.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
An integrated circuit die stack is disclosed that includes a digital device layer, an underlying layer, and a cooling solution. The underlying layer has a lower power consumption relative to the digital device layer. The digital device layer is disposed closer to the cooling solution. In another example, memory layers and a digital device layer are configured into a three-dimensional memory stack. The digital device layer has a first surface (side) located closest to a cooling solution and the memory layers are located on a second surface (side) of the digital device layer opposite to the first surface (side) thereof. The cooling solution is adapted to receive and dissipate heat from the digital device layer and the memory layers.
H01L 23/427 - Refroidissement par changement d'état, p. ex. caloducs
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
58.
DISTRIBUTED REVERSE INDEXING OF NETWORK FLOW LOGS IN A FABRIC COMPOSED OF DPUS
Rather than collecting flow logs at a central location, and then processing these flow logs to create general purpose or specialized data stores, the embodiments herein rely on the network appliances to create the flow logs and metadata that indexes these flow logs. The flow logs and the metadata can then be collected at the central location (e.g., a central analyzer) and merged with flow logs and metadata generated by other network appliances to yield a data store that can be used to analyze the flow logs in computing environment (e.g., a data center).
H04L 41/069 - Gestion des fautes, des événements, des alarmes ou des notifications en utilisant des journaux de notificationsPost-traitement des notifications
A data processor includes a memory controller and a physical interface circuit coupled to the memory controller. In response to a system startup, the memory controller controls the physical interface circuit to selectively train a memory based on whether a first memory clock frequency of a plurality of power states equals any other memory clock frequency of the plurality of power states.
Dynamic voltage drop analysis for a circuit design includes generating, by computer hardware, bias information for a circuit design. The bias information specifies switching information for a plurality of instances of one or more standard cells of the circuit design. A schedule specifying switching for the plurality of instances of the circuit design is generated by the computer hardware based on the bias information. A dynamic voltage analysis is performed by the computer hardware on the circuit design to generate dynamic voltage analysis results by switching the plurality of instances of the circuit design based on the schedule.
G06F 30/367 - Vérification de la conception, p. ex. par simulation, programme de simulation avec emphase de circuit intégré [SPICE], méthodes directes ou de relaxation
G06F 119/06 - Analyse de puissance ou optimisation de puissance
Disclosed herein are chip packages that integrate multiple compute dies through a single interposer die to a memory stack. The interposer die includes memory controller circuitry that allowing multiple compute dies to access the memory stack in an efficient manner.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
H01L 23/04 - ConteneursScellements caractérisés par la forme
A processing system [100] includes one or more accelerator units (AUs) [114] each having a modular architecture. To this end, each AU includes a connection circuitry [116] and one or more memory stacks [122] disposed on the connection circuitry. Further, each AU includes one or more interposer dies [118] each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack via the connection circuitry. Further, each interposer die of each AU includes sets of circuitry [578, 580] configured to concurrently support two or more types of compute dies [300, 400].
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
A processing unit includes a plurality of processing cores and is configured to arrange a sparse matrix for parallel performance by the cores on different rows of the matrix at least in part by calculating a respective quantity of non-zero elements in each row, assigning each row to a respective collection according to the respective quantity of non-zero elements for the row, wherein the processing unit is configured to assign at least one first row of the sparse matrix to respective collections of in parallel with assigning at least one second row of the sparse matrix to respective collections, and performing at least one mathematical operation on at least a first collection of the plurality of collections in parallel with performing the at least one mathematical operation on at least a second collection of the plurality of collections.
A technique for rendering is provided. The technique includes obtaining one or more samples for a pixel, the samples obtained for a microfacet surface from a spherical cap cut off by a lower plane positioned to exclude reflected rays that are occluded by the microfacet surface; obtaining one or more contributions corresponding to the one or more samples; determining a color for the pixel based on the one or more contributions.
As part of rendering a scene including at least one graphics object in a display space, the display space is divided into a plurality of tiles. A determination is made that contents of at least two of the plurality of tiles are no longer used after a current render pass. A write back memory address associated with a second tile is changed to match a write back memory address associated with a first tile. As a result, data is overwritten on a same physical page.
A processing system includes one or more accelerator units (AUs) each having a modular architecture. To this end, each AU includes a connection circuitry and one or more memory stacks disposed on the connection circuitry. Further, each AU includes one or more interposer dies each disposed on the connection circuitry such that each interposer die of the one or more interposer dies is communicatively coupled to a corresponding memory stack of the memory stacks via the connection circuitry. Further, each interposer die of each AU includes circuitry configured to concurrently support two or more types of compute dies.
A method can include overriding settings of an integrated circuit device by reading one or more settings from a setting record that correspond to a part number of the integrated circuit device. The method can also include performing an override of the settings of the integrated circuit device based on the one or more settings of the setting record that correspond to the part number of the integrated circuit device. Various other methods and systems are also disclosed.
G06F 21/70 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur
68.
SYSTEM AND METHOD FOR SEU DETECTION AND CORRECTION
Embodiments herein describe a circuit for detecting a single event upset (SEU). The circuit includes a latch including an output node, a first parity node, and a second parity node and correction circuitry configured to correct a single event upset (SEU) at the output node using the first and second parity nodes.
A chip package and method for fabricating the same are provided that include a IC dies bonded to a thermal carrier having a plurality of metallic pillars. In one example, a chip package includes an interconnect routing structure and a first die disposed on a first surface of the interconnect routing structure. The first die has a circuitry connected to a circuitry of the interconnect routing structure. The chip package also includes a second die at least partially disposed over the first die. The second die has a circuitry connected to the circuitry of the first die. A thermal carrier is bonded on the second die. At least one of the thermal carrier, the first die, or the second die includes a plurality of metallic pillars configured to transfer heat, wherein the plurality of metallic pillars are electrically floating.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/36 - Emploi de matériaux spécifiés ou mise en forme, en vue de faciliter le refroidissement ou le chauffage, p. ex. dissipateurs de chaleur
H01L 23/538 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre la structure d'interconnexion entre une pluralité de puces semi-conductrices se trouvant au-dessus ou à l'intérieur de substrats isolants
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
Disclosed herein are chip packages that integrate multiple compute dies through a single interposer die to a memory stack. The interposer die includes memory controller circuitry that allowing multiple compute dies to access the memory stack in an efficient manner.
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 23/053 - ConteneursScellements caractérisés par la forme le conteneur étant une structure creuse ayant une base isolante qui sert de support pour le corps semi-conducteur
H01L 23/498 - Connexions électriques sur des substrats isolants
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H10B 80/00 - Ensembles de plusieurs dispositifs comprenant au moins un dispositif de mémoire couvert par la présente sous-classe
71.
Prioritization of memory traffic for multi-process workloads
The disclosed device includes a memory-semantic fabric comprising memory components accessible by multiple processors and a controller for the memory-semantic fabric. The controller receives, from multiple processes, memory requests for a memory-semantic fabric. The controller also identifies, within the processes, a source process for each of the memory requests and prioritizes forwarding the memory requests to the memory-semantic fabric based on the source processes. Various other methods, systems, and computer-readable media are also disclosed.
A memory controller includes a command queue for receiving memory access requests and an arbiter. The arbiter is operable to allow cross-mode activations during a streak of accesses of a current mode in response to a number of cross-mode accesses present in the command queue exceeding an adaptive threshold.
In accordance with the described techniques, a host processor receives a task graph including tasks and indicating dependencies between the task graph. The host processor formats the task graph, in part, by sorting the tasks of the task graph in an order based on the dependencies between the tasks. Further, the host processor submits the formatted task graph to a scalable input/output virtualization (SIOV) device, which directs the SIOV device to process the tasks of the task graph based on the order.
Memory access validation for input/output operations using an interposer is described. In one or more implementations, an interposer is disposed logically between an input/output device and a memory. The interposer receives a plurality of requests from the input/output device to access the memory non-sequentially in association with an input/output operation. Responsive to each request, the interposer updates an accumulated error code using error-detection logic. Based upon the accumulated error code, the interposer outputs an I/O validity indicator.
G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts
G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
75.
SYNCHRONIZED AUDIO STREAMING FROM MULTIPLE CONTROLLERS
A processing system includes a hardware synchronizer to synchronize the transmission of audio data from multiple I2S controllers of a processing system to one or more audio codecs. In some embodiments, each of the I2S controllers receives audio data from one or more audio data sources and stores the audio data at a buffer associated with the controller. The hardware synchronizer initiates synchronized transmission of the audio data from the plurality of controllers to the one or more codecs in response to the buffer associated with each controller being filled to a predetermined level. In some embodiments, until the controllers begin transmission of the audio data, the controllers transmit mute (null) data to the one or more codecs such that the one or more codecs receives a frame start followed by null data for each frame.
A processing system includes dispatch circuitry that sends elements to one or more processing circuits such as shader circuitry for execution. The dispatch circuitry includes a dispatch queue and an arbitration circuit. The dispatch queue stores the elements to be sent to the one or more processing circuits. The arbitration circuit schedules the elements of the dispatch queue for execution based on priority indicators corresponding to the elements. As a result, prioritization of the elements is implemented at the dispatch circuitry in hardware without changing a design of the dispatch queue to store the priority information.
An accelerated processor includes a processor core die including a plurality of compute units, the plurality of compute units including a first level (L1) cache. The accelerated processor also includes a plurality of memory cache dies coupled to the processor core die, the plurality of memory cache dies including a last level cache (LLC) such as a level 3 (L3) cache. The accelerated processor includes an LLC controller to issue a cache access request to the LLC and, based on a latency of the cache access request, direct the cache access request to a subset of the plurality of memory cache dies.
In accordance with the described techniques for data compression using reconfigurable hardware based on data redundancy patterns, a computing device includes a memory, processing-in-memory units, a host processing unit, and a compression unit having reconfigurable logic for performing multiple compression algorithms. The host processing unit issues processing-in-memory requests instructing the processing-in-memory units to scan a block of the memory for one or more data redundancy patterns, and to identify a compression algorithm of the multiple compression algorithms based on the one or more data redundancy patterns. Further, the host processing unit issues a memory request to access a memory address in the block of the memory. The memory request causes data of the memory address to be communicated from the block of the memory to the compression unit to be compressed using the compression algorithm.
A fused bounding volume hierarchy, which is a combination of a base bounding volume hierarchy and one or more non-base bounding volume hierarchies, is generated. For each non-base bounding volume hierarchy, multiple subtrees in the non-base bounding volume hierarchy that include less than a threshold number of child nodes are identified. Each of these subtrees is then fused with the base bounding volume hierarchy at one of the nodes of the base bounding volume hierarchy, and an identifier of the level of detail for the non-base bounding volume hierarchy is included in the node. When displaying a scene or image, for a particular portion of the scene or image the level of detail to use is identified. The fused bounding volume hierarchy is traversed and the geometric objects in the nodes of the fused bounding volume hierarchy corresponding to the identified level of detail are displayed.
The disclosed device includes a cache organized by sets and ways and a control circuit that selects a first way for a cache replacement from a first half of a set of ways. The control circuit also selects another way from a second half of the set of ways, and uses the second way for the cache replacement when the first way is unavailable. Various other methods, systems, and computer-readable media are also disclosed.
G06F 12/122 - Commande de remplacement utilisant des algorithmes de remplacement du type le moins fréquemment utilisé [LFU], p. ex. avec valeur de comptage individuelle
Scratchpad memory translation lookaside buffer techniques are described. In an implementation, the techniques described herein relate to a device including a memory management unit implemented in hardware of an integrated circuit to receive a mapping instruction from a mapping instruction source, the mapping instruction specifying a mapping between a virtual memory address and a physical memory address of a scratchpad memory and store a virtual-to-physical mapping entry in a translation lookaside buffer based on the mapping instruction.
G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
82.
SYSTEMS AND METHODS FOR IMPROVING EMBEDDED SUBSTRATE THERMALS
A method can include embedding one or more thermal sources in a semiconductor package substrate and positioning one or more substrate buildup layers above the one or more thermal sources. The method can also include forming one or more thermal vias in the one or more substrate buildup layers. Various other methods and systems are also disclosed.
Efficient memory operation using a destructive read memory array is described. In accordance with the described techniques, a system may include a memory configured to store data of a first logic state in a ferroelectric capacitor when an electric polarization of the ferroelectric capacitor is in a first direction. A system may include a controller configured to erase the data from the memory by commanding the electric polarization of the ferroelectric capacitor in a second direction, opposite of the first direction and skipping a subsequent write operation of a null value to the memory.
G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
G11C 11/22 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments électriques utilisant des éléments ferro-électriques
H10B 53/30 - Dispositifs RAM ferro-électrique [FeRAM] comprenant des condensateurs ferro-électriques de mémoire caractérisés par la région noyau de mémoire
84.
TECHNIQUE FOR GENERATING A BOUNDING VOLUME HIERARCHY
A technique for building a bounding volume hierarchy is disclosed. The technique includes for a subject node, selecting a dimension along which to perform a split to form child nodes of the subject node; assigning primitives of the subject node to the child nodes; and updating bounds for the child nodes in a next split dimension and not in the other dimensions.
A technique for rendering is provided. The technique includes determining a level of detail for a shade space texture and a screen space; shading the shade space texture having a resolution based on the level of detail; and for a reconstruction operation, performing sampling from the shade space texture, the sampling including a high frequency attenuation of samples of the shade space texture.
A technique for performing ray tracing operations is provided. The technique includes for a ray being tested for intersection with geometry associated with a bounding volume hierarchy, traversing to a pre-filtering node that includes information for filtering out triangles of a leaf node of the bounding volume hierarchy; evaluating a quantized ray that corresponds to the ray against quantized triangles of the pre-filtering node to filter out one or more triangles of the leaf node from consideration; and testing the triangles of the leaf node that are not filtered out and not testing the triangles of the leaf node that are filtered out.
Systems and techniques for selectively transferring one or more portions of a cache block in response to a request are described. Computing system components are informed as to instances where data transfer operations involve moving less than an entirety of data included in a cache block cache block. In one example, executable code for a computational task includes hints that identify when memory requests involve accessing and transmitting less than an entirety of a cache block and cause system components to communicate a subset of the cache block during a memory access. In another example, a data differentiator unit is implemented to analyze a cache block and return a portion of the cache block that is selected based on one or more criteria specified for a computational task. The described techniques thus overcome conventional drawbacks facing systems that transmit an entire cache block when only a portion is needed.
G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatially-adaptive sampling; performing a sparse shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatially-adaptive sampling; performing a regularization operation based on an output of the sparse shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
A technique for rendering is provided. The technique includes performing a visibility pass that designates portions of shade space textures visible in a scene, wherein the visibility pass generates tiles that cover shade space textures visible in the scene; performing a rate controller operation on output of the visibility pass using spatiotemporal adaptive sampling; performing a shade space shading operation on the tiles that cover the shade space textures visible in the scene based on a result of the spatiotemporal adaptive sampling; performing a regularization operation based on an output of the shade space shading operation; and performing a reconstruction operation using output from the regularization operation to produce a final scene.
Devices and methods for rendering objects using ray tracing are provided which include during a build time: generating an accelerated hierarchy structure comprising data representing an approximate volume bounding a group of geometric shapes representing the objects in the scene and data representing the geometric shapes; and generating additional data used to transform rays, to be cast in the scene, from a high precision space to a low precision space; and during a render time occurring after the build time: performing ray intersection tests, using the additional data generated during the build time, for the rays in the scene; and rendering the scene based on the ray intersection tests. Because the additional data is generated prior to render time, the additional data can be used to perform the ray intersection testing more efficiently.
The disclosed device includes power circuits that can communicate with a control circuit. In response to a power circuit communicating a low efficiency state, the control circuit can redistribute at least a portion of a load of the power circuit to one or more other power circuits. Various other methods, systems, and computer-readable media are also disclosed.
H02J 4/00 - Circuits pour réseaux principaux ou de distribution, la nature alternative ou continue du courant n'étant pas précisée
G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
92.
ARBITRATED INTERRUPT STEERING IN HETEROGENEOUS PROCESSORS
The disclosed device includes a heterogeneous processor architecture having heterogeneous processors, and a control circuit that can assign, in response to an interrupt, the interrupt to one of the heterogenous processors that is selected based on power efficiency. Various other methods, systems, and computer-readable media are also disclosed.
A data interface connector and method of manufacture and/or assembly thereof can include first electrical terminals at a first end of the data interface connector, the first electrical terminals being configured to interface with a mating data interface connector conforming to a first data interface specification. The data interface connector and method of manufacture and/or assembly thereof can include second electrical terminals at a second end of the data interface connector, the second electrical terminals being configured to interface with data interface pads on a circuit board; where the data interface pads have pitches and lengths according to a second data interface specification.
Systems, apparatuses, and methods for rendering textures by prefetching texture data are disclosed. Source texture data is identified based at least in part on one or more programmable instructions. A prefetch of the source texture data is caused based on level of details associated with the source texture data. Further, a list data blocks of the source texture data and a mapping between each data block and corresponding allocated memory address space allocated to each data block on the memory device is maintained. Responsive to a request to load a given data block, the given data block from the memory device is loaded using the list.
Disclosed is a computer-implemented method for model ensemble acceleration in an active learning loop. The method includes receiving a set of datapoint inputs, where each datapoint input is an unlabeled equivalent of other datapoint inputs in the set of datapoint inputs and has a different applied weight value. The method then executes a set of neural network models, where the execution of each neural network model is based on the received set of datapoint inputs. The outputs from the set of neural network models are analyzed, where an inference computation is performed, and a label for the set of datapoints is determined. The method then stores the labeled set of datapoint inputs in a database. Various other methods, systems, and computer-readable media are also disclosed.
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
An apparatus and method for reducing the memory bandwidth of executing machine learning models. A computing system includes two or more processing nodes, each including at least one or more processors and a corresponding local memory. Switch circuitry communicates with at least the local memories and a system memory of the computing system. The switch includes multiple direct memory access (DMA) interfaces. Each of one or more processing nodes stores multiple embedding rows of embedding tables. A processor of the processing node identifies two or more embedding rows as source operands of a reduction operation. The switch executes memory access requests to retrieve data of the two or more embedding rows from the corresponding local memory, and generates a result by performing the reduction operation. The switch sends the result to the local memory.
An apparatus and method for efficiently managing memory requests. An integrated circuit includes multiple compute circuits, each capable of processing a data block of multiple data blocks. An amount of available data storage space of a cache is smaller than storage space in a memory for storing the multiple data blocks. In various implementations, the multiple compute circuits process data blocks in a contiguous manner, and pointer updating circuitry assigns data block identifiers in a contiguous manner. The circuitry updates the pointer of an initial data block to use for a particular stage of data processing to a value which increases cache hits during the particular stage of data processing. The circuitry accounts for the number of data blocks of intermediate results to increase or decrease for a particular stage of data processing when updating the pointers.
A hybrid bonding method includes fabricating plural semiconductor devices in a region of a bottom wafer adjacent to a front surface thereof, fusion bonding the front surface to a carrier substrate, thinning the bottom wafer opposite to the front surface to expose conductive regions of the semiconductor devices, forming a dielectric layer over a backside of the semiconductor devices, forming openings in the dielectric layer to expose the conductive regions, forming metal pads within the openings, dicing the bottom wafer and the carrier substrate to singulate the plural semiconductor devices, bonding the dielectric layer overlying the backside of the semiconductor devices to a dielectric layer overlying a front surface of a top wafer, bonding the metal pads within the openings in the dielectric layer to metal pads overlying the front surface of the top wafer, and removing the carrier substrate from the front surface of the bottom wafer.
H01L 21/20 - Dépôt de matériaux semi-conducteurs sur un substrat, p. ex. croissance épitaxiale
H01L 21/683 - Appareils spécialement adaptés pour la manipulation des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide pendant leur fabrication ou leur traitementAppareils spécialement adaptés pour la manipulation des plaquettes pendant la fabrication ou le traitement des dispositifs à semi-conducteurs ou des dispositifs électriques à l'état solide ou de leurs composants pour le maintien ou la préhension
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
99.
SYSTEMS AND METHODS FOR ENABLING A FEATURE OF A SEMICONDUCTOR DEVICE
A computer-implemented method for enabling a feature of a semiconductor device can include receiving, by at least one processor of a semiconductor device, a command to enable a feature of the semiconductor device. The method can also include burning, by the at least one processor and in response to the command, an electronic fuse of the semiconductor device. Various other methods, systems, and computer-readable media are also disclosed.
G06F 1/08 - Générateurs d'horloge ayant une fréquence de base modifiable ou programmable
G06F 21/64 - Protection de l’intégrité des données, p. ex. par sommes de contrôle, certificats ou signatures
G06F 21/73 - Protection de composants spécifiques internes ou périphériques, où la protection d'un composant mène à la protection de tout le calculateur pour assurer la sécurité du calcul ou du traitement de l’information par création ou détermination de l’identification de la machine, p. ex. numéros de série
H01L 23/525 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées avec des interconnexions modifiables
100.
VOLTAGE REGULATOR WITH PROGRAMMABLE TELEMETRY CONFIGURATION
An apparatus can include: a processor; a voltage regulator configured to provide a processor voltage and a processor current to the processor; and a voltage regulator controller that can include a current sensor comprising an analog-to-digital converter (ADC) having an ADC input range and configured to provide current data based on an ADC input voltage, and a configuration manager configured to receive processor power data and adjust the ADC input range based on the processor power data. Various other methods, systems, and computer-readable media are also disclosed.
H03M 1/36 - Valeur analogique comparée à des valeurs de référence uniquement simultanément, c.-à-d. du type parallèle
H03M 1/16 - Conversion par étapes, avec pour chaque étape la mise en jeu de moyens de conversion identiques ou différents et délivrant plus d'un bit avec modification de l'échelle, c.-à-d. en changeant l'amplification entre les étapes
H04Q 9/00 - Dispositions dans les systèmes de commande à distance ou de télémétrie pour appeler sélectivement une sous-station à partir d'une station principale, sous-station dans laquelle un appareil recherché est choisi pour appliquer un signal de commande ou pour obtenir des valeurs mesurées
