Abrégé

An apparatus is described. The apparatus includes a network interface having a system interface, a media access interface and circuitry to construct a block of null values for a logical block address (LBA) in response to a remote storage system having informed the network interface that the LBA was un-mappable.

Classes IPC  ?

• G06F 12/0811 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec hiérarchies de mémoires cache multi-niveaux
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/0873 - Mappage de mémoire de mémoire cache vers des dispositifs ou des parties de dispositifs de stockage

Abrégé

An embodiment of an electronic apparatus may include a substrate and a controller coupled to the substrate, the controller including circuitry to control access to a NAND-based storage media that includes a plurality of NAND devices located on the substrate and organized into two or more physical clusters with each NAND device uniquely assigned to one of the two or more physical clusters, perform data access to a first physical cluster of the two or more physical clusters at a first bandwidth, and perform data access to a second physical cluster of the two or more physical clusters at a second bandwidth that is slower than the first bandwidth. Other embodiments are disclosed and claimed.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device and related method, the device including system memory for storing at least two queue groups, each of which includes commands, and processing circuitry. For each respective queue group, the processing circuitry determines an allocated command value indicative of a number of commands that are capable of being fetched from the respective queue group, determines a number of outstanding commands to be fetched from the respective queue group, and compares the allocated command value to the number of outstanding commands to be fetched for the respective queue group. When the allocated command value is greater than the number of outstanding commands to be fetched for the respective queue group, the processing circuitry designates the respective queue group as an available queue group. The processing circuitry then selects a queue group from the designated available queue groups and fetches at least one command from the selected queue group.

Classes IPC  ?

• G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire

Abrégé

In accordance with some embodiments of the present disclosure, a method is performed by processing circuitry of a storage device for writing data to memory of a storage device. The method is related to executing a program to write data written in a plurality of single-layer cells (SLCs) in a first portion of the memory to a plurality of multi-level cells (MLCs) in a second portion of the memory using a single program command. The single program command includes an address of each SLC in the first portion of the memory and optionally, additional information regarding SLC read-level shifts. Executing the single program command includes reading from each SLC of the plurality of SLCs, storing at least some of the respective SLC data in the plurality of latches, and writing the SLC data that was stored in the plurality of latches to the plurality of MLCs.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

A method for updating a device includes receiving an instruction to update from a first configuration in the device to a second configuration, where a first heap memory allocated to the first configuration includes multiple first allocated memory blocks and corresponding first memory blocks metadata. The method also includes performing a warm reset, the reset including determining, based on the first memory blocks metadata, that when updating from the first configuration to the second configuration, data of at least one of the first allocated memory blocks should be persisted to a second heap memory allocated to the second configuration, and causing the device to update from the first configuration to the second configuration, where the update includes persisting, based on the first memory blocks metadata, the data of at least one of the first allocated memory blocks to a second heap memory allocated to the second configuration.

Classes IPC  ?

• G06F 8/654 - Mises à jour utilisant des techniques spécialement adaptées aux mémoires de masse réinscriptibles, p. ex. aux mémoires EEPROM ou flash
• G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
• G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

Abrégé

Mechanisms, including systems, methods, and media, for tuning a solid-state drive (SSD) are provided, the mechanisms including: providing as an input to a first neural network (NN) current parameter settings (PSs) of the SSD; receiving as an output from the first NN at least one adjustment to the current PSs; based on the at least one adjustment, adjusting the current PSs of the SSD so that the SSD is using adjusted PSs; causing the SSD to execute a workload using the adjusted PSs; determining performance data of the SSD while executing the workload; determining a reward value based on the performance data; and back propagating the first NN based on the reward value.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An embodiment of an electronic apparatus comprises a main board, a wing board electrically coupled to the main board by a flexible connector along an edge of the main board, wherein the wing board is arranged at an angle that is non-parallel with respect to the main board. Other embodiments are disclosed and claimed.

Classes IPC  ?

• H05K 1/14 - Association structurale de plusieurs circuits imprimés
• H05K 1/02 - Circuits imprimés Détails
• H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

Abrégé

A method for updating a device includes receiving an instruction to update from a first configuration in the device to a second configuration, where a first heap memory allocated to the first configuration includes multiple first allocated memory blocks and corresponding first memory blocks metadata. The method also includes performing a warm reset, the reset including determining, based on the first memory blocks metadata, that when updating from the first configuration to the second configuration, data of at least one of the first allocated memory blocks should be persisted to a second heap memory allocated to the second configuration, and causing the device to update from the first configuration to the second configuration, where the update includes persisting, based on the first memory blocks metadata, the data of at least one of the first allocated memory blocks to a second heap memory allocated to the second configuration.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A system and related method for loading firmware on a device including processing circuitry and immutable storage memory, where the processing circuitry causes a device startup to be initiated based on startup code stored in the immutable storage memory. While the device startup is being initiated, the processing circuitry is to receive a first signal and determine that a second signal was not received within a minimum wait time following the receipt of the first signal. Once the processing circuitry has determined that the second signal was not received within the minimum wait time following the receipt of the first signal, the processing circuitry is to load the firmware on the device. A controller may be used when loading firmware on one or more devices of a plurality of devices. The first signal and the second signal may be a first interrupt signal and a second interrupt signal, respectively.

Classes IPC  ?

• G06F 9/48 - Lancement de programmes Commutation de programmes, p. ex. par interruption
• G06F 9/4401 - Amorçage
• G06F 8/65 - Mises à jour
• G06F 8/61 - Installation
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

A system and related method for loading firmware on a device including processing circuitry and immutable storage memory, where the processing circuitry causes a device startup to be initiated based on startup code stored in the immutable storage memory. While the device startup is being initiated, the processing circuitry is to receive a first signal and determine that a second signal was not received within a minimum wait time following the receipt of the first signal. Once the processing circuitry has determined that the second signal was not received within the minimum wait time following the receipt of the first signal, the processing circuitry is to load the firmware on the device. A controller may be used when loading firmware on one or more devices of a plurality of devices. The first signal and the second signal may be a first interrupt signal and a second interrupt signal, respectively.

Classes IPC  ?

• G06F 8/654 - Mises à jour utilisant des techniques spécialement adaptées aux mémoires de masse réinscriptibles, p. ex. aux mémoires EEPROM ou flash
• G06F 9/4401 - Amorçage

Abrégé

In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Produits et services

Downloadable computer software for managing solid state drives; downloadable computer software for updating solid state drives; downloadable computer software for optimizing solid state drive systems; downloadable computer software for controlling solid state drives; downloadable computer software for solid state drives; downloadable computer software for use with solid state drives (SSDs); downloadable computer software for use in electronic storage of data; downloadable computer software for enhancing solid-state drive performance; downloadable computer software for computer storage acceleration; downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; downloadable computer software for supporting computer storage acceleration and performance; downloadable computer software for optimizing and accelerating high-capacity storage on computers; downloadable computer software for facilitating adoption of new storage technologies; downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; downloadable computer software for generating machine learning models; downloadable computer software for reviewing data and images and identifying irregularities; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI); downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI). Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives. Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; providing online non-downloadable electronic publications in the nature of blogs, white papers and reports in the field of data storage and solid state drives via a website; education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives. Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; product failure analysis services; engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; quality management services, namely, quality evaluation and analysis, quality assurance and quality control, in the field of solid state drive (SSDs) devices; technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; technological consultation in the technology field of data storage, artificial intelligence, and computing technology.

Abrégé

A method and memory system for calculating checksums in a controller inside a memory device. This method and system select a subset matrix derived from an error correction code (ECC) parity-check matrix used in the controller and perform a partial checksum calculation using the subset matrix to estimate bit error rate (BER).

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11

Abrégé

Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
• G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
• G11C 16/04 - Mémoires mortes programmables effaçables programmables électriquement utilisant des transistors à seuil variable, p. ex. FAMOS
• G11C 16/26 - Circuits de détection ou de lectureCircuits de sortie de données
• H03M 13/45 - Décodage discret, c.-à-d. utilisant l'information de fiabilité des symboles

Abrégé

An embodiment of an electronic apparatus may comprise one or more substrates and a controller coupled to the one or more substrates, the controller including circuitry to identify failed memory regions in a memory by a rank, bank, and device associated with the failed memory region, and provide recovery for failed memory regions in three or more banks of a first rank of the memory or three or more devices of the first rank of the memory by virtual lock step device data correction with one or more other ranks of the memory. Other embodiments are disclosed and claimed.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 11/07 - Réaction à l'apparition d'un défaut, p. ex. tolérance de certains défauts

Abrégé

This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

Disclosed herein are IC structures, packages, and devices that include recesses processed via selective growth. An example integrated circuit (IC) structure, includes a first dielectric material, a second dielectric material on the first dielectric material, and a recess in the second dielectric material, wherein the recess includes a bottom, a top, and sidewalls. The IC further includes a first material within the recess and at a bottom of the recess, wherein the first material includes a metal and oxygen, a self-assembled monolayer (SAM) material, or an organic material, and a second material within the recess and between the first material and the top of the recess, wherein the second material is in contact with the sidewalls of the recess.

Classes IPC  ?

• H01L 23/532 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées caractérisées par les matériaux
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/31 - Encapsulations, p. ex. couches d’encapsulation, revêtements caractérisées par leur disposition
• H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
• H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.

Classes IPC  ?

• G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to compressing a logical-to-physical address indirection table in a memory system of an electronic device. The electronic device identifies an address block including a plurality of physical addresses that corresponds to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device further determines that a first physical address is associated with a first word having a first word location in the address block, and extracts the first word from the first word location in the address block. Based on the first word location, the electronic device determines a first bit location in a supplemental word that is distinct from the first word. The electronic device extracts at least a first bit from the first bit location of the supplemental word, and generates the first physical address based on the first word and the first bit.

Classes IPC  ?

• G06F 12/1045 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB] associée à une mémoire cache de données
• G06F 12/02 - Adressage ou affectationRéadressage

Produits et services

Downloadable computer software for managing solid state drives; downloadable computer software for updating solid state drives; downloadable computer software for optimizing solid state drive systems; downloadable computer software for controlling solid state drives; downloadable computer software for solid state drives; downloadable computer software for use with solid state drives (SSDs); downloadable computer software for use in electronic storage of data; downloadable computer software for enhancing solid-state drive performance; downloadable computer software for supporting computer storage acceleration and performance; downloadable computer software for optimizing and accelerating high-capacity storage on computers; downloadable computer software for facilitating adoption of new storage technologies; downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; downloadable computer software for generating machine learning models; downloadable computer software for reviewing data and images and identifying irregularities; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI); downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI); downloadable computer software for computer storage acceleration; downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance. Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives. Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; providing online non-downloadable electronic publications in the nature of blogs, white papers and reports in the field of data storage and solid state drives via a website; education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives. Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid-state drive (SSDs) devices; product failure analysis services; technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; technological consultation in the technology field of data storage, artificial intelligence, and computing technology.

Abrégé

A device and related method, the device including system memory for storing at least two queue groups, each of which includes commands, and processing circuitry. For each respective queue group, the processing circuitry determines an allocated command value indicative of a number of commands that are capable of being fetched from the respective queue group, determines a number of outstanding commands to be fetched from the respective queue group, and compares the allocated command value to the number of outstanding commands to be fetched for the respective queue group. When the allocated command value is greater than the number of outstanding commands to be fetched for the respective queue group, the processing circuitry designates the respective queue group as an available queue group. The processing circuitry then selects a queue group from the designated available queue groups and fetches at least one command from the selected queue group.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device and related method, the device communicatively coupled to a host, and the device including arbitration circuitry, command fetch circuitry, and processing circuitry. For each virtual machine of the host, arbitration circuitry determines (a) first credits value indicative of a number of commands that may be fetched and (b) a second credits value indicative of a bandwidth to fetch at least one command, from a queue group associated with the virtual machine. The arbitration circuitry selects a virtual machine based on at least one of the first credits values and the second credits values of the virtual machines, and communicates a signal to command fetch circuitry to fetch at least one command. In response to the reception of the signal, the command fetch circuitry fetches at least one command from the queue group associated with the selected virtual machine and communicates the fetched commands to processing circuitry for execution.

Classes IPC  ?

• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

Abrégé

This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a first variable node that corresponds to a data bit in a block of data, and obtains check node data from each of the set of check nodes. Each check node is associated with a set of respective variable nodes including the first variable node, and the check node data identifies at least a respective target node providing the smallest variable node data among the respective variable nodes. The electronic device identifies a subset of check nodes for each of which the check node data identifies the first variable node as the respective target node, determines that the subset of check nodes includes a first number of check nodes, and determines variable node data of the first variable node based on the first number.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Produits et services

Downloadable computer software for managing solid state drives; downloadable computer software for updating solid state drives; downloadable computer software for optimizing solid state drive systems; downloadable computer software for controlling solid state drives; downloadable computer software for solid state drives; downloadable computer software for use with solid state drives (SSDs); downloadable computer software for use in electronic storage of data; downloadable computer software for enhancing solid-state drive performance; downloadable computer software for computer storage acceleration; downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; downloadable computer software for supporting computer storage acceleration and performance; downloadable computer software for optimizing and accelerating high-capacity storage on computers; downloadable computer software for facilitating adoption of new storage technologies; downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; downloadable computer software for generating machine learning models; downloadable computer software for reviewing data and images and identifying irregularities; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI); downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI). Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives. Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; providing online non-downloadable electronic publications in the nature of blogs, white papers and reports in the field of data storage and solid state drives via a website; education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives. Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; product failure analysis services; engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid-state drive (SSDs) devices; technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; technological consultation in the technology field of data storage, artificial intelligence, and computing technology.

Abrégé

A device and related method, the device communicatively coupled to a host, and the device including arbitration circuitry, command fetch circuitry, and processing circuitry. For each virtual machine of the host, arbitration circuitry determines (a) first credits value indicative of a number of commands that may be fetched and (b) a second credits value indicative of a bandwidth to fetch at least one command, from a queue group associated with the virtual machine. The arbitration circuitry selects a virtual machine based on at least one of the first credits values and the second credits values of the virtual machines, and communicates a signal to command fetch circuitry to fetch at least one command. In response to the reception of the signal, the command fetch circuitry fetches at least one command from the queue group associated with the selected virtual machine and communicates the fetched commands to processing circuitry for execution.

Classes IPC  ?

• G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation

Abrégé

This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An apparatus may comprise a skew detection circuit to sample a common mode voltage of a differential signal, wherein the sampled common mode voltage is indicative of an amount of skew between a first signal of the differential signal and a second signal of the differential signal; and a skew compensation circuit to adjust a delay of the first signal or the second signal based on the sampled common mode voltage to reduce the amount of skew.

Classes IPC  ?

• G01R 31/317 - Tests de circuits numériques
• H04L 25/02 - Systèmes à bande de base Détails

Abrégé

This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a first variable node that corresponds to a data bit in a block of data, and obtains check node data from each of the set of check nodes. Each check node is associated with a set of respective variable nodes including the first variable node, and the check node data identifies at least a respective target node providing the smallest variable node data among the respective variable nodes. The electronic device identifies a subset of check nodes for each of which the check node data identifies the first variable node as the respective target node, determines that the subset of check nodes includes a first number of check nodes, and determines variable node data of the first variable node based on the first number.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

Mechanism include: storing first, second, and third entries in a cache; calculating an index value that corresponds to the entries; storing, in a first table location corresponding to the index value, first information identifying a first location of the first entry; storing, in a second table location corresponding to the index value, second information identifying a second location of the second entry; storing, in a linked-list corresponding to the index value, third information identifying a third location of the third entry; in response to a request to access the third entry, comparing the request to each of at least part of the first information, at least part of the second information, and at least part of the third information; determining that the request corresponds to the at least part of the third information; and retrieving data responsive to the request based on the third information.

Classes IPC  ?

• G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation
• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 12/0817 - Protocoles de cohérence de mémoire cache à l’aide de méthodes de répertoire

Abrégé

A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device's logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

Abrégé

Mechanisms for improving read command processing times in a solid-state drive (SSD) are provided, the mechanisms comprising: determining a workload type of an SSD; in response to determining that the workload type is a pure read workload type: determining at least one command size into which an original background write is to be split-up using at least one hardware processor; and splitting-up the background write into a plurality of split background writes, each having one of the determined at least one command size. In some embodiments, the at least one command size accounts for a page of the physical medium of the SSD. In some embodiments, the at least one command size includes at least two different sizes. In some embodiments, the mechanisms further comprise combining two or more split background writes. In some embodiments, the original background write is split-up before being placed in a channel queue.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA's entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device and related method, the device including system memory for storing at least two queue groups, each of which includes commands, and processing circuitry. For each respective queue group, the processing circuitry determines an allocated command value indicative of a number of commands that are capable of being fetched from the respective queue group, determines a number of outstanding commands to be fetched from the respective queue group, and compares the allocated command value to the number of outstanding commands to be fetched for the respective queue group. When the allocated command value is greater than the number of outstanding commands to be fetched for the respective queue group, the processing circuitry designates the respective queue group as an available queue group. The processing circuitry then selects a queue group from the designated available queue groups and fetches at least one command from the selected queue group.

Classes IPC  ?

• G06F 9/38 - Exécution simultanée d'instructions, p. ex. pipeline ou lecture en mémoire

Abrégé

A method and controller for operating a memory system in communication with a host. The method and controller logically arrange a sequence of reclaim sub-groups within a memory device. The method and controller process the reclaim sub-groups according to the sequence to control the memory device to perform garbage collection on the reclaim sub-groups in the memory device. In the sequence, the reclaim sub-groups are processed during the garbage collection such that at least one re-ordered data sequence in the sequence of the reclaim sub-groups being processed has re-ordered valid data that is not clumped.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An embodiment of an electronic apparatus may comprise one or more substrates, and circuitry coupled to the one or more substrates, the circuitry to track transactions that access a first memory level of a multi-level memory, control access to at least the first memory level of the multi-level memory, and control a roll back of at least the first memory level of the multi-level memory based on the tracked transactions. In another embodiment, the circuitry is to control a roll back of a multi-level memory in response to a request to roll back the multi-level memory. Other embodiments are disclosed and claimed.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 12/0891 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache utilisant des moyens d’effacement, d’invalidation ou de réinitialisation

Abrégé

Examples described herein relate to a switch, when operational, that is configured to receive in a packet an indicator of number of remaining bytes in a flow and to selectively send a congestion message based on a fullness level of a buffer and indication of remainder of the flow. In some examples, the indicator is received in an Internet Protocol version 4 consistent Options header field or Internet Protocol version 6 consistent Flow label field. In some examples, the congestion message comprises one or more of: an Explicit Congestion Control Notification (ECN), priority-based flow control (PFC), and/or in-band telemetry (INT). In some examples, to selectively send a congestion message to a transmitter based on a fullness level of a buffer that stored the packet and the number of remaining bytes in flow, the switch is to determine whether the buffer is large enough to store the remaining bytes in the flow.

Classes IPC  ?

• H04L 47/127 - Prévention de la congestionRécupération de la congestion en utilisant la prévision de congestion
• H04L 47/122 - Prévention de la congestionRécupération de la congestion en détournant le trafic des entités congestionnées
• H04L 47/2441 - Trafic caractérisé par des attributs spécifiques, p. ex. la priorité ou QoS en s'appuyant sur la classification des flux, p. ex. en utilisant des services intégrés [IntServ]
• H04L 47/30 - Commande de fluxCommande de la congestion en combinaison avec des informations sur l'occupation de mémoires tampon à chaque extrémité ou aux nœuds de transit

Produits et services

(1) Downloadable computer software for managing solid state drives; downloadable computer software for updating solid state drives; downloadable computer software for optimizing solid state drive systems; downloadable computer software for controlling solid state drives; downloadable computer software for solid state drives; downloadable computer software for use with solid state drives (SSDs); downloadable computer software for use in electronic storage of data; downloadable computer software for enhancing solid-state drive performance; downloadable computer software for computer storage acceleration; downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; downloadable computer software for supporting computer storage acceleration and performance; downloadable computer software for optimizing and accelerating high-capacity storage on computers; downloadable computer software for facilitating adoption of new storage technologies; downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; downloadable computer software for generating machine learning models; downloadable computer software for reviewing data and images and identifying irregularities; downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI); downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI). (1) Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives. (2) Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; providing online non-downloadable electronic publications in the nature of blogs, white papers and reports in the field of data storage and solid state drives via a website; education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives. (3) Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; product failure analysis services; engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; quality management services, namely, quality evaluation and analysis, quality assurance and quality control, in the field of solid state drive (SSDs) devices; technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; technological consultation in the technology field of data storage, artificial intelligence, and computing technology.

Produits et services

Downloadable computer software for use with solid state drives (SSDs); downloadable computer software for use in electronic storage of data; downloadable computer software for enhancing solid-state drive performance; downloadable computer software for computer storage acceleration downloadable software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; downloadable computer software for supporting computer storage acceleration and performance; downloadable computer software for optimizing and accelerating high-capacity storage on computers; downloadable computer software for facilitating adoption of new storage technologies; downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance. Technical support services, namely, troubleshooting of computer software problems.

Abrégé

Provided are devices and methods relating to temperature control in a solid state drive (SSD). One embodiment include a SSD including a housing including a plurality of sides surrounding an interior region. The SSD includes at least one vent on the housing, the at least one vent configured to be opened and closed in response to a signal. The SSD also includes a tempera and a controller, the controller configured to send a signal to open the at least one vent when a temperature sensed inside the interior region reaches a first temperature, and the controller configured to close the at least one vent when a temperature sensed inside the interior region reaches a second temperature, wherein the first temperature is greater than the second temperature. Other embodiments are described and claimed.

Classes IPC  ?

• G06F 1/20 - Moyens de refroidissement
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G11C 7/04 - Dispositions pour écrire une information ou pour lire une information dans une mémoire numérique avec des moyens d'éviter les effets perturbateurs thermiques

Produits et services

(Based on Use) Electronic components in the nature of semiconductor dies and interconnects; Structured semi-conductor wafers; Electronic chips for the manufacture of integrated circuits; Silicon wafers; Wafers for integrated circuits; Downloadable computer software for managing solid state drives; Downloadable computer software for updating solid state drives; Downloadable computer software for optimizing solid state drive systems; Downloadable computer software for controlling solid state drives; Downloadable computer software for solid state drives; Downloadable computer software for use with solid state drives (SSDs); Downloadable computer software for use in electronic storage of data; Downloadable computer software for enhancing solid-state drive performance; Downloadable computer software for computer storage acceleration; Downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; Downloadable computer software for supporting computer storage acceleration and performance; Downloadable computer software for optimizing and accelerating high-capacity storage on computers; Downloadable computer software for facilitating adoption of new storage technologies; Downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; Downloadable computer software for generating machine learning models; Downloadable computer software for reviewing data and images and identifying irregularities; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); Downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI) (Based on Intent to Use) Downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); Downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI) Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; Providing a website featuring resources, namely, non-downloadable publications in the nature of blogs, white papers, and reports in the field of data storage and solid state drives; Education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; Product failure analysis services; Engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; Quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid-state drive (SSDs) devices; Technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; Technological consultation in the technology field of data storage, artificial intelligence, and computing technology

Produits et services

(Based on Use) Downloadable computer software for managing solid state drives; Downloadable computer software for updating solid state drives; Downloadable computer software for optimizing solid state drive systems; Downloadable computer software for controlling solid state drives; Downloadable computer software for solid state drives; Downloadable computer software for use with solid state drives (SSDs); Downloadable computer software for use in electronic storage of data; Downloadable computer software for enhancing solid-state drive performance; Downloadable computer software for computer storage acceleration; Downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; Downloadable computer software for supporting computer storage acceleration and performance; Downloadable computer software for optimizing and accelerating high-capacity storage on computers; Downloadable computer software for facilitating adoption of new storage technologies; Downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; Downloadable computer software for generating machine learning models; Downloadable computer software for reviewing data and images and identifying irregularities; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); Downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI) (Based on Intent to Use) Downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); Downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI) Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; Providing a website featuring resources, namely, non-downloadable publications in the nature of blogs, white papers, and reports in the field of data storage and solid state drives; Education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; Product failure analysis services; Engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; Quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid-state drive (SSDs) devices; Technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; Technological consultation in the technology field of data storage, artificial intelligence, and computing technology

Produits et services

(Based on Use) Downloadable computer software for managing solid state drives; Downloadable computer software for updating solid state drives; Downloadable computer software for optimizing solid state drive systems; Downloadable computer software for controlling solid state drives; Downloadable computer software for solid state drives; Downloadable computer software for use with solid state drives (SSDs); Downloadable computer software for use in electronic storage of data; Downloadable computer software for enhancing solid-state drive performance; Downloadable computer software for supporting computer storage acceleration and performance; Downloadable computer software for optimizing and accelerating high-capacity storage on computers; Downloadable computer software for facilitating adoption of new storage technologies; Downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; Downloadable computer software for generating machine learning models; Downloadable computer software for reviewing data and images and identifying irregularities; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); Downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI); Downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); Downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI) (Based on Intent to Use) Downloadable computer software for computer storage acceleration; Downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; Providing a website featuring resources, namely, non-downloadable publications in the nature of blogs, white papers, and reports in the field of data storage and solid state drives; Education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; Engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; Quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid-state drive (SSDs) devices; Product failure analysis services; Technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; Technological consultation in the technology field of data storage, artificial intelligence, and computing technology

Produits et services

(Based on Use) Downloadable computer software for managing solid state drives; Downloadable computer software for updating solid state drives; Downloadable computer software for optimizing solid state drive systems; Downloadable computer software for controlling solid state drives; Downloadable computer software for solid state drives; Downloadable computer software for use with solid state drives (SSDs); Downloadable computer software for use in electronic storage of data; Downloadable computer software for enhancing solid-state drive performance; Downloadable computer software for computer storage acceleration; Downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; Downloadable computer software for supporting computer storage acceleration and performance; Downloadable computer software for optimizing and accelerating high-capacity storage on computers; Downloadable computer software for facilitating adoption of new storage technologies; Downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, and storing data and images; Downloadable computer software for generating machine learning models; Downloadable computer software for reviewing data and images and identifying irregularities; Downloadable computer software for analyzing, identifying, categorizing, labeling, sorting, managing, storing, and reviewing data and images, identifying irregularities, and machine learning using artificial intelligence (AI); Downloadable computer software for identifying defects and anomalies in manufacturing, production and distribution using artificial intelligence (AI) (Based on Intent to Use) Downloadable computer software for medical diagnostics and assessments using artificial intelligence (AI); Downloadable computer software for detecting anomalies in energy transmission using artificial intelligence (AI) Providing on-line forums for transmission of messages among computer users concerning data storage and solid state drives Educational services, namely, conducting conferences, seminars, and presentations in the field of data storage and solid state drives; Providing a website featuring resources, namely, non-downloadable publications in the nature of blogs, white papers, and reports in the field of data storage and solid state drives; Education services, namely, providing non-downloadable webinars in the field of data storage and solid state drives Providing temporary use of on-line non-downloadable software and applications for estimating and comparing solid state drive product life; Product failure analysis services; Engineering services, namely, engineering for the testing of new products for others in the nature of reliability testing, product assurance testing, failure analysis testing, and product qualification testing, all relating to data storage systems and solid state drives; Quality management services, namely, quality evaluation and analysis, quality assurance, and quality control, in the field of solid state drive (SSDs) devices; Technological planning and consulting services in the field of data storage, artificial intelligence, and computing technology; Technological consultation in the technology field of data storage, artificial intelligence, and computing technology

Abrégé

A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.

Classes IPC  ?

• G11C 16/28 - Circuits de détection ou de lectureCircuits de sortie de données utilisant des cellules de détection différentielle ou des cellules de référence, p. ex. des cellules factices
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots
• G11C 16/30 - Circuits d'alimentation

Abrégé

This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.

Classes IPC  ?

• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

Abrégé

Mechanisms for prioritizing read commands over write commands to a storage device are provided, the mechanisms comprising: determining counts of read commands targeting a plurality of portions of the storage device; calculating a threshold based on a function of an average of the counts of read commands targeting the plurality of portions of the storage device; determining that a count of read command(s) targeting one of the plurality of portions of the storage device meets the threshold; and in response to determining that the count of read command(s) targeting the one of the plurality of portions of the storage device meets the threshold, prioritizing a read command to access the one of the plurality of portions of the storage device over at least one write command.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A die, an integrated circuit (IC) device including two or more stacked dies, and a process of forming a die are provided. The die includes a circuit, a passivation layer arranged above the circuit and includes a top side and a bottom side, and a polyimide layer disposed on the top side of the passivation layer. The top side of the passivation layer includes portions of different respective heights extending vertically away from the circuit. A top side of the polyimide layer opposite the top side of the passivation layer includes portions of different respective heights extending vertically away from the circuit such that the surface area of the top side of the polyimide layer is increased compared to a planar top side.

Classes IPC  ?

• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 25/10 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs ayant des conteneurs séparés

Abrégé

Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

This application is directed to managing garbage collection using a plurality of queues of memory bands of a memory system. The memory system obtains a request to organize data stored in a plurality of memory bands of the memory system, and each memory band has a data validity level. In response to the request, the memory system generates the plurality of queues of memory bands based on the data validity levels of the plurality of memory bands, and the plurality of queues correspond to a plurality of non-overlapping validity level ranges. The plurality of memory bands are assigned into a subset of queues based on the data validity levels of the plurality of memory bands. The memory system 200 allocates a first memory bandwidth among the subset of queues, and implements garbage collection operations on the subset of queues in parallel using respective portions of the first memory bandwidth.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to dynamic power management among multiple memory devices of an electronic system. A plurality of memory devices are coupled into a ring of memory devices, and passes a power data packet along a power control path that tracks the ring of memory devices continuously. During a current cycle, a first memory device receives the power data packet from an upstream memory device on the power control path, and the power data packet includes at least a system power level indicating total power consumption of the plurality of memory devices. The first memory device sets a current power level of the first memory device based on the received power data packet, updates the power data packet based on the current power level, and sends the updated power data packet to a downstream memory device on the power control path.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation
• G11C 5/14 - Dispositions pour l'alimentation
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device and related method, the device including memory, communications circuitry, and processing circuitry. The processing circuitry allocates processing bandwidth of the device to process the received instructions and executes the instructions based on the allocated processing bandwidth using a first amount of free memory. If the used first amount of free memory is at least a first threshold, processing circuitry reduces the allocated processing bandwidth to process the received instructions based on the used first amount of free memory and continues to execute the instructions based on the reduced allocated processing bandwidth using a second amount of free memory of the device. If the used second amount of free memory is at least a second threshold, processing circuitry further reduces the allocated processing bandwidth to process the received instructions based on the used second amount of free memory, and allocates processing bandwidth to perform garbage collection of the memory.

Classes IPC  ?

• G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]

Abrégé

This application is directed to managing memory operations in a memory system or device (e.g., a solid-state drive (SSD)). While implementing one or more write operations on one or more active memory dies, the memory device identifies a first read request for data stored on a first memory die. The first read request is waiting next in a queue of read requests. In accordance with a determination (1) that the first memory die is distinct from the one or more active memory dies and (2) that no sufficient power is available to implement the first read request concurrently with the one or more write operations, the memory device suspends the one or more write operations according to a suspension scheme and implements the first read operation on the first memory die.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to monitoring a package of an electronic device (e.g., a memory device including a solid state drive (SSD)). The electronic device includes a package substrate, a package, and an interface circuit. The package substrate includes one or more connectors. The package includes a plurality of electrodes that are exposed on a top surface of the package and electrically coupled to the one or more connectors. The interface circuit is coupled to the one or more connectors of the package substrate, and configured to measure one or more electrical signals via the one or more connectors of the package substrate and determine one or more interface parameters of the top surface of the package based on the one or more electrical signals. The package is physically coupled to the package substrate and configured to enclose and protect an integrated circuit (e.g., including the interface circuit).

Classes IPC  ?

• H01L 23/367 - Refroidissement facilité par la forme du dispositif
• H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
• H01L 23/373 - Refroidissement facilité par l'emploi de matériaux particuliers pour le dispositif
• H01L 23/498 - Connexions électriques sur des substrats isolants
• H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe

Abrégé

A device and related method, the device including memory, communications circuitry, and processing circuitry. The processing circuitry allocates processing bandwidth of the device to process the received instructions and executes the instructions based on the allocated processing bandwidth using a first amount of free memory. If the used first amount of free memory is at least a first threshold, processing circuitry reduces the allocated processing bandwidth to process the received instructions based on the used first amount of free memory and continues to execute the instructions based on the reduced allocated processing bandwidth using a second amount of free memory of the device. If the used second amount of free memory is at least a second threshold, processing circuitry further reduces the allocated processing bandwidth to process the received instructions based on the used second amount of free memory, and allocates processing bandwidth to perform garbage collection of the memory.

Classes IPC  ?

• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
• G06F 13/362 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus ou au système à bus communs avec commande d'accès centralisée

Abrégé

This application is directed to managing memory operations in a memory system or device (e.g., a solid-state drive (SSD)). While implementing one or more write operations on one or more active memory dies, the memory device identifies a first read request for data stored on a first memory die. The first read request is waiting next in a queue of read requests. In accordance with a determination (1) that the first memory die is distinct from the one or more active memory dies and (2) that no sufficient power is available to implement the first read request concurrently with the one or more write operations, the memory device suspends the one or more write operations according to a suspension scheme and implements the first read operation on the first memory die.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to managing errors on a memory device. The memory device includes non-volatile memory (NVM) storing data and dynamic random-access memory (DRAM) storing a logic-to-physical (L2P) table and a poison table. The memory device obtains a data access request to access a data item stored in the NVM, and the data access request includes a logical address of the data item. The memory device identifies, in the L2P table, a mapping entry corresponding to the logical address of the data item, and the mapping entry maps the logical address of the data item to a physical address of the data item within the NVM, and determines that the mapping entry has an uncorrectable error. In accordance with a determination that the mapping entry has the uncorrectable error, the memory device adds, in the poison table, an index identifying the mapping entry in the L2P table.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/06 - Adressage d'un bloc physique de transfert, p. ex. par adresse de base, adressage de modules, extension de l'espace d'adresse, spécialisation de mémoire
• G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page

Abrégé

This application is directed to data validation and refresh in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device, which includes a plurality of memory cells that store two consecutive data items and correspond to two nominal threshold voltages. In response to the inquiry, the memory device selects a first readout voltage and a second readout voltage between the two nominal threshold voltages, and applies the first readout voltage and the second readout voltage to read the plurality of memory cells and generate first readout data and second readout data, respectively. An error rate of the page is determined based on the first readout data and the second readout data, and in some embodiments, further used to determine whether an error correction process or a background data refresh need to be implemented on the page.

Classes IPC  ?

• G11C 29/52 - Protection du contenu des mémoiresDétection d'erreurs dans le contenu des mémoires
• G11C 11/406 - Organisation ou commande des cycles de rafraîchissement ou de régénération de la charge
• G11C 11/4096 - Circuits de commande ou de gestion d'entrée/sortie [E/S, I/O] de données, p. ex. circuits pour la lecture ou l'écriture, circuits d'attaque d'entrée/sortie ou commutateurs de lignes de bits

Abrégé

This application is directed to managing errors on a memory device. The memory device includes non-volatile memory (NVM) storing data and dynamic random-access memory (DRAM) storing a logic-to-physical (L2P) table and a poison table. The memory device obtains a data access request to access a data item stored in the NVM, and the data access request includes a logical address of the data item. The memory device identifies, in the L2P table, a mapping entry corresponding to the logical address of the data item, and the mapping entry maps the logical address of the data item to a physical address of the data item within the NVM, and determines that the mapping entry has an uncorrectable error. In accordance with a determination that the mapping entry has the uncorrectable error, the memory device adds, in the poison table, an index identifying the mapping entry in the L2P table.

Classes IPC  ?

• G06F 12/00 - Accès à, adressage ou affectation dans des systèmes ou des architectures de mémoires
• G06F 12/0873 - Mappage de mémoire de mémoire cache vers des dispositifs ou des parties de dispositifs de stockage
• G06F 12/14 - Protection contre l'utilisation non autorisée de mémoire

Abrégé

A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.

Classes IPC  ?

• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité
• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes

Abrégé

This application is directed to data validation and refresh in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device, which includes a plurality of memory cells that store two consecutive data items and correspond to two nominal threshold voltages. In response to the inquiry, the memory device selects a first readout voltage and a second readout voltage between the two nominal threshold voltages, and applies the first readout voltage and the second readout voltage to read the plurality of memory cells and generate first readout data and second readout data, respectively. An error rate of the page is determined based on the first readout data and the second readout data, and in some embodiments, further used to determine whether an error correction process or a background data refresh need to be implemented on the page.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to monitoring a package of an electronic device (e.g., a memory device including a solid state drive(SSD)). The electronic device includes a package substrate, a package, and an interface circuit. The package substrate includes one or more connectors. The package includes a plurality of electrodes that are exposed on a top surface of the package and electrically coupled to the one or more connectors. The interface circuit is coupled to the one or more connectors of the package substrate, and configured to measure one or more electrical signals via the one or more connectors of the package substrate and determine one or more interface parameters of the top surface of the package based on the one or more electrical signals. The package is physically coupled to the package substrate and configured to enclose and protect an integrated circuit (e.g., including the interface circuit).

Classes IPC  ?

• G01R 31/28 - Test de circuits électroniques, p. ex. à l'aide d'un traceur de signaux
• G01R 19/165 - Indication de ce qu'un courant ou une tension est, soit supérieur ou inférieur à une valeur prédéterminée, soit à l'intérieur ou à l'extérieur d'une plage de valeurs prédéterminée
• G01R 27/02 - Mesure de résistances, de réactances, d'impédances réelles ou complexes, ou autres caractéristiques bipolaires qui en dérivent, p. ex. constante de temps
• G08B 21/18 - Alarmes de situation

Abrégé

This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.

Classes IPC  ?

• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
• H03M 13/11 - Détection d'erreurs ou correction d'erreurs transmises par redondance dans la représentation des données, c.-à-d. mots de code contenant plus de chiffres que les mots source utilisant un codage par blocs, c.-à-d. un nombre prédéterminé de bits de contrôle ajouté à un nombre prédéterminé de bits d'information utilisant plusieurs bits de parité

Abrégé

Mechanisms for providing solid-state drives (SSDs) (such as NAND SSDs) with a dynamic system area are provided. In some embodiments, the mechanism includes: determining a memory die from a plurality of individual memory dies on which system-related data is stored in a reserved band from a plurality of bands; determining lifetime information associated with the memory die on which the system-related data is stored in the reserved band; in response to determining that the lifetime information associated with the memory die is greater than a threshold value, determining unused dies from the plurality of individual memory dies on which the reserved band does not contain the system-related data; selecting at least one unused die based on the determined unused dies; and storing the system-related data in the reserved band of the selected unused die.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device, non-transitory computer-readable medium and related method, the device including memory and a processing circuitry. Processing circuitry, which is communicatively coupled to the memory, receives a write request from a host, the write request including information indicative of system characteristics and a destination address at which to store data. Processing circuitry determines the system characteristics based on the information indicative of the system characteristics and determines whether any of the system characteristics match with mapped system characteristics of a data placement table, wherein each mapped system characteristic corresponds to a respective placement identification (ID). Processing circuitry determines a location in memory at which to store the data based on one or more placement IDs corresponding to matched mapped system characteristics of the data placement table and without regard to the destination address, and causes the data to be stored at the location.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A device, non-transitory computer-readable medium and related method, the device including memory and a processing circuitry. Processing circuitry, which is communicatively coupled to the memory, receives a write request from a host, the write request including information indicative of system characteristics and a destination address at which to store data. Processing circuitry determines the system characteristics based on the information indicative of the system characteristics and determines whether any of the system characteristics match with mapped system characteristics of a data placement table, wherein each mapped system characteristic corresponds to a respective placement identification (ID). Processing circuitry determines a location in memory at which to store the data based on one or more placement IDs corresponding to matched mapped system characteristics of the data placement table and without regard to the destination address, and causes the data to be stored at the location.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

Mechanisms for providing solid-state drives (SSDs) (such as HAND SSDs) with a dynamic system area are provided. In some embodiments, the mechanism includes: determining a memory die from a plurality of individual memory dies on which system-related data is stored in a reserved band from a plurality of bands; determining lifetime information associated with the memory die on which the system-related data is stored in the reserved band; in response to determining that the lifetime information associated with the memory die is greater than a threshold value, determining unused dies from the plurality of individual memory dies on which the reserved band does not contain the system-related data; selecting at least one unused die based on the determined unused dies; and storing the system-related data in the reserved band of the selected unused die.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a primary persistent storage with a first type of media and a nonvolatile memory buffer with a second type of media that is different from the first type of media, store metadata for incoming write data in the nonvolatile memory buffer, store other data for the incoming write data in the primary persistent storage, and provide both runtime and power-fail write atomicity for the incoming write data. Other embodiments are disclosed and claimed.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page

Abrégé

Mechanisms for recovering NVM devices from power loss including: identifying a first last valid written page (LVWP) of a first block of the NVM device; identifying a first first empty page (FEP) after the first LVWP of the first block; determining that no pages exist between the first LVWP and the first FEP using a hardware processor; and in response to determining that no pages exist between the first LVWP and the first FEP, indicating that the first block can be used. In some embodiments, the mechanisms further comprise: identifying a second LVWP of a second block of the NVM device; identifying a second FEP after the second LVWP of the second block; determining that pages exist between the second LVWP and the second FEP; and in response to determining that pages exist between the second LVWP and the second FEP, performing a recovery process on the second block.

Classes IPC  ?

• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots

Abrégé

A device and related method, the device including a port, memory circuitry, and processing circuitry which is coupled to the port and to the memory circuitry. The processing circuitry receives multiple commands through the port, wherein the multiple commands are from at least two hosts using an interposer and wherein each command of the multiple commands includes a respective memory address and a respective port identification (ID). The processing circuitry segments each of the received commands into multiple segments, each segment being of a predetermined transfer size. The processing circuitry also transmits each segment of each command to a respective data structure instantiation corresponding to the port ID of the respective received command and performs data transfer for each segment of the multiple segments by accessing the memory circuitry at each respective memory address associated with each segment.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

Mechanisms for recovering NVM devices from power loss including: identifying a first last valid written page (LVWP) of a first block of the NVM device; identifying a first first empty page (FEP) after the first LVWP of the first block; determining that no pages exist between the first LVWP and the first FEP using a hardware processor; and in response to determining that no pages exist between the first LVWP and the first FEP, indicating that the first block can be used. In some embodiments, the mechanisms further comprise: identifying a second LVWP of a second block of the NVM device; identifying a second FEP after the second LVWP of the second block; determining that pages exist between the second LVWP and the second FEP; and in response to determining that pages exist between the second LVWP and the second FEP, performing a recovery process on the second block.

Classes IPC  ?

• G11C 16/30 - Circuits d'alimentation
• G11C 5/14 - Dispositions pour l'alimentation
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 16/08 - Circuits d'adressageDécodeursCircuits de commande de lignes de mots

Abrégé

A device and related method, the device including a port, memory circuitry, and processing circuitry which is coupled to the port and to the memory circuitry. The processing circuitry receives multiple commands through the port, wherein the multiple commands are from at least two hosts using an interposer and wherein each command of the multiple commands includes a respective memory address and a respective port identification (ID). The processing circuitry segments each of the received commands into multiple segments, each segment being of a predetermined transfer size. The processing circuitry also transmits each segment of each command to a respective data structure instantiation corresponding to the port ID of the respective received command and performs data transfer for each segment of the multiple segments by accessing the memory circuitry at each respective memory address associated with each segment.

Classes IPC  ?

• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire

Abrégé

Mechanisms for unordered input/output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input/output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input/output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input/output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input/output direct memory access operation request is for a write operation.

Classes IPC  ?

• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 12/0808 - Systèmes de mémoire cache multi-utilisateurs, multiprocesseurs ou multitraitement avec moyen d'invalidation de mémoires cache

Abrégé

Mechanisms for unordered input/output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input/output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input/output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input/output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input/output direct memory access operation request is for a write operation.

Classes IPC  ?

• G06F 12/0831 - Protocoles de cohérence de mémoire cache à l’aide d’un schéma de bus, p. ex. avec moyen de contrôle ou de surveillance
• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

Systems and methods for eliminating garbage collection in solid-state drives (SSDs) of a data center are disclosed herein. A data placement block (DPB) size is determined. An SSD receives, from a host device, a write command specifying a virtual logical block address (LBA). The SSD identifies a DPB based on the virtual LBA of the write command. The SSD causes data associated with the write command to be written to an erasable unit of memory of the SSD based on the identified DPB, and causes an association between the erasable unit of memory of the SSD and the virtual LBA of the write command to be stored.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Produits et services

Downloadable computer software for use with solid state drives (SSDs), specifically software for enhancing solid-state drive performance; Downloadable computer software for use in electronic storage of data; Downloadable computer software for enhancing solid-state drive performance; Downloadable computer software for computer storage acceleration; downloadable computer software for pairing of most-used computer hard drive files with solid state drive (SSD) cache for increasing performance; Downloadable computer software for supporting computer storage acceleration and performance; Downloadable computer software for optimizing and accelerating high-capacity storage on computers; Downloadable computer software for facilitating adoption of new storage technologies; Downloadable computer software for caching data to a solid state drive (SSD) to accelerate computer performance Technical support services, namely, troubleshooting of computer software problems

Abrégé

In accordance with some embodiments of the present disclosure, a method is performed on a memory storage device for updating data stored in the memory storage device. The method includes writing a first stream data to a first portion of memory, wherein the first stream data includes a plurality of substreams, and writing first additional data to a second portion of memory, wherein the first additional data includes data indicative of an update of at least one substream of the first stream data and is no larger than a substream of the plurality of substreams of the first stream data. Concurrent with writing the first additional data, the method also includes writing second additional data to the second portion of memory, wherein the second additional data includes at least one of data indicative of an update of at least one substream of a second stream data, or non-stream data.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A system and related method, the system including control circuitry and memory with a first memory block of a first memory density and a second memory block of a second memory density which is greater than the first memory density. Control circuitry, which is communicatively coupled to the memory, is configured to determine to transfer data from the first memory block to the second memory block, generate parity data based on the data and cause to store the parity data at a parity address corresponding to an available portion of the first memory block. Control circuitry is further to cause to update a look-up table with the parity data address and cause to copy the data from the first memory block to the second memory block.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix. Processing circuitry then configures a transmitting device that receives and encodes transmission data the using the further modified first matrix and further modified second matrix, and transmits the encoded transmission data.

Classes IPC  ?

• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

In accordance with some embodiments of the present disclosure, a method is performed on a memory storage device for updating data stored in the memory storage device. The method includes writing a first stream data to a first portion of memory, wherein the first stream data includes a plurality of substreams, and writing first additional data to a second portion of memory, wherein the first additional data includes data indicative of an update of at least one substream of the first stream data and is no larger than a substream of the plurality of substreams of the first stream data. Concurrent with writing the first additional data, the method also includes writing second additional data to the second portion of memory, wherein the second additional data includes at least one of data indicative of an update of at least one substream of a second stream data, or non-stream data.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to reading data from a memory device by structured data filtering within the memory device. The memory device is coupled into a host device and includes a plurality of memory blocks. The memory device receives, from the host device, a read request for data in a data structure including a plurality of data records. The read request comprises a bitmap identifying a subset of data records in the plurality of data records. Based on the read request, the memory device reads data from the plurality of memory blocks. The read data is filtered based on the bitmap to generate filtered data. The memory device returns the filtered data to the host device in response to the read request.

Classes IPC  ?

• G06F 16/245 - Traitement des requêtes
• G06F 16/2455 - Exécution des requêtes
• G06F 16/2453 - Optimisation des requêtes
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

A system and related method, the system including control circuitry and memory with a first memory block of a first memory density and a second memory block of a second memory density which is greater than the first memory density. Control circuitry, which is communicatively coupled to the memory, is configured to determine to transfer data from the first memory block to the second memory block, generate parity data based on the data and cause to store the parity data at a parity address corresponding to an available portion of the first memory block. Control circuitry is further to cause to update a look-up table with the parity data address and cause to copy the data from the first memory block to the second memory block.

Classes IPC  ?

• G06F 11/10 - Détection ou correction d'erreur par introduction de redondance dans la représentation des données, p. ex. en utilisant des codes de contrôle en ajoutant des chiffres binaires ou des symboles particuliers aux données exprimées suivant un code, p. ex. contrôle de parité, exclusion des 9 ou des 11
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory -based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.

Classes IPC  ?

• G11C 11/56 - Mémoires numériques caractérisées par l'utilisation d'éléments d'emmagasinage électriques ou magnétiques particuliersÉléments d'emmagasinage correspondants utilisant des éléments d'emmagasinage comportant plus de deux états stables représentés par des échelons, p. ex. de tension, de courant, de phase, de fréquence
• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 12/0893 - Mémoires cache caractérisées par leur organisation ou leur structure

Abrégé

This application is directed to managing firmware control data stored in a memory device of an electronic device. The electronic device obtains a current data descriptor map (DDM) corresponding to a current version of a firmware program, and identifies, in the memory device, a prior DDM and a prior control data structure corresponding to a prior version of the firmware program. Each of the prior and current DDMs maps a plurality of data descriptors to a plurality of locations in a respective control data structure. The prior control data structure stores a plurality of prior control data items identified by a plurality of prior data descriptors. A current control data structure is automatically generated for the current version of the firmware program based on the prior control data structure, the current DDM, and the prior DDM, and stores a plurality of current control data items identified by the data descriptors.

Classes IPC  ?

• G06F 8/65 - Mises à jour
• G06F 8/71 - Gestion de versions Gestion de configuration

Abrégé

This application is directed to writing data in a memory device supporting multiple bits per cell by dynamically using a y-level cell (YLC) cache. The memory device is coupled into a host device, and includes a plurality of x-level cell (XLC) memory blocks, where x is greater than one and greater than y. The memory device identifies a write shaping status of the host device. Based on the write shaping status, the memory device determines that the host device performs write operations without a memory-based cache. In accordance with a determination that the host device performs write operations without the memory-based cache, a YLC cache is allocated in the memory device to act as the memory-based cache. In response to one or more write requests, the memory device stores data into the plurality of XLC memory blocks via the YLC cache.

Classes IPC  ?

• G06F 12/0802 - Adressage d’un niveau de mémoire dans lequel l’accès aux données ou aux blocs de données désirés nécessite des moyens d’adressage associatif, p. ex. mémoires cache

Abrégé

This application is directed to managing firmware control data stored in a memory device of an electronic device. The electronic device obtains a current data descriptor map (DDM) corresponding to a current version of a firmware program, and identifies, in the memory device, a prior DDM and a prior control data structure corresponding to a prior version of the firmware program. Each of the prior and current DDMs maps a plurality of data descriptors to a plurality of locations in a respective control data structure. The prior control data structure stores a plurality of prior control data items identified by a plurality of prior data descriptors. A current control data structure is automatically generated for the current version of the firmware program based on the prior control data structure, the current DDM, and the prior DDM, and stores a plurality of current control data items identified by the data descriptors.

Classes IPC  ?

• G06F 9/30 - Dispositions pour exécuter des instructions machines, p. ex. décodage d'instructions
• G06F 9/445 - Chargement ou démarrage de programme
• G06F 9/4401 - Amorçage
• G06F 8/654 - Mises à jour utilisant des techniques spécialement adaptées aux mémoires de masse réinscriptibles, p. ex. aux mémoires EEPROM ou flash
• G06F 8/71 - Gestion de versions Gestion de configuration

Abrégé

A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix. Processing circuitry then configures a transmitting device that receives and encodes transmission data the using the further modified first matrix and further modified second matrix, and transmits the encoded transmission data.

Classes IPC  ?

• H03M 13/00 - Codage, décodage ou conversion de code pour détecter ou corriger des erreursHypothèses de base sur la théorie du codageLimites de codageMéthodes d'évaluation de la probabilité d'erreurModèles de canauxSimulation ou test des codes
• H04L 1/00 - Dispositions pour détecter ou empêcher les erreurs dans l'information reçue

Abrégé

A memory system comprising a memory device including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of latches coupled to the bit lines, and configured to program input data stored in the latches into memory cells of a selected word line during a program operation, and output, as information data, at least one or more data among first data stored in the latches and second data stored in the memory cells of the selected word line during a program suspend operation for suspending the program operation, and a controller configured to repair the input data by performing a set logic operation on the information data from the memory device, and apply the set logic operation whose type is different according to an execution moment of the program suspend operation.

Classes IPC  ?

• G11C 29/44 - Indication ou identification d'erreurs, p. ex. pour la réparation

Abrégé

This application is directed to controlling data timing in a memory system. The memory system includes a controller, a memory module, and an input data bus coupled between the memory controller and the memory module. The memory system transmits a data signal and a strobe signal via the input data bus from the memory controller to the memory module, and the data signal includes a train of serial input data. The memory system determines a skew time of the data signal with respect to the strobe signal, and generates a skew signal including a train of serial skew data based on the skew time of the data signal. The skew signal is transmitted from the memory module to the memory controller via a dedicated sideband bus that is distinct from the input data bus.

Classes IPC  ?

• G11C 16/32 - Circuits de synchronisation
• G11C 7/22 - Circuits de synchronisation ou d'horloge pour la lecture-écriture [R-W]Générateurs ou gestion de signaux de commande pour la lecture-écriture [R-W]
• G11C 16/10 - Circuits de programmation ou d'entrée de données
• G11C 7/10 - Dispositions d'interface d'entrée/sortie [E/S, I/O] de données, p. ex. circuits de commande E/S de données, mémoires tampon de données E/S
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement

Abrégé

This application is directed to controlling data timing in a memory system. The memory system includes a controller, a memory module, and an input data bus coupled between the memory controller and the memory module. The memory system transmits a data signal and a strobe signal via the input data bus from the memory controller to the memory module, and the data signal includes a train of serial input data. The memory system determines a skew time of the data signal with respect to the strobe signal, and generates a skew signal including a train of serial skew data based on the skew time of the data signal. The skew signal is transmitted from the memory module to the memory controller via a dedicated sideband bus that is distinct from the input data bus.

Classes IPC  ?

• G06F 13/16 - Gestion de demandes d'interconnexion ou de transfert pour l'accès au bus de mémoire
• G06F 1/10 - Répartition des signaux d'horloge
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation

Abrégé

A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

An enclosure, a related method for manufacturing thereof, and a device which includes thereof are disclosed herein. The enclosure includes a first outer surface and a second outer surface opposing the first outer surface. The enclosure further includes a heat sink arranged on the first outer surface, the heat sink including a plurality of protrusions extending outward from the first outer surface and a discernible component. The discernible component protrudes from the first outer surface and is recessed from the plurality of protrusions. The discernible component is distinguishable from the protrusions. The enclosure is to enclose circuitry between the first outer surface and the second outer surface, such that the circuitry is arranged closer to the second outer surface than to the first outer surface.

Classes IPC  ?

• H01L 23/42 - Choix ou disposition de matériaux de remplissage ou de pièces auxiliaires dans le conteneur pour faciliter le chauffage ou le refroidissement
• H01L 23/367 - Refroidissement facilité par la forme du dispositif
• H05K 1/02 - Circuits imprimés Détails

Abrégé

An enclosure, a related method for manufacturing thereof, and a device which includes thereof are disclosed herein. The enclosure includes a first outer surface and a second outer surface opposing the first outer surface. The enclosure further includes a heat sink arranged on the first outer surface, the heat sink including a plurality of protrusions extending outward from the first outer surface and a discernible component. The discernible component protrudes from the first outer surface and is recessed from the plurality of protrusions. The discernible component is distinguishable from the protrusions. The enclosure is to enclose circuitry between the first outer surface and the second outer surface, such that the circuitry is arranged closer to the second outer surface than to the first outer surface.

Classes IPC  ?

• H05K 7/20 - Modifications en vue de faciliter la réfrigération, l'aération ou le chauffage

Abrégé

Examples may include techniques to predict or determine time-to-ready (TTR) for a storage device. TTR may be predicted or determined based on operating information included in a snapshot associated with a first time interval during operation of the storage device. The TTR predicted or determined indicates an amount of time the storage device will be at an operational state following a power loss recover of the storage device.

Classes IPC  ?

• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06N 5/04 - Modèles d’inférence ou de raisonnement

Abrégé

This application is directed to dynamic power management among multiple memory devices of an electronic system. A plurality of memory devices are coupled into a ring of memory devices, and passes a power data packet along a power control path that tracks the ring of memory devices continuously. During a current cycle, a first memory device receives the power data packet from an upstream memory device on the power control path, and the power data packet includes at least a system power level indicating total power consumption of the plurality of memory devices. The first memory device sets a current power level of the first memory device based on the received power data packet, updates the power data packet based on the current power level, and sends the updated power data packet to a downstream memory device on the power control path.

Classes IPC  ?

• G06F 1/3225 - Surveillance de dispositifs périphériques de mémoires
• G06F 1/324 - Économie d’énergie caractérisée par l'action entreprise par réduction de la fréquence d’horloge

Abrégé

This application is directed to accessing data in a memory system of an electronic system. The memory system a storage-side DRAM and one or more memory channels. The memory system receives a memory access request for target data stored in the memory system, and the memory access request includes a target virtual address of the target data. In response to the memory access request, the memory system searches a page table of the storage-side dynamic random-access memory (DRAM) for a target physical address mapped to the target virtual address of the target data. The page table includes mappings between a plurality of virtual addresses and a plurality of physical addresses of the storage-side DRAM. Based on a search result, the memory system extracts the target data stored in one of the storage-side DRAM and the one or more memory channels according to the target physical address.

Classes IPC  ?

• G06F 12/1009 - Traduction d'adresses avec tables de pages, p. ex. structures de table de page
• G06F 12/02 - Adressage ou affectationRéadressage
• G06F 3/06 - Entrée numérique à partir de, ou sortie numérique vers des supports d'enregistrement
• G06F 13/42 - Protocole de transfert pour bus, p. ex. liaisonSynchronisation
• G06F 12/1027 - Traduction d'adresses utilisant des moyens de traduction d’adresse associatifs ou pseudo-associatifs, p. ex. un répertoire de pages actives [TLB]

Abrégé

This invention is directed to managing data storage in a memory system. The memory system receives a host request for an erase operation on a first erasable unit of a first memory block. In response to the host request, the memory system identifies an unused erasable unit of a second memory block in the memory system, remaps the first erasable unit of the first memory block to the unused erasable unit of the second memory block, and applies the erase operation on the unused erasable unit of the second memory block in place of the first erasable unit of the first memory block. In some embodiments, at a time of receiving the host request, the memory system further includes a space reserve of over-provisioning, and the second memory block is different from the space reserve. In some embodiments, the second memory block is moved offline to join the space reserve.

Classes IPC  ?

• G06F 12/02 - Adressage ou affectationRéadressage

Abrégé

This application is directed to dynamic power management among multiple memory devices of an electronic system. A plurality of memory devices are coupled into a ring of memory devices, and passes a power data packet along a power control path that tracks the ring of memory devices continuously. During a current cycle, a first memory device receives the power data packet from an upstream memory device on the power control path, and the power data packet includes at least a system power level indicating total power consumption of the plurality of memory devices. The first memory device sets a current power level of the first memory device based on the received power data packet, updates the power data packet based on the current power level, and sends the updated power data packet to a downstream memory device on the power control path.

Classes IPC  ?

• G06F 1/26 - Alimentation en énergie électrique, p. ex. régulation à cet effet
• G06F 1/32 - Moyens destinés à économiser de l'énergie
• G06F 1/3234 - Économie d’énergie caractérisée par l'action entreprise
• G06F 1/3296 - Économie d’énergie caractérisée par l'action entreprise par diminution de la tension d’alimentation ou de la tension de fonctionnement