An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and obtaining a plurality of test controls using a field of the instruction. The one or more test controls of the plurality of test controls are used to specify which digit positions of the source value are to be tested for validity and what codes are valid codes for the digit positions specified to be tested. Validity testing of at least a portion of the source value is performed based on the plurality of test controls obtained using the field of the instruction, and the performing the validity testing provides a result. The result is provided for use in further processing.
A conversion-type positive electrode and formation thereof. The conversion-type positive electrode includes a composite film and a porous inorganic layer formed on the top surface of the composite film, where the composite film includes an electrically conductive porous material and a conversion-type positive electrode active material, and where the porous inorganic layer does not undergo a reversible redox reaction during cycling of the conversion-type positive electrode.
H01M 4/58 - Emploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de composés inorganiques autres que les oxydes ou les hydroxydes, p. ex. sulfures, séléniures, tellurures, halogénures ou LiCoFyEmploi de substances spécifiées comme matériaux actifs, masses actives, liquides actifs de structures polyanioniques, p. ex. phosphates, silicates ou borates
H01M 4/02 - Électrodes composées d'un ou comprenant un matériau actif
3.
VECTOR TEST ZONED INSTRUCTION FOR VALIDITY TESTING
An instruction to perform validity testing of a source value is executed. The executing the instruction includes obtaining the source value using at least one field of the instruction and performing validity testing of at least a portion of the source value. The performing the validity testing is based on one or more test controls obtained using a field of the instruction. The performing the validity testing determines whether a format of the at least the portion of the source value adheres to a data format variation specified by, at least, the one or more test controls. The performing the validity testing provides a result, and the result is provided for use in further processing.
A set of data keys arranged in a particular order is obtained. The set of data keys includes multiple data keys. The multiple data keys include a protected key. The protected key is prevented from being in a selected position within the particular order. The set of data keys is encrypted as a single encrypted key. The single encrypted key is an encryption of the multiple data keys. The single encrypted key is returned. The single encrypted key is to be decrypted to obtain multiple decrypted keys. At least one decrypted key of the multiple decrypted keys is a decrypted protected key to be used in encryption of a confidential value.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
A device comprises a superconducting parametric interferometric circuit, which comprises a signal input port and a signal output port, and a first parametric mixing circuit and a second parametric mixing circuit coupled in parallel between the signal input port and the signal output port. The signal input port configured to receive an input signal having a first frequency. The first parametric mixing circuit is configured to convert the input signal to a first output signal having a second frequency, and the second parametric mixing circuit is configured to convert the input signal to a second output signal having the second frequency. The superconducting parametric interferometric circuit is configured to constructively combine the first and second output signals at the signal output port to generate an output signal having the second frequency, and provide isolation of the signal input port from a signal which is present at the signal output port.
The embodiments herein describe techniques for implementing enhanced boot processing of an embedded compute complex including a plurality of cores. Disclosed embodiments enable isolating the plurality of cores of the embedded compute complex from other components of a computing system when the cores are released from reset at the beginning of the boot initialization sequence, and enable a hierarchical boot process for booting the plurality of cores of the embedded compute complex.
A multi-chip module with a reduced number of routing layers. The multi-chip module, such as a quad-chip module, includes identical integrated circuits arranged in a coplanar manner, where the identical integrated circuits are rotated by either 0, 90 or 180 degrees with respect to each other. Furthermore, the multi-chip module includes pinwheel-shaped connections between diagonally positioned integrated circuits. Pinwheel-shaped connections refer to arc- shaped connections in the form of a pinwheel, such as similar to the lightweight vanes that revolve at the end of the stick of the pinwheel. For example, a transmitter macro in one of the identical integrated circuits is connected to a receiver macro in a diagonally located integrated circuit in the multi-chip module using such a pinwheel-shaped connection. By utilizing such pinwheel-shaped connections, which may be routed under the dies, the crossing of the diagonal connections is eliminated and the number of wiring layers is reduced.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 23/50 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes pour des dispositifs à circuit intégré
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
A release mechanism is provided to connect to a cable connector, with the cable connector being latchable to a connector receptacle. The release mechanism includes a pull release to operatively couple to a latching mechanism of the cable connector to selectively release a latch of the latching mechanism from latching the cable connector to the connector receptacle when operatively coupled to the connector receptacle. The pull release is adapted to, at least in part, break apart in operation in response to a predetermined excess stress event on the pull release to facilitate protecting the cable connector from excessive stress due to the stress event.
H01R 13/633 - Moyens additionnels pour faciliter l'engagement ou la séparation des pièces de couplage, p. ex. moyens pour aligner ou guider, leviers, pression de gaz pour la séparation uniquement
A system is provided which includes a first carriage assembly (630) to support a first cable connector (611) of a cable (610), and a second carriage assembly (640) to support a second cable connector (612) of the cable (610). The first and second carriage assemblies move along a guide (620). Further, the system includes a controller (602) to monitor and adjust position of at least the second carriage assembly (640) to maintain tension on the cable (610) within a specified range during an automated cabling operation of the system.
H01R 43/26 - Appareils ou procédés spécialement adaptés à la fabrication, l'assemblage, l'entretien ou la réparation de connecteurs de lignes ou de collecteurs de courant ou pour relier les conducteurs électriques pour engager ou séparer les deux pièces d'un dispositif de couplage
1INOUTiii) adding dispersion, configured to cause suppression of one or more sideband frequency components. The circuit may be a Josephson traveling- wave parametric amplifier (JTWPA), particularly for amplifying a readout signal of a quantum bit.
H03F 19/00 - Amplificateurs utilisant les effets de supraconductivité
H03D 7/00 - Transfert de modulation d'une porteuse à une autre, p. ex. changement de fréquence
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
11.
NEAR MEMORY PROCESSING DEVICE FOR PROCESSING COEFFICIENT ELEMENTS RESULTING FROM DECOMPOSITION OF POLYNOMIALS
Provided are a near memory device, system, and method for processing coefficient elements resulting from decomposition of polynomials. The near memory device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. A tile includes a memory and a processing element to perform operations on decomposed coefficients stored in the memory of the tile. An enclave controller in an enclave of the enclaves receives an operation for coefficients of a polynomial. Each of the coefficients are decomposed into a number of levels of coefficient elements. The enclave controller distributes the coefficient elements to the tiles in the enclave to have processing elements of the tiles load and process the coefficient elements and store the processed results.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/72 - Méthodes ou dispositions pour effectuer des calculs en utilisant une représentation numérique non codée, c.-à-d. une représentation de nombres sans baseDispositifs de calcul utilisant une combinaison de représentations de nombres codées et non codées utilisant l'arithmétique des résidus
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
12.
NEAR MEMORY PROCESSING DEVICE FOR PROCESSING HIEARCHICAL COMMANDS TO PROCESS COEFFICIENT ELEMENTS RESULTING FROM DECOMPOSITION OF POLYNOMIALS
Provided are a device, system, and computer program product for a near memory processing device to process coefficient elements resulting from decomposition of polynomials. A near memory processing device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. Coefficients of a polynomial are decomposed into a number of levels of the coefficient elements. Each level of coefficient elements comprises a limb. A device control receives hierarchical commands, from an application, that map operations to perform on limbs of coefficient elements to the enclaves and that map operations for the enclaves to the tiles in the enclaves. The device controller distributes operations for the tiles in the hierarchical commands to perform on the coefficient elements to the enclaves to distribute operations to perform on the coefficient elements to the tiles.
G06F 7/544 - Méthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs n'établissant pas de contact, p. ex. tube, dispositif à l'état solideMéthodes ou dispositions pour effectuer des calculs en utilisant exclusivement une représentation numérique codée, p. ex. en utilisant une représentation binaire, ternaire, décimale utilisant des dispositifs non spécifiés pour l'évaluation de fonctions par calcul
G06F 7/72 - Méthodes ou dispositions pour effectuer des calculs en utilisant une représentation numérique non codée, c.-à-d. une représentation de nombres sans baseDispositifs de calcul utilisant une combinaison de représentations de nombres codées et non codées utilisant l'arithmétique des résidus
H04L 9/00 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité
13.
COMPILING AN APPLICATION HAVING POLYNOMIAL OPERATIONS TO PRODUCE DIRECTED ACYCLIC GRAPHS HAVING COMMANDS TO EXECUTE IN A NEAR MEMORY PROCESSING DEVICE
Provided are a computer program product, system, and method for compiling an application having polynomial operations to produce directed acyclic graphs having commands to execute in a near memory processing device. An application is compiled including operations on a polynomial having coefficients, decomposed into a number of levels of coefficient elements, to generate hierarchical directed acyclic graphs (DAGs) having nodes indicating commands for execution by a hierarchy of hardware components in a near memory processing (NMP) device. The hierarchy of hardware components includes a plurality of enclaves of tiles. Each tile includes memory and a processing element to perform operations on the decomposed coefficients stored in the memory of the tile. Each of the hardware components includes a controller to process the commands in the DAG generated for the hardware components. The DAGs are provided to a hierarchical DAG tracker to generate commands for the NMP device.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 15/80 - Architectures de calculateurs universels à programmes enregistrés comprenant un ensemble d'unités de traitement à commande commune, p. ex. plusieurs processeurs de données à instruction unique
14.
SELF-CONSISTENT RECOVERY OF CONFIGURATIONS FROM NOISY CONCENTRATED WAVE FUNCTIONS APPLIED TO QUANTUM SELECTED CONFIGURATION INTERACTION
The various embodiments pertain to extracting one or more noiseless configurations from a collection of noisy configurations generated by a quantum processor. A configuration can be represented as a series of bits, 1's and 0's, whereby 1 indicates a spin orbital is occupied and 0 indicates spin orbital is empty. Noise in the quantum system can cause a respective bit to be flipped from a 0 to a 1, and vice-versa. During removal of the noise effect(s), bits can be flipped from their current value to an alternate value (e.g., 0 → 1, 1 → 0). After bit flipping, a Hamiltonian diagonalization process can be applied to the noiseless configuration to generate an eigenstate from which a ground state of the system represented by the noisy configuration can be determined. The system can be an atom or molecule, with the bits relating to a spin orbital of an electron.
Disclosed herein is a computer implemented method of deployment and resource allocation of microservices of a distributed computing environment. The distributed computing environment comprises a microservice deployment scheduler and one or more computing nodes. The microservice deployment scheduler comprises a reinforcement learning based dynamic workload orchestration module. The method comprises receiving microservice constraints descriptive of a microservice computing task by the microservice deployment scheduler. The method further comprises receiving node specific properties from the one or more computing nodes by the microservice deployment scheduler. The node specific properties are descriptive of a computing capacity and/or computing capabilities of the one or more computing nodes. The method further comprises orchestrating operation of the one or more computing nodes by the microservice deployment scheduler by inputting the microservice constraints and the node specific properties into the reinforcement learning based dynamic workload orchestration module.
A method, system, and computer program product for empirically identifying a dynamical decoupling sequence for error suppression on a quantum computer. A training quantum circuit, with an equivalent circuit structure to the target quantum circuit, is selected to identify the optimal dynamical decoupling sequence. A population of dynamical decoupling sequences represented as sequences in a genetic algorithm is generated. Offsprings of a selected set of sequences ("parents") from the population are then generated via reproduction and mutation forming candidate dynamical decoupling sequences, which refer to those dynamical decoupling sequences that may be selected to be used as a "parent" in a subsequent iteration for generating offsprings or selected as the dynamical decoupling sequence to run on the target quantum circuit. One or more dynamical decoupling sequences are selected from the candidate dynamical decoupling sequences based on their fitness with the objective function.
G06N 3/126 - Algorithmes évolutionnaires, p. ex. algorithmes génétiques ou programmation génétique
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
Disclosed herein is a computer implemented method of computer implemented method of log compression. The method comprises receiving a log stream from an instance of an application executed within a container of a remote computational system via a network connection. The log stream comprises metadata. The metadata comprises an application identifier. The application identifier uniquely identifies the executable code of the application. The method further comprises searching a compression dictionary library for a current compression dictionary using the application identifier. The application identifier uniquely identifies the current compression dictionary for the application. The method further comprises sending the current compression dictionary to the remote computational system via the network connection.
Techniques are provided for hybrid bonding metallic bonding pads embedded in high- K dielectric material to form a high capacitance device. For example, a device comprises a first semiconductor structure bonded to a second semiconductor structure, and a plurality of metal pads at an interface portion between the first semiconductor structure and the second semiconductor structure. The plurality of metal pads are disposed in a high-K dielectric layer. The plurality of metal pads and the high-K dielectric layer comprise at least one capacitor.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 23/00 - Détails de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/00 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide
19.
ELECTROFORMED ENERGY-EFFICIENT PHASE CHANGE MEMORY DEVICE WITH THIN ACTIVE REGION
A memory structure (300) and corresponding method of making and operating that includes: a first electrode (115); a first phase change material (PCM) layer (130) comprising a first PCM positioned above the first electrode; a second PCM layer (150) comprising a second PCM located above the first PCM layer, wherein the second PCM is compositionally different than the first PCM and has at least one of: a higher crystallization temperature than the first PCM, a longer crystallization time than the first PCM, and/or more easily forms a void than the first PCM; a barrier layer (140) positioned in between the first PCM layer and the second PCM layer to inhibit intermixing of the first PCM and the second PCM layer; and a second electrode (170) positioned above the second PCM layer. The PCM memory structure can further include an insulating and/or resistive region (265) formed above the barrier layer in the second PCM layer.
H10N 70/00 - Dispositifs à l’état solide n’ayant pas de barrières de potentiel, spécialement adaptés au redressement, à l'amplification, à la production d'oscillations ou à la commutation
H10N 70/20 - Dispositifs de commutation multistables, p. ex. memristors
20.
MODULAR PACKAGE STRUCTURES WITH INTERPOSERS HAVING ALIGNMENT FEATURES
A package structure comprises a first interposer, a second interposer, and a quantum chip. The first interposer comprises a first alignment feature. The second interposer comprises a second alignment feature. The quantum chip is bonded to the first interposer with an extended portion of the first quantum chip extending past a first edge of the first interposer. The first interposer and the second interposer are disposed with the first alignment feature engaging with the second alignment feature to cause alignment and coupling of one or more components on the extended portion of the first quantum chip with one or more components on the second interposer.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H01L 23/544 - Marques appliquées sur le dispositif semi-conducteur, p. ex. marques de repérage, schémas de test
21.
NEUROMORPHIC DEVICES OF HEUSLER ALLOY BASED SPIN-TRANSFER-TORQUE MAGNETIC TUNNEL JUNCTIONS
SAMSUNG ELECTRONICS CO., LTD. (République de Corée)
IBM DEUTSCHLAND GMBH (Allemagne)
Inventeur(s)
Yang, See-Hun
Garg, Chirag
Filippou, Panagiotis
Jeong, Jaewoo
Samant, Mahesh
Abrégé
A neuromorphic computing array includes horizontal lines and vertical lines that intersect the horizontal lines at cell locations. Magnetic tunnel junction cells are located at the cell locations. Each cell is electrically connected to a corresponding one of the horizontal lines and to a corresponding one of the vertical lines. Each cell includes a substrate (1401), a seed layer (1403) overlying the substrate, and a nitride layer (1403A) overlying the seed layer, and optionally having a thickness greater than 5 Angstroms. Each cell further includes a templating layer (1403B) outward of the nitride layer, including a binary alloy having an alternating layer lattice structure, and having a thickness greater than 50 Angstroms. Each cell still further includes a first magnetic layer (1405) overlying the templating layer, a tunnel barrier (1409) outward of the first magnetic layer; and a second magnetic layer (1411) outward of the tunnel barrier. The first magnetic layer (1405) includes a Heusler compound and exhibits perpendicular magnetic anisotropy, PMA.
Deploying a neural network to a new edge server in an edge computing environment includes deploying a plurality of copies of a centralized neural network respectively to a corresponding plurality of edge servers, wherein each of the copies of the centralized neural network is independently operated and trained at a respective one of the edge servers based on inputs received at that edge server to create independently trained neural networks. Each of the edge servers stores edge devices information including a physical location of each edge device that accessed the independently trained neural network operating at the edge server. A new edge neural network is generated for deployment to the new edge server, including performing neural network breeding based on the independently trained neural networks and the stored edge devices information, and based on anticipated edge devices information for edge devices expected to access the new edge server.
An electrical device that includes thermal cooling through silicon vias (TSVs) and micro-channels embedded in the carrier wafer for back side power distribution networks (BSPDN). The carrier wafer is at one end of a stacked structure providing the electrical device. At least one active device layer in the stacked structure that is present a level of the electrical device that is separate from a level containing the thermal cooling through silicon vias (TSVs) and micro-channels.
H01L 23/367 - Refroidissement facilité par la forme du dispositif
H01L 23/44 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température le dispositif complet étant totalement immergé dans un fluide autre que l'air
H01L 23/473 - Dispositions pour le refroidissement, le chauffage, la ventilation ou la compensation de la température impliquant le transfert de chaleur par des fluides en circulation par une circulation de liquides
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
24.
IDENTIFICATION AND CORRECTION OF ANOMALOUS SENSOR BEHAVIOR USING CALIBRATION HARMONIZATION
Sensor calibration harmonization includes generating, over a time epoch, a time series of uncalibrated sensor measurements produced by a plurality of sensors. The time epoch is a dynamically variable span of time during which enough uncalibrated sensor measurements are collected to enable estimation of calibration gains and offsets for the plurality of sensors during the time epoch. The calibration gains and offsets are determined based on calibration harmonization of the uncalibrated sensor measurements. The calibration harmonization generates a linear transformation that determines the offsets by projecting a selected set of uncalibrated gains onto a linear subspace, and determines the calibrated gains based on the offsets. The plurality of sensors may be reconfigured in response to determining which sensors generate measurements that when calibrated based on calibration harmonization lie within an acceptable range.
G01D 18/00 - Test ou étalonnage des appareils ou des dispositions prévus dans les groupes
G01D 3/08 - Dispositions pour la mesure prévues pour les objets particuliers indiqués dans les sous-groupes du présent groupe avec dispositions pour protéger l'appareil, p. ex. contre les fonctionnements anormaux, contre les pannes
25.
CONTINUAL NEURAL NETWORK TRAINING IN AN EDGE COMPUTING ENVIRONMENT
Continual neural network training in an edge computing environment includes deploying a plurality of copies of a centralized neural network respectively to a corresponding plurality of edge servers, wherein each of the copies of the centralized neural network is independently operated and trained at a respective one of the edge servers based on inputs received at that edge server to create independently trained neural networks. At periodic intervals, copies of the independently trained neural networks and a corresponding fitness measure for each of the copies of the independently trained neural networks are sent from the plurality of edge servers to a cloud-based data center. The centralized neural network is updated at the cloud-based data center, including performing neural network breeding based on the copies of the independently trained neural networks sent from the plurality of edge servers.
A semiconductor device includes a gate metal and a gate extension disposed within a region between two transistors of opposite conductivity and connected to the gate metal. The gate extension extends toward a side of the semiconductor device having power rails. A gate cut is disposed within the gate metal and through the gate extension to cut the gate extension into portions that are electrically isolated from each other. Each of the portions of the gate extension is coupled to a backside power rail.
H10D 64/27 - Électrodes ne transportant pas le courant à redresser, à amplifier, à faire osciller ou à commuter, p. ex. grilles
H10D 84/83 - Dispositifs intégrés formés dans ou sur des substrats semi-conducteurs qui comprennent uniquement des couches semi-conductrices, p. ex. sur des plaquettes de Si ou sur des plaquettes de GaAs-sur-Si caractérisés par l'intégration d'au moins un composant couvert par les groupes ou , p. ex. l'intégration de transistors IGFET de composants à effet de champ uniquement de transistors FET à grille isolée [IGFET] uniquement
H10D 84/85 - Transistors IGFET complémentaires, p. ex. CMOS
An embodiment provisions a Validation Area within a consistency group of a primary site and a Validation Area within a consistency group of a secondary site. The embodiment provisions a Validation Writer in the primary site and provisions a Validation Reader in the secondary site; the Validation Writer writes a validation metric into the Validation Area in the primary site at an interval determined by a recovery point objective. The embodiment also reads the validation metric by the Validation Reader in the secondary site, computes a validation result based on the validation metric, the recovery point objective and a recovery point time delta where the validation result comprises an outcome of a replication of the primary site to the secondary site where the Validation Area of the primary site, the Validation Area of the secondary site, the Validation Writer and the Validation Reader are storage and application agnostic.
H04L 67/1095 - Réplication ou mise en miroir des données, p. ex. l’ordonnancement ou le transport pour la synchronisation des données entre les nœuds du réseau
H04L 69/40 - Dispositions, protocoles ou services de réseau indépendants de la charge utile de l'application et non couverts dans un des autres groupes de la présente sous-classe pour se remettre d'une défaillance d'une instance de protocole ou d'une entité, p. ex. protocoles de redondance de service, état de redondance de protocole ou redirection de service de protocole
According to an embodiment, a structure for a qubit architecture is presented. The structure may include a plurality of qubits. The structure may include a plurality of couplings between each qubits. The couplings are arranged based on a relationship between each qubit and its placement on a torus. The coupling for each qubit comprises coupling to four nearest neighbor qubits on the torus and coupling to two cross-coupled qubits based on a definition and a set of parameters of a bivariate bicycle code. Methods for using and manufacturing the qubit architecture are additionally presented.
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
29.
MODULAR AND SCALABLE QUANUTM COMPUTER WITH TRAPEZOIDAL UNIT CELLS
Systems and techniques that facilitate scalable cryostats and cryogenic systems are provided. In an embodiment, a cryogenic system (300) can comprise a plurality of unit cells (304) joined together, wherein each unit cell comprises: a trapezoidal-shaped frame (704), wherein frames from adjacent unit cells are connected in a vacuum-tight manner to form a continuous, global vacuum enclosure, and wherein the unit cells are capable of being horizontally removed from or inserted into the plurality of joined unit cells. Furthermore, each unit cell can comprise at least one temperature shell (508, 510, 512), wherein temperature shells from adjacent unit cells are connected to form a continuous, global temperature shell. Moreover, each unit cell can comprise at least one cryogenic payload (514) located within the at least one temperature shell, that is cooled by at least one retrofitted version of a standard dilution refrigerator.
A system includes a cable passing from a first plate to a second plate via an intermediate plate, an attachment coupling the cable to the intermediate plate, and a conductive cladding connected to an outer surface of the cable and extended a first length from the attachment toward the second plate. The total length of the thermally conductive cladding is larger than the total length of the attachment, and the cable is thermally connected to the first plate, the second plate, and the intermediate plate.
H01B 12/14 - Conducteurs, câbles ou lignes de transmission supraconducteurs ou hyperconducteurs caractérisés par la disposition de l'isolation thermique
F25B 9/10 - Machines, installations ou systèmes à compression dans lesquels le fluide frigorigène est l'air ou un autre gaz à point d'ébullition peu élevé avec plusieurs étages de refroidissement
F25D 19/00 - Disposition ou montage des groupes frigorifiques dans les dispositifs
H01B 12/16 - Conducteurs, câbles ou lignes de transmission supraconducteurs ou hyperconducteurs caractérisés par le refroidissement
31.
CREATING A UNIQUE FUNCTION IDENTIFIER USING DATAFLOW AND GRAPH EMBEDDING
An approach is provided for creating dataflow-based function signatures. Using intermediate representations of application binaries of respective applications, functions included in the application binaries are extracted. Respective dataflows are generated for the extracted functions. Respective dataflow graphs are generated for the dataflows. The dataflow graphs are converted into respective sets of embeddings. A knowledge base in a data repository is populated with the sets of embeddings. Using a first similarity function, a second similarity function, and the populated knowledge base, it is determined that an unlabeled application binary matches one of the application binaries.
Provided is a method, system, and computer program product for performing automated feature dimensionality reduction without accuracy loss. A processor may determine a first training value associated with a first dataset of a machine learning model. The processor may rank features of the first dataset in relation to the first training value. The processor may compare the ranked features of the first dataset to a predetermined threshold. The processor may generate a second dataset from the first dataset by removing a third dataset, the third dataset having a set of features that did not meet the predetermined threshold. The processor may determine a second training value associated with the second dataset. The processor may compare the first training value to the second training value. In response to the second training value being lower than the first training value, the processor may analyze the third dataset with a dimensionality reduction algorithm.
One or more systems, devices, computer program products and/or computer- implemented methods of use provided herein relate to buffers for streaming in quantum- centric supercomputing. A system can comprise a memory that can store computer- executable components. The system can further comprise a processor that can execute the computer-executable components stored in the memory, wherein the computer-executable components can comprise a receiver component that can receive, from a source node, a quantum input and a release criterion associated with the quantum input. The computer- executable components can further comprise a computation component that can perform a computation based on the quantum input, in a buffering environment, to generate a result that can meet the release criterion.
G06N 10/80 - Programmation quantique, p. ex. interfaces, langages ou boîtes à outils de développement logiciel pour la création ou la manipulation de programmes capables de fonctionner sur des ordinateurs quantiquesPlate-formes pour la simulation ou l’accès aux ordinateurs quantiques, p. ex. informatique quantique en nuage
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/20 - Modèles d’informatique quantique, p. ex. circuits quantiques ou ordinateurs quantiques universels
G06N 10/60 - Algorithmes quantiques, p. ex. fondés sur l'optimisation quantique ou les transformées quantiques de Fourier ou de Hadamard
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
34.
PERFORMING SELECT INPUT/OUTPUT REQUESTS WHILE IN PROTECTED MEMORY STATES
A computer-implemented method, according to one approach, includes: receiving an indication that memory has entered a protected state. Additionally, I/O requests intended for target locations in the memory are received. A determination is made as to whether the target locations are permitted to perform I/O requests while the memory is in the protected state. In response to determining one or more of the target locations are not permitted to perform I/O requests while the memory is in the protected state, the respective one or more of the received I/O requests are denied. However, in response to determining one or more of the target locations are permitted to perform I/O requests while the memory is in the protected state, the respective one or more of the received I/O requests are performed at the one or more target locations.
A method comprises forming a shadow evaporation mask (100) on a substrate (110), and utilizing the shadow evaporation mask to perform a double angle evaporation process to form a plurality of tunnel junction devices in each of the different regions of the substrate. The shadow evaporation mask comprises a plurality of patterned openings in different regions of the substrate, wherein each of the patterned openings comprises a same size and shaped opening. The tunnel junction devices each comprise a first metal layer and a second metal layer having an overlapping area, wherein the overlapping areas of the tunnel junction devices are invariant over the different regions of the substrate.
Obscured location verification may include: obtaining, by a computing device, location information associated with the computing device; generating, by the computing device, a hash of region data for each of a plurality of regions associated with the location information using a key associated with the computing device to produce a plurality of hashes; sending, by the computing device, the plurality of hashes to a server; and receiving, by the device from the server, authentication information from the server indicative of whether one or more of the plurality of regions is authenticated based upon a corresponding hash from the plurality of hashes.
A computer-implemented method, according to one approach, includes: receiving an indication that memory has entered a protected state. An I/O request that is intended for a target location in the memory is also received. Moreover, the relative significance of the I/O request is evaluated, and in response to concluding the I/O request is sufficiently significant, the I/O request is performed at the target location. However, in response to concluding the I/O request is insufficiently significant, the I/O request is denied.
Execution of an instruction includes obtaining software objects and loading instructions into a memory and storing the workload type attribute for each software object. The execution includes operations that during runtime, deploy a first hardware instruction to trigger a firmware process to sample, at each interval of timed pre-configured intervals, instructions from the sets of instructions of the one or more software objects being executed during the interval by one or more processors of the computing system. The operations include deploying a second hardware instruction to obtain and store samples from the firmware process in the memory. The operations include generating, based on analyzing the stored samples, execution parameters associated with each sample. The operations include determining accesses to the software libraries in the computing system, by workload type attribute. The operations automatically implement an action related to at least one software object in the computing system.
A method for reduced latency between software services operating in a service mesh, where the software services are instantiated when fulfilling requests is disclosed. The method comprises providing a plurality of services which fulfill a request, where communication between the services is based on support components, The method also comprises creating a directed dependency graph of the plurality of services by tracing request flows between the plurality of services, thereby nodes of the directed dependency graph represent services and edges of the directed dependency graph represent used communication paths between selected ones of the services, determining a dependent service for an incoming request to a selected one of the plurality of services based on the directed dependency graph, and starting an instance of the dependent service together with the selected one of the plurality of services.
A method for dependent task prioritization is disclosed. The method comprises providing base data comprising task identifiers, failure values and dependency data values, where each dependency data value is associated with a pair of tasks. The method comprises also generating a probabilistic model, using a directed acyclic graph, where each task is associated with a network node, and where each dependency data value is associated with a network edge of the directed acyclic graph, wherein each dependency data value is indicative of a conditional probability in relation to the respective failure rate per time unit. Additionally, the method comprises determining for each task in the acyclic directed graph a posterior marginal probability value indicative of a probability of a failure of the task, and selecting, based upon the posterior marginal probability values, a sequence of tasks that is likely to fail fastest.
The present disclosure relates to a method comprising determining by a specific first computer system of the first computer systems a need to fine-tune a first artificial intelligence model for performing a specific task; performing a federated learning for a set of trained second artificial intelligence models for generating a combined artificial intelligence model, the second artificial intelligence models being configured to perform the specific task, each second artificial intelligence model having a structure which is at least a substructure of the first artificial intelligence model; using learnable parameters of the combined artificial intelligence model for fine-tuning at the specific first computer system the first artificial intelligence model.
A method, in accordance with one aspect, includes writing, by a tape drive, data tracks to a data band of a magnetic tape having servo bands flanking the data band, the writing being performed using a magnetic head that is not designed for a format of the magnetic tape. The writing includes overwriting a portion of each of the servo bands with the data tracks. A method, in accordance with another aspect, includes writing data tracks to a data band using a magnetic head that is not designed for a format of the magnetic tape. An effective pitch of servo readers of the magnetic head used simultaneously during the writing matches a servo reader pitch specification of the format of the magnetic tape. An average effective pitch of write transducers of the magnetic head is greater than a data track pitch specification of the format of the magnetic tape.
G11B 5/584 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'une bande
G11B 5/008 - Enregistrement, reproduction ou effacement sur des bandes ou des fils magnétiques
43.
SYMMETRICAL MAGNETIC HEAD AND MAGNETIC MEDIA FOR USE WITH SUCH HEAD
An apparatus, in accordance with one aspect of the present invention, includes a magnetic head having an array of transducers, the transducers comprising data elements, at least two first servo readers positioned toward a first end of the array and at least two second servo readers positioned toward a second end of the array. The array is symmetrical about a centerpoint of the array, such that a distance between a center of an innermost one of the first servo readers and a center of the data element closest thereto is the same as a distance between a center of an innermost one of the second servo readers and a center of the data element closest thereto, and such that a distance between a center of an outermost one of the first servo readers and the center of the data element closest thereto is the same as a distance between a center of an outermost one of the second servo readers and the center of the data element closest thereto.
G11B 5/008 - Enregistrement, reproduction ou effacement sur des bandes ou des fils magnétiques
G11B 5/29 - Structure ou fabrication de dispositifs unitaires formés de plusieurs têtes pour plus d'une piste
G11B 5/48 - Disposition ou montage des têtes par rapport aux supports d'enregistrement
G11B 5/584 - Disposition ou montage des têtes par rapport aux supports d'enregistrement comportant des dispositions pour déplacer la tête dans le but de maintenir l'alignement relatif de la tête et du support d'enregistrement pendant l'opération de transduction, p. ex. pour compenser les irrégularités de surface ou pour suivre les pistes du support pour suivre les pistes d'une bande
Method and apparatus for regression testing. A first plurality of sequences of events is generated by executing a plurality of test paths on a first computing environment. A test workload is constructed based on the first plurality of sequences of events. A second plurality of sequences of events is generated by executing the test workload on a second computing environment. One or more variances are identified by comparing the first plurality of sequences of events with the second plurality of sequences of events. And the second computing environment is reconfigured based on the one or more variances.
Define a plurality of qubit collision types and a plurality of constraints. For a group of qubits, use a computerized mixed-integer programming solver to, subject to the constraints, iteratively minimize collisions by minimizing a sum of products of weights multiplied by an amount of frequency collisions for given ones of the constraints of each one of the collision types. Output a frequency tuning plan for the group of qubits, based on the iterative minimization. Facilitate tuning physical qubits in accordance with the frequency tuning plan.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
46.
FREQUENCY PLAN GENERATOR FOR MULTI-QUBIT PROCESSORS
With a computerized frequency plan generator, for each node in a quantum lattice: determine a list of possible frequencies subject to at least one of nearest neighbor and next nearest neighbor collision constraints; and assign a highest possible frequency; apply a collision cleaning routine to the quantum lattice with the assigned frequencies until at least one of a condition where there are no remaining collisions and a condition where collision count ceases to improve; and apply a frequency perturbation routine to the collision-cleaned quantum lattice to move apart at least one of a high-risk nearest neighbor collision and a high risk next nearest neighbor collision.
G06N 5/01 - Techniques de recherche dynamiqueHeuristiquesArbres dynamiquesSéparation et évaluation
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
47.
ENERGY CONSUMPTION AGGREGATION AND TRACKING PER DATA OBJECT BASED ON A BLOCKCHAIN TOKEN
An embodiment registers a node and a data object on a blockchain. The embodiment schedules by a Scheduler an object task associated with the data object in a Data Controller, generating a task execution token by the Data Controller on the blockchain where the task execution token is associated with the object task. The embodiment senses the task execution token by the node received from the Data Controller; responsive to the sensed task execution token executes the object task on the node and generating a node energy consumption metric and an energy consumption token of the object task on the blockchain. The embodiment also sends the energy consumption token to the Data Controller from the node causing a smart contract to compute a task energy consumption metric based on the node energy consumption metric where the data object on the blockchain is updated with the task energy consumption metric.
Embodiments herein describe techniques for a host to provide TX packets to a shared adapter that then uses a NIC to forward the TX packet to a network. In one embodiment, the host creates or fills in one or more TX storage block page entries (SBPE) for the TX packet and stores an index of the TX SBPE in host memory. The host memory can also store an initiative state that tracks whether the shared adapter is currently processing TX packets. If not, the host can issue an interrupt to the shared adapter, along with the index associated with the TX SBPE. The shared adapter can then fetch the TX SBPE from host memory and program the NIC to transmit the TX packet.
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
49.
ARTIFICIAL DATA GENERATION FOR DIFFERENTIAL PRIVACY
An embodiment configures a plurality of parameters, the parameters being usable to generate artificial data from original data, the configuring adjusting a level of privacy in the artificial data. An embodiment fits a distribution type to a variable of the original data. An embodiment adjusts, using a desired level of privacy and the distribution type, a level of noise, wherein the level of noise corresponds to the desired level of privacy. An embodiment generates, using the distribution type and the level of noise, the artificial data, the artificial data achieving the desired level of privacy by including noise data corresponding to the level of noise.
Techniques regarding modifying a forecasting model are provided. For example, one or more embodiments described herein can comprise a modeling system, which can comprise a memory that can store computer executable components. The modeling system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include an identifying component that can identify qualitative information related to a forecasting model of an operation of a system, wherein the forecasting model was generated through data obtained from the operation of the system. The computer executable components can include a modifying component that can modify the forecasting model based on intervention information generated based on the qualitative information, wherein the intervention information is associated with a prediction of the forecasting model.
G06Q 10/04 - Prévision ou optimisation spécialement adaptées à des fins administratives ou de gestion, p. ex. programmation linéaire ou "problème d’optimisation des stocks"
A method, computer program product, and computer system to control an exporting and importing of reactive power by nodes of a network. One node of the network (capable of exporting Q units of reactive power to the network) and N nodes of the network (each capable of importing reactive power from the network) are identified. Initially, Q > 0 or Q < 0. The N nodes are sorted in ascending order of relative distance between the one node and each of the N nodes. A loop over the sorted N nodes is performed. A next iteration of the loop includes: sending a first and second electromagnetic signal to the first node and a next node, directing the first node and the next node to export an amount Qʹ of reactive power and to import an amount of reactive power, respectively; and updating Q via Q = Q - Qʹ.
H02J 3/16 - Circuits pour réseaux principaux ou de distribution, à courant alternatif pour règler la tension dans des réseaux à courant alternatif par changement d'une caractéristique de la charge du réseau par réglage de puissance réactive
H02J 3/18 - Dispositions pour réglage, élimination ou compensation de puissance réactive dans les réseaux
The present disclosure relates to a method comprising: determining a current resource utilization status in a distributed system; inputting, to a second artificial intelligence model, the current resource utilization status and an in-use split configuration of a first artificial intelligence model, the second artificial intelligence model being configured for predicting a split configuration for the first artificial intelligence model; receiving an output from the second artificial intelligence, the output indicating a current split configuration for the first artificial intelligence model; splitting the first artificial intelligence model using the current split configuration; deploying the split first artificial intelligence model such that the input and output blocks may be executed on one or more first computer systems of the set of first computer systems and such that the intermediate block may be executed on a second computer system of the at least one second computer system; executing the workload.
G06F 9/50 - Allocation de ressources, p. ex. de l'unité centrale de traitement [UCT]
G06N 3/063 - Réalisation physique, c.-à-d. mise en œuvre matérielle de réseaux neuronaux, de neurones ou de parties de neurone utilisant des moyens électroniques
53.
HANDLING SURGE OF CURRENT DUE TO A SUDDEN INCREASE IN OPERATION LOAD
A computer-implemented method, system, and computer program product for handling a surge of current due to a sudden increase in operation load. A task is scheduled to be executed, where the task only includes a real load. Upon executing the task, it is determined if the amount of the current change ratio caused by the real load exceeds a threshold value within a period of time. If the amount of the current change ratio is predicted to exceed the threshold value within the period of time, a predicted rush current (surge of current) may be said to occur. In response to predicting a potential rush current, a dummy load is added in the high-power multi-voltage system or a dummy sink current is added to an output of the switching regulator of the power module in order to reduce the amount of the current change ratio.
A computer-implemented process for updating an electronic document includes the following operations. Using a preprocessor, preprocessing is performed on the electronic document to generate a computer data structure. The computer data structure is evaluated using a word sense disambiguation (WSD) engine and a deep neural network to determine a context of a sentence within the electronic document. Based upon the context, a determination is made that a word within the sentence is a word of interest. The sentence is rewritten using a mitigation engine and a large language model to generate a revised sentence that does not include the word of interest. A determination is made that the revised sentence does not include any other word of interest; and the electronic document is updated to include the revised sentence.
A processor set is configured to receive tabular data records and generate a plurality of clusters, associated with specific real-world entities, within the received tabular data records, wherein each cluster is associated with a specific real-world entity. The processor set may further identify informative features within a first cluster and mask a subset of the informative features. Based on the masked subset of informative features and using self-supervision techniques, the processor set may train a tabular foundation model.
A computer-implemented method for controlling a plurality of IT processes is disclosed. The method comprises measuring periodically start-times and related end-times of each of the plurality of IT processes during a first time interval, determining, for each of the IT processes, regularized binary time-series data based on the measured start-times and the related end-times, during a second time interval, building a plurality of vectors, wherein each component of each of the vectors of the plurality represents data of a respective one of the time-series data of the plurality of IT processes during a given second time interval, training of a machine-learning system to build a machine-learning model using the plurality of vectors as training data, thereby determining weights for edges between nodes of the machine-learning system, and using the determined weights of the edges between the nodes as indicators for dependencies between the IT processes.
Techniques are described with respect to a system, method, and computer program product for visualizing gaming virtual objects. An associated method includes analyzing a physical object within a physical space; rendering a virtual object associated with the physical object based on the analysis; optimizing the virtual object within a virtual environment associated with the physical space; and integrating the optimized virtual object into the virtual environment.
A63F 13/213 - Dispositions d'entrée pour les dispositifs de jeu vidéo caractérisées par leurs capteurs, leurs finalités ou leurs types comprenant des moyens de photo-détection, p. ex. des caméras, des photodiodes ou des cellules infrarouges
A63F 13/52 - Commande des signaux de sortie en fonction de la progression du jeu incluant des aspects de la scène de jeu affichée
A63F 13/65 - Création ou modification du contenu du jeu avant ou pendant l’exécution du programme de jeu, p. ex. au moyen d’outils spécialement adaptés au développement du jeu ou d’un éditeur de niveau intégré au jeu automatiquement par des dispositifs ou des serveurs de jeu, à partir de données provenant du monde réel, p. ex. les mesures en direct dans les compétitions de course réelles
A63F 13/67 - Création ou modification du contenu du jeu avant ou pendant l’exécution du programme de jeu, p. ex. au moyen d’outils spécialement adaptés au développement du jeu ou d’un éditeur de niveau intégré au jeu en s’adaptant à ou par apprentissage des actions de joueurs, p. ex. modification du niveau de compétences ou stockage de séquences de combats réussies en vue de leur réutilisation
58.
DYNAMIC ADAPTATION OF BACKUP POLICY SCHEMES BASED ON THREAT CONFIDENCE
Method and apparatus for data backup. A first backup of a computing system is generated at a first time. A first confidence of compromise level of the computing system for the first time is generated. The first backup is stored along with metadata, where the metadata comprises the first confidence of compromise level of the computing system at the first time. In response to evaluating the first confidence of compromise level based on one or more backup criteria, a backup policy of the computing system is modified.
G06F 21/55 - Détection d’intrusion locale ou mise en œuvre de contre-mesures
G06F 11/14 - Détection ou correction d'erreur dans les données par redondance dans les opérations, p. ex. en utilisant différentes séquences d'opérations aboutissant au même résultat
G06F 21/57 - Certification ou préservation de plates-formes informatiques fiables, p. ex. démarrages ou arrêts sécurisés, suivis de version, contrôles de logiciel système, mises à jour sécurisées ou évaluation de vulnérabilité
For a set in sets of candidate factors, a classification model is trained to predict a computer problem possibility, an accuracy score of the classification model is determined based on model validation, and factor weights of the candidate factors in the set are adjusted based on the accuracy score. This processing is done with respect to all sets of candidate factors. A low accuracy classification model having an accuracy score lower than a threshold criterion is selected. A higher accuracy classification model having an accuracy score that is higher than the accuracy score of the low accuracy classification model is selected. The set of candidate factors used to train the low accuracy classification model is updated using one or more of the candidate factors used to train the higher accuracy classification model. The low accuracy classification model is updated based on the updated set of candidate factors.
A transistor includes one or more tapered inner spacers. The tapered inner spacer may include a base region that extends or protrudes beyond a plane that is coplanar with a first sidewall of the gate. The base region(s) may reduce the gate length of the gate adjacent to the base region. When two base regions are associated with the same gate, the two base regions may merge and may be between and/or isolate the gate from the underlying substrate. The tapered inner spacers may result in reduced parasitic capacitances between gate and the substrate and/or between the gate and adjacent source/drain region(s), and/or may reduce current leakage from the gate into the substrate or other underlying structure.
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/165 - Corps semi-conducteurs caractérisés par les matériaux dont ils sont constitués comprenant, mis à part les matériaux de dopage ou autres impuretés, seulement des éléments du groupe IV de la classification périodique, sous forme non combinée comprenant plusieurs des éléments prévus en dans différentes régions semi-conductrices
H01L 29/78 - Transistors à effet de champ l'effet de champ étant produit par une porte isolée
A semiconductor device includes a top side and a bottom side opposite the top side. A central portion including a semiconductor substrate is disposed between the top side and the bottom side. A component is disposed in the central portion in contact with the semiconductor substrate. The component includes a first electrical connection from the top side and a second electrical connection from the bottom side.
H01L 23/522 - Dispositions pour conduire le courant électrique à l'intérieur du dispositif pendant son fonctionnement, d'un composant à un autre comprenant des interconnexions externes formées d'une structure multicouche de couches conductrices et isolantes inséparables du corps semi-conducteur sur lequel elles ont été déposées
H01L 21/8238 - Transistors à effet de champ complémentaires, p.ex. CMOS
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 21/822 - Fabrication ou traitement de dispositifs consistant en une pluralité de composants à l'état solide ou de circuits intégrés formés dans ou sur un substrat commun avec une division ultérieure du substrat en plusieurs dispositifs individuels pour produire des dispositifs, p.ex. des circuits intégrés, consistant chacun en une pluralité de composants le substrat étant un semi-conducteur, en utilisant une technologie au silicium
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
62.
ARTIFICIAL INTELLIGENCE SIMULATION OF OPERATING SYSTEMS AND COMMAND-LINE-INTERFACES FOR OPERATING SYSTEMS
Mechanisms are provided for simulating operating systems. The mechanisms train, for each operating system, a corresponding artificial intelligence (AI) computer model that learns, by way of machine learning training, patterns of input features of inputs to the operating system and corresponding responses from the operating system. A request to simulate a requested operating system is received along with a simulation input whose processing by the requested operating system is to be simulated. An AI computer model corresponding to the requested operating system is executed on the simulation input to simulate processing the simulation input to generate a simulated response. The simulated response is returned as a simulated output of the requested operating system responsive to the input.
G06F 9/451 - Dispositions d’exécution pour interfaces utilisateur
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
A computer-implemented method for improving entity matching in a probabilistic matching engine can train a graph neural network (GNN) model on an output of a probabilistic matching engine to perform entity matching and determine counterfactual explanations for non-matches of entities. A list of data transformations can be identified by actionable recourse using the GNN model. The list of data transformations can be ranked, using the GNN model, based on computational overhead and an estimated improvement in entity matching within the probabilistic matching engine.
An embodiment defines, by a site reliability engineering maturity engine, a plurality of tenets, a tenet in the plurality of tenets representing a principle of site reliability engineering. The embodiment generates, by the site reliability engineering maturity engine for the plurality of tenets, a first site reliability engineering maturity assessment for a first hybrid cloud component, a second site reliability engineering maturity assessment for a second hybrid cloud component, and a third site reliability engineering maturity assessment for an application. The embodiment determines, by the site reliability engineering maturity engine, a workload placement for the application based on the first, second, and third site reliability engineering maturity assessments. The embodiment initiates, by the site reliability engineering maturity engine, a workload migration for the application based on the workload placement.
An apparatus comprises optical apparatus, and electrical characterization apparatus. The optical apparatus and the electrical characterization apparatus comprise an integrated configuration to perform laser annealing operations for tuning junction resistances of superconducting tunnel junction devices on a quantum chip, and to perform in-situ resistance measurements to measure the junction resistances of the superconducting tunnel junction devices on the quantum chip.
In several aspects, a computing device analyzes data to determine its characteristics. The computing device selects at least one compression process based on the characteristics. A compression switch and a compression level are dynamically adjusted based on multiple factors including available system resources, desired storage savings and performance requirement. The compression level dynamically varies depending on the data being processed and a workload on a system. Performance of compression and decompression operations are continuously monitored for dynamically adjusting compression parameters to optimize performance.
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet
H03M 7/30 - CompressionExpansionÉlimination de données inutiles, p. ex. réduction de redondance
The present disclosure relates to a method comprising receiving a request to execute a workload using an artificial intelligence model. A current resource utilization status in the distributed system may be determined. The current resource utilization status may be used to define a deployment configuration of the artificial intelligence model, wherein the deployment configuration is defined by: a number and structure of input blocks, a number and structure of output blocks and the intermediate block of the artificial intelligence model, a second computer system to execute the intermediate block, and one or more first computer systems to execute the input and output blocks. The artificial intelligence model may be deployed in accordance with the defined deployment configuration and the workload may be executed.
Provided are a method, a system, a computer program product, an Application Specific Integrated Circuit, and a cryptographic module, where a partitioning is performed of a SHA-2 state update into three blocks. A set of operations associated with the three blocks are executed in a pipelined manner, where each block feeds back for computation into itself.
H04L 9/06 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité l'appareil de chiffrement utilisant des registres à décalage ou des mémoires pour le codage par blocs, p. ex. système DES
69.
PROCESSING OF UE APPLICATIONS IN A WIRELESS COMMUNICATION SYSTEM
The present disclosure relates to a method for prescheduling resources for user equipments in a wireless communication system. The method comprises: identifying a network-based client-server application and a user equipment, wherein the user equipment comprises a client side of the application. A usage profile may be determined for the user equipment, the usage profile of the user equipment indicating an activity pattern of the user equipment for the application. The usage profile may be used for predicting an upcoming activity of the user equipment with regard to the application. The upcoming activity may be used for prescheduling resources for the user equipment to enable the user equipment to use the application. A notification may be sent to the user equipment indicating the prescheduled resources.
H04W 72/52 - Critères d’affectation ou de planification des ressources sans fil sur la base des charges
H04W 72/543 - Critères d’affectation ou de planification des ressources sans fil sur la base de critères de qualité sur la base de la qualité demandée, p. ex. QdS [QoS]
70.
COORDINATION OF EDGE COMPUTING IN A MOBILE NETWORK
The invention relates to a method of coordinating edge computing in a mobile network by an MEC orchestrator, comprising: monitoring deployment metrics and controlling deployment parameters related to a deployment of software applications on edge nodes of the mobile network; receiving an optimization report from a network orchestrator of the mobile network; based on the optimization report, determining a current optimization efficiency of the mobile network; if the optimization efficiency fulfils an inefficiency criterion: determining deployment suggestions having assigned one or more of the deployment parameters and being indicative of an expected response of one or more of the deployment metrics to a suggested variation of the assigned deployment parameters; and transmitting the deployment suggestions to the network orchestrator; in response to receiving from the network orchestrator an indication of a selected deployment suggestion, applying the corresponding suggested variation.
H04L 41/0823 - Réglages de configuration caractérisés par les objectifs d’un changement de paramètres, p. ex. l’optimisation de la configuration pour améliorer la fiabilité
H04L 41/342 - Canaux de signalisation pour la communication dédiée à la gestion du réseau entre entités virtuelles, p. ex. orchestrateurs, SDN ou NFV
H04L 41/5025 - Pratiques de respect de l’accord du niveau de service en réagissant de manière proactive aux changements de qualité du service, p. ex. par reconfiguration après dégradation ou mise à niveau de la qualité du service
H04L 41/5009 - Détermination des paramètres de rendement du niveau de service ou violations des contrats de niveau de service, p. ex. violations du temps de réponse convenu ou du temps moyen entre l’échec [MTBF]
H04L 43/08 - Surveillance ou test en fonction de métriques spécifiques, p. ex. la qualité du service [QoS], la consommation d’énergie ou les paramètres environnementaux
A trace assist unit operable with a plurality of processor cores is described. The trace assist unit comprises a plurality of physical buffers, and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers. The loading circuitry receives trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories. The loading circuitry writes the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories. The loading circuitry transmits, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory.
According to an example of the present subject matter, a secured radio frequency identification device includes: a first radio frequency identification (RFID) tag; and a secured radio frequency identification (RFID) tag having a transmission control for selectively enabling and disabling data transmission from the secured RFID tag. The first RFID tag is to store non-sensitive data from a data set and the secured RFID tag is to store sensitive data from the same data set such that all the data of the data set is only accessible when the secured RFID tag is enabled for data transmission.
Disclosed herein is a computer implemented method of accessing a shared data set using a shared and an exclusive lock. The method comprises: initiating at least one reader thread configured to perform a read operation; recording a reader thread state for the at least one reader thread in a data structure; selectively acquiring the shared lock for the at least one reader thread; implementing processing of the at least one reader thread; selectively interrupting the processing of the at least one reader thread in response to an exclusive lock request; restoring the at least one reader thread state using the reader thread state recorded in the data structure and releasing the shared lock; acquiring an exclusive lock; resuming the processing of the at least one reader thread; reacquiring the shared lock for the at least one reader thread in response to determining a releasing of the exclusive lock.
A computer-implemented method, according to one approach, includes: detecting new data generated at a first edge node, and causing a first copy of the new data to be transferred to a central data storage location in real-time. A second copy of the new data is also stored in a first location at the first edge node. In response to a predetermined condition being met, a determination is made as to whether any information in the first copy of the new data transferred is missing at the central data storage location. The first copy of the new data is removed from the first location at the first edge node in response to determining that no information in the first copy of the new data transferred is missing at the central data storage location.
The present disclosure relates to a method for detecting information breach in a computer system. The method comprises: detecting a radio frequency signal in an area of the computer system. A set of samples of the radio frequency signal may be input to a machine learning model. An output of the machine learning model may be received. The output indicates whether the detected radio frequency signal is anomalous. An alarm signal may be generated in case the detected radio frequency signal is predicted as an anomalous signal.
A package structure includes a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.
H01L 25/065 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant tous d'un type prévu dans une seule des sous-classes , , , , ou , p. ex. ensembles de diodes redresseuses les dispositifs n'ayant pas de conteneurs séparés les dispositifs étant d'un type prévu dans le groupe
H01L 25/18 - Ensembles consistant en une pluralité de dispositifs à semi-conducteurs ou d'autres dispositifs à l'état solide les dispositifs étant de types prévus dans plusieurs différents groupes principaux de la même sous-classe , , , , ou
According to one embodiment, a method, computer system, and computer program product for performing data synchronization between a source DBMS, comprising a trusted database, and a target DBMS, comprising an untrusted datastore and a trusted datastore, is disclosed. The present invention may include upon the source DBMS performing an update to an object in the trusted source database, sending the object change to a trusted data replication engine, encrypting the object change, sending the encrypted object change with a related decryption key to the target DBMS, upon receiving the encrypted object change and the related decryption key at the target DBMS, searching an object related to the object change in the untrusted target data store, identifying a decryption key for the searched object, replacing the identified decryption key by the received decryption key, and integrating the encrypted object change in encrypted form into the untrusted target data store.
G06F 21/62 - Protection de l’accès à des données via une plate-forme, p. ex. par clés ou règles de contrôle de l’accès
G06F 16/27 - Réplication, distribution ou synchronisation de données entre bases de données ou dans un système de bases de données distribuéesArchitectures de systèmes de bases de données distribuées à cet effet
78.
CLIENT-SERVER RESPONSE TIME BASED COMPUTER SYSTEM GEOLOCATION
An embodiment sends, at a first time, from a boundary server to a client system in response to a challenge request, a challenge specifying a computational problem to be solved by the client system, the boundary server specified in a challenge list sent to the client system. An embodiment receives, at a second time, at the boundary server, a challenge response from the client system, the challenge response comprising a solution to the computational problem. An embodiment generates, at the boundary server, a certificate encoding an elapsed time between the first time and the second time, the certificate usable by the client system to prove a location of the client system. An embodiment sends, from the boundary server to the client system, the certificate.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
H04W 4/029 - Services de gestion ou de suivi basés sur la localisation
H04W 12/63 - Sécurité dépendant du contexte dépendant de la localisationSécurité dépendant du contexte dépendant de la proximité
H04W 64/00 - Localisation d'utilisateurs ou de terminaux pour la gestion du réseau, p. ex. gestion de la mobilité
79.
MULTIPOLE BANDPASS FILTER NETWORK BASED ISOLATOR DEVICES
A device comprises filter circuitry and non-linear mixing devices. The filter circuitry comprises a first port, a second port, a first bandpass filter, and a second bandpass filter. The non-linear mixing devices are responsive to control signals to couple poles of the first bandpass filter to respective poles of the second bandpass filter to cause non-reciprocal transmission of signals from the first port to the second port.
H03H 11/38 - Réseaux à transmission unidirectionnelle
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
H03H 7/01 - Réseaux à deux accès sélecteurs de fréquence
H03H 7/52 - Réseaux à transmission unidirectionnelle
A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source OS comprises a source ABI; the target OS comprises a target application ABI; the target ABI is different from the source application binary interface, wherein the library is implemented by a source object file; the source object file is compliant with the source application binary interface and comprising at least a source memory image, source symbol information, and source relocation information, where the source relocation information is free of relative relocation information. The method comprises also creating a target memory image compliant with the target application binary interface and derived from the source memory image, enriching the target memory image with a fixed-length eye-catcher information, and writing the target memory image to a target object file.
A semiconductor structure including a plurality of stacked devices having different gate dielectrics is provided. The different gate dielectrics for the stacked devices are designed to improve the performance and the reliability for each of the stacked devices.
H01L 27/06 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant une pluralité de composants individuels dans une configuration non répétitive
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/423 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative ne transportant pas le courant à redresser, à amplifier ou à commuter
H01L 27/092 - Transistors à effet de champ métal-isolant-semi-conducteur complémentaires
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A semiconductor structure including a first transistor comprising a first placeholder and a first gate pitch and a second transistor comprising a second placeholder and a second gate pitch, where the first gate pitch is less than the second gate pitch, and wherein the first placeholder is smaller than the second placeholder.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/06 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
A computer-implemented method for transforming a library from a source operating system to a target operating system is disclosed. Thereby, the source operating system comprises an ABI, the target operating system comprising a target ABI, the target ABI being different from the source ABI, the library being implemented by a source object file that is compliant with the source application binary interface and comprising a source memory image, source symbol and source relocation information. The method comprises also creating a target memory image, that is compliant with the target application binary interface, wherein the target memory is derived from the source memory image, enriching the target memory image with an address information pointing to a variable length information, and writing the target memory image to the target object file to implement the transformed library by the target object file.
An approach is provided for securing a secret for usage by an application utilizing a client to retrieve secrets. A request is sent from a client in a workload container within a trusted execution environment (TEE) to retrieve an encrypted secret from an application programming interface (API) server outside the TEE. The request is hooked and sent to the API server by a proxy or a secret proxy plugin within the TEE. The secret is received from the API server by the proxy or secret proxy plugin. An agent within the TEE is called to request a private key. The agent obtains the private key. The secret is decrypted by using the private key. The decrypted secret is returned to the client by the proxy or secret proxy plugin, which ensures that a plain text version of sensitive information in the decrypted secret is not accessible outside the TEE.
G06F 21/53 - Contrôle des utilisateurs, des programmes ou des dispositifs de préservation de l’intégrité des plates-formes, p. ex. des processeurs, des micrologiciels ou des systèmes d’exploitation au stade de l’exécution du programme, p. ex. intégrité de la pile, débordement de tampon ou prévention d'effacement involontaire de données par exécution dans un environnement restreint, p. ex. "boîte à sable" ou machine virtuelle sécurisée
A microelectronic device including a nanosheet transistor that includes a first source/drain (170) and a second source/drain (172), a frontside contact (182) connected to the first source/drain and a backside contact (210) connected to the second source/drain. A plurality of isolation layers is located beneath the nanosheet transistor, and the second source/drain extends through the plurality of isolation layers to connect with the backside contact.
H01L 27/088 - Dispositifs consistant en une pluralité de composants semi-conducteurs ou d'autres composants à l'état solide formés dans ou sur un substrat commun comprenant des éléments de circuit passif intégrés avec au moins une barrière de potentiel ou une barrière de surface le substrat étant un corps semi-conducteur comprenant uniquement des composants semi-conducteurs d'un seul type comprenant uniquement des composants à effet de champ les composants étant des transistors à effet de champ à porte isolée
H01L 29/417 - Electrodes caractérisées par leur forme, leurs dimensions relatives ou leur disposition relative transportant le courant à redresser, à amplifier ou à commuter
H01L 29/66 - Types de dispositifs semi-conducteurs
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 29/08 - Corps semi-conducteurs caractérisés par les formes, les dimensions relatives, ou les dispositions des régions semi-conductrices avec des régions semi-conductrices connectées à une électrode transportant le courant à redresser, amplifier ou commuter, cette électrode faisant partie d'un dispositif à semi-conducteur qui comporte trois électrodes ou plus
An embodiment configures a software robot to operate collaboratively with a plurality of platforms within a work environment. The embodiment decomposes, via the software robot, a request to perform a task received from one of the platforms, into at least one integration-action pair. An integration in this pair represents a configuration to operate on an execution platform within the plurality of platforms where a function is to be executed; an action in the pair represents the function to be performed on the execution platform. Responsive to the determination that the at least one integration-action pair does not exist in a database of integration-action pairs, the embodiment trains the software robot to perform the function on the platform.
A computer-implemented method for live migration of a logical dedicated host and virtual machines (VMs) associated therewith from a first physical server to a second physical server, in accordance with one aspect of the present invention, includes, in response to receiving a request to migrate a logical dedicated host from the first physical server, creating a clone of the logical dedicated host thereby creating a clone dedicated host. The clone dedicated host is provisioned on a second physical server. VMs are migrated from the logical dedicated host to the clone dedicated host. The migration is transparent such that user operations being performed on the VMs continue uninterrupted during the migration. In response to completion of the migrating of the VMs to the clone dedicated host, the logical dedicated host is caused to be de-provisioned from the first physical server.
According to one embodiment, a method, computer system, and computer program product for mitigating a camera failure during volumetric capture is provided. The embodiment may include monitoring respective status of functionality (SoF) array data structures of a set of cameras tasked with capturing volumetric video of a scene. The set of cameras comprises cameras designated as backup cameras and cameras designated for active volumetric capture. The embodiment may include detecting a failed camera of the cameras designated for active volumetric capture based on evaluation of an SoF array data structure of the failed camera. In response to detecting the failed camera, the embodiment may include determining whether a backup camera of the cameras designated as backup cameras is available to replace the failed camera. In response to determining the backup camera is available, the embodiment may include replacing the failed camera with the backup camera.
A device-implemented method, in accordance with one aspect of the present invention, includes receiving a command having an address field of predefined length. A first subset of bits in the address field identify an external key of a particular tenant, and a second subset of the bits in the address field corresponds to one of a plurality of type keys associated with different data types. The external key identified by the first subset of bits is retrieved. The type key corresponding to the second subset of bits is also retrieved. The tenant and type keys are combined to create a combined key for use in encrypting and/or decrypting data associated with the command.
Intelligent wireless energy sharing is provided. An ad hoc wireless mesh network that includes a plurality of energy nodes is formed using a set of machine learning models. The plurality of energy nodes is comprised of the energy node and a set of other energy nodes. A source energy node and a sink energy node in the plurality of energy nodes is identified using the set of machine learning models in response to forming the ad hoc wireless mesh network. Energy is wirelessly transferred from the energy node as the source energy node to the sink energy node via the ad hoc wireless mesh network utilizing a transceiver.
B60L 53/126 - Procédés pour associer un véhicule et une station de charge, p. ex. en établissant une relation directe entre un transmetteur d'énergie sans fil et un récepteur d'énergie sans fil
B60L 55/00 - Dispositions relatives à la fourniture d'énergie emmagasinée dans un véhicule à un réseau électrique, c.-à-d. du véhicule au réseau [V2G]
H04B 5/00 - Systèmes de transmission en champ proche, p. ex. systèmes à transmission capacitive ou inductive
B60L 53/66 - Transfert de données entre les stations de charge et le véhicule
91.
DETECTING AND PREDICTING ELECTRONIC STORAGE DEVICE DATA ANOMALIES
A computer-implemented method, a system and a computer program product for device failure detection are disclosed. In the method, phase-based predictions may be performed on a plurality of storage devices to determine a plurality of sampling scopes and corresponding sampling ratios. The respective sampling scopes may comprise at least one storage device of the plurality of storage devices. A sampling dataset may be obtained by selecting a group of storage devices from the respective sampling scopes with the corresponding sampling ratios. Device failure may be detected for the group of storage devices based on the sampling dataset.
A microelectronic structure including a nanosheet transistor that includes a source/drain. A frontside contact that includes a first section located on the frontside of the source/drain and a via section that extends to the backside of the nanosheet transistor. A shallow isolation layer located around a portion of the via section the first frontside contact. A backside metal line located on a backside surface of the via section and located on a backside surface of the shallow trench isolation layer. A dielectric liner located along a sidewall of the backside metal line and located along a bottom surface of the backside metal line.
H01L 21/768 - Fixation d'interconnexions servant à conduire le courant entre des composants distincts à l'intérieur du dispositif
H01L 23/485 - Dispositions pour conduire le courant électrique vers le ou hors du corps à l'état solide pendant son fonctionnement, p. ex. fils de connexion ou bornes formées de couches conductrices inséparables du corps semi-conducteur sur lequel elles ont été déposées formées de structures en couches comprenant des couches conductrices et isolantes, p. ex. contacts planaires
H01L 23/528 - Configuration de la structure d'interconnexion
H01L 29/775 - Transistors à effet de champ avec un canal à gaz de porteurs de charge à une dimension, p.ex. FET à fil quantique
According to one embodiment, a method, computer system, and computer program product for establishing identity-based hierarchical sessions on a hardware security module (HSM) for binding secure keys to a guest system, is disclosed. The present invention may include establishing a communication channel between the guest system and the HSM, wherein the communication channel is identity-based, end-to-end and encrypted, thereby establishing a session, transferring login information of the guest system through the communication channel to the HSM, maintaining a predefined security level throughout a hierarchy of the sessions, wherein no child session has a higher security level than its parent session, and performing a challenge-response protocol based on a session ownership verification with the guest, such that an HSM generated and secured key is bound to a related session.
H04L 9/32 - Dispositions pour les communications secrètes ou protégéesProtocoles réseaux de sécurité comprenant des moyens pour vérifier l'identité ou l'autorisation d'un utilisateur du système
G06F 9/455 - ÉmulationInterprétationSimulation de logiciel, p. ex. virtualisation ou émulation des moteurs d’exécution d’applications ou de systèmes d’exploitation
94.
ACCELERATE INFERENCE PERFORMANCE ON ARTIFICIAL INTELLIGENCE ACCELERATORS
A method for inference performance in an artificial intelligence model provides reduction of pre-processing overhead. The method includes receiving a plurality of operations associated with the artificial intelligence model. A computational graph for the artificial intelligence model is generated. Each of the operations is categorized into one of three categories including: accelerator designated operations, central processing unit (CPU) designated operations, and undetermined processing designated operations. An estimated processing time is determined for the operations. The operations are inserted into the computational graph. The computational graph is divided into sub-graphs. Edges of the sub-graphs where pre-processing steps will be performed is determined. A conversion is applied to the sub-graphs converting the undetermined processing designated operations, into one of the accelerator designated operations or the CPU designated operations, based on a condition that minimizes a number of the pre-processing steps in the sub-graph.
A method, system and computer program product for improving discernment between qubit states in superconducting quantum computers. Channels are calibrated to train the kernel to contain the correct calibration data ("kernel states"). After calibrating a channel, testing is performed in which quantum operations are performed on qubits at the same time in adjacent channels, including the recently calibrated channel, to determine if the kernel response differs from the expected kernel response, where the expected kernel response is based on the kernel states of the trained kernel of the recently calibrated channel, beyond a threshold value. If such a situation occurs, then the phase of the signal for the recently calibrated channel is shifted and the process of recalibrating the channel (using the phase shifted signal) and testing is repeated until the difference between the kernel response and the expected kernel response is not beyond the threshold value.
G06N 10/40 - Réalisations ou architectures physiques de processeurs ou de composants quantiques pour la manipulation de qubits, p. ex. couplage ou commande de qubit
G06N 10/70 - Correction, détection ou prévention d’erreur quantique, p. ex. codes de surface ou distillation d’état magique
A method for rendering clear visibility through the windscreen of a vehicle. The method includes monitoring, by one or more sensors, visibility of a windscreen, wherein monitoring includes analyzing a level of visibility of the windscreen, generating a visibility score, and responsive to the visibility score falling below a predetermined threshold, converting, dynamically, the windscreen into a display surface. The method further includes analyzing an external sensor feed of a vehicle to identify the visibility of a surrounding area. The method further includes initiating, dynamically, a generative adversarial network (GAN) enabled adaptation of the surrounding area of the vehicle, in real-time, to reconstruct a visual based on the external sensor feed, and rendering, in real-time, the GAN enabled adaptation of the surrounding area of the vehicle on a transparent display layer of the windscreen of the vehicle.
B60K 35/235 - Dispositifs d'affichage "tête haute" [HUD] comportant des moyens de détection de la direction du regard ou de points de repère oculaires du conducteur
B60K 35/40 - Instruments spécialement adaptés à l’amélioration de leur visibilité pour l'utilisateur, p. ex. dispositions antibuée ou antireflet
B60K 35/81 - Dispositions pour la commande des instruments pour la commande des affichages
G06V 20/56 - Contexte ou environnement de l’image à l’extérieur d’un véhicule à partir de capteurs embarqués
Dynamic adjusting of pod resource limits is provided at runtime of a container orchestration platform pod. The process includes deploying a container orchestration platform pod with one or more pod resources in a computing environment, where the pod resources have one or more associated pod resource limits. Further, the process includes monitoring a runtime resource usage of the container orchestration platform pod, and predicting, by a trained machine learning model, upcoming resource usage of the container orchestration platform pod. The predicting uses, at least in part, the monitored runtime resource usage. Further, the process includes dynamically adjusting a pod resource limit of the one or more pod resource limits of the container orchestration platform pod in the computing environment. The dynamically adjusting is based on the monitored runtime resource usage, and the predicted upcoming resource usage.
According to one embodiment, a method, computer system, and computer program product for 3D printing is provided. The present invention may include identifying one or more physical objects to be infused within an object being 3D printed; generating at least one digital model of the one or more identified physical objects; analyzing a digital model of the object being 3D printed; determining one or more identified physical object that can be infused within the object being 3D printed; modifying the digital model of the object being 3D printed to comprise an internal physical object infused within the object being 3D printed; and printing the object being 3D printed over the internal physical object. Additionally, according to one embodiment, a method for manufacturing a three-dimensional product is provided. Additionally, according to one embodiment, a data processing device for 3D printing is provided.
A computer implemented method for merging loops. A number of processor units identifies loops in computer code. The loops are sequences of instructions that are repeated until conditions for the loops are reached. The number of processor units creates a tree comprising nodes that represent the loops and edges that represent relationships between nodes. The number of processor units utilizes the tree to identify a pair of candidate loops from sibling nodes. The number of processor units creates a new loop from the pair of candidate loops with an expanded iteration space based on iteration spaces for the pair of candidate loops in response to the pair of candidate loops being eligible for merging.
Described are techniques for caching a data payload on a peripheral device for delivery to a target device. The techniques include receiving, at a peripheral device via a short-range wireless protocol, a data payload intended for a target device, where the data payload is received from a source device configured to send the data payload to the target device. The techniques further include storing the data payload in a memory of the peripheral device for a time that allows the peripheral device to be placed in network proximity of the target device and transfer the data payload from the peripheral device to the target device. The techniques further include detecting the target device via a short-range wireless network, and sending the data payload to the target device via a short-range wireless protocol used by the target device.
H04L 67/12 - Protocoles spécialement adaptés aux environnements propriétaires ou de mise en réseau pour un usage spécial, p. ex. les réseaux médicaux, les réseaux de capteurs, les réseaux dans les véhicules ou les réseaux de mesure à distance
H04L 67/568 - Stockage temporaire des données à un stade intermédiaire, p. ex. par mise en antémémoire
H04L 69/18 - Gestionnaires multi-protocoles, p. ex. dispositifs uniques capables de gérer plusieurs protocoles
brevets